2 * Copyright (c) 1996, by Steve Passe
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. The name of the developer may NOT be used to endorse or promote products
11 * derived from this software without specific prior written permission.
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * $FreeBSD: src/sys/i386/i386/mp_machdep.c,v 1.115.2.15 2003/03/14 21:22:35 jhb Exp $
26 * $DragonFly: src/sys/platform/pc32/i386/mp_machdep.c,v 1.60 2008/06/07 12:03:52 mneumann Exp $
31 #include <sys/param.h>
32 #include <sys/systm.h>
33 #include <sys/kernel.h>
34 #include <sys/sysctl.h>
35 #include <sys/malloc.h>
36 #include <sys/memrange.h>
37 #include <sys/cons.h> /* cngetc() */
38 #include <sys/machintr.h>
41 #include <vm/vm_param.h>
43 #include <vm/vm_kern.h>
44 #include <vm/vm_extern.h>
46 #include <vm/vm_map.h>
52 #include <machine/smp.h>
53 #include <machine_base/apic/apicreg.h>
54 #include <machine/atomic.h>
55 #include <machine/cpufunc.h>
56 #include <machine_base/apic/mpapic.h>
57 #include <machine/psl.h>
58 #include <machine/segments.h>
59 #include <machine/tss.h>
60 #include <machine/specialreg.h>
61 #include <machine/globaldata.h>
63 #include <machine/md_var.h> /* setidt() */
64 #include <machine_base/icu/icu.h> /* IPIs */
65 #include <machine_base/isa/intr_machdep.h> /* IPIs */
67 #define FIXUP_EXTRA_APIC_INTS 8 /* additional entries we may create */
69 #define WARMBOOT_TARGET 0
70 #define WARMBOOT_OFF (KERNBASE + 0x0467)
71 #define WARMBOOT_SEG (KERNBASE + 0x0469)
73 #define BIOS_BASE (0xf0000)
74 #define BIOS_BASE2 (0xe0000)
75 #define BIOS_SIZE (0x10000)
76 #define BIOS_COUNT (BIOS_SIZE/4)
78 #define CMOS_REG (0x70)
79 #define CMOS_DATA (0x71)
80 #define BIOS_RESET (0x0f)
81 #define BIOS_WARM (0x0a)
83 #define PROCENTRY_FLAG_EN 0x01
84 #define PROCENTRY_FLAG_BP 0x02
85 #define IOAPICENTRY_FLAG_EN 0x01
88 /* MP Floating Pointer Structure */
89 typedef struct MPFPS {
102 /* MP Configuration Table Header */
103 typedef struct MPCTH {
105 u_short base_table_length;
109 u_char product_id[12];
110 void *oem_table_pointer;
111 u_short oem_table_size;
114 u_short extended_table_length;
115 u_char extended_table_checksum;
120 typedef struct PROCENTRY {
125 u_long cpu_signature;
126 u_long feature_flags;
131 typedef struct BUSENTRY {
137 typedef struct IOAPICENTRY {
143 } *io_apic_entry_ptr;
145 typedef struct INTENTRY {
155 /* descriptions of MP basetable entries */
156 typedef struct BASETABLE_ENTRY {
165 vm_size_t mp_cth_mapsz;
168 typedef int (*mptable_iter_func)(void *, const void *, int);
171 * this code MUST be enabled here and in mpboot.s.
172 * it follows the very early stages of AP boot by placing values in CMOS ram.
173 * it NORMALLY will never be needed and thus the primitive method for enabling.
176 #if defined(CHECK_POINTS)
177 #define CHECK_READ(A) (outb(CMOS_REG, (A)), inb(CMOS_DATA))
178 #define CHECK_WRITE(A,D) (outb(CMOS_REG, (A)), outb(CMOS_DATA, (D)))
180 #define CHECK_INIT(D); \
181 CHECK_WRITE(0x34, (D)); \
182 CHECK_WRITE(0x35, (D)); \
183 CHECK_WRITE(0x36, (D)); \
184 CHECK_WRITE(0x37, (D)); \
185 CHECK_WRITE(0x38, (D)); \
186 CHECK_WRITE(0x39, (D));
188 #define CHECK_PRINT(S); \
189 kprintf("%s: %d, %d, %d, %d, %d, %d\n", \
198 #else /* CHECK_POINTS */
200 #define CHECK_INIT(D)
201 #define CHECK_PRINT(S)
203 #endif /* CHECK_POINTS */
206 * Values to send to the POST hardware.
208 #define MP_BOOTADDRESS_POST 0x10
209 #define MP_PROBE_POST 0x11
210 #define MPTABLE_PASS1_POST 0x12
212 #define MP_START_POST 0x13
213 #define MP_ENABLE_POST 0x14
214 #define MPTABLE_PASS2_POST 0x15
216 #define START_ALL_APS_POST 0x16
217 #define INSTALL_AP_TRAMP_POST 0x17
218 #define START_AP_POST 0x18
220 #define MP_ANNOUNCE_POST 0x19
222 /** XXX FIXME: where does this really belong, isa.h/isa.c perhaps? */
223 int current_postcode;
225 /** XXX FIXME: what system files declare these??? */
226 extern struct region_descriptor r_gdt, r_idt;
228 int mp_naps; /* # of Applications processors */
230 static int mp_nbusses; /* # of busses */
231 int mp_napics; /* # of IO APICs */
234 vm_offset_t io_apic_address[NAPICID]; /* NAPICID is more than enough */
235 u_int32_t *io_apic_versions;
239 u_int32_t cpu_apic_versions[MAXCPU];
241 extern int64_t tsc_offsets[];
243 extern u_long ebda_addr;
246 struct apic_intmapinfo int_to_apicintpin[APIC_INTMAPSIZE];
250 * APIC ID logical/physical mapping structures.
251 * We oversize these to simplify boot-time config.
253 int cpu_num_to_apic_id[NAPICID];
255 int io_num_to_apic_id[NAPICID];
257 int apic_id_to_logical[NAPICID];
259 /* AP uses this during bootstrap. Do not staticize. */
263 /* Hotwire a 0->4MB V==P mapping */
264 extern pt_entry_t *KPTphys;
267 * SMP page table page. Setup by locore to point to a page table
268 * page from which we allocate per-cpu privatespace areas io_apics,
272 #define IO_MAPPING_START_INDEX \
273 (SMP_MAXCPU * sizeof(struct privatespace) / PAGE_SIZE)
275 extern pt_entry_t *SMPpt;
276 static int SMPpt_alloc_index = IO_MAPPING_START_INDEX;
278 struct pcb stoppcbs[MAXCPU];
280 static basetable_entry basetable_entry_types[] =
282 {0, 20, "Processor"},
290 * Local data and functions.
293 static u_int boot_address;
294 static u_int base_memory;
295 static int mp_finish;
297 static void mp_enable(u_int boot_addr);
299 static int mptable_iterate_entries(const mpcth_t,
300 mptable_iter_func, void *);
301 static int mptable_probe(void);
302 static int mptable_search(void);
303 static int mptable_check(vm_paddr_t);
304 static int mptable_search_sig(u_int32_t target, int count);
305 static int mptable_hyperthread_fixup(u_int, int);
306 static void mptable_pass1(struct mptable_pos *);
307 static void mptable_pass2(struct mptable_pos *);
308 static void mptable_default(int type);
309 static void mptable_fix(void);
310 static int mptable_map(struct mptable_pos *, vm_paddr_t);
311 static void mptable_unmap(struct mptable_pos *);
312 static void mptable_imcr(struct mptable_pos *);
314 static int mptable_lapic_probe(struct lapic_enumerator *);
315 static void mptable_lapic_enumerate(struct lapic_enumerator *);
316 static void mptable_lapic_default(void);
319 static void setup_apic_irq_mapping(void);
320 static int apic_int_is_bus_type(int intr, int bus_type);
322 static int start_all_aps(u_int boot_addr);
323 static void install_ap_tramp(u_int boot_addr);
324 static int start_ap(struct mdglobaldata *gd, u_int boot_addr);
326 static cpumask_t smp_startup_mask = 1; /* which cpus have been started */
327 cpumask_t smp_active_mask = 1; /* which cpus are ready for IPIs etc? */
328 SYSCTL_INT(_machdep, OID_AUTO, smp_active, CTLFLAG_RD, &smp_active_mask, 0, "");
331 * Calculate usable address in base memory for AP trampoline code.
334 mp_bootaddress(u_int basemem)
336 POSTCODE(MP_BOOTADDRESS_POST);
338 base_memory = basemem;
340 boot_address = base_memory & ~0xfff; /* round down to 4k boundary */
341 if ((base_memory - boot_address) < bootMP_size)
342 boot_address -= 4096; /* not enough, lower by 4k */
353 mpfps_paddr = mptable_search();
354 if (mptable_check(mpfps_paddr))
361 * Look for an Intel MP spec table (ie, SMP capable hardware).
370 * Make sure our SMPpt[] page table is big enough to hold all the
373 KKASSERT(IO_MAPPING_START_INDEX < NPTEPG - 2);
375 POSTCODE(MP_PROBE_POST);
377 /* see if EBDA exists */
378 if (ebda_addr != 0) {
379 /* search first 1K of EBDA */
380 target = (u_int32_t)ebda_addr;
381 if ((x = mptable_search_sig(target, 1024 / 4)) > 0)
384 /* last 1K of base memory, effective 'top of base' passed in */
385 target = (u_int32_t)(base_memory - 0x400);
386 if ((x = mptable_search_sig(target, 1024 / 4)) > 0)
390 /* search the BIOS */
391 target = (u_int32_t)BIOS_BASE;
392 if ((x = mptable_search_sig(target, BIOS_COUNT)) > 0)
395 /* search the extended BIOS */
396 target = (u_int32_t)BIOS_BASE2;
397 if ((x = mptable_search_sig(target, BIOS_COUNT)) > 0)
404 struct mptable_check_cbarg {
410 mptable_check_callback(void *xarg, const void *pos, int type)
412 const struct PROCENTRY *ent;
413 struct mptable_check_cbarg *arg = xarg;
419 if ((ent->cpu_flags & PROCENTRY_FLAG_EN) == 0)
423 if (ent->cpu_flags & PROCENTRY_FLAG_BP) {
424 if (arg->found_bsp) {
425 kprintf("more than one BSP in base MP table\n");
434 mptable_check(vm_paddr_t mpfps_paddr)
436 struct mptable_pos mpt;
437 struct mptable_check_cbarg arg;
441 if (mpfps_paddr == 0)
444 error = mptable_map(&mpt, mpfps_paddr);
448 if (mpt.mp_fps->mpfb1 != 0)
456 if (cth->apic_address == 0)
459 bzero(&arg, sizeof(arg));
460 error = mptable_iterate_entries(cth, mptable_check_callback, &arg);
462 if (arg.cpu_count == 0) {
463 kprintf("MP table contains no processor entries\n");
465 } else if (!arg.found_bsp) {
466 kprintf("MP table does not contains BSP entry\n");
476 mptable_iterate_entries(const mpcth_t cth, mptable_iter_func func, void *arg)
478 int count, total_size;
479 const void *position;
481 KKASSERT(cth->base_table_length >= sizeof(struct MPCTH));
482 total_size = cth->base_table_length - sizeof(struct MPCTH);
483 position = (const uint8_t *)cth + sizeof(struct MPCTH);
484 count = cth->entry_count;
489 KKASSERT(total_size >= 0);
490 if (total_size == 0) {
491 kprintf("invalid base MP table, "
492 "entry count and length mismatch\n");
496 type = *(const uint8_t *)position;
498 case 0: /* processor_entry */
499 case 1: /* bus_entry */
500 case 2: /* io_apic_entry */
501 case 3: /* int_entry */
502 case 4: /* int_entry */
505 kprintf("unknown base MP table entry type %d\n", type);
509 if (total_size < basetable_entry_types[type].length) {
510 kprintf("invalid base MP table length, "
511 "does not contain all entries\n");
514 total_size -= basetable_entry_types[type].length;
516 error = func(arg, position, type);
520 position = (const uint8_t *)position +
521 basetable_entry_types[type].length;
528 * Startup the SMP processors.
533 POSTCODE(MP_START_POST);
534 mp_enable(boot_address);
539 * Print various information about the SMP system hardware and setup.
546 POSTCODE(MP_ANNOUNCE_POST);
548 kprintf("DragonFly/MP: Multiprocessor motherboard\n");
549 kprintf(" cpu0 (BSP): apic id: %2d", CPU_TO_ID(0));
550 kprintf(", version: 0x%08x\n", cpu_apic_versions[0]);
551 for (x = 1; x <= mp_naps; ++x) {
552 kprintf(" cpu%d (AP): apic id: %2d", x, CPU_TO_ID(x));
553 kprintf(", version: 0x%08x\n", cpu_apic_versions[x]);
557 for (x = 0; x < mp_napics; ++x) {
558 kprintf(" io%d (APIC): apic id: %2d", x, IO_TO_ID(x));
559 kprintf(", version: 0x%08x", io_apic_versions[x]);
560 kprintf(", at 0x%08lx\n", io_apic_address[x]);
563 kprintf(" Warning: APIC I/O disabled\n");
568 * AP cpu's call this to sync up protected mode.
570 * WARNING! We must ensure that the cpu is sufficiently initialized to
571 * be able to use to the FP for our optimized bzero/bcopy code before
572 * we enter more mainstream C code.
574 * WARNING! %fs is not set up on entry. This routine sets up %fs.
580 int x, myid = bootAP;
582 struct mdglobaldata *md;
583 struct privatespace *ps;
585 ps = &CPU_prvspace[myid];
587 gdt_segs[GPRIV_SEL].ssd_base = (int)ps;
588 gdt_segs[GPROC0_SEL].ssd_base =
589 (int) &ps->mdglobaldata.gd_common_tss;
590 ps->mdglobaldata.mi.gd_prvspace = ps;
592 for (x = 0; x < NGDT; x++) {
593 ssdtosd(&gdt_segs[x], &gdt[myid * NGDT + x].sd);
596 r_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1;
597 r_gdt.rd_base = (int) &gdt[myid * NGDT];
598 lgdt(&r_gdt); /* does magic intra-segment return */
603 mdcpu->gd_currentldt = _default_ldt;
605 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL);
606 gdt[myid * NGDT + GPROC0_SEL].sd.sd_type = SDT_SYS386TSS;
608 md = mdcpu; /* loaded through %fs:0 (mdglobaldata.mi.gd_prvspace)*/
610 md->gd_common_tss.tss_esp0 = 0; /* not used until after switch */
611 md->gd_common_tss.tss_ss0 = GSEL(GDATA_SEL, SEL_KPL);
612 md->gd_common_tss.tss_ioopt = (sizeof md->gd_common_tss) << 16;
613 md->gd_tss_gdt = &gdt[myid * NGDT + GPROC0_SEL].sd;
614 md->gd_common_tssd = *md->gd_tss_gdt;
618 * Set to a known state:
619 * Set by mpboot.s: CR0_PG, CR0_PE
620 * Set by cpu_setregs: CR0_NE, CR0_MP, CR0_TS, CR0_WP, CR0_AM
623 cr0 &= ~(CR0_CD | CR0_NW | CR0_EM);
625 pmap_set_opt(); /* PSE/4MB pages, etc */
627 /* set up CPU registers and state */
630 /* set up FPU state on the AP */
631 npxinit(__INITIAL_NPXCW__);
633 /* set up SSE registers */
637 /*******************************************************************
638 * local functions and data
642 * start the SMP system
645 mp_enable(u_int boot_addr)
651 vm_paddr_t mpfps_paddr;
652 struct mptable_pos mpt;
654 POSTCODE(MP_ENABLE_POST);
658 mpfps_paddr = mptable_probe();
660 mptable_map(&mpt, mpfps_paddr);
667 panic("no MP table, disable APIC_IO!\n");
669 mptable_map(&mpt, mpfps_paddr);
672 * Examine the MP table for needed info
679 /* Post scan cleanup */
682 setup_apic_irq_mapping();
684 /* fill the LOGICAL io_apic_versions table */
685 for (apic = 0; apic < mp_napics; ++apic) {
686 ux = io_apic_read(apic, IOAPIC_VER);
687 io_apic_versions[apic] = ux;
688 io_apic_set_id(apic, IO_TO_ID(apic));
691 /* program each IO APIC in the system */
692 for (apic = 0; apic < mp_napics; ++apic)
693 if (io_apic_setup(apic) < 0)
694 panic("IO APIC setup failure");
699 * These are required for SMP operation
702 /* install a 'Spurious INTerrupt' vector */
703 setidt(XSPURIOUSINT_OFFSET, Xspuriousint,
704 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
706 /* install an inter-CPU IPI for TLB invalidation */
707 setidt(XINVLTLB_OFFSET, Xinvltlb,
708 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
710 /* install an inter-CPU IPI for IPIQ messaging */
711 setidt(XIPIQ_OFFSET, Xipiq,
712 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
714 /* install a timer vector */
715 setidt(XTIMER_OFFSET, Xtimer,
716 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
718 /* install an inter-CPU IPI for CPU stop/restart */
719 setidt(XCPUSTOP_OFFSET, Xcpustop,
720 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
722 /* start each Application Processor */
723 start_all_aps(boot_addr);
728 * look for the MP spec signature
731 /* string defined by the Intel MP Spec as identifying the MP table */
732 #define MP_SIG 0x5f504d5f /* _MP_ */
733 #define NEXT(X) ((X) += 4)
735 mptable_search_sig(u_int32_t target, int count)
741 KKASSERT(target != 0);
743 map_size = count * sizeof(u_int32_t);
744 addr = pmap_mapdev((vm_paddr_t)target, map_size);
747 for (x = 0; x < count; NEXT(x)) {
748 if (addr[x] == MP_SIG) {
749 /* make array index a byte index */
750 ret = target + (x * sizeof(u_int32_t));
755 pmap_unmapdev((vm_offset_t)addr, map_size);
760 typedef struct BUSDATA {
762 enum busTypes bus_type;
765 typedef struct INTDATA {
775 typedef struct BUSTYPENAME {
780 static bus_type_name bus_type_table[] =
786 {UNKNOWN_BUSTYPE, "---"},
789 {UNKNOWN_BUSTYPE, "---"},
790 {UNKNOWN_BUSTYPE, "---"},
791 {UNKNOWN_BUSTYPE, "---"},
792 {UNKNOWN_BUSTYPE, "---"},
793 {UNKNOWN_BUSTYPE, "---"},
795 {UNKNOWN_BUSTYPE, "---"},
796 {UNKNOWN_BUSTYPE, "---"},
797 {UNKNOWN_BUSTYPE, "---"},
798 {UNKNOWN_BUSTYPE, "---"},
800 {UNKNOWN_BUSTYPE, "---"}
802 /* from MP spec v1.4, table 5-1 */
803 static int default_data[7][5] =
805 /* nbus, id0, type0, id1, type1 */
806 {1, 0, ISA, 255, 255},
807 {1, 0, EISA, 255, 255},
808 {1, 0, EISA, 255, 255},
809 {1, 0, MCA, 255, 255},
811 {2, 0, EISA, 1, PCI},
819 static bus_datum *bus_data;
821 /* the IO INT data, one entry per possible APIC INTerrupt */
822 static io_int *io_apic_ints;
827 static int processor_entry (const struct PROCENTRY *entry, int cpu);
829 static int bus_entry (const struct BUSENTRY *entry, int bus);
830 static int io_apic_entry (const struct IOAPICENTRY *entry, int apic);
831 static int int_entry (const struct INTENTRY *entry, int intr);
833 static int lookup_bus_type (char *name);
838 mptable_ioapic_pass1_callback(void *xarg, const void *pos, int type)
840 const struct IOAPICENTRY *ioapic_ent;
843 case 1: /* bus_entry */
847 case 2: /* io_apic_entry */
849 if (ioapic_ent->apic_flags & IOAPICENTRY_FLAG_EN) {
850 io_apic_address[mp_napics++] =
851 (vm_offset_t)ioapic_ent->apic_address;
855 case 3: /* int_entry */
865 * 1st pass on motherboard's Intel MP specification table.
874 mptable_pass1(struct mptable_pos *mpt)
880 POSTCODE(MPTABLE_PASS1_POST);
883 KKASSERT(fps != NULL);
885 /* clear various tables */
886 for (x = 0; x < NAPICID; ++x)
887 io_apic_address[x] = ~0; /* IO APIC address table */
893 /* check for use of 'default' configuration */
894 if (fps->mpfb1 != 0) {
895 io_apic_address[0] = DEFAULT_IO_APIC_BASE;
896 mp_nbusses = default_data[fps->mpfb1 - 1][0];
902 error = mptable_iterate_entries(mpt->mp_cth,
903 mptable_ioapic_pass1_callback, NULL);
905 panic("mptable_iterate_entries(ioapic_pass1) failed\n");
912 struct mptable_ioapic2_cbarg {
919 mptable_ioapic_pass2_callback(void *xarg, const void *pos, int type)
921 struct mptable_ioapic2_cbarg *arg = xarg;
925 if (bus_entry(pos, arg->bus))
930 if (io_apic_entry(pos, arg->apic))
935 if (int_entry(pos, arg->intr))
945 * 2nd pass on motherboard's Intel MP specification table.
948 * ID_TO_IO(N), phy APIC ID to log CPU/IO table
949 * IO_TO_ID(N), logical IO to APIC ID table
954 mptable_pass2(struct mptable_pos *mpt)
957 struct mptable_ioapic2_cbarg arg;
961 POSTCODE(MPTABLE_PASS2_POST);
964 KKASSERT(fps != NULL);
966 MALLOC(io_apic_versions, u_int32_t *, sizeof(u_int32_t) * mp_napics,
968 MALLOC(ioapic, volatile ioapic_t **, sizeof(ioapic_t *) * mp_napics,
969 M_DEVBUF, M_WAITOK | M_ZERO);
970 MALLOC(io_apic_ints, io_int *, sizeof(io_int) * (nintrs + FIXUP_EXTRA_APIC_INTS),
972 MALLOC(bus_data, bus_datum *, sizeof(bus_datum) * mp_nbusses,
975 for (x = 0; x < mp_napics; x++)
976 ioapic[x] = permanent_io_mapping(io_apic_address[x]);
978 /* clear various tables */
979 for (x = 0; x < NAPICID; ++x) {
980 ID_TO_IO(x) = -1; /* phy APIC ID to log CPU/IO table */
981 IO_TO_ID(x) = -1; /* logical IO to APIC ID table */
984 /* clear bus data table */
985 for (x = 0; x < mp_nbusses; ++x)
986 bus_data[x].bus_id = 0xff;
988 /* clear IO APIC INT table */
989 for (x = 0; x < (nintrs + 1); ++x) {
990 io_apic_ints[x].int_type = 0xff;
991 io_apic_ints[x].int_vector = 0xff;
994 /* check for use of 'default' configuration */
995 if (fps->mpfb1 != 0) {
996 mptable_default(fps->mpfb1);
1000 bzero(&arg, sizeof(arg));
1001 error = mptable_iterate_entries(mpt->mp_cth,
1002 mptable_ioapic_pass2_callback, &arg);
1004 panic("mptable_iterate_entries(ioapic_pass2) failed\n");
1009 * Check if we should perform a hyperthreading "fix-up" to
1010 * enumerate any logical CPU's that aren't already listed
1013 * XXX: We assume that all of the physical CPUs in the
1014 * system have the same number of logical CPUs.
1016 * XXX: We assume that APIC ID's are allocated such that
1017 * the APIC ID's for a physical processor are aligned
1018 * with the number of logical CPU's in the processor.
1021 mptable_hyperthread_fixup(u_int id_mask, int cpu_count)
1023 int i, id, lcpus_max, logical_cpus;
1025 if ((cpu_feature & CPUID_HTT) == 0)
1028 lcpus_max = (cpu_procinfo & CPUID_HTT_CORES) >> 16;
1032 if (strcmp(cpu_vendor, "GenuineIntel") == 0) {
1034 * INSTRUCTION SET REFERENCE, A-M (#253666)
1035 * Page 3-181, Table 3-20
1036 * "The nearest power-of-2 integer that is not smaller
1037 * than EBX[23:16] is the number of unique initial APIC
1038 * IDs reserved for addressing different logical
1039 * processors in a physical package."
1041 for (i = 0; ; ++i) {
1042 if ((1 << i) >= lcpus_max) {
1049 KKASSERT(cpu_count != 0);
1050 if (cpu_count == lcpus_max) {
1051 /* We have nothing to fix */
1053 } else if (cpu_count == 1) {
1054 /* XXX this may be incorrect */
1055 logical_cpus = lcpus_max;
1057 int cur, prev, dist;
1060 * Calculate the distances between two nearest
1061 * APIC IDs. If all such distances are same,
1062 * then it is the number of missing cpus that
1063 * we are going to fill later.
1065 dist = cur = prev = -1;
1066 for (id = 0; id < MAXCPU; ++id) {
1067 if ((id_mask & 1 << id) == 0)
1072 int new_dist = cur - prev;
1078 * Make sure that all distances
1079 * between two nearest APIC IDs
1082 if (dist != new_dist)
1090 /* Must be power of 2 */
1091 if (dist & (dist - 1))
1094 /* Can't exceed CPU package capacity */
1095 if (dist > lcpus_max)
1096 logical_cpus = lcpus_max;
1098 logical_cpus = dist;
1102 * For each APIC ID of a CPU that is set in the mask,
1103 * scan the other candidate APIC ID's for this
1104 * physical processor. If any of those ID's are
1105 * already in the table, then kill the fixup.
1107 for (id = 0; id < MAXCPU; id++) {
1108 if ((id_mask & 1 << id) == 0)
1110 /* First, make sure we are on a logical_cpus boundary. */
1111 if (id % logical_cpus != 0)
1113 for (i = id + 1; i < id + logical_cpus; i++)
1114 if ((id_mask & 1 << i) != 0)
1117 return logical_cpus;
1121 mptable_map(struct mptable_pos *mpt, vm_paddr_t mpfps_paddr)
1125 vm_size_t cth_mapsz = 0;
1127 bzero(mpt, sizeof(*mpt));
1129 fps = pmap_mapdev(mpfps_paddr, sizeof(*fps));
1130 if (fps->pap != 0) {
1132 * Map configuration table header to get
1133 * the base table size
1135 cth = pmap_mapdev(fps->pap, sizeof(*cth));
1136 cth_mapsz = cth->base_table_length;
1137 pmap_unmapdev((vm_offset_t)cth, sizeof(*cth));
1139 if (cth_mapsz < sizeof(*cth)) {
1140 kprintf("invalid base MP table length %d\n",
1142 pmap_unmapdev((vm_offset_t)fps, sizeof(*fps));
1147 * Map the base table
1149 cth = pmap_mapdev(fps->pap, cth_mapsz);
1154 mpt->mp_cth_mapsz = cth_mapsz;
1160 mptable_unmap(struct mptable_pos *mpt)
1162 if (mpt->mp_cth != NULL) {
1163 pmap_unmapdev((vm_offset_t)mpt->mp_cth, mpt->mp_cth_mapsz);
1165 mpt->mp_cth_mapsz = 0;
1167 if (mpt->mp_fps != NULL) {
1168 pmap_unmapdev((vm_offset_t)mpt->mp_fps, sizeof(*mpt->mp_fps));
1176 assign_apic_irq(int apic, int intpin, int irq)
1180 if (int_to_apicintpin[irq].ioapic != -1)
1181 panic("assign_apic_irq: inconsistent table");
1183 int_to_apicintpin[irq].ioapic = apic;
1184 int_to_apicintpin[irq].int_pin = intpin;
1185 int_to_apicintpin[irq].apic_address = ioapic[apic];
1186 int_to_apicintpin[irq].redirindex = IOAPIC_REDTBL + 2 * intpin;
1188 for (x = 0; x < nintrs; x++) {
1189 if ((io_apic_ints[x].int_type == 0 ||
1190 io_apic_ints[x].int_type == 3) &&
1191 io_apic_ints[x].int_vector == 0xff &&
1192 io_apic_ints[x].dst_apic_id == IO_TO_ID(apic) &&
1193 io_apic_ints[x].dst_apic_int == intpin)
1194 io_apic_ints[x].int_vector = irq;
1199 revoke_apic_irq(int irq)
1205 if (int_to_apicintpin[irq].ioapic == -1)
1206 panic("revoke_apic_irq: inconsistent table");
1208 oldapic = int_to_apicintpin[irq].ioapic;
1209 oldintpin = int_to_apicintpin[irq].int_pin;
1211 int_to_apicintpin[irq].ioapic = -1;
1212 int_to_apicintpin[irq].int_pin = 0;
1213 int_to_apicintpin[irq].apic_address = NULL;
1214 int_to_apicintpin[irq].redirindex = 0;
1216 for (x = 0; x < nintrs; x++) {
1217 if ((io_apic_ints[x].int_type == 0 ||
1218 io_apic_ints[x].int_type == 3) &&
1219 io_apic_ints[x].int_vector != 0xff &&
1220 io_apic_ints[x].dst_apic_id == IO_TO_ID(oldapic) &&
1221 io_apic_ints[x].dst_apic_int == oldintpin)
1222 io_apic_ints[x].int_vector = 0xff;
1230 allocate_apic_irq(int intr)
1236 if (io_apic_ints[intr].int_vector != 0xff)
1237 return; /* Interrupt handler already assigned */
1239 if (io_apic_ints[intr].int_type != 0 &&
1240 (io_apic_ints[intr].int_type != 3 ||
1241 (io_apic_ints[intr].dst_apic_id == IO_TO_ID(0) &&
1242 io_apic_ints[intr].dst_apic_int == 0)))
1243 return; /* Not INT or ExtInt on != (0, 0) */
1246 while (irq < APIC_INTMAPSIZE &&
1247 int_to_apicintpin[irq].ioapic != -1)
1250 if (irq >= APIC_INTMAPSIZE)
1251 return; /* No free interrupt handlers */
1253 apic = ID_TO_IO(io_apic_ints[intr].dst_apic_id);
1254 intpin = io_apic_ints[intr].dst_apic_int;
1256 assign_apic_irq(apic, intpin, irq);
1257 io_apic_setup_intpin(apic, intpin);
1262 swap_apic_id(int apic, int oldid, int newid)
1269 return; /* Nothing to do */
1271 kprintf("Changing APIC ID for IO APIC #%d from %d to %d in MP table\n",
1272 apic, oldid, newid);
1274 /* Swap physical APIC IDs in interrupt entries */
1275 for (x = 0; x < nintrs; x++) {
1276 if (io_apic_ints[x].dst_apic_id == oldid)
1277 io_apic_ints[x].dst_apic_id = newid;
1278 else if (io_apic_ints[x].dst_apic_id == newid)
1279 io_apic_ints[x].dst_apic_id = oldid;
1282 /* Swap physical APIC IDs in IO_TO_ID mappings */
1283 for (oapic = 0; oapic < mp_napics; oapic++)
1284 if (IO_TO_ID(oapic) == newid)
1287 if (oapic < mp_napics) {
1288 kprintf("Changing APIC ID for IO APIC #%d from "
1289 "%d to %d in MP table\n",
1290 oapic, newid, oldid);
1291 IO_TO_ID(oapic) = oldid;
1293 IO_TO_ID(apic) = newid;
1298 fix_id_to_io_mapping(void)
1302 for (x = 0; x < NAPICID; x++)
1305 for (x = 0; x <= mp_naps; x++)
1306 if (CPU_TO_ID(x) < NAPICID)
1307 ID_TO_IO(CPU_TO_ID(x)) = x;
1309 for (x = 0; x < mp_napics; x++)
1310 if (IO_TO_ID(x) < NAPICID)
1311 ID_TO_IO(IO_TO_ID(x)) = x;
1316 first_free_apic_id(void)
1320 for (freeid = 0; freeid < NAPICID; freeid++) {
1321 for (x = 0; x <= mp_naps; x++)
1322 if (CPU_TO_ID(x) == freeid)
1326 for (x = 0; x < mp_napics; x++)
1327 if (IO_TO_ID(x) == freeid)
1338 io_apic_id_acceptable(int apic, int id)
1340 int cpu; /* Logical CPU number */
1341 int oapic; /* Logical IO APIC number for other IO APIC */
1344 return 0; /* Out of range */
1346 for (cpu = 0; cpu <= mp_naps; cpu++)
1347 if (CPU_TO_ID(cpu) == id)
1348 return 0; /* Conflict with CPU */
1350 for (oapic = 0; oapic < mp_napics && oapic < apic; oapic++)
1351 if (IO_TO_ID(oapic) == id)
1352 return 0; /* Conflict with other APIC */
1354 return 1; /* ID is acceptable for IO APIC */
1359 io_apic_find_int_entry(int apic, int pin)
1363 /* search each of the possible INTerrupt sources */
1364 for (x = 0; x < nintrs; ++x) {
1365 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1366 (pin == io_apic_ints[x].dst_apic_int))
1367 return (&io_apic_ints[x]);
1375 * parse an Intel MP specification table
1383 int apic; /* IO APIC unit number */
1384 int freeid; /* Free physical APIC ID */
1385 int physid; /* Current physical IO APIC ID */
1387 int bus_0 = 0; /* Stop GCC warning */
1388 int bus_pci = 0; /* Stop GCC warning */
1392 * Fix mis-numbering of the PCI bus and its INT entries if the BIOS
1393 * did it wrong. The MP spec says that when more than 1 PCI bus
1394 * exists the BIOS must begin with bus entries for the PCI bus and use
1395 * actual PCI bus numbering. This implies that when only 1 PCI bus
1396 * exists the BIOS can choose to ignore this ordering, and indeed many
1397 * MP motherboards do ignore it. This causes a problem when the PCI
1398 * sub-system makes requests of the MP sub-system based on PCI bus
1399 * numbers. So here we look for the situation and renumber the
1400 * busses and associated INTs in an effort to "make it right".
1403 /* find bus 0, PCI bus, count the number of PCI busses */
1404 for (num_pci_bus = 0, x = 0; x < mp_nbusses; ++x) {
1405 if (bus_data[x].bus_id == 0) {
1408 if (bus_data[x].bus_type == PCI) {
1414 * bus_0 == slot of bus with ID of 0
1415 * bus_pci == slot of last PCI bus encountered
1418 /* check the 1 PCI bus case for sanity */
1419 /* if it is number 0 all is well */
1420 if (num_pci_bus == 1 &&
1421 bus_data[bus_pci].bus_id != 0) {
1423 /* mis-numbered, swap with whichever bus uses slot 0 */
1425 /* swap the bus entry types */
1426 bus_data[bus_pci].bus_type = bus_data[bus_0].bus_type;
1427 bus_data[bus_0].bus_type = PCI;
1429 /* swap each relavant INTerrupt entry */
1430 id = bus_data[bus_pci].bus_id;
1431 for (x = 0; x < nintrs; ++x) {
1432 if (io_apic_ints[x].src_bus_id == id) {
1433 io_apic_ints[x].src_bus_id = 0;
1435 else if (io_apic_ints[x].src_bus_id == 0) {
1436 io_apic_ints[x].src_bus_id = id;
1441 /* Assign IO APIC IDs.
1443 * First try the existing ID. If a conflict is detected, try
1444 * the ID in the MP table. If a conflict is still detected, find
1447 * We cannot use the ID_TO_IO table before all conflicts has been
1448 * resolved and the table has been corrected.
1450 for (apic = 0; apic < mp_napics; ++apic) { /* For all IO APICs */
1452 /* First try to use the value set by the BIOS */
1453 physid = io_apic_get_id(apic);
1454 if (io_apic_id_acceptable(apic, physid)) {
1455 if (IO_TO_ID(apic) != physid)
1456 swap_apic_id(apic, IO_TO_ID(apic), physid);
1460 /* Then check if the value in the MP table is acceptable */
1461 if (io_apic_id_acceptable(apic, IO_TO_ID(apic)))
1464 /* Last resort, find a free APIC ID and use it */
1465 freeid = first_free_apic_id();
1466 if (freeid >= NAPICID)
1467 panic("No free physical APIC IDs found");
1469 if (io_apic_id_acceptable(apic, freeid)) {
1470 swap_apic_id(apic, IO_TO_ID(apic), freeid);
1473 panic("Free physical APIC ID not usable");
1475 fix_id_to_io_mapping();
1477 /* detect and fix broken Compaq MP table */
1478 if (apic_int_type(0, 0) == -1) {
1479 kprintf("APIC_IO: MP table broken: 8259->APIC entry missing!\n");
1480 io_apic_ints[nintrs].int_type = 3; /* ExtInt */
1481 io_apic_ints[nintrs].int_vector = 0xff; /* Unassigned */
1482 /* XXX fixme, set src bus id etc, but it doesn't seem to hurt */
1483 io_apic_ints[nintrs].dst_apic_id = IO_TO_ID(0);
1484 io_apic_ints[nintrs].dst_apic_int = 0; /* Pin 0 */
1486 } else if (apic_int_type(0, 0) == 0) {
1487 kprintf("APIC_IO: MP table broken: ExtINT entry corrupt!\n");
1488 for (x = 0; x < nintrs; ++x)
1489 if ((0 == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1490 (0 == io_apic_ints[x].dst_apic_int)) {
1491 io_apic_ints[x].int_type = 3;
1492 io_apic_ints[x].int_vector = 0xff;
1498 * Fix missing IRQ 15 when IRQ 14 is an ISA interrupt. IDE
1499 * controllers universally come in pairs. If IRQ 14 is specified
1500 * as an ISA interrupt, then IRQ 15 had better be too.
1502 * [ Shuttle XPC / AMD Athlon X2 ]
1503 * The MPTable is missing an entry for IRQ 15. Note that the
1504 * ACPI table has an entry for both 14 and 15.
1506 if (apic_int_type(0, 14) == 0 && apic_int_type(0, 15) == -1) {
1507 kprintf("APIC_IO: MP table broken: IRQ 15 not ISA when IRQ 14 is!\n");
1508 io14 = io_apic_find_int_entry(0, 14);
1509 io_apic_ints[nintrs] = *io14;
1510 io_apic_ints[nintrs].src_bus_irq = 15;
1511 io_apic_ints[nintrs].dst_apic_int = 15;
1519 /* Assign low level interrupt handlers */
1521 setup_apic_irq_mapping(void)
1527 for (x = 0; x < APIC_INTMAPSIZE; x++) {
1528 int_to_apicintpin[x].ioapic = -1;
1529 int_to_apicintpin[x].int_pin = 0;
1530 int_to_apicintpin[x].apic_address = NULL;
1531 int_to_apicintpin[x].redirindex = 0;
1533 /* Default to masked */
1534 int_to_apicintpin[x].flags = IOAPIC_IM_FLAG_MASKED;
1537 /* First assign ISA/EISA interrupts */
1538 for (x = 0; x < nintrs; x++) {
1539 int_vector = io_apic_ints[x].src_bus_irq;
1540 if (int_vector < APIC_INTMAPSIZE &&
1541 io_apic_ints[x].int_vector == 0xff &&
1542 int_to_apicintpin[int_vector].ioapic == -1 &&
1543 (apic_int_is_bus_type(x, ISA) ||
1544 apic_int_is_bus_type(x, EISA)) &&
1545 io_apic_ints[x].int_type == 0) {
1546 assign_apic_irq(ID_TO_IO(io_apic_ints[x].dst_apic_id),
1547 io_apic_ints[x].dst_apic_int,
1552 /* Assign ExtInt entry if no ISA/EISA interrupt 0 entry */
1553 for (x = 0; x < nintrs; x++) {
1554 if (io_apic_ints[x].dst_apic_int == 0 &&
1555 io_apic_ints[x].dst_apic_id == IO_TO_ID(0) &&
1556 io_apic_ints[x].int_vector == 0xff &&
1557 int_to_apicintpin[0].ioapic == -1 &&
1558 io_apic_ints[x].int_type == 3) {
1559 assign_apic_irq(0, 0, 0);
1563 /* PCI interrupt assignment is deferred */
1569 mp_set_cpuids(int cpu_id, int apic_id)
1571 CPU_TO_ID(cpu_id) = apic_id;
1572 ID_TO_CPU(apic_id) = cpu_id;
1576 processor_entry(const struct PROCENTRY *entry, int cpu)
1580 /* check for usability */
1581 if (!(entry->cpu_flags & PROCENTRY_FLAG_EN))
1584 /* check for BSP flag */
1585 if (entry->cpu_flags & PROCENTRY_FLAG_BP) {
1586 mp_set_cpuids(0, entry->apic_id);
1587 return 0; /* its already been counted */
1590 /* add another AP to list, if less than max number of CPUs */
1591 else if (cpu < MAXCPU) {
1592 mp_set_cpuids(cpu, entry->apic_id);
1602 bus_entry(const struct BUSENTRY *entry, int bus)
1607 /* encode the name into an index */
1608 for (x = 0; x < 6; ++x) {
1609 if ((c = entry->bus_type[x]) == ' ')
1615 if ((x = lookup_bus_type(name)) == UNKNOWN_BUSTYPE)
1616 panic("unknown bus type: '%s'", name);
1618 bus_data[bus].bus_id = entry->bus_id;
1619 bus_data[bus].bus_type = x;
1625 io_apic_entry(const struct IOAPICENTRY *entry, int apic)
1627 if (!(entry->apic_flags & IOAPICENTRY_FLAG_EN))
1630 IO_TO_ID(apic) = entry->apic_id;
1631 ID_TO_IO(entry->apic_id) = apic;
1639 lookup_bus_type(char *name)
1643 for (x = 0; x < MAX_BUSTYPE; ++x)
1644 if (strcmp(bus_type_table[x].name, name) == 0)
1645 return bus_type_table[x].type;
1647 return UNKNOWN_BUSTYPE;
1653 int_entry(const struct INTENTRY *entry, int intr)
1657 io_apic_ints[intr].int_type = entry->int_type;
1658 io_apic_ints[intr].int_flags = entry->int_flags;
1659 io_apic_ints[intr].src_bus_id = entry->src_bus_id;
1660 io_apic_ints[intr].src_bus_irq = entry->src_bus_irq;
1661 if (entry->dst_apic_id == 255) {
1662 /* This signal goes to all IO APICS. Select an IO APIC
1663 with sufficient number of interrupt pins */
1664 for (apic = 0; apic < mp_napics; apic++)
1665 if (((io_apic_read(apic, IOAPIC_VER) &
1666 IOART_VER_MAXREDIR) >> MAXREDIRSHIFT) >=
1667 entry->dst_apic_int)
1669 if (apic < mp_napics)
1670 io_apic_ints[intr].dst_apic_id = IO_TO_ID(apic);
1672 io_apic_ints[intr].dst_apic_id = entry->dst_apic_id;
1674 io_apic_ints[intr].dst_apic_id = entry->dst_apic_id;
1675 io_apic_ints[intr].dst_apic_int = entry->dst_apic_int;
1681 apic_int_is_bus_type(int intr, int bus_type)
1685 for (bus = 0; bus < mp_nbusses; ++bus)
1686 if ((bus_data[bus].bus_id == io_apic_ints[intr].src_bus_id)
1687 && ((int) bus_data[bus].bus_type == bus_type))
1694 * Given a traditional ISA INT mask, return an APIC mask.
1697 isa_apic_mask(u_int isa_mask)
1702 #if defined(SKIP_IRQ15_REDIRECT)
1703 if (isa_mask == (1 << 15)) {
1704 kprintf("skipping ISA IRQ15 redirect\n");
1707 #endif /* SKIP_IRQ15_REDIRECT */
1709 isa_irq = ffs(isa_mask); /* find its bit position */
1710 if (isa_irq == 0) /* doesn't exist */
1712 --isa_irq; /* make it zero based */
1714 apic_pin = isa_apic_irq(isa_irq); /* look for APIC connection */
1718 return (1 << apic_pin); /* convert pin# to a mask */
1722 * Determine which APIC pin an ISA/EISA INT is attached to.
1724 #define INTTYPE(I) (io_apic_ints[(I)].int_type)
1725 #define INTPIN(I) (io_apic_ints[(I)].dst_apic_int)
1726 #define INTIRQ(I) (io_apic_ints[(I)].int_vector)
1727 #define INTAPIC(I) (ID_TO_IO(io_apic_ints[(I)].dst_apic_id))
1729 #define SRCBUSIRQ(I) (io_apic_ints[(I)].src_bus_irq)
1731 isa_apic_irq(int isa_irq)
1735 for (intr = 0; intr < nintrs; ++intr) { /* check each record */
1736 if (INTTYPE(intr) == 0) { /* standard INT */
1737 if (SRCBUSIRQ(intr) == isa_irq) {
1738 if (apic_int_is_bus_type(intr, ISA) ||
1739 apic_int_is_bus_type(intr, EISA)) {
1740 if (INTIRQ(intr) == 0xff)
1741 return -1; /* unassigned */
1742 return INTIRQ(intr); /* found */
1747 return -1; /* NOT found */
1752 * Determine which APIC pin a PCI INT is attached to.
1754 #define SRCBUSID(I) (io_apic_ints[(I)].src_bus_id)
1755 #define SRCBUSDEVICE(I) ((io_apic_ints[(I)].src_bus_irq >> 2) & 0x1f)
1756 #define SRCBUSLINE(I) (io_apic_ints[(I)].src_bus_irq & 0x03)
1758 pci_apic_irq(int pciBus, int pciDevice, int pciInt)
1762 --pciInt; /* zero based */
1764 for (intr = 0; intr < nintrs; ++intr) { /* check each record */
1765 if ((INTTYPE(intr) == 0) /* standard INT */
1766 && (SRCBUSID(intr) == pciBus)
1767 && (SRCBUSDEVICE(intr) == pciDevice)
1768 && (SRCBUSLINE(intr) == pciInt)) { /* a candidate IRQ */
1769 if (apic_int_is_bus_type(intr, PCI)) {
1770 if (INTIRQ(intr) == 0xff)
1771 allocate_apic_irq(intr);
1772 if (INTIRQ(intr) == 0xff)
1773 return -1; /* unassigned */
1774 return INTIRQ(intr); /* exact match */
1779 return -1; /* NOT found */
1783 next_apic_irq(int irq)
1790 for (intr = 0; intr < nintrs; intr++) {
1791 if (INTIRQ(intr) != irq || INTTYPE(intr) != 0)
1793 bus = SRCBUSID(intr);
1794 bustype = apic_bus_type(bus);
1795 if (bustype != ISA &&
1801 if (intr >= nintrs) {
1804 for (ointr = intr + 1; ointr < nintrs; ointr++) {
1805 if (INTTYPE(ointr) != 0)
1807 if (bus != SRCBUSID(ointr))
1809 if (bustype == PCI) {
1810 if (SRCBUSDEVICE(intr) != SRCBUSDEVICE(ointr))
1812 if (SRCBUSLINE(intr) != SRCBUSLINE(ointr))
1815 if (bustype == ISA || bustype == EISA) {
1816 if (SRCBUSIRQ(intr) != SRCBUSIRQ(ointr))
1819 if (INTPIN(intr) == INTPIN(ointr))
1823 if (ointr >= nintrs) {
1826 return INTIRQ(ointr);
1841 * Reprogram the MB chipset to NOT redirect an ISA INTerrupt.
1844 * Exactly what this means is unclear at this point. It is a solution
1845 * for motherboards that redirect the MBIRQ0 pin. Generically a motherboard
1846 * could route any of the ISA INTs to upper (>15) IRQ values. But most would
1847 * NOT be redirected via MBIRQ0, thus "undirect()ing" them would NOT be an
1851 undirect_isa_irq(int rirq)
1855 kprintf("Freeing redirected ISA irq %d.\n", rirq);
1856 /** FIXME: tickle the MB redirector chip */
1860 kprintf("Freeing (NOT implemented) redirected ISA irq %d.\n", rirq);
1867 * Reprogram the MB chipset to NOT redirect a PCI INTerrupt
1870 undirect_pci_irq(int rirq)
1874 kprintf("Freeing redirected PCI irq %d.\n", rirq);
1876 /** FIXME: tickle the MB redirector chip */
1880 kprintf("Freeing (NOT implemented) redirected PCI irq %d.\n",
1890 * given a bus ID, return:
1891 * the bus type if found
1895 apic_bus_type(int id)
1899 for (x = 0; x < mp_nbusses; ++x)
1900 if (bus_data[x].bus_id == id)
1901 return bus_data[x].bus_type;
1907 * given a LOGICAL APIC# and pin#, return:
1908 * the associated src bus ID if found
1912 apic_src_bus_id(int apic, int pin)
1916 /* search each of the possible INTerrupt sources */
1917 for (x = 0; x < nintrs; ++x)
1918 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1919 (pin == io_apic_ints[x].dst_apic_int))
1920 return (io_apic_ints[x].src_bus_id);
1922 return -1; /* NOT found */
1926 * given a LOGICAL APIC# and pin#, return:
1927 * the associated src bus IRQ if found
1931 apic_src_bus_irq(int apic, int pin)
1935 for (x = 0; x < nintrs; x++)
1936 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1937 (pin == io_apic_ints[x].dst_apic_int))
1938 return (io_apic_ints[x].src_bus_irq);
1940 return -1; /* NOT found */
1945 * given a LOGICAL APIC# and pin#, return:
1946 * the associated INTerrupt type if found
1950 apic_int_type(int apic, int pin)
1954 /* search each of the possible INTerrupt sources */
1955 for (x = 0; x < nintrs; ++x) {
1956 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1957 (pin == io_apic_ints[x].dst_apic_int))
1958 return (io_apic_ints[x].int_type);
1960 return -1; /* NOT found */
1964 * Return the IRQ associated with an APIC pin
1967 apic_irq(int apic, int pin)
1972 for (x = 0; x < nintrs; ++x) {
1973 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1974 (pin == io_apic_ints[x].dst_apic_int)) {
1975 res = io_apic_ints[x].int_vector;
1978 if (apic != int_to_apicintpin[res].ioapic)
1979 panic("apic_irq: inconsistent table %d/%d", apic, int_to_apicintpin[res].ioapic);
1980 if (pin != int_to_apicintpin[res].int_pin)
1981 panic("apic_irq inconsistent table (2)");
1990 * given a LOGICAL APIC# and pin#, return:
1991 * the associated trigger mode if found
1995 apic_trigger(int apic, int pin)
1999 /* search each of the possible INTerrupt sources */
2000 for (x = 0; x < nintrs; ++x)
2001 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
2002 (pin == io_apic_ints[x].dst_apic_int))
2003 return ((io_apic_ints[x].int_flags >> 2) & 0x03);
2005 return -1; /* NOT found */
2010 * given a LOGICAL APIC# and pin#, return:
2011 * the associated 'active' level if found
2015 apic_polarity(int apic, int pin)
2019 /* search each of the possible INTerrupt sources */
2020 for (x = 0; x < nintrs; ++x)
2021 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
2022 (pin == io_apic_ints[x].dst_apic_int))
2023 return (io_apic_ints[x].int_flags & 0x03);
2025 return -1; /* NOT found */
2031 * set data according to MP defaults
2032 * FIXME: probably not complete yet...
2035 mptable_default(int type)
2037 #if defined(APIC_IO)
2042 kprintf(" MP default config type: %d\n", type);
2045 kprintf(" bus: ISA, APIC: 82489DX\n");
2048 kprintf(" bus: EISA, APIC: 82489DX\n");
2051 kprintf(" bus: EISA, APIC: 82489DX\n");
2054 kprintf(" bus: MCA, APIC: 82489DX\n");
2057 kprintf(" bus: ISA+PCI, APIC: Integrated\n");
2060 kprintf(" bus: EISA+PCI, APIC: Integrated\n");
2063 kprintf(" bus: MCA+PCI, APIC: Integrated\n");
2066 kprintf(" future type\n");
2072 /* one and only IO APIC */
2073 io_apic_id = (io_apic_read(0, IOAPIC_ID) & APIC_ID_MASK) >> 24;
2076 * sanity check, refer to MP spec section 3.6.6, last paragraph
2077 * necessary as some hardware isn't properly setting up the IO APIC
2079 #if defined(REALLY_ANAL_IOAPICID_VALUE)
2080 if (io_apic_id != 2) {
2082 if ((io_apic_id == 0) || (io_apic_id == 1) || (io_apic_id == 15)) {
2083 #endif /* REALLY_ANAL_IOAPICID_VALUE */
2084 io_apic_set_id(0, 2);
2087 IO_TO_ID(0) = io_apic_id;
2088 ID_TO_IO(io_apic_id) = 0;
2090 /* fill out bus entries */
2099 bus_data[0].bus_id = default_data[type - 1][1];
2100 bus_data[0].bus_type = default_data[type - 1][2];
2101 bus_data[1].bus_id = default_data[type - 1][3];
2102 bus_data[1].bus_type = default_data[type - 1][4];
2105 /* case 4: case 7: MCA NOT supported */
2106 default: /* illegal/reserved */
2107 panic("BAD default MP config: %d", type);
2111 /* general cases from MP v1.4, table 5-2 */
2112 for (pin = 0; pin < 16; ++pin) {
2113 io_apic_ints[pin].int_type = 0;
2114 io_apic_ints[pin].int_flags = 0x05; /* edge/active-hi */
2115 io_apic_ints[pin].src_bus_id = 0;
2116 io_apic_ints[pin].src_bus_irq = pin; /* IRQ2 caught below */
2117 io_apic_ints[pin].dst_apic_id = io_apic_id;
2118 io_apic_ints[pin].dst_apic_int = pin; /* 1-to-1 */
2121 /* special cases from MP v1.4, table 5-2 */
2123 io_apic_ints[2].int_type = 0xff; /* N/C */
2124 io_apic_ints[13].int_type = 0xff; /* N/C */
2125 #if !defined(APIC_MIXED_MODE)
2127 panic("sorry, can't support type 2 default yet");
2128 #endif /* APIC_MIXED_MODE */
2131 io_apic_ints[2].src_bus_irq = 0; /* ISA IRQ0 is on APIC INT 2 */
2134 io_apic_ints[0].int_type = 0xff; /* N/C */
2136 io_apic_ints[0].int_type = 3; /* vectored 8259 */
2137 #endif /* APIC_IO */
2141 * Map a physical memory address representing I/O into KVA. The I/O
2142 * block is assumed not to cross a page boundary.
2145 permanent_io_mapping(vm_paddr_t pa)
2151 KKASSERT(pa < 0x100000000LL);
2153 pgeflag = 0; /* not used for SMP yet */
2156 * If the requested physical address has already been incidently
2157 * mapped, just use the existing mapping. Otherwise create a new
2160 for (i = IO_MAPPING_START_INDEX; i < SMPpt_alloc_index; ++i) {
2161 if (((vm_offset_t)SMPpt[i] & PG_FRAME) ==
2162 ((vm_offset_t)pa & PG_FRAME)) {
2166 if (i == SMPpt_alloc_index) {
2167 if (i == NPTEPG - 2) {
2168 panic("permanent_io_mapping: We ran out of space"
2171 SMPpt[i] = (pt_entry_t)(PG_V | PG_RW | PG_N | pgeflag |
2172 ((vm_offset_t)pa & PG_FRAME));
2173 ++SMPpt_alloc_index;
2175 vaddr = (vm_offset_t)CPU_prvspace + (i * PAGE_SIZE) +
2176 ((vm_offset_t)pa & PAGE_MASK);
2177 return ((void *)vaddr);
2181 * start each AP in our list
2184 start_all_aps(u_int boot_addr)
2188 u_char mpbiosreason;
2189 u_long mpbioswarmvec;
2190 struct mdglobaldata *gd;
2191 struct privatespace *ps;
2195 POSTCODE(START_ALL_APS_POST);
2197 /* Initialize BSP's local APIC */
2198 apic_initialize(TRUE);
2200 /* install the AP 1st level boot code */
2201 install_ap_tramp(boot_addr);
2204 /* save the current value of the warm-start vector */
2205 mpbioswarmvec = *((u_long *) WARMBOOT_OFF);
2206 outb(CMOS_REG, BIOS_RESET);
2207 mpbiosreason = inb(CMOS_DATA);
2209 /* set up temporary P==V mapping for AP boot */
2210 /* XXX this is a hack, we should boot the AP on its own stack/PTD */
2211 kptbase = (uintptr_t)(void *)KPTphys;
2212 for (x = 0; x < NKPT; x++) {
2213 PTD[x] = (pd_entry_t)(PG_V | PG_RW |
2214 ((kptbase + x * PAGE_SIZE) & PG_FRAME));
2219 for (x = 1; x <= mp_naps; ++x) {
2221 /* This is a bit verbose, it will go away soon. */
2223 /* first page of AP's private space */
2224 pg = x * i386_btop(sizeof(struct privatespace));
2226 /* allocate new private data page(s) */
2227 gd = (struct mdglobaldata *)kmem_alloc(&kernel_map,
2228 MDGLOBALDATA_BASEALLOC_SIZE);
2229 /* wire it into the private page table page */
2230 for (i = 0; i < MDGLOBALDATA_BASEALLOC_SIZE; i += PAGE_SIZE) {
2231 SMPpt[pg + i / PAGE_SIZE] = (pt_entry_t)
2232 (PG_V | PG_RW | vtophys_pte((char *)gd + i));
2234 pg += MDGLOBALDATA_BASEALLOC_PAGES;
2236 SMPpt[pg + 0] = 0; /* *gd_CMAP1 */
2237 SMPpt[pg + 1] = 0; /* *gd_CMAP2 */
2238 SMPpt[pg + 2] = 0; /* *gd_CMAP3 */
2239 SMPpt[pg + 3] = 0; /* *gd_PMAP1 */
2241 /* allocate and set up an idle stack data page */
2242 stack = (char *)kmem_alloc(&kernel_map, UPAGES*PAGE_SIZE);
2243 for (i = 0; i < UPAGES; i++) {
2244 SMPpt[pg + 4 + i] = (pt_entry_t)
2245 (PG_V | PG_RW | vtophys_pte(PAGE_SIZE * i + stack));
2248 gd = &CPU_prvspace[x].mdglobaldata; /* official location */
2249 bzero(gd, sizeof(*gd));
2250 gd->mi.gd_prvspace = ps = &CPU_prvspace[x];
2252 /* prime data page for it to use */
2253 mi_gdinit(&gd->mi, x);
2255 gd->gd_CMAP1 = &SMPpt[pg + 0];
2256 gd->gd_CMAP2 = &SMPpt[pg + 1];
2257 gd->gd_CMAP3 = &SMPpt[pg + 2];
2258 gd->gd_PMAP1 = &SMPpt[pg + 3];
2259 gd->gd_CADDR1 = ps->CPAGE1;
2260 gd->gd_CADDR2 = ps->CPAGE2;
2261 gd->gd_CADDR3 = ps->CPAGE3;
2262 gd->gd_PADDR1 = (unsigned *)ps->PPAGE1;
2263 gd->mi.gd_ipiq = (void *)kmem_alloc(&kernel_map, sizeof(lwkt_ipiq) * (mp_naps + 1));
2264 bzero(gd->mi.gd_ipiq, sizeof(lwkt_ipiq) * (mp_naps + 1));
2266 /* setup a vector to our boot code */
2267 *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET;
2268 *((volatile u_short *) WARMBOOT_SEG) = (boot_addr >> 4);
2269 outb(CMOS_REG, BIOS_RESET);
2270 outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */
2273 * Setup the AP boot stack
2275 bootSTK = &ps->idlestack[UPAGES*PAGE_SIZE/2];
2278 /* attempt to start the Application Processor */
2279 CHECK_INIT(99); /* setup checkpoints */
2280 if (!start_ap(gd, boot_addr)) {
2281 kprintf("AP #%d (PHY# %d) failed!\n", x, CPU_TO_ID(x));
2282 CHECK_PRINT("trace"); /* show checkpoints */
2283 /* better panic as the AP may be running loose */
2284 kprintf("panic y/n? [y] ");
2285 if (cngetc() != 'n')
2288 CHECK_PRINT("trace"); /* show checkpoints */
2290 /* record its version info */
2291 cpu_apic_versions[x] = cpu_apic_versions[0];
2294 /* set ncpus to 1 + highest logical cpu. Not all may have come up */
2297 /* ncpus2 -- ncpus rounded down to the nearest power of 2 */
2298 for (shift = 0; (1 << shift) <= ncpus; ++shift)
2301 ncpus2_shift = shift;
2302 ncpus2 = 1 << shift;
2303 ncpus2_mask = ncpus2 - 1;
2305 /* ncpus_fit -- ncpus rounded up to the nearest power of 2 */
2306 if ((1 << shift) < ncpus)
2308 ncpus_fit = 1 << shift;
2309 ncpus_fit_mask = ncpus_fit - 1;
2311 /* build our map of 'other' CPUs */
2312 mycpu->gd_other_cpus = smp_startup_mask & ~(1 << mycpu->gd_cpuid);
2313 mycpu->gd_ipiq = (void *)kmem_alloc(&kernel_map, sizeof(lwkt_ipiq) * ncpus);
2314 bzero(mycpu->gd_ipiq, sizeof(lwkt_ipiq) * ncpus);
2316 /* fill in our (BSP) APIC version */
2317 cpu_apic_versions[0] = lapic.version;
2319 /* restore the warmstart vector */
2320 *(u_long *) WARMBOOT_OFF = mpbioswarmvec;
2321 outb(CMOS_REG, BIOS_RESET);
2322 outb(CMOS_DATA, mpbiosreason);
2325 * NOTE! The idlestack for the BSP was setup by locore. Finish
2326 * up, clean out the P==V mapping we did earlier.
2328 for (x = 0; x < NKPT; x++)
2332 /* number of APs actually started */
2338 * load the 1st level AP boot code into base memory.
2341 /* targets for relocation */
2342 extern void bigJump(void);
2343 extern void bootCodeSeg(void);
2344 extern void bootDataSeg(void);
2345 extern void MPentry(void);
2346 extern u_int MP_GDT;
2347 extern u_int mp_gdtbase;
2350 install_ap_tramp(u_int boot_addr)
2353 int size = *(int *) ((u_long) & bootMP_size);
2354 u_char *src = (u_char *) ((u_long) bootMP);
2355 u_char *dst = (u_char *) boot_addr + KERNBASE;
2356 u_int boot_base = (u_int) bootMP;
2361 POSTCODE(INSTALL_AP_TRAMP_POST);
2363 for (x = 0; x < size; ++x)
2367 * modify addresses in code we just moved to basemem. unfortunately we
2368 * need fairly detailed info about mpboot.s for this to work. changes
2369 * to mpboot.s might require changes here.
2372 /* boot code is located in KERNEL space */
2373 dst = (u_char *) boot_addr + KERNBASE;
2375 /* modify the lgdt arg */
2376 dst32 = (u_int32_t *) (dst + ((u_int) & mp_gdtbase - boot_base));
2377 *dst32 = boot_addr + ((u_int) & MP_GDT - boot_base);
2379 /* modify the ljmp target for MPentry() */
2380 dst32 = (u_int32_t *) (dst + ((u_int) bigJump - boot_base) + 1);
2381 *dst32 = ((u_int) MPentry - KERNBASE);
2383 /* modify the target for boot code segment */
2384 dst16 = (u_int16_t *) (dst + ((u_int) bootCodeSeg - boot_base));
2385 dst8 = (u_int8_t *) (dst16 + 1);
2386 *dst16 = (u_int) boot_addr & 0xffff;
2387 *dst8 = ((u_int) boot_addr >> 16) & 0xff;
2389 /* modify the target for boot data segment */
2390 dst16 = (u_int16_t *) (dst + ((u_int) bootDataSeg - boot_base));
2391 dst8 = (u_int8_t *) (dst16 + 1);
2392 *dst16 = (u_int) boot_addr & 0xffff;
2393 *dst8 = ((u_int) boot_addr >> 16) & 0xff;
2398 * this function starts the AP (application processor) identified
2399 * by the APIC ID 'physicalCpu'. It does quite a "song and dance"
2400 * to accomplish this. This is necessary because of the nuances
2401 * of the different hardware we might encounter. It ain't pretty,
2402 * but it seems to work.
2404 * NOTE: eventually an AP gets to ap_init(), which is called just
2405 * before the AP goes into the LWKT scheduler's idle loop.
2408 start_ap(struct mdglobaldata *gd, u_int boot_addr)
2412 u_long icr_lo, icr_hi;
2414 POSTCODE(START_AP_POST);
2416 /* get the PHYSICAL APIC ID# */
2417 physical_cpu = CPU_TO_ID(gd->mi.gd_cpuid);
2419 /* calculate the vector */
2420 vector = (boot_addr >> 12) & 0xff;
2422 /* Make sure the target cpu sees everything */
2426 * first we do an INIT/RESET IPI this INIT IPI might be run, reseting
2427 * and running the target CPU. OR this INIT IPI might be latched (P5
2428 * bug), CPU waiting for STARTUP IPI. OR this INIT IPI might be
2432 /* setup the address for the target AP */
2433 icr_hi = lapic.icr_hi & ~APIC_ID_MASK;
2434 icr_hi |= (physical_cpu << 24);
2435 lapic.icr_hi = icr_hi;
2437 /* do an INIT IPI: assert RESET */
2438 icr_lo = lapic.icr_lo & 0xfff00000;
2439 lapic.icr_lo = icr_lo | 0x0000c500;
2441 /* wait for pending status end */
2442 while (lapic.icr_lo & APIC_DELSTAT_MASK)
2445 /* do an INIT IPI: deassert RESET */
2446 lapic.icr_lo = icr_lo | 0x00008500;
2448 /* wait for pending status end */
2449 u_sleep(10000); /* wait ~10mS */
2450 while (lapic.icr_lo & APIC_DELSTAT_MASK)
2454 * next we do a STARTUP IPI: the previous INIT IPI might still be
2455 * latched, (P5 bug) this 1st STARTUP would then terminate
2456 * immediately, and the previously started INIT IPI would continue. OR
2457 * the previous INIT IPI has already run. and this STARTUP IPI will
2458 * run. OR the previous INIT IPI was ignored. and this STARTUP IPI
2462 /* do a STARTUP IPI */
2463 lapic.icr_lo = icr_lo | 0x00000600 | vector;
2464 while (lapic.icr_lo & APIC_DELSTAT_MASK)
2466 u_sleep(200); /* wait ~200uS */
2469 * finally we do a 2nd STARTUP IPI: this 2nd STARTUP IPI should run IF
2470 * the previous STARTUP IPI was cancelled by a latched INIT IPI. OR
2471 * this STARTUP IPI will be ignored, as only ONE STARTUP IPI is
2472 * recognized after hardware RESET or INIT IPI.
2475 lapic.icr_lo = icr_lo | 0x00000600 | vector;
2476 while (lapic.icr_lo & APIC_DELSTAT_MASK)
2478 u_sleep(200); /* wait ~200uS */
2480 /* wait for it to start, see ap_init() */
2481 set_apic_timer(5000000);/* == 5 seconds */
2482 while (read_apic_timer()) {
2483 if (smp_startup_mask & (1 << gd->mi.gd_cpuid))
2484 return 1; /* return SUCCESS */
2486 return 0; /* return FAILURE */
2491 * Lazy flush the TLB on all other CPU's. DEPRECATED.
2493 * If for some reason we were unable to start all cpus we cannot safely
2494 * use broadcast IPIs.
2500 if (smp_startup_mask == smp_active_mask) {
2501 all_but_self_ipi(XINVLTLB_OFFSET);
2503 selected_apic_ipi(smp_active_mask, XINVLTLB_OFFSET,
2504 APIC_DELMODE_FIXED);
2510 * When called the executing CPU will send an IPI to all other CPUs
2511 * requesting that they halt execution.
2513 * Usually (but not necessarily) called with 'other_cpus' as its arg.
2515 * - Signals all CPUs in map to stop.
2516 * - Waits for each to stop.
2523 * XXX FIXME: this is not MP-safe, needs a lock to prevent multiple CPUs
2524 * from executing at same time.
2527 stop_cpus(u_int map)
2529 map &= smp_active_mask;
2531 /* send the Xcpustop IPI to all CPUs in map */
2532 selected_apic_ipi(map, XCPUSTOP_OFFSET, APIC_DELMODE_FIXED);
2534 while ((stopped_cpus & map) != map)
2542 * Called by a CPU to restart stopped CPUs.
2544 * Usually (but not necessarily) called with 'stopped_cpus' as its arg.
2546 * - Signals all CPUs in map to restart.
2547 * - Waits for each to restart.
2555 restart_cpus(u_int map)
2557 /* signal other cpus to restart */
2558 started_cpus = map & smp_active_mask;
2560 while ((stopped_cpus & map) != 0) /* wait for each to clear its bit */
2567 * This is called once the mpboot code has gotten us properly relocated
2568 * and the MMU turned on, etc. ap_init() is actually the idle thread,
2569 * and when it returns the scheduler will call the real cpu_idle() main
2570 * loop for the idlethread. Interrupts are disabled on entry and should
2571 * remain disabled at return.
2579 * Adjust smp_startup_mask to signal the BSP that we have started
2580 * up successfully. Note that we do not yet hold the BGL. The BSP
2581 * is waiting for our signal.
2583 * We can't set our bit in smp_active_mask yet because we are holding
2584 * interrupts physically disabled and remote cpus could deadlock
2585 * trying to send us an IPI.
2587 smp_startup_mask |= 1 << mycpu->gd_cpuid;
2591 * Interlock for finalization. Wait until mp_finish is non-zero,
2592 * then get the MP lock.
2594 * Note: We are in a critical section.
2596 * Note: We have to synchronize td_mpcount to our desired MP state
2597 * before calling cpu_try_mplock().
2599 * Note: we are the idle thread, we can only spin.
2601 * Note: The load fence is memory volatile and prevents the compiler
2602 * from improperly caching mp_finish, and the cpu from improperly
2605 while (mp_finish == 0)
2607 ++curthread->td_mpcount;
2608 while (cpu_try_mplock() == 0)
2611 if (cpu_feature & CPUID_TSC) {
2613 * The BSP is constantly updating tsc0_offset, figure out the
2614 * relative difference to synchronize ktrdump.
2616 tsc_offsets[mycpu->gd_cpuid] = rdtsc() - tsc0_offset;
2619 /* BSP may have changed PTD while we're waiting for the lock */
2622 #if defined(I586_CPU) && !defined(NO_F00F_HACK)
2626 /* Build our map of 'other' CPUs. */
2627 mycpu->gd_other_cpus = smp_startup_mask & ~(1 << mycpu->gd_cpuid);
2629 kprintf("SMP: AP CPU #%d Launched!\n", mycpu->gd_cpuid);
2631 /* A quick check from sanity claus */
2632 apic_id = (apic_id_to_logical[(lapic.id & 0x0f000000) >> 24]);
2633 if (mycpu->gd_cpuid != apic_id) {
2634 kprintf("SMP: cpuid = %d\n", mycpu->gd_cpuid);
2635 kprintf("SMP: apic_id = %d\n", apic_id);
2636 kprintf("PTD[MPPTDI] = %p\n", (void *)PTD[MPPTDI]);
2637 panic("cpuid mismatch! boom!!");
2640 /* Initialize AP's local APIC for irq's */
2641 apic_initialize(FALSE);
2643 /* Set memory range attributes for this CPU to match the BSP */
2644 mem_range_AP_init();
2647 * Once we go active we must process any IPIQ messages that may
2648 * have been queued, because no actual IPI will occur until we
2649 * set our bit in the smp_active_mask. If we don't the IPI
2650 * message interlock could be left set which would also prevent
2653 * The idle loop doesn't expect the BGL to be held and while
2654 * lwkt_switch() normally cleans things up this is a special case
2655 * because we returning almost directly into the idle loop.
2657 * The idle thread is never placed on the runq, make sure
2658 * nothing we've done put it there.
2660 KKASSERT(curthread->td_mpcount == 1);
2661 smp_active_mask |= 1 << mycpu->gd_cpuid;
2664 * Enable interrupts here. idle_restore will also do it, but
2665 * doing it here lets us clean up any strays that got posted to
2666 * the CPU during the AP boot while we are still in a critical
2669 __asm __volatile("sti; pause; pause"::);
2670 mdcpu->gd_fpending = 0;
2672 initclocks_pcpu(); /* clock interrupts (via IPIs) */
2673 lwkt_process_ipiq();
2676 * Releasing the mp lock lets the BSP finish up the SMP init
2679 KKASSERT((curthread->td_flags & TDF_RUNQ) == 0);
2683 * Get SMP fully working before we start initializing devices.
2691 kprintf("Finish MP startup\n");
2692 if (cpu_feature & CPUID_TSC)
2693 tsc0_offset = rdtsc();
2696 while (smp_active_mask != smp_startup_mask) {
2698 if (cpu_feature & CPUID_TSC)
2699 tsc0_offset = rdtsc();
2701 while (try_mplock() == 0)
2704 kprintf("Active CPU Mask: %08x\n", smp_active_mask);
2707 SYSINIT(finishsmp, SI_BOOT2_FINISH_SMP, SI_ORDER_FIRST, ap_finish, NULL)
2710 cpu_send_ipiq(int dcpu)
2712 if ((1 << dcpu) & smp_active_mask)
2713 single_apic_ipi(dcpu, XIPIQ_OFFSET, APIC_DELMODE_FIXED);
2716 #if 0 /* single_apic_ipi_passive() not working yet */
2718 * Returns 0 on failure, 1 on success
2721 cpu_send_ipiq_passive(int dcpu)
2724 if ((1 << dcpu) & smp_active_mask) {
2725 r = single_apic_ipi_passive(dcpu, XIPIQ_OFFSET,
2726 APIC_DELMODE_FIXED);
2732 struct mptable_lapic_cbarg1 {
2735 u_int ht_apicid_mask;
2739 mptable_lapic_pass1_callback(void *xarg, const void *pos, int type)
2741 const struct PROCENTRY *ent;
2742 struct mptable_lapic_cbarg1 *arg = xarg;
2748 if ((ent->cpu_flags & PROCENTRY_FLAG_EN) == 0)
2752 if (ent->apic_id < 32) {
2753 arg->ht_apicid_mask |= 1 << ent->apic_id;
2754 } else if (arg->ht_fixup) {
2755 kprintf("MPTABLE: lapic id > 32, disable HTT fixup\n");
2761 struct mptable_lapic_cbarg2 {
2768 mptable_lapic_pass2_callback(void *xarg, const void *pos, int type)
2770 const struct PROCENTRY *ent;
2771 struct mptable_lapic_cbarg2 *arg = xarg;
2777 if (ent->cpu_flags & PROCENTRY_FLAG_BP) {
2778 KKASSERT(!arg->found_bsp);
2782 if (processor_entry(ent, arg->cpu))
2785 if (arg->logical_cpus) {
2786 struct PROCENTRY proc;
2790 * Create fake mptable processor entries
2791 * and feed them to processor_entry() to
2792 * enumerate the logical CPUs.
2794 bzero(&proc, sizeof(proc));
2796 proc.cpu_flags = PROCENTRY_FLAG_EN;
2797 proc.apic_id = ent->apic_id;
2799 for (i = 1; i < arg->logical_cpus; i++) {
2801 processor_entry(&proc, arg->cpu);
2809 mptable_imcr(struct mptable_pos *mpt)
2811 /* record whether PIC or virtual-wire mode */
2812 machintr_setvar_simple(MACHINTR_VAR_IMCR_PRESENT,
2813 mpt->mp_fps->mpfb2 & 0x80);
2816 struct mptable_lapic_enumerator {
2817 struct lapic_enumerator enumerator;
2818 vm_paddr_t mpfps_paddr;
2822 mptable_lapic_default(void)
2824 int ap_apicid, bsp_apicid;
2826 mp_naps = 1; /* exclude BSP */
2828 /* Map local apic before the id field is accessed */
2829 lapic_map(DEFAULT_APIC_BASE);
2831 bsp_apicid = APIC_ID(lapic.id);
2832 ap_apicid = (bsp_apicid == 0) ? 1 : 0;
2835 mp_set_cpuids(0, bsp_apicid);
2836 /* one and only AP */
2837 mp_set_cpuids(1, ap_apicid);
2843 * ID_TO_CPU(N), APIC ID to logical CPU table
2844 * CPU_TO_ID(N), logical CPU to APIC ID table
2847 mptable_lapic_enumerate(struct lapic_enumerator *e)
2849 struct mptable_pos mpt;
2850 struct mptable_lapic_cbarg1 arg1;
2851 struct mptable_lapic_cbarg2 arg2;
2853 int error, logical_cpus = 0;
2854 vm_offset_t lapic_addr;
2855 vm_paddr_t mpfps_paddr;
2857 mpfps_paddr = ((struct mptable_lapic_enumerator *)e)->mpfps_paddr;
2858 KKASSERT(mpfps_paddr != 0);
2860 error = mptable_map(&mpt, mpfps_paddr);
2862 panic("mptable_lapic_enumerate mptable_map failed\n");
2864 KKASSERT(mpt.mp_fps != NULL);
2867 * Check for use of 'default' configuration
2869 if (mpt.mp_fps->mpfb1 != 0) {
2870 mptable_lapic_default();
2871 mptable_unmap(&mpt);
2876 KKASSERT(cth != NULL);
2878 /* Save local apic address */
2879 lapic_addr = (vm_offset_t)cth->apic_address;
2880 KKASSERT(lapic_addr != 0);
2883 * Find out how many CPUs do we have
2885 bzero(&arg1, sizeof(arg1));
2886 arg1.ht_fixup = 1; /* Apply ht fixup by default */
2888 error = mptable_iterate_entries(cth,
2889 mptable_lapic_pass1_callback, &arg1);
2891 panic("mptable_iterate_entries(lapic_pass1) failed\n");
2892 KKASSERT(arg1.cpu_count != 0);
2894 /* See if we need to fixup HT logical CPUs. */
2895 if (arg1.ht_fixup) {
2896 logical_cpus = mptable_hyperthread_fixup(arg1.ht_apicid_mask,
2898 if (logical_cpus != 0)
2899 arg1.cpu_count *= logical_cpus;
2901 mp_naps = arg1.cpu_count;
2903 /* Qualify the numbers again, after possible HT fixup */
2904 if (mp_naps > MAXCPU) {
2905 kprintf("Warning: only using %d of %d available CPUs!\n",
2910 --mp_naps; /* subtract the BSP */
2913 * Link logical CPU id to local apic id
2915 bzero(&arg2, sizeof(arg2));
2917 arg2.logical_cpus = logical_cpus;
2919 error = mptable_iterate_entries(cth,
2920 mptable_lapic_pass2_callback, &arg2);
2922 panic("mptable_iterate_entries(lapic_pass2) failed\n");
2923 KKASSERT(arg2.found_bsp);
2925 /* Map local apic */
2926 lapic_map(lapic_addr);
2928 mptable_unmap(&mpt);
2932 mptable_lapic_probe(struct lapic_enumerator *e)
2934 vm_paddr_t mpfps_paddr;
2936 mpfps_paddr = mptable_probe();
2937 if (mpfps_paddr == 0)
2940 ((struct mptable_lapic_enumerator *)e)->mpfps_paddr = mpfps_paddr;
2944 static struct mptable_lapic_enumerator mptable_lapic_enumerator = {
2946 .lapic_prio = LAPIC_ENUM_PRIO_MPTABLE,
2947 .lapic_probe = mptable_lapic_probe,
2948 .lapic_enumerate = mptable_lapic_enumerate
2953 mptable_apic_register(void)
2955 lapic_enumerator_register(&mptable_lapic_enumerator.enumerator);
2957 SYSINIT(madt, SI_BOOT2_PRESMP, SI_ORDER_ANY, mptable_apic_register, 0);