igb: Add per-TX ring enable flag.
[dragonfly.git] / sys / dev / netif / igb / if_igb.c
1 /*
2  * Copyright (c) 2001-2011, Intel Corporation 
3  * All rights reserved.
4  * 
5  * Redistribution and use in source and binary forms, with or without 
6  * modification, are permitted provided that the following conditions are met:
7  * 
8  *  1. Redistributions of source code must retain the above copyright notice, 
9  *     this list of conditions and the following disclaimer.
10  * 
11  *  2. Redistributions in binary form must reproduce the above copyright 
12  *     notice, this list of conditions and the following disclaimer in the 
13  *     documentation and/or other materials provided with the distribution.
14  * 
15  *  3. Neither the name of the Intel Corporation nor the names of its 
16  *     contributors may be used to endorse or promote products derived from 
17  *     this software without specific prior written permission.
18  * 
19  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 
21  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 
22  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 
23  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 
24  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 
25  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
26  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
27  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
28  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29  * POSSIBILITY OF SUCH DAMAGE.
30  */
31
32 #include "opt_ifpoll.h"
33 #include "opt_igb.h"
34
35 #include <sys/param.h>
36 #include <sys/bus.h>
37 #include <sys/endian.h>
38 #include <sys/interrupt.h>
39 #include <sys/kernel.h>
40 #include <sys/malloc.h>
41 #include <sys/mbuf.h>
42 #include <sys/proc.h>
43 #include <sys/rman.h>
44 #include <sys/serialize.h>
45 #include <sys/serialize2.h>
46 #include <sys/socket.h>
47 #include <sys/sockio.h>
48 #include <sys/sysctl.h>
49 #include <sys/systm.h>
50
51 #include <net/bpf.h>
52 #include <net/ethernet.h>
53 #include <net/if.h>
54 #include <net/if_arp.h>
55 #include <net/if_dl.h>
56 #include <net/if_media.h>
57 #include <net/ifq_var.h>
58 #include <net/toeplitz.h>
59 #include <net/toeplitz2.h>
60 #include <net/vlan/if_vlan_var.h>
61 #include <net/vlan/if_vlan_ether.h>
62 #include <net/if_poll.h>
63
64 #include <netinet/in_systm.h>
65 #include <netinet/in.h>
66 #include <netinet/ip.h>
67 #include <netinet/tcp.h>
68 #include <netinet/udp.h>
69
70 #include <bus/pci/pcivar.h>
71 #include <bus/pci/pcireg.h>
72
73 #include <dev/netif/ig_hal/e1000_api.h>
74 #include <dev/netif/ig_hal/e1000_82575.h>
75 #include <dev/netif/igb/if_igb.h>
76
77 #ifdef IGB_RSS_DEBUG
78 #define IGB_RSS_DPRINTF(sc, lvl, fmt, ...) \
79 do { \
80         if (sc->rss_debug >= lvl) \
81                 if_printf(&sc->arpcom.ac_if, fmt, __VA_ARGS__); \
82 } while (0)
83 #else   /* !IGB_RSS_DEBUG */
84 #define IGB_RSS_DPRINTF(sc, lvl, fmt, ...)      ((void)0)
85 #endif  /* IGB_RSS_DEBUG */
86
87 #define IGB_NAME        "Intel(R) PRO/1000 "
88 #define IGB_DEVICE(id)  \
89         { IGB_VENDOR_ID, E1000_DEV_ID_##id, IGB_NAME #id }
90 #define IGB_DEVICE_NULL { 0, 0, NULL }
91
92 static struct igb_device {
93         uint16_t        vid;
94         uint16_t        did;
95         const char      *desc;
96 } igb_devices[] = {
97         IGB_DEVICE(82575EB_COPPER),
98         IGB_DEVICE(82575EB_FIBER_SERDES),
99         IGB_DEVICE(82575GB_QUAD_COPPER),
100         IGB_DEVICE(82576),
101         IGB_DEVICE(82576_NS),
102         IGB_DEVICE(82576_NS_SERDES),
103         IGB_DEVICE(82576_FIBER),
104         IGB_DEVICE(82576_SERDES),
105         IGB_DEVICE(82576_SERDES_QUAD),
106         IGB_DEVICE(82576_QUAD_COPPER),
107         IGB_DEVICE(82576_QUAD_COPPER_ET2),
108         IGB_DEVICE(82576_VF),
109         IGB_DEVICE(82580_COPPER),
110         IGB_DEVICE(82580_FIBER),
111         IGB_DEVICE(82580_SERDES),
112         IGB_DEVICE(82580_SGMII),
113         IGB_DEVICE(82580_COPPER_DUAL),
114         IGB_DEVICE(82580_QUAD_FIBER),
115         IGB_DEVICE(DH89XXCC_SERDES),
116         IGB_DEVICE(DH89XXCC_SGMII),
117         IGB_DEVICE(DH89XXCC_SFP),
118         IGB_DEVICE(DH89XXCC_BACKPLANE),
119         IGB_DEVICE(I350_COPPER),
120         IGB_DEVICE(I350_FIBER),
121         IGB_DEVICE(I350_SERDES),
122         IGB_DEVICE(I350_SGMII),
123         IGB_DEVICE(I350_VF),
124
125         /* required last entry */
126         IGB_DEVICE_NULL
127 };
128
129 static int      igb_probe(device_t);
130 static int      igb_attach(device_t);
131 static int      igb_detach(device_t);
132 static int      igb_shutdown(device_t);
133 static int      igb_suspend(device_t);
134 static int      igb_resume(device_t);
135
136 static boolean_t igb_is_valid_ether_addr(const uint8_t *);
137 static void     igb_setup_ifp(struct igb_softc *);
138 static boolean_t igb_txcsum_ctx(struct igb_tx_ring *, struct mbuf *);
139 static int      igb_tso_pullup(struct igb_tx_ring *, struct mbuf **);
140 static void     igb_tso_ctx(struct igb_tx_ring *, struct mbuf *, uint32_t *);
141 static void     igb_add_sysctl(struct igb_softc *);
142 static int      igb_sysctl_intr_rate(SYSCTL_HANDLER_ARGS);
143 static int      igb_sysctl_msix_rate(SYSCTL_HANDLER_ARGS);
144 static int      igb_sysctl_tx_intr_nsegs(SYSCTL_HANDLER_ARGS);
145 static int      igb_sysctl_tx_wreg_nsegs(SYSCTL_HANDLER_ARGS);
146 static int      igb_sysctl_rx_wreg_nsegs(SYSCTL_HANDLER_ARGS);
147 static void     igb_set_ring_inuse(struct igb_softc *, boolean_t);
148 static int      igb_get_rxring_inuse(const struct igb_softc *, boolean_t);
149 static int      igb_get_txring_inuse(const struct igb_softc *, boolean_t);
150 #ifdef IFPOLL_ENABLE
151 static int      igb_sysctl_npoll_rxoff(SYSCTL_HANDLER_ARGS);
152 static int      igb_sysctl_npoll_txoff(SYSCTL_HANDLER_ARGS);
153 #endif
154
155 static void     igb_vf_init_stats(struct igb_softc *);
156 static void     igb_reset(struct igb_softc *);
157 static void     igb_update_stats_counters(struct igb_softc *);
158 static void     igb_update_vf_stats_counters(struct igb_softc *);
159 static void     igb_update_link_status(struct igb_softc *);
160 static void     igb_init_tx_unit(struct igb_softc *);
161 static void     igb_init_rx_unit(struct igb_softc *);
162
163 static void     igb_set_vlan(struct igb_softc *);
164 static void     igb_set_multi(struct igb_softc *);
165 static void     igb_set_promisc(struct igb_softc *);
166 static void     igb_disable_promisc(struct igb_softc *);
167
168 static int      igb_alloc_rings(struct igb_softc *);
169 static void     igb_free_rings(struct igb_softc *);
170 static int      igb_create_tx_ring(struct igb_tx_ring *);
171 static int      igb_create_rx_ring(struct igb_rx_ring *);
172 static void     igb_free_tx_ring(struct igb_tx_ring *);
173 static void     igb_free_rx_ring(struct igb_rx_ring *);
174 static void     igb_destroy_tx_ring(struct igb_tx_ring *, int);
175 static void     igb_destroy_rx_ring(struct igb_rx_ring *, int);
176 static void     igb_init_tx_ring(struct igb_tx_ring *);
177 static int      igb_init_rx_ring(struct igb_rx_ring *);
178 static int      igb_newbuf(struct igb_rx_ring *, int, boolean_t);
179 static int      igb_encap(struct igb_tx_ring *, struct mbuf **, int *, int *);
180 static void     igb_rx_refresh(struct igb_rx_ring *, int);
181
182 static void     igb_stop(struct igb_softc *);
183 static void     igb_init(void *);
184 static int      igb_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
185 static void     igb_media_status(struct ifnet *, struct ifmediareq *);
186 static int      igb_media_change(struct ifnet *);
187 static void     igb_timer(void *);
188 static void     igb_watchdog(struct ifaltq_subque *);
189 static void     igb_start(struct ifnet *, struct ifaltq_subque *);
190 #ifdef IFPOLL_ENABLE
191 static void     igb_npoll(struct ifnet *, struct ifpoll_info *);
192 static void     igb_npoll_rx(struct ifnet *, void *, int);
193 static void     igb_npoll_tx(struct ifnet *, void *, int);
194 static void     igb_npoll_status(struct ifnet *);
195 #endif
196 static void     igb_serialize(struct ifnet *, enum ifnet_serialize);
197 static void     igb_deserialize(struct ifnet *, enum ifnet_serialize);
198 static int      igb_tryserialize(struct ifnet *, enum ifnet_serialize);
199 #ifdef INVARIANTS
200 static void     igb_serialize_assert(struct ifnet *, enum ifnet_serialize,
201                     boolean_t);
202 #endif
203
204 static void     igb_intr(void *);
205 static void     igb_intr_shared(void *);
206 static void     igb_rxeof(struct igb_rx_ring *, int);
207 static void     igb_txeof(struct igb_tx_ring *);
208 static void     igb_set_eitr(struct igb_softc *, int, int);
209 static void     igb_enable_intr(struct igb_softc *);
210 static void     igb_disable_intr(struct igb_softc *);
211 static void     igb_init_unshared_intr(struct igb_softc *);
212 static void     igb_init_intr(struct igb_softc *);
213 static int      igb_setup_intr(struct igb_softc *);
214 static void     igb_set_txintr_mask(struct igb_tx_ring *, int *, int);
215 static void     igb_set_rxintr_mask(struct igb_rx_ring *, int *, int);
216 static void     igb_set_intr_mask(struct igb_softc *);
217 static int      igb_alloc_intr(struct igb_softc *);
218 static void     igb_free_intr(struct igb_softc *);
219 static void     igb_teardown_intr(struct igb_softc *);
220 static void     igb_msix_try_alloc(struct igb_softc *);
221 static void     igb_msix_free(struct igb_softc *, boolean_t);
222 static int      igb_msix_setup(struct igb_softc *);
223 static void     igb_msix_teardown(struct igb_softc *, int);
224 static void     igb_msix_rx(void *);
225 static void     igb_msix_tx(void *);
226 static void     igb_msix_status(void *);
227
228 /* Management and WOL Support */
229 static void     igb_get_mgmt(struct igb_softc *);
230 static void     igb_rel_mgmt(struct igb_softc *);
231 static void     igb_get_hw_control(struct igb_softc *);
232 static void     igb_rel_hw_control(struct igb_softc *);
233 static void     igb_enable_wol(device_t);
234
235 static device_method_t igb_methods[] = {
236         /* Device interface */
237         DEVMETHOD(device_probe,         igb_probe),
238         DEVMETHOD(device_attach,        igb_attach),
239         DEVMETHOD(device_detach,        igb_detach),
240         DEVMETHOD(device_shutdown,      igb_shutdown),
241         DEVMETHOD(device_suspend,       igb_suspend),
242         DEVMETHOD(device_resume,        igb_resume),
243         { 0, 0 }
244 };
245
246 static driver_t igb_driver = {
247         "igb",
248         igb_methods,
249         sizeof(struct igb_softc),
250 };
251
252 static devclass_t igb_devclass;
253
254 DECLARE_DUMMY_MODULE(if_igb);
255 MODULE_DEPEND(igb, ig_hal, 1, 1, 1);
256 DRIVER_MODULE(if_igb, pci, igb_driver, igb_devclass, NULL, NULL);
257
258 static int      igb_rxd = IGB_DEFAULT_RXD;
259 static int      igb_txd = IGB_DEFAULT_TXD;
260 static int      igb_rxr = 0;
261 static int      igb_txr = 0;
262 static int      igb_msi_enable = 1;
263 static int      igb_msix_enable = 1;
264 static int      igb_eee_disabled = 1;   /* Energy Efficient Ethernet */
265 static int      igb_fc_setting = e1000_fc_full;
266
267 /*
268  * DMA Coalescing, only for i350 - default to off,
269  * this feature is for power savings
270  */
271 static int      igb_dma_coalesce = 0;
272
273 TUNABLE_INT("hw.igb.rxd", &igb_rxd);
274 TUNABLE_INT("hw.igb.txd", &igb_txd);
275 TUNABLE_INT("hw.igb.rxr", &igb_rxr);
276 TUNABLE_INT("hw.igb.txr", &igb_txr);
277 TUNABLE_INT("hw.igb.msi.enable", &igb_msi_enable);
278 TUNABLE_INT("hw.igb.msix.enable", &igb_msix_enable);
279 TUNABLE_INT("hw.igb.fc_setting", &igb_fc_setting);
280
281 /* i350 specific */
282 TUNABLE_INT("hw.igb.eee_disabled", &igb_eee_disabled);
283 TUNABLE_INT("hw.igb.dma_coalesce", &igb_dma_coalesce);
284
285 static __inline void
286 igb_rxcsum(uint32_t staterr, struct mbuf *mp)
287 {
288         /* Ignore Checksum bit is set */
289         if (staterr & E1000_RXD_STAT_IXSM)
290                 return;
291
292         if ((staterr & (E1000_RXD_STAT_IPCS | E1000_RXDEXT_STATERR_IPE)) ==
293             E1000_RXD_STAT_IPCS)
294                 mp->m_pkthdr.csum_flags |= CSUM_IP_CHECKED | CSUM_IP_VALID;
295
296         if (staterr & (E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS)) {
297                 if ((staterr & E1000_RXDEXT_STATERR_TCPE) == 0) {
298                         mp->m_pkthdr.csum_flags |= CSUM_DATA_VALID |
299                             CSUM_PSEUDO_HDR | CSUM_FRAG_NOT_CHECKED;
300                         mp->m_pkthdr.csum_data = htons(0xffff);
301                 }
302         }
303 }
304
305 static __inline struct pktinfo *
306 igb_rssinfo(struct mbuf *m, struct pktinfo *pi,
307     uint32_t hash, uint32_t hashtype, uint32_t staterr)
308 {
309         switch (hashtype) {
310         case E1000_RXDADV_RSSTYPE_IPV4_TCP:
311                 pi->pi_netisr = NETISR_IP;
312                 pi->pi_flags = 0;
313                 pi->pi_l3proto = IPPROTO_TCP;
314                 break;
315
316         case E1000_RXDADV_RSSTYPE_IPV4:
317                 if (staterr & E1000_RXD_STAT_IXSM)
318                         return NULL;
319
320                 if ((staterr &
321                      (E1000_RXD_STAT_TCPCS | E1000_RXDEXT_STATERR_TCPE)) ==
322                     E1000_RXD_STAT_TCPCS) {
323                         pi->pi_netisr = NETISR_IP;
324                         pi->pi_flags = 0;
325                         pi->pi_l3proto = IPPROTO_UDP;
326                         break;
327                 }
328                 /* FALL THROUGH */
329         default:
330                 return NULL;
331         }
332
333         m->m_flags |= M_HASH;
334         m->m_pkthdr.hash = toeplitz_hash(hash);
335         return pi;
336 }
337
338 static int
339 igb_probe(device_t dev)
340 {
341         const struct igb_device *d;
342         uint16_t vid, did;
343
344         vid = pci_get_vendor(dev);
345         did = pci_get_device(dev);
346
347         for (d = igb_devices; d->desc != NULL; ++d) {
348                 if (vid == d->vid && did == d->did) {
349                         device_set_desc(dev, d->desc);
350                         return 0;
351                 }
352         }
353         return ENXIO;
354 }
355
356 static int
357 igb_attach(device_t dev)
358 {
359         struct igb_softc *sc = device_get_softc(dev);
360         uint16_t eeprom_data;
361         int error = 0, i, j, ring_max;
362 #ifdef IFPOLL_ENABLE
363         int offset, offset_def;
364 #endif
365
366 #ifdef notyet
367         /* SYSCTL stuff */
368         SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
369             SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
370             OID_AUTO, "nvm", CTLTYPE_INT|CTLFLAG_RW, adapter, 0,
371             igb_sysctl_nvm_info, "I", "NVM Information");
372         SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
373             SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
374             OID_AUTO, "flow_control", CTLTYPE_INT|CTLFLAG_RW,
375             adapter, 0, igb_set_flowcntl, "I", "Flow Control");
376 #endif
377
378         callout_init_mp(&sc->timer);
379         lwkt_serialize_init(&sc->main_serialize);
380
381         if_initname(&sc->arpcom.ac_if, device_get_name(dev),
382             device_get_unit(dev));
383         sc->dev = sc->osdep.dev = dev;
384
385         /*
386          * Determine hardware and mac type
387          */
388         sc->hw.vendor_id = pci_get_vendor(dev);
389         sc->hw.device_id = pci_get_device(dev);
390         sc->hw.revision_id = pci_read_config(dev, PCIR_REVID, 1);
391         sc->hw.subsystem_vendor_id = pci_read_config(dev, PCIR_SUBVEND_0, 2);
392         sc->hw.subsystem_device_id = pci_read_config(dev, PCIR_SUBDEV_0, 2);
393
394         if (e1000_set_mac_type(&sc->hw))
395                 return ENXIO;
396
397         /* Are we a VF device? */
398         if (sc->hw.mac.type == e1000_vfadapt ||
399             sc->hw.mac.type == e1000_vfadapt_i350)
400                 sc->vf_ifp = 1;
401         else
402                 sc->vf_ifp = 0;
403
404         /*
405          * Configure total supported RX/TX ring count
406          */
407         switch (sc->hw.mac.type) {
408         case e1000_82575:
409                 ring_max = IGB_MAX_RING_82575;
410                 break;
411         case e1000_82580:
412                 ring_max = IGB_MAX_RING_82580;
413                 break;
414         case e1000_i350:
415                 ring_max = IGB_MAX_RING_I350;
416                 break;
417         case e1000_82576:
418                 ring_max = IGB_MAX_RING_82576;
419                 break;
420         default:
421                 ring_max = IGB_MIN_RING;
422                 break;
423         }
424
425         sc->rx_ring_cnt = device_getenv_int(dev, "rxr", igb_rxr);
426         sc->rx_ring_cnt = if_ring_count2(sc->rx_ring_cnt, ring_max);
427 #ifdef IGB_RSS_DEBUG
428         sc->rx_ring_cnt = device_getenv_int(dev, "rxr_debug", sc->rx_ring_cnt);
429 #endif
430         sc->rx_ring_inuse = sc->rx_ring_cnt;
431
432         sc->tx_ring_cnt = device_getenv_int(dev, "txr", igb_txr);
433         sc->tx_ring_cnt = if_ring_count2(sc->tx_ring_cnt, /* XXX ring_max */1);
434 #ifdef IGB_TSS_DEBUG
435         sc->tx_ring_cnt = device_getenv_int(dev, "txr_debug", sc->tx_ring_cnt);
436 #endif
437         sc->tx_ring_inuse = sc->tx_ring_cnt;
438
439         /* Enable bus mastering */
440         pci_enable_busmaster(dev);
441
442         /*
443          * Allocate IO memory
444          */
445         sc->mem_rid = PCIR_BAR(0);
446         sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->mem_rid,
447             RF_ACTIVE);
448         if (sc->mem_res == NULL) {
449                 device_printf(dev, "Unable to allocate bus resource: memory\n");
450                 error = ENXIO;
451                 goto failed;
452         }
453         sc->osdep.mem_bus_space_tag = rman_get_bustag(sc->mem_res);
454         sc->osdep.mem_bus_space_handle = rman_get_bushandle(sc->mem_res);
455
456         sc->hw.hw_addr = (uint8_t *)&sc->osdep.mem_bus_space_handle;
457
458         /* Save PCI command register for Shared Code */
459         sc->hw.bus.pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2);
460         sc->hw.back = &sc->osdep;
461
462         /* Do Shared Code initialization */
463         if (e1000_setup_init_funcs(&sc->hw, TRUE)) {
464                 device_printf(dev, "Setup of Shared code failed\n");
465                 error = ENXIO;
466                 goto failed;
467         }
468
469         e1000_get_bus_info(&sc->hw);
470
471         sc->hw.mac.autoneg = DO_AUTO_NEG;
472         sc->hw.phy.autoneg_wait_to_complete = FALSE;
473         sc->hw.phy.autoneg_advertised = AUTONEG_ADV_DEFAULT;
474
475         /* Copper options */
476         if (sc->hw.phy.media_type == e1000_media_type_copper) {
477                 sc->hw.phy.mdix = AUTO_ALL_MODES;
478                 sc->hw.phy.disable_polarity_correction = FALSE;
479                 sc->hw.phy.ms_type = IGB_MASTER_SLAVE;
480         }
481
482         /* Set the frame limits assuming  standard ethernet sized frames. */
483         sc->max_frame_size = ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN;
484
485         /* Allocate RX/TX rings */
486         error = igb_alloc_rings(sc);
487         if (error)
488                 goto failed;
489
490 #ifdef IFPOLL_ENABLE
491         /*
492          * NPOLLING RX CPU offset
493          */
494         if (sc->rx_ring_cnt == ncpus2) {
495                 offset = 0;
496         } else {
497                 offset_def = (sc->rx_ring_cnt * device_get_unit(dev)) % ncpus2;
498                 offset = device_getenv_int(dev, "npoll.rxoff", offset_def);
499                 if (offset >= ncpus2 ||
500                     offset % sc->rx_ring_cnt != 0) {
501                         device_printf(dev, "invalid npoll.rxoff %d, use %d\n",
502                             offset, offset_def);
503                         offset = offset_def;
504                 }
505         }
506         sc->rx_npoll_off = offset;
507
508         /*
509          * NPOLLING TX CPU offset
510          */
511         if (sc->tx_ring_cnt == ncpus2) {
512                 offset = 0;
513         } else {
514                 offset_def = (sc->tx_ring_cnt * device_get_unit(dev)) % ncpus2;
515                 offset = device_getenv_int(dev, "npoll.txoff", offset_def);
516                 if (offset >= ncpus2 ||
517                     offset % sc->tx_ring_cnt != 0) {
518                         device_printf(dev, "invalid npoll.txoff %d, use %d\n",
519                             offset, offset_def);
520                         offset = offset_def;
521                 }
522         }
523         sc->tx_npoll_off = offset;
524 #endif
525
526         /* Allocate interrupt */
527         error = igb_alloc_intr(sc);
528         if (error)
529                 goto failed;
530
531         /*
532          * Setup serializers
533          */
534         i = 0;
535         sc->serializes[i++] = &sc->main_serialize;
536
537         sc->tx_serialize = i;
538         for (j = 0; j < sc->tx_ring_cnt; ++j)
539                 sc->serializes[i++] = &sc->tx_rings[j].tx_serialize;
540
541         sc->rx_serialize = i;
542         for (j = 0; j < sc->rx_ring_cnt; ++j)
543                 sc->serializes[i++] = &sc->rx_rings[j].rx_serialize;
544
545         sc->serialize_cnt = i;
546         KKASSERT(sc->serialize_cnt <= IGB_NSERIALIZE);
547
548         /* Allocate the appropriate stats memory */
549         if (sc->vf_ifp) {
550                 sc->stats = kmalloc(sizeof(struct e1000_vf_stats), M_DEVBUF,
551                     M_WAITOK | M_ZERO);
552                 igb_vf_init_stats(sc);
553         } else {
554                 sc->stats = kmalloc(sizeof(struct e1000_hw_stats), M_DEVBUF,
555                     M_WAITOK | M_ZERO);
556         }
557
558         /* Allocate multicast array memory. */
559         sc->mta = kmalloc(ETHER_ADDR_LEN * MAX_NUM_MULTICAST_ADDRESSES,
560             M_DEVBUF, M_WAITOK);
561
562         /* Some adapter-specific advanced features */
563         if (sc->hw.mac.type >= e1000_i350) {
564 #ifdef notyet
565                 igb_set_sysctl_value(adapter, "dma_coalesce",
566                     "configure dma coalesce",
567                     &adapter->dma_coalesce, igb_dma_coalesce);
568                 igb_set_sysctl_value(adapter, "eee_disabled",
569                     "enable Energy Efficient Ethernet",
570                     &adapter->hw.dev_spec._82575.eee_disable,
571                     igb_eee_disabled);
572 #else
573                 sc->dma_coalesce = igb_dma_coalesce;
574                 sc->hw.dev_spec._82575.eee_disable = igb_eee_disabled;
575 #endif
576                 e1000_set_eee_i350(&sc->hw);
577         }
578
579         /*
580          * Start from a known state, this is important in reading the nvm and
581          * mac from that.
582          */
583         e1000_reset_hw(&sc->hw);
584
585         /* Make sure we have a good EEPROM before we read from it */
586         if (e1000_validate_nvm_checksum(&sc->hw) < 0) {
587                 /*
588                  * Some PCI-E parts fail the first check due to
589                  * the link being in sleep state, call it again,
590                  * if it fails a second time its a real issue.
591                  */
592                 if (e1000_validate_nvm_checksum(&sc->hw) < 0) {
593                         device_printf(dev,
594                             "The EEPROM Checksum Is Not Valid\n");
595                         error = EIO;
596                         goto failed;
597                 }
598         }
599
600         /* Copy the permanent MAC address out of the EEPROM */
601         if (e1000_read_mac_addr(&sc->hw) < 0) {
602                 device_printf(dev, "EEPROM read error while reading MAC"
603                     " address\n");
604                 error = EIO;
605                 goto failed;
606         }
607         if (!igb_is_valid_ether_addr(sc->hw.mac.addr)) {
608                 device_printf(dev, "Invalid MAC address\n");
609                 error = EIO;
610                 goto failed;
611         }
612
613         /* Setup OS specific network interface */
614         igb_setup_ifp(sc);
615
616         /* Add sysctl tree, must after igb_setup_ifp() */
617         igb_add_sysctl(sc);
618
619         /* Now get a good starting state */
620         igb_reset(sc);
621
622         /* Initialize statistics */
623         igb_update_stats_counters(sc);
624
625         sc->hw.mac.get_link_status = 1;
626         igb_update_link_status(sc);
627
628         /* Indicate SOL/IDER usage */
629         if (e1000_check_reset_block(&sc->hw)) {
630                 device_printf(dev,
631                     "PHY reset is blocked due to SOL/IDER session.\n");
632         }
633
634         /* Determine if we have to control management hardware */
635         if (e1000_enable_mng_pass_thru(&sc->hw))
636                 sc->flags |= IGB_FLAG_HAS_MGMT;
637
638         /*
639          * Setup Wake-on-Lan
640          */
641         /* APME bit in EEPROM is mapped to WUC.APME */
642         eeprom_data = E1000_READ_REG(&sc->hw, E1000_WUC) & E1000_WUC_APME;
643         if (eeprom_data)
644                 sc->wol = E1000_WUFC_MAG;
645         /* XXX disable WOL */
646         sc->wol = 0; 
647
648 #ifdef notyet
649         /* Register for VLAN events */
650         adapter->vlan_attach = EVENTHANDLER_REGISTER(vlan_config,
651              igb_register_vlan, adapter, EVENTHANDLER_PRI_FIRST);
652         adapter->vlan_detach = EVENTHANDLER_REGISTER(vlan_unconfig,
653              igb_unregister_vlan, adapter, EVENTHANDLER_PRI_FIRST);
654 #endif
655
656 #ifdef notyet
657         igb_add_hw_stats(adapter);
658 #endif
659
660         error = igb_setup_intr(sc);
661         if (error) {
662                 ether_ifdetach(&sc->arpcom.ac_if);
663                 goto failed;
664         }
665
666         for (i = 0; i < sc->tx_ring_cnt; ++i) {
667                 struct ifaltq_subque *ifsq =
668                     ifq_get_subq(&sc->arpcom.ac_if.if_snd, i);
669                 struct igb_tx_ring *txr = &sc->tx_rings[i];
670
671                 ifsq_set_cpuid(ifsq, txr->tx_intr_cpuid);
672                 ifsq_set_priv(ifsq, txr);
673                 txr->ifsq = ifsq;
674
675                 ifsq_watchdog_init(&txr->tx_watchdog, ifsq, igb_watchdog);
676         }
677
678         return 0;
679
680 failed:
681         igb_detach(dev);
682         return error;
683 }
684
685 static int
686 igb_detach(device_t dev)
687 {
688         struct igb_softc *sc = device_get_softc(dev);
689
690         if (device_is_attached(dev)) {
691                 struct ifnet *ifp = &sc->arpcom.ac_if;
692
693                 ifnet_serialize_all(ifp);
694
695                 igb_stop(sc);
696
697                 e1000_phy_hw_reset(&sc->hw);
698
699                 /* Give control back to firmware */
700                 igb_rel_mgmt(sc);
701                 igb_rel_hw_control(sc);
702
703                 if (sc->wol) {
704                         E1000_WRITE_REG(&sc->hw, E1000_WUC, E1000_WUC_PME_EN);
705                         E1000_WRITE_REG(&sc->hw, E1000_WUFC, sc->wol);
706                         igb_enable_wol(dev);
707                 }
708
709                 igb_teardown_intr(sc);
710
711                 ifnet_deserialize_all(ifp);
712
713                 ether_ifdetach(ifp);
714         } else if (sc->mem_res != NULL) {
715                 igb_rel_hw_control(sc);
716         }
717         bus_generic_detach(dev);
718
719         if (sc->sysctl_tree != NULL)
720                 sysctl_ctx_free(&sc->sysctl_ctx);
721
722         igb_free_intr(sc);
723
724         if (sc->msix_mem_res != NULL) {
725                 bus_release_resource(dev, SYS_RES_MEMORY, sc->msix_mem_rid,
726                     sc->msix_mem_res);
727         }
728         if (sc->mem_res != NULL) {
729                 bus_release_resource(dev, SYS_RES_MEMORY, sc->mem_rid,
730                     sc->mem_res);
731         }
732
733         igb_free_rings(sc);
734
735         if (sc->mta != NULL)
736                 kfree(sc->mta, M_DEVBUF);
737         if (sc->stats != NULL)
738                 kfree(sc->stats, M_DEVBUF);
739
740         return 0;
741 }
742
743 static int
744 igb_shutdown(device_t dev)
745 {
746         return igb_suspend(dev);
747 }
748
749 static int
750 igb_suspend(device_t dev)
751 {
752         struct igb_softc *sc = device_get_softc(dev);
753         struct ifnet *ifp = &sc->arpcom.ac_if;
754
755         ifnet_serialize_all(ifp);
756
757         igb_stop(sc);
758
759         igb_rel_mgmt(sc);
760         igb_rel_hw_control(sc);
761
762         if (sc->wol) {
763                 E1000_WRITE_REG(&sc->hw, E1000_WUC, E1000_WUC_PME_EN);
764                 E1000_WRITE_REG(&sc->hw, E1000_WUFC, sc->wol);
765                 igb_enable_wol(dev);
766         }
767
768         ifnet_deserialize_all(ifp);
769
770         return bus_generic_suspend(dev);
771 }
772
773 static int
774 igb_resume(device_t dev)
775 {
776         struct igb_softc *sc = device_get_softc(dev);
777         struct ifnet *ifp = &sc->arpcom.ac_if;
778         int i;
779
780         ifnet_serialize_all(ifp);
781
782         igb_init(sc);
783         igb_get_mgmt(sc);
784
785         for (i = 0; i < sc->tx_ring_inuse; ++i)
786                 ifsq_devstart_sched(sc->tx_rings[i].ifsq);
787
788         ifnet_deserialize_all(ifp);
789
790         return bus_generic_resume(dev);
791 }
792
793 static int
794 igb_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
795 {
796         struct igb_softc *sc = ifp->if_softc;
797         struct ifreq *ifr = (struct ifreq *)data;
798         int max_frame_size, mask, reinit;
799         int error = 0;
800
801         ASSERT_IFNET_SERIALIZED_ALL(ifp);
802
803         switch (command) {
804         case SIOCSIFMTU:
805                 max_frame_size = 9234;
806                 if (ifr->ifr_mtu > max_frame_size - ETHER_HDR_LEN -
807                     ETHER_CRC_LEN) {
808                         error = EINVAL;
809                         break;
810                 }
811
812                 ifp->if_mtu = ifr->ifr_mtu;
813                 sc->max_frame_size = ifp->if_mtu + ETHER_HDR_LEN +
814                     ETHER_CRC_LEN;
815
816                 if (ifp->if_flags & IFF_RUNNING)
817                         igb_init(sc);
818                 break;
819
820         case SIOCSIFFLAGS:
821                 if (ifp->if_flags & IFF_UP) {
822                         if (ifp->if_flags & IFF_RUNNING) {
823                                 if ((ifp->if_flags ^ sc->if_flags) &
824                                     (IFF_PROMISC | IFF_ALLMULTI)) {
825                                         igb_disable_promisc(sc);
826                                         igb_set_promisc(sc);
827                                 }
828                         } else {
829                                 igb_init(sc);
830                         }
831                 } else if (ifp->if_flags & IFF_RUNNING) {
832                         igb_stop(sc);
833                 }
834                 sc->if_flags = ifp->if_flags;
835                 break;
836
837         case SIOCADDMULTI:
838         case SIOCDELMULTI:
839                 if (ifp->if_flags & IFF_RUNNING) {
840                         igb_disable_intr(sc);
841                         igb_set_multi(sc);
842 #ifdef IFPOLL_ENABLE
843                         if (!(ifp->if_flags & IFF_NPOLLING))
844 #endif
845                                 igb_enable_intr(sc);
846                 }
847                 break;
848
849         case SIOCSIFMEDIA:
850                 /*
851                  * As the speed/duplex settings are being
852                  * changed, we need toreset the PHY.
853                  */
854                 sc->hw.phy.reset_disable = FALSE;
855
856                 /* Check SOL/IDER usage */
857                 if (e1000_check_reset_block(&sc->hw)) {
858                         if_printf(ifp, "Media change is "
859                             "blocked due to SOL/IDER session.\n");
860                         break;
861                 }
862                 /* FALL THROUGH */
863
864         case SIOCGIFMEDIA:
865                 error = ifmedia_ioctl(ifp, ifr, &sc->media, command);
866                 break;
867
868         case SIOCSIFCAP:
869                 reinit = 0;
870                 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
871                 if (mask & IFCAP_RXCSUM) {
872                         ifp->if_capenable ^= IFCAP_RXCSUM;
873                         reinit = 1;
874                 }
875                 if (mask & IFCAP_VLAN_HWTAGGING) {
876                         ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
877                         reinit = 1;
878                 }
879                 if (mask & IFCAP_TXCSUM) {
880                         ifp->if_capenable ^= IFCAP_TXCSUM;
881                         if (ifp->if_capenable & IFCAP_TXCSUM)
882                                 ifp->if_hwassist |= IGB_CSUM_FEATURES;
883                         else
884                                 ifp->if_hwassist &= ~IGB_CSUM_FEATURES;
885                 }
886                 if (mask & IFCAP_TSO) {
887                         ifp->if_capenable ^= IFCAP_TSO;
888                         if (ifp->if_capenable & IFCAP_TSO)
889                                 ifp->if_hwassist |= CSUM_TSO;
890                         else
891                                 ifp->if_hwassist &= ~CSUM_TSO;
892                 }
893                 if (mask & IFCAP_RSS)
894                         ifp->if_capenable ^= IFCAP_RSS;
895                 if (reinit && (ifp->if_flags & IFF_RUNNING))
896                         igb_init(sc);
897                 break;
898
899         default:
900                 error = ether_ioctl(ifp, command, data);
901                 break;
902         }
903         return error;
904 }
905
906 static void
907 igb_init(void *xsc)
908 {
909         struct igb_softc *sc = xsc;
910         struct ifnet *ifp = &sc->arpcom.ac_if;
911         boolean_t polling;
912         int i;
913
914         ASSERT_IFNET_SERIALIZED_ALL(ifp);
915
916         igb_stop(sc);
917
918         /* Get the latest mac address, User can use a LAA */
919         bcopy(IF_LLADDR(ifp), sc->hw.mac.addr, ETHER_ADDR_LEN);
920
921         /* Put the address into the Receive Address Array */
922         e1000_rar_set(&sc->hw, sc->hw.mac.addr, 0);
923
924         igb_reset(sc);
925         igb_update_link_status(sc);
926
927         E1000_WRITE_REG(&sc->hw, E1000_VET, ETHERTYPE_VLAN);
928
929         /* Configure for OS presence */
930         igb_get_mgmt(sc);
931
932         polling = FALSE;
933 #ifdef IFPOLL_ENABLE
934         if (ifp->if_flags & IFF_NPOLLING)
935                 polling = TRUE;
936 #endif
937
938         /* Configured used RX/TX rings */
939         igb_set_ring_inuse(sc, polling);
940
941         /* Initialize interrupt */
942         igb_init_intr(sc);
943
944         /* Prepare transmit descriptors and buffers */
945         for (i = 0; i < sc->tx_ring_inuse; ++i)
946                 igb_init_tx_ring(&sc->tx_rings[i]);
947         igb_init_tx_unit(sc);
948
949         /* Setup Multicast table */
950         igb_set_multi(sc);
951
952 #if 0
953         /*
954          * Figure out the desired mbuf pool
955          * for doing jumbo/packetsplit
956          */
957         if (adapter->max_frame_size <= 2048)
958                 adapter->rx_mbuf_sz = MCLBYTES;
959         else if (adapter->max_frame_size <= 4096)
960                 adapter->rx_mbuf_sz = MJUMPAGESIZE;
961         else
962                 adapter->rx_mbuf_sz = MJUM9BYTES;
963 #endif
964
965         /* Prepare receive descriptors and buffers */
966         for (i = 0; i < sc->rx_ring_inuse; ++i) {
967                 int error;
968
969                 error = igb_init_rx_ring(&sc->rx_rings[i]);
970                 if (error) {
971                         if_printf(ifp, "Could not setup receive structures\n");
972                         igb_stop(sc);
973                         return;
974                 }
975         }
976         igb_init_rx_unit(sc);
977
978         /* Enable VLAN support */
979         if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING)
980                 igb_set_vlan(sc);
981
982         /* Don't lose promiscuous settings */
983         igb_set_promisc(sc);
984
985         ifp->if_flags |= IFF_RUNNING;
986         for (i = 0; i < sc->tx_ring_inuse; ++i) {
987                 ifsq_clr_oactive(sc->tx_rings[i].ifsq);
988                 ifsq_watchdog_start(&sc->tx_rings[i].tx_watchdog);
989         }
990
991         if (polling || sc->intr_type == PCI_INTR_TYPE_MSIX)
992                 sc->timer_cpuid = 0; /* XXX fixed */
993         else
994                 sc->timer_cpuid = rman_get_cpuid(sc->intr_res);
995         callout_reset_bycpu(&sc->timer, hz, igb_timer, sc, sc->timer_cpuid);
996         e1000_clear_hw_cntrs_base_generic(&sc->hw);
997
998         /* This clears any pending interrupts */
999         E1000_READ_REG(&sc->hw, E1000_ICR);
1000
1001         /*
1002          * Only enable interrupts if we are not polling, make sure
1003          * they are off otherwise.
1004          */
1005         if (polling) {
1006                 igb_disable_intr(sc);
1007         } else {
1008                 igb_enable_intr(sc);
1009                 E1000_WRITE_REG(&sc->hw, E1000_ICS, E1000_ICS_LSC);
1010         }
1011
1012         /* Set Energy Efficient Ethernet */
1013         e1000_set_eee_i350(&sc->hw);
1014
1015         /* Don't reset the phy next time init gets called */
1016         sc->hw.phy.reset_disable = TRUE;
1017 }
1018
1019 static void
1020 igb_media_status(struct ifnet *ifp, struct ifmediareq *ifmr)
1021 {
1022         struct igb_softc *sc = ifp->if_softc;
1023         u_char fiber_type = IFM_1000_SX;
1024
1025         ASSERT_IFNET_SERIALIZED_ALL(ifp);
1026
1027         igb_update_link_status(sc);
1028
1029         ifmr->ifm_status = IFM_AVALID;
1030         ifmr->ifm_active = IFM_ETHER;
1031
1032         if (!sc->link_active)
1033                 return;
1034
1035         ifmr->ifm_status |= IFM_ACTIVE;
1036
1037         if (sc->hw.phy.media_type == e1000_media_type_fiber ||
1038             sc->hw.phy.media_type == e1000_media_type_internal_serdes) {
1039                 ifmr->ifm_active |= fiber_type | IFM_FDX;
1040         } else {
1041                 switch (sc->link_speed) {
1042                 case 10:
1043                         ifmr->ifm_active |= IFM_10_T;
1044                         break;
1045
1046                 case 100:
1047                         ifmr->ifm_active |= IFM_100_TX;
1048                         break;
1049
1050                 case 1000:
1051                         ifmr->ifm_active |= IFM_1000_T;
1052                         break;
1053                 }
1054                 if (sc->link_duplex == FULL_DUPLEX)
1055                         ifmr->ifm_active |= IFM_FDX;
1056                 else
1057                         ifmr->ifm_active |= IFM_HDX;
1058         }
1059 }
1060
1061 static int
1062 igb_media_change(struct ifnet *ifp)
1063 {
1064         struct igb_softc *sc = ifp->if_softc;
1065         struct ifmedia *ifm = &sc->media;
1066
1067         ASSERT_IFNET_SERIALIZED_ALL(ifp);
1068
1069         if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
1070                 return EINVAL;
1071
1072         switch (IFM_SUBTYPE(ifm->ifm_media)) {
1073         case IFM_AUTO:
1074                 sc->hw.mac.autoneg = DO_AUTO_NEG;
1075                 sc->hw.phy.autoneg_advertised = AUTONEG_ADV_DEFAULT;
1076                 break;
1077
1078         case IFM_1000_LX:
1079         case IFM_1000_SX:
1080         case IFM_1000_T:
1081                 sc->hw.mac.autoneg = DO_AUTO_NEG;
1082                 sc->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
1083                 break;
1084
1085         case IFM_100_TX:
1086                 sc->hw.mac.autoneg = FALSE;
1087                 sc->hw.phy.autoneg_advertised = 0;
1088                 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
1089                         sc->hw.mac.forced_speed_duplex = ADVERTISE_100_FULL;
1090                 else
1091                         sc->hw.mac.forced_speed_duplex = ADVERTISE_100_HALF;
1092                 break;
1093
1094         case IFM_10_T:
1095                 sc->hw.mac.autoneg = FALSE;
1096                 sc->hw.phy.autoneg_advertised = 0;
1097                 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
1098                         sc->hw.mac.forced_speed_duplex = ADVERTISE_10_FULL;
1099                 else
1100                         sc->hw.mac.forced_speed_duplex = ADVERTISE_10_HALF;
1101                 break;
1102
1103         default:
1104                 if_printf(ifp, "Unsupported media type\n");
1105                 break;
1106         }
1107
1108         igb_init(sc);
1109
1110         return 0;
1111 }
1112
1113 static void
1114 igb_set_promisc(struct igb_softc *sc)
1115 {
1116         struct ifnet *ifp = &sc->arpcom.ac_if;
1117         struct e1000_hw *hw = &sc->hw;
1118         uint32_t reg;
1119
1120         if (sc->vf_ifp) {
1121                 e1000_promisc_set_vf(hw, e1000_promisc_enabled);
1122                 return;
1123         }
1124
1125         reg = E1000_READ_REG(hw, E1000_RCTL);
1126         if (ifp->if_flags & IFF_PROMISC) {
1127                 reg |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
1128                 E1000_WRITE_REG(hw, E1000_RCTL, reg);
1129         } else if (ifp->if_flags & IFF_ALLMULTI) {
1130                 reg |= E1000_RCTL_MPE;
1131                 reg &= ~E1000_RCTL_UPE;
1132                 E1000_WRITE_REG(hw, E1000_RCTL, reg);
1133         }
1134 }
1135
1136 static void
1137 igb_disable_promisc(struct igb_softc *sc)
1138 {
1139         struct e1000_hw *hw = &sc->hw;
1140         uint32_t reg;
1141
1142         if (sc->vf_ifp) {
1143                 e1000_promisc_set_vf(hw, e1000_promisc_disabled);
1144                 return;
1145         }
1146         reg = E1000_READ_REG(hw, E1000_RCTL);
1147         reg &= ~E1000_RCTL_UPE;
1148         reg &= ~E1000_RCTL_MPE;
1149         E1000_WRITE_REG(hw, E1000_RCTL, reg);
1150 }
1151
1152 static void
1153 igb_set_multi(struct igb_softc *sc)
1154 {
1155         struct ifnet *ifp = &sc->arpcom.ac_if;
1156         struct ifmultiaddr *ifma;
1157         uint32_t reg_rctl = 0;
1158         uint8_t *mta;
1159         int mcnt = 0;
1160
1161         mta = sc->mta;
1162         bzero(mta, ETH_ADDR_LEN * MAX_NUM_MULTICAST_ADDRESSES);
1163
1164         TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1165                 if (ifma->ifma_addr->sa_family != AF_LINK)
1166                         continue;
1167
1168                 if (mcnt == MAX_NUM_MULTICAST_ADDRESSES)
1169                         break;
1170
1171                 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
1172                     &mta[mcnt * ETH_ADDR_LEN], ETH_ADDR_LEN);
1173                 mcnt++;
1174         }
1175
1176         if (mcnt >= MAX_NUM_MULTICAST_ADDRESSES) {
1177                 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL);
1178                 reg_rctl |= E1000_RCTL_MPE;
1179                 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl);
1180         } else {
1181                 e1000_update_mc_addr_list(&sc->hw, mta, mcnt);
1182         }
1183 }
1184
1185 static void
1186 igb_timer(void *xsc)
1187 {
1188         struct igb_softc *sc = xsc;
1189
1190         lwkt_serialize_enter(&sc->main_serialize);
1191
1192         igb_update_link_status(sc);
1193         igb_update_stats_counters(sc);
1194
1195         callout_reset_bycpu(&sc->timer, hz, igb_timer, sc, sc->timer_cpuid);
1196
1197         lwkt_serialize_exit(&sc->main_serialize);
1198 }
1199
1200 static void
1201 igb_update_link_status(struct igb_softc *sc)
1202 {
1203         struct ifnet *ifp = &sc->arpcom.ac_if;
1204         struct e1000_hw *hw = &sc->hw;
1205         uint32_t link_check, thstat, ctrl;
1206
1207         link_check = thstat = ctrl = 0;
1208
1209         /* Get the cached link value or read for real */
1210         switch (hw->phy.media_type) {
1211         case e1000_media_type_copper:
1212                 if (hw->mac.get_link_status) {
1213                         /* Do the work to read phy */
1214                         e1000_check_for_link(hw);
1215                         link_check = !hw->mac.get_link_status;
1216                 } else {
1217                         link_check = TRUE;
1218                 }
1219                 break;
1220
1221         case e1000_media_type_fiber:
1222                 e1000_check_for_link(hw);
1223                 link_check = E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU;
1224                 break;
1225
1226         case e1000_media_type_internal_serdes:
1227                 e1000_check_for_link(hw);
1228                 link_check = hw->mac.serdes_has_link;
1229                 break;
1230
1231         /* VF device is type_unknown */
1232         case e1000_media_type_unknown:
1233                 e1000_check_for_link(hw);
1234                 link_check = !hw->mac.get_link_status;
1235                 /* Fall thru */
1236         default:
1237                 break;
1238         }
1239
1240         /* Check for thermal downshift or shutdown */
1241         if (hw->mac.type == e1000_i350) {
1242                 thstat = E1000_READ_REG(hw, E1000_THSTAT);
1243                 ctrl = E1000_READ_REG(hw, E1000_CTRL_EXT);
1244         }
1245
1246         /* Now we check if a transition has happened */
1247         if (link_check && sc->link_active == 0) {
1248                 e1000_get_speed_and_duplex(hw, 
1249                     &sc->link_speed, &sc->link_duplex);
1250                 if (bootverbose) {
1251                         if_printf(ifp, "Link is up %d Mbps %s\n",
1252                             sc->link_speed,
1253                             sc->link_duplex == FULL_DUPLEX ?
1254                             "Full Duplex" : "Half Duplex");
1255                 }
1256                 sc->link_active = 1;
1257
1258                 ifp->if_baudrate = sc->link_speed * 1000000;
1259                 if ((ctrl & E1000_CTRL_EXT_LINK_MODE_GMII) &&
1260                     (thstat & E1000_THSTAT_LINK_THROTTLE))
1261                         if_printf(ifp, "Link: thermal downshift\n");
1262                 /* This can sleep */
1263                 ifp->if_link_state = LINK_STATE_UP;
1264                 if_link_state_change(ifp);
1265         } else if (!link_check && sc->link_active == 1) {
1266                 ifp->if_baudrate = sc->link_speed = 0;
1267                 sc->link_duplex = 0;
1268                 if (bootverbose)
1269                         if_printf(ifp, "Link is Down\n");
1270                 if ((ctrl & E1000_CTRL_EXT_LINK_MODE_GMII) &&
1271                     (thstat & E1000_THSTAT_PWR_DOWN))
1272                         if_printf(ifp, "Link: thermal shutdown\n");
1273                 sc->link_active = 0;
1274                 /* This can sleep */
1275                 ifp->if_link_state = LINK_STATE_DOWN;
1276                 if_link_state_change(ifp);
1277         }
1278 }
1279
1280 static void
1281 igb_stop(struct igb_softc *sc)
1282 {
1283         struct ifnet *ifp = &sc->arpcom.ac_if;
1284         int i;
1285
1286         ASSERT_IFNET_SERIALIZED_ALL(ifp);
1287
1288         igb_disable_intr(sc);
1289
1290         callout_stop(&sc->timer);
1291
1292         ifp->if_flags &= ~IFF_RUNNING;
1293         for (i = 0; i < sc->tx_ring_cnt; ++i) {
1294                 ifsq_clr_oactive(sc->tx_rings[i].ifsq);
1295                 ifsq_watchdog_stop(&sc->tx_rings[i].tx_watchdog);
1296                 sc->tx_rings[i].tx_flags &= ~IGB_TXFLAG_ENABLED;
1297         }
1298
1299         e1000_reset_hw(&sc->hw);
1300         E1000_WRITE_REG(&sc->hw, E1000_WUC, 0);
1301
1302         e1000_led_off(&sc->hw);
1303         e1000_cleanup_led(&sc->hw);
1304
1305         for (i = 0; i < sc->tx_ring_cnt; ++i)
1306                 igb_free_tx_ring(&sc->tx_rings[i]);
1307         for (i = 0; i < sc->rx_ring_cnt; ++i)
1308                 igb_free_rx_ring(&sc->rx_rings[i]);
1309 }
1310
1311 static void
1312 igb_reset(struct igb_softc *sc)
1313 {
1314         struct ifnet *ifp = &sc->arpcom.ac_if;
1315         struct e1000_hw *hw = &sc->hw;
1316         struct e1000_fc_info *fc = &hw->fc;
1317         uint32_t pba = 0;
1318         uint16_t hwm;
1319
1320         /* Let the firmware know the OS is in control */
1321         igb_get_hw_control(sc);
1322
1323         /*
1324          * Packet Buffer Allocation (PBA)
1325          * Writing PBA sets the receive portion of the buffer
1326          * the remainder is used for the transmit buffer.
1327          */
1328         switch (hw->mac.type) {
1329         case e1000_82575:
1330                 pba = E1000_PBA_32K;
1331                 break;
1332
1333         case e1000_82576:
1334         case e1000_vfadapt:
1335                 pba = E1000_READ_REG(hw, E1000_RXPBS);
1336                 pba &= E1000_RXPBS_SIZE_MASK_82576;
1337                 break;
1338
1339         case e1000_82580:
1340         case e1000_i350:
1341         case e1000_vfadapt_i350:
1342                 pba = E1000_READ_REG(hw, E1000_RXPBS);
1343                 pba = e1000_rxpbs_adjust_82580(pba);
1344                 break;
1345                 /* XXX pba = E1000_PBA_35K; */
1346
1347         default:
1348                 break;
1349         }
1350
1351         /* Special needs in case of Jumbo frames */
1352         if (hw->mac.type == e1000_82575 && ifp->if_mtu > ETHERMTU) {
1353                 uint32_t tx_space, min_tx, min_rx;
1354
1355                 pba = E1000_READ_REG(hw, E1000_PBA);
1356                 tx_space = pba >> 16;
1357                 pba &= 0xffff;
1358
1359                 min_tx = (sc->max_frame_size +
1360                     sizeof(struct e1000_tx_desc) - ETHER_CRC_LEN) * 2;
1361                 min_tx = roundup2(min_tx, 1024);
1362                 min_tx >>= 10;
1363                 min_rx = sc->max_frame_size;
1364                 min_rx = roundup2(min_rx, 1024);
1365                 min_rx >>= 10;
1366                 if (tx_space < min_tx && (min_tx - tx_space) < pba) {
1367                         pba = pba - (min_tx - tx_space);
1368                         /*
1369                          * if short on rx space, rx wins
1370                          * and must trump tx adjustment
1371                          */
1372                         if (pba < min_rx)
1373                                 pba = min_rx;
1374                 }
1375                 E1000_WRITE_REG(hw, E1000_PBA, pba);
1376         }
1377
1378         /*
1379          * These parameters control the automatic generation (Tx) and
1380          * response (Rx) to Ethernet PAUSE frames.
1381          * - High water mark should allow for at least two frames to be
1382          *   received after sending an XOFF.
1383          * - Low water mark works best when it is very near the high water mark.
1384          *   This allows the receiver to restart by sending XON when it has
1385          *   drained a bit.
1386          */
1387         hwm = min(((pba << 10) * 9 / 10),
1388             ((pba << 10) - 2 * sc->max_frame_size));
1389
1390         if (hw->mac.type < e1000_82576) {
1391                 fc->high_water = hwm & 0xFFF8; /* 8-byte granularity */
1392                 fc->low_water = fc->high_water - 8;
1393         } else {
1394                 fc->high_water = hwm & 0xFFF0; /* 16-byte granularity */
1395                 fc->low_water = fc->high_water - 16;
1396         }
1397         fc->pause_time = IGB_FC_PAUSE_TIME;
1398         fc->send_xon = TRUE;
1399
1400         /* Issue a global reset */
1401         e1000_reset_hw(hw);
1402         E1000_WRITE_REG(hw, E1000_WUC, 0);
1403
1404         if (e1000_init_hw(hw) < 0)
1405                 if_printf(ifp, "Hardware Initialization Failed\n");
1406
1407         /* Setup DMA Coalescing */
1408         if (hw->mac.type == e1000_i350 && sc->dma_coalesce) {
1409                 uint32_t reg;
1410
1411                 hwm = (pba - 4) << 10;
1412                 reg = ((pba - 6) << E1000_DMACR_DMACTHR_SHIFT)
1413                     & E1000_DMACR_DMACTHR_MASK;
1414
1415                 /* transition to L0x or L1 if available..*/
1416                 reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK);
1417
1418                 /* timer = +-1000 usec in 32usec intervals */
1419                 reg |= (1000 >> 5);
1420                 E1000_WRITE_REG(hw, E1000_DMACR, reg);
1421
1422                 /* No lower threshold */
1423                 E1000_WRITE_REG(hw, E1000_DMCRTRH, 0);
1424
1425                 /* set hwm to PBA -  2 * max frame size */
1426                 E1000_WRITE_REG(hw, E1000_FCRTC, hwm);
1427
1428                 /* Set the interval before transition */
1429                 reg = E1000_READ_REG(hw, E1000_DMCTLX);
1430                 reg |= 0x800000FF; /* 255 usec */
1431                 E1000_WRITE_REG(hw, E1000_DMCTLX, reg);
1432
1433                 /* free space in tx packet buffer to wake from DMA coal */
1434                 E1000_WRITE_REG(hw, E1000_DMCTXTH,
1435                     (20480 - (2 * sc->max_frame_size)) >> 6);
1436
1437                 /* make low power state decision controlled by DMA coal */
1438                 reg = E1000_READ_REG(hw, E1000_PCIEMISC);
1439                 E1000_WRITE_REG(hw, E1000_PCIEMISC,
1440                     reg | E1000_PCIEMISC_LX_DECISION);
1441                 if_printf(ifp, "DMA Coalescing enabled\n");
1442         }
1443
1444         E1000_WRITE_REG(&sc->hw, E1000_VET, ETHERTYPE_VLAN);
1445         e1000_get_phy_info(hw);
1446         e1000_check_for_link(hw);
1447 }
1448
1449 static void
1450 igb_setup_ifp(struct igb_softc *sc)
1451 {
1452         struct ifnet *ifp = &sc->arpcom.ac_if;
1453
1454         ifp->if_softc = sc;
1455         ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1456         ifp->if_init = igb_init;
1457         ifp->if_ioctl = igb_ioctl;
1458         ifp->if_start = igb_start;
1459         ifp->if_serialize = igb_serialize;
1460         ifp->if_deserialize = igb_deserialize;
1461         ifp->if_tryserialize = igb_tryserialize;
1462 #ifdef INVARIANTS
1463         ifp->if_serialize_assert = igb_serialize_assert;
1464 #endif
1465 #ifdef IFPOLL_ENABLE
1466         ifp->if_npoll = igb_npoll;
1467 #endif
1468
1469         ifq_set_maxlen(&ifp->if_snd, sc->tx_rings[0].num_tx_desc - 1);
1470         ifq_set_ready(&ifp->if_snd);
1471
1472         ether_ifattach(ifp, sc->hw.mac.addr, NULL);
1473
1474         ifp->if_capabilities =
1475             IFCAP_HWCSUM | IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU | IFCAP_TSO;
1476         if (IGB_ENABLE_HWRSS(sc))
1477                 ifp->if_capabilities |= IFCAP_RSS;
1478         ifp->if_capenable = ifp->if_capabilities;
1479         ifp->if_hwassist = IGB_CSUM_FEATURES | CSUM_TSO;
1480
1481         /*
1482          * Tell the upper layer(s) we support long frames
1483          */
1484         ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
1485
1486         /*
1487          * Specify the media types supported by this adapter and register
1488          * callbacks to update media and link information
1489          */
1490         ifmedia_init(&sc->media, IFM_IMASK, igb_media_change, igb_media_status);
1491         if (sc->hw.phy.media_type == e1000_media_type_fiber ||
1492             sc->hw.phy.media_type == e1000_media_type_internal_serdes) {
1493                 ifmedia_add(&sc->media, IFM_ETHER | IFM_1000_SX | IFM_FDX,
1494                     0, NULL);
1495                 ifmedia_add(&sc->media, IFM_ETHER | IFM_1000_SX, 0, NULL);
1496         } else {
1497                 ifmedia_add(&sc->media, IFM_ETHER | IFM_10_T, 0, NULL);
1498                 ifmedia_add(&sc->media, IFM_ETHER | IFM_10_T | IFM_FDX,
1499                     0, NULL);
1500                 ifmedia_add(&sc->media, IFM_ETHER | IFM_100_TX, 0, NULL);
1501                 ifmedia_add(&sc->media, IFM_ETHER | IFM_100_TX | IFM_FDX,
1502                     0, NULL);
1503                 if (sc->hw.phy.type != e1000_phy_ife) {
1504                         ifmedia_add(&sc->media,
1505                             IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL);
1506                         ifmedia_add(&sc->media,
1507                             IFM_ETHER | IFM_1000_T, 0, NULL);
1508                 }
1509         }
1510         ifmedia_add(&sc->media, IFM_ETHER | IFM_AUTO, 0, NULL);
1511         ifmedia_set(&sc->media, IFM_ETHER | IFM_AUTO);
1512 }
1513
1514 static void
1515 igb_add_sysctl(struct igb_softc *sc)
1516 {
1517         char node[32];
1518         int i;
1519
1520         sysctl_ctx_init(&sc->sysctl_ctx);
1521         sc->sysctl_tree = SYSCTL_ADD_NODE(&sc->sysctl_ctx,
1522             SYSCTL_STATIC_CHILDREN(_hw), OID_AUTO,
1523             device_get_nameunit(sc->dev), CTLFLAG_RD, 0, "");
1524         if (sc->sysctl_tree == NULL) {
1525                 device_printf(sc->dev, "can't add sysctl node\n");
1526                 return;
1527         }
1528
1529         SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1530             OID_AUTO, "rxr", CTLFLAG_RD, &sc->rx_ring_cnt, 0, "# of RX rings");
1531         SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1532             OID_AUTO, "rxr_inuse", CTLFLAG_RD, &sc->rx_ring_inuse, 0,
1533             "# of RX rings used");
1534         SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1535             OID_AUTO, "txr", CTLFLAG_RD, &sc->tx_ring_cnt, 0, "# of TX rings");
1536         SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1537             OID_AUTO, "txr_inuse", CTLFLAG_RD, &sc->tx_ring_inuse, 0,
1538             "# of TX rings used");
1539         SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1540             OID_AUTO, "rxd", CTLFLAG_RD, &sc->rx_rings[0].num_rx_desc, 0,
1541             "# of RX descs");
1542         SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1543             OID_AUTO, "txd", CTLFLAG_RD, &sc->tx_rings[0].num_tx_desc, 0,
1544             "# of TX descs");
1545
1546         if (sc->intr_type != PCI_INTR_TYPE_MSIX) {
1547                 SYSCTL_ADD_PROC(&sc->sysctl_ctx,
1548                     SYSCTL_CHILDREN(sc->sysctl_tree),
1549                     OID_AUTO, "intr_rate", CTLTYPE_INT | CTLFLAG_RW,
1550                     sc, 0, igb_sysctl_intr_rate, "I", "interrupt rate");
1551         } else {
1552                 for (i = 0; i < sc->msix_cnt; ++i) {
1553                         struct igb_msix_data *msix = &sc->msix_data[i];
1554
1555                         ksnprintf(node, sizeof(node), "msix%d_rate", i);
1556                         SYSCTL_ADD_PROC(&sc->sysctl_ctx,
1557                             SYSCTL_CHILDREN(sc->sysctl_tree),
1558                             OID_AUTO, node, CTLTYPE_INT | CTLFLAG_RW,
1559                             msix, 0, igb_sysctl_msix_rate, "I",
1560                             msix->msix_rate_desc);
1561                 }
1562         }
1563
1564         SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1565             OID_AUTO, "tx_intr_nsegs", CTLTYPE_INT | CTLFLAG_RW,
1566             sc, 0, igb_sysctl_tx_intr_nsegs, "I",
1567             "# of segments per TX interrupt");
1568
1569         SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1570             OID_AUTO, "tx_wreg_nsegs", CTLTYPE_INT | CTLFLAG_RW,
1571             sc, 0, igb_sysctl_tx_wreg_nsegs, "I",
1572             "# of segments sent before write to hardware register");
1573
1574         SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1575             OID_AUTO, "rx_wreg_nsegs", CTLTYPE_INT | CTLFLAG_RW,
1576             sc, 0, igb_sysctl_rx_wreg_nsegs, "I",
1577             "# of segments received before write to hardware register");
1578
1579 #ifdef IFPOLL_ENABLE
1580         SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1581             OID_AUTO, "npoll_rxoff", CTLTYPE_INT|CTLFLAG_RW,
1582             sc, 0, igb_sysctl_npoll_rxoff, "I", "NPOLLING RX cpu offset");
1583         SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1584             OID_AUTO, "npoll_txoff", CTLTYPE_INT|CTLFLAG_RW,
1585             sc, 0, igb_sysctl_npoll_txoff, "I", "NPOLLING TX cpu offset");
1586 #endif
1587
1588 #ifdef IGB_RSS_DEBUG
1589         SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1590             OID_AUTO, "rss_debug", CTLFLAG_RW, &sc->rss_debug, 0,
1591             "RSS debug level");
1592         for (i = 0; i < sc->rx_ring_cnt; ++i) {
1593                 ksnprintf(node, sizeof(node), "rx%d_pkt", i);
1594                 SYSCTL_ADD_ULONG(&sc->sysctl_ctx,
1595                     SYSCTL_CHILDREN(sc->sysctl_tree), OID_AUTO, node,
1596                     CTLFLAG_RW, &sc->rx_rings[i].rx_packets, "RXed packets");
1597         }
1598 #endif
1599 }
1600
1601 static int
1602 igb_alloc_rings(struct igb_softc *sc)
1603 {
1604         int error, i;
1605
1606         /*
1607          * Create top level busdma tag
1608          */
1609         error = bus_dma_tag_create(NULL, 1, 0,
1610             BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL,
1611             BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 0,
1612             &sc->parent_tag);
1613         if (error) {
1614                 device_printf(sc->dev, "could not create top level DMA tag\n");
1615                 return error;
1616         }
1617
1618         /*
1619          * Allocate TX descriptor rings and buffers
1620          */
1621         sc->tx_rings = kmalloc_cachealign(
1622             sizeof(struct igb_tx_ring) * sc->tx_ring_cnt,
1623             M_DEVBUF, M_WAITOK | M_ZERO);
1624         for (i = 0; i < sc->tx_ring_cnt; ++i) {
1625                 struct igb_tx_ring *txr = &sc->tx_rings[i];
1626
1627                 /* Set up some basics */
1628                 txr->sc = sc;
1629                 txr->me = i;
1630                 lwkt_serialize_init(&txr->tx_serialize);
1631
1632                 error = igb_create_tx_ring(txr);
1633                 if (error)
1634                         return error;
1635         }
1636
1637         /*
1638          * Allocate RX descriptor rings and buffers
1639          */ 
1640         sc->rx_rings = kmalloc_cachealign(
1641             sizeof(struct igb_rx_ring) * sc->rx_ring_cnt,
1642             M_DEVBUF, M_WAITOK | M_ZERO);
1643         for (i = 0; i < sc->rx_ring_cnt; ++i) {
1644                 struct igb_rx_ring *rxr = &sc->rx_rings[i];
1645
1646                 /* Set up some basics */
1647                 rxr->sc = sc;
1648                 rxr->me = i;
1649                 lwkt_serialize_init(&rxr->rx_serialize);
1650
1651                 error = igb_create_rx_ring(rxr);
1652                 if (error)
1653                         return error;
1654         }
1655
1656         return 0;
1657 }
1658
1659 static void
1660 igb_free_rings(struct igb_softc *sc)
1661 {
1662         int i;
1663
1664         if (sc->tx_rings != NULL) {
1665                 for (i = 0; i < sc->tx_ring_cnt; ++i) {
1666                         struct igb_tx_ring *txr = &sc->tx_rings[i];
1667
1668                         igb_destroy_tx_ring(txr, txr->num_tx_desc);
1669                 }
1670                 kfree(sc->tx_rings, M_DEVBUF);
1671         }
1672
1673         if (sc->rx_rings != NULL) {
1674                 for (i = 0; i < sc->rx_ring_cnt; ++i) {
1675                         struct igb_rx_ring *rxr = &sc->rx_rings[i];
1676
1677                         igb_destroy_rx_ring(rxr, rxr->num_rx_desc);
1678                 }
1679                 kfree(sc->rx_rings, M_DEVBUF);
1680         }
1681 }
1682
1683 static int
1684 igb_create_tx_ring(struct igb_tx_ring *txr)
1685 {
1686         int tsize, error, i, ntxd;
1687
1688         /*
1689          * Validate number of transmit descriptors. It must not exceed
1690          * hardware maximum, and must be multiple of IGB_DBA_ALIGN.
1691          */
1692         ntxd = device_getenv_int(txr->sc->dev, "txd", igb_txd);
1693         if ((ntxd * sizeof(struct e1000_tx_desc)) % IGB_DBA_ALIGN != 0 ||
1694             ntxd > IGB_MAX_TXD || ntxd < IGB_MIN_TXD) {
1695                 device_printf(txr->sc->dev,
1696                     "Using %d TX descriptors instead of %d!\n",
1697                     IGB_DEFAULT_TXD, ntxd);
1698                 txr->num_tx_desc = IGB_DEFAULT_TXD;
1699         } else {
1700                 txr->num_tx_desc = ntxd;
1701         }
1702
1703         /*
1704          * Allocate TX descriptor ring
1705          */
1706         tsize = roundup2(txr->num_tx_desc * sizeof(union e1000_adv_tx_desc),
1707             IGB_DBA_ALIGN);
1708         txr->txdma.dma_vaddr = bus_dmamem_coherent_any(txr->sc->parent_tag,
1709             IGB_DBA_ALIGN, tsize, BUS_DMA_WAITOK,
1710             &txr->txdma.dma_tag, &txr->txdma.dma_map, &txr->txdma.dma_paddr);
1711         if (txr->txdma.dma_vaddr == NULL) {
1712                 device_printf(txr->sc->dev,
1713                     "Unable to allocate TX Descriptor memory\n");
1714                 return ENOMEM;
1715         }
1716         txr->tx_base = txr->txdma.dma_vaddr;
1717         bzero(txr->tx_base, tsize);
1718
1719         tsize = __VM_CACHELINE_ALIGN(
1720             sizeof(struct igb_tx_buf) * txr->num_tx_desc);
1721         txr->tx_buf = kmalloc_cachealign(tsize, M_DEVBUF, M_WAITOK | M_ZERO);
1722
1723         /*
1724          * Allocate TX head write-back buffer
1725          */
1726         txr->tx_hdr = bus_dmamem_coherent_any(txr->sc->parent_tag,
1727             __VM_CACHELINE_SIZE, __VM_CACHELINE_SIZE, BUS_DMA_WAITOK,
1728             &txr->tx_hdr_dtag, &txr->tx_hdr_dmap, &txr->tx_hdr_paddr);
1729         if (txr->tx_hdr == NULL) {
1730                 device_printf(txr->sc->dev,
1731                     "Unable to allocate TX head write-back buffer\n");
1732                 return ENOMEM;
1733         }
1734
1735         /*
1736          * Create DMA tag for TX buffers
1737          */
1738         error = bus_dma_tag_create(txr->sc->parent_tag,
1739             1, 0,               /* alignment, bounds */
1740             BUS_SPACE_MAXADDR,  /* lowaddr */
1741             BUS_SPACE_MAXADDR,  /* highaddr */
1742             NULL, NULL,         /* filter, filterarg */
1743             IGB_TSO_SIZE,       /* maxsize */
1744             IGB_MAX_SCATTER,    /* nsegments */
1745             PAGE_SIZE,          /* maxsegsize */
1746             BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW |
1747             BUS_DMA_ONEBPAGE,   /* flags */
1748             &txr->tx_tag);
1749         if (error) {
1750                 device_printf(txr->sc->dev, "Unable to allocate TX DMA tag\n");
1751                 kfree(txr->tx_buf, M_DEVBUF);
1752                 txr->tx_buf = NULL;
1753                 return error;
1754         }
1755
1756         /*
1757          * Create DMA maps for TX buffers
1758          */
1759         for (i = 0; i < txr->num_tx_desc; ++i) {
1760                 struct igb_tx_buf *txbuf = &txr->tx_buf[i];
1761
1762                 error = bus_dmamap_create(txr->tx_tag,
1763                     BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE, &txbuf->map);
1764                 if (error) {
1765                         device_printf(txr->sc->dev,
1766                             "Unable to create TX DMA map\n");
1767                         igb_destroy_tx_ring(txr, i);
1768                         return error;
1769                 }
1770         }
1771
1772         if (txr->sc->hw.mac.type == e1000_82575)
1773                 txr->tx_flags |= IGB_TXFLAG_TSO_IPLEN0;
1774
1775         /*
1776          * Initialize various watermark
1777          */
1778         txr->spare_desc = IGB_TX_SPARE;
1779         txr->intr_nsegs = txr->num_tx_desc / 16;
1780         txr->wreg_nsegs = IGB_DEF_TXWREG_NSEGS;
1781         txr->oact_hi_desc = txr->num_tx_desc / 2;
1782         txr->oact_lo_desc = txr->num_tx_desc / 8;
1783         if (txr->oact_lo_desc > IGB_TX_OACTIVE_MAX)
1784                 txr->oact_lo_desc = IGB_TX_OACTIVE_MAX;
1785         if (txr->oact_lo_desc < txr->spare_desc + IGB_TX_RESERVED)
1786                 txr->oact_lo_desc = txr->spare_desc + IGB_TX_RESERVED;
1787
1788         return 0;
1789 }
1790
1791 static void
1792 igb_free_tx_ring(struct igb_tx_ring *txr)
1793 {
1794         int i;
1795
1796         for (i = 0; i < txr->num_tx_desc; ++i) {
1797                 struct igb_tx_buf *txbuf = &txr->tx_buf[i];
1798
1799                 if (txbuf->m_head != NULL) {
1800                         bus_dmamap_unload(txr->tx_tag, txbuf->map);
1801                         m_freem(txbuf->m_head);
1802                         txbuf->m_head = NULL;
1803                 }
1804         }
1805 }
1806
1807 static void
1808 igb_destroy_tx_ring(struct igb_tx_ring *txr, int ndesc)
1809 {
1810         int i;
1811
1812         if (txr->txdma.dma_vaddr != NULL) {
1813                 bus_dmamap_unload(txr->txdma.dma_tag, txr->txdma.dma_map);
1814                 bus_dmamem_free(txr->txdma.dma_tag, txr->txdma.dma_vaddr,
1815                     txr->txdma.dma_map);
1816                 bus_dma_tag_destroy(txr->txdma.dma_tag);
1817                 txr->txdma.dma_vaddr = NULL;
1818         }
1819
1820         if (txr->tx_hdr != NULL) {
1821                 bus_dmamap_unload(txr->tx_hdr_dtag, txr->tx_hdr_dmap);
1822                 bus_dmamem_free(txr->tx_hdr_dtag, txr->tx_hdr,
1823                     txr->tx_hdr_dmap);
1824                 bus_dma_tag_destroy(txr->tx_hdr_dtag);
1825                 txr->tx_hdr = NULL;
1826         }
1827
1828         if (txr->tx_buf == NULL)
1829                 return;
1830
1831         for (i = 0; i < ndesc; ++i) {
1832                 struct igb_tx_buf *txbuf = &txr->tx_buf[i];
1833
1834                 KKASSERT(txbuf->m_head == NULL);
1835                 bus_dmamap_destroy(txr->tx_tag, txbuf->map);
1836         }
1837         bus_dma_tag_destroy(txr->tx_tag);
1838
1839         kfree(txr->tx_buf, M_DEVBUF);
1840         txr->tx_buf = NULL;
1841 }
1842
1843 static void
1844 igb_init_tx_ring(struct igb_tx_ring *txr)
1845 {
1846         /* Clear the old descriptor contents */
1847         bzero(txr->tx_base,
1848             sizeof(union e1000_adv_tx_desc) * txr->num_tx_desc);
1849
1850         /* Clear TX head write-back buffer */
1851         *(txr->tx_hdr) = 0;
1852
1853         /* Reset indices */
1854         txr->next_avail_desc = 0;
1855         txr->next_to_clean = 0;
1856         txr->tx_nsegs = 0;
1857
1858         /* Set number of descriptors available */
1859         txr->tx_avail = txr->num_tx_desc;
1860
1861         /* Enable this TX ring */
1862         txr->tx_flags |= IGB_TXFLAG_ENABLED;
1863 }
1864
1865 static void
1866 igb_init_tx_unit(struct igb_softc *sc)
1867 {
1868         struct e1000_hw *hw = &sc->hw;
1869         uint32_t tctl;
1870         int i;
1871
1872         /* Setup the Tx Descriptor Rings */
1873         for (i = 0; i < sc->tx_ring_inuse; ++i) {
1874                 struct igb_tx_ring *txr = &sc->tx_rings[i];
1875                 uint64_t bus_addr = txr->txdma.dma_paddr;
1876                 uint64_t hdr_paddr = txr->tx_hdr_paddr;
1877                 uint32_t txdctl = 0;
1878                 uint32_t dca_txctrl;
1879
1880                 E1000_WRITE_REG(hw, E1000_TDLEN(i),
1881                     txr->num_tx_desc * sizeof(struct e1000_tx_desc));
1882                 E1000_WRITE_REG(hw, E1000_TDBAH(i),
1883                     (uint32_t)(bus_addr >> 32));
1884                 E1000_WRITE_REG(hw, E1000_TDBAL(i),
1885                     (uint32_t)bus_addr);
1886
1887                 /* Setup the HW Tx Head and Tail descriptor pointers */
1888                 E1000_WRITE_REG(hw, E1000_TDT(i), 0);
1889                 E1000_WRITE_REG(hw, E1000_TDH(i), 0);
1890
1891                 dca_txctrl = E1000_READ_REG(hw, E1000_DCA_TXCTRL(i));
1892                 dca_txctrl &= ~E1000_DCA_TXCTRL_TX_WB_RO_EN;
1893                 E1000_WRITE_REG(hw, E1000_DCA_TXCTRL(i), dca_txctrl);
1894
1895                 /*
1896                  * Don't set WB_on_EITR:
1897                  * - 82575 does not have it
1898                  * - It almost has no effect on 82576, see:
1899                  *   82576 specification update errata #26
1900                  * - It causes unnecessary bus traffic
1901                  */
1902                 E1000_WRITE_REG(hw, E1000_TDWBAH(i),
1903                     (uint32_t)(hdr_paddr >> 32));
1904                 E1000_WRITE_REG(hw, E1000_TDWBAL(i),
1905                     ((uint32_t)hdr_paddr) | E1000_TX_HEAD_WB_ENABLE);
1906
1907                 /*
1908                  * WTHRESH is ignored by the hardware, since header
1909                  * write back mode is used.
1910                  */
1911                 txdctl |= IGB_TX_PTHRESH;
1912                 txdctl |= IGB_TX_HTHRESH << 8;
1913                 txdctl |= IGB_TX_WTHRESH << 16;
1914                 txdctl |= E1000_TXDCTL_QUEUE_ENABLE;
1915                 E1000_WRITE_REG(hw, E1000_TXDCTL(i), txdctl);
1916         }
1917
1918         if (sc->vf_ifp)
1919                 return;
1920
1921         e1000_config_collision_dist(hw);
1922
1923         /* Program the Transmit Control Register */
1924         tctl = E1000_READ_REG(hw, E1000_TCTL);
1925         tctl &= ~E1000_TCTL_CT;
1926         tctl |= (E1000_TCTL_PSP | E1000_TCTL_RTLC | E1000_TCTL_EN |
1927             (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT));
1928
1929         /* This write will effectively turn on the transmit unit. */
1930         E1000_WRITE_REG(hw, E1000_TCTL, tctl);
1931 }
1932
1933 static boolean_t
1934 igb_txcsum_ctx(struct igb_tx_ring *txr, struct mbuf *mp)
1935 {
1936         struct e1000_adv_tx_context_desc *TXD;
1937         uint32_t vlan_macip_lens, type_tucmd_mlhl, mss_l4len_idx;
1938         int ehdrlen, ctxd, ip_hlen = 0;
1939         boolean_t offload = TRUE;
1940
1941         if ((mp->m_pkthdr.csum_flags & IGB_CSUM_FEATURES) == 0)
1942                 offload = FALSE;
1943
1944         vlan_macip_lens = type_tucmd_mlhl = mss_l4len_idx = 0;
1945
1946         ctxd = txr->next_avail_desc;
1947         TXD = (struct e1000_adv_tx_context_desc *)&txr->tx_base[ctxd];
1948
1949         /*
1950          * In advanced descriptors the vlan tag must 
1951          * be placed into the context descriptor, thus
1952          * we need to be here just for that setup.
1953          */
1954         if (mp->m_flags & M_VLANTAG) {
1955                 uint16_t vlantag;
1956
1957                 vlantag = htole16(mp->m_pkthdr.ether_vlantag);
1958                 vlan_macip_lens |= (vlantag << E1000_ADVTXD_VLAN_SHIFT);
1959         } else if (!offload) {
1960                 return FALSE;
1961         }
1962
1963         ehdrlen = mp->m_pkthdr.csum_lhlen;
1964         KASSERT(ehdrlen > 0, ("invalid ether hlen"));
1965
1966         /* Set the ether header length */
1967         vlan_macip_lens |= ehdrlen << E1000_ADVTXD_MACLEN_SHIFT;
1968         if (mp->m_pkthdr.csum_flags & CSUM_IP) {
1969                 type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_IPV4;
1970                 ip_hlen = mp->m_pkthdr.csum_iphlen;
1971                 KASSERT(ip_hlen > 0, ("invalid ip hlen"));
1972         }
1973         vlan_macip_lens |= ip_hlen;
1974
1975         type_tucmd_mlhl |= E1000_ADVTXD_DCMD_DEXT | E1000_ADVTXD_DTYP_CTXT;
1976         if (mp->m_pkthdr.csum_flags & CSUM_TCP)
1977                 type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_L4T_TCP;
1978         else if (mp->m_pkthdr.csum_flags & CSUM_UDP)
1979                 type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_L4T_UDP;
1980
1981         /* 82575 needs the queue index added */
1982         if (txr->sc->hw.mac.type == e1000_82575)
1983                 mss_l4len_idx = txr->me << 4;
1984
1985         /* Now copy bits into descriptor */
1986         TXD->vlan_macip_lens = htole32(vlan_macip_lens);
1987         TXD->type_tucmd_mlhl = htole32(type_tucmd_mlhl);
1988         TXD->seqnum_seed = htole32(0);
1989         TXD->mss_l4len_idx = htole32(mss_l4len_idx);
1990
1991         /* We've consumed the first desc, adjust counters */
1992         if (++ctxd == txr->num_tx_desc)
1993                 ctxd = 0;
1994         txr->next_avail_desc = ctxd;
1995         --txr->tx_avail;
1996
1997         return offload;
1998 }
1999
2000 static void
2001 igb_txeof(struct igb_tx_ring *txr)
2002 {
2003         struct ifnet *ifp = &txr->sc->arpcom.ac_if;
2004         int first, hdr, avail;
2005
2006         if (txr->tx_avail == txr->num_tx_desc)
2007                 return;
2008
2009         first = txr->next_to_clean;
2010         hdr = *(txr->tx_hdr);
2011
2012         if (first == hdr)
2013                 return;
2014
2015         avail = txr->tx_avail;
2016         while (first != hdr) {
2017                 struct igb_tx_buf *txbuf = &txr->tx_buf[first];
2018
2019                 ++avail;
2020                 if (txbuf->m_head) {
2021                         bus_dmamap_unload(txr->tx_tag, txbuf->map);
2022                         m_freem(txbuf->m_head);
2023                         txbuf->m_head = NULL;
2024                         ++ifp->if_opackets;
2025                 }
2026                 if (++first == txr->num_tx_desc)
2027                         first = 0;
2028         }
2029         txr->next_to_clean = first;
2030         txr->tx_avail = avail;
2031
2032         /*
2033          * If we have a minimum free, clear OACTIVE
2034          * to tell the stack that it is OK to send packets.
2035          */
2036         if (IGB_IS_NOT_OACTIVE(txr)) {
2037                 ifsq_clr_oactive(txr->ifsq);
2038
2039                 /*
2040                  * We have enough TX descriptors, turn off
2041                  * the watchdog.  We allow small amount of
2042                  * packets (roughly intr_nsegs) pending on
2043                  * the transmit ring.
2044                  */
2045                 txr->tx_watchdog.wd_timer = 0;
2046         }
2047 }
2048
2049 static int
2050 igb_create_rx_ring(struct igb_rx_ring *rxr)
2051 {
2052         int rsize, i, error, nrxd;
2053
2054         /*
2055          * Validate number of receive descriptors. It must not exceed
2056          * hardware maximum, and must be multiple of IGB_DBA_ALIGN.
2057          */
2058         nrxd = device_getenv_int(rxr->sc->dev, "rxd", igb_rxd);
2059         if ((nrxd * sizeof(struct e1000_rx_desc)) % IGB_DBA_ALIGN != 0 ||
2060             nrxd > IGB_MAX_RXD || nrxd < IGB_MIN_RXD) {
2061                 device_printf(rxr->sc->dev,
2062                     "Using %d RX descriptors instead of %d!\n",
2063                     IGB_DEFAULT_RXD, nrxd);
2064                 rxr->num_rx_desc = IGB_DEFAULT_RXD;
2065         } else {
2066                 rxr->num_rx_desc = nrxd;
2067         }
2068
2069         /*
2070          * Allocate RX descriptor ring
2071          */
2072         rsize = roundup2(rxr->num_rx_desc * sizeof(union e1000_adv_rx_desc),
2073             IGB_DBA_ALIGN);
2074         rxr->rxdma.dma_vaddr = bus_dmamem_coherent_any(rxr->sc->parent_tag,
2075             IGB_DBA_ALIGN, rsize, BUS_DMA_WAITOK,
2076             &rxr->rxdma.dma_tag, &rxr->rxdma.dma_map,
2077             &rxr->rxdma.dma_paddr);
2078         if (rxr->rxdma.dma_vaddr == NULL) {
2079                 device_printf(rxr->sc->dev,
2080                     "Unable to allocate RxDescriptor memory\n");
2081                 return ENOMEM;
2082         }
2083         rxr->rx_base = rxr->rxdma.dma_vaddr;
2084         bzero(rxr->rx_base, rsize);
2085
2086         rsize = __VM_CACHELINE_ALIGN(
2087             sizeof(struct igb_rx_buf) * rxr->num_rx_desc);
2088         rxr->rx_buf = kmalloc_cachealign(rsize, M_DEVBUF, M_WAITOK | M_ZERO);
2089
2090         /*
2091          * Create DMA tag for RX buffers
2092          */
2093         error = bus_dma_tag_create(rxr->sc->parent_tag,
2094             1, 0,               /* alignment, bounds */
2095             BUS_SPACE_MAXADDR,  /* lowaddr */
2096             BUS_SPACE_MAXADDR,  /* highaddr */
2097             NULL, NULL,         /* filter, filterarg */
2098             MCLBYTES,           /* maxsize */
2099             1,                  /* nsegments */
2100             MCLBYTES,           /* maxsegsize */
2101             BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, /* flags */
2102             &rxr->rx_tag);
2103         if (error) {
2104                 device_printf(rxr->sc->dev,
2105                     "Unable to create RX payload DMA tag\n");
2106                 kfree(rxr->rx_buf, M_DEVBUF);
2107                 rxr->rx_buf = NULL;
2108                 return error;
2109         }
2110
2111         /*
2112          * Create spare DMA map for RX buffers
2113          */
2114         error = bus_dmamap_create(rxr->rx_tag, BUS_DMA_WAITOK,
2115             &rxr->rx_sparemap);
2116         if (error) {
2117                 device_printf(rxr->sc->dev,
2118                     "Unable to create spare RX DMA maps\n");
2119                 bus_dma_tag_destroy(rxr->rx_tag);
2120                 kfree(rxr->rx_buf, M_DEVBUF);
2121                 rxr->rx_buf = NULL;
2122                 return error;
2123         }
2124
2125         /*
2126          * Create DMA maps for RX buffers
2127          */
2128         for (i = 0; i < rxr->num_rx_desc; i++) {
2129                 struct igb_rx_buf *rxbuf = &rxr->rx_buf[i];
2130
2131                 error = bus_dmamap_create(rxr->rx_tag,
2132                     BUS_DMA_WAITOK, &rxbuf->map);
2133                 if (error) {
2134                         device_printf(rxr->sc->dev,
2135                             "Unable to create RX DMA maps\n");
2136                         igb_destroy_rx_ring(rxr, i);
2137                         return error;
2138                 }
2139         }
2140
2141         /*
2142          * Initialize various watermark
2143          */
2144         rxr->wreg_nsegs = IGB_DEF_RXWREG_NSEGS;
2145
2146         return 0;
2147 }
2148
2149 static void
2150 igb_free_rx_ring(struct igb_rx_ring *rxr)
2151 {
2152         int i;
2153
2154         for (i = 0; i < rxr->num_rx_desc; ++i) {
2155                 struct igb_rx_buf *rxbuf = &rxr->rx_buf[i];
2156
2157                 if (rxbuf->m_head != NULL) {
2158                         bus_dmamap_unload(rxr->rx_tag, rxbuf->map);
2159                         m_freem(rxbuf->m_head);
2160                         rxbuf->m_head = NULL;
2161                 }
2162         }
2163
2164         if (rxr->fmp != NULL)
2165                 m_freem(rxr->fmp);
2166         rxr->fmp = NULL;
2167         rxr->lmp = NULL;
2168 }
2169
2170 static void
2171 igb_destroy_rx_ring(struct igb_rx_ring *rxr, int ndesc)
2172 {
2173         int i;
2174
2175         if (rxr->rxdma.dma_vaddr != NULL) {
2176                 bus_dmamap_unload(rxr->rxdma.dma_tag, rxr->rxdma.dma_map);
2177                 bus_dmamem_free(rxr->rxdma.dma_tag, rxr->rxdma.dma_vaddr,
2178                     rxr->rxdma.dma_map);
2179                 bus_dma_tag_destroy(rxr->rxdma.dma_tag);
2180                 rxr->rxdma.dma_vaddr = NULL;
2181         }
2182
2183         if (rxr->rx_buf == NULL)
2184                 return;
2185
2186         for (i = 0; i < ndesc; ++i) {
2187                 struct igb_rx_buf *rxbuf = &rxr->rx_buf[i];
2188
2189                 KKASSERT(rxbuf->m_head == NULL);
2190                 bus_dmamap_destroy(rxr->rx_tag, rxbuf->map);
2191         }
2192         bus_dmamap_destroy(rxr->rx_tag, rxr->rx_sparemap);
2193         bus_dma_tag_destroy(rxr->rx_tag);
2194
2195         kfree(rxr->rx_buf, M_DEVBUF);
2196         rxr->rx_buf = NULL;
2197 }
2198
2199 static void
2200 igb_setup_rxdesc(union e1000_adv_rx_desc *rxd, const struct igb_rx_buf *rxbuf)
2201 {
2202         rxd->read.pkt_addr = htole64(rxbuf->paddr);
2203         rxd->wb.upper.status_error = 0;
2204 }
2205
2206 static int
2207 igb_newbuf(struct igb_rx_ring *rxr, int i, boolean_t wait)
2208 {
2209         struct mbuf *m;
2210         bus_dma_segment_t seg;
2211         bus_dmamap_t map;
2212         struct igb_rx_buf *rxbuf;
2213         int error, nseg;
2214
2215         m = m_getcl(wait ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR);
2216         if (m == NULL) {
2217                 if (wait) {
2218                         if_printf(&rxr->sc->arpcom.ac_if,
2219                             "Unable to allocate RX mbuf\n");
2220                 }
2221                 return ENOBUFS;
2222         }
2223         m->m_len = m->m_pkthdr.len = MCLBYTES;
2224
2225         if (rxr->sc->max_frame_size <= MCLBYTES - ETHER_ALIGN)
2226                 m_adj(m, ETHER_ALIGN);
2227
2228         error = bus_dmamap_load_mbuf_segment(rxr->rx_tag,
2229             rxr->rx_sparemap, m, &seg, 1, &nseg, BUS_DMA_NOWAIT);
2230         if (error) {
2231                 m_freem(m);
2232                 if (wait) {
2233                         if_printf(&rxr->sc->arpcom.ac_if,
2234                             "Unable to load RX mbuf\n");
2235                 }
2236                 return error;
2237         }
2238
2239         rxbuf = &rxr->rx_buf[i];
2240         if (rxbuf->m_head != NULL)
2241                 bus_dmamap_unload(rxr->rx_tag, rxbuf->map);
2242
2243         map = rxbuf->map;
2244         rxbuf->map = rxr->rx_sparemap;
2245         rxr->rx_sparemap = map;
2246
2247         rxbuf->m_head = m;
2248         rxbuf->paddr = seg.ds_addr;
2249
2250         igb_setup_rxdesc(&rxr->rx_base[i], rxbuf);
2251         return 0;
2252 }
2253
2254 static int
2255 igb_init_rx_ring(struct igb_rx_ring *rxr)
2256 {
2257         int i;
2258
2259         /* Clear the ring contents */
2260         bzero(rxr->rx_base,
2261             rxr->num_rx_desc * sizeof(union e1000_adv_rx_desc));
2262
2263         /* Now replenish the ring mbufs */
2264         for (i = 0; i < rxr->num_rx_desc; ++i) {
2265                 int error;
2266
2267                 error = igb_newbuf(rxr, i, TRUE);
2268                 if (error)
2269                         return error;
2270         }
2271
2272         /* Setup our descriptor indices */
2273         rxr->next_to_check = 0;
2274
2275         rxr->fmp = NULL;
2276         rxr->lmp = NULL;
2277         rxr->discard = FALSE;
2278
2279         return 0;
2280 }
2281
2282 static void
2283 igb_init_rx_unit(struct igb_softc *sc)
2284 {
2285         struct ifnet *ifp = &sc->arpcom.ac_if;
2286         struct e1000_hw *hw = &sc->hw;
2287         uint32_t rctl, rxcsum, srrctl = 0;
2288         int i;
2289
2290         /*
2291          * Make sure receives are disabled while setting
2292          * up the descriptor ring
2293          */
2294         rctl = E1000_READ_REG(hw, E1000_RCTL);
2295         E1000_WRITE_REG(hw, E1000_RCTL, rctl & ~E1000_RCTL_EN);
2296
2297 #if 0
2298         /*
2299         ** Set up for header split
2300         */
2301         if (igb_header_split) {
2302                 /* Use a standard mbuf for the header */
2303                 srrctl |= IGB_HDR_BUF << E1000_SRRCTL_BSIZEHDRSIZE_SHIFT;
2304                 srrctl |= E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
2305         } else
2306 #endif
2307                 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
2308
2309         /*
2310         ** Set up for jumbo frames
2311         */
2312         if (ifp->if_mtu > ETHERMTU) {
2313                 rctl |= E1000_RCTL_LPE;
2314 #if 0
2315                 if (adapter->rx_mbuf_sz == MJUMPAGESIZE) {
2316                         srrctl |= 4096 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
2317                         rctl |= E1000_RCTL_SZ_4096 | E1000_RCTL_BSEX;
2318                 } else if (adapter->rx_mbuf_sz > MJUMPAGESIZE) {
2319                         srrctl |= 8192 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
2320                         rctl |= E1000_RCTL_SZ_8192 | E1000_RCTL_BSEX;
2321                 }
2322                 /* Set maximum packet len */
2323                 psize = adapter->max_frame_size;
2324                 /* are we on a vlan? */
2325                 if (adapter->ifp->if_vlantrunk != NULL)
2326                         psize += VLAN_TAG_SIZE;
2327                 E1000_WRITE_REG(&adapter->hw, E1000_RLPML, psize);
2328 #else
2329                 srrctl |= 2048 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
2330                 rctl |= E1000_RCTL_SZ_2048;
2331 #endif
2332         } else {
2333                 rctl &= ~E1000_RCTL_LPE;
2334                 srrctl |= 2048 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
2335                 rctl |= E1000_RCTL_SZ_2048;
2336         }
2337
2338         /* Setup the Base and Length of the Rx Descriptor Rings */
2339         for (i = 0; i < sc->rx_ring_inuse; ++i) {
2340                 struct igb_rx_ring *rxr = &sc->rx_rings[i];
2341                 uint64_t bus_addr = rxr->rxdma.dma_paddr;
2342                 uint32_t rxdctl;
2343
2344                 E1000_WRITE_REG(hw, E1000_RDLEN(i),
2345                     rxr->num_rx_desc * sizeof(struct e1000_rx_desc));
2346                 E1000_WRITE_REG(hw, E1000_RDBAH(i),
2347                     (uint32_t)(bus_addr >> 32));
2348                 E1000_WRITE_REG(hw, E1000_RDBAL(i),
2349                     (uint32_t)bus_addr);
2350                 E1000_WRITE_REG(hw, E1000_SRRCTL(i), srrctl);
2351                 /* Enable this Queue */
2352                 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(i));
2353                 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
2354                 rxdctl &= 0xFFF00000;
2355                 rxdctl |= IGB_RX_PTHRESH;
2356                 rxdctl |= IGB_RX_HTHRESH << 8;
2357                 /*
2358                  * Don't set WTHRESH to a value above 1 on 82576, see:
2359                  * 82576 specification update errata #26
2360                  */
2361                 rxdctl |= IGB_RX_WTHRESH << 16;
2362                 E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl);
2363         }
2364
2365         rxcsum = E1000_READ_REG(&sc->hw, E1000_RXCSUM);
2366         rxcsum &= ~(E1000_RXCSUM_PCSS_MASK | E1000_RXCSUM_IPPCSE);
2367
2368         /*
2369          * Receive Checksum Offload for TCP and UDP
2370          *
2371          * Checksum offloading is also enabled if multiple receive
2372          * queue is to be supported, since we need it to figure out
2373          * fragments.
2374          */
2375         if ((ifp->if_capenable & IFCAP_RXCSUM) || IGB_ENABLE_HWRSS(sc)) {
2376                 /*
2377                  * NOTE:
2378                  * PCSD must be enabled to enable multiple
2379                  * receive queues.
2380                  */
2381                 rxcsum |= E1000_RXCSUM_IPOFL | E1000_RXCSUM_TUOFL |
2382                     E1000_RXCSUM_PCSD;
2383         } else {
2384                 rxcsum &= ~(E1000_RXCSUM_IPOFL | E1000_RXCSUM_TUOFL |
2385                     E1000_RXCSUM_PCSD);
2386         }
2387         E1000_WRITE_REG(&sc->hw, E1000_RXCSUM, rxcsum);
2388
2389         if (IGB_ENABLE_HWRSS(sc)) {
2390                 uint8_t key[IGB_NRSSRK * IGB_RSSRK_SIZE];
2391                 uint32_t reta_shift;
2392                 int j, r;
2393
2394                 /*
2395                  * NOTE:
2396                  * When we reach here, RSS has already been disabled
2397                  * in igb_stop(), so we could safely configure RSS key
2398                  * and redirect table.
2399                  */
2400
2401                 /*
2402                  * Configure RSS key
2403                  */
2404                 toeplitz_get_key(key, sizeof(key));
2405                 for (i = 0; i < IGB_NRSSRK; ++i) {
2406                         uint32_t rssrk;
2407
2408                         rssrk = IGB_RSSRK_VAL(key, i);
2409                         IGB_RSS_DPRINTF(sc, 1, "rssrk%d 0x%08x\n", i, rssrk);
2410
2411                         E1000_WRITE_REG(hw, E1000_RSSRK(i), rssrk);
2412                 }
2413
2414                 /*
2415                  * Configure RSS redirect table in following fashion:
2416                  * (hash & ring_cnt_mask) == rdr_table[(hash & rdr_table_mask)]
2417                  */
2418                 reta_shift = IGB_RETA_SHIFT;
2419                 if (hw->mac.type == e1000_82575)
2420                         reta_shift = IGB_RETA_SHIFT_82575;
2421
2422                 r = 0;
2423                 for (j = 0; j < IGB_NRETA; ++j) {
2424                         uint32_t reta = 0;
2425
2426                         for (i = 0; i < IGB_RETA_SIZE; ++i) {
2427                                 uint32_t q;
2428
2429                                 q = (r % sc->rx_ring_inuse) << reta_shift;
2430                                 reta |= q << (8 * i);
2431                                 ++r;
2432                         }
2433                         IGB_RSS_DPRINTF(sc, 1, "reta 0x%08x\n", reta);
2434                         E1000_WRITE_REG(hw, E1000_RETA(j), reta);
2435                 }
2436
2437                 /*
2438                  * Enable multiple receive queues.
2439                  * Enable IPv4 RSS standard hash functions.
2440                  * Disable RSS interrupt on 82575
2441                  */
2442                 E1000_WRITE_REG(&sc->hw, E1000_MRQC,
2443                                 E1000_MRQC_ENABLE_RSS_4Q |
2444                                 E1000_MRQC_RSS_FIELD_IPV4_TCP |
2445                                 E1000_MRQC_RSS_FIELD_IPV4);
2446         }
2447
2448         /* Setup the Receive Control Register */
2449         rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
2450         rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_LBM_NO |
2451             E1000_RCTL_RDMTS_HALF |
2452             (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
2453         /* Strip CRC bytes. */
2454         rctl |= E1000_RCTL_SECRC;
2455         /* Make sure VLAN Filters are off */
2456         rctl &= ~E1000_RCTL_VFE;
2457         /* Don't store bad packets */
2458         rctl &= ~E1000_RCTL_SBP;
2459
2460         /* Enable Receives */
2461         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2462
2463         /*
2464          * Setup the HW Rx Head and Tail Descriptor Pointers
2465          *   - needs to be after enable
2466          */
2467         for (i = 0; i < sc->rx_ring_inuse; ++i) {
2468                 struct igb_rx_ring *rxr = &sc->rx_rings[i];
2469
2470                 E1000_WRITE_REG(hw, E1000_RDH(i), rxr->next_to_check);
2471                 E1000_WRITE_REG(hw, E1000_RDT(i), rxr->num_rx_desc - 1);
2472         }
2473 }
2474
2475 static void
2476 igb_rx_refresh(struct igb_rx_ring *rxr, int i)
2477 {
2478         if (--i < 0)
2479                 i = rxr->num_rx_desc - 1;
2480         E1000_WRITE_REG(&rxr->sc->hw, E1000_RDT(rxr->me), i);
2481 }
2482
2483 static void
2484 igb_rxeof(struct igb_rx_ring *rxr, int count)
2485 {
2486         struct ifnet *ifp = &rxr->sc->arpcom.ac_if;
2487         union e1000_adv_rx_desc *cur;
2488         uint32_t staterr;
2489         int i, ncoll = 0;
2490
2491         i = rxr->next_to_check;
2492         cur = &rxr->rx_base[i];
2493         staterr = le32toh(cur->wb.upper.status_error);
2494
2495         if ((staterr & E1000_RXD_STAT_DD) == 0)
2496                 return;
2497
2498         while ((staterr & E1000_RXD_STAT_DD) && count != 0) {
2499                 struct pktinfo *pi = NULL, pi0;
2500                 struct igb_rx_buf *rxbuf = &rxr->rx_buf[i];
2501                 struct mbuf *m = NULL;
2502                 boolean_t eop;
2503
2504                 eop = (staterr & E1000_RXD_STAT_EOP) ? TRUE : FALSE;
2505                 if (eop)
2506                         --count;
2507
2508                 ++ncoll;
2509                 if ((staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) == 0 &&
2510                     !rxr->discard) {
2511                         struct mbuf *mp = rxbuf->m_head;
2512                         uint32_t hash, hashtype;
2513                         uint16_t vlan;
2514                         int len;
2515
2516                         len = le16toh(cur->wb.upper.length);
2517                         if (rxr->sc->hw.mac.type == e1000_i350 &&
2518                             (staterr & E1000_RXDEXT_STATERR_LB))
2519                                 vlan = be16toh(cur->wb.upper.vlan);
2520                         else
2521                                 vlan = le16toh(cur->wb.upper.vlan);
2522
2523                         hash = le32toh(cur->wb.lower.hi_dword.rss);
2524                         hashtype = le32toh(cur->wb.lower.lo_dword.data) &
2525                             E1000_RXDADV_RSSTYPE_MASK;
2526
2527                         IGB_RSS_DPRINTF(rxr->sc, 10,
2528                             "ring%d, hash 0x%08x, hashtype %u\n",
2529                             rxr->me, hash, hashtype);
2530
2531                         bus_dmamap_sync(rxr->rx_tag, rxbuf->map,
2532                             BUS_DMASYNC_POSTREAD);
2533
2534                         if (igb_newbuf(rxr, i, FALSE) != 0) {
2535                                 ifp->if_iqdrops++;
2536                                 goto discard;
2537                         }
2538
2539                         mp->m_len = len;
2540                         if (rxr->fmp == NULL) {
2541                                 mp->m_pkthdr.len = len;
2542                                 rxr->fmp = mp;
2543                                 rxr->lmp = mp;
2544                         } else {
2545                                 rxr->lmp->m_next = mp;
2546                                 rxr->lmp = rxr->lmp->m_next;
2547                                 rxr->fmp->m_pkthdr.len += len;
2548                         }
2549
2550                         if (eop) {
2551                                 m = rxr->fmp;
2552                                 rxr->fmp = NULL;
2553                                 rxr->lmp = NULL;
2554
2555                                 m->m_pkthdr.rcvif = ifp;
2556                                 ifp->if_ipackets++;
2557
2558                                 if (ifp->if_capenable & IFCAP_RXCSUM)
2559                                         igb_rxcsum(staterr, m);
2560
2561                                 if (staterr & E1000_RXD_STAT_VP) {
2562                                         m->m_pkthdr.ether_vlantag = vlan;
2563                                         m->m_flags |= M_VLANTAG;
2564                                 }
2565
2566                                 if (ifp->if_capenable & IFCAP_RSS) {
2567                                         pi = igb_rssinfo(m, &pi0,
2568                                             hash, hashtype, staterr);
2569                                 }
2570 #ifdef IGB_RSS_DEBUG
2571                                 rxr->rx_packets++;
2572 #endif
2573                         }
2574                 } else {
2575                         ifp->if_ierrors++;
2576 discard:
2577                         igb_setup_rxdesc(cur, rxbuf);
2578                         if (!eop)
2579                                 rxr->discard = TRUE;
2580                         else
2581                                 rxr->discard = FALSE;
2582                         if (rxr->fmp != NULL) {
2583                                 m_freem(rxr->fmp);
2584                                 rxr->fmp = NULL;
2585                                 rxr->lmp = NULL;
2586                         }
2587                         m = NULL;
2588                 }
2589
2590                 if (m != NULL)
2591                         ether_input_pkt(ifp, m, pi);
2592
2593                 /* Advance our pointers to the next descriptor. */
2594                 if (++i == rxr->num_rx_desc)
2595                         i = 0;
2596
2597                 if (ncoll >= rxr->wreg_nsegs) {
2598                         igb_rx_refresh(rxr, i);
2599                         ncoll = 0;
2600                 }
2601
2602                 cur = &rxr->rx_base[i];
2603                 staterr = le32toh(cur->wb.upper.status_error);
2604         }
2605         rxr->next_to_check = i;
2606
2607         if (ncoll > 0)
2608                 igb_rx_refresh(rxr, i);
2609 }
2610
2611
2612 static void
2613 igb_set_vlan(struct igb_softc *sc)
2614 {
2615         struct e1000_hw *hw = &sc->hw;
2616         uint32_t reg;
2617 #if 0
2618         struct ifnet *ifp = sc->arpcom.ac_if;
2619 #endif
2620
2621         if (sc->vf_ifp) {
2622                 e1000_rlpml_set_vf(hw, sc->max_frame_size + VLAN_TAG_SIZE);
2623                 return;
2624         }
2625
2626         reg = E1000_READ_REG(hw, E1000_CTRL);
2627         reg |= E1000_CTRL_VME;
2628         E1000_WRITE_REG(hw, E1000_CTRL, reg);
2629
2630 #if 0
2631         /* Enable the Filter Table */
2632         if (ifp->if_capenable & IFCAP_VLAN_HWFILTER) {
2633                 reg = E1000_READ_REG(hw, E1000_RCTL);
2634                 reg &= ~E1000_RCTL_CFIEN;
2635                 reg |= E1000_RCTL_VFE;
2636                 E1000_WRITE_REG(hw, E1000_RCTL, reg);
2637         }
2638 #endif
2639
2640         /* Update the frame size */
2641         E1000_WRITE_REG(&sc->hw, E1000_RLPML,
2642             sc->max_frame_size + VLAN_TAG_SIZE);
2643
2644 #if 0
2645         /* Don't bother with table if no vlans */
2646         if ((adapter->num_vlans == 0) ||
2647             ((ifp->if_capenable & IFCAP_VLAN_HWFILTER) == 0))
2648                 return;
2649         /*
2650         ** A soft reset zero's out the VFTA, so
2651         ** we need to repopulate it now.
2652         */
2653         for (int i = 0; i < IGB_VFTA_SIZE; i++)
2654                 if (adapter->shadow_vfta[i] != 0) {
2655                         if (adapter->vf_ifp)
2656                                 e1000_vfta_set_vf(hw,
2657                                     adapter->shadow_vfta[i], TRUE);
2658                         else
2659                                 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA,
2660                                  i, adapter->shadow_vfta[i]);
2661                 }
2662 #endif
2663 }
2664
2665 static void
2666 igb_enable_intr(struct igb_softc *sc)
2667 {
2668         if (sc->intr_type != PCI_INTR_TYPE_MSIX) {
2669                 lwkt_serialize_handler_enable(&sc->main_serialize);
2670         } else {
2671                 int i;
2672
2673                 for (i = 0; i < sc->msix_cnt; ++i) {
2674                         lwkt_serialize_handler_enable(
2675                             sc->msix_data[i].msix_serialize);
2676                 }
2677         }
2678
2679         if ((sc->flags & IGB_FLAG_SHARED_INTR) == 0) {
2680                 if (sc->intr_type == PCI_INTR_TYPE_MSIX)
2681                         E1000_WRITE_REG(&sc->hw, E1000_EIAC, sc->intr_mask);
2682                 else
2683                         E1000_WRITE_REG(&sc->hw, E1000_EIAC, 0);
2684                 E1000_WRITE_REG(&sc->hw, E1000_EIAM, sc->intr_mask);
2685                 E1000_WRITE_REG(&sc->hw, E1000_EIMS, sc->intr_mask);
2686                 E1000_WRITE_REG(&sc->hw, E1000_IMS, E1000_IMS_LSC);
2687         } else {
2688                 E1000_WRITE_REG(&sc->hw, E1000_IMS, IMS_ENABLE_MASK);
2689         }
2690         E1000_WRITE_FLUSH(&sc->hw);
2691 }
2692
2693 static void
2694 igb_disable_intr(struct igb_softc *sc)
2695 {
2696         if ((sc->flags & IGB_FLAG_SHARED_INTR) == 0) {
2697                 E1000_WRITE_REG(&sc->hw, E1000_EIMC, 0xffffffff);
2698                 E1000_WRITE_REG(&sc->hw, E1000_EIAC, 0);
2699         }
2700         E1000_WRITE_REG(&sc->hw, E1000_IMC, 0xffffffff);
2701         E1000_WRITE_FLUSH(&sc->hw);
2702
2703         if (sc->intr_type != PCI_INTR_TYPE_MSIX) {
2704                 lwkt_serialize_handler_disable(&sc->main_serialize);
2705         } else {
2706                 int i;
2707
2708                 for (i = 0; i < sc->msix_cnt; ++i) {
2709                         lwkt_serialize_handler_disable(
2710                             sc->msix_data[i].msix_serialize);
2711                 }
2712         }
2713 }
2714
2715 /*
2716  * Bit of a misnomer, what this really means is
2717  * to enable OS management of the system... aka
2718  * to disable special hardware management features 
2719  */
2720 static void
2721 igb_get_mgmt(struct igb_softc *sc)
2722 {
2723         if (sc->flags & IGB_FLAG_HAS_MGMT) {
2724                 int manc2h = E1000_READ_REG(&sc->hw, E1000_MANC2H);
2725                 int manc = E1000_READ_REG(&sc->hw, E1000_MANC);
2726
2727                 /* disable hardware interception of ARP */
2728                 manc &= ~E1000_MANC_ARP_EN;
2729
2730                 /* enable receiving management packets to the host */
2731                 manc |= E1000_MANC_EN_MNG2HOST;
2732                 manc2h |= 1 << 5; /* Mng Port 623 */
2733                 manc2h |= 1 << 6; /* Mng Port 664 */
2734                 E1000_WRITE_REG(&sc->hw, E1000_MANC2H, manc2h);
2735                 E1000_WRITE_REG(&sc->hw, E1000_MANC, manc);
2736         }
2737 }
2738
2739 /*
2740  * Give control back to hardware management controller
2741  * if there is one.
2742  */
2743 static void
2744 igb_rel_mgmt(struct igb_softc *sc)
2745 {
2746         if (sc->flags & IGB_FLAG_HAS_MGMT) {
2747                 int manc = E1000_READ_REG(&sc->hw, E1000_MANC);
2748
2749                 /* Re-enable hardware interception of ARP */
2750                 manc |= E1000_MANC_ARP_EN;
2751                 manc &= ~E1000_MANC_EN_MNG2HOST;
2752
2753                 E1000_WRITE_REG(&sc->hw, E1000_MANC, manc);
2754         }
2755 }
2756
2757 /*
2758  * Sets CTRL_EXT:DRV_LOAD bit.
2759  *
2760  * For ASF and Pass Through versions of f/w this means that
2761  * the driver is loaded. 
2762  */
2763 static void
2764 igb_get_hw_control(struct igb_softc *sc)
2765 {
2766         uint32_t ctrl_ext;
2767
2768         if (sc->vf_ifp)
2769                 return;
2770
2771         /* Let firmware know the driver has taken over */
2772         ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT);
2773         E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT,
2774             ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
2775 }
2776
2777 /*
2778  * Resets CTRL_EXT:DRV_LOAD bit.
2779  *
2780  * For ASF and Pass Through versions of f/w this means that the
2781  * driver is no longer loaded.
2782  */
2783 static void
2784 igb_rel_hw_control(struct igb_softc *sc)
2785 {
2786         uint32_t ctrl_ext;
2787
2788         if (sc->vf_ifp)
2789                 return;
2790
2791         /* Let firmware taken over control of h/w */
2792         ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT);
2793         E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT,
2794             ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
2795 }
2796
2797 static int
2798 igb_is_valid_ether_addr(const uint8_t *addr)
2799 {
2800         uint8_t zero_addr[ETHER_ADDR_LEN] = { 0, 0, 0, 0, 0, 0 };
2801
2802         if ((addr[0] & 1) || !bcmp(addr, zero_addr, ETHER_ADDR_LEN))
2803                 return FALSE;
2804         return TRUE;
2805 }
2806
2807 /*
2808  * Enable PCI Wake On Lan capability
2809  */
2810 static void
2811 igb_enable_wol(device_t dev)
2812 {
2813         uint16_t cap, status;
2814         uint8_t id;
2815
2816         /* First find the capabilities pointer*/
2817         cap = pci_read_config(dev, PCIR_CAP_PTR, 2);
2818
2819         /* Read the PM Capabilities */
2820         id = pci_read_config(dev, cap, 1);
2821         if (id != PCIY_PMG)     /* Something wrong */
2822                 return;
2823
2824         /*
2825          * OK, we have the power capabilities,
2826          * so now get the status register
2827          */
2828         cap += PCIR_POWER_STATUS;
2829         status = pci_read_config(dev, cap, 2);
2830         status |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
2831         pci_write_config(dev, cap, status, 2);
2832 }
2833
2834 static void
2835 igb_update_stats_counters(struct igb_softc *sc)
2836 {
2837         struct e1000_hw *hw = &sc->hw;
2838         struct e1000_hw_stats *stats;
2839         struct ifnet *ifp = &sc->arpcom.ac_if;
2840
2841         /* 
2842          * The virtual function adapter has only a
2843          * small controlled set of stats, do only 
2844          * those and return.
2845          */
2846         if (sc->vf_ifp) {
2847                 igb_update_vf_stats_counters(sc);
2848                 return;
2849         }
2850         stats = sc->stats;
2851
2852         if (sc->hw.phy.media_type == e1000_media_type_copper ||
2853             (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
2854                 stats->symerrs +=
2855                     E1000_READ_REG(hw,E1000_SYMERRS);
2856                 stats->sec += E1000_READ_REG(hw, E1000_SEC);
2857         }
2858
2859         stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
2860         stats->mpc += E1000_READ_REG(hw, E1000_MPC);
2861         stats->scc += E1000_READ_REG(hw, E1000_SCC);
2862         stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
2863
2864         stats->mcc += E1000_READ_REG(hw, E1000_MCC);
2865         stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
2866         stats->colc += E1000_READ_REG(hw, E1000_COLC);
2867         stats->dc += E1000_READ_REG(hw, E1000_DC);
2868         stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
2869         stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
2870         stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
2871
2872         /*
2873          * For watchdog management we need to know if we have been
2874          * paused during the last interval, so capture that here.
2875          */ 
2876         sc->pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
2877         stats->xoffrxc += sc->pause_frames;
2878         stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
2879         stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
2880         stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
2881         stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
2882         stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
2883         stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
2884         stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
2885         stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
2886         stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
2887         stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
2888         stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
2889         stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
2890
2891         /* For the 64-bit byte counters the low dword must be read first. */
2892         /* Both registers clear on the read of the high dword */
2893
2894         stats->gorc += E1000_READ_REG(hw, E1000_GORCL) +
2895             ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
2896         stats->gotc += E1000_READ_REG(hw, E1000_GOTCL) +
2897             ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
2898
2899         stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
2900         stats->ruc += E1000_READ_REG(hw, E1000_RUC);
2901         stats->rfc += E1000_READ_REG(hw, E1000_RFC);
2902         stats->roc += E1000_READ_REG(hw, E1000_ROC);
2903         stats->rjc += E1000_READ_REG(hw, E1000_RJC);
2904
2905         stats->tor += E1000_READ_REG(hw, E1000_TORH);
2906         stats->tot += E1000_READ_REG(hw, E1000_TOTH);
2907
2908         stats->tpr += E1000_READ_REG(hw, E1000_TPR);
2909         stats->tpt += E1000_READ_REG(hw, E1000_TPT);
2910         stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
2911         stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
2912         stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
2913         stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
2914         stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
2915         stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
2916         stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
2917         stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
2918
2919         /* Interrupt Counts */
2920
2921         stats->iac += E1000_READ_REG(hw, E1000_IAC);
2922         stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
2923         stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
2924         stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
2925         stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
2926         stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
2927         stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
2928         stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
2929         stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
2930
2931         /* Host to Card Statistics */
2932
2933         stats->cbtmpc += E1000_READ_REG(hw, E1000_CBTMPC);
2934         stats->htdpmc += E1000_READ_REG(hw, E1000_HTDPMC);
2935         stats->cbrdpc += E1000_READ_REG(hw, E1000_CBRDPC);
2936         stats->cbrmpc += E1000_READ_REG(hw, E1000_CBRMPC);
2937         stats->rpthc += E1000_READ_REG(hw, E1000_RPTHC);
2938         stats->hgptc += E1000_READ_REG(hw, E1000_HGPTC);
2939         stats->htcbdpc += E1000_READ_REG(hw, E1000_HTCBDPC);
2940         stats->hgorc += (E1000_READ_REG(hw, E1000_HGORCL) +
2941             ((uint64_t)E1000_READ_REG(hw, E1000_HGORCH) << 32));
2942         stats->hgotc += (E1000_READ_REG(hw, E1000_HGOTCL) +
2943             ((uint64_t)E1000_READ_REG(hw, E1000_HGOTCH) << 32));
2944         stats->lenerrs += E1000_READ_REG(hw, E1000_LENERRS);
2945         stats->scvpc += E1000_READ_REG(hw, E1000_SCVPC);
2946         stats->hrmpc += E1000_READ_REG(hw, E1000_HRMPC);
2947
2948         stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
2949         stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
2950         stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
2951         stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
2952         stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
2953         stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
2954
2955         ifp->if_collisions = stats->colc;
2956
2957         /* Rx Errors */
2958         ifp->if_ierrors = stats->rxerrc + stats->crcerrs + stats->algnerrc +
2959             stats->ruc + stats->roc + stats->mpc + stats->cexterr;
2960
2961         /* Tx Errors */
2962         ifp->if_oerrors = stats->ecol + stats->latecol + sc->watchdog_events;
2963
2964         /* Driver specific counters */
2965         sc->device_control = E1000_READ_REG(hw, E1000_CTRL);
2966         sc->rx_control = E1000_READ_REG(hw, E1000_RCTL);
2967         sc->int_mask = E1000_READ_REG(hw, E1000_IMS);
2968         sc->eint_mask = E1000_READ_REG(hw, E1000_EIMS);
2969         sc->packet_buf_alloc_tx =
2970             ((E1000_READ_REG(hw, E1000_PBA) & 0xffff0000) >> 16);
2971         sc->packet_buf_alloc_rx =
2972             (E1000_READ_REG(hw, E1000_PBA) & 0xffff);
2973 }
2974
2975 static void
2976 igb_vf_init_stats(struct igb_softc *sc)
2977 {
2978         struct e1000_hw *hw = &sc->hw;
2979         struct e1000_vf_stats *stats;
2980
2981         stats = sc->stats;
2982         stats->last_gprc = E1000_READ_REG(hw, E1000_VFGPRC);
2983         stats->last_gorc = E1000_READ_REG(hw, E1000_VFGORC);
2984         stats->last_gptc = E1000_READ_REG(hw, E1000_VFGPTC);
2985         stats->last_gotc = E1000_READ_REG(hw, E1000_VFGOTC);
2986         stats->last_mprc = E1000_READ_REG(hw, E1000_VFMPRC);
2987 }
2988  
2989 static void
2990 igb_update_vf_stats_counters(struct igb_softc *sc)
2991 {
2992         struct e1000_hw *hw = &sc->hw;
2993         struct e1000_vf_stats *stats;
2994
2995         if (sc->link_speed == 0)
2996                 return;
2997
2998         stats = sc->stats;
2999         UPDATE_VF_REG(E1000_VFGPRC, stats->last_gprc, stats->gprc);
3000         UPDATE_VF_REG(E1000_VFGORC, stats->last_gorc, stats->gorc);
3001         UPDATE_VF_REG(E1000_VFGPTC, stats->last_gptc, stats->gptc);
3002         UPDATE_VF_REG(E1000_VFGOTC, stats->last_gotc, stats->gotc);
3003         UPDATE_VF_REG(E1000_VFMPRC, stats->last_mprc, stats->mprc);
3004 }
3005
3006 #ifdef IFPOLL_ENABLE
3007
3008 static void
3009 igb_npoll_status(struct ifnet *ifp)
3010 {
3011         struct igb_softc *sc = ifp->if_softc;
3012         uint32_t reg_icr;
3013
3014         ASSERT_SERIALIZED(&sc->main_serialize);
3015
3016         reg_icr = E1000_READ_REG(&sc->hw, E1000_ICR);
3017         if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
3018                 sc->hw.mac.get_link_status = 1;
3019                 igb_update_link_status(sc);
3020         }
3021 }
3022
3023 static void
3024 igb_npoll_tx(struct ifnet *ifp, void *arg, int cycle __unused)
3025 {
3026         struct igb_tx_ring *txr = arg;
3027
3028         ASSERT_SERIALIZED(&txr->tx_serialize);
3029
3030         igb_txeof(txr);
3031         if (!ifsq_is_empty(txr->ifsq))
3032                 ifsq_devstart(txr->ifsq);
3033 }
3034
3035 static void
3036 igb_npoll_rx(struct ifnet *ifp __unused, void *arg, int cycle)
3037 {
3038         struct igb_rx_ring *rxr = arg;
3039
3040         ASSERT_SERIALIZED(&rxr->rx_serialize);
3041
3042         igb_rxeof(rxr, cycle);
3043 }
3044
3045 static void
3046 igb_npoll(struct ifnet *ifp, struct ifpoll_info *info)
3047 {
3048         struct igb_softc *sc = ifp->if_softc;
3049         int i, txr_cnt, rxr_cnt;
3050
3051         ASSERT_IFNET_SERIALIZED_ALL(ifp);
3052
3053         if (info) {
3054                 int off;
3055
3056                 info->ifpi_status.status_func = igb_npoll_status;
3057                 info->ifpi_status.serializer = &sc->main_serialize;
3058
3059                 txr_cnt = igb_get_txring_inuse(sc, TRUE);
3060                 off = sc->tx_npoll_off;
3061                 for (i = 0; i < txr_cnt; ++i) {
3062                         struct igb_tx_ring *txr = &sc->tx_rings[i];
3063                         int idx = i + off;
3064
3065                         KKASSERT(idx < ncpus2);
3066                         info->ifpi_tx[idx].poll_func = igb_npoll_tx;
3067                         info->ifpi_tx[idx].arg = txr;
3068                         info->ifpi_tx[idx].serializer = &txr->tx_serialize;
3069                         ifsq_set_cpuid(txr->ifsq, idx);
3070                 }
3071
3072                 rxr_cnt = igb_get_rxring_inuse(sc, TRUE);
3073                 off = sc->rx_npoll_off;
3074                 for (i = 0; i < rxr_cnt; ++i) {
3075                         struct igb_rx_ring *rxr = &sc->rx_rings[i];
3076                         int idx = i + off;
3077
3078                         KKASSERT(idx < ncpus2);
3079                         info->ifpi_rx[idx].poll_func = igb_npoll_rx;
3080                         info->ifpi_rx[idx].arg = rxr;
3081                         info->ifpi_rx[idx].serializer = &rxr->rx_serialize;
3082                 }
3083
3084                 if (ifp->if_flags & IFF_RUNNING) {
3085                         if (rxr_cnt == sc->rx_ring_inuse &&
3086                             txr_cnt == sc->tx_ring_inuse)
3087                                 igb_disable_intr(sc);
3088                         else
3089                                 igb_init(sc);
3090                 }
3091         } else {
3092                 for (i = 0; i < sc->tx_ring_cnt; ++i) {
3093                         struct igb_tx_ring *txr = &sc->tx_rings[i];
3094
3095                         ifsq_set_cpuid(txr->ifsq, txr->tx_intr_cpuid);
3096                 }
3097
3098                 if (ifp->if_flags & IFF_RUNNING) {
3099                         txr_cnt = igb_get_txring_inuse(sc, FALSE);
3100                         rxr_cnt = igb_get_rxring_inuse(sc, FALSE);
3101
3102                         if (rxr_cnt == sc->rx_ring_inuse &&
3103                             txr_cnt == sc->tx_ring_inuse)
3104                                 igb_enable_intr(sc);
3105                         else
3106                                 igb_init(sc);
3107                 }
3108         }
3109 }
3110
3111 #endif /* IFPOLL_ENABLE */
3112
3113 static void
3114 igb_intr(void *xsc)
3115 {
3116         struct igb_softc *sc = xsc;
3117         struct ifnet *ifp = &sc->arpcom.ac_if;
3118         uint32_t eicr;
3119
3120         ASSERT_SERIALIZED(&sc->main_serialize);
3121
3122         eicr = E1000_READ_REG(&sc->hw, E1000_EICR);
3123
3124         if (eicr == 0)
3125                 return;
3126
3127         if (ifp->if_flags & IFF_RUNNING) {
3128                 struct igb_tx_ring *txr = &sc->tx_rings[0];
3129                 int i;
3130
3131                 for (i = 0; i < sc->rx_ring_inuse; ++i) {
3132                         struct igb_rx_ring *rxr = &sc->rx_rings[i];
3133
3134                         if (eicr & rxr->rx_intr_mask) {
3135                                 lwkt_serialize_enter(&rxr->rx_serialize);
3136                                 igb_rxeof(rxr, -1);
3137                                 lwkt_serialize_exit(&rxr->rx_serialize);
3138                         }
3139                 }
3140
3141                 if (eicr & txr->tx_intr_mask) {
3142                         lwkt_serialize_enter(&txr->tx_serialize);
3143                         igb_txeof(txr);
3144                         if (!ifsq_is_empty(txr->ifsq))
3145                                 ifsq_devstart(txr->ifsq);
3146                         lwkt_serialize_exit(&txr->tx_serialize);
3147                 }
3148         }
3149
3150         if (eicr & E1000_EICR_OTHER) {
3151                 uint32_t icr = E1000_READ_REG(&sc->hw, E1000_ICR);
3152
3153                 /* Link status change */
3154                 if (icr & E1000_ICR_LSC) {
3155                         sc->hw.mac.get_link_status = 1;
3156                         igb_update_link_status(sc);
3157                 }
3158         }
3159
3160         /*
3161          * Reading EICR has the side effect to clear interrupt mask,
3162          * so all interrupts need to be enabled here.
3163          */
3164         E1000_WRITE_REG(&sc->hw, E1000_EIMS, sc->intr_mask);
3165 }
3166
3167 static void
3168 igb_intr_shared(void *xsc)
3169 {
3170         struct igb_softc *sc = xsc;
3171         struct ifnet *ifp = &sc->arpcom.ac_if;
3172         uint32_t reg_icr;
3173
3174         ASSERT_SERIALIZED(&sc->main_serialize);
3175
3176         reg_icr = E1000_READ_REG(&sc->hw, E1000_ICR);
3177
3178         /* Hot eject?  */
3179         if (reg_icr == 0xffffffff)
3180                 return;
3181
3182         /* Definitely not our interrupt.  */
3183         if (reg_icr == 0x0)
3184                 return;
3185
3186         if ((reg_icr & E1000_ICR_INT_ASSERTED) == 0)
3187                 return;
3188
3189         if (ifp->if_flags & IFF_RUNNING) {
3190                 if (reg_icr &
3191                     (E1000_ICR_RXT0 | E1000_ICR_RXDMT0 | E1000_ICR_RXO)) {
3192                         int i;
3193
3194                         for (i = 0; i < sc->rx_ring_inuse; ++i) {
3195                                 struct igb_rx_ring *rxr = &sc->rx_rings[i];
3196
3197                                 lwkt_serialize_enter(&rxr->rx_serialize);
3198                                 igb_rxeof(rxr, -1);
3199                                 lwkt_serialize_exit(&rxr->rx_serialize);
3200                         }
3201                 }
3202
3203                 if (reg_icr & E1000_ICR_TXDW) {
3204                         struct igb_tx_ring *txr = &sc->tx_rings[0];
3205
3206                         lwkt_serialize_enter(&txr->tx_serialize);
3207                         igb_txeof(txr);
3208                         if (!ifsq_is_empty(txr->ifsq))
3209                                 ifsq_devstart(txr->ifsq);
3210                         lwkt_serialize_exit(&txr->tx_serialize);
3211                 }
3212         }
3213
3214         /* Link status change */
3215         if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
3216                 sc->hw.mac.get_link_status = 1;
3217                 igb_update_link_status(sc);
3218         }
3219
3220         if (reg_icr & E1000_ICR_RXO)
3221                 sc->rx_overruns++;
3222 }
3223
3224 static int
3225 igb_encap(struct igb_tx_ring *txr, struct mbuf **m_headp,
3226     int *segs_used, int *idx)
3227 {
3228         bus_dma_segment_t segs[IGB_MAX_SCATTER];
3229         bus_dmamap_t map;
3230         struct igb_tx_buf *tx_buf, *tx_buf_mapped;
3231         union e1000_adv_tx_desc *txd = NULL;
3232         struct mbuf *m_head = *m_headp;
3233         uint32_t olinfo_status = 0, cmd_type_len = 0, cmd_rs = 0;
3234         int maxsegs, nsegs, i, j, error;
3235         uint32_t hdrlen = 0;
3236
3237         if (m_head->m_pkthdr.csum_flags & CSUM_TSO) {
3238                 error = igb_tso_pullup(txr, m_headp);
3239                 if (error)
3240                         return error;
3241                 m_head = *m_headp;
3242         }
3243
3244         /* Set basic descriptor constants */
3245         cmd_type_len |= E1000_ADVTXD_DTYP_DATA;
3246         cmd_type_len |= E1000_ADVTXD_DCMD_IFCS | E1000_ADVTXD_DCMD_DEXT;
3247         if (m_head->m_flags & M_VLANTAG)
3248                 cmd_type_len |= E1000_ADVTXD_DCMD_VLE;
3249
3250         /*
3251          * Map the packet for DMA.
3252          */
3253         tx_buf = &txr->tx_buf[txr->next_avail_desc];
3254         tx_buf_mapped = tx_buf;
3255         map = tx_buf->map;
3256
3257         maxsegs = txr->tx_avail - IGB_TX_RESERVED;
3258         KASSERT(maxsegs >= txr->spare_desc, ("not enough spare TX desc\n"));
3259         if (maxsegs > IGB_MAX_SCATTER)
3260                 maxsegs = IGB_MAX_SCATTER;
3261
3262         error = bus_dmamap_load_mbuf_defrag(txr->tx_tag, map, m_headp,
3263             segs, maxsegs, &nsegs, BUS_DMA_NOWAIT);
3264         if (error) {
3265                 if (error == ENOBUFS)
3266                         txr->sc->mbuf_defrag_failed++;
3267                 else
3268                         txr->sc->no_tx_dma_setup++;
3269
3270                 m_freem(*m_headp);
3271                 *m_headp = NULL;
3272                 return error;
3273         }
3274         bus_dmamap_sync(txr->tx_tag, map, BUS_DMASYNC_PREWRITE);
3275
3276         m_head = *m_headp;
3277
3278         /*
3279          * Set up the TX context descriptor, if any hardware offloading is
3280          * needed.  This includes CSUM, VLAN, and TSO.  It will consume one
3281          * TX descriptor.
3282          *
3283          * Unlike these chips' predecessors (em/emx), TX context descriptor
3284          * will _not_ interfere TX data fetching pipelining.
3285          */
3286         if (m_head->m_pkthdr.csum_flags & CSUM_TSO) {
3287                 igb_tso_ctx(txr, m_head, &hdrlen);
3288                 cmd_type_len |= E1000_ADVTXD_DCMD_TSE;
3289                 olinfo_status |= E1000_TXD_POPTS_IXSM << 8;
3290                 olinfo_status |= E1000_TXD_POPTS_TXSM << 8;
3291                 txr->tx_nsegs++;
3292                 (*segs_used)++;
3293         } else if (igb_txcsum_ctx(txr, m_head)) {
3294                 if (m_head->m_pkthdr.csum_flags & CSUM_IP)
3295                         olinfo_status |= (E1000_TXD_POPTS_IXSM << 8);
3296                 if (m_head->m_pkthdr.csum_flags & (CSUM_UDP | CSUM_TCP))
3297                         olinfo_status |= (E1000_TXD_POPTS_TXSM << 8);
3298                 txr->tx_nsegs++;
3299                 (*segs_used)++;
3300         }
3301
3302         *segs_used += nsegs;
3303         txr->tx_nsegs += nsegs;
3304         if (txr->tx_nsegs >= txr->intr_nsegs) {
3305                 /*
3306                  * Report Status (RS) is turned on every intr_nsegs
3307                  * descriptors (roughly).
3308                  */
3309                 txr->tx_nsegs = 0;
3310                 cmd_rs = E1000_ADVTXD_DCMD_RS;
3311         }
3312
3313         /* Calculate payload length */
3314         olinfo_status |= ((m_head->m_pkthdr.len - hdrlen)
3315             << E1000_ADVTXD_PAYLEN_SHIFT);
3316
3317         /* 82575 needs the queue index added */
3318         if (txr->sc->hw.mac.type == e1000_82575)
3319                 olinfo_status |= txr->me << 4;
3320
3321         /* Set up our transmit descriptors */
3322         i = txr->next_avail_desc;
3323         for (j = 0; j < nsegs; j++) {
3324                 bus_size_t seg_len;
3325                 bus_addr_t seg_addr;
3326
3327                 tx_buf = &txr->tx_buf[i];
3328                 txd = (union e1000_adv_tx_desc *)&txr->tx_base[i];
3329                 seg_addr = segs[j].ds_addr;
3330                 seg_len = segs[j].ds_len;
3331
3332                 txd->read.buffer_addr = htole64(seg_addr);
3333                 txd->read.cmd_type_len = htole32(cmd_type_len | seg_len);
3334                 txd->read.olinfo_status = htole32(olinfo_status);
3335                 if (++i == txr->num_tx_desc)
3336                         i = 0;
3337                 tx_buf->m_head = NULL;
3338         }
3339
3340         KASSERT(txr->tx_avail > nsegs, ("invalid avail TX desc\n"));
3341         txr->next_avail_desc = i;
3342         txr->tx_avail -= nsegs;
3343
3344         tx_buf->m_head = m_head;
3345         tx_buf_mapped->map = tx_buf->map;
3346         tx_buf->map = map;
3347
3348         /*
3349          * Last Descriptor of Packet needs End Of Packet (EOP)
3350          */
3351         txd->read.cmd_type_len |= htole32(E1000_ADVTXD_DCMD_EOP | cmd_rs);
3352
3353         /*
3354          * Defer TDT updating, until enough descrptors are setup
3355          */
3356         *idx = i;
3357         ++txr->tx_packets;
3358
3359         return 0;
3360 }
3361
3362 static void
3363 igb_start(struct ifnet *ifp, struct ifaltq_subque *ifsq)
3364 {
3365         struct igb_softc *sc = ifp->if_softc;
3366         struct igb_tx_ring *txr = ifsq_get_priv(ifsq);
3367         struct mbuf *m_head;
3368         int idx = -1, nsegs = 0;
3369
3370         KKASSERT(txr->ifsq == ifsq);
3371         ASSERT_SERIALIZED(&txr->tx_serialize);
3372
3373         if ((ifp->if_flags & IFF_RUNNING) == 0 || ifsq_is_oactive(ifsq))
3374                 return;
3375
3376         if (!sc->link_active || (txr->tx_flags & IGB_TXFLAG_ENABLED) == 0) {
3377                 ifsq_purge(ifsq);
3378                 return;
3379         }
3380
3381         if (!IGB_IS_NOT_OACTIVE(txr))
3382                 igb_txeof(txr);
3383
3384         while (!ifsq_is_empty(ifsq)) {
3385                 if (IGB_IS_OACTIVE(txr)) {
3386                         ifsq_set_oactive(ifsq);
3387                         /* Set watchdog on */
3388                         txr->tx_watchdog.wd_timer = 5;
3389                         break;
3390                 }
3391
3392                 m_head = ifsq_dequeue(ifsq, NULL);
3393                 if (m_head == NULL)
3394                         break;
3395
3396                 if (igb_encap(txr, &m_head, &nsegs, &idx)) {
3397                         ifp->if_oerrors++;
3398                         continue;
3399                 }
3400
3401                 if (nsegs >= txr->wreg_nsegs) {
3402                         E1000_WRITE_REG(&txr->sc->hw, E1000_TDT(txr->me), idx);
3403                         idx = -1;
3404                         nsegs = 0;
3405                 }
3406
3407                 /* Send a copy of the frame to the BPF listener */
3408                 ETHER_BPF_MTAP(ifp, m_head);
3409         }
3410         if (idx >= 0)
3411                 E1000_WRITE_REG(&txr->sc->hw, E1000_TDT(txr->me), idx);
3412 }
3413
3414 static void
3415 igb_watchdog(struct ifaltq_subque *ifsq)
3416 {
3417         struct igb_tx_ring *txr = ifsq_get_priv(ifsq);
3418         struct ifnet *ifp = ifsq_get_ifp(ifsq);
3419         struct igb_softc *sc = ifp->if_softc;
3420         int i;
3421
3422         KKASSERT(txr->ifsq == ifsq);
3423         ASSERT_IFNET_SERIALIZED_ALL(ifp);
3424
3425         /* 
3426          * If flow control has paused us since last checking
3427          * it invalidates the watchdog timing, so dont run it.
3428          */
3429         if (sc->pause_frames) {
3430                 sc->pause_frames = 0;
3431                 txr->tx_watchdog.wd_timer = 5;
3432                 return;
3433         }
3434
3435         if_printf(ifp, "Watchdog timeout -- resetting\n");
3436         if_printf(ifp, "Queue(%d) tdh = %d, hw tdt = %d\n", txr->me,
3437             E1000_READ_REG(&sc->hw, E1000_TDH(txr->me)),
3438             E1000_READ_REG(&sc->hw, E1000_TDT(txr->me)));
3439         if_printf(ifp, "TX(%d) desc avail = %d, "
3440             "Next TX to Clean = %d\n",
3441             txr->me, txr->tx_avail, txr->next_to_clean);
3442
3443         ifp->if_oerrors++;
3444         sc->watchdog_events++;
3445
3446         igb_init(sc);
3447         for (i = 0; i < sc->tx_ring_inuse; ++i)
3448                 ifsq_devstart_sched(sc->tx_rings[i].ifsq);
3449 }
3450
3451 static void
3452 igb_set_eitr(struct igb_softc *sc, int idx, int rate)
3453 {
3454         uint32_t eitr = 0;
3455
3456         if (rate > 0) {
3457                 if (sc->hw.mac.type == e1000_82575) {
3458                         eitr = 1000000000 / 256 / rate;
3459                         /*
3460                          * NOTE:
3461                          * Document is wrong on the 2 bits left shift
3462                          */
3463                 } else {
3464                         eitr = 1000000 / rate;
3465                         eitr <<= IGB_EITR_INTVL_SHIFT;
3466                 }
3467
3468                 if (eitr == 0) {
3469                         /* Don't disable it */
3470                         eitr = 1 << IGB_EITR_INTVL_SHIFT;
3471                 } else if (eitr > IGB_EITR_INTVL_MASK) {
3472                         /* Don't allow it to be too large */
3473                         eitr = IGB_EITR_INTVL_MASK;
3474                 }
3475         }
3476         if (sc->hw.mac.type == e1000_82575)
3477                 eitr |= eitr << 16;
3478         else
3479                 eitr |= E1000_EITR_CNT_IGNR;
3480         E1000_WRITE_REG(&sc->hw, E1000_EITR(idx), eitr);
3481 }
3482
3483 static int
3484 igb_sysctl_intr_rate(SYSCTL_HANDLER_ARGS)
3485 {
3486         struct igb_softc *sc = (void *)arg1;
3487         struct ifnet *ifp = &sc->arpcom.ac_if;
3488         int error, intr_rate;
3489
3490         intr_rate = sc->intr_rate;
3491         error = sysctl_handle_int(oidp, &intr_rate, 0, req);
3492         if (error || req->newptr == NULL)
3493                 return error;
3494         if (intr_rate < 0)
3495                 return EINVAL;
3496
3497         ifnet_serialize_all(ifp);
3498
3499         sc->intr_rate = intr_rate;
3500         if (ifp->if_flags & IFF_RUNNING)
3501                 igb_set_eitr(sc, 0, sc->intr_rate);
3502
3503         if (bootverbose)
3504                 if_printf(ifp, "interrupt rate set to %d/sec\n", sc->intr_rate);
3505
3506         ifnet_deserialize_all(ifp);
3507
3508         return 0;
3509 }
3510
3511 static int
3512 igb_sysctl_msix_rate(SYSCTL_HANDLER_ARGS)
3513 {
3514         struct igb_msix_data *msix = (void *)arg1;
3515         struct igb_softc *sc = msix->msix_sc;
3516         struct ifnet *ifp = &sc->arpcom.ac_if;
3517         int error, msix_rate;
3518
3519         msix_rate = msix->msix_rate;
3520         error = sysctl_handle_int(oidp, &msix_rate, 0, req);
3521         if (error || req->newptr == NULL)
3522                 return error;
3523         if (msix_rate < 0)
3524                 return EINVAL;
3525
3526         lwkt_serialize_enter(msix->msix_serialize);
3527
3528         msix->msix_rate = msix_rate;
3529         if (ifp->if_flags & IFF_RUNNING)
3530                 igb_set_eitr(sc, msix->msix_vector, msix->msix_rate);
3531
3532         if (bootverbose) {
3533                 if_printf(ifp, "%s set to %d/sec\n", msix->msix_rate_desc,
3534                     msix->msix_rate);
3535         }
3536
3537         lwkt_serialize_exit(msix->msix_serialize);
3538
3539         return 0;
3540 }
3541
3542 static int
3543 igb_sysctl_tx_intr_nsegs(SYSCTL_HANDLER_ARGS)
3544 {
3545         struct igb_softc *sc = (void *)arg1;
3546         struct ifnet *ifp = &sc->arpcom.ac_if;
3547         struct igb_tx_ring *txr = &sc->tx_rings[0];
3548         int error, nsegs;
3549
3550         nsegs = txr->intr_nsegs;
3551         error = sysctl_handle_int(oidp, &nsegs, 0, req);
3552         if (error || req->newptr == NULL)
3553                 return error;
3554         if (nsegs <= 0)
3555                 return EINVAL;
3556
3557         ifnet_serialize_all(ifp);
3558
3559         if (nsegs >= txr->num_tx_desc - txr->oact_lo_desc ||
3560             nsegs >= txr->oact_hi_desc - IGB_MAX_SCATTER) {
3561                 error = EINVAL;
3562         } else {
3563                 int i;
3564
3565                 error = 0;
3566                 for (i = 0; i < sc->tx_ring_cnt; ++i)
3567                         sc->tx_rings[i].intr_nsegs = nsegs;
3568         }
3569
3570         ifnet_deserialize_all(ifp);
3571
3572         return error;
3573 }
3574
3575 static int
3576 igb_sysctl_rx_wreg_nsegs(SYSCTL_HANDLER_ARGS)
3577 {
3578         struct igb_softc *sc = (void *)arg1;
3579         struct ifnet *ifp = &sc->arpcom.ac_if;
3580         int error, nsegs, i;
3581
3582         nsegs = sc->rx_rings[0].wreg_nsegs;
3583         error = sysctl_handle_int(oidp, &nsegs, 0, req);
3584         if (error || req->newptr == NULL)
3585                 return error;
3586
3587         ifnet_serialize_all(ifp);
3588         for (i = 0; i < sc->rx_ring_cnt; ++i)
3589                 sc->rx_rings[i].wreg_nsegs =nsegs;
3590         ifnet_deserialize_all(ifp);
3591
3592         return 0;
3593 }
3594
3595 static int
3596 igb_sysctl_tx_wreg_nsegs(SYSCTL_HANDLER_ARGS)
3597 {
3598         struct igb_softc *sc = (void *)arg1;
3599         struct ifnet *ifp = &sc->arpcom.ac_if;
3600         int error, nsegs, i;
3601
3602         nsegs = sc->tx_rings[0].wreg_nsegs;
3603         error = sysctl_handle_int(oidp, &nsegs, 0, req);
3604         if (error || req->newptr == NULL)
3605                 return error;
3606
3607         ifnet_serialize_all(ifp);
3608         for (i = 0; i < sc->tx_ring_cnt; ++i)
3609                 sc->tx_rings[i].wreg_nsegs =nsegs;
3610         ifnet_deserialize_all(ifp);
3611
3612         return 0;
3613 }
3614
3615 #ifdef IFPOLL_ENABLE
3616
3617 static int
3618 igb_sysctl_npoll_rxoff(SYSCTL_HANDLER_ARGS)
3619 {
3620         struct igb_softc *sc = (void *)arg1;
3621         struct ifnet *ifp = &sc->arpcom.ac_if;
3622         int error, off;
3623
3624         off = sc->rx_npoll_off;
3625         error = sysctl_handle_int(oidp, &off, 0, req);
3626         if (error || req->newptr == NULL)
3627                 return error;
3628         if (off < 0)
3629                 return EINVAL;
3630
3631         ifnet_serialize_all(ifp);
3632         if (off >= ncpus2 || off % sc->rx_ring_cnt != 0) {
3633                 error = EINVAL;
3634         } else {
3635                 error = 0;
3636                 sc->rx_npoll_off = off;
3637         }
3638         ifnet_deserialize_all(ifp);
3639
3640         return error;
3641 }
3642
3643 static int
3644 igb_sysctl_npoll_txoff(SYSCTL_HANDLER_ARGS)
3645 {
3646         struct igb_softc *sc = (void *)arg1;
3647         struct ifnet *ifp = &sc->arpcom.ac_if;
3648         int error, off;
3649
3650         off = sc->tx_npoll_off;
3651         error = sysctl_handle_int(oidp, &off, 0, req);
3652         if (error || req->newptr == NULL)
3653                 return error;
3654         if (off < 0)
3655                 return EINVAL;
3656
3657         ifnet_serialize_all(ifp);
3658         if (off >= ncpus2 || off % sc->tx_ring_cnt != 0) {
3659                 error = EINVAL;
3660         } else {
3661                 error = 0;
3662                 sc->tx_npoll_off = off;
3663         }
3664         ifnet_deserialize_all(ifp);
3665
3666         return error;
3667 }
3668
3669 #endif  /* IFPOLL_ENABLE */
3670
3671 static void
3672 igb_init_intr(struct igb_softc *sc)
3673 {
3674         igb_set_intr_mask(sc);
3675
3676         if ((sc->flags & IGB_FLAG_SHARED_INTR) == 0)
3677                 igb_init_unshared_intr(sc);
3678
3679         if (sc->intr_type != PCI_INTR_TYPE_MSIX) {
3680                 igb_set_eitr(sc, 0, sc->intr_rate);
3681         } else {
3682                 int i;
3683
3684                 for (i = 0; i < sc->msix_cnt; ++i)
3685                         igb_set_eitr(sc, i, sc->msix_data[i].msix_rate);
3686         }
3687 }
3688
3689 static void
3690 igb_init_unshared_intr(struct igb_softc *sc)
3691 {
3692         struct e1000_hw *hw = &sc->hw;
3693         const struct igb_rx_ring *rxr;
3694         const struct igb_tx_ring *txr;
3695         uint32_t ivar, index;
3696         int i;
3697
3698         /*
3699          * Enable extended mode
3700          */
3701         if (sc->hw.mac.type != e1000_82575) {
3702                 uint32_t gpie;
3703                 int ivar_max;
3704
3705                 gpie = E1000_GPIE_NSICR;
3706                 if (sc->intr_type == PCI_INTR_TYPE_MSIX) {
3707                         gpie |= E1000_GPIE_MSIX_MODE |
3708                             E1000_GPIE_EIAME |
3709                             E1000_GPIE_PBA;
3710                 }
3711                 E1000_WRITE_REG(hw, E1000_GPIE, gpie);
3712
3713                 /*
3714                  * Clear IVARs
3715                  */
3716                 switch (sc->hw.mac.type) {
3717                 case e1000_82580:
3718                         ivar_max = IGB_MAX_IVAR_82580;
3719                         break;
3720
3721                 case e1000_i350:
3722                         ivar_max = IGB_MAX_IVAR_I350;
3723                         break;
3724
3725                 case e1000_vfadapt:
3726                 case e1000_vfadapt_i350:
3727                         ivar_max = IGB_MAX_IVAR_VF;
3728                         break;
3729
3730                 case e1000_82576:
3731                         ivar_max = IGB_MAX_IVAR_82576;
3732                         break;
3733
3734                 default:
3735                         panic("unknown mac type %d\n", sc->hw.mac.type);
3736                 }
3737                 for (i = 0; i < ivar_max; ++i)
3738                         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, i, 0);
3739                 E1000_WRITE_REG(hw, E1000_IVAR_MISC, 0);
3740         } else {
3741                 uint32_t tmp;
3742
3743                 KASSERT(sc->intr_type != PCI_INTR_TYPE_MSIX,
3744                     ("82575 w/ MSI-X"));
3745                 tmp = E1000_READ_REG(hw, E1000_CTRL_EXT);
3746                 tmp |= E1000_CTRL_EXT_IRCA;
3747                 E1000_WRITE_REG(hw, E1000_CTRL_EXT, tmp);
3748         }
3749
3750         /*
3751          * Map TX/RX interrupts to EICR
3752          */
3753         switch (sc->hw.mac.type) {
3754         case e1000_82580:
3755         case e1000_i350:
3756         case e1000_vfadapt:
3757         case e1000_vfadapt_i350:
3758                 /* RX entries */
3759                 for (i = 0; i < sc->rx_ring_inuse; ++i) {
3760                         rxr = &sc->rx_rings[i];
3761
3762                         index = i >> 1;
3763                         ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
3764
3765                         if (i & 1) {
3766                                 ivar &= 0xff00ffff;
3767                                 ivar |=
3768                                 (rxr->rx_intr_bit | E1000_IVAR_VALID) << 16;
3769                         } else {
3770                                 ivar &= 0xffffff00;
3771                                 ivar |=
3772                                 (rxr->rx_intr_bit | E1000_IVAR_VALID);
3773                         }
3774                         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
3775                 }
3776                 /* TX entries */
3777                 for (i = 0; i < sc->tx_ring_inuse; ++i) {
3778                         txr = &sc->tx_rings[i];
3779
3780                         index = i >> 1;
3781                         ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
3782
3783                         if (i & 1) {
3784                                 ivar &= 0x00ffffff;
3785                                 ivar |=
3786                                 (txr->tx_intr_bit | E1000_IVAR_VALID) << 24;
3787                         } else {
3788                                 ivar &= 0xffff00ff;
3789                                 ivar |=
3790                                 (txr->tx_intr_bit | E1000_IVAR_VALID) << 8;
3791                         }
3792                         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
3793                 }
3794                 if (sc->intr_type == PCI_INTR_TYPE_MSIX) {
3795                         ivar = (sc->sts_intr_bit | E1000_IVAR_VALID) << 8;
3796                         E1000_WRITE_REG(hw, E1000_IVAR_MISC, ivar);
3797                 }
3798                 break;
3799
3800         case e1000_82576:
3801                 /* RX entries */
3802                 for (i = 0; i < sc->rx_ring_inuse; ++i) {
3803                         rxr = &sc->rx_rings[i];
3804
3805                         index = i & 0x7; /* Each IVAR has two entries */
3806                         ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
3807
3808                         if (i < 8) {
3809                                 ivar &= 0xffffff00;
3810                                 ivar |=
3811                                 (rxr->rx_intr_bit | E1000_IVAR_VALID);
3812                         } else {
3813                                 ivar &= 0xff00ffff;
3814                                 ivar |=
3815                                 (rxr->rx_intr_bit | E1000_IVAR_VALID) << 16;
3816                         }
3817                         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
3818                 }
3819                 /* TX entries */
3820                 for (i = 0; i < sc->tx_ring_inuse; ++i) {
3821                         txr = &sc->tx_rings[i];
3822
3823                         index = i & 0x7; /* Each IVAR has two entries */
3824                         ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
3825
3826                         if (i < 8) {
3827                                 ivar &= 0xffff00ff;
3828                                 ivar |=
3829                                 (txr->tx_intr_bit | E1000_IVAR_VALID) << 8;
3830                         } else {
3831                                 ivar &= 0x00ffffff;
3832                                 ivar |=
3833                                 (txr->tx_intr_bit | E1000_IVAR_VALID) << 24;
3834                         }
3835                         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
3836                 }
3837                 if (sc->intr_type == PCI_INTR_TYPE_MSIX) {
3838                         ivar = (sc->sts_intr_bit | E1000_IVAR_VALID) << 8;
3839                         E1000_WRITE_REG(hw, E1000_IVAR_MISC, ivar);
3840                 }
3841                 break;
3842
3843         case e1000_82575:
3844                 /*
3845                  * Enable necessary interrupt bits.
3846                  *
3847                  * The name of the register is confusing; in addition to
3848                  * configuring the first vector of MSI-X, it also configures
3849                  * which bits of EICR could be set by the hardware even when
3850                  * MSI or line interrupt is used; it thus controls interrupt
3851                  * generation.  It MUST be configured explicitly; the default
3852                  * value mentioned in the datasheet is wrong: RX queue0 and
3853                  * TX queue0 are NOT enabled by default.
3854                  */
3855                 E1000_WRITE_REG(&sc->hw, E1000_MSIXBM(0), sc->intr_mask);
3856                 break;
3857
3858         default:
3859                 panic("unknown mac type %d\n", sc->hw.mac.type);
3860         }
3861 }
3862
3863 static int
3864 igb_setup_intr(struct igb_softc *sc)
3865 {
3866         int error;
3867
3868         if (sc->intr_type == PCI_INTR_TYPE_MSIX)
3869                 return igb_msix_setup(sc);
3870
3871         error = bus_setup_intr(sc->dev, sc->intr_res, INTR_MPSAFE,
3872             (sc->flags & IGB_FLAG_SHARED_INTR) ? igb_intr_shared : igb_intr,
3873             sc, &sc->intr_tag, &sc->main_serialize);
3874         if (error) {
3875                 device_printf(sc->dev, "Failed to register interrupt handler");
3876                 return error;
3877         }
3878         sc->tx_rings[0].tx_intr_cpuid = rman_get_cpuid(sc->intr_res);
3879
3880         return 0;
3881 }
3882
3883 static void
3884 igb_set_txintr_mask(struct igb_tx_ring *txr, int *intr_bit0, int intr_bitmax)
3885 {
3886         if (txr->sc->hw.mac.type == e1000_82575) {
3887                 txr->tx_intr_bit = 0;   /* unused */
3888                 switch (txr->me) {
3889                 case 0:
3890                         txr->tx_intr_mask = E1000_EICR_TX_QUEUE0;
3891                         break;
3892                 case 1:
3893                         txr->tx_intr_mask = E1000_EICR_TX_QUEUE1;
3894                         break;
3895                 case 2:
3896                         txr->tx_intr_mask = E1000_EICR_TX_QUEUE2;
3897                         break;
3898                 case 3:
3899                         txr->tx_intr_mask = E1000_EICR_TX_QUEUE3;
3900                         break;
3901                 default:
3902                         panic("unsupported # of TX ring, %d\n", txr->me);
3903                 }
3904         } else {
3905                 int intr_bit = *intr_bit0;
3906
3907                 txr->tx_intr_bit = intr_bit % intr_bitmax;
3908                 txr->tx_intr_mask = 1 << txr->tx_intr_bit;
3909
3910                 *intr_bit0 = intr_bit + 1;
3911         }
3912 }
3913
3914 static void
3915 igb_set_rxintr_mask(struct igb_rx_ring *rxr, int *intr_bit0, int intr_bitmax)
3916 {
3917         if (rxr->sc->hw.mac.type == e1000_82575) {
3918                 rxr->rx_intr_bit = 0;   /* unused */
3919                 switch (rxr->me) {
3920                 case 0:
3921                         rxr->rx_intr_mask = E1000_EICR_RX_QUEUE0;
3922                         break;
3923                 case 1:
3924                         rxr->rx_intr_mask = E1000_EICR_RX_QUEUE1;
3925                         break;
3926                 case 2:
3927                         rxr->rx_intr_mask = E1000_EICR_RX_QUEUE2;
3928                         break;
3929                 case 3:
3930                         rxr->rx_intr_mask = E1000_EICR_RX_QUEUE3;
3931                         break;
3932                 default:
3933                         panic("unsupported # of RX ring, %d\n", rxr->me);
3934                 }
3935         } else {
3936                 int intr_bit = *intr_bit0;
3937
3938                 rxr->rx_intr_bit = intr_bit % intr_bitmax;
3939                 rxr->rx_intr_mask = 1 << rxr->rx_intr_bit;
3940
3941                 *intr_bit0 = intr_bit + 1;
3942         }
3943 }
3944
3945 static void
3946 igb_serialize(struct ifnet *ifp, enum ifnet_serialize slz)
3947 {
3948         struct igb_softc *sc = ifp->if_softc;
3949
3950         ifnet_serialize_array_enter(sc->serializes, sc->serialize_cnt,
3951             sc->tx_serialize, sc->rx_serialize, slz);
3952 }
3953
3954 static void
3955 igb_deserialize(struct ifnet *ifp, enum ifnet_serialize slz)
3956 {
3957         struct igb_softc *sc = ifp->if_softc;
3958
3959         ifnet_serialize_array_exit(sc->serializes, sc->serialize_cnt,
3960             sc->tx_serialize, sc->rx_serialize, slz);
3961 }
3962
3963 static int
3964 igb_tryserialize(struct ifnet *ifp, enum ifnet_serialize slz)
3965 {
3966         struct igb_softc *sc = ifp->if_softc;
3967
3968         return ifnet_serialize_array_try(sc->serializes, sc->serialize_cnt,
3969             sc->tx_serialize, sc->rx_serialize, slz);
3970 }
3971
3972 #ifdef INVARIANTS
3973
3974 static void
3975 igb_serialize_assert(struct ifnet *ifp, enum ifnet_serialize slz,
3976     boolean_t serialized)
3977 {
3978         struct igb_softc *sc = ifp->if_softc;
3979
3980         ifnet_serialize_array_assert(sc->serializes, sc->serialize_cnt,
3981             sc->tx_serialize, sc->rx_serialize, slz, serialized);
3982 }
3983
3984 #endif  /* INVARIANTS */
3985
3986 static void
3987 igb_set_intr_mask(struct igb_softc *sc)
3988 {
3989         int i;
3990
3991         sc->intr_mask = sc->sts_intr_mask;
3992         for (i = 0; i < sc->rx_ring_inuse; ++i)
3993                 sc->intr_mask |= sc->rx_rings[i].rx_intr_mask;
3994         for (i = 0; i < sc->tx_ring_inuse; ++i)
3995                 sc->intr_mask |= sc->tx_rings[i].tx_intr_mask;
3996         if (bootverbose) {
3997                 if_printf(&sc->arpcom.ac_if, "intr mask 0x%08x\n",
3998                     sc->intr_mask);
3999         }
4000 }
4001
4002 static int
4003 igb_alloc_intr(struct igb_softc *sc)
4004 {
4005         int i, intr_bit, intr_bitmax;
4006         u_int intr_flags;
4007
4008         igb_msix_try_alloc(sc);
4009         if (sc->intr_type == PCI_INTR_TYPE_MSIX)
4010                 goto done;
4011
4012         /*
4013          * Allocate MSI/legacy interrupt resource
4014          */
4015         sc->intr_type = pci_alloc_1intr(sc->dev, igb_msi_enable,
4016             &sc->intr_rid, &intr_flags);
4017
4018         if (sc->intr_type == PCI_INTR_TYPE_LEGACY) {
4019                 int unshared;
4020
4021                 unshared = device_getenv_int(sc->dev, "irq.unshared", 0);
4022                 if (!unshared) {
4023                         sc->flags |= IGB_FLAG_SHARED_INTR;
4024                         if (bootverbose)
4025                                 device_printf(sc->dev, "IRQ shared\n");
4026                 } else {
4027                         intr_flags &= ~RF_SHAREABLE;
4028                         if (bootverbose)
4029                                 device_printf(sc->dev, "IRQ unshared\n");
4030                 }
4031         }
4032
4033         sc->intr_res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ,
4034             &sc->intr_rid, intr_flags);
4035         if (sc->intr_res == NULL) {
4036                 device_printf(sc->dev, "Unable to allocate bus resource: "
4037                     "interrupt\n");
4038                 return ENXIO;
4039         }
4040
4041         /*
4042          * Setup MSI/legacy interrupt mask
4043          */
4044         switch (sc->hw.mac.type) {
4045         case e1000_82575:
4046                 intr_bitmax = IGB_MAX_TXRXINT_82575;
4047                 break;
4048         case e1000_82580:
4049                 intr_bitmax = IGB_MAX_TXRXINT_82580;
4050                 break;
4051         case e1000_i350:
4052                 intr_bitmax = IGB_MAX_TXRXINT_I350;
4053                 break;
4054         case e1000_82576:
4055                 intr_bitmax = IGB_MAX_TXRXINT_82576;
4056                 break;
4057         default:
4058                 intr_bitmax = IGB_MIN_TXRXINT;
4059                 break;
4060         }
4061         intr_bit = 0;
4062         for (i = 0; i < sc->tx_ring_cnt; ++i)
4063                 igb_set_txintr_mask(&sc->tx_rings[i], &intr_bit, intr_bitmax);
4064         for (i = 0; i < sc->rx_ring_cnt; ++i)
4065                 igb_set_rxintr_mask(&sc->rx_rings[i], &intr_bit, intr_bitmax);
4066         sc->sts_intr_bit = 0;
4067         sc->sts_intr_mask = E1000_EICR_OTHER;
4068
4069         /* Initialize interrupt rate */
4070         sc->intr_rate = IGB_INTR_RATE;
4071 done:
4072         igb_set_ring_inuse(sc, FALSE);
4073         igb_set_intr_mask(sc);