sys/dev/netif/jme/if_jme.c

   1 /*-
   2  * Copyright (c) 2008, Pyun YongHyeon <yongari@FreeBSD.org>
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions
   7  * are met:
   8  * 1. Redistributions of source code must retain the above copyright
   9  *    notice unmodified, this list of conditions, and the following
  10  *    disclaimer.
  11  * 2. Redistributions in binary form must reproduce the above copyright
  12  *    notice, this list of conditions and the following disclaimer in the
  13  *    documentation and/or other materials provided with the distribution.
  14  *
  15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  16  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  17  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  18  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  19  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  20  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  21  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  22  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  23  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  24  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  25  * SUCH DAMAGE.
  26  *
  27  * $FreeBSD: src/sys/dev/jme/if_jme.c,v 1.2 2008/07/18 04:20:48 yongari Exp $
  28  */
  29
  30 #include "opt_polling.h"
  31 #include "opt_jme.h"
  32
  33 #include <sys/param.h>
  34 #include <sys/endian.h>
  35 #include <sys/kernel.h>
  36 #include <sys/bus.h>
  37 #include <sys/interrupt.h>
  38 #include <sys/malloc.h>
  39 #include <sys/proc.h>
  40 #include <sys/rman.h>
  41 #include <sys/serialize.h>
  42 #include <sys/serialize2.h>
  43 #include <sys/socket.h>
  44 #include <sys/sockio.h>
  45 #include <sys/sysctl.h>
  46
  47 #include <net/ethernet.h>
  48 #include <net/if.h>
  49 #include <net/bpf.h>
  50 #include <net/if_arp.h>
  51 #include <net/if_dl.h>
  52 #include <net/if_media.h>
  53 #include <net/ifq_var.h>
  54 #include <net/toeplitz.h>
  55 #include <net/toeplitz2.h>
  56 #include <net/vlan/if_vlan_var.h>
  57 #include <net/vlan/if_vlan_ether.h>
  58
  59 #include <netinet/in.h>
  60
  61 #include <dev/netif/mii_layer/miivar.h>
  62 #include <dev/netif/mii_layer/jmphyreg.h>
  63
  64 #include <bus/pci/pcireg.h>
  65 #include <bus/pci/pcivar.h>
  66 #include <bus/pci/pcidevs.h>
  67
  68 #include <dev/netif/jme/if_jmereg.h>
  69 #include <dev/netif/jme/if_jmevar.h>
  70
  71 #include "miibus_if.h"
  72
  73 /* Define the following to disable printing Rx errors. */
  74 #undef  JME_SHOW_ERRORS
  75
  76 #define JME_CSUM_FEATURES       (CSUM_IP | CSUM_TCP | CSUM_UDP)
  77
  78 #ifdef JME_RSS_DEBUG
  79 #define JME_RSS_DPRINTF(sc, lvl, fmt, ...) \
  80 do { \
  81         if ((sc)->jme_rss_debug >= (lvl)) \
  82                 if_printf(&(sc)->arpcom.ac_if, fmt, __VA_ARGS__); \
  83 } while (0)
  84 #else   /* !JME_RSS_DEBUG */
  85 #define JME_RSS_DPRINTF(sc, lvl, fmt, ...)      ((void)0)
  86 #endif  /* JME_RSS_DEBUG */
  87
  88 static int      jme_probe(device_t);
  89 static int      jme_attach(device_t);
  90 static int      jme_detach(device_t);
  91 static int      jme_shutdown(device_t);
  92 static int      jme_suspend(device_t);
  93 static int      jme_resume(device_t);
  94
  95 static int      jme_miibus_readreg(device_t, int, int);
  96 static int      jme_miibus_writereg(device_t, int, int, int);
  97 static void     jme_miibus_statchg(device_t);
  98
  99 static void     jme_init(void *);
 100 static int      jme_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
 101 static void     jme_start(struct ifnet *);
 102 static void     jme_watchdog(struct ifnet *);
 103 static void     jme_mediastatus(struct ifnet *, struct ifmediareq *);
 104 static int      jme_mediachange(struct ifnet *);
 105 #ifdef DEVICE_POLLING
 106 static void     jme_poll(struct ifnet *, enum poll_cmd, int);
 107 #endif
 108 static void     jme_serialize(struct ifnet *, enum ifnet_serialize);
 109 static void     jme_deserialize(struct ifnet *, enum ifnet_serialize);
 110 static int      jme_tryserialize(struct ifnet *, enum ifnet_serialize);
 111 #ifdef INVARIANTS
 112 static void     jme_serialize_assert(struct ifnet *, enum ifnet_serialize,
 113                     boolean_t);
 114 #endif
 115
 116 static void     jme_intr(void *);
 117 static void     jme_msix_tx(void *);
 118 static void     jme_msix_rx(void *);
 119 static void     jme_txeof(struct jme_softc *);
 120 static void     jme_rxeof(struct jme_rxdata *, int);
 121 static void     jme_rx_intr(struct jme_softc *, uint32_t);
 122
 123 static int      jme_msix_setup(device_t);
 124 static void     jme_msix_teardown(device_t, int);
 125 static int      jme_intr_setup(device_t);
 126 static void     jme_intr_teardown(device_t);
 127 static void     jme_msix_try_alloc(device_t);
 128 static void     jme_msix_free(device_t);
 129 static int      jme_intr_alloc(device_t);
 130 static void     jme_intr_free(device_t);
 131 static int      jme_dma_alloc(struct jme_softc *);
 132 static void     jme_dma_free(struct jme_softc *);
 133 static int      jme_init_rx_ring(struct jme_rxdata *);
 134 static void     jme_init_tx_ring(struct jme_softc *);
 135 static void     jme_init_ssb(struct jme_softc *);
 136 static int      jme_newbuf(struct jme_rxdata *, struct jme_rxdesc *, int);
 137 static int      jme_encap(struct jme_softc *, struct mbuf **);
 138 static void     jme_rxpkt(struct jme_rxdata *);
 139 static int      jme_rxring_dma_alloc(struct jme_rxdata *);
 140 static int      jme_rxbuf_dma_alloc(struct jme_rxdata *);
 141
 142 static void     jme_tick(void *);
 143 static void     jme_stop(struct jme_softc *);
 144 static void     jme_reset(struct jme_softc *);
 145 static void     jme_set_msinum(struct jme_softc *);
 146 static void     jme_set_vlan(struct jme_softc *);
 147 static void     jme_set_filter(struct jme_softc *);
 148 static void     jme_stop_tx(struct jme_softc *);
 149 static void     jme_stop_rx(struct jme_softc *);
 150 static void     jme_mac_config(struct jme_softc *);
 151 static void     jme_reg_macaddr(struct jme_softc *, uint8_t[]);
 152 static int      jme_eeprom_macaddr(struct jme_softc *, uint8_t[]);
 153 static int      jme_eeprom_read_byte(struct jme_softc *, uint8_t, uint8_t *);
 154 #ifdef notyet
 155 static void     jme_setwol(struct jme_softc *);
 156 static void     jme_setlinkspeed(struct jme_softc *);
 157 #endif
 158 static void     jme_set_tx_coal(struct jme_softc *);
 159 static void     jme_set_rx_coal(struct jme_softc *);
 160 static void     jme_enable_rss(struct jme_softc *);
 161 static void     jme_disable_rss(struct jme_softc *);
 162
 163 static void     jme_sysctl_node(struct jme_softc *);
 164 static int      jme_sysctl_tx_coal_to(SYSCTL_HANDLER_ARGS);
 165 static int      jme_sysctl_tx_coal_pkt(SYSCTL_HANDLER_ARGS);
 166 static int      jme_sysctl_rx_coal_to(SYSCTL_HANDLER_ARGS);
 167 static int      jme_sysctl_rx_coal_pkt(SYSCTL_HANDLER_ARGS);
 168
 169 /*
 170  * Devices supported by this driver.
 171  */
 172 static const struct jme_dev {
 173         uint16_t        jme_vendorid;
 174         uint16_t        jme_deviceid;
 175         uint32_t        jme_caps;
 176         const char      *jme_name;
 177 } jme_devs[] = {
 178         { PCI_VENDOR_JMICRON, PCI_PRODUCT_JMICRON_JMC250,
 179             JME_CAP_JUMBO,
 180             "JMicron Inc, JMC250 Gigabit Ethernet" },
 181         { PCI_VENDOR_JMICRON, PCI_PRODUCT_JMICRON_JMC260,
 182             JME_CAP_FASTETH,
 183             "JMicron Inc, JMC260 Fast Ethernet" },
 184         { 0, 0, 0, NULL }
 185 };
 186
 187 static device_method_t jme_methods[] = {
 188         /* Device interface. */
 189         DEVMETHOD(device_probe,         jme_probe),
 190         DEVMETHOD(device_attach,        jme_attach),
 191         DEVMETHOD(device_detach,        jme_detach),
 192         DEVMETHOD(device_shutdown,      jme_shutdown),
 193         DEVMETHOD(device_suspend,       jme_suspend),
 194         DEVMETHOD(device_resume,        jme_resume),
 195
 196         /* Bus interface. */
 197         DEVMETHOD(bus_print_child,      bus_generic_print_child),
 198         DEVMETHOD(bus_driver_added,     bus_generic_driver_added),
 199
 200         /* MII interface. */
 201         DEVMETHOD(miibus_readreg,       jme_miibus_readreg),
 202         DEVMETHOD(miibus_writereg,      jme_miibus_writereg),
 203         DEVMETHOD(miibus_statchg,       jme_miibus_statchg),
 204
 205         { NULL, NULL }
 206 };
 207
 208 static driver_t jme_driver = {
 209         "jme",
 210         jme_methods,
 211         sizeof(struct jme_softc)
 212 };
 213
 214 static devclass_t jme_devclass;
 215
 216 DECLARE_DUMMY_MODULE(if_jme);
 217 MODULE_DEPEND(if_jme, miibus, 1, 1, 1);
 218 DRIVER_MODULE(if_jme, pci, jme_driver, jme_devclass, NULL, NULL);
 219 DRIVER_MODULE(miibus, jme, miibus_driver, miibus_devclass, NULL, NULL);
 220
 221 static const struct {
 222         uint32_t        jme_coal;
 223         uint32_t        jme_comp;
 224         uint32_t        jme_empty;
 225 } jme_rx_status[JME_NRXRING_MAX] = {
 226         { INTR_RXQ0_COAL | INTR_RXQ0_COAL_TO, INTR_RXQ0_COMP,
 227           INTR_RXQ0_DESC_EMPTY },
 228         { INTR_RXQ1_COAL | INTR_RXQ1_COAL_TO, INTR_RXQ1_COMP,
 229           INTR_RXQ1_DESC_EMPTY },
 230         { INTR_RXQ2_COAL | INTR_RXQ2_COAL_TO, INTR_RXQ2_COMP,
 231           INTR_RXQ2_DESC_EMPTY },
 232         { INTR_RXQ3_COAL | INTR_RXQ3_COAL_TO, INTR_RXQ3_COMP,
 233           INTR_RXQ3_DESC_EMPTY }
 234 };
 235
 236 static int      jme_rx_desc_count = JME_RX_DESC_CNT_DEF;
 237 static int      jme_tx_desc_count = JME_TX_DESC_CNT_DEF;
 238 static int      jme_rx_ring_count = 1;
 239 static int      jme_msi_enable = 1;
 240 static int      jme_msix_enable = 1;
 241
 242 TUNABLE_INT("hw.jme.rx_desc_count", &jme_rx_desc_count);
 243 TUNABLE_INT("hw.jme.tx_desc_count", &jme_tx_desc_count);
 244 TUNABLE_INT("hw.jme.rx_ring_count", &jme_rx_ring_count);
 245 TUNABLE_INT("hw.jme.msi.enable", &jme_msi_enable);
 246 TUNABLE_INT("hw.jme.msix.enable", &jme_msix_enable);
 247
 248 static __inline void
 249 jme_setup_rxdesc(struct jme_rxdesc *rxd)
 250 {
 251         struct jme_desc *desc;
 252
 253         desc = rxd->rx_desc;
 254         desc->buflen = htole32(MCLBYTES);
 255         desc->addr_lo = htole32(JME_ADDR_LO(rxd->rx_paddr));
 256         desc->addr_hi = htole32(JME_ADDR_HI(rxd->rx_paddr));
 257         desc->flags = htole32(JME_RD_OWN | JME_RD_INTR | JME_RD_64BIT);
 258 }
 259
 260 /*
 261  *      Read a PHY register on the MII of the JMC250.
 262  */
 263 static int
 264 jme_miibus_readreg(device_t dev, int phy, int reg)
 265 {
 266         struct jme_softc *sc = device_get_softc(dev);
 267         uint32_t val;
 268         int i;
 269
 270         /* For FPGA version, PHY address 0 should be ignored. */
 271         if (sc->jme_caps & JME_CAP_FPGA) {
 272                 if (phy == 0)
 273                         return (0);
 274         } else {
 275                 if (sc->jme_phyaddr != phy)
 276                         return (0);
 277         }
 278
 279         CSR_WRITE_4(sc, JME_SMI, SMI_OP_READ | SMI_OP_EXECUTE |
 280             SMI_PHY_ADDR(phy) | SMI_REG_ADDR(reg));
 281
 282         for (i = JME_PHY_TIMEOUT; i > 0; i--) {
 283                 DELAY(1);
 284                 if (((val = CSR_READ_4(sc, JME_SMI)) & SMI_OP_EXECUTE) == 0)
 285                         break;
 286         }
 287         if (i == 0) {
 288                 device_printf(sc->jme_dev, "phy read timeout: "
 289                               "phy %d, reg %d\n", phy, reg);
 290                 return (0);
 291         }
 292
 293         return ((val & SMI_DATA_MASK) >> SMI_DATA_SHIFT);
 294 }
 295
 296 /*
 297  *      Write a PHY register on the MII of the JMC250.
 298  */
 299 static int
 300 jme_miibus_writereg(device_t dev, int phy, int reg, int val)
 301 {
 302         struct jme_softc *sc = device_get_softc(dev);
 303         int i;
 304
 305         /* For FPGA version, PHY address 0 should be ignored. */
 306         if (sc->jme_caps & JME_CAP_FPGA) {
 307                 if (phy == 0)
 308                         return (0);
 309         } else {
 310                 if (sc->jme_phyaddr != phy)
 311                         return (0);
 312         }
 313
 314         CSR_WRITE_4(sc, JME_SMI, SMI_OP_WRITE | SMI_OP_EXECUTE |
 315             ((val << SMI_DATA_SHIFT) & SMI_DATA_MASK) |
 316             SMI_PHY_ADDR(phy) | SMI_REG_ADDR(reg));
 317
 318         for (i = JME_PHY_TIMEOUT; i > 0; i--) {
 319                 DELAY(1);
 320                 if (((val = CSR_READ_4(sc, JME_SMI)) & SMI_OP_EXECUTE) == 0)
 321                         break;
 322         }
 323         if (i == 0) {
 324                 device_printf(sc->jme_dev, "phy write timeout: "
 325                               "phy %d, reg %d\n", phy, reg);
 326         }
 327
 328         return (0);
 329 }
 330
 331 /*
 332  *      Callback from MII layer when media changes.
 333  */
 334 static void
 335 jme_miibus_statchg(device_t dev)
 336 {
 337         struct jme_softc *sc = device_get_softc(dev);
 338         struct ifnet *ifp = &sc->arpcom.ac_if;
 339         struct mii_data *mii;
 340         struct jme_txdesc *txd;
 341         bus_addr_t paddr;
 342         int i, r;
 343
 344         ASSERT_IFNET_SERIALIZED_ALL(ifp);
 345
 346         if ((ifp->if_flags & IFF_RUNNING) == 0)
 347                 return;
 348
 349         mii = device_get_softc(sc->jme_miibus);
 350
 351         sc->jme_flags &= ~JME_FLAG_LINK;
 352         if ((mii->mii_media_status & IFM_AVALID) != 0) {
 353                 switch (IFM_SUBTYPE(mii->mii_media_active)) {
 354                 case IFM_10_T:
 355                 case IFM_100_TX:
 356                         sc->jme_flags |= JME_FLAG_LINK;
 357                         break;
 358                 case IFM_1000_T:
 359                         if (sc->jme_caps & JME_CAP_FASTETH)
 360                                 break;
 361                         sc->jme_flags |= JME_FLAG_LINK;
 362                         break;
 363                 default:
 364                         break;
 365                 }
 366         }
 367
 368         /*
 369          * Disabling Rx/Tx MACs have a side-effect of resetting
 370          * JME_TXNDA/JME_RXNDA register to the first address of
 371          * Tx/Rx descriptor address. So driver should reset its
 372          * internal procucer/consumer pointer and reclaim any
 373          * allocated resources.  Note, just saving the value of
 374          * JME_TXNDA and JME_RXNDA registers before stopping MAC
 375          * and restoring JME_TXNDA/JME_RXNDA register is not
 376          * sufficient to make sure correct MAC state because
 377          * stopping MAC operation can take a while and hardware
 378          * might have updated JME_TXNDA/JME_RXNDA registers
 379          * during the stop operation.
 380          */
 381
 382         /* Disable interrupts */
 383         CSR_WRITE_4(sc, JME_INTR_MASK_CLR, JME_INTRS);
 384
 385         /* Stop driver */
 386         ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
 387         ifp->if_timer = 0;
 388         callout_stop(&sc->jme_tick_ch);
 389
 390         /* Stop receiver/transmitter. */
 391         jme_stop_rx(sc);
 392         jme_stop_tx(sc);
 393
 394         for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) {
 395                 struct jme_rxdata *rdata = &sc->jme_cdata.jme_rx_data[r];
 396
 397                 jme_rxeof(rdata, -1);
 398                 if (rdata->jme_rxhead != NULL)
 399                         m_freem(rdata->jme_rxhead);
 400                 JME_RXCHAIN_RESET(rdata);
 401
 402                 /*
 403                  * Reuse configured Rx descriptors and reset
 404                  * procuder/consumer index.
 405                  */
 406                 rdata->jme_rx_cons = 0;
 407         }
 408         if (sc->jme_cdata.jme_rx_ring_cnt > JME_NRXRING_MIN)
 409                 jme_enable_rss(sc);
 410         else
 411                 jme_disable_rss(sc);
 412
 413         jme_txeof(sc);
 414         if (sc->jme_cdata.jme_tx_cnt != 0) {
 415                 /* Remove queued packets for transmit. */
 416                 for (i = 0; i < sc->jme_cdata.jme_tx_desc_cnt; i++) {
 417                         txd = &sc->jme_cdata.jme_txdesc[i];
 418                         if (txd->tx_m != NULL) {
 419                                 bus_dmamap_unload(
 420                                     sc->jme_cdata.jme_tx_tag,
 421                                     txd->tx_dmamap);
 422                                 m_freem(txd->tx_m);
 423                                 txd->tx_m = NULL;
 424                                 txd->tx_ndesc = 0;
 425                                 ifp->if_oerrors++;
 426                         }
 427                 }
 428         }
 429         jme_init_tx_ring(sc);
 430
 431         /* Initialize shadow status block. */
 432         jme_init_ssb(sc);
 433
 434         /* Program MAC with resolved speed/duplex/flow-control. */
 435         if (sc->jme_flags & JME_FLAG_LINK) {
 436                 jme_mac_config(sc);
 437
 438                 CSR_WRITE_4(sc, JME_TXCSR, sc->jme_txcsr);
 439
 440                 /* Set Tx ring address to the hardware. */
 441                 paddr = sc->jme_cdata.jme_tx_ring_paddr;
 442                 CSR_WRITE_4(sc, JME_TXDBA_HI, JME_ADDR_HI(paddr));
 443                 CSR_WRITE_4(sc, JME_TXDBA_LO, JME_ADDR_LO(paddr));
 444
 445                 for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) {
 446                         CSR_WRITE_4(sc, JME_RXCSR,
 447                             sc->jme_rxcsr | RXCSR_RXQ_N_SEL(r));
 448
 449                         /* Set Rx ring address to the hardware. */
 450                         paddr = sc->jme_cdata.jme_rx_data[r].jme_rx_ring_paddr;
 451                         CSR_WRITE_4(sc, JME_RXDBA_HI, JME_ADDR_HI(paddr));
 452                         CSR_WRITE_4(sc, JME_RXDBA_LO, JME_ADDR_LO(paddr));
 453                 }
 454
 455                 /* Restart receiver/transmitter. */
 456                 CSR_WRITE_4(sc, JME_RXCSR, sc->jme_rxcsr | RXCSR_RX_ENB |
 457                     RXCSR_RXQ_START);
 458                 CSR_WRITE_4(sc, JME_TXCSR, sc->jme_txcsr | TXCSR_TX_ENB);
 459         }
 460
 461         ifp->if_flags |= IFF_RUNNING;
 462         ifp->if_flags &= ~IFF_OACTIVE;
 463         callout_reset(&sc->jme_tick_ch, hz, jme_tick, sc);
 464
 465 #ifdef DEVICE_POLLING
 466         if (!(ifp->if_flags & IFF_POLLING))
 467 #endif
 468         /* Reenable interrupts. */
 469         CSR_WRITE_4(sc, JME_INTR_MASK_SET, JME_INTRS);
 470 }
 471
 472 /*
 473  *      Get the current interface media status.
 474  */
 475 static void
 476 jme_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr)
 477 {
 478         struct jme_softc *sc = ifp->if_softc;
 479         struct mii_data *mii = device_get_softc(sc->jme_miibus);
 480
 481         ASSERT_IFNET_SERIALIZED_ALL(ifp);
 482
 483         mii_pollstat(mii);
 484         ifmr->ifm_status = mii->mii_media_status;
 485         ifmr->ifm_active = mii->mii_media_active;
 486 }
 487
 488 /*
 489  *      Set hardware to newly-selected media.
 490  */
 491 static int
 492 jme_mediachange(struct ifnet *ifp)
 493 {
 494         struct jme_softc *sc = ifp->if_softc;
 495         struct mii_data *mii = device_get_softc(sc->jme_miibus);
 496         int error;
 497
 498         ASSERT_IFNET_SERIALIZED_ALL(ifp);
 499
 500         if (mii->mii_instance != 0) {
 501                 struct mii_softc *miisc;
 502
 503                 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
 504                         mii_phy_reset(miisc);
 505         }
 506         error = mii_mediachg(mii);
 507
 508         return (error);
 509 }
 510
 511 static int
 512 jme_probe(device_t dev)
 513 {
 514         const struct jme_dev *sp;
 515         uint16_t vid, did;
 516
 517         vid = pci_get_vendor(dev);
 518         did = pci_get_device(dev);
 519         for (sp = jme_devs; sp->jme_name != NULL; ++sp) {
 520                 if (vid == sp->jme_vendorid && did == sp->jme_deviceid) {
 521                         struct jme_softc *sc = device_get_softc(dev);
 522
 523                         sc->jme_caps = sp->jme_caps;
 524                         device_set_desc(dev, sp->jme_name);
 525                         return (0);
 526                 }
 527         }
 528         return (ENXIO);
 529 }
 530
 531 static int
 532 jme_eeprom_read_byte(struct jme_softc *sc, uint8_t addr, uint8_t *val)
 533 {
 534         uint32_t reg;
 535         int i;
 536
 537         *val = 0;
 538         for (i = JME_TIMEOUT; i > 0; i--) {
 539                 reg = CSR_READ_4(sc, JME_SMBCSR);
 540                 if ((reg & SMBCSR_HW_BUSY_MASK) == SMBCSR_HW_IDLE)
 541                         break;
 542                 DELAY(1);
 543         }
 544
 545         if (i == 0) {
 546                 device_printf(sc->jme_dev, "EEPROM idle timeout!\n");
 547                 return (ETIMEDOUT);
 548         }
 549
 550         reg = ((uint32_t)addr << SMBINTF_ADDR_SHIFT) & SMBINTF_ADDR_MASK;
 551         CSR_WRITE_4(sc, JME_SMBINTF, reg | SMBINTF_RD | SMBINTF_CMD_TRIGGER);
 552         for (i = JME_TIMEOUT; i > 0; i--) {
 553                 DELAY(1);
 554                 reg = CSR_READ_4(sc, JME_SMBINTF);
 555                 if ((reg & SMBINTF_CMD_TRIGGER) == 0)
 556                         break;
 557         }
 558
 559         if (i == 0) {
 560                 device_printf(sc->jme_dev, "EEPROM read timeout!\n");
 561                 return (ETIMEDOUT);
 562         }
 563
 564         reg = CSR_READ_4(sc, JME_SMBINTF);
 565         *val = (reg & SMBINTF_RD_DATA_MASK) >> SMBINTF_RD_DATA_SHIFT;
 566
 567         return (0);
 568 }
 569
 570 static int
 571 jme_eeprom_macaddr(struct jme_softc *sc, uint8_t eaddr[])
 572 {
 573         uint8_t fup, reg, val;
 574         uint32_t offset;
 575         int match;
 576
 577         offset = 0;
 578         if (jme_eeprom_read_byte(sc, offset++, &fup) != 0 ||
 579             fup != JME_EEPROM_SIG0)
 580                 return (ENOENT);
 581         if (jme_eeprom_read_byte(sc, offset++, &fup) != 0 ||
 582             fup != JME_EEPROM_SIG1)
 583                 return (ENOENT);
 584         match = 0;
 585         do {
 586                 if (jme_eeprom_read_byte(sc, offset, &fup) != 0)
 587                         break;
 588                 if (JME_EEPROM_MKDESC(JME_EEPROM_FUNC0, JME_EEPROM_PAGE_BAR1) ==
 589                     (fup & (JME_EEPROM_FUNC_MASK | JME_EEPROM_PAGE_MASK))) {
 590                         if (jme_eeprom_read_byte(sc, offset + 1, &reg) != 0)
 591                                 break;
 592                         if (reg >= JME_PAR0 &&
 593                             reg < JME_PAR0 + ETHER_ADDR_LEN) {
 594                                 if (jme_eeprom_read_byte(sc, offset + 2,
 595                                     &val) != 0)
 596                                         break;
 597                                 eaddr[reg - JME_PAR0] = val;
 598                                 match++;
 599                         }
 600                 }
 601                 /* Check for the end of EEPROM descriptor. */
 602                 if ((fup & JME_EEPROM_DESC_END) == JME_EEPROM_DESC_END)
 603                         break;
 604                 /* Try next eeprom descriptor. */
 605                 offset += JME_EEPROM_DESC_BYTES;
 606         } while (match != ETHER_ADDR_LEN && offset < JME_EEPROM_END);
 607
 608         if (match == ETHER_ADDR_LEN)
 609                 return (0);
 610
 611         return (ENOENT);
 612 }
 613
 614 static void
 615 jme_reg_macaddr(struct jme_softc *sc, uint8_t eaddr[])
 616 {
 617         uint32_t par0, par1;
 618
 619         /* Read station address. */
 620         par0 = CSR_READ_4(sc, JME_PAR0);
 621         par1 = CSR_READ_4(sc, JME_PAR1);
 622         par1 &= 0xFFFF;
 623         if ((par0 == 0 && par1 == 0) || (par0 & 0x1)) {
 624                 device_printf(sc->jme_dev,
 625                     "generating fake ethernet address.\n");
 626                 par0 = karc4random();
 627                 /* Set OUI to JMicron. */
 628                 eaddr[0] = 0x00;
 629                 eaddr[1] = 0x1B;
 630                 eaddr[2] = 0x8C;
 631                 eaddr[3] = (par0 >> 16) & 0xff;
 632                 eaddr[4] = (par0 >> 8) & 0xff;
 633                 eaddr[5] = par0 & 0xff;
 634         } else {
 635                 eaddr[0] = (par0 >> 0) & 0xFF;
 636                 eaddr[1] = (par0 >> 8) & 0xFF;
 637                 eaddr[2] = (par0 >> 16) & 0xFF;
 638                 eaddr[3] = (par0 >> 24) & 0xFF;
 639                 eaddr[4] = (par1 >> 0) & 0xFF;
 640                 eaddr[5] = (par1 >> 8) & 0xFF;
 641         }
 642 }
 643
 644 static int
 645 jme_attach(device_t dev)
 646 {
 647         struct jme_softc *sc = device_get_softc(dev);
 648         struct ifnet *ifp = &sc->arpcom.ac_if;
 649         uint32_t reg;
 650         uint16_t did;
 651         uint8_t pcie_ptr, rev;
 652         int error = 0, i, j, rx_desc_cnt;
 653         uint8_t eaddr[ETHER_ADDR_LEN];
 654
 655         lwkt_serialize_init(&sc->jme_serialize);
 656         lwkt_serialize_init(&sc->jme_cdata.jme_tx_serialize);
 657         for (i = 0; i < JME_NRXRING_MAX; ++i) {
 658                 lwkt_serialize_init(
 659                     &sc->jme_cdata.jme_rx_data[i].jme_rx_serialize);
 660         }
 661
 662         rx_desc_cnt = device_getenv_int(dev, "rx_desc_count",
 663             jme_rx_desc_count);
 664         rx_desc_cnt = roundup(rx_desc_cnt, JME_NDESC_ALIGN);
 665         if (rx_desc_cnt > JME_NDESC_MAX)
 666                 rx_desc_cnt = JME_NDESC_MAX;
 667
 668         sc->jme_cdata.jme_tx_desc_cnt = device_getenv_int(dev, "tx_desc_count",
 669             jme_tx_desc_count);
 670         sc->jme_cdata.jme_tx_desc_cnt = roundup(sc->jme_cdata.jme_tx_desc_cnt,
 671             JME_NDESC_ALIGN);
 672         if (sc->jme_cdata.jme_tx_desc_cnt > JME_NDESC_MAX)
 673                 sc->jme_cdata.jme_tx_desc_cnt = JME_NDESC_MAX;
 674
 675         /*
 676          * Calculate rx rings
 677          */
 678         sc->jme_cdata.jme_rx_ring_cnt = device_getenv_int(dev, "rx_ring_count",
 679             jme_rx_ring_count);
 680         sc->jme_cdata.jme_rx_ring_cnt =
 681             if_ring_count2(sc->jme_cdata.jme_rx_ring_cnt, JME_NRXRING_MAX);
 682
 683         i = 0;
 684         sc->jme_serialize_arr[i++] = &sc->jme_serialize;
 685         sc->jme_serialize_arr[i++] = &sc->jme_cdata.jme_tx_serialize;
 686         for (j = 0; j < sc->jme_cdata.jme_rx_ring_cnt; ++j) {
 687                 sc->jme_serialize_arr[i++] =
 688                     &sc->jme_cdata.jme_rx_data[j].jme_rx_serialize;
 689         }
 690         KKASSERT(i <= JME_NSERIALIZE);
 691         sc->jme_serialize_cnt = i;
 692
 693         sc->jme_cdata.jme_sc = sc;
 694         for (i = 0; i < sc->jme_cdata.jme_rx_ring_cnt; ++i) {
 695                 struct jme_rxdata *rdata = &sc->jme_cdata.jme_rx_data[i];
 696
 697                 rdata->jme_sc = sc;
 698                 rdata->jme_rx_coal = jme_rx_status[i].jme_coal;
 699                 rdata->jme_rx_comp = jme_rx_status[i].jme_comp;
 700                 rdata->jme_rx_empty = jme_rx_status[i].jme_empty;
 701                 rdata->jme_rx_idx = i;
 702                 rdata->jme_rx_desc_cnt = rx_desc_cnt;
 703         }
 704
 705         sc->jme_dev = dev;
 706         sc->jme_lowaddr = BUS_SPACE_MAXADDR;
 707
 708         if_initname(ifp, device_get_name(dev), device_get_unit(dev));
 709
 710         callout_init(&sc->jme_tick_ch);
 711
 712 #ifndef BURN_BRIDGES
 713         if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
 714                 uint32_t irq, mem;
 715
 716                 irq = pci_read_config(dev, PCIR_INTLINE, 4);
 717                 mem = pci_read_config(dev, JME_PCIR_BAR, 4);
 718
 719                 device_printf(dev, "chip is in D%d power mode "
 720                     "-- setting to D0\n", pci_get_powerstate(dev));
 721
 722                 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
 723
 724                 pci_write_config(dev, PCIR_INTLINE, irq, 4);
 725                 pci_write_config(dev, JME_PCIR_BAR, mem, 4);
 726         }
 727 #endif  /* !BURN_BRIDGE */
 728
 729         /* Enable bus mastering */
 730         pci_enable_busmaster(dev);
 731
 732         /*
 733          * Allocate IO memory
 734          *
 735          * JMC250 supports both memory mapped and I/O register space
 736          * access.  Because I/O register access should use different
 737          * BARs to access registers it's waste of time to use I/O
 738          * register spce access.  JMC250 uses 16K to map entire memory
 739          * space.
 740          */
 741         sc->jme_mem_rid = JME_PCIR_BAR;
 742         sc->jme_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
 743                                                  &sc->jme_mem_rid, RF_ACTIVE);
 744         if (sc->jme_mem_res == NULL) {
 745                 device_printf(dev, "can't allocate IO memory\n");
 746                 return ENXIO;
 747         }
 748         sc->jme_mem_bt = rman_get_bustag(sc->jme_mem_res);
 749         sc->jme_mem_bh = rman_get_bushandle(sc->jme_mem_res);
 750
 751         /*
 752          * Allocate IRQ
 753          */
 754         error = jme_intr_alloc(dev);
 755         if (error)
 756                 goto fail;
 757
 758         /*
 759          * Extract revisions
 760          */
 761         reg = CSR_READ_4(sc, JME_CHIPMODE);
 762         if (((reg & CHIPMODE_FPGA_REV_MASK) >> CHIPMODE_FPGA_REV_SHIFT) !=
 763             CHIPMODE_NOT_FPGA) {
 764                 sc->jme_caps |= JME_CAP_FPGA;
 765                 if (bootverbose) {
 766                         device_printf(dev, "FPGA revision: 0x%04x\n",
 767                                       (reg & CHIPMODE_FPGA_REV_MASK) >>
 768                                       CHIPMODE_FPGA_REV_SHIFT);
 769                 }
 770         }
 771
 772         /* NOTE: FM revision is put in the upper 4 bits */
 773         rev = ((reg & CHIPMODE_REVFM_MASK) >> CHIPMODE_REVFM_SHIFT) << 4;
 774         rev |= (reg & CHIPMODE_REVECO_MASK) >> CHIPMODE_REVECO_SHIFT;
 775         if (bootverbose)
 776                 device_printf(dev, "Revision (FM/ECO): 0x%02x\n", rev);
 777
 778         did = pci_get_device(dev);
 779         switch (did) {
 780         case PCI_PRODUCT_JMICRON_JMC250:
 781                 if (rev == JME_REV1_A2)
 782                         sc->jme_workaround |= JME_WA_EXTFIFO | JME_WA_HDX;
 783                 break;
 784
 785         case PCI_PRODUCT_JMICRON_JMC260:
 786                 if (rev == JME_REV2)
 787                         sc->jme_lowaddr = BUS_SPACE_MAXADDR_32BIT;
 788                 break;
 789
 790         default:
 791                 panic("unknown device id 0x%04x", did);
 792         }
 793         if (rev >= JME_REV2) {
 794                 sc->jme_clksrc = GHC_TXOFL_CLKSRC | GHC_TXMAC_CLKSRC;
 795                 sc->jme_clksrc_1000 = GHC_TXOFL_CLKSRC_1000 |
 796                                       GHC_TXMAC_CLKSRC_1000;
 797         }
 798
 799         /* Reset the ethernet controller. */
 800         jme_reset(sc);
 801
 802         /* Map MSI/MSI-X vectors */
 803         jme_set_msinum(sc);
 804
 805         /* Get station address. */
 806         reg = CSR_READ_4(sc, JME_SMBCSR);
 807         if (reg & SMBCSR_EEPROM_PRESENT)
 808                 error = jme_eeprom_macaddr(sc, eaddr);
 809         if (error != 0 || (reg & SMBCSR_EEPROM_PRESENT) == 0) {
 810                 if (error != 0 && (bootverbose)) {
 811                         device_printf(dev, "ethernet hardware address "
 812                                       "not found in EEPROM.\n");
 813                 }
 814                 jme_reg_macaddr(sc, eaddr);
 815         }
 816
 817         /*
 818          * Save PHY address.
 819          * Integrated JR0211 has fixed PHY address whereas FPGA version
 820          * requires PHY probing to get correct PHY address.
 821          */
 822         if ((sc->jme_caps & JME_CAP_FPGA) == 0) {
 823                 sc->jme_phyaddr = CSR_READ_4(sc, JME_GPREG0) &
 824                     GPREG0_PHY_ADDR_MASK;
 825                 if (bootverbose) {
 826                         device_printf(dev, "PHY is at address %d.\n",
 827                             sc->jme_phyaddr);
 828                 }
 829         } else {
 830                 sc->jme_phyaddr = 0;
 831         }
 832
 833         /* Set max allowable DMA size. */
 834         pcie_ptr = pci_get_pciecap_ptr(dev);
 835         if (pcie_ptr != 0) {
 836                 uint16_t ctrl;
 837
 838                 sc->jme_caps |= JME_CAP_PCIE;
 839                 ctrl = pci_read_config(dev, pcie_ptr + PCIER_DEVCTRL, 2);
 840                 if (bootverbose) {
 841                         device_printf(dev, "Read request size : %d bytes.\n",
 842                             128 << ((ctrl >> 12) & 0x07));
 843                         device_printf(dev, "TLP payload size : %d bytes.\n",
 844                             128 << ((ctrl >> 5) & 0x07));
 845                 }
 846                 switch (ctrl & PCIEM_DEVCTL_MAX_READRQ_MASK) {
 847                 case PCIEM_DEVCTL_MAX_READRQ_128:
 848                         sc->jme_tx_dma_size = TXCSR_DMA_SIZE_128;
 849                         break;
 850                 case PCIEM_DEVCTL_MAX_READRQ_256:
 851                         sc->jme_tx_dma_size = TXCSR_DMA_SIZE_256;
 852                         break;
 853                 default:
 854                         sc->jme_tx_dma_size = TXCSR_DMA_SIZE_512;
 855                         break;
 856                 }
 857                 sc->jme_rx_dma_size = RXCSR_DMA_SIZE_128;
 858         } else {
 859                 sc->jme_tx_dma_size = TXCSR_DMA_SIZE_512;
 860                 sc->jme_rx_dma_size = RXCSR_DMA_SIZE_128;
 861         }
 862
 863 #ifdef notyet
 864         if (pci_find_extcap(dev, PCIY_PMG, &pmc) == 0)
 865                 sc->jme_caps |= JME_CAP_PMCAP;
 866 #endif
 867
 868         /*
 869          * Create sysctl tree
 870          */
 871         jme_sysctl_node(sc);
 872
 873         /* Allocate DMA stuffs */
 874         error = jme_dma_alloc(sc);
 875         if (error)
 876                 goto fail;
 877
 878         ifp->if_softc = sc;
 879         ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
 880         ifp->if_init = jme_init;
 881         ifp->if_ioctl = jme_ioctl;
 882         ifp->if_start = jme_start;
 883 #ifdef DEVICE_POLLING
 884         ifp->if_poll = jme_poll;
 885 #endif
 886         ifp->if_watchdog = jme_watchdog;
 887         ifp->if_serialize = jme_serialize;
 888         ifp->if_deserialize = jme_deserialize;
 889         ifp->if_tryserialize = jme_tryserialize;
 890 #ifdef INVARIANTS
 891         ifp->if_serialize_assert = jme_serialize_assert;
 892 #endif
 893         ifq_set_maxlen(&ifp->if_snd,
 894             sc->jme_cdata.jme_tx_desc_cnt - JME_TXD_RSVD);
 895         ifq_set_ready(&ifp->if_snd);
 896
 897         /* JMC250 supports Tx/Rx checksum offload and hardware vlan tagging. */
 898         ifp->if_capabilities = IFCAP_HWCSUM |
 899                                IFCAP_VLAN_MTU |
 900                                IFCAP_VLAN_HWTAGGING;
 901         if (sc->jme_cdata.jme_rx_ring_cnt > JME_NRXRING_MIN)
 902                 ifp->if_capabilities |= IFCAP_RSS;
 903         ifp->if_capenable = ifp->if_capabilities;
 904
 905         /*
 906          * Disable TXCSUM by default to improve bulk data
 907          * transmit performance (+20Mbps improvement).
 908          */
 909         ifp->if_capenable &= ~IFCAP_TXCSUM;
 910
 911         if (ifp->if_capenable & IFCAP_TXCSUM)
 912                 ifp->if_hwassist = JME_CSUM_FEATURES;
 913
 914         /* Set up MII bus. */
 915         error = mii_phy_probe(dev, &sc->jme_miibus,
 916                               jme_mediachange, jme_mediastatus);
 917         if (error) {
 918                 device_printf(dev, "no PHY found!\n");
 919                 goto fail;
 920         }
 921
 922         /*
 923          * Save PHYADDR for FPGA mode PHY.
 924          */
 925         if (sc->jme_caps & JME_CAP_FPGA) {
 926                 struct mii_data *mii = device_get_softc(sc->jme_miibus);
 927
 928                 if (mii->mii_instance != 0) {
 929                         struct mii_softc *miisc;
 930
 931                         LIST_FOREACH(miisc, &mii->mii_phys, mii_list) {
 932                                 if (miisc->mii_phy != 0) {
 933                                         sc->jme_phyaddr = miisc->mii_phy;
 934                                         break;
 935                                 }
 936                         }
 937                         if (sc->jme_phyaddr != 0) {
 938                                 device_printf(sc->jme_dev,
 939                                     "FPGA PHY is at %d\n", sc->jme_phyaddr);
 940                                 /* vendor magic. */
 941                                 jme_miibus_writereg(dev, sc->jme_phyaddr,
 942                                     JMPHY_CONF, JMPHY_CONF_DEFFIFO);
 943
 944                                 /* XXX should we clear JME_WA_EXTFIFO */
 945                         }
 946                 }
 947         }
 948
 949         ether_ifattach(ifp, eaddr, NULL);
 950
 951         /* Tell the upper layer(s) we support long frames. */
 952         ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
 953
 954         error = jme_intr_setup(dev);
 955         if (error) {
 956                 ether_ifdetach(ifp);
 957                 goto fail;
 958         }
 959
 960         return 0;
 961 fail:
 962         jme_detach(dev);
 963         return (error);
 964 }
 965
 966 static int
 967 jme_detach(device_t dev)
 968 {
 969         struct jme_softc *sc = device_get_softc(dev);
 970
 971         if (device_is_attached(dev)) {
 972                 struct ifnet *ifp = &sc->arpcom.ac_if;
 973
 974                 ifnet_serialize_all(ifp);
 975                 jme_stop(sc);
 976                 jme_intr_teardown(dev);
 977                 ifnet_deserialize_all(ifp);
 978
 979                 ether_ifdetach(ifp);
 980         }
 981
 982         if (sc->jme_sysctl_tree != NULL)
 983                 sysctl_ctx_free(&sc->jme_sysctl_ctx);
 984
 985         if (sc->jme_miibus != NULL)
 986                 device_delete_child(dev, sc->jme_miibus);
 987         bus_generic_detach(dev);
 988
 989         jme_intr_free(dev);
 990
 991         if (sc->jme_mem_res != NULL) {
 992                 bus_release_resource(dev, SYS_RES_MEMORY, sc->jme_mem_rid,
 993                                      sc->jme_mem_res);
 994         }
 995
 996         jme_dma_free(sc);
 997
 998         return (0);
 999 }
1000
1001 static void
1002 jme_sysctl_node(struct jme_softc *sc)
1003 {
1004         int coal_max;
1005 #ifdef JME_RSS_DEBUG
1006         int r;
1007 #endif
1008
1009         sysctl_ctx_init(&sc->jme_sysctl_ctx);
1010         sc->jme_sysctl_tree = SYSCTL_ADD_NODE(&sc->jme_sysctl_ctx,
1011                                 SYSCTL_STATIC_CHILDREN(_hw), OID_AUTO,
1012                                 device_get_nameunit(sc->jme_dev),
1013                                 CTLFLAG_RD, 0, "");
1014         if (sc->jme_sysctl_tree == NULL) {
1015                 device_printf(sc->jme_dev, "can't add sysctl node\n");
1016                 return;
1017         }
1018
1019         SYSCTL_ADD_PROC(&sc->jme_sysctl_ctx,
1020             SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO,
1021             "tx_coal_to", CTLTYPE_INT | CTLFLAG_RW,
1022             sc, 0, jme_sysctl_tx_coal_to, "I", "jme tx coalescing timeout");
1023
1024         SYSCTL_ADD_PROC(&sc->jme_sysctl_ctx,
1025             SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO,
1026             "tx_coal_pkt", CTLTYPE_INT | CTLFLAG_RW,
1027             sc, 0, jme_sysctl_tx_coal_pkt, "I", "jme tx coalescing packet");
1028
1029         SYSCTL_ADD_PROC(&sc->jme_sysctl_ctx,
1030             SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO,
1031             "rx_coal_to", CTLTYPE_INT | CTLFLAG_RW,
1032             sc, 0, jme_sysctl_rx_coal_to, "I", "jme rx coalescing timeout");
1033
1034         SYSCTL_ADD_PROC(&sc->jme_sysctl_ctx,
1035             SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO,
1036             "rx_coal_pkt", CTLTYPE_INT | CTLFLAG_RW,
1037             sc, 0, jme_sysctl_rx_coal_pkt, "I", "jme rx coalescing packet");
1038
1039         SYSCTL_ADD_INT(&sc->jme_sysctl_ctx,
1040                        SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO,
1041                        "rx_desc_count", CTLFLAG_RD,
1042                        &sc->jme_cdata.jme_rx_data[0].jme_rx_desc_cnt,
1043                        0, "RX desc count");
1044         SYSCTL_ADD_INT(&sc->jme_sysctl_ctx,
1045                        SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO,
1046                        "tx_desc_count", CTLFLAG_RD,
1047                        &sc->jme_cdata.jme_tx_desc_cnt,
1048                        0, "TX desc count");
1049         SYSCTL_ADD_INT(&sc->jme_sysctl_ctx,
1050                        SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO,
1051                        "rx_ring_count", CTLFLAG_RD,
1052                        &sc->jme_cdata.jme_rx_ring_cnt,
1053                        0, "RX ring count");
1054 #ifdef JME_RSS_DEBUG
1055         SYSCTL_ADD_INT(&sc->jme_sysctl_ctx,
1056                        SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO,
1057                        "rss_debug", CTLFLAG_RW, &sc->jme_rss_debug,
1058                        0, "RSS debug level");
1059         for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) {
1060                 char rx_ring_pkt[32];
1061
1062                 ksnprintf(rx_ring_pkt, sizeof(rx_ring_pkt), "rx_ring%d_pkt", r);
1063                 SYSCTL_ADD_ULONG(&sc->jme_sysctl_ctx,
1064                     SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO,
1065                     rx_ring_pkt, CTLFLAG_RW,
1066                     &sc->jme_cdata.jme_rx_data[r].jme_rx_pkt, "RXed packets");
1067         }
1068 #endif
1069
1070         /*
1071          * Set default coalesce valves
1072          */
1073         sc->jme_tx_coal_to = PCCTX_COAL_TO_DEFAULT;
1074         sc->jme_tx_coal_pkt = PCCTX_COAL_PKT_DEFAULT;
1075         sc->jme_rx_coal_to = PCCRX_COAL_TO_DEFAULT;
1076         sc->jme_rx_coal_pkt = PCCRX_COAL_PKT_DEFAULT;
1077
1078         /*
1079          * Adjust coalesce valves, in case that the number of TX/RX
1080          * descs are set to small values by users.
1081          *
1082          * NOTE: coal_max will not be zero, since number of descs
1083          * must aligned by JME_NDESC_ALIGN (16 currently)
1084          */
1085         coal_max = sc->jme_cdata.jme_tx_desc_cnt / 6;
1086         if (coal_max < sc->jme_tx_coal_pkt)
1087                 sc->jme_tx_coal_pkt = coal_max;
1088
1089         coal_max = sc->jme_cdata.jme_rx_data[0].jme_rx_desc_cnt / 4;
1090         if (coal_max < sc->jme_rx_coal_pkt)
1091                 sc->jme_rx_coal_pkt = coal_max;
1092 }
1093
1094 static int
1095 jme_dma_alloc(struct jme_softc *sc)
1096 {
1097         struct jme_txdesc *txd;
1098         bus_dmamem_t dmem;
1099         int error, i, asize;
1100
1101         sc->jme_cdata.jme_txdesc =
1102         kmalloc(sc->jme_cdata.jme_tx_desc_cnt * sizeof(struct jme_txdesc),
1103                 M_DEVBUF, M_WAITOK | M_ZERO);
1104         for (i = 0; i < sc->jme_cdata.jme_rx_ring_cnt; ++i) {
1105                 struct jme_rxdata *rdata = &sc->jme_cdata.jme_rx_data[i];
1106
1107                 rdata->jme_rxdesc =
1108                 kmalloc(rdata->jme_rx_desc_cnt * sizeof(struct jme_rxdesc),
1109                         M_DEVBUF, M_WAITOK | M_ZERO);
1110         }
1111
1112         /* Create parent ring tag. */
1113         error = bus_dma_tag_create(NULL,/* parent */
1114             1, JME_RING_BOUNDARY,       /* algnmnt, boundary */
1115             sc->jme_lowaddr,            /* lowaddr */
1116             BUS_SPACE_MAXADDR,          /* highaddr */
1117             NULL, NULL,                 /* filter, filterarg */
1118             BUS_SPACE_MAXSIZE_32BIT,    /* maxsize */
1119             0,                          /* nsegments */
1120             BUS_SPACE_MAXSIZE_32BIT,    /* maxsegsize */
1121             0,                          /* flags */
1122             &sc->jme_cdata.jme_ring_tag);
1123         if (error) {
1124                 device_printf(sc->jme_dev,
1125                     "could not create parent ring DMA tag.\n");
1126                 return error;
1127         }
1128
1129         /*
1130          * Create DMA stuffs for TX ring
1131          */
1132         asize = roundup2(JME_TX_RING_SIZE(sc), JME_TX_RING_ALIGN);
1133         error = bus_dmamem_coherent(sc->jme_cdata.jme_ring_tag,
1134                         JME_TX_RING_ALIGN, 0,
1135                         BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
1136                         asize, BUS_DMA_WAITOK | BUS_DMA_ZERO, &dmem);
1137         if (error) {
1138                 device_printf(sc->jme_dev, "could not allocate Tx ring.\n");
1139                 return error;
1140         }
1141         sc->jme_cdata.jme_tx_ring_tag = dmem.dmem_tag;
1142         sc->jme_cdata.jme_tx_ring_map = dmem.dmem_map;
1143         sc->jme_cdata.jme_tx_ring = dmem.dmem_addr;
1144         sc->jme_cdata.jme_tx_ring_paddr = dmem.dmem_busaddr;
1145
1146         /*
1147          * Create DMA stuffs for RX rings
1148          */
1149         for (i = 0; i < sc->jme_cdata.jme_rx_ring_cnt; ++i) {
1150                 error = jme_rxring_dma_alloc(&sc->jme_cdata.jme_rx_data[i]);
1151                 if (error)
1152                         return error;
1153         }
1154
1155         /* Create parent buffer tag. */
1156         error = bus_dma_tag_create(NULL,/* parent */
1157             1, 0,                       /* algnmnt, boundary */
1158             sc->jme_lowaddr,            /* lowaddr */
1159             BUS_SPACE_MAXADDR,          /* highaddr */
1160             NULL, NULL,                 /* filter, filterarg */
1161             BUS_SPACE_MAXSIZE_32BIT,    /* maxsize */
1162             0,                          /* nsegments */
1163             BUS_SPACE_MAXSIZE_32BIT,    /* maxsegsize */
1164             0,                          /* flags */
1165             &sc->jme_cdata.jme_buffer_tag);
1166         if (error) {
1167                 device_printf(sc->jme_dev,
1168                     "could not create parent buffer DMA tag.\n");
1169                 return error;
1170         }
1171
1172         /*
1173          * Create DMA stuffs for shadow status block
1174          */
1175         asize = roundup2(JME_SSB_SIZE, JME_SSB_ALIGN);
1176         error = bus_dmamem_coherent(sc->jme_cdata.jme_buffer_tag,
1177                         JME_SSB_ALIGN, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
1178                         asize, BUS_DMA_WAITOK | BUS_DMA_ZERO, &dmem);
1179         if (error) {
1180                 device_printf(sc->jme_dev,
1181                     "could not create shadow status block.\n");
1182                 return error;
1183         }
1184         sc->jme_cdata.jme_ssb_tag = dmem.dmem_tag;
1185         sc->jme_cdata.jme_ssb_map = dmem.dmem_map;
1186         sc->jme_cdata.jme_ssb_block = dmem.dmem_addr;
1187         sc->jme_cdata.jme_ssb_block_paddr = dmem.dmem_busaddr;
1188
1189         /*
1190          * Create DMA stuffs for TX buffers
1191          */
1192
1193         /* Create tag for Tx buffers. */
1194         error = bus_dma_tag_create(sc->jme_cdata.jme_buffer_tag,/* parent */
1195             1, 0,                       /* algnmnt, boundary */
1196             BUS_SPACE_MAXADDR,          /* lowaddr */
1197             BUS_SPACE_MAXADDR,          /* highaddr */
1198             NULL, NULL,                 /* filter, filterarg */
1199             JME_JUMBO_FRAMELEN,         /* maxsize */
1200             JME_MAXTXSEGS,              /* nsegments */
1201             JME_MAXSEGSIZE,             /* maxsegsize */
1202             BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE,/* flags */
1203             &sc->jme_cdata.jme_tx_tag);
1204         if (error != 0) {
1205                 device_printf(sc->jme_dev, "could not create Tx DMA tag.\n");
1206                 return error;
1207         }
1208
1209         /* Create DMA maps for Tx buffers. */
1210         for (i = 0; i < sc->jme_cdata.jme_tx_desc_cnt; i++) {
1211                 txd = &sc->jme_cdata.jme_txdesc[i];
1212                 error = bus_dmamap_create(sc->jme_cdata.jme_tx_tag,
1213                                 BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE,
1214                                 &txd->tx_dmamap);
1215                 if (error) {
1216                         int j;
1217
1218                         device_printf(sc->jme_dev,
1219                             "could not create %dth Tx dmamap.\n", i);
1220
1221                         for (j = 0; j < i; ++j) {
1222                                 txd = &sc->jme_cdata.jme_txdesc[j];
1223                                 bus_dmamap_destroy(sc->jme_cdata.jme_tx_tag,
1224                                                    txd->tx_dmamap);
1225                         }
1226                         bus_dma_tag_destroy(sc->jme_cdata.jme_tx_tag);
1227                         sc->jme_cdata.jme_tx_tag = NULL;
1228                         return error;
1229                 }
1230         }
1231
1232         /*
1233          * Create DMA stuffs for RX buffers
1234          */
1235         for (i = 0; i < sc->jme_cdata.jme_rx_ring_cnt; ++i) {
1236                 error = jme_rxbuf_dma_alloc(&sc->jme_cdata.jme_rx_data[i]);
1237                 if (error)
1238                         return error;
1239         }
1240         return 0;
1241 }
1242
1243 static void
1244 jme_dma_free(struct jme_softc *sc)
1245 {
1246         struct jme_txdesc *txd;
1247         struct jme_rxdesc *rxd;
1248         struct jme_rxdata *rdata;
1249         int i, r;
1250
1251         /* Tx ring */
1252         if (sc->jme_cdata.jme_tx_ring_tag != NULL) {
1253                 bus_dmamap_unload(sc->jme_cdata.jme_tx_ring_tag,
1254                     sc->jme_cdata.jme_tx_ring_map);
1255                 bus_dmamem_free(sc->jme_cdata.jme_tx_ring_tag,
1256                     sc->jme_cdata.jme_tx_ring,
1257                     sc->jme_cdata.jme_tx_ring_map);
1258                 bus_dma_tag_destroy(sc->jme_cdata.jme_tx_ring_tag);
1259                 sc->jme_cdata.jme_tx_ring_tag = NULL;
1260         }
1261
1262         /* Rx ring */
1263         for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) {
1264                 rdata = &sc->jme_cdata.jme_rx_data[r];
1265                 if (rdata->jme_rx_ring_tag != NULL) {
1266                         bus_dmamap_unload(rdata->jme_rx_ring_tag,
1267                                           rdata->jme_rx_ring_map);
1268                         bus_dmamem_free(rdata->jme_rx_ring_tag,
1269                                         rdata->jme_rx_ring,
1270                                         rdata->jme_rx_ring_map);
1271                         bus_dma_tag_destroy(rdata->jme_rx_ring_tag);
1272                         rdata->jme_rx_ring_tag = NULL;
1273                 }
1274         }
1275
1276         /* Tx buffers */
1277         if (sc->jme_cdata.jme_tx_tag != NULL) {
1278                 for (i = 0; i < sc->jme_cdata.jme_tx_desc_cnt; i++) {
1279                         txd = &sc->jme_cdata.jme_txdesc[i];
1280                         bus_dmamap_destroy(sc->jme_cdata.jme_tx_tag,
1281                             txd->tx_dmamap);
1282                 }
1283                 bus_dma_tag_destroy(sc->jme_cdata.jme_tx_tag);
1284                 sc->jme_cdata.jme_tx_tag = NULL;
1285         }
1286
1287         /* Rx buffers */
1288         for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) {
1289                 rdata = &sc->jme_cdata.jme_rx_data[r];
1290                 if (rdata->jme_rx_tag != NULL) {
1291                         for (i = 0; i < rdata->jme_rx_desc_cnt; i++) {
1292                                 rxd = &rdata->jme_rxdesc[i];
1293                                 bus_dmamap_destroy(rdata->jme_rx_tag,
1294                                                    rxd->rx_dmamap);
1295                         }
1296                         bus_dmamap_destroy(rdata->jme_rx_tag,
1297                                            rdata->jme_rx_sparemap);
1298                         bus_dma_tag_destroy(rdata->jme_rx_tag);
1299                         rdata->jme_rx_tag = NULL;
1300                 }
1301         }
1302
1303         /* Shadow status block. */
1304         if (sc->jme_cdata.jme_ssb_tag != NULL) {
1305                 bus_dmamap_unload(sc->jme_cdata.jme_ssb_tag,
1306                     sc->jme_cdata.jme_ssb_map);
1307                 bus_dmamem_free(sc->jme_cdata.jme_ssb_tag,
1308                     sc->jme_cdata.jme_ssb_block,
1309                     sc->jme_cdata.jme_ssb_map);
1310                 bus_dma_tag_destroy(sc->jme_cdata.jme_ssb_tag);
1311                 sc->jme_cdata.jme_ssb_tag = NULL;
1312         }
1313
1314         if (sc->jme_cdata.jme_buffer_tag != NULL) {
1315                 bus_dma_tag_destroy(sc->jme_cdata.jme_buffer_tag);
1316                 sc->jme_cdata.jme_buffer_tag = NULL;
1317         }
1318         if (sc->jme_cdata.jme_ring_tag != NULL) {
1319                 bus_dma_tag_destroy(sc->jme_cdata.jme_ring_tag);
1320                 sc->jme_cdata.jme_ring_tag = NULL;
1321         }
1322
1323         if (sc->jme_cdata.jme_txdesc != NULL) {
1324                 kfree(sc->jme_cdata.jme_txdesc, M_DEVBUF);
1325                 sc->jme_cdata.jme_txdesc = NULL;
1326         }
1327         for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) {
1328                 rdata = &sc->jme_cdata.jme_rx_data[r];
1329                 if (rdata->jme_rxdesc != NULL) {
1330                         kfree(rdata->jme_rxdesc, M_DEVBUF);
1331                         rdata->jme_rxdesc = NULL;
1332                 }
1333         }
1334 }
1335
1336 /*
1337  *      Make sure the interface is stopped at reboot time.
1338  */
1339 static int
1340 jme_shutdown(device_t dev)
1341 {
1342         return jme_suspend(dev);
1343 }
1344
1345 #ifdef notyet
1346 /*
1347  * Unlike other ethernet controllers, JMC250 requires
1348  * explicit resetting link speed to 10/100Mbps as gigabit
1349  * link will cunsume more power than 375mA.
1350  * Note, we reset the link speed to 10/100Mbps with
1351  * auto-negotiation but we don't know whether that operation
1352  * would succeed or not as we have no control after powering
1353  * off. If the renegotiation fail WOL may not work. Running
1354  * at 1Gbps draws more power than 375mA at 3.3V which is
1355  * specified in PCI specification and that would result in
1356  * complete shutdowning power to ethernet controller.
1357  *
1358  * TODO
1359  *  Save current negotiated media speed/duplex/flow-control
1360  *  to softc and restore the same link again after resuming.
1361  *  PHY handling such as power down/resetting to 100Mbps
1362  *  may be better handled in suspend method in phy driver.
1363  */
1364 static void
1365 jme_setlinkspeed(struct jme_softc *sc)
1366 {
1367         struct mii_data *mii;
1368         int aneg, i;
1369
1370         JME_LOCK_ASSERT(sc);
1371
1372         mii = device_get_softc(sc->jme_miibus);
1373         mii_pollstat(mii);
1374         aneg = 0;
1375         if ((mii->mii_media_status & IFM_AVALID) != 0) {
1376                 switch IFM_SUBTYPE(mii->mii_media_active) {
1377                 case IFM_10_T:
1378                 case IFM_100_TX:
1379                         return;
1380                 case IFM_1000_T:
1381                         aneg++;
1382                 default:
1383                         break;
1384                 }
1385         }
1386         jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr, MII_100T2CR, 0);
1387         jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr, MII_ANAR,
1388             ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10 | ANAR_CSMA);
1389         jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr, MII_BMCR,
1390             BMCR_AUTOEN | BMCR_STARTNEG);
1391         DELAY(1000);
1392         if (aneg != 0) {
1393                 /* Poll link state until jme(4) get a 10/100 link. */
1394                 for (i = 0; i < MII_ANEGTICKS_GIGE; i++) {
1395                         mii_pollstat(mii);
1396                         if ((mii->mii_media_status & IFM_AVALID) != 0) {
1397                                 switch (IFM_SUBTYPE(mii->mii_media_active)) {
1398                                 case IFM_10_T:
1399                                 case IFM_100_TX:
1400                                         jme_mac_config(sc);
1401                                         return;
1402                                 default:
1403                                         break;
1404                                 }
1405                         }
1406                         JME_UNLOCK(sc);
1407                         pause("jmelnk", hz);
1408                         JME_LOCK(sc);
1409                 }
1410                 if (i == MII_ANEGTICKS_GIGE)
1411                         device_printf(sc->jme_dev, "establishing link failed, "
1412                             "WOL may not work!");
1413         }
1414         /*
1415          * No link, force MAC to have 100Mbps, full-duplex link.
1416          * This is the last resort and may/may not work.
1417          */
1418         mii->mii_media_status = IFM_AVALID | IFM_ACTIVE;
1419         mii->mii_media_active = IFM_ETHER | IFM_100_TX | IFM_FDX;
1420         jme_mac_config(sc);
1421 }
1422
1423 static void
1424 jme_setwol(struct jme_softc *sc)
1425 {
1426         struct ifnet *ifp = &sc->arpcom.ac_if;
1427         uint32_t gpr, pmcs;
1428         uint16_t pmstat;
1429         int pmc;
1430
1431         if (pci_find_extcap(sc->jme_dev, PCIY_PMG, &pmc) != 0) {
1432                 /* No PME capability, PHY power down. */
1433                 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr,
1434                     MII_BMCR, BMCR_PDOWN);
1435                 return;
1436         }
1437
1438         gpr = CSR_READ_4(sc, JME_GPREG0) & ~GPREG0_PME_ENB;
1439         pmcs = CSR_READ_4(sc, JME_PMCS);
1440         pmcs &= ~PMCS_WOL_ENB_MASK;
1441         if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) {
1442                 pmcs |= PMCS_MAGIC_FRAME | PMCS_MAGIC_FRAME_ENB;
1443                 /* Enable PME message. */
1444                 gpr |= GPREG0_PME_ENB;
1445                 /* For gigabit controllers, reset link speed to 10/100. */
1446                 if ((sc->jme_caps & JME_CAP_FASTETH) == 0)
1447                         jme_setlinkspeed(sc);
1448         }
1449
1450         CSR_WRITE_4(sc, JME_PMCS, pmcs);
1451         CSR_WRITE_4(sc, JME_GPREG0, gpr);
1452
1453         /* Request PME. */
1454         pmstat = pci_read_config(sc->jme_dev, pmc + PCIR_POWER_STATUS, 2);
1455         pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE);
1456         if ((ifp->if_capenable & IFCAP_WOL) != 0)
1457                 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
1458         pci_write_config(sc->jme_dev, pmc + PCIR_POWER_STATUS, pmstat, 2);
1459         if ((ifp->if_capenable & IFCAP_WOL) == 0) {
1460                 /* No WOL, PHY power down. */
1461                 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr,
1462                     MII_BMCR, BMCR_PDOWN);
1463         }
1464 }
1465 #endif
1466
1467 static int
1468 jme_suspend(device_t dev)
1469 {
1470         struct jme_softc *sc = device_get_softc(dev);
1471         struct ifnet *ifp = &sc->arpcom.ac_if;
1472
1473         ifnet_serialize_all(ifp);
1474         jme_stop(sc);
1475 #ifdef notyet
1476         jme_setwol(sc);
1477 #endif
1478         ifnet_deserialize_all(ifp);
1479
1480         return (0);
1481 }
1482
1483 static int
1484 jme_resume(device_t dev)
1485 {
1486         struct jme_softc *sc = device_get_softc(dev);
1487         struct ifnet *ifp = &sc->arpcom.ac_if;
1488 #ifdef notyet
1489         int pmc;
1490 #endif
1491
1492         ifnet_serialize_all(ifp);
1493
1494 #ifdef notyet
1495         if (pci_find_extcap(sc->jme_dev, PCIY_PMG, &pmc) != 0) {
1496                 uint16_t pmstat;
1497
1498                 pmstat = pci_read_config(sc->jme_dev,
1499                     pmc + PCIR_POWER_STATUS, 2);
1500                 /* Disable PME clear PME status. */
1501                 pmstat &= ~PCIM_PSTAT_PMEENABLE;
1502                 pci_write_config(sc->jme_dev,
1503                     pmc + PCIR_POWER_STATUS, pmstat, 2);
1504         }
1505 #endif
1506
1507         if (ifp->if_flags & IFF_UP)
1508                 jme_init(sc);
1509
1510         ifnet_deserialize_all(ifp);
1511
1512         return (0);
1513 }
1514
1515 static int
1516 jme_encap(struct jme_softc *sc, struct mbuf **m_head)
1517 {
1518         struct jme_txdesc *txd;
1519         struct jme_desc *desc;
1520         struct mbuf *m;
1521         bus_dma_segment_t txsegs[JME_MAXTXSEGS];
1522         int maxsegs, nsegs;
1523         int error, i, prod, symbol_desc;
1524         uint32_t cflags, flag64;
1525
1526         M_ASSERTPKTHDR((*m_head));
1527
1528         prod = sc->jme_cdata.jme_tx_prod;
1529         txd = &sc->jme_cdata.jme_txdesc[prod];
1530
1531         if (sc->jme_lowaddr != BUS_SPACE_MAXADDR_32BIT)
1532                 symbol_desc = 1;
1533         else
1534                 symbol_desc = 0;
1535
1536         maxsegs = (sc->jme_cdata.jme_tx_desc_cnt - sc->jme_cdata.jme_tx_cnt) -
1537                   (JME_TXD_RSVD + symbol_desc);
1538         if (maxsegs > JME_MAXTXSEGS)
1539                 maxsegs = JME_MAXTXSEGS;
1540         KASSERT(maxsegs >= (sc->jme_txd_spare - symbol_desc),
1541                 ("not enough segments %d", maxsegs));
1542
1543         error = bus_dmamap_load_mbuf_defrag(sc->jme_cdata.jme_tx_tag,
1544                         txd->tx_dmamap, m_head,
1545                         txsegs, maxsegs, &nsegs, BUS_DMA_NOWAIT);
1546         if (error)
1547                 goto fail;
1548
1549         bus_dmamap_sync(sc->jme_cdata.jme_tx_tag, txd->tx_dmamap,
1550                         BUS_DMASYNC_PREWRITE);
1551
1552         m = *m_head;
1553         cflags = 0;
1554
1555         /* Configure checksum offload. */
1556         if (m->m_pkthdr.csum_flags & CSUM_IP)
1557                 cflags |= JME_TD_IPCSUM;
1558         if (m->m_pkthdr.csum_flags & CSUM_TCP)
1559                 cflags |= JME_TD_TCPCSUM;
1560         if (m->m_pkthdr.csum_flags & CSUM_UDP)
1561                 cflags |= JME_TD_UDPCSUM;
1562
1563         /* Configure VLAN. */
1564         if (m->m_flags & M_VLANTAG) {
1565                 cflags |= (m->m_pkthdr.ether_vlantag & JME_TD_VLAN_MASK);
1566                 cflags |= JME_TD_VLAN_TAG;
1567         }
1568
1569         desc = &sc->jme_cdata.jme_tx_ring[prod];
1570         desc->flags = htole32(cflags);
1571         desc->addr_hi = htole32(m->m_pkthdr.len);
1572         if (sc->jme_lowaddr != BUS_SPACE_MAXADDR_32BIT) {
1573                 /*
1574                  * Use 64bits TX desc chain format.
1575                  *
1576                  * The first TX desc of the chain, which is setup here,
1577                  * is just a symbol TX desc carrying no payload.
1578                  */
1579                 flag64 = JME_TD_64BIT;
1580                 desc->buflen = 0;
1581                 desc->addr_lo = 0;
1582
1583                 /* No effective TX desc is consumed */
1584                 i = 0;
1585         } else {
1586                 /*
1587                  * Use 32bits TX desc chain format.
1588                  *
1589                  * The first TX desc of the chain, which is setup here,
1590                  * is an effective TX desc carrying the first segment of
1591                  * the mbuf chain.
1592                  */
1593                 flag64 = 0;
1594                 desc->buflen = htole32(txsegs[0].ds_len);
1595                 desc->addr_lo = htole32(JME_ADDR_LO(txsegs[0].ds_addr));
1596
1597                 /* One effective TX desc is consumed */
1598                 i = 1;
1599         }
1600         sc->jme_cdata.jme_tx_cnt++;
1601         KKASSERT(sc->jme_cdata.jme_tx_cnt - i <
1602                  sc->jme_cdata.jme_tx_desc_cnt - JME_TXD_RSVD);
1603         JME_DESC_INC(prod, sc->jme_cdata.jme_tx_desc_cnt);
1604
1605         txd->tx_ndesc = 1 - i;
1606         for (; i < nsegs; i++) {
1607                 desc = &sc->jme_cdata.jme_tx_ring[prod];
1608                 desc->buflen = htole32(txsegs[i].ds_len);
1609                 desc->addr_hi = htole32(JME_ADDR_HI(txsegs[i].ds_addr));
1610                 desc->addr_lo = htole32(JME_ADDR_LO(txsegs[i].ds_addr));
1611                 desc->flags = htole32(JME_TD_OWN | flag64);
1612
1613                 sc->jme_cdata.jme_tx_cnt++;
1614                 KKASSERT(sc->jme_cdata.jme_tx_cnt <=
1615                          sc->jme_cdata.jme_tx_desc_cnt - JME_TXD_RSVD);
1616                 JME_DESC_INC(prod, sc->jme_cdata.jme_tx_desc_cnt);
1617         }
1618
1619         /* Update producer index. */
1620         sc->jme_cdata.jme_tx_prod = prod;
1621         /*
1622          * Finally request interrupt and give the first descriptor
1623          * owenership to hardware.
1624          */
1625         desc = txd->tx_desc;
1626         desc->flags |= htole32(JME_TD_OWN | JME_TD_INTR);
1627
1628         txd->tx_m = m;
1629         txd->tx_ndesc += nsegs;
1630
1631         return 0;
1632 fail:
1633         m_freem(*m_head);
1634         *m_head = NULL;
1635         return error;
1636 }
1637
1638 static void
1639 jme_start(struct ifnet *ifp)
1640 {
1641         struct jme_softc *sc = ifp->if_softc;
1642         struct mbuf *m_head;
1643         int enq = 0;
1644
1645         ASSERT_SERIALIZED(&sc->jme_cdata.jme_tx_serialize);
1646
1647         if ((sc->jme_flags & JME_FLAG_LINK) == 0) {
1648                 ifq_purge(&ifp->if_snd);
1649                 return;
1650         }
1651
1652         if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING)
1653                 return;
1654
1655         if (sc->jme_cdata.jme_tx_cnt >= JME_TX_DESC_HIWAT(sc))
1656                 jme_txeof(sc);
1657
1658         while (!ifq_is_empty(&ifp->if_snd)) {
1659                 /*
1660                  * Check number of available TX descs, always
1661                  * leave JME_TXD_RSVD free TX descs.
1662                  */
1663                 if (sc->jme_cdata.jme_tx_cnt + sc->jme_txd_spare >
1664                     sc->jme_cdata.jme_tx_desc_cnt - JME_TXD_RSVD) {
1665                         ifp->if_flags |= IFF_OACTIVE;
1666                         break;
1667                 }
1668
1669                 m_head = ifq_dequeue(&ifp->if_snd, NULL);
1670                 if (m_head == NULL)
1671                         break;
1672
1673                 /*
1674                  * Pack the data into the transmit ring. If we
1675                  * don't have room, set the OACTIVE flag and wait
1676                  * for the NIC to drain the ring.
1677                  */
1678                 if (jme_encap(sc, &m_head)) {
1679                         KKASSERT(m_head == NULL);
1680                         ifp->if_oerrors++;
1681                         ifp->if_flags |= IFF_OACTIVE;
1682                         break;
1683                 }
1684                 enq++;
1685
1686                 /*
1687                  * If there's a BPF listener, bounce a copy of this frame
1688                  * to him.
1689                  */
1690                 ETHER_BPF_MTAP(ifp, m_head);
1691         }
1692
1693         if (enq > 0) {
1694                 /*
1695                  * Reading TXCSR takes very long time under heavy load
1696                  * so cache TXCSR value and writes the ORed value with
1697                  * the kick command to the TXCSR. This saves one register
1698                  * access cycle.
1699                  */
1700                 CSR_WRITE_4(sc, JME_TXCSR, sc->jme_txcsr | TXCSR_TX_ENB |
1701                     TXCSR_TXQ_N_START(TXCSR_TXQ0));
1702                 /* Set a timeout in case the chip goes out to lunch. */
1703                 ifp->if_timer = JME_TX_TIMEOUT;
1704         }
1705 }
1706
1707 static void
1708 jme_watchdog(struct ifnet *ifp)
1709 {
1710         struct jme_softc *sc = ifp->if_softc;
1711
1712         ASSERT_IFNET_SERIALIZED_ALL(ifp);
1713
1714         if ((sc->jme_flags & JME_FLAG_LINK) == 0) {
1715                 if_printf(ifp, "watchdog timeout (missed link)\n");
1716                 ifp->if_oerrors++;
1717                 jme_init(sc);
1718                 return;
1719         }
1720
1721         jme_txeof(sc);
1722         if (sc->jme_cdata.jme_tx_cnt == 0) {
1723                 if_printf(ifp, "watchdog timeout (missed Tx interrupts) "
1724                           "-- recovering\n");
1725                 if (!ifq_is_empty(&ifp->if_snd))
1726                         if_devstart(ifp);
1727                 return;
1728         }
1729
1730         if_printf(ifp, "watchdog timeout\n");
1731         ifp->if_oerrors++;
1732         jme_init(sc);
1733         if (!ifq_is_empty(&ifp->if_snd))
1734                 if_devstart(ifp);
1735 }
1736
1737 static int
1738 jme_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data, struct ucred *cr)
1739 {
1740         struct jme_softc *sc = ifp->if_softc;
1741         struct mii_data *mii = device_get_softc(sc->jme_miibus);
1742         struct ifreq *ifr = (struct ifreq *)data;
1743         int error = 0, mask;
1744
1745         ASSERT_IFNET_SERIALIZED_ALL(ifp);
1746
1747         switch (cmd) {
1748         case SIOCSIFMTU:
1749                 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > JME_JUMBO_MTU ||
1750                     (!(sc->jme_caps & JME_CAP_JUMBO) &&
1751                      ifr->ifr_mtu > JME_MAX_MTU)) {
1752                         error = EINVAL;
1753                         break;
1754                 }
1755
1756                 if (ifp->if_mtu != ifr->ifr_mtu) {
1757                         /*
1758                          * No special configuration is required when interface
1759                          * MTU is changed but availability of Tx checksum
1760                          * offload should be chcked against new MTU size as
1761                          * FIFO size is just 2K.
1762                          */
1763                         if (ifr->ifr_mtu >= JME_TX_FIFO_SIZE) {
1764                                 ifp->if_capenable &= ~IFCAP_TXCSUM;
1765                                 ifp->if_hwassist &= ~JME_CSUM_FEATURES;
1766                         }
1767                         ifp->if_mtu = ifr->ifr_mtu;
1768                         if (ifp->if_flags & IFF_RUNNING)
1769                                 jme_init(sc);
1770                 }
1771                 break;
1772
1773         case SIOCSIFFLAGS:
1774                 if (ifp->if_flags & IFF_UP) {
1775                         if (ifp->if_flags & IFF_RUNNING) {
1776                                 if ((ifp->if_flags ^ sc->jme_if_flags) &
1777                                     (IFF_PROMISC | IFF_ALLMULTI))
1778                                         jme_set_filter(sc);
1779                         } else {
1780                                 jme_init(sc);
1781                         }
1782                 } else {
1783                         if (ifp->if_flags & IFF_RUNNING)
1784                                 jme_stop(sc);
1785                 }
1786                 sc->jme_if_flags = ifp->if_flags;
1787                 break;
1788
1789         case SIOCADDMULTI:
1790         case SIOCDELMULTI:
1791                 if (ifp->if_flags & IFF_RUNNING)
1792                         jme_set_filter(sc);
1793                 break;
1794
1795         case SIOCSIFMEDIA:
1796         case SIOCGIFMEDIA:
1797                 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd);
1798                 break;
1799
1800         case SIOCSIFCAP:
1801                 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
1802
1803                 if ((mask & IFCAP_TXCSUM) && ifp->if_mtu < JME_TX_FIFO_SIZE) {
1804                         ifp->if_capenable ^= IFCAP_TXCSUM;
1805                         if (IFCAP_TXCSUM & ifp->if_capenable)
1806                                 ifp->if_hwassist |= JME_CSUM_FEATURES;
1807                         else
1808                                 ifp->if_hwassist &= ~JME_CSUM_FEATURES;
1809                 }
1810                 if (mask & IFCAP_RXCSUM) {
1811                         uint32_t reg;
1812
1813                         ifp->if_capenable ^= IFCAP_RXCSUM;
1814                         reg = CSR_READ_4(sc, JME_RXMAC);
1815                         reg &= ~RXMAC_CSUM_ENB;
1816                         if (ifp->if_capenable & IFCAP_RXCSUM)
1817                                 reg |= RXMAC_CSUM_ENB;
1818                         CSR_WRITE_4(sc, JME_RXMAC, reg);
1819                 }
1820
1821                 if (mask & IFCAP_VLAN_HWTAGGING) {
1822                         ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
1823                         jme_set_vlan(sc);
1824                 }
1825
1826                 if (mask & IFCAP_RSS)
1827                         ifp->if_capenable ^= IFCAP_RSS;
1828                 break;
1829
1830         default:
1831                 error = ether_ioctl(ifp, cmd, data);
1832                 break;
1833         }
1834         return (error);
1835 }
1836
1837 static void
1838 jme_mac_config(struct jme_softc *sc)
1839 {
1840         struct mii_data *mii;
1841         uint32_t ghc, rxmac, txmac, txpause, gp1;
1842         int phyconf = JMPHY_CONF_DEFFIFO, hdx = 0;
1843
1844         mii = device_get_softc(sc->jme_miibus);
1845
1846         CSR_WRITE_4(sc, JME_GHC, GHC_RESET);
1847         DELAY(10);
1848         CSR_WRITE_4(sc, JME_GHC, 0);
1849         ghc = 0;
1850         rxmac = CSR_READ_4(sc, JME_RXMAC);
1851         rxmac &= ~RXMAC_FC_ENB;
1852         txmac = CSR_READ_4(sc, JME_TXMAC);
1853         txmac &= ~(TXMAC_CARRIER_EXT | TXMAC_FRAME_BURST);
1854         txpause = CSR_READ_4(sc, JME_TXPFC);
1855         txpause &= ~TXPFC_PAUSE_ENB;
1856         if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) {
1857                 ghc |= GHC_FULL_DUPLEX;
1858                 rxmac &= ~RXMAC_COLL_DET_ENB;
1859                 txmac &= ~(TXMAC_COLL_ENB | TXMAC_CARRIER_SENSE |
1860                     TXMAC_BACKOFF | TXMAC_CARRIER_EXT |
1861                     TXMAC_FRAME_BURST);
1862 #ifdef notyet
1863                 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0)
1864                         txpause |= TXPFC_PAUSE_ENB;
1865                 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0)
1866                         rxmac |= RXMAC_FC_ENB;
1867 #endif
1868                 /* Disable retry transmit timer/retry limit. */
1869                 CSR_WRITE_4(sc, JME_TXTRHD, CSR_READ_4(sc, JME_TXTRHD) &
1870                     ~(TXTRHD_RT_PERIOD_ENB | TXTRHD_RT_LIMIT_ENB));
1871         } else {
1872                 rxmac |= RXMAC_COLL_DET_ENB;
1873                 txmac |= TXMAC_COLL_ENB | TXMAC_CARRIER_SENSE | TXMAC_BACKOFF;
1874                 /* Enable retry transmit timer/retry limit. */
1875                 CSR_WRITE_4(sc, JME_TXTRHD, CSR_READ_4(sc, JME_TXTRHD) |
1876                     TXTRHD_RT_PERIOD_ENB | TXTRHD_RT_LIMIT_ENB);
1877         }
1878
1879         /*
1880          * Reprogram Tx/Rx MACs with resolved speed/duplex.
1881          */
1882         gp1 = CSR_READ_4(sc, JME_GPREG1);
1883         gp1 &= ~GPREG1_WA_HDX;
1884
1885         if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) == 0)
1886                 hdx = 1;
1887
1888         switch (IFM_SUBTYPE(mii->mii_media_active)) {
1889         case IFM_10_T:
1890                 ghc |= GHC_SPEED_10 | sc->jme_clksrc;
1891                 if (hdx)
1892                         gp1 |= GPREG1_WA_HDX;
1893                 break;
1894
1895         case IFM_100_TX:
1896                 ghc |= GHC_SPEED_100 | sc->jme_clksrc;
1897                 if (hdx)
1898                         gp1 |= GPREG1_WA_HDX;
1899
1900                 /*
1901                  * Use extended FIFO depth to workaround CRC errors
1902                  * emitted by chips before JMC250B
1903                  */
1904                 phyconf = JMPHY_CONF_EXTFIFO;
1905                 break;
1906
1907         case IFM_1000_T:
1908                 if (sc->jme_caps & JME_CAP_FASTETH)
1909                         break;
1910
1911                 ghc |= GHC_SPEED_1000 | sc->jme_clksrc_1000;
1912                 if (hdx)
1913                         txmac |= TXMAC_CARRIER_EXT | TXMAC_FRAME_BURST;
1914                 break;
1915
1916         default:
1917                 break;
1918         }
1919         CSR_WRITE_4(sc, JME_GHC, ghc);
1920         CSR_WRITE_4(sc, JME_RXMAC, rxmac);
1921         CSR_WRITE_4(sc, JME_TXMAC, txmac);
1922         CSR_WRITE_4(sc, JME_TXPFC, txpause);
1923
1924         if (sc->jme_workaround & JME_WA_EXTFIFO) {
1925                 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr,
1926                                     JMPHY_CONF, phyconf);
1927         }
1928         if (sc->jme_workaround & JME_WA_HDX)
1929                 CSR_WRITE_4(sc, JME_GPREG1, gp1);
1930 }
1931
1932 static void
1933 jme_intr(void *xsc)
1934 {
1935         struct jme_softc *sc = xsc;
1936         struct ifnet *ifp = &sc->arpcom.ac_if;
1937         uint32_t status;
1938         int r;
1939
1940         ASSERT_SERIALIZED(&sc->jme_serialize);
1941
1942         status = CSR_READ_4(sc, JME_INTR_REQ_STATUS);
1943         if (status == 0 || status == 0xFFFFFFFF)
1944                 return;
1945
1946         /* Disable interrupts. */
1947         CSR_WRITE_4(sc, JME_INTR_MASK_CLR, JME_INTRS);
1948
1949         status = CSR_READ_4(sc, JME_INTR_STATUS);
1950         if ((status & JME_INTRS) == 0 || status == 0xFFFFFFFF)
1951                 goto back;
1952
1953         /* Reset PCC counter/timer and Ack interrupts. */
1954         status &= ~(INTR_TXQ_COMP | INTR_RXQ_COMP);
1955
1956         if (status & (INTR_TXQ_COAL | INTR_TXQ_COAL_TO))
1957                 status |= INTR_TXQ_COAL | INTR_TXQ_COAL_TO | INTR_TXQ_COMP;
1958
1959         for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) {
1960                 if (status & jme_rx_status[r].jme_coal) {
1961                         status |= jme_rx_status[r].jme_coal |
1962                                   jme_rx_status[r].jme_comp;
1963                 }
1964         }
1965
1966         CSR_WRITE_4(sc, JME_INTR_STATUS, status);
1967
1968         if (ifp->if_flags & IFF_RUNNING) {
1969                 if (status & (INTR_RXQ_COAL | INTR_RXQ_COAL_TO))
1970                         jme_rx_intr(sc, status);
1971
1972                 if (status & INTR_RXQ_DESC_EMPTY) {
1973                         /*
1974                          * Notify hardware availability of new Rx buffers.
1975                          * Reading RXCSR takes very long time under heavy
1976                          * load so cache RXCSR value and writes the ORed
1977                          * value with the kick command to the RXCSR. This
1978                          * saves one register access cycle.
1979                          */
1980                         CSR_WRITE_4(sc, JME_RXCSR, sc->jme_rxcsr |
1981                             RXCSR_RX_ENB | RXCSR_RXQ_START);
1982                 }
1983
1984                 if (status & (INTR_TXQ_COAL | INTR_TXQ_COAL_TO)) {
1985                         lwkt_serialize_enter(&sc->jme_cdata.jme_tx_serialize);
1986                         jme_txeof(sc);
1987                         if (!ifq_is_empty(&ifp->if_snd))
1988                                 if_devstart(ifp);
1989                         lwkt_serialize_exit(&sc->jme_cdata.jme_tx_serialize);
1990                 }
1991         }
1992 back:
1993         /* Reenable interrupts. */
1994         CSR_WRITE_4(sc, JME_INTR_MASK_SET, JME_INTRS);
1995 }
1996
1997 static void
1998 jme_txeof(struct jme_softc *sc)
1999 {
2000         struct ifnet *ifp = &sc->arpcom.ac_if;
2001         struct jme_txdesc *txd;
2002         uint32_t status;
2003         int cons, nsegs;
2004
2005         cons = sc->jme_cdata.jme_tx_cons;
2006         if (cons == sc->jme_cdata.jme_tx_prod)
2007                 return;
2008
2009         /*
2010          * Go through our Tx list and free mbufs for those
2011          * frames which have been transmitted.
2012          */
2013         while (cons != sc->jme_cdata.jme_tx_prod) {
2014                 txd = &sc->jme_cdata.jme_txdesc[cons];
2015                 KASSERT(txd->tx_m != NULL,
2016                         ("%s: freeing NULL mbuf!", __func__));
2017
2018                 status = le32toh(txd->tx_desc->flags);
2019                 if ((status & JME_TD_OWN) == JME_TD_OWN)
2020                         break;
2021
2022                 if (status & (JME_TD_TMOUT | JME_TD_RETRY_EXP)) {
2023                         ifp->if_oerrors++;
2024                 } else {
2025                         ifp->if_opackets++;
2026                         if (status & JME_TD_COLLISION) {
2027                                 ifp->if_collisions +=
2028                                     le32toh(txd->tx_desc->buflen) &
2029                                     JME_TD_BUF_LEN_MASK;
2030                         }
2031                 }
2032
2033                 /*
2034                  * Only the first descriptor of multi-descriptor
2035                  * transmission is updated so driver have to skip entire
2036                  * chained buffers for the transmiited frame. In other
2037                  * words, JME_TD_OWN bit is valid only at the first
2038                  * descriptor of a multi-descriptor transmission.
2039                  */
2040                 for (nsegs = 0; nsegs < txd->tx_ndesc; nsegs++) {
2041                         sc->jme_cdata.jme_tx_ring[cons].flags = 0;
2042                         JME_DESC_INC(cons, sc->jme_cdata.jme_tx_desc_cnt);
2043                 }
2044
2045                 /* Reclaim transferred mbufs. */
2046                 bus_dmamap_unload(sc->jme_cdata.jme_tx_tag, txd->tx_dmamap);
2047                 m_freem(txd->tx_m);
2048                 txd->tx_m = NULL;
2049                 sc->jme_cdata.jme_tx_cnt -= txd->tx_ndesc;
2050                 KASSERT(sc->jme_cdata.jme_tx_cnt >= 0,
2051                         ("%s: Active Tx desc counter was garbled", __func__));
2052                 txd->tx_ndesc = 0;
2053         }
2054         sc->jme_cdata.jme_tx_cons = cons;
2055
2056         if (sc->jme_cdata.jme_tx_cnt == 0)
2057                 ifp->if_timer = 0;
2058
2059         if (sc->jme_cdata.jme_tx_cnt + sc->jme_txd_spare <=
2060             sc->jme_cdata.jme_tx_desc_cnt - JME_TXD_RSVD)
2061                 ifp->if_flags &= ~IFF_OACTIVE;
2062 }
2063
2064 static __inline void
2065 jme_discard_rxbufs(struct jme_rxdata *rdata, int cons, int count)
2066 {
2067         int i;
2068
2069         for (i = 0; i < count; ++i) {
2070                 jme_setup_rxdesc(&rdata->jme_rxdesc[cons]);
2071                 JME_DESC_INC(cons, rdata->jme_rx_desc_cnt);
2072         }
2073 }
2074
2075 static __inline struct pktinfo *
2076 jme_pktinfo(struct pktinfo *pi, uint32_t flags)
2077 {
2078         if (flags & JME_RD_IPV4)
2079                 pi->pi_netisr = NETISR_IP;
2080         else if (flags & JME_RD_IPV6)
2081                 pi->pi_netisr = NETISR_IPV6;
2082         else
2083                 return NULL;
2084
2085         pi->pi_flags = 0;
2086         pi->pi_l3proto = IPPROTO_UNKNOWN;
2087
2088         if (flags & JME_RD_MORE_FRAG)
2089                 pi->pi_flags |= PKTINFO_FLAG_FRAG;
2090         else if (flags & JME_RD_TCP)
2091                 pi->pi_l3proto = IPPROTO_TCP;
2092         else if (flags & JME_RD_UDP)
2093                 pi->pi_l3proto = IPPROTO_UDP;
2094         else
2095                 pi = NULL;
2096         return pi;
2097 }
2098
2099 /* Receive a frame. */
2100 static void
2101 jme_rxpkt(struct jme_rxdata *rdata)
2102 {
2103         struct ifnet *ifp = &rdata->jme_sc->arpcom.ac_if;
2104         struct jme_desc *desc;
2105         struct jme_rxdesc *rxd;
2106         struct mbuf *mp, *m;
2107         uint32_t flags, status, hash, hashinfo;
2108         int cons, count, nsegs;
2109
2110         cons = rdata->jme_rx_cons;
2111         desc = &rdata->jme_rx_ring[cons];
2112         flags = le32toh(desc->flags);
2113         status = le32toh(desc->buflen);
2114         hash = le32toh(desc->addr_hi);
2115         hashinfo = le32toh(desc->addr_lo);
2116         nsegs = JME_RX_NSEGS(status);
2117
2118         JME_RSS_DPRINTF(rdata->jme_sc, 15, "ring%d, flags 0x%08x, "
2119                         "hash 0x%08x, hash info 0x%08x\n",
2120                         rdata->jme_rx_idx, flags, hash, hashinfo);
2121
2122         if (status & JME_RX_ERR_STAT) {
2123                 ifp->if_ierrors++;
2124                 jme_discard_rxbufs(rdata, cons, nsegs);
2125 #ifdef JME_SHOW_ERRORS
2126                 if_printf(ifp, "%s : receive error = 0x%b\n",
2127                     __func__, JME_RX_ERR(status), JME_RX_ERR_BITS);
2128 #endif
2129                 rdata->jme_rx_cons += nsegs;
2130                 rdata->jme_rx_cons %= rdata->jme_rx_desc_cnt;
2131                 return;
2132         }
2133
2134         rdata->jme_rxlen = JME_RX_BYTES(status) - JME_RX_PAD_BYTES;
2135         for (count = 0; count < nsegs; count++,
2136              JME_DESC_INC(cons, rdata->jme_rx_desc_cnt)) {
2137                 rxd = &rdata->jme_rxdesc[cons];
2138                 mp = rxd->rx_m;
2139
2140                 /* Add a new receive buffer to the ring. */
2141                 if (jme_newbuf(rdata, rxd, 0) != 0) {
2142                         ifp->if_iqdrops++;
2143                         /* Reuse buffer. */
2144                         jme_discard_rxbufs(rdata, cons, nsegs - count);
2145                         if (rdata->jme_rxhead != NULL) {
2146                                 m_freem(rdata->jme_rxhead);
2147                                 JME_RXCHAIN_RESET(rdata);
2148                         }
2149                         break;
2150                 }
2151
2152                 /*
2153                  * Assume we've received a full sized frame.
2154                  * Actual size is fixed when we encounter the end of
2155                  * multi-segmented frame.
2156                  */
2157                 mp->m_len = MCLBYTES;
2158
2159                 /* Chain received mbufs. */
2160                 if (rdata->jme_rxhead == NULL) {
2161                         rdata->jme_rxhead = mp;
2162                         rdata->jme_rxtail = mp;
2163                 } else {
2164                         /*
2165                          * Receive processor can receive a maximum frame
2166                          * size of 65535 bytes.
2167                          */
2168                         rdata->jme_rxtail->m_next = mp;
2169                         rdata->jme_rxtail = mp;
2170                 }
2171
2172                 if (count == nsegs - 1) {
2173                         struct pktinfo pi0, *pi;
2174
2175                         /* Last desc. for this frame. */
2176                         m = rdata->jme_rxhead;
2177                         m->m_pkthdr.len = rdata->jme_rxlen;
2178                         if (nsegs > 1) {
2179                                 /* Set first mbuf size. */
2180                                 m->m_len = MCLBYTES - JME_RX_PAD_BYTES;
2181                                 /* Set last mbuf size. */
2182                                 mp->m_len = rdata->jme_rxlen -
2183                                     ((MCLBYTES - JME_RX_PAD_BYTES) +
2184                                     (MCLBYTES * (nsegs - 2)));
2185                         } else {
2186                                 m->m_len = rdata->jme_rxlen;
2187                         }
2188                         m->m_pkthdr.rcvif = ifp;
2189
2190                         /*
2191                          * Account for 10bytes auto padding which is used
2192                          * to align IP header on 32bit boundary. Also note,
2193                          * CRC bytes is automatically removed by the
2194                          * hardware.
2195                          */
2196                         m->m_data += JME_RX_PAD_BYTES;
2197
2198                         /* Set checksum information. */
2199                         if ((ifp->if_capenable & IFCAP_RXCSUM) &&
2200                             (flags & JME_RD_IPV4)) {
2201                                 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
2202                                 if (flags & JME_RD_IPCSUM)
2203                                         m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
2204                                 if ((flags & JME_RD_MORE_FRAG) == 0 &&
2205                                     ((flags & (JME_RD_TCP | JME_RD_TCPCSUM)) ==
2206                                      (JME_RD_TCP | JME_RD_TCPCSUM) ||
2207                                      (flags & (JME_RD_UDP | JME_RD_UDPCSUM)) ==
2208                                      (JME_RD_UDP | JME_RD_UDPCSUM))) {
2209                                         m->m_pkthdr.csum_flags |=
2210                                             CSUM_DATA_VALID | CSUM_PSEUDO_HDR;
2211                                         m->m_pkthdr.csum_data = 0xffff;
2212                                 }
2213                         }
2214
2215                         /* Check for VLAN tagged packets. */
2216                         if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) &&
2217                             (flags & JME_RD_VLAN_TAG)) {
2218                                 m->m_pkthdr.ether_vlantag =
2219                                     flags & JME_RD_VLAN_MASK;
2220                                 m->m_flags |= M_VLANTAG;
2221                         }
2222
2223                         ifp->if_ipackets++;
2224
2225                         if (ifp->if_capenable & IFCAP_RSS)
2226                                 pi = jme_pktinfo(&pi0, flags);
2227                         else
2228                                 pi = NULL;
2229
2230                         if (pi != NULL &&
2231                             (hashinfo & JME_RD_HASH_FN_MASK) != 0) {
2232                                 m->m_flags |= M_HASH;
2233                                 m->m_pkthdr.hash = toeplitz_hash(hash);
2234                         }
2235
2236 #ifdef JME_RSS_DEBUG
2237                         if (pi != NULL) {
2238                                 JME_RSS_DPRINTF(rdata->jme_sc, 10,
2239                                     "isr %d flags %08x, l3 %d %s\n",
2240                                     pi->pi_netisr, pi->pi_flags,
2241                                     pi->pi_l3proto,
2242                                     (m->m_flags & M_HASH) ? "hash" : "");
2243                         }
2244 #endif
2245
2246                         /* Pass it on. */
2247                         ether_input_pkt(ifp, m, pi);
2248
2249                         /* Reset mbuf chains. */
2250                         JME_RXCHAIN_RESET(rdata);
2251 #ifdef JME_RSS_DEBUG
2252                         rdata->jme_rx_pkt++;
2253 #endif
2254                 }
2255         }
2256
2257         rdata->jme_rx_cons += nsegs;
2258         rdata->jme_rx_cons %= rdata->jme_rx_desc_cnt;
2259 }
2260
2261 static void
2262 jme_rxeof(struct jme_rxdata *rdata, int count)
2263 {
2264         struct jme_desc *desc;
2265         int nsegs, pktlen;
2266
2267         for (;;) {
2268 #ifdef DEVICE_POLLING
2269                 if (count >= 0 && count-- == 0)
2270                         break;
2271 #endif
2272                 desc = &rdata->jme_rx_ring[rdata->jme_rx_cons];
2273                 if ((le32toh(desc->flags) & JME_RD_OWN) == JME_RD_OWN)
2274                         break;
2275                 if ((le32toh(desc->buflen) & JME_RD_VALID) == 0)
2276                         break;
2277
2278                 /*
2279                  * Check number of segments against received bytes.
2280                  * Non-matching value would indicate that hardware
2281                  * is still trying to update Rx descriptors. I'm not
2282                  * sure whether this check is needed.
2283                  */
2284                 nsegs = JME_RX_NSEGS(le32toh(desc->buflen));
2285                 pktlen = JME_RX_BYTES(le32toh(desc->buflen));
2286                 if (nsegs != howmany(pktlen, MCLBYTES)) {
2287                         if_printf(&rdata->jme_sc->arpcom.ac_if,
2288                             "RX fragment count(%d) and "
2289                             "packet size(%d) mismach\n", nsegs, pktlen);
2290                         break;
2291                 }
2292
2293                 /* Received a frame. */
2294                 jme_rxpkt(rdata);
2295         }
2296 }
2297
2298 static void
2299 jme_tick(void *xsc)
2300 {
2301         struct jme_softc *sc = xsc;
2302         struct ifnet *ifp = &sc->arpcom.ac_if;
2303         struct mii_data *mii = device_get_softc(sc->jme_miibus);
2304
2305         ifnet_serialize_all(ifp);
2306
2307         mii_tick(mii);
2308         callout_reset(&sc->jme_tick_ch, hz, jme_tick, sc);
2309
2310         ifnet_deserialize_all(ifp);
2311 }
2312
2313 static void
2314 jme_reset(struct jme_softc *sc)
2315 {
2316         uint32_t val;
2317
2318         /* Make sure that TX and RX are stopped */
2319         jme_stop_tx(sc);
2320         jme_stop_rx(sc);
2321
2322         /* Start reset */
2323         CSR_WRITE_4(sc, JME_GHC, GHC_RESET);
2324         DELAY(20);
2325
2326         /*
2327          * Hold reset bit before stop reset
2328          */
2329
2330         /* Disable TXMAC and TXOFL clock sources */
2331         CSR_WRITE_4(sc, JME_GHC, GHC_RESET);
2332         /* Disable RXMAC clock source */
2333         val = CSR_READ_4(sc, JME_GPREG1);
2334         CSR_WRITE_4(sc, JME_GPREG1, val | GPREG1_DIS_RXMAC_CLKSRC);
2335         /* Flush */
2336         CSR_READ_4(sc, JME_GHC);
2337
2338         /* Stop reset */
2339         CSR_WRITE_4(sc, JME_GHC, 0);
2340         /* Flush */
2341         CSR_READ_4(sc, JME_GHC);
2342
2343         /*
2344          * Clear reset bit after stop reset
2345          */
2346
2347         /* Enable TXMAC and TXOFL clock sources */
2348         CSR_WRITE_4(sc, JME_GHC, GHC_TXOFL_CLKSRC | GHC_TXMAC_CLKSRC);
2349         /* Enable RXMAC clock source */
2350         val = CSR_READ_4(sc, JME_GPREG1);
2351         CSR_WRITE_4(sc, JME_GPREG1, val & ~GPREG1_DIS_RXMAC_CLKSRC);
2352         /* Flush */
2353         CSR_READ_4(sc, JME_GHC);
2354
2355         /* Disable TXMAC and TXOFL clock sources */
2356         CSR_WRITE_4(sc, JME_GHC, 0);
2357         /* Disable RXMAC clock source */
2358         val = CSR_READ_4(sc, JME_GPREG1);
2359         CSR_WRITE_4(sc, JME_GPREG1, val | GPREG1_DIS_RXMAC_CLKSRC);
2360         /* Flush */
2361         CSR_READ_4(sc, JME_GHC);
2362
2363         /* Enable TX and RX */
2364         val = CSR_READ_4(sc, JME_TXCSR);
2365         CSR_WRITE_4(sc, JME_TXCSR, val | TXCSR_TX_ENB);
2366         val = CSR_READ_4(sc, JME_RXCSR);
2367         CSR_WRITE_4(sc, JME_RXCSR, val | RXCSR_RX_ENB);
2368         /* Flush */
2369         CSR_READ_4(sc, JME_TXCSR);
2370         CSR_READ_4(sc, JME_RXCSR);
2371
2372         /* Enable TXMAC and TXOFL clock sources */
2373         CSR_WRITE_4(sc, JME_GHC, GHC_TXOFL_CLKSRC | GHC_TXMAC_CLKSRC);
2374         /* Eisable RXMAC clock source */
2375         val = CSR_READ_4(sc, JME_GPREG1);
2376         CSR_WRITE_4(sc, JME_GPREG1, val & ~GPREG1_DIS_RXMAC_CLKSRC);
2377         /* Flush */
2378         CSR_READ_4(sc, JME_GHC);
2379
2380         /* Stop TX and RX */
2381         jme_stop_tx(sc);
2382         jme_stop_rx(sc);
2383 }
2384
2385 static void
2386 jme_init(void *xsc)
2387 {
2388         struct jme_softc *sc = xsc;
2389         struct ifnet *ifp = &sc->arpcom.ac_if;
2390         struct mii_data *mii;
2391         uint8_t eaddr[ETHER_ADDR_LEN];
2392         bus_addr_t paddr;
2393         uint32_t reg;
2394         int error, r;
2395
2396         ASSERT_IFNET_SERIALIZED_ALL(ifp);
2397
2398         /*
2399          * Cancel any pending I/O.
2400          */
2401         jme_stop(sc);
2402
2403         /*
2404          * Reset the chip to a known state.
2405          */
2406         jme_reset(sc);
2407
2408         /*
2409          * Setup MSI/MSI-X vectors to interrupts mapping
2410          */
2411         jme_set_msinum(sc);
2412
2413         sc->jme_txd_spare =
2414         howmany(ifp->if_mtu + sizeof(struct ether_vlan_header), MCLBYTES);
2415         KKASSERT(sc->jme_txd_spare >= 1);
2416
2417         /*
2418          * If we use 64bit address mode for transmitting, each Tx request
2419          * needs one more symbol descriptor.
2420          */
2421         if (sc->jme_lowaddr != BUS_SPACE_MAXADDR_32BIT)
2422                 sc->jme_txd_spare += 1;
2423
2424         if (sc->jme_cdata.jme_rx_ring_cnt > JME_NRXRING_MIN)
2425                 jme_enable_rss(sc);
2426         else
2427                 jme_disable_rss(sc);
2428
2429         /* Init RX descriptors */
2430         for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) {
2431                 error = jme_init_rx_ring(&sc->jme_cdata.jme_rx_data[r]);
2432                 if (error) {
2433                         if_printf(ifp, "initialization failed: "
2434                                   "no memory for %dth RX ring.\n", r);
2435                         jme_stop(sc);
2436                         return;
2437                 }
2438         }
2439
2440         /* Init TX descriptors */
2441         jme_init_tx_ring(sc);
2442
2443         /* Initialize shadow status block. */
2444         jme_init_ssb(sc);
2445
2446         /* Reprogram the station address. */
2447         bcopy(IF_LLADDR(ifp), eaddr, ETHER_ADDR_LEN);
2448         CSR_WRITE_4(sc, JME_PAR0,
2449             eaddr[3] << 24 | eaddr[2] << 16 | eaddr[1] << 8 | eaddr[0]);
2450         CSR_WRITE_4(sc, JME_PAR1, eaddr[5] << 8 | eaddr[4]);
2451
2452         /*
2453          * Configure Tx queue.
2454          *  Tx priority queue weight value : 0
2455          *  Tx FIFO threshold for processing next packet : 16QW
2456          *  Maximum Tx DMA length : 512
2457          *  Allow Tx DMA burst.
2458          */
2459         sc->jme_txcsr = TXCSR_TXQ_N_SEL(TXCSR_TXQ0);
2460         sc->jme_txcsr |= TXCSR_TXQ_WEIGHT(TXCSR_TXQ_WEIGHT_MIN);
2461         sc->jme_txcsr |= TXCSR_FIFO_THRESH_16QW;
2462         sc->jme_txcsr |= sc->jme_tx_dma_size;
2463         sc->jme_txcsr |= TXCSR_DMA_BURST;
2464         CSR_WRITE_4(sc, JME_TXCSR, sc->jme_txcsr);
2465
2466         /* Set Tx descriptor counter. */
2467         CSR_WRITE_4(sc, JME_TXQDC, sc->jme_cdata.jme_tx_desc_cnt);
2468
2469         /* Set Tx ring address to the hardware. */
2470         paddr = sc->jme_cdata.jme_tx_ring_paddr;
2471         CSR_WRITE_4(sc, JME_TXDBA_HI, JME_ADDR_HI(paddr));
2472         CSR_WRITE_4(sc, JME_TXDBA_LO, JME_ADDR_LO(paddr));
2473
2474         /* Configure TxMAC parameters. */
2475         reg = TXMAC_IFG1_DEFAULT | TXMAC_IFG2_DEFAULT | TXMAC_IFG_ENB;
2476         reg |= TXMAC_THRESH_1_PKT;
2477         reg |= TXMAC_CRC_ENB | TXMAC_PAD_ENB;
2478         CSR_WRITE_4(sc, JME_TXMAC, reg);
2479
2480         /*
2481          * Configure Rx queue.
2482          *  FIFO full threshold for transmitting Tx pause packet : 128T
2483          *  FIFO threshold for processing next packet : 128QW
2484          *  Rx queue 0 select
2485          *  Max Rx DMA length : 128
2486          *  Rx descriptor retry : 32
2487          *  Rx descriptor retry time gap : 256ns
2488          *  Don't receive runt/bad frame.
2489          */
2490         sc->jme_rxcsr = RXCSR_FIFO_FTHRESH_128T;
2491 #if 0
2492         /*
2493          * Since Rx FIFO size is 4K bytes, receiving frames larger
2494          * than 4K bytes will suffer from Rx FIFO overruns. So
2495          * decrease FIFO threshold to reduce the FIFO overruns for
2496          * frames larger than 4000 bytes.
2497          * For best performance of standard MTU sized frames use
2498          * maximum allowable FIFO threshold, 128QW.
2499          */
2500         if ((ifp->if_mtu + ETHER_HDR_LEN + EVL_ENCAPLEN + ETHER_CRC_LEN) >
2501             JME_RX_FIFO_SIZE)
2502                 sc->jme_rxcsr |= RXCSR_FIFO_THRESH_16QW;
2503         else
2504                 sc->jme_rxcsr |= RXCSR_FIFO_THRESH_128QW;
2505 #else
2506         /* Improve PCI Express compatibility */
2507         sc->jme_rxcsr |= RXCSR_FIFO_THRESH_16QW;
2508 #endif
2509         sc->jme_rxcsr |= sc->jme_rx_dma_size;
2510         sc->jme_rxcsr |= RXCSR_DESC_RT_CNT(RXCSR_DESC_RT_CNT_DEFAULT);
2511         sc->jme_rxcsr |= RXCSR_DESC_RT_GAP_256 & RXCSR_DESC_RT_GAP_MASK;
2512         /* XXX TODO DROP_BAD */
2513
2514         for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) {
2515                 struct jme_rxdata *rdata = &sc->jme_cdata.jme_rx_data[r];
2516
2517                 CSR_WRITE_4(sc, JME_RXCSR, sc->jme_rxcsr | RXCSR_RXQ_N_SEL(r));
2518
2519                 /* Set Rx descriptor counter. */
2520                 CSR_WRITE_4(sc, JME_RXQDC, rdata->jme_rx_desc_cnt);
2521
2522                 /* Set Rx ring address to the hardware. */
2523                 paddr = rdata->jme_rx_ring_paddr;
2524                 CSR_WRITE_4(sc, JME_RXDBA_HI, JME_ADDR_HI(paddr));
2525                 CSR_WRITE_4(sc, JME_RXDBA_LO, JME_ADDR_LO(paddr));
2526         }
2527
2528         /* Clear receive filter. */
2529         CSR_WRITE_4(sc, JME_RXMAC, 0);
2530
2531         /* Set up the receive filter. */
2532         jme_set_filter(sc);
2533         jme_set_vlan(sc);
2534
2535         /*
2536          * Disable all WOL bits as WOL can interfere normal Rx
2537          * operation. Also clear WOL detection status bits.
2538          */
2539         reg = CSR_READ_4(sc, JME_PMCS);
2540         reg &= ~PMCS_WOL_ENB_MASK;
2541         CSR_WRITE_4(sc, JME_PMCS, reg);
2542
2543         /*
2544          * Pad 10bytes right before received frame. This will greatly
2545          * help Rx performance on strict-alignment architectures as
2546          * it does not need to copy the frame to align the payload.
2547          */
2548         reg = CSR_READ_4(sc, JME_RXMAC);
2549         reg |= RXMAC_PAD_10BYTES;
2550
2551         if (ifp->if_capenable & IFCAP_RXCSUM)
2552                 reg |= RXMAC_CSUM_ENB;
2553         CSR_WRITE_4(sc, JME_RXMAC, reg);
2554
2555         /* Configure general purpose reg0 */
2556         reg = CSR_READ_4(sc, JME_GPREG0);
2557         reg &= ~GPREG0_PCC_UNIT_MASK;
2558         /* Set PCC timer resolution to micro-seconds unit. */
2559         reg |= GPREG0_PCC_UNIT_US;
2560         /*
2561          * Disable all shadow register posting as we have to read
2562          * JME_INTR_STATUS register in jme_intr. Also it seems
2563          * that it's hard to synchronize interrupt status between
2564          * hardware and software with shadow posting due to
2565          * requirements of bus_dmamap_sync(9).
2566          */
2567         reg |= GPREG0_SH_POST_DW7_DIS | GPREG0_SH_POST_DW6_DIS |
2568             GPREG0_SH_POST_DW5_DIS | GPREG0_SH_POST_DW4_DIS |
2569             GPREG0_SH_POST_DW3_DIS | GPREG0_SH_POST_DW2_DIS |
2570             GPREG0_SH_POST_DW1_DIS | GPREG0_SH_POST_DW0_DIS;
2571         /* Disable posting of DW0. */
2572         reg &= ~GPREG0_POST_DW0_ENB;
2573         /* Clear PME message. */
2574         reg &= ~GPREG0_PME_ENB;
2575         /* Set PHY address. */
2576         reg &= ~GPREG0_PHY_ADDR_MASK;
2577         reg |= sc->jme_phyaddr;
2578         CSR_WRITE_4(sc, JME_GPREG0, reg);
2579
2580         /* Configure Tx queue 0 packet completion coalescing. */
2581         jme_set_tx_coal(sc);
2582
2583         /* Configure Rx queues packet completion coalescing. */
2584         jme_set_rx_coal(sc);
2585
2586         /* Configure shadow status block but don't enable posting. */
2587         paddr = sc->jme_cdata.jme_ssb_block_paddr;
2588         CSR_WRITE_4(sc, JME_SHBASE_ADDR_HI, JME_ADDR_HI(paddr));
2589         CSR_WRITE_4(sc, JME_SHBASE_ADDR_LO, JME_ADDR_LO(paddr));
2590
2591         /* Disable Timer 1 and Timer 2. */
2592         CSR_WRITE_4(sc, JME_TIMER1, 0);
2593         CSR_WRITE_4(sc, JME_TIMER2, 0);
2594
2595         /* Configure retry transmit period, retry limit value. */
2596         CSR_WRITE_4(sc, JME_TXTRHD,
2597             ((TXTRHD_RT_PERIOD_DEFAULT << TXTRHD_RT_PERIOD_SHIFT) &
2598             TXTRHD_RT_PERIOD_MASK) |
2599             ((TXTRHD_RT_LIMIT_DEFAULT << TXTRHD_RT_LIMIT_SHIFT) &
2600             TXTRHD_RT_LIMIT_SHIFT));
2601
2602 #ifdef DEVICE_POLLING
2603         if (!(ifp->if_flags & IFF_POLLING))
2604 #endif
2605         /* Initialize the interrupt mask. */
2606         CSR_WRITE_4(sc, JME_INTR_MASK_SET, JME_INTRS);
2607         CSR_WRITE_4(sc, JME_INTR_STATUS, 0xFFFFFFFF);
2608
2609         /*
2610          * Enabling Tx/Rx DMA engines and Rx queue processing is
2611          * done after detection of valid link in jme_miibus_statchg.
2612          */
2613         sc->jme_flags &= ~JME_FLAG_LINK;
2614
2615         /* Set the current media. */
2616         mii = device_get_softc(sc->jme_miibus);
2617         mii_mediachg(mii);
2618
2619         callout_reset(&sc->jme_tick_ch, hz, jme_tick, sc);
2620
2621         ifp->if_flags |= IFF_RUNNING;
2622         ifp->if_flags &= ~IFF_OACTIVE;
2623 }
2624
2625 static void
2626 jme_stop(struct jme_softc *sc)
2627 {
2628         struct ifnet *ifp = &sc->arpcom.ac_if;
2629         struct jme_txdesc *txd;
2630         struct jme_rxdesc *rxd;
2631         struct jme_rxdata *rdata;
2632         int i, r;
2633
2634         ASSERT_IFNET_SERIALIZED_ALL(ifp);
2635
2636         /*
2637          * Mark the interface down and cancel the watchdog timer.
2638          */
2639         ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
2640         ifp->if_timer = 0;
2641
2642         callout_stop(&sc->jme_tick_ch);
2643         sc->jme_flags &= ~JME_FLAG_LINK;
2644
2645         /*
2646          * Disable interrupts.
2647          */
2648         CSR_WRITE_4(sc, JME_INTR_MASK_CLR, JME_INTRS);
2649         CSR_WRITE_4(sc, JME_INTR_STATUS, 0xFFFFFFFF);
2650
2651         /* Disable updating shadow status block. */
2652         CSR_WRITE_4(sc, JME_SHBASE_ADDR_LO,
2653             CSR_READ_4(sc, JME_SHBASE_ADDR_LO) & ~SHBASE_POST_ENB);
2654
2655         /* Stop receiver, transmitter. */
2656         jme_stop_rx(sc);
2657         jme_stop_tx(sc);
2658
2659         /*
2660          * Free partial finished RX segments
2661          */
2662         for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) {
2663                 rdata = &sc->jme_cdata.jme_rx_data[r];
2664                 if (rdata->jme_rxhead != NULL)
2665                         m_freem(rdata->jme_rxhead);
2666                 JME_RXCHAIN_RESET(rdata);
2667         }
2668
2669         /*
2670          * Free RX and TX mbufs still in the queues.
2671          */
2672         for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) {
2673                 rdata = &sc->jme_cdata.jme_rx_data[r];
2674                 for (i = 0; i < rdata->jme_rx_desc_cnt; i++) {
2675                         rxd = &rdata->jme_rxdesc[i];
2676                         if (rxd->rx_m != NULL) {
2677                                 bus_dmamap_unload(rdata->jme_rx_tag,
2678                                                   rxd->rx_dmamap);
2679                                 m_freem(rxd->rx_m);
2680                                 rxd->rx_m = NULL;
2681                         }
2682                 }
2683         }
2684         for (i = 0; i < sc->jme_cdata.jme_tx_desc_cnt; i++) {
2685                 txd = &sc->jme_cdata.jme_txdesc[i];
2686                 if (txd->tx_m != NULL) {
2687                         bus_dmamap_unload(sc->jme_cdata.jme_tx_tag,
2688                             txd->tx_dmamap);
2689                         m_freem(txd->tx_m);
2690                         txd->tx_m = NULL;
2691                         txd->tx_ndesc = 0;
2692                 }
2693         }
2694 }
2695
2696 static void
2697 jme_stop_tx(struct jme_softc *sc)
2698 {
2699         uint32_t reg;
2700         int i;
2701
2702         reg = CSR_READ_4(sc, JME_TXCSR);
2703         if ((reg & TXCSR_TX_ENB) == 0)
2704                 return;
2705         reg &= ~TXCSR_TX_ENB;
2706         CSR_WRITE_4(sc, JME_TXCSR, reg);
2707         for (i = JME_TIMEOUT; i > 0; i--) {
2708                 DELAY(1);
2709                 if ((CSR_READ_4(sc, JME_TXCSR) & TXCSR_TX_ENB) == 0)
2710                         break;
2711         }
2712         if (i == 0)
2713                 device_printf(sc->jme_dev, "stopping transmitter timeout!\n");
2714 }
2715
2716 static void
2717 jme_stop_rx(struct jme_softc *sc)
2718 {
2719         uint32_t reg;
2720         int i;
2721
2722         reg = CSR_READ_4(sc, JME_RXCSR);
2723         if ((reg & RXCSR_RX_ENB) == 0)
2724                 return;
2725         reg &= ~RXCSR_RX_ENB;
2726         CSR_WRITE_4(sc, JME_RXCSR, reg);
2727         for (i = JME_TIMEOUT; i > 0; i--) {
2728                 DELAY(1);
2729                 if ((CSR_READ_4(sc, JME_RXCSR) & RXCSR_RX_ENB) == 0)
2730                         break;
2731         }
2732         if (i == 0)
2733                 device_printf(sc->jme_dev, "stopping recevier timeout!\n");
2734 }
2735
2736 static void
2737 jme_init_tx_ring(struct jme_softc *sc)
2738 {
2739         struct jme_chain_data *cd;
2740         struct jme_txdesc *txd;
2741         int i;
2742
2743         sc->jme_cdata.jme_tx_prod = 0;
2744         sc->jme_cdata.jme_tx_cons = 0;
2745         sc->jme_cdata.jme_tx_cnt = 0;
2746
2747         cd = &sc->jme_cdata;
2748         bzero(cd->jme_tx_ring, JME_TX_RING_SIZE(sc));
2749         for (i = 0; i < sc->jme_cdata.jme_tx_desc_cnt; i++) {
2750                 txd = &sc->jme_cdata.jme_txdesc[i];
2751                 txd->tx_m = NULL;
2752                 txd->tx_desc = &cd->jme_tx_ring[i];
2753                 txd->tx_ndesc = 0;
2754         }
2755 }
2756
2757 static void
2758 jme_init_ssb(struct jme_softc *sc)
2759 {
2760         struct jme_chain_data *cd;
2761
2762         cd = &sc->jme_cdata;
2763         bzero(cd->jme_ssb_block, JME_SSB_SIZE);
2764 }
2765
2766 static int
2767 jme_init_rx_ring(struct jme_rxdata *rdata)
2768 {
2769         struct jme_rxdesc *rxd;
2770         int i;
2771
2772         KKASSERT(rdata->jme_rxhead == NULL &&
2773                  rdata->jme_rxtail == NULL &&
2774                  rdata->jme_rxlen == 0);
2775         rdata->jme_rx_cons = 0;
2776
2777         bzero(rdata->jme_rx_ring, JME_RX_RING_SIZE(rdata));
2778         for (i = 0; i < rdata->jme_rx_desc_cnt; i++) {
2779                 int error;
2780
2781                 rxd = &rdata->jme_rxdesc[i];
2782                 rxd->rx_m = NULL;
2783                 rxd->rx_desc = &rdata->jme_rx_ring[i];
2784                 error = jme_newbuf(rdata, rxd, 1);
2785                 if (error)
2786                         return error;
2787         }
2788         return 0;
2789 }
2790
2791 static int
2792 jme_newbuf(struct jme_rxdata *rdata, struct jme_rxdesc *rxd, int init)
2793 {
2794         struct mbuf *m;
2795         bus_dma_segment_t segs;
2796         bus_dmamap_t map;
2797         int error, nsegs;
2798
2799         m = m_getcl(init ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR);
2800         if (m == NULL)
2801                 return ENOBUFS;
2802         /*
2803          * JMC250 has 64bit boundary alignment limitation so jme(4)
2804          * takes advantage of 10 bytes padding feature of hardware
2805          * in order not to copy entire frame to align IP header on
2806          * 32bit boundary.
2807          */
2808         m->m_len = m->m_pkthdr.len = MCLBYTES;
2809
2810         error = bus_dmamap_load_mbuf_segment(rdata->jme_rx_tag,
2811                         rdata->jme_rx_sparemap, m, &segs, 1, &nsegs,
2812                         BUS_DMA_NOWAIT);
2813         if (error) {
2814                 m_freem(m);
2815                 if (init) {
2816                         if_printf(&rdata->jme_sc->arpcom.ac_if,
2817                             "can't load RX mbuf\n");
2818                 }
2819                 return error;
2820         }
2821
2822         if (rxd->rx_m != NULL) {
2823                 bus_dmamap_sync(rdata->jme_rx_tag, rxd->rx_dmamap,
2824                                 BUS_DMASYNC_POSTREAD);
2825                 bus_dmamap_unload(rdata->jme_rx_tag, rxd->rx_dmamap);
2826         }
2827         map = rxd->rx_dmamap;
2828         rxd->rx_dmamap = rdata->jme_rx_sparemap;
2829         rdata->jme_rx_sparemap = map;
2830         rxd->rx_m = m;
2831         rxd->rx_paddr = segs.ds_addr;
2832
2833         jme_setup_rxdesc(rxd);
2834         return 0;
2835 }
2836
2837 static void
2838 jme_set_vlan(struct jme_softc *sc)
2839 {
2840         struct ifnet *ifp = &sc->arpcom.ac_if;
2841         uint32_t reg;
2842
2843         ASSERT_IFNET_SERIALIZED_ALL(ifp);
2844
2845         reg = CSR_READ_4(sc, JME_RXMAC);
2846         reg &= ~RXMAC_VLAN_ENB;
2847         if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING)
2848                 reg |= RXMAC_VLAN_ENB;
2849         CSR_WRITE_4(sc, JME_RXMAC, reg);
2850 }
2851
2852 static void
2853 jme_set_filter(struct jme_softc *sc)
2854 {
2855         struct ifnet *ifp = &sc->arpcom.ac_if;
2856         struct ifmultiaddr *ifma;
2857         uint32_t crc;
2858         uint32_t mchash[2];
2859         uint32_t rxcfg;
2860
2861         ASSERT_IFNET_SERIALIZED_ALL(ifp);
2862
2863         rxcfg = CSR_READ_4(sc, JME_RXMAC);
2864         rxcfg &= ~(RXMAC_BROADCAST | RXMAC_PROMISC | RXMAC_MULTICAST |
2865             RXMAC_ALLMULTI);
2866
2867         /*
2868          * Always accept frames destined to our station address.
2869          * Always accept broadcast frames.
2870          */
2871         rxcfg |= RXMAC_UNICAST | RXMAC_BROADCAST;
2872
2873         if (ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) {
2874                 if (ifp->if_flags & IFF_PROMISC)
2875                         rxcfg |= RXMAC_PROMISC;
2876                 if (ifp->if_flags & IFF_ALLMULTI)
2877                         rxcfg |= RXMAC_ALLMULTI;
2878                 CSR_WRITE_4(sc, JME_MAR0, 0xFFFFFFFF);
2879                 CSR_WRITE_4(sc, JME_MAR1, 0xFFFFFFFF);
2880                 CSR_WRITE_4(sc, JME_RXMAC, rxcfg);
2881                 return;
2882         }
2883
2884         /*
2885          * Set up the multicast address filter by passing all multicast
2886          * addresses through a CRC generator, and then using the low-order
2887          * 6 bits as an index into the 64 bit multicast hash table.  The
2888          * high order bits select the register, while the rest of the bits
2889          * select the bit within the register.
2890          */
2891         rxcfg |= RXMAC_MULTICAST;
2892         bzero(mchash, sizeof(mchash));
2893
2894         TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
2895                 if (ifma->ifma_addr->sa_family != AF_LINK)
2896                         continue;
2897                 crc = ether_crc32_be(LLADDR((struct sockaddr_dl *)
2898                     ifma->ifma_addr), ETHER_ADDR_LEN);
2899
2900                 /* Just want the 6 least significant bits. */
2901                 crc &= 0x3f;
2902
2903                 /* Set the corresponding bit in the hash table. */
2904                 mchash[crc >> 5] |= 1 << (crc & 0x1f);
2905         }
2906
2907         CSR_WRITE_4(sc, JME_MAR0, mchash[0]);
2908         CSR_WRITE_4(sc, JME_MAR1, mchash[1]);
2909         CSR_WRITE_4(sc, JME_RXMAC, rxcfg);
2910 }
2911
2912 static int
2913 jme_sysctl_tx_coal_to(SYSCTL_HANDLER_ARGS)
2914 {
2915         struct jme_softc *sc = arg1;
2916         struct ifnet *ifp = &sc->arpcom.ac_if;
2917         int error, v;
2918
2919         ifnet_serialize_all(ifp);
2920
2921         v = sc->jme_tx_coal_to;
2922         error = sysctl_handle_int(oidp, &v, 0, req);
2923         if (error || req->newptr == NULL)
2924                 goto back;
2925
2926         if (v < PCCTX_COAL_TO_MIN || v > PCCTX_COAL_TO_MAX) {
2927                 error = EINVAL;
2928                 goto back;
2929         }
2930
2931         if (v != sc->jme_tx_coal_to) {
2932                 sc->jme_tx_coal_to = v;
2933                 if (ifp->if_flags & IFF_RUNNING)
2934                         jme_set_tx_coal(sc);
2935         }
2936 back:
2937         ifnet_deserialize_all(ifp);
2938         return error;
2939 }
2940
2941 static int
2942 jme_sysctl_tx_coal_pkt(SYSCTL_HANDLER_ARGS)
2943 {
2944         struct jme_softc *sc = arg1;
2945         struct ifnet *ifp = &sc->arpcom.ac_if;
2946         int error, v;
2947
2948         ifnet_serialize_all(ifp);
2949
2950         v = sc->jme_tx_coal_pkt;
2951         error = sysctl_handle_int(oidp, &v, 0, req);
2952         if (error || req->newptr == NULL)
2953                 goto back;
2954
2955         if (v < PCCTX_COAL_PKT_MIN || v > PCCTX_COAL_PKT_MAX) {
2956                 error = EINVAL;
2957                 goto back;
2958         }
2959
2960         if (v != sc->jme_tx_coal_pkt) {
2961                 sc->jme_tx_coal_pkt = v;
2962                 if (ifp->if_flags & IFF_RUNNING)
2963                         jme_set_tx_coal(sc);
2964         }
2965 back:
2966         ifnet_deserialize_all(ifp);
2967         return error;
2968 }
2969
2970 static int
2971 jme_sysctl_rx_coal_to(SYSCTL_HANDLER_ARGS)
2972 {
2973         struct jme_softc *sc = arg1;
2974         struct ifnet *ifp = &sc->arpcom.ac_if;
2975         int error, v;
2976
2977         ifnet_serialize_all(ifp);
2978
2979         v = sc->jme_rx_coal_to;
2980         error = sysctl_handle_int(oidp, &v, 0, req);
2981         if (error || req->newptr == NULL)
2982                 goto back;
2983
2984         if (v < PCCRX_COAL_TO_MIN || v > PCCRX_COAL_TO_MAX) {
2985                 error = EINVAL;
2986                 goto back;
2987         }
2988
2989         if (v != sc->jme_rx_coal_to) {
2990                 sc->jme_rx_coal_to = v;
2991                 if (ifp->if_flags & IFF_RUNNING)
2992                         jme_set_rx_coal(sc);
2993         }
2994 back:
2995         ifnet_deserialize_all(ifp);
2996         return error;
2997 }
2998
2999 static int
3000 jme_sysctl_rx_coal_pkt(SYSCTL_HANDLER_ARGS)
3001 {
3002         struct jme_softc *sc = arg1;
3003         struct ifnet *ifp = &sc->arpcom.ac_if;
3004         int error, v;
3005
3006         ifnet_serialize_all(ifp);
3007
3008         v = sc->jme_rx_coal_pkt;
3009         error = sysctl_handle_int(oidp, &v, 0, req);
3010         if (error || req->newptr == NULL)
3011                 goto back;
3012
3013         if (v < PCCRX_COAL_PKT_MIN || v > PCCRX_COAL_PKT_MAX) {
3014                 error = EINVAL;
3015                 goto back;
3016         }
3017
3018         if (v != sc->jme_rx_coal_pkt) {
3019                 sc->jme_rx_coal_pkt = v;
3020                 if (ifp->if_flags & IFF_RUNNING)
3021                         jme_set_rx_coal(sc);
3022         }
3023 back:
3024         ifnet_deserialize_all(ifp);
3025         return error;
3026 }
3027
3028 static void
3029 jme_set_tx_coal(struct jme_softc *sc)
3030 {
3031         uint32_t reg;
3032
3033         reg = (sc->jme_tx_coal_to << PCCTX_COAL_TO_SHIFT) &
3034             PCCTX_COAL_TO_MASK;
3035         reg |= (sc->jme_tx_coal_pkt << PCCTX_COAL_PKT_SHIFT) &
3036             PCCTX_COAL_PKT_MASK;
3037         reg |= PCCTX_COAL_TXQ0;
3038         CSR_WRITE_4(sc, JME_PCCTX, reg);
3039 }
3040
3041 static void
3042 jme_set_rx_coal(struct jme_softc *sc)
3043 {
3044         uint32_t reg;
3045         int r;
3046
3047         reg = (sc->jme_rx_coal_to << PCCRX_COAL_TO_SHIFT) &
3048             PCCRX_COAL_TO_MASK;
3049         reg |= (sc->jme_rx_coal_pkt << PCCRX_COAL_PKT_SHIFT) &
3050             PCCRX_COAL_PKT_MASK;
3051         for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r)
3052                 CSR_WRITE_4(sc, JME_PCCRX(r), reg);
3053 }
3054
3055 #ifdef DEVICE_POLLING
3056
3057 static void
3058 jme_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
3059 {
3060         struct jme_softc *sc = ifp->if_softc;
3061         uint32_t status;
3062         int r;
3063
3064         ASSERT_SERIALIZED(&sc->jme_serialize);
3065
3066         switch (cmd) {
3067         case POLL_REGISTER:
3068                 CSR_WRITE_4(sc, JME_INTR_MASK_CLR, JME_INTRS);
3069                 break;
3070
3071         case POLL_DEREGISTER:
3072                 CSR_WRITE_4(sc, JME_INTR_MASK_SET, JME_INTRS);
3073                 break;
3074
3075         case POLL_AND_CHECK_STATUS:
3076         case POLL_ONLY:
3077                 status = CSR_READ_4(sc, JME_INTR_STATUS);
3078
3079                 for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) {
3080                         struct jme_rxdata *rdata =
3081                             &sc->jme_cdata.jme_rx_data[r];
3082
3083                         lwkt_serialize_enter(&rdata->jme_rx_serialize);
3084                         jme_rxeof(rdata, count);
3085                         lwkt_serialize_exit(&rdata->jme_rx_serialize);
3086                 }
3087
3088                 if (status & INTR_RXQ_DESC_EMPTY) {
3089                         CSR_WRITE_4(sc, JME_INTR_STATUS, status);
3090                         CSR_WRITE_4(sc, JME_RXCSR, sc->jme_rxcsr |
3091                             RXCSR_RX_ENB | RXCSR_RXQ_START);
3092                 }
3093
3094                 lwkt_serialize_enter(&sc->jme_cdata.jme_tx_serialize);
3095                 jme_txeof(sc);
3096                 if (!ifq_is_empty(&ifp->if_snd))
3097                         if_devstart(ifp);
3098                 lwkt_serialize_exit(&sc->jme_cdata.jme_tx_serialize);
3099                 break;
3100         }
3101 }
3102
3103 #endif  /* DEVICE_POLLING */
3104
3105 static int
3106 jme_rxring_dma_alloc(struct jme_rxdata *rdata)
3107 {
3108         bus_dmamem_t dmem;
3109         int error, asize;
3110
3111         asize = roundup2(JME_RX_RING_SIZE(rdata), JME_RX_RING_ALIGN);
3112         error = bus_dmamem_coherent(rdata->jme_sc->jme_cdata.jme_ring_tag,
3113                         JME_RX_RING_ALIGN, 0,
3114                         BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
3115                         asize, BUS_DMA_WAITOK | BUS_DMA_ZERO, &dmem);
3116         if (error) {
3117                 device_printf(rdata->jme_sc->jme_dev,
3118                     "could not allocate %dth Rx ring.\n", rdata->jme_rx_idx);
3119                 return error;
3120         }
3121         rdata->jme_rx_ring_tag = dmem.dmem_tag;
3122         rdata->jme_rx_ring_map = dmem.dmem_map;
3123         rdata->jme_rx_ring = dmem.dmem_addr;
3124         rdata->jme_rx_ring_paddr = dmem.dmem_busaddr;
3125
3126         return 0;
3127 }
3128
3129 static int
3130 jme_rxbuf_dma_alloc(struct jme_rxdata *rdata)
3131 {
3132         int i, error;
3133
3134         /* Create tag for Rx buffers. */
3135         error = bus_dma_tag_create(
3136             rdata->jme_sc->jme_cdata.jme_buffer_tag,/* parent */
3137             JME_RX_BUF_ALIGN, 0,        /* algnmnt, boundary */
3138             BUS_SPACE_MAXADDR,          /* lowaddr */
3139             BUS_SPACE_MAXADDR,          /* highaddr */
3140             NULL, NULL,                 /* filter, filterarg */
3141             MCLBYTES,                   /* maxsize */
3142             1,                          /* nsegments */
3143             MCLBYTES,                   /* maxsegsize */
3144             BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK | BUS_DMA_ALIGNED,/* flags */
3145             &rdata->jme_rx_tag);
3146         if (error) {
3147                 device_printf(rdata->jme_sc->jme_dev,
3148                     "could not create %dth Rx DMA tag.\n", rdata->jme_rx_idx);
3149                 return error;
3150         }
3151
3152         /* Create DMA maps for Rx buffers. */
3153         error = bus_dmamap_create(rdata->jme_rx_tag, BUS_DMA_WAITOK,
3154                                   &rdata->jme_rx_sparemap);
3155         if (error) {
3156                 device_printf(rdata->jme_sc->jme_dev,
3157                     "could not create %dth spare Rx dmamap.\n",
3158                     rdata->jme_rx_idx);
3159                 bus_dma_tag_destroy(rdata->jme_rx_tag);
3160                 rdata->jme_rx_tag = NULL;
3161                 return error;
3162         }
3163         for (i = 0; i < rdata->jme_rx_desc_cnt; i++) {
3164                 struct jme_rxdesc *rxd = &rdata->jme_rxdesc[i];
3165
3166                 error = bus_dmamap_create(rdata->jme_rx_tag, BUS_DMA_WAITOK,
3167                                           &rxd->rx_dmamap);
3168                 if (error) {
3169                         int j;
3170
3171                         device_printf(rdata->jme_sc->jme_dev,
3172                             "could not create %dth Rx dmamap "
3173                             "for %dth RX ring.\n", i, rdata->jme_rx_idx);
3174
3175                         for (j = 0; j < i; ++j) {
3176                                 rxd = &rdata->jme_rxdesc[j];
3177                                 bus_dmamap_destroy(rdata->jme_rx_tag,
3178                                                    rxd->rx_dmamap);
3179                         }
3180                         bus_dmamap_destroy(rdata->jme_rx_tag,
3181                                            rdata->jme_rx_sparemap);
3182                         bus_dma_tag_destroy(rdata->jme_rx_tag);
3183                         rdata->jme_rx_tag = NULL;
3184                         return error;
3185                 }
3186         }
3187         return 0;
3188 }
3189
3190 static void
3191 jme_rx_intr(struct jme_softc *sc, uint32_t status)
3192 {
3193         int r;
3194
3195         for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) {
3196                 struct jme_rxdata *rdata = &sc->jme_cdata.jme_rx_data[r];
3197
3198                 if (status & rdata->jme_rx_coal) {
3199                         lwkt_serialize_enter(&rdata->jme_rx_serialize);
3200                         jme_rxeof(rdata, -1);
3201                         lwkt_serialize_exit(&rdata->jme_rx_serialize);
3202                 }
3203         }
3204 }
3205
3206 static void
3207 jme_enable_rss(struct jme_softc *sc)
3208 {
3209         uint32_t rssc, ind;
3210         uint8_t key[RSSKEY_NREGS * RSSKEY_REGSIZE];
3211         int i;
3212
3213         KASSERT(sc->jme_cdata.jme_rx_ring_cnt == JME_NRXRING_2 ||
3214                 sc->jme_cdata.jme_rx_ring_cnt == JME_NRXRING_4,
3215                 ("%s: invalid # of RX rings (%d)",
3216                  sc->arpcom.ac_if.if_xname, sc->jme_cdata.jme_rx_ring_cnt));
3217
3218         rssc = RSSC_HASH_64_ENTRY;
3219         rssc |= RSSC_HASH_IPV4 | RSSC_HASH_IPV4_TCP;
3220         rssc |= sc->jme_cdata.jme_rx_ring_cnt >> 1;
3221         JME_RSS_DPRINTF(sc, 1, "rssc 0x%08x\n", rssc);
3222         CSR_WRITE_4(sc, JME_RSSC, rssc);
3223
3224         toeplitz_get_key(key, sizeof(key));
3225         for (i = 0; i < RSSKEY_NREGS; ++i) {
3226                 uint32_t keyreg;
3227
3228                 keyreg = RSSKEY_REGVAL(key, i);
3229                 JME_RSS_DPRINTF(sc, 5, "keyreg%d 0x%08x\n", i, keyreg);
3230
3231                 CSR_WRITE_4(sc, RSSKEY_REG(i), keyreg);
3232         }
3233
3234         /*
3235          * Create redirect table in following fashion:
3236          * (hash & ring_cnt_mask) == rdr_table[(hash & rdr_table_mask)]
3237          */
3238         ind = 0;
3239         for (i = 0; i < RSSTBL_REGSIZE; ++i) {
3240                 int q;
3241
3242                 q = i % sc->jme_cdata.jme_rx_ring_cnt;
3243                 ind |= q << (i * 8);
3244         }
3245         JME_RSS_DPRINTF(sc, 1, "ind 0x%08x\n", ind);
3246
3247         for (i = 0; i < RSSTBL_NREGS; ++i)
3248                 CSR_WRITE_4(sc, RSSTBL_REG(i), ind);
3249 }
3250
3251 static void
3252 jme_disable_rss(struct jme_softc *sc)
3253 {
3254         CSR_WRITE_4(sc, JME_RSSC, RSSC_DIS_RSS);
3255 }
3256
3257 static void
3258 jme_serialize(struct ifnet *ifp, enum ifnet_serialize slz)
3259 {
3260         struct jme_softc *sc = ifp->if_softc;
3261
3262         switch (slz) {
3263         case IFNET_SERIALIZE_ALL:
3264                 lwkt_serialize_array_enter(sc->jme_serialize_arr,
3265                     sc->jme_serialize_cnt, 0);
3266                 break;
3267
3268         case IFNET_SERIALIZE_MAIN:
3269                 lwkt_serialize_enter(&sc->jme_serialize);
3270                 break;
3271
3272         case IFNET_SERIALIZE_TX:
3273                 lwkt_serialize_enter(&sc->jme_cdata.jme_tx_serialize);
3274                 break;
3275
3276         case IFNET_SERIALIZE_RX(0):
3277                 lwkt_serialize_enter(
3278                     &sc->jme_cdata.jme_rx_data[0].jme_rx_serialize);
3279                 break;
3280
3281         case IFNET_SERIALIZE_RX(1):
3282                 lwkt_serialize_enter(
3283                     &sc->jme_cdata.jme_rx_data[1].jme_rx_serialize);
3284                 break;
3285
3286         case IFNET_SERIALIZE_RX(2):
3287                 lwkt_serialize_enter(
3288                     &sc->jme_cdata.jme_rx_data[2].jme_rx_serialize);
3289                 break;
3290
3291         case IFNET_SERIALIZE_RX(3):
3292                 lwkt_serialize_enter(
3293                     &sc->jme_cdata.jme_rx_data[3].jme_rx_serialize);
3294                 break;
3295
3296         default:
3297                 panic("%s unsupported serialize type", ifp->if_xname);
3298         }
3299 }
3300
3301 static void
3302 jme_deserialize(struct ifnet *ifp, enum ifnet_serialize slz)
3303 {
3304         struct jme_softc *sc = ifp->if_softc;
3305
3306         switch (slz) {
3307         case IFNET_SERIALIZE_ALL:
3308                 lwkt_serialize_array_exit(sc->jme_serialize_arr,
3309                     sc->jme_serialize_cnt, 0);
3310                 break;
3311
3312         case IFNET_SERIALIZE_MAIN:
3313                 lwkt_serialize_exit(&sc->jme_serialize);
3314                 break;
3315
3316         case IFNET_SERIALIZE_TX:
3317                 lwkt_serialize_exit(&sc->jme_cdata.jme_tx_serialize);
3318                 break;
3319
3320         case IFNET_SERIALIZE_RX(0):
3321                 lwkt_serialize_exit(
3322                     &sc->jme_cdata.jme_rx_data[0].jme_rx_serialize);
3323                 break;
3324
3325         case IFNET_SERIALIZE_RX(1):
3326                 lwkt_serialize_exit(
3327                     &sc->jme_cdata.jme_rx_data[1].jme_rx_serialize);
3328                 break;
3329
3330         case IFNET_SERIALIZE_RX(2):
3331                 lwkt_serialize_exit(
3332                     &sc->jme_cdata.jme_rx_data[2].jme_rx_serialize);
3333                 break;
3334
3335         case IFNET_SERIALIZE_RX(3):
3336                 lwkt_serialize_exit(
3337                     &sc->jme_cdata.jme_rx_data[3].jme_rx_serialize);
3338                 break;
3339
3340         default:
3341                 panic("%s unsupported serialize type", ifp->if_xname);
3342         }
3343 }
3344
3345 static int
3346 jme_tryserialize(struct ifnet *ifp, enum ifnet_serialize slz)
3347 {
3348         struct jme_softc *sc = ifp->if_softc;
3349
3350         switch (slz) {
3351         case IFNET_SERIALIZE_ALL:
3352                 return lwkt_serialize_array_try(sc->jme_serialize_arr,
3353                     sc->jme_serialize_cnt, 0);
3354
3355         case IFNET_SERIALIZE_MAIN:
3356                 return lwkt_serialize_try(&sc->jme_serialize);
3357
3358         case IFNET_SERIALIZE_TX:
3359                 return lwkt_serialize_try(&sc->jme_cdata.jme_tx_serialize);
3360
3361         case IFNET_SERIALIZE_RX(0):
3362                 return lwkt_serialize_try(
3363                     &sc->jme_cdata.jme_rx_data[0].jme_rx_serialize);
3364
3365         case IFNET_SERIALIZE_RX(1):
3366                 return lwkt_serialize_try(
3367                     &sc->jme_cdata.jme_rx_data[1].jme_rx_serialize);
3368
3369         case IFNET_SERIALIZE_RX(2):
3370                 return lwkt_serialize_try(
3371                     &sc->jme_cdata.jme_rx_data[2].jme_rx_serialize);
3372
3373         case IFNET_SERIALIZE_RX(3):
3374                 return lwkt_serialize_try(
3375                     &sc->jme_cdata.jme_rx_data[3].jme_rx_serialize);
3376
3377         default:
3378                 panic("%s unsupported serialize type", ifp->if_xname);
3379         }
3380 }
3381
3382 #ifdef INVARIANTS
3383
3384 static void
3385 jme_serialize_assert(struct ifnet *ifp, enum ifnet_serialize slz,
3386     boolean_t serialized)
3387 {
3388         struct jme_softc *sc = ifp->if_softc;
3389         struct jme_rxdata *rdata;
3390         int i;
3391
3392         switch (slz) {
3393         case IFNET_SERIALIZE_ALL:
3394                 if (serialized) {
3395                         for (i = 0; i < sc->jme_serialize_cnt; ++i)
3396                                 ASSERT_SERIALIZED(sc->jme_serialize_arr[i]);
3397                 } else {
3398                         for (i = 0; i < sc->jme_serialize_cnt; ++i)
3399                                 ASSERT_NOT_SERIALIZED(sc->jme_serialize_arr[i]);
3400                 }
3401                 break;
3402
3403         case IFNET_SERIALIZE_MAIN:
3404                 if (serialized)
3405                         ASSERT_SERIALIZED(&sc->jme_serialize);
3406                 else
3407                         ASSERT_NOT_SERIALIZED(&sc->jme_serialize);
3408                 break;
3409
3410         case IFNET_SERIALIZE_TX:
3411                 if (serialized)
3412                         ASSERT_SERIALIZED(&sc->jme_cdata.jme_tx_serialize);
3413                 else
3414                         ASSERT_NOT_SERIALIZED(&sc->jme_cdata.jme_tx_serialize);
3415                 break;
3416
3417         case IFNET_SERIALIZE_RX(0):
3418                 rdata = &sc->jme_cdata.jme_rx_data[0];
3419                 if (serialized)
3420                         ASSERT_SERIALIZED(&rdata->jme_rx_serialize);
3421                 else
3422                         ASSERT_NOT_SERIALIZED(&rdata->jme_rx_serialize);
3423                 break;
3424
3425         case IFNET_SERIALIZE_RX(1):
3426                 rdata = &sc->jme_cdata.jme_rx_data[1];
3427                 if (serialized)
3428                         ASSERT_SERIALIZED(&rdata->jme_rx_serialize);
3429                 else
3430                         ASSERT_NOT_SERIALIZED(&rdata->jme_rx_serialize);
3431                 break;
3432
3433         case IFNET_SERIALIZE_RX(2):
3434                 rdata = &sc->jme_cdata.jme_rx_data[2];
3435                 if (serialized)
3436                         ASSERT_SERIALIZED(&rdata->jme_rx_serialize);
3437                 else
3438                         ASSERT_NOT_SERIALIZED(&rdata->jme_rx_serialize);
3439                 break;
3440
3441         case IFNET_SERIALIZE_RX(3):
3442                 rdata = &sc->jme_cdata.jme_rx_data[3];
3443                 if (serialized)
3444                         ASSERT_SERIALIZED(&rdata->jme_rx_serialize);
3445                 else
3446                         ASSERT_NOT_SERIALIZED(&rdata->jme_rx_serialize);
3447                 break;
3448
3449         default:
3450                 panic("%s unsupported serialize type", ifp->if_xname);
3451         }
3452 }
3453
3454 #endif  /* INVARIANTS */
3455
3456 static void
3457 jme_msix_try_alloc(device_t dev)
3458 {
3459         struct jme_softc *sc = device_get_softc(dev);
3460         struct jme_msix_data *msix;
3461         int error, i, r, msix_enable, msix_count;
3462
3463         msix_count = 1 + sc->jme_cdata.jme_rx_ring_cnt;
3464         KKASSERT(msix_count <= JME_NMSIX);
3465
3466         msix_enable = device_getenv_int(dev, "msix.enable", jme_msix_enable);
3467
3468         /*
3469          * We leave the 1st MSI-X vector unused, so we
3470          * actually need msix_count + 1 MSI-X vectors.
3471          */
3472         if (!msix_enable || pci_msix_count(dev) < (msix_count + 1))
3473                 return;
3474
3475         for (i = 0; i < msix_count; ++i)
3476                 sc->jme_msix[i].jme_msix_rid = -1;
3477
3478         i = 0;
3479
3480         msix = &sc->jme_msix[i++];
3481         msix->jme_msix_cpuid = 0;               /* XXX Put TX to cpu0 */
3482         msix->jme_msix_arg = &sc->jme_cdata;
3483         msix->jme_msix_func = jme_msix_tx;
3484         msix->jme_msix_intrs = INTR_TXQ_COAL | INTR_TXQ_COAL_TO;
3485         msix->jme_msix_serialize = &sc->jme_cdata.jme_tx_serialize;
3486         ksnprintf(msix->jme_msix_desc, sizeof(msix->jme_msix_desc), "%s tx",
3487             device_get_nameunit(dev));
3488
3489         for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) {
3490                 struct jme_rxdata *rdata = &sc->jme_cdata.jme_rx_data[r];
3491
3492                 msix = &sc->jme_msix[i++];
3493                 msix->jme_msix_cpuid = r;       /* XXX Put RX to cpuX */
3494                 msix->jme_msix_arg = rdata;
3495                 msix->jme_msix_func = jme_msix_rx;
3496                 msix->jme_msix_intrs = rdata->jme_rx_coal | rdata->jme_rx_empty;
3497                 msix->jme_msix_serialize = &rdata->jme_rx_serialize;
3498                 ksnprintf(msix->jme_msix_desc, sizeof(msix->jme_msix_desc),
3499                     "%s rx%d", device_get_nameunit(dev), r);
3500         }
3501
3502         KKASSERT(i == msix_count);
3503
3504         error = pci_setup_msix(dev);
3505         if (error)
3506                 return;
3507
3508         /* Setup jme_msix_cnt early, so we could cleanup */
3509         sc->jme_msix_cnt = msix_count;
3510
3511         for (i = 0; i < msix_count; ++i) {
3512                 msix = &sc->jme_msix[i];
3513
3514                 msix->jme_msix_vector = i + 1;
3515                 error = pci_alloc_msix_vector(dev, msix->jme_msix_vector,
3516                     &msix->jme_msix_rid, msix->jme_msix_cpuid);
3517                 if (error)
3518                         goto back;
3519
3520                 msix->jme_msix_res = bus_alloc_resource_any(dev, SYS_RES_IRQ,
3521                     &msix->jme_msix_rid, RF_ACTIVE);
3522                 if (msix->jme_msix_res == NULL) {
3523                         error = ENOMEM;
3524                         goto back;
3525                 }
3526         }
3527
3528         for (i = 0; i < JME_INTR_CNT; ++i) {
3529                 uint32_t intr_mask = (1 << i);
3530                 int x;
3531
3532                 if ((JME_INTRS & intr_mask) == 0)
3533                         continue;
3534
3535                 for (x = 0; x < msix_count; ++x) {
3536                         msix = &sc->jme_msix[x];
3537                         if (msix->jme_msix_intrs & intr_mask) {
3538                                 int reg, shift;
3539
3540                                 reg = i / JME_MSINUM_FACTOR;
3541                                 KKASSERT(reg < JME_MSINUM_CNT);
3542
3543                                 shift = (i % JME_MSINUM_FACTOR) * 4;
3544
3545                                 sc->jme_msinum[reg] |=
3546                                     (msix->jme_msix_vector << shift);
3547
3548                                 break;
3549                         }
3550                 }
3551         }
3552
3553         if (bootverbose) {
3554                 for (i = 0; i < JME_MSINUM_CNT; ++i) {
3555                         device_printf(dev, "MSINUM%d: %#x\n", i,
3556                             sc->jme_msinum[i]);
3557                 }
3558         }
3559
3560         pci_enable_msix(dev);
3561         sc->jme_irq_type = PCI_INTR_TYPE_MSIX;
3562
3563 back:
3564         if (error)
3565                 jme_msix_free(dev);
3566 }
3567
3568 static int
3569 jme_intr_alloc(device_t dev)
3570 {
3571         struct jme_softc *sc = device_get_softc(dev);
3572         u_int irq_flags;
3573
3574         jme_msix_try_alloc(dev);
3575
3576         if (sc->jme_irq_type != PCI_INTR_TYPE_MSIX) {
3577                 sc->jme_irq_type = pci_alloc_1intr(dev, jme_msi_enable,
3578                     &sc->jme_irq_rid, &irq_flags);
3579
3580                 sc->jme_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ,
3581                     &sc->jme_irq_rid, irq_flags);
3582                 if (sc->jme_irq_res == NULL) {
3583                         device_printf(dev, "can't allocate irq\n");
3584                         return ENXIO;
3585                 }
3586         }
3587         return 0;
3588 }
3589
3590 static void
3591 jme_msix_free(device_t dev)
3592 {
3593         struct jme_softc *sc = device_get_softc(dev);
3594         int i;
3595
3596         KKASSERT(sc->jme_msix_cnt > 1);
3597
3598         for (i = 0; i < sc->jme_msix_cnt; ++i) {
3599                 struct jme_msix_data *msix = &sc->jme_msix[i];
3600
3601                 if (msix->jme_msix_res != NULL) {
3602                         bus_release_resource(dev, SYS_RES_IRQ,
3603                             msix->jme_msix_rid, msix->jme_msix_res);
3604                         msix->jme_msix_res = NULL;
3605                 }
3606                 if (msix->jme_msix_rid >= 0) {
3607                         pci_release_msix_vector(dev, msix->jme_msix_rid);
3608                         msix->jme_msix_rid = -1;
3609                 }
3610         }
3611         pci_teardown_msix(dev);
3612 }
3613
3614 static void
3615 jme_intr_free(device_t dev)
3616 {
3617         struct jme_softc *sc = device_get_softc(dev);
3618
3619         if (sc->jme_irq_type != PCI_INTR_TYPE_MSIX) {
3620                 if (sc->jme_irq_res != NULL) {
3621                         bus_release_resource(dev, SYS_RES_IRQ, sc->jme_irq_rid,
3622                                              sc->jme_irq_res);
3623                 }
3624                 if (sc->jme_irq_type == PCI_INTR_TYPE_MSI)
3625                         pci_release_msi(dev);
3626         } else {
3627                 jme_msix_free(dev);
3628         }
3629 }
3630
3631 static void
3632 jme_msix_tx(void *xcd)
3633 {
3634         struct jme_chain_data *cd = xcd;
3635         struct jme_softc *sc = cd->jme_sc;
3636         struct ifnet *ifp = &sc->arpcom.ac_if;
3637
3638         ASSERT_SERIALIZED(&cd->jme_tx_serialize);
3639
3640         CSR_WRITE_4(sc, JME_INTR_MASK_CLR, INTR_TXQ_COAL | INTR_TXQ_COAL_TO);
3641
3642         CSR_WRITE_4(sc, JME_INTR_STATUS,
3643             INTR_TXQ_COAL | INTR_TXQ_COAL_TO | INTR_TXQ_COMP);
3644
3645         if (ifp->if_flags & IFF_RUNNING) {
3646                 jme_txeof(sc);
3647                 if (!ifq_is_empty(&ifp->if_snd))
3648                         if_devstart(ifp);
3649         }
3650
3651         CSR_WRITE_4(sc, JME_INTR_MASK_SET, INTR_TXQ_COAL | INTR_TXQ_COAL_TO);
3652 }
3653
3654 static void
3655 jme_msix_rx(void *xrdata)
3656 {
3657         struct jme_rxdata *rdata = xrdata;
3658         struct jme_softc *sc = rdata->jme_sc;
3659         struct ifnet *ifp = &sc->arpcom.ac_if;
3660         uint32_t status;
3661
3662         ASSERT_SERIALIZED(&rdata->jme_rx_serialize);
3663
3664         CSR_WRITE_4(sc, JME_INTR_MASK_CLR,
3665             (rdata->jme_rx_coal | rdata->jme_rx_empty));
3666
3667         status = CSR_READ_4(sc, JME_INTR_STATUS);
3668         status &= (rdata->jme_rx_coal | rdata->jme_rx_empty);
3669
3670         if (status & rdata->jme_rx_coal)
3671                 status |= (rdata->jme_rx_coal | rdata->jme_rx_comp);
3672         CSR_WRITE_4(sc, JME_INTR_STATUS, status);
3673
3674         if (ifp->if_flags & IFF_RUNNING) {
3675                 if (status & rdata->jme_rx_coal)
3676                         jme_rxeof(rdata, -1);
3677
3678                 if (status & rdata->jme_rx_empty) {
3679                         CSR_WRITE_4(sc, JME_RXCSR, sc->jme_rxcsr |
3680                             RXCSR_RX_ENB | RXCSR_RXQ_START);
3681                 }
3682         }
3683
3684         CSR_WRITE_4(sc, JME_INTR_MASK_SET,
3685             (rdata->jme_rx_coal | rdata->jme_rx_empty));
3686 }
3687
3688 static void
3689 jme_set_msinum(struct jme_softc *sc)
3690 {
3691         int i;
3692
3693         for (i = 0; i < JME_MSINUM_CNT; ++i)
3694                 CSR_WRITE_4(sc, JME_MSINUM(i), sc->jme_msinum[i]);
3695 }
3696
3697 static int
3698 jme_intr_setup(device_t dev)
3699 {
3700         struct jme_softc *sc = device_get_softc(dev);
3701         struct ifnet *ifp = &sc->arpcom.ac_if;
3702         int error;
3703
3704         if (sc->jme_irq_type == PCI_INTR_TYPE_MSIX)
3705                 return jme_msix_setup(dev);
3706
3707         error = bus_setup_intr(dev, sc->jme_irq_res, INTR_MPSAFE,
3708             jme_intr, sc, &sc->jme_irq_handle, &sc->jme_serialize);
3709         if (error) {
3710                 device_printf(dev, "could not set up interrupt handler.\n");
3711                 return error;
3712         }
3713
3714         ifp->if_cpuid = rman_get_cpuid(sc->jme_irq_res);
3715         KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus);
3716         return 0;
3717 }
3718
3719 static void
3720 jme_intr_teardown(device_t dev)
3721 {
3722         struct jme_softc *sc = device_get_softc(dev);
3723
3724         if (sc->jme_irq_type == PCI_INTR_TYPE_MSIX)
3725                 jme_msix_teardown(dev, sc->jme_msix_cnt);
3726         else
3727                 bus_teardown_intr(dev, sc->jme_irq_res, sc->jme_irq_handle);
3728 }
3729
3730 static int
3731 jme_msix_setup(device_t dev)
3732 {
3733         struct jme_softc *sc = device_get_softc(dev);
3734         struct ifnet *ifp = &sc->arpcom.ac_if;
3735         int x;
3736
3737         for (x = 0; x < sc->jme_msix_cnt; ++x) {
3738                 struct jme_msix_data *msix = &sc->jme_msix[x];
3739                 int error;
3740
3741                 error = bus_setup_intr_descr(dev, msix->jme_msix_res,
3742                     INTR_MPSAFE, msix->jme_msix_func, msix->jme_msix_arg,
3743                     &msix->jme_msix_handle, msix->jme_msix_serialize,
3744                     msix->jme_msix_desc);
3745                 if (error) {
3746                         device_printf(dev, "could not set up %s "
3747                             "interrupt handler.\n", msix->jme_msix_desc);
3748                         jme_msix_teardown(dev, x);
3749                         return error;
3750                 }
3751         }
3752         ifp->if_cpuid = 0; /* XXX */
3753         return 0;
3754 }
3755
3756 static void
3757 jme_msix_teardown(device_t dev, int msix_count)
3758 {
3759         struct jme_softc *sc = device_get_softc(dev);
3760         int x;
3761
3762         for (x = 0; x < msix_count; ++x) {
3763                 struct jme_msix_data *msix = &sc->jme_msix[x];
3764
3765                 bus_teardown_intr(dev, msix->jme_msix_res,
3766                     msix->jme_msix_handle);
3767         }
3768 }