sys/dev/netif/jme/if_jme.c

   1 /*-
   2  * Copyright (c) 2008, Pyun YongHyeon <yongari@FreeBSD.org>
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions
   7  * are met:
   8  * 1. Redistributions of source code must retain the above copyright
   9  *    notice unmodified, this list of conditions, and the following
  10  *    disclaimer.
  11  * 2. Redistributions in binary form must reproduce the above copyright
  12  *    notice, this list of conditions and the following disclaimer in the
  13  *    documentation and/or other materials provided with the distribution.
  14  *
  15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  16  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  17  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  18  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  19  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  20  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  21  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  22  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  23  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  24  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  25  * SUCH DAMAGE.
  26  *
  27  * $FreeBSD: src/sys/dev/jme/if_jme.c,v 1.2 2008/07/18 04:20:48 yongari Exp $
  28  */
  29
  30 #include "opt_polling.h"
  31 #include "opt_rss.h"
  32 #include "opt_jme.h"
  33
  34 #include <sys/param.h>
  35 #include <sys/endian.h>
  36 #include <sys/kernel.h>
  37 #include <sys/bus.h>
  38 #include <sys/interrupt.h>
  39 #include <sys/malloc.h>
  40 #include <sys/proc.h>
  41 #include <sys/rman.h>
  42 #include <sys/serialize.h>
  43 #include <sys/serialize2.h>
  44 #include <sys/socket.h>
  45 #include <sys/sockio.h>
  46 #include <sys/sysctl.h>
  47
  48 #include <net/ethernet.h>
  49 #include <net/if.h>
  50 #include <net/bpf.h>
  51 #include <net/if_arp.h>
  52 #include <net/if_dl.h>
  53 #include <net/if_media.h>
  54 #include <net/ifq_var.h>
  55 #include <net/toeplitz.h>
  56 #include <net/toeplitz2.h>
  57 #include <net/vlan/if_vlan_var.h>
  58 #include <net/vlan/if_vlan_ether.h>
  59
  60 #include <netinet/in.h>
  61
  62 #include <dev/netif/mii_layer/miivar.h>
  63 #include <dev/netif/mii_layer/jmphyreg.h>
  64
  65 #include <bus/pci/pcireg.h>
  66 #include <bus/pci/pcivar.h>
  67 #include <bus/pci/pcidevs.h>
  68
  69 #include <dev/netif/jme/if_jmereg.h>
  70 #include <dev/netif/jme/if_jmevar.h>
  71
  72 #include "miibus_if.h"
  73
  74 /* Define the following to disable printing Rx errors. */
  75 #undef  JME_SHOW_ERRORS
  76
  77 #define JME_CSUM_FEATURES       (CSUM_IP | CSUM_TCP | CSUM_UDP)
  78
  79 #ifdef JME_RSS_DEBUG
  80 #define JME_RSS_DPRINTF(sc, lvl, fmt, ...) \
  81 do { \
  82         if ((sc)->jme_rss_debug >= (lvl)) \
  83                 if_printf(&(sc)->arpcom.ac_if, fmt, __VA_ARGS__); \
  84 } while (0)
  85 #else   /* !JME_RSS_DEBUG */
  86 #define JME_RSS_DPRINTF(sc, lvl, fmt, ...)      ((void)0)
  87 #endif  /* JME_RSS_DEBUG */
  88
  89 static int      jme_probe(device_t);
  90 static int      jme_attach(device_t);
  91 static int      jme_detach(device_t);
  92 static int      jme_shutdown(device_t);
  93 static int      jme_suspend(device_t);
  94 static int      jme_resume(device_t);
  95
  96 static int      jme_miibus_readreg(device_t, int, int);
  97 static int      jme_miibus_writereg(device_t, int, int, int);
  98 static void     jme_miibus_statchg(device_t);
  99
 100 static void     jme_init(void *);
 101 static int      jme_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
 102 static void     jme_start(struct ifnet *);
 103 static void     jme_watchdog(struct ifnet *);
 104 static void     jme_mediastatus(struct ifnet *, struct ifmediareq *);
 105 static int      jme_mediachange(struct ifnet *);
 106 #ifdef DEVICE_POLLING
 107 static void     jme_poll(struct ifnet *, enum poll_cmd, int);
 108 #endif
 109 static void     jme_serialize(struct ifnet *, enum ifnet_serialize);
 110 static void     jme_deserialize(struct ifnet *, enum ifnet_serialize);
 111 static int      jme_tryserialize(struct ifnet *, enum ifnet_serialize);
 112 #ifdef INVARIANTS
 113 static void     jme_serialize_assert(struct ifnet *, enum ifnet_serialize,
 114                     boolean_t);
 115 #endif
 116
 117 static void     jme_intr(void *);
 118 static void     jme_msix_tx(void *);
 119 static void     jme_msix_rx(void *);
 120 static void     jme_txeof(struct jme_softc *);
 121 static void     jme_rxeof(struct jme_softc *, int, int);
 122 static void     jme_rx_intr(struct jme_softc *, uint32_t);
 123
 124 static int      jme_msix_setup(device_t);
 125 static void     jme_msix_teardown(device_t, int);
 126 static int      jme_intr_setup(device_t);
 127 static void     jme_intr_teardown(device_t);
 128 static void     jme_msix_try_alloc(device_t);
 129 static void     jme_msix_free(device_t);
 130 static int      jme_intr_alloc(device_t);
 131 static void     jme_intr_free(device_t);
 132 static int      jme_dma_alloc(struct jme_softc *);
 133 static void     jme_dma_free(struct jme_softc *);
 134 static int      jme_init_rx_ring(struct jme_softc *, int);
 135 static void     jme_init_tx_ring(struct jme_softc *);
 136 static void     jme_init_ssb(struct jme_softc *);
 137 static int      jme_newbuf(struct jme_softc *, int, struct jme_rxdesc *, int);
 138 static int      jme_encap(struct jme_softc *, struct mbuf **);
 139 static void     jme_rxpkt(struct jme_softc *, int);
 140 static int      jme_rxring_dma_alloc(struct jme_softc *, int);
 141 static int      jme_rxbuf_dma_alloc(struct jme_softc *, int);
 142
 143 static void     jme_tick(void *);
 144 static void     jme_stop(struct jme_softc *);
 145 static void     jme_reset(struct jme_softc *);
 146 static void     jme_set_msinum(struct jme_softc *);
 147 static void     jme_set_vlan(struct jme_softc *);
 148 static void     jme_set_filter(struct jme_softc *);
 149 static void     jme_stop_tx(struct jme_softc *);
 150 static void     jme_stop_rx(struct jme_softc *);
 151 static void     jme_mac_config(struct jme_softc *);
 152 static void     jme_reg_macaddr(struct jme_softc *, uint8_t[]);
 153 static int      jme_eeprom_macaddr(struct jme_softc *, uint8_t[]);
 154 static int      jme_eeprom_read_byte(struct jme_softc *, uint8_t, uint8_t *);
 155 #ifdef notyet
 156 static void     jme_setwol(struct jme_softc *);
 157 static void     jme_setlinkspeed(struct jme_softc *);
 158 #endif
 159 static void     jme_set_tx_coal(struct jme_softc *);
 160 static void     jme_set_rx_coal(struct jme_softc *);
 161 static void     jme_enable_rss(struct jme_softc *);
 162 static void     jme_disable_rss(struct jme_softc *);
 163
 164 static void     jme_sysctl_node(struct jme_softc *);
 165 static int      jme_sysctl_tx_coal_to(SYSCTL_HANDLER_ARGS);
 166 static int      jme_sysctl_tx_coal_pkt(SYSCTL_HANDLER_ARGS);
 167 static int      jme_sysctl_rx_coal_to(SYSCTL_HANDLER_ARGS);
 168 static int      jme_sysctl_rx_coal_pkt(SYSCTL_HANDLER_ARGS);
 169
 170 /*
 171  * Devices supported by this driver.
 172  */
 173 static const struct jme_dev {
 174         uint16_t        jme_vendorid;
 175         uint16_t        jme_deviceid;
 176         uint32_t        jme_caps;
 177         const char      *jme_name;
 178 } jme_devs[] = {
 179         { PCI_VENDOR_JMICRON, PCI_PRODUCT_JMICRON_JMC250,
 180             JME_CAP_JUMBO,
 181             "JMicron Inc, JMC250 Gigabit Ethernet" },
 182         { PCI_VENDOR_JMICRON, PCI_PRODUCT_JMICRON_JMC260,
 183             JME_CAP_FASTETH,
 184             "JMicron Inc, JMC260 Fast Ethernet" },
 185         { 0, 0, 0, NULL }
 186 };
 187
 188 static device_method_t jme_methods[] = {
 189         /* Device interface. */
 190         DEVMETHOD(device_probe,         jme_probe),
 191         DEVMETHOD(device_attach,        jme_attach),
 192         DEVMETHOD(device_detach,        jme_detach),
 193         DEVMETHOD(device_shutdown,      jme_shutdown),
 194         DEVMETHOD(device_suspend,       jme_suspend),
 195         DEVMETHOD(device_resume,        jme_resume),
 196
 197         /* Bus interface. */
 198         DEVMETHOD(bus_print_child,      bus_generic_print_child),
 199         DEVMETHOD(bus_driver_added,     bus_generic_driver_added),
 200
 201         /* MII interface. */
 202         DEVMETHOD(miibus_readreg,       jme_miibus_readreg),
 203         DEVMETHOD(miibus_writereg,      jme_miibus_writereg),
 204         DEVMETHOD(miibus_statchg,       jme_miibus_statchg),
 205
 206         { NULL, NULL }
 207 };
 208
 209 static driver_t jme_driver = {
 210         "jme",
 211         jme_methods,
 212         sizeof(struct jme_softc)
 213 };
 214
 215 static devclass_t jme_devclass;
 216
 217 DECLARE_DUMMY_MODULE(if_jme);
 218 MODULE_DEPEND(if_jme, miibus, 1, 1, 1);
 219 DRIVER_MODULE(if_jme, pci, jme_driver, jme_devclass, NULL, NULL);
 220 DRIVER_MODULE(miibus, jme, miibus_driver, miibus_devclass, NULL, NULL);
 221
 222 static const struct {
 223         uint32_t        jme_coal;
 224         uint32_t        jme_comp;
 225         uint32_t        jme_empty;
 226 } jme_rx_status[JME_NRXRING_MAX] = {
 227         { INTR_RXQ0_COAL | INTR_RXQ0_COAL_TO, INTR_RXQ0_COMP,
 228           INTR_RXQ0_DESC_EMPTY },
 229         { INTR_RXQ1_COAL | INTR_RXQ1_COAL_TO, INTR_RXQ1_COMP,
 230           INTR_RXQ1_DESC_EMPTY },
 231         { INTR_RXQ2_COAL | INTR_RXQ2_COAL_TO, INTR_RXQ2_COMP,
 232           INTR_RXQ2_DESC_EMPTY },
 233         { INTR_RXQ3_COAL | INTR_RXQ3_COAL_TO, INTR_RXQ3_COMP,
 234           INTR_RXQ3_DESC_EMPTY }
 235 };
 236
 237 static int      jme_rx_desc_count = JME_RX_DESC_CNT_DEF;
 238 static int      jme_tx_desc_count = JME_TX_DESC_CNT_DEF;
 239 static int      jme_rx_ring_count = 0;
 240 static int      jme_msi_enable = 1;
 241 static int      jme_msix_enable = 1;
 242
 243 TUNABLE_INT("hw.jme.rx_desc_count", &jme_rx_desc_count);
 244 TUNABLE_INT("hw.jme.tx_desc_count", &jme_tx_desc_count);
 245 TUNABLE_INT("hw.jme.rx_ring_count", &jme_rx_ring_count);
 246 TUNABLE_INT("hw.jme.msi.enable", &jme_msi_enable);
 247 TUNABLE_INT("hw.jme.msix.enable", &jme_msix_enable);
 248
 249 /*
 250  *      Read a PHY register on the MII of the JMC250.
 251  */
 252 static int
 253 jme_miibus_readreg(device_t dev, int phy, int reg)
 254 {
 255         struct jme_softc *sc = device_get_softc(dev);
 256         uint32_t val;
 257         int i;
 258
 259         /* For FPGA version, PHY address 0 should be ignored. */
 260         if (sc->jme_caps & JME_CAP_FPGA) {
 261                 if (phy == 0)
 262                         return (0);
 263         } else {
 264                 if (sc->jme_phyaddr != phy)
 265                         return (0);
 266         }
 267
 268         CSR_WRITE_4(sc, JME_SMI, SMI_OP_READ | SMI_OP_EXECUTE |
 269             SMI_PHY_ADDR(phy) | SMI_REG_ADDR(reg));
 270
 271         for (i = JME_PHY_TIMEOUT; i > 0; i--) {
 272                 DELAY(1);
 273                 if (((val = CSR_READ_4(sc, JME_SMI)) & SMI_OP_EXECUTE) == 0)
 274                         break;
 275         }
 276         if (i == 0) {
 277                 device_printf(sc->jme_dev, "phy read timeout: "
 278                               "phy %d, reg %d\n", phy, reg);
 279                 return (0);
 280         }
 281
 282         return ((val & SMI_DATA_MASK) >> SMI_DATA_SHIFT);
 283 }
 284
 285 /*
 286  *      Write a PHY register on the MII of the JMC250.
 287  */
 288 static int
 289 jme_miibus_writereg(device_t dev, int phy, int reg, int val)
 290 {
 291         struct jme_softc *sc = device_get_softc(dev);
 292         int i;
 293
 294         /* For FPGA version, PHY address 0 should be ignored. */
 295         if (sc->jme_caps & JME_CAP_FPGA) {
 296                 if (phy == 0)
 297                         return (0);
 298         } else {
 299                 if (sc->jme_phyaddr != phy)
 300                         return (0);
 301         }
 302
 303         CSR_WRITE_4(sc, JME_SMI, SMI_OP_WRITE | SMI_OP_EXECUTE |
 304             ((val << SMI_DATA_SHIFT) & SMI_DATA_MASK) |
 305             SMI_PHY_ADDR(phy) | SMI_REG_ADDR(reg));
 306
 307         for (i = JME_PHY_TIMEOUT; i > 0; i--) {
 308                 DELAY(1);
 309                 if (((val = CSR_READ_4(sc, JME_SMI)) & SMI_OP_EXECUTE) == 0)
 310                         break;
 311         }
 312         if (i == 0) {
 313                 device_printf(sc->jme_dev, "phy write timeout: "
 314                               "phy %d, reg %d\n", phy, reg);
 315         }
 316
 317         return (0);
 318 }
 319
 320 /*
 321  *      Callback from MII layer when media changes.
 322  */
 323 static void
 324 jme_miibus_statchg(device_t dev)
 325 {
 326         struct jme_softc *sc = device_get_softc(dev);
 327         struct ifnet *ifp = &sc->arpcom.ac_if;
 328         struct mii_data *mii;
 329         struct jme_txdesc *txd;
 330         bus_addr_t paddr;
 331         int i, r;
 332
 333         ASSERT_IFNET_SERIALIZED_ALL(ifp);
 334
 335         if ((ifp->if_flags & IFF_RUNNING) == 0)
 336                 return;
 337
 338         mii = device_get_softc(sc->jme_miibus);
 339
 340         sc->jme_flags &= ~JME_FLAG_LINK;
 341         if ((mii->mii_media_status & IFM_AVALID) != 0) {
 342                 switch (IFM_SUBTYPE(mii->mii_media_active)) {
 343                 case IFM_10_T:
 344                 case IFM_100_TX:
 345                         sc->jme_flags |= JME_FLAG_LINK;
 346                         break;
 347                 case IFM_1000_T:
 348                         if (sc->jme_caps & JME_CAP_FASTETH)
 349                                 break;
 350                         sc->jme_flags |= JME_FLAG_LINK;
 351                         break;
 352                 default:
 353                         break;
 354                 }
 355         }
 356
 357         /*
 358          * Disabling Rx/Tx MACs have a side-effect of resetting
 359          * JME_TXNDA/JME_RXNDA register to the first address of
 360          * Tx/Rx descriptor address. So driver should reset its
 361          * internal procucer/consumer pointer and reclaim any
 362          * allocated resources.  Note, just saving the value of
 363          * JME_TXNDA and JME_RXNDA registers before stopping MAC
 364          * and restoring JME_TXNDA/JME_RXNDA register is not
 365          * sufficient to make sure correct MAC state because
 366          * stopping MAC operation can take a while and hardware
 367          * might have updated JME_TXNDA/JME_RXNDA registers
 368          * during the stop operation.
 369          */
 370
 371         /* Disable interrupts */
 372         CSR_WRITE_4(sc, JME_INTR_MASK_CLR, JME_INTRS);
 373
 374         /* Stop driver */
 375         ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
 376         ifp->if_timer = 0;
 377         callout_stop(&sc->jme_tick_ch);
 378
 379         /* Stop receiver/transmitter. */
 380         jme_stop_rx(sc);
 381         jme_stop_tx(sc);
 382
 383         for (r = 0; r < sc->jme_rx_ring_inuse; ++r) {
 384                 struct jme_rxdata *rdata = &sc->jme_cdata.jme_rx_data[r];
 385
 386                 jme_rxeof(sc, r, -1);
 387                 if (rdata->jme_rxhead != NULL)
 388                         m_freem(rdata->jme_rxhead);
 389                 JME_RXCHAIN_RESET(sc, r);
 390
 391                 /*
 392                  * Reuse configured Rx descriptors and reset
 393                  * procuder/consumer index.
 394                  */
 395                 rdata->jme_rx_cons = 0;
 396         }
 397
 398         jme_txeof(sc);
 399         if (sc->jme_cdata.jme_tx_cnt != 0) {
 400                 /* Remove queued packets for transmit. */
 401                 for (i = 0; i < sc->jme_tx_desc_cnt; i++) {
 402                         txd = &sc->jme_cdata.jme_txdesc[i];
 403                         if (txd->tx_m != NULL) {
 404                                 bus_dmamap_unload(
 405                                     sc->jme_cdata.jme_tx_tag,
 406                                     txd->tx_dmamap);
 407                                 m_freem(txd->tx_m);
 408                                 txd->tx_m = NULL;
 409                                 txd->tx_ndesc = 0;
 410                                 ifp->if_oerrors++;
 411                         }
 412                 }
 413         }
 414         jme_init_tx_ring(sc);
 415
 416         /* Initialize shadow status block. */
 417         jme_init_ssb(sc);
 418
 419         /* Program MAC with resolved speed/duplex/flow-control. */
 420         if (sc->jme_flags & JME_FLAG_LINK) {
 421                 jme_mac_config(sc);
 422
 423                 CSR_WRITE_4(sc, JME_TXCSR, sc->jme_txcsr);
 424
 425                 /* Set Tx ring address to the hardware. */
 426                 paddr = sc->jme_cdata.jme_tx_ring_paddr;
 427                 CSR_WRITE_4(sc, JME_TXDBA_HI, JME_ADDR_HI(paddr));
 428                 CSR_WRITE_4(sc, JME_TXDBA_LO, JME_ADDR_LO(paddr));
 429
 430                 for (r = 0; r < sc->jme_rx_ring_inuse; ++r) {
 431                         CSR_WRITE_4(sc, JME_RXCSR,
 432                             sc->jme_rxcsr | RXCSR_RXQ_N_SEL(r));
 433
 434                         /* Set Rx ring address to the hardware. */
 435                         paddr = sc->jme_cdata.jme_rx_data[r].jme_rx_ring_paddr;
 436                         CSR_WRITE_4(sc, JME_RXDBA_HI, JME_ADDR_HI(paddr));
 437                         CSR_WRITE_4(sc, JME_RXDBA_LO, JME_ADDR_LO(paddr));
 438                 }
 439
 440                 /* Restart receiver/transmitter. */
 441                 CSR_WRITE_4(sc, JME_RXCSR, sc->jme_rxcsr | RXCSR_RX_ENB |
 442                     RXCSR_RXQ_START);
 443                 CSR_WRITE_4(sc, JME_TXCSR, sc->jme_txcsr | TXCSR_TX_ENB);
 444         }
 445
 446         ifp->if_flags |= IFF_RUNNING;
 447         ifp->if_flags &= ~IFF_OACTIVE;
 448         callout_reset(&sc->jme_tick_ch, hz, jme_tick, sc);
 449
 450 #ifdef DEVICE_POLLING
 451         if (!(ifp->if_flags & IFF_POLLING))
 452 #endif
 453         /* Reenable interrupts. */
 454         CSR_WRITE_4(sc, JME_INTR_MASK_SET, JME_INTRS);
 455 }
 456
 457 /*
 458  *      Get the current interface media status.
 459  */
 460 static void
 461 jme_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr)
 462 {
 463         struct jme_softc *sc = ifp->if_softc;
 464         struct mii_data *mii = device_get_softc(sc->jme_miibus);
 465
 466         ASSERT_IFNET_SERIALIZED_ALL(ifp);
 467
 468         mii_pollstat(mii);
 469         ifmr->ifm_status = mii->mii_media_status;
 470         ifmr->ifm_active = mii->mii_media_active;
 471 }
 472
 473 /*
 474  *      Set hardware to newly-selected media.
 475  */
 476 static int
 477 jme_mediachange(struct ifnet *ifp)
 478 {
 479         struct jme_softc *sc = ifp->if_softc;
 480         struct mii_data *mii = device_get_softc(sc->jme_miibus);
 481         int error;
 482
 483         ASSERT_IFNET_SERIALIZED_ALL(ifp);
 484
 485         if (mii->mii_instance != 0) {
 486                 struct mii_softc *miisc;
 487
 488                 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
 489                         mii_phy_reset(miisc);
 490         }
 491         error = mii_mediachg(mii);
 492
 493         return (error);
 494 }
 495
 496 static int
 497 jme_probe(device_t dev)
 498 {
 499         const struct jme_dev *sp;
 500         uint16_t vid, did;
 501
 502         vid = pci_get_vendor(dev);
 503         did = pci_get_device(dev);
 504         for (sp = jme_devs; sp->jme_name != NULL; ++sp) {
 505                 if (vid == sp->jme_vendorid && did == sp->jme_deviceid) {
 506                         struct jme_softc *sc = device_get_softc(dev);
 507
 508                         sc->jme_caps = sp->jme_caps;
 509                         device_set_desc(dev, sp->jme_name);
 510                         return (0);
 511                 }
 512         }
 513         return (ENXIO);
 514 }
 515
 516 static int
 517 jme_eeprom_read_byte(struct jme_softc *sc, uint8_t addr, uint8_t *val)
 518 {
 519         uint32_t reg;
 520         int i;
 521
 522         *val = 0;
 523         for (i = JME_TIMEOUT; i > 0; i--) {
 524                 reg = CSR_READ_4(sc, JME_SMBCSR);
 525                 if ((reg & SMBCSR_HW_BUSY_MASK) == SMBCSR_HW_IDLE)
 526                         break;
 527                 DELAY(1);
 528         }
 529
 530         if (i == 0) {
 531                 device_printf(sc->jme_dev, "EEPROM idle timeout!\n");
 532                 return (ETIMEDOUT);
 533         }
 534
 535         reg = ((uint32_t)addr << SMBINTF_ADDR_SHIFT) & SMBINTF_ADDR_MASK;
 536         CSR_WRITE_4(sc, JME_SMBINTF, reg | SMBINTF_RD | SMBINTF_CMD_TRIGGER);
 537         for (i = JME_TIMEOUT; i > 0; i--) {
 538                 DELAY(1);
 539                 reg = CSR_READ_4(sc, JME_SMBINTF);
 540                 if ((reg & SMBINTF_CMD_TRIGGER) == 0)
 541                         break;
 542         }
 543
 544         if (i == 0) {
 545                 device_printf(sc->jme_dev, "EEPROM read timeout!\n");
 546                 return (ETIMEDOUT);
 547         }
 548
 549         reg = CSR_READ_4(sc, JME_SMBINTF);
 550         *val = (reg & SMBINTF_RD_DATA_MASK) >> SMBINTF_RD_DATA_SHIFT;
 551
 552         return (0);
 553 }
 554
 555 static int
 556 jme_eeprom_macaddr(struct jme_softc *sc, uint8_t eaddr[])
 557 {
 558         uint8_t fup, reg, val;
 559         uint32_t offset;
 560         int match;
 561
 562         offset = 0;
 563         if (jme_eeprom_read_byte(sc, offset++, &fup) != 0 ||
 564             fup != JME_EEPROM_SIG0)
 565                 return (ENOENT);
 566         if (jme_eeprom_read_byte(sc, offset++, &fup) != 0 ||
 567             fup != JME_EEPROM_SIG1)
 568                 return (ENOENT);
 569         match = 0;
 570         do {
 571                 if (jme_eeprom_read_byte(sc, offset, &fup) != 0)
 572                         break;
 573                 if (JME_EEPROM_MKDESC(JME_EEPROM_FUNC0, JME_EEPROM_PAGE_BAR1) ==
 574                     (fup & (JME_EEPROM_FUNC_MASK | JME_EEPROM_PAGE_MASK))) {
 575                         if (jme_eeprom_read_byte(sc, offset + 1, &reg) != 0)
 576                                 break;
 577                         if (reg >= JME_PAR0 &&
 578                             reg < JME_PAR0 + ETHER_ADDR_LEN) {
 579                                 if (jme_eeprom_read_byte(sc, offset + 2,
 580                                     &val) != 0)
 581                                         break;
 582                                 eaddr[reg - JME_PAR0] = val;
 583                                 match++;
 584                         }
 585                 }
 586                 /* Check for the end of EEPROM descriptor. */
 587                 if ((fup & JME_EEPROM_DESC_END) == JME_EEPROM_DESC_END)
 588                         break;
 589                 /* Try next eeprom descriptor. */
 590                 offset += JME_EEPROM_DESC_BYTES;
 591         } while (match != ETHER_ADDR_LEN && offset < JME_EEPROM_END);
 592
 593         if (match == ETHER_ADDR_LEN)
 594                 return (0);
 595
 596         return (ENOENT);
 597 }
 598
 599 static void
 600 jme_reg_macaddr(struct jme_softc *sc, uint8_t eaddr[])
 601 {
 602         uint32_t par0, par1;
 603
 604         /* Read station address. */
 605         par0 = CSR_READ_4(sc, JME_PAR0);
 606         par1 = CSR_READ_4(sc, JME_PAR1);
 607         par1 &= 0xFFFF;
 608         if ((par0 == 0 && par1 == 0) || (par0 & 0x1)) {
 609                 device_printf(sc->jme_dev,
 610                     "generating fake ethernet address.\n");
 611                 par0 = karc4random();
 612                 /* Set OUI to JMicron. */
 613                 eaddr[0] = 0x00;
 614                 eaddr[1] = 0x1B;
 615                 eaddr[2] = 0x8C;
 616                 eaddr[3] = (par0 >> 16) & 0xff;
 617                 eaddr[4] = (par0 >> 8) & 0xff;
 618                 eaddr[5] = par0 & 0xff;
 619         } else {
 620                 eaddr[0] = (par0 >> 0) & 0xFF;
 621                 eaddr[1] = (par0 >> 8) & 0xFF;
 622                 eaddr[2] = (par0 >> 16) & 0xFF;
 623                 eaddr[3] = (par0 >> 24) & 0xFF;
 624                 eaddr[4] = (par1 >> 0) & 0xFF;
 625                 eaddr[5] = (par1 >> 8) & 0xFF;
 626         }
 627 }
 628
 629 static int
 630 jme_attach(device_t dev)
 631 {
 632         struct jme_softc *sc = device_get_softc(dev);
 633         struct ifnet *ifp = &sc->arpcom.ac_if;
 634         uint32_t reg;
 635         uint16_t did;
 636         uint8_t pcie_ptr, rev;
 637         int error = 0, i, j;
 638         uint8_t eaddr[ETHER_ADDR_LEN];
 639
 640         lwkt_serialize_init(&sc->jme_serialize);
 641         lwkt_serialize_init(&sc->jme_cdata.jme_tx_serialize);
 642         for (i = 0; i < JME_NRXRING_MAX; ++i) {
 643                 lwkt_serialize_init(
 644                     &sc->jme_cdata.jme_rx_data[i].jme_rx_serialize);
 645         }
 646
 647         sc->jme_rx_desc_cnt = device_getenv_int(dev, "rx_desc_count",
 648             jme_rx_desc_count);
 649         sc->jme_rx_desc_cnt = roundup(sc->jme_rx_desc_cnt, JME_NDESC_ALIGN);
 650         if (sc->jme_rx_desc_cnt > JME_NDESC_MAX)
 651                 sc->jme_rx_desc_cnt = JME_NDESC_MAX;
 652
 653         sc->jme_tx_desc_cnt = device_getenv_int(dev, "tx_desc_count",
 654             jme_tx_desc_count);
 655         sc->jme_tx_desc_cnt = roundup(sc->jme_tx_desc_cnt, JME_NDESC_ALIGN);
 656         if (sc->jme_tx_desc_cnt > JME_NDESC_MAX)
 657                 sc->jme_tx_desc_cnt = JME_NDESC_MAX;
 658
 659         /*
 660          * Calculate rx rings
 661          */
 662         sc->jme_rx_ring_cnt = device_getenv_int(dev, "rx_ring_count",
 663             jme_rx_ring_count);
 664         sc->jme_rx_ring_cnt = if_ring_count2(sc->jme_rx_ring_cnt,
 665             JME_NRXRING_MAX);
 666         sc->jme_rx_ring_inuse = sc->jme_rx_ring_cnt;
 667
 668         i = 0;
 669         sc->jme_serialize_arr[i++] = &sc->jme_serialize;
 670         sc->jme_serialize_arr[i++] = &sc->jme_cdata.jme_tx_serialize;
 671         for (j = 0; j < sc->jme_rx_ring_cnt; ++j) {
 672                 sc->jme_serialize_arr[i++] =
 673                     &sc->jme_cdata.jme_rx_data[j].jme_rx_serialize;
 674         }
 675         KKASSERT(i <= JME_NSERIALIZE);
 676         sc->jme_serialize_cnt = i;
 677
 678         sc->jme_cdata.jme_sc = sc;
 679         for (i = 0; i < sc->jme_rx_ring_cnt; ++i) {
 680                 struct jme_rxdata *rdata = &sc->jme_cdata.jme_rx_data[i];
 681
 682                 rdata->jme_sc = sc;
 683                 rdata->jme_rx_coal = jme_rx_status[i].jme_coal;
 684                 rdata->jme_rx_comp = jme_rx_status[i].jme_comp;
 685                 rdata->jme_rx_empty = jme_rx_status[i].jme_empty;
 686                 rdata->jme_rx_idx = i;
 687         }
 688
 689         sc->jme_dev = dev;
 690         sc->jme_lowaddr = BUS_SPACE_MAXADDR;
 691
 692         if_initname(ifp, device_get_name(dev), device_get_unit(dev));
 693
 694         callout_init(&sc->jme_tick_ch);
 695
 696 #ifndef BURN_BRIDGES
 697         if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
 698                 uint32_t irq, mem;
 699
 700                 irq = pci_read_config(dev, PCIR_INTLINE, 4);
 701                 mem = pci_read_config(dev, JME_PCIR_BAR, 4);
 702
 703                 device_printf(dev, "chip is in D%d power mode "
 704                     "-- setting to D0\n", pci_get_powerstate(dev));
 705
 706                 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
 707
 708                 pci_write_config(dev, PCIR_INTLINE, irq, 4);
 709                 pci_write_config(dev, JME_PCIR_BAR, mem, 4);
 710         }
 711 #endif  /* !BURN_BRIDGE */
 712
 713         /* Enable bus mastering */
 714         pci_enable_busmaster(dev);
 715
 716         /*
 717          * Allocate IO memory
 718          *
 719          * JMC250 supports both memory mapped and I/O register space
 720          * access.  Because I/O register access should use different
 721          * BARs to access registers it's waste of time to use I/O
 722          * register spce access.  JMC250 uses 16K to map entire memory
 723          * space.
 724          */
 725         sc->jme_mem_rid = JME_PCIR_BAR;
 726         sc->jme_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
 727                                                  &sc->jme_mem_rid, RF_ACTIVE);
 728         if (sc->jme_mem_res == NULL) {
 729                 device_printf(dev, "can't allocate IO memory\n");
 730                 return ENXIO;
 731         }
 732         sc->jme_mem_bt = rman_get_bustag(sc->jme_mem_res);
 733         sc->jme_mem_bh = rman_get_bushandle(sc->jme_mem_res);
 734
 735         /*
 736          * Allocate IRQ
 737          */
 738         error = jme_intr_alloc(dev);
 739         if (error)
 740                 goto fail;
 741
 742         /*
 743          * Extract revisions
 744          */
 745         reg = CSR_READ_4(sc, JME_CHIPMODE);
 746         if (((reg & CHIPMODE_FPGA_REV_MASK) >> CHIPMODE_FPGA_REV_SHIFT) !=
 747             CHIPMODE_NOT_FPGA) {
 748                 sc->jme_caps |= JME_CAP_FPGA;
 749                 if (bootverbose) {
 750                         device_printf(dev, "FPGA revision: 0x%04x\n",
 751                                       (reg & CHIPMODE_FPGA_REV_MASK) >>
 752                                       CHIPMODE_FPGA_REV_SHIFT);
 753                 }
 754         }
 755
 756         /* NOTE: FM revision is put in the upper 4 bits */
 757         rev = ((reg & CHIPMODE_REVFM_MASK) >> CHIPMODE_REVFM_SHIFT) << 4;
 758         rev |= (reg & CHIPMODE_REVECO_MASK) >> CHIPMODE_REVECO_SHIFT;
 759         if (bootverbose)
 760                 device_printf(dev, "Revision (FM/ECO): 0x%02x\n", rev);
 761
 762         did = pci_get_device(dev);
 763         switch (did) {
 764         case PCI_PRODUCT_JMICRON_JMC250:
 765                 if (rev == JME_REV1_A2)
 766                         sc->jme_workaround |= JME_WA_EXTFIFO | JME_WA_HDX;
 767                 break;
 768
 769         case PCI_PRODUCT_JMICRON_JMC260:
 770                 if (rev == JME_REV2)
 771                         sc->jme_lowaddr = BUS_SPACE_MAXADDR_32BIT;
 772                 break;
 773
 774         default:
 775                 panic("unknown device id 0x%04x\n", did);
 776         }
 777         if (rev >= JME_REV2) {
 778                 sc->jme_clksrc = GHC_TXOFL_CLKSRC | GHC_TXMAC_CLKSRC;
 779                 sc->jme_clksrc_1000 = GHC_TXOFL_CLKSRC_1000 |
 780                                       GHC_TXMAC_CLKSRC_1000;
 781         }
 782
 783         /* Reset the ethernet controller. */
 784         jme_reset(sc);
 785
 786         /* Map MSI/MSI-X vectors */
 787         jme_set_msinum(sc);
 788
 789         /* Get station address. */
 790         reg = CSR_READ_4(sc, JME_SMBCSR);
 791         if (reg & SMBCSR_EEPROM_PRESENT)
 792                 error = jme_eeprom_macaddr(sc, eaddr);
 793         if (error != 0 || (reg & SMBCSR_EEPROM_PRESENT) == 0) {
 794                 if (error != 0 && (bootverbose)) {
 795                         device_printf(dev, "ethernet hardware address "
 796                                       "not found in EEPROM.\n");
 797                 }
 798                 jme_reg_macaddr(sc, eaddr);
 799         }
 800
 801         /*
 802          * Save PHY address.
 803          * Integrated JR0211 has fixed PHY address whereas FPGA version
 804          * requires PHY probing to get correct PHY address.
 805          */
 806         if ((sc->jme_caps & JME_CAP_FPGA) == 0) {
 807                 sc->jme_phyaddr = CSR_READ_4(sc, JME_GPREG0) &
 808                     GPREG0_PHY_ADDR_MASK;
 809                 if (bootverbose) {
 810                         device_printf(dev, "PHY is at address %d.\n",
 811                             sc->jme_phyaddr);
 812                 }
 813         } else {
 814                 sc->jme_phyaddr = 0;
 815         }
 816
 817         /* Set max allowable DMA size. */
 818         pcie_ptr = pci_get_pciecap_ptr(dev);
 819         if (pcie_ptr != 0) {
 820                 uint16_t ctrl;
 821
 822                 sc->jme_caps |= JME_CAP_PCIE;
 823                 ctrl = pci_read_config(dev, pcie_ptr + PCIER_DEVCTRL, 2);
 824                 if (bootverbose) {
 825                         device_printf(dev, "Read request size : %d bytes.\n",
 826                             128 << ((ctrl >> 12) & 0x07));
 827                         device_printf(dev, "TLP payload size : %d bytes.\n",
 828                             128 << ((ctrl >> 5) & 0x07));
 829                 }
 830                 switch (ctrl & PCIEM_DEVCTL_MAX_READRQ_MASK) {
 831                 case PCIEM_DEVCTL_MAX_READRQ_128:
 832                         sc->jme_tx_dma_size = TXCSR_DMA_SIZE_128;
 833                         break;
 834                 case PCIEM_DEVCTL_MAX_READRQ_256:
 835                         sc->jme_tx_dma_size = TXCSR_DMA_SIZE_256;
 836                         break;
 837                 default:
 838                         sc->jme_tx_dma_size = TXCSR_DMA_SIZE_512;
 839                         break;
 840                 }
 841                 sc->jme_rx_dma_size = RXCSR_DMA_SIZE_128;
 842         } else {
 843                 sc->jme_tx_dma_size = TXCSR_DMA_SIZE_512;
 844                 sc->jme_rx_dma_size = RXCSR_DMA_SIZE_128;
 845         }
 846
 847 #ifdef notyet
 848         if (pci_find_extcap(dev, PCIY_PMG, &pmc) == 0)
 849                 sc->jme_caps |= JME_CAP_PMCAP;
 850 #endif
 851
 852         /*
 853          * Create sysctl tree
 854          */
 855         jme_sysctl_node(sc);
 856
 857         /* Allocate DMA stuffs */
 858         error = jme_dma_alloc(sc);
 859         if (error)
 860                 goto fail;
 861
 862         ifp->if_softc = sc;
 863         ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
 864         ifp->if_init = jme_init;
 865         ifp->if_ioctl = jme_ioctl;
 866         ifp->if_start = jme_start;
 867 #ifdef DEVICE_POLLING
 868         ifp->if_poll = jme_poll;
 869 #endif
 870         ifp->if_watchdog = jme_watchdog;
 871         ifp->if_serialize = jme_serialize;
 872         ifp->if_deserialize = jme_deserialize;
 873         ifp->if_tryserialize = jme_tryserialize;
 874 #ifdef INVARIANTS
 875         ifp->if_serialize_assert = jme_serialize_assert;
 876 #endif
 877         ifq_set_maxlen(&ifp->if_snd, sc->jme_tx_desc_cnt - JME_TXD_RSVD);
 878         ifq_set_ready(&ifp->if_snd);
 879
 880         /* JMC250 supports Tx/Rx checksum offload and hardware vlan tagging. */
 881         ifp->if_capabilities = IFCAP_HWCSUM |
 882                                IFCAP_VLAN_MTU |
 883                                IFCAP_VLAN_HWTAGGING;
 884         if (sc->jme_rx_ring_cnt > JME_NRXRING_MIN)
 885                 ifp->if_capabilities |= IFCAP_RSS;
 886         ifp->if_capenable = ifp->if_capabilities;
 887
 888         /*
 889          * Disable TXCSUM by default to improve bulk data
 890          * transmit performance (+20Mbps improvement).
 891          */
 892         ifp->if_capenable &= ~IFCAP_TXCSUM;
 893
 894         if (ifp->if_capenable & IFCAP_TXCSUM)
 895                 ifp->if_hwassist = JME_CSUM_FEATURES;
 896
 897         /* Set up MII bus. */
 898         error = mii_phy_probe(dev, &sc->jme_miibus,
 899                               jme_mediachange, jme_mediastatus);
 900         if (error) {
 901                 device_printf(dev, "no PHY found!\n");
 902                 goto fail;
 903         }
 904
 905         /*
 906          * Save PHYADDR for FPGA mode PHY.
 907          */
 908         if (sc->jme_caps & JME_CAP_FPGA) {
 909                 struct mii_data *mii = device_get_softc(sc->jme_miibus);
 910
 911                 if (mii->mii_instance != 0) {
 912                         struct mii_softc *miisc;
 913
 914                         LIST_FOREACH(miisc, &mii->mii_phys, mii_list) {
 915                                 if (miisc->mii_phy != 0) {
 916                                         sc->jme_phyaddr = miisc->mii_phy;
 917                                         break;
 918                                 }
 919                         }
 920                         if (sc->jme_phyaddr != 0) {
 921                                 device_printf(sc->jme_dev,
 922                                     "FPGA PHY is at %d\n", sc->jme_phyaddr);
 923                                 /* vendor magic. */
 924                                 jme_miibus_writereg(dev, sc->jme_phyaddr,
 925                                     JMPHY_CONF, JMPHY_CONF_DEFFIFO);
 926
 927                                 /* XXX should we clear JME_WA_EXTFIFO */
 928                         }
 929                 }
 930         }
 931
 932         ether_ifattach(ifp, eaddr, NULL);
 933
 934         /* Tell the upper layer(s) we support long frames. */
 935         ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
 936
 937         error = jme_intr_setup(dev);
 938         if (error) {
 939                 ether_ifdetach(ifp);
 940                 goto fail;
 941         }
 942
 943         return 0;
 944 fail:
 945         jme_detach(dev);
 946         return (error);
 947 }
 948
 949 static int
 950 jme_detach(device_t dev)
 951 {
 952         struct jme_softc *sc = device_get_softc(dev);
 953
 954         if (device_is_attached(dev)) {
 955                 struct ifnet *ifp = &sc->arpcom.ac_if;
 956
 957                 ifnet_serialize_all(ifp);
 958                 jme_stop(sc);
 959                 jme_intr_teardown(dev);
 960                 ifnet_deserialize_all(ifp);
 961
 962                 ether_ifdetach(ifp);
 963         }
 964
 965         if (sc->jme_sysctl_tree != NULL)
 966                 sysctl_ctx_free(&sc->jme_sysctl_ctx);
 967
 968         if (sc->jme_miibus != NULL)
 969                 device_delete_child(dev, sc->jme_miibus);
 970         bus_generic_detach(dev);
 971
 972         jme_intr_free(dev);
 973
 974         if (sc->jme_mem_res != NULL) {
 975                 bus_release_resource(dev, SYS_RES_MEMORY, sc->jme_mem_rid,
 976                                      sc->jme_mem_res);
 977         }
 978
 979         jme_dma_free(sc);
 980
 981         return (0);
 982 }
 983
 984 static void
 985 jme_sysctl_node(struct jme_softc *sc)
 986 {
 987         int coal_max;
 988 #ifdef JME_RSS_DEBUG
 989         char rx_ring_pkt[32];
 990         int r;
 991 #endif
 992
 993         sysctl_ctx_init(&sc->jme_sysctl_ctx);
 994         sc->jme_sysctl_tree = SYSCTL_ADD_NODE(&sc->jme_sysctl_ctx,
 995                                 SYSCTL_STATIC_CHILDREN(_hw), OID_AUTO,
 996                                 device_get_nameunit(sc->jme_dev),
 997                                 CTLFLAG_RD, 0, "");
 998         if (sc->jme_sysctl_tree == NULL) {
 999                 device_printf(sc->jme_dev, "can't add sysctl node\n");
1000                 return;
1001         }
1002
1003         SYSCTL_ADD_PROC(&sc->jme_sysctl_ctx,
1004             SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO,
1005             "tx_coal_to", CTLTYPE_INT | CTLFLAG_RW,
1006             sc, 0, jme_sysctl_tx_coal_to, "I", "jme tx coalescing timeout");
1007
1008         SYSCTL_ADD_PROC(&sc->jme_sysctl_ctx,
1009             SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO,
1010             "tx_coal_pkt", CTLTYPE_INT | CTLFLAG_RW,
1011             sc, 0, jme_sysctl_tx_coal_pkt, "I", "jme tx coalescing packet");
1012
1013         SYSCTL_ADD_PROC(&sc->jme_sysctl_ctx,
1014             SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO,
1015             "rx_coal_to", CTLTYPE_INT | CTLFLAG_RW,
1016             sc, 0, jme_sysctl_rx_coal_to, "I", "jme rx coalescing timeout");
1017
1018         SYSCTL_ADD_PROC(&sc->jme_sysctl_ctx,
1019             SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO,
1020             "rx_coal_pkt", CTLTYPE_INT | CTLFLAG_RW,
1021             sc, 0, jme_sysctl_rx_coal_pkt, "I", "jme rx coalescing packet");
1022
1023         SYSCTL_ADD_INT(&sc->jme_sysctl_ctx,
1024                        SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO,
1025                        "rx_desc_count", CTLFLAG_RD, &sc->jme_rx_desc_cnt,
1026                        0, "RX desc count");
1027         SYSCTL_ADD_INT(&sc->jme_sysctl_ctx,
1028                        SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO,
1029                        "tx_desc_count", CTLFLAG_RD, &sc->jme_tx_desc_cnt,
1030                        0, "TX desc count");
1031         SYSCTL_ADD_INT(&sc->jme_sysctl_ctx,
1032                        SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO,
1033                        "rx_ring_count", CTLFLAG_RD, &sc->jme_rx_ring_cnt,
1034                        0, "RX ring count");
1035         SYSCTL_ADD_INT(&sc->jme_sysctl_ctx,
1036                        SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO,
1037                        "rx_ring_inuse", CTLFLAG_RD, &sc->jme_rx_ring_inuse,
1038                        0, "RX ring in use");
1039 #ifdef JME_RSS_DEBUG
1040         SYSCTL_ADD_INT(&sc->jme_sysctl_ctx,
1041                        SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO,
1042                        "rss_debug", CTLFLAG_RW, &sc->jme_rss_debug,
1043                        0, "RSS debug level");
1044         for (r = 0; r < sc->jme_rx_ring_cnt; ++r) {
1045                 ksnprintf(rx_ring_pkt, sizeof(rx_ring_pkt), "rx_ring%d_pkt", r);
1046                 SYSCTL_ADD_UINT(&sc->jme_sysctl_ctx,
1047                                 SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO,
1048                                 rx_ring_pkt, CTLFLAG_RW,
1049                                 &sc->jme_rx_ring_pkt[r],
1050                                 0, "RXed packets");
1051         }
1052 #endif
1053
1054         /*
1055          * Set default coalesce valves
1056          */
1057         sc->jme_tx_coal_to = PCCTX_COAL_TO_DEFAULT;
1058         sc->jme_tx_coal_pkt = PCCTX_COAL_PKT_DEFAULT;
1059         sc->jme_rx_coal_to = PCCRX_COAL_TO_DEFAULT;
1060         sc->jme_rx_coal_pkt = PCCRX_COAL_PKT_DEFAULT;
1061
1062         /*
1063          * Adjust coalesce valves, in case that the number of TX/RX
1064          * descs are set to small values by users.
1065          *
1066          * NOTE: coal_max will not be zero, since number of descs
1067          * must aligned by JME_NDESC_ALIGN (16 currently)
1068          */
1069         coal_max = sc->jme_tx_desc_cnt / 6;
1070         if (coal_max < sc->jme_tx_coal_pkt)
1071                 sc->jme_tx_coal_pkt = coal_max;
1072
1073         coal_max = sc->jme_rx_desc_cnt / 4;
1074         if (coal_max < sc->jme_rx_coal_pkt)
1075                 sc->jme_rx_coal_pkt = coal_max;
1076 }
1077
1078 static int
1079 jme_dma_alloc(struct jme_softc *sc)
1080 {
1081         struct jme_txdesc *txd;
1082         bus_dmamem_t dmem;
1083         int error, i;
1084
1085         sc->jme_cdata.jme_txdesc =
1086         kmalloc(sc->jme_tx_desc_cnt * sizeof(struct jme_txdesc),
1087                 M_DEVBUF, M_WAITOK | M_ZERO);
1088         for (i = 0; i < sc->jme_rx_ring_cnt; ++i) {
1089                 sc->jme_cdata.jme_rx_data[i].jme_rxdesc =
1090                 kmalloc(sc->jme_rx_desc_cnt * sizeof(struct jme_rxdesc),
1091                         M_DEVBUF, M_WAITOK | M_ZERO);
1092         }
1093
1094         /* Create parent ring tag. */
1095         error = bus_dma_tag_create(NULL,/* parent */
1096             1, JME_RING_BOUNDARY,       /* algnmnt, boundary */
1097             sc->jme_lowaddr,            /* lowaddr */
1098             BUS_SPACE_MAXADDR,          /* highaddr */
1099             NULL, NULL,                 /* filter, filterarg */
1100             BUS_SPACE_MAXSIZE_32BIT,    /* maxsize */
1101             0,                          /* nsegments */
1102             BUS_SPACE_MAXSIZE_32BIT,    /* maxsegsize */
1103             0,                          /* flags */
1104             &sc->jme_cdata.jme_ring_tag);
1105         if (error) {
1106                 device_printf(sc->jme_dev,
1107                     "could not create parent ring DMA tag.\n");
1108                 return error;
1109         }
1110
1111         /*
1112          * Create DMA stuffs for TX ring
1113          */
1114         error = bus_dmamem_coherent(sc->jme_cdata.jme_ring_tag,
1115                         JME_TX_RING_ALIGN, 0,
1116                         BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
1117                         JME_TX_RING_SIZE(sc),
1118                         BUS_DMA_WAITOK | BUS_DMA_ZERO, &dmem);
1119         if (error) {
1120                 device_printf(sc->jme_dev, "could not allocate Tx ring.\n");
1121                 return error;
1122         }
1123         sc->jme_cdata.jme_tx_ring_tag = dmem.dmem_tag;
1124         sc->jme_cdata.jme_tx_ring_map = dmem.dmem_map;
1125         sc->jme_cdata.jme_tx_ring = dmem.dmem_addr;
1126         sc->jme_cdata.jme_tx_ring_paddr = dmem.dmem_busaddr;
1127
1128         /*
1129          * Create DMA stuffs for RX rings
1130          */
1131         for (i = 0; i < sc->jme_rx_ring_cnt; ++i) {
1132                 error = jme_rxring_dma_alloc(sc, i);
1133                 if (error)
1134                         return error;
1135         }
1136
1137         /* Create parent buffer tag. */
1138         error = bus_dma_tag_create(NULL,/* parent */
1139             1, 0,                       /* algnmnt, boundary */
1140             sc->jme_lowaddr,            /* lowaddr */
1141             BUS_SPACE_MAXADDR,          /* highaddr */
1142             NULL, NULL,                 /* filter, filterarg */
1143             BUS_SPACE_MAXSIZE_32BIT,    /* maxsize */
1144             0,                          /* nsegments */
1145             BUS_SPACE_MAXSIZE_32BIT,    /* maxsegsize */
1146             0,                          /* flags */
1147             &sc->jme_cdata.jme_buffer_tag);
1148         if (error) {
1149                 device_printf(sc->jme_dev,
1150                     "could not create parent buffer DMA tag.\n");
1151                 return error;
1152         }
1153
1154         /*
1155          * Create DMA stuffs for shadow status block
1156          */
1157         error = bus_dmamem_coherent(sc->jme_cdata.jme_buffer_tag,
1158                         JME_SSB_ALIGN, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
1159                         JME_SSB_SIZE, BUS_DMA_WAITOK | BUS_DMA_ZERO, &dmem);
1160         if (error) {
1161                 device_printf(sc->jme_dev,
1162                     "could not create shadow status block.\n");
1163                 return error;
1164         }
1165         sc->jme_cdata.jme_ssb_tag = dmem.dmem_tag;
1166         sc->jme_cdata.jme_ssb_map = dmem.dmem_map;
1167         sc->jme_cdata.jme_ssb_block = dmem.dmem_addr;
1168         sc->jme_cdata.jme_ssb_block_paddr = dmem.dmem_busaddr;
1169
1170         /*
1171          * Create DMA stuffs for TX buffers
1172          */
1173
1174         /* Create tag for Tx buffers. */
1175         error = bus_dma_tag_create(sc->jme_cdata.jme_buffer_tag,/* parent */
1176             1, 0,                       /* algnmnt, boundary */
1177             BUS_SPACE_MAXADDR,          /* lowaddr */
1178             BUS_SPACE_MAXADDR,          /* highaddr */
1179             NULL, NULL,                 /* filter, filterarg */
1180             JME_JUMBO_FRAMELEN,         /* maxsize */
1181             JME_MAXTXSEGS,              /* nsegments */
1182             JME_MAXSEGSIZE,             /* maxsegsize */
1183             BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE,/* flags */
1184             &sc->jme_cdata.jme_tx_tag);
1185         if (error != 0) {
1186                 device_printf(sc->jme_dev, "could not create Tx DMA tag.\n");
1187                 return error;
1188         }
1189
1190         /* Create DMA maps for Tx buffers. */
1191         for (i = 0; i < sc->jme_tx_desc_cnt; i++) {
1192                 txd = &sc->jme_cdata.jme_txdesc[i];
1193                 error = bus_dmamap_create(sc->jme_cdata.jme_tx_tag,
1194                                 BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE,
1195                                 &txd->tx_dmamap);
1196                 if (error) {
1197                         int j;
1198
1199                         device_printf(sc->jme_dev,
1200                             "could not create %dth Tx dmamap.\n", i);
1201
1202                         for (j = 0; j < i; ++j) {
1203                                 txd = &sc->jme_cdata.jme_txdesc[j];
1204                                 bus_dmamap_destroy(sc->jme_cdata.jme_tx_tag,
1205                                                    txd->tx_dmamap);
1206                         }
1207                         bus_dma_tag_destroy(sc->jme_cdata.jme_tx_tag);
1208                         sc->jme_cdata.jme_tx_tag = NULL;
1209                         return error;
1210                 }
1211         }
1212
1213         /*
1214          * Create DMA stuffs for RX buffers
1215          */
1216         for (i = 0; i < sc->jme_rx_ring_cnt; ++i) {
1217                 error = jme_rxbuf_dma_alloc(sc, i);
1218                 if (error)
1219                         return error;
1220         }
1221         return 0;
1222 }
1223
1224 static void
1225 jme_dma_free(struct jme_softc *sc)
1226 {
1227         struct jme_txdesc *txd;
1228         struct jme_rxdesc *rxd;
1229         struct jme_rxdata *rdata;
1230         int i, r;
1231
1232         /* Tx ring */
1233         if (sc->jme_cdata.jme_tx_ring_tag != NULL) {
1234                 bus_dmamap_unload(sc->jme_cdata.jme_tx_ring_tag,
1235                     sc->jme_cdata.jme_tx_ring_map);
1236                 bus_dmamem_free(sc->jme_cdata.jme_tx_ring_tag,
1237                     sc->jme_cdata.jme_tx_ring,
1238                     sc->jme_cdata.jme_tx_ring_map);
1239                 bus_dma_tag_destroy(sc->jme_cdata.jme_tx_ring_tag);
1240                 sc->jme_cdata.jme_tx_ring_tag = NULL;
1241         }
1242
1243         /* Rx ring */
1244         for (r = 0; r < sc->jme_rx_ring_cnt; ++r) {
1245                 rdata = &sc->jme_cdata.jme_rx_data[r];
1246                 if (rdata->jme_rx_ring_tag != NULL) {
1247                         bus_dmamap_unload(rdata->jme_rx_ring_tag,
1248                                           rdata->jme_rx_ring_map);
1249                         bus_dmamem_free(rdata->jme_rx_ring_tag,
1250                                         rdata->jme_rx_ring,
1251                                         rdata->jme_rx_ring_map);
1252                         bus_dma_tag_destroy(rdata->jme_rx_ring_tag);
1253                         rdata->jme_rx_ring_tag = NULL;
1254                 }
1255         }
1256
1257         /* Tx buffers */
1258         if (sc->jme_cdata.jme_tx_tag != NULL) {
1259                 for (i = 0; i < sc->jme_tx_desc_cnt; i++) {
1260                         txd = &sc->jme_cdata.jme_txdesc[i];
1261                         bus_dmamap_destroy(sc->jme_cdata.jme_tx_tag,
1262                             txd->tx_dmamap);
1263                 }
1264                 bus_dma_tag_destroy(sc->jme_cdata.jme_tx_tag);
1265                 sc->jme_cdata.jme_tx_tag = NULL;
1266         }
1267
1268         /* Rx buffers */
1269         for (r = 0; r < sc->jme_rx_ring_cnt; ++r) {
1270                 rdata = &sc->jme_cdata.jme_rx_data[r];
1271                 if (rdata->jme_rx_tag != NULL) {
1272                         for (i = 0; i < sc->jme_rx_desc_cnt; i++) {
1273                                 rxd = &rdata->jme_rxdesc[i];
1274                                 bus_dmamap_destroy(rdata->jme_rx_tag,
1275                                                    rxd->rx_dmamap);
1276                         }
1277                         bus_dmamap_destroy(rdata->jme_rx_tag,
1278                                            rdata->jme_rx_sparemap);
1279                         bus_dma_tag_destroy(rdata->jme_rx_tag);
1280                         rdata->jme_rx_tag = NULL;
1281                 }
1282         }
1283
1284         /* Shadow status block. */
1285         if (sc->jme_cdata.jme_ssb_tag != NULL) {
1286                 bus_dmamap_unload(sc->jme_cdata.jme_ssb_tag,
1287                     sc->jme_cdata.jme_ssb_map);
1288                 bus_dmamem_free(sc->jme_cdata.jme_ssb_tag,
1289                     sc->jme_cdata.jme_ssb_block,
1290                     sc->jme_cdata.jme_ssb_map);
1291                 bus_dma_tag_destroy(sc->jme_cdata.jme_ssb_tag);
1292                 sc->jme_cdata.jme_ssb_tag = NULL;
1293         }
1294
1295         if (sc->jme_cdata.jme_buffer_tag != NULL) {
1296                 bus_dma_tag_destroy(sc->jme_cdata.jme_buffer_tag);
1297                 sc->jme_cdata.jme_buffer_tag = NULL;
1298         }
1299         if (sc->jme_cdata.jme_ring_tag != NULL) {
1300                 bus_dma_tag_destroy(sc->jme_cdata.jme_ring_tag);
1301                 sc->jme_cdata.jme_ring_tag = NULL;
1302         }
1303
1304         if (sc->jme_cdata.jme_txdesc != NULL) {
1305                 kfree(sc->jme_cdata.jme_txdesc, M_DEVBUF);
1306                 sc->jme_cdata.jme_txdesc = NULL;
1307         }
1308         for (r = 0; r < sc->jme_rx_ring_cnt; ++r) {
1309                 rdata = &sc->jme_cdata.jme_rx_data[r];
1310                 if (rdata->jme_rxdesc != NULL) {
1311                         kfree(rdata->jme_rxdesc, M_DEVBUF);
1312                         rdata->jme_rxdesc = NULL;
1313                 }
1314         }
1315 }
1316
1317 /*
1318  *      Make sure the interface is stopped at reboot time.
1319  */
1320 static int
1321 jme_shutdown(device_t dev)
1322 {
1323         return jme_suspend(dev);
1324 }
1325
1326 #ifdef notyet
1327 /*
1328  * Unlike other ethernet controllers, JMC250 requires
1329  * explicit resetting link speed to 10/100Mbps as gigabit
1330  * link will cunsume more power than 375mA.
1331  * Note, we reset the link speed to 10/100Mbps with
1332  * auto-negotiation but we don't know whether that operation
1333  * would succeed or not as we have no control after powering
1334  * off. If the renegotiation fail WOL may not work. Running
1335  * at 1Gbps draws more power than 375mA at 3.3V which is
1336  * specified in PCI specification and that would result in
1337  * complete shutdowning power to ethernet controller.
1338  *
1339  * TODO
1340  *  Save current negotiated media speed/duplex/flow-control
1341  *  to softc and restore the same link again after resuming.
1342  *  PHY handling such as power down/resetting to 100Mbps
1343  *  may be better handled in suspend method in phy driver.
1344  */
1345 static void
1346 jme_setlinkspeed(struct jme_softc *sc)
1347 {
1348         struct mii_data *mii;
1349         int aneg, i;
1350
1351         JME_LOCK_ASSERT(sc);
1352
1353         mii = device_get_softc(sc->jme_miibus);
1354         mii_pollstat(mii);
1355         aneg = 0;
1356         if ((mii->mii_media_status & IFM_AVALID) != 0) {
1357                 switch IFM_SUBTYPE(mii->mii_media_active) {
1358                 case IFM_10_T:
1359                 case IFM_100_TX:
1360                         return;
1361                 case IFM_1000_T:
1362                         aneg++;
1363                 default:
1364                         break;
1365                 }
1366         }
1367         jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr, MII_100T2CR, 0);
1368         jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr, MII_ANAR,
1369             ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10 | ANAR_CSMA);
1370         jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr, MII_BMCR,
1371             BMCR_AUTOEN | BMCR_STARTNEG);
1372         DELAY(1000);
1373         if (aneg != 0) {
1374                 /* Poll link state until jme(4) get a 10/100 link. */
1375                 for (i = 0; i < MII_ANEGTICKS_GIGE; i++) {
1376                         mii_pollstat(mii);
1377                         if ((mii->mii_media_status & IFM_AVALID) != 0) {
1378                                 switch (IFM_SUBTYPE(mii->mii_media_active)) {
1379                                 case IFM_10_T:
1380                                 case IFM_100_TX:
1381                                         jme_mac_config(sc);
1382                                         return;
1383                                 default:
1384                                         break;
1385                                 }
1386                         }
1387                         JME_UNLOCK(sc);
1388                         pause("jmelnk", hz);
1389                         JME_LOCK(sc);
1390                 }
1391                 if (i == MII_ANEGTICKS_GIGE)
1392                         device_printf(sc->jme_dev, "establishing link failed, "
1393                             "WOL may not work!");
1394         }
1395         /*
1396          * No link, force MAC to have 100Mbps, full-duplex link.
1397          * This is the last resort and may/may not work.
1398          */
1399         mii->mii_media_status = IFM_AVALID | IFM_ACTIVE;
1400         mii->mii_media_active = IFM_ETHER | IFM_100_TX | IFM_FDX;
1401         jme_mac_config(sc);
1402 }
1403
1404 static void
1405 jme_setwol(struct jme_softc *sc)
1406 {
1407         struct ifnet *ifp = &sc->arpcom.ac_if;
1408         uint32_t gpr, pmcs;
1409         uint16_t pmstat;
1410         int pmc;
1411
1412         if (pci_find_extcap(sc->jme_dev, PCIY_PMG, &pmc) != 0) {
1413                 /* No PME capability, PHY power down. */
1414                 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr,
1415                     MII_BMCR, BMCR_PDOWN);
1416                 return;
1417         }
1418
1419         gpr = CSR_READ_4(sc, JME_GPREG0) & ~GPREG0_PME_ENB;
1420         pmcs = CSR_READ_4(sc, JME_PMCS);
1421         pmcs &= ~PMCS_WOL_ENB_MASK;
1422         if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) {
1423                 pmcs |= PMCS_MAGIC_FRAME | PMCS_MAGIC_FRAME_ENB;
1424                 /* Enable PME message. */
1425                 gpr |= GPREG0_PME_ENB;
1426                 /* For gigabit controllers, reset link speed to 10/100. */
1427                 if ((sc->jme_caps & JME_CAP_FASTETH) == 0)
1428                         jme_setlinkspeed(sc);
1429         }
1430
1431         CSR_WRITE_4(sc, JME_PMCS, pmcs);
1432         CSR_WRITE_4(sc, JME_GPREG0, gpr);
1433
1434         /* Request PME. */
1435         pmstat = pci_read_config(sc->jme_dev, pmc + PCIR_POWER_STATUS, 2);
1436         pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE);
1437         if ((ifp->if_capenable & IFCAP_WOL) != 0)
1438                 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
1439         pci_write_config(sc->jme_dev, pmc + PCIR_POWER_STATUS, pmstat, 2);
1440         if ((ifp->if_capenable & IFCAP_WOL) == 0) {
1441                 /* No WOL, PHY power down. */
1442                 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr,
1443                     MII_BMCR, BMCR_PDOWN);
1444         }
1445 }
1446 #endif
1447
1448 static int
1449 jme_suspend(device_t dev)
1450 {
1451         struct jme_softc *sc = device_get_softc(dev);
1452         struct ifnet *ifp = &sc->arpcom.ac_if;
1453
1454         ifnet_serialize_all(ifp);
1455         jme_stop(sc);
1456 #ifdef notyet
1457         jme_setwol(sc);
1458 #endif
1459         ifnet_deserialize_all(ifp);
1460
1461         return (0);
1462 }
1463
1464 static int
1465 jme_resume(device_t dev)
1466 {
1467         struct jme_softc *sc = device_get_softc(dev);
1468         struct ifnet *ifp = &sc->arpcom.ac_if;
1469 #ifdef notyet
1470         int pmc;
1471 #endif
1472
1473         ifnet_serialize_all(ifp);
1474
1475 #ifdef notyet
1476         if (pci_find_extcap(sc->jme_dev, PCIY_PMG, &pmc) != 0) {
1477                 uint16_t pmstat;
1478
1479                 pmstat = pci_read_config(sc->jme_dev,
1480                     pmc + PCIR_POWER_STATUS, 2);
1481                 /* Disable PME clear PME status. */
1482                 pmstat &= ~PCIM_PSTAT_PMEENABLE;
1483                 pci_write_config(sc->jme_dev,
1484                     pmc + PCIR_POWER_STATUS, pmstat, 2);
1485         }
1486 #endif
1487
1488         if (ifp->if_flags & IFF_UP)
1489                 jme_init(sc);
1490
1491         ifnet_deserialize_all(ifp);
1492
1493         return (0);
1494 }
1495
1496 static int
1497 jme_encap(struct jme_softc *sc, struct mbuf **m_head)
1498 {
1499         struct jme_txdesc *txd;
1500         struct jme_desc *desc;
1501         struct mbuf *m;
1502         bus_dma_segment_t txsegs[JME_MAXTXSEGS];
1503         int maxsegs, nsegs;
1504         int error, i, prod, symbol_desc;
1505         uint32_t cflags, flag64;
1506
1507         M_ASSERTPKTHDR((*m_head));
1508
1509         prod = sc->jme_cdata.jme_tx_prod;
1510         txd = &sc->jme_cdata.jme_txdesc[prod];
1511
1512         if (sc->jme_lowaddr != BUS_SPACE_MAXADDR_32BIT)
1513                 symbol_desc = 1;
1514         else
1515                 symbol_desc = 0;
1516
1517         maxsegs = (sc->jme_tx_desc_cnt - sc->jme_cdata.jme_tx_cnt) -
1518                   (JME_TXD_RSVD + symbol_desc);
1519         if (maxsegs > JME_MAXTXSEGS)
1520                 maxsegs = JME_MAXTXSEGS;
1521         KASSERT(maxsegs >= (sc->jme_txd_spare - symbol_desc),
1522                 ("not enough segments %d\n", maxsegs));
1523
1524         error = bus_dmamap_load_mbuf_defrag(sc->jme_cdata.jme_tx_tag,
1525                         txd->tx_dmamap, m_head,
1526                         txsegs, maxsegs, &nsegs, BUS_DMA_NOWAIT);
1527         if (error)
1528                 goto fail;
1529
1530         bus_dmamap_sync(sc->jme_cdata.jme_tx_tag, txd->tx_dmamap,
1531                         BUS_DMASYNC_PREWRITE);
1532
1533         m = *m_head;
1534         cflags = 0;
1535
1536         /* Configure checksum offload. */
1537         if (m->m_pkthdr.csum_flags & CSUM_IP)
1538                 cflags |= JME_TD_IPCSUM;
1539         if (m->m_pkthdr.csum_flags & CSUM_TCP)
1540                 cflags |= JME_TD_TCPCSUM;
1541         if (m->m_pkthdr.csum_flags & CSUM_UDP)
1542                 cflags |= JME_TD_UDPCSUM;
1543
1544         /* Configure VLAN. */
1545         if (m->m_flags & M_VLANTAG) {
1546                 cflags |= (m->m_pkthdr.ether_vlantag & JME_TD_VLAN_MASK);
1547                 cflags |= JME_TD_VLAN_TAG;
1548         }
1549
1550         desc = &sc->jme_cdata.jme_tx_ring[prod];
1551         desc->flags = htole32(cflags);
1552         desc->addr_hi = htole32(m->m_pkthdr.len);
1553         if (sc->jme_lowaddr != BUS_SPACE_MAXADDR_32BIT) {
1554                 /*
1555                  * Use 64bits TX desc chain format.
1556                  *
1557                  * The first TX desc of the chain, which is setup here,
1558                  * is just a symbol TX desc carrying no payload.
1559                  */
1560                 flag64 = JME_TD_64BIT;
1561                 desc->buflen = 0;
1562                 desc->addr_lo = 0;
1563
1564                 /* No effective TX desc is consumed */
1565                 i = 0;
1566         } else {
1567                 /*
1568                  * Use 32bits TX desc chain format.
1569                  *
1570                  * The first TX desc of the chain, which is setup here,
1571                  * is an effective TX desc carrying the first segment of
1572                  * the mbuf chain.
1573                  */
1574                 flag64 = 0;
1575                 desc->buflen = htole32(txsegs[0].ds_len);
1576                 desc->addr_lo = htole32(JME_ADDR_LO(txsegs[0].ds_addr));
1577
1578                 /* One effective TX desc is consumed */
1579                 i = 1;
1580         }
1581         sc->jme_cdata.jme_tx_cnt++;
1582         KKASSERT(sc->jme_cdata.jme_tx_cnt - i <
1583                  sc->jme_tx_desc_cnt - JME_TXD_RSVD);
1584         JME_DESC_INC(prod, sc->jme_tx_desc_cnt);
1585
1586         txd->tx_ndesc = 1 - i;
1587         for (; i < nsegs; i++) {
1588                 desc = &sc->jme_cdata.jme_tx_ring[prod];
1589                 desc->flags = htole32(JME_TD_OWN | flag64);
1590                 desc->buflen = htole32(txsegs[i].ds_len);
1591                 desc->addr_hi = htole32(JME_ADDR_HI(txsegs[i].ds_addr));
1592                 desc->addr_lo = htole32(JME_ADDR_LO(txsegs[i].ds_addr));
1593
1594                 sc->jme_cdata.jme_tx_cnt++;
1595                 KKASSERT(sc->jme_cdata.jme_tx_cnt <=
1596                          sc->jme_tx_desc_cnt - JME_TXD_RSVD);
1597                 JME_DESC_INC(prod, sc->jme_tx_desc_cnt);
1598         }
1599
1600         /* Update producer index. */
1601         sc->jme_cdata.jme_tx_prod = prod;
1602         /*
1603          * Finally request interrupt and give the first descriptor
1604          * owenership to hardware.
1605          */
1606         desc = txd->tx_desc;
1607         desc->flags |= htole32(JME_TD_OWN | JME_TD_INTR);
1608
1609         txd->tx_m = m;
1610         txd->tx_ndesc += nsegs;
1611
1612         return 0;
1613 fail:
1614         m_freem(*m_head);
1615         *m_head = NULL;
1616         return error;
1617 }
1618
1619 static void
1620 jme_start(struct ifnet *ifp)
1621 {
1622         struct jme_softc *sc = ifp->if_softc;
1623         struct mbuf *m_head;
1624         int enq = 0;
1625
1626         ASSERT_SERIALIZED(&sc->jme_cdata.jme_tx_serialize);
1627
1628         if ((sc->jme_flags & JME_FLAG_LINK) == 0) {
1629                 ifq_purge(&ifp->if_snd);
1630                 return;
1631         }
1632
1633         if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING)
1634                 return;
1635
1636         if (sc->jme_cdata.jme_tx_cnt >= JME_TX_DESC_HIWAT(sc))
1637                 jme_txeof(sc);
1638
1639         while (!ifq_is_empty(&ifp->if_snd)) {
1640                 /*
1641                  * Check number of available TX descs, always
1642                  * leave JME_TXD_RSVD free TX descs.
1643                  */
1644                 if (sc->jme_cdata.jme_tx_cnt + sc->jme_txd_spare >
1645                     sc->jme_tx_desc_cnt - JME_TXD_RSVD) {
1646                         ifp->if_flags |= IFF_OACTIVE;
1647                         break;
1648                 }
1649
1650                 m_head = ifq_dequeue(&ifp->if_snd, NULL);
1651                 if (m_head == NULL)
1652                         break;
1653
1654                 /*
1655                  * Pack the data into the transmit ring. If we
1656                  * don't have room, set the OACTIVE flag and wait
1657                  * for the NIC to drain the ring.
1658                  */
1659                 if (jme_encap(sc, &m_head)) {
1660                         KKASSERT(m_head == NULL);
1661                         ifp->if_oerrors++;
1662                         ifp->if_flags |= IFF_OACTIVE;
1663                         break;
1664                 }
1665                 enq++;
1666
1667                 /*
1668                  * If there's a BPF listener, bounce a copy of this frame
1669                  * to him.
1670                  */
1671                 ETHER_BPF_MTAP(ifp, m_head);
1672         }
1673
1674         if (enq > 0) {
1675                 /*
1676                  * Reading TXCSR takes very long time under heavy load
1677                  * so cache TXCSR value and writes the ORed value with
1678                  * the kick command to the TXCSR. This saves one register
1679                  * access cycle.
1680                  */
1681                 CSR_WRITE_4(sc, JME_TXCSR, sc->jme_txcsr | TXCSR_TX_ENB |
1682                     TXCSR_TXQ_N_START(TXCSR_TXQ0));
1683                 /* Set a timeout in case the chip goes out to lunch. */
1684                 ifp->if_timer = JME_TX_TIMEOUT;
1685         }
1686 }
1687
1688 static void
1689 jme_watchdog(struct ifnet *ifp)
1690 {
1691         struct jme_softc *sc = ifp->if_softc;
1692
1693         ASSERT_IFNET_SERIALIZED_ALL(ifp);
1694
1695         if ((sc->jme_flags & JME_FLAG_LINK) == 0) {
1696                 if_printf(ifp, "watchdog timeout (missed link)\n");
1697                 ifp->if_oerrors++;
1698                 jme_init(sc);
1699                 return;
1700         }
1701
1702         jme_txeof(sc);
1703         if (sc->jme_cdata.jme_tx_cnt == 0) {
1704                 if_printf(ifp, "watchdog timeout (missed Tx interrupts) "
1705                           "-- recovering\n");
1706                 if (!ifq_is_empty(&ifp->if_snd))
1707                         if_devstart(ifp);
1708                 return;
1709         }
1710
1711         if_printf(ifp, "watchdog timeout\n");
1712         ifp->if_oerrors++;
1713         jme_init(sc);
1714         if (!ifq_is_empty(&ifp->if_snd))
1715                 if_devstart(ifp);
1716 }
1717
1718 static int
1719 jme_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data, struct ucred *cr)
1720 {
1721         struct jme_softc *sc = ifp->if_softc;
1722         struct mii_data *mii = device_get_softc(sc->jme_miibus);
1723         struct ifreq *ifr = (struct ifreq *)data;
1724         int error = 0, mask;
1725
1726         ASSERT_IFNET_SERIALIZED_ALL(ifp);
1727
1728         switch (cmd) {
1729         case SIOCSIFMTU:
1730                 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > JME_JUMBO_MTU ||
1731                     (!(sc->jme_caps & JME_CAP_JUMBO) &&
1732                      ifr->ifr_mtu > JME_MAX_MTU)) {
1733                         error = EINVAL;
1734                         break;
1735                 }
1736
1737                 if (ifp->if_mtu != ifr->ifr_mtu) {
1738                         /*
1739                          * No special configuration is required when interface
1740                          * MTU is changed but availability of Tx checksum
1741                          * offload should be chcked against new MTU size as
1742                          * FIFO size is just 2K.
1743                          */
1744                         if (ifr->ifr_mtu >= JME_TX_FIFO_SIZE) {
1745                                 ifp->if_capenable &= ~IFCAP_TXCSUM;
1746                                 ifp->if_hwassist &= ~JME_CSUM_FEATURES;
1747                         }
1748                         ifp->if_mtu = ifr->ifr_mtu;
1749                         if (ifp->if_flags & IFF_RUNNING)
1750                                 jme_init(sc);
1751                 }
1752                 break;
1753
1754         case SIOCSIFFLAGS:
1755                 if (ifp->if_flags & IFF_UP) {
1756                         if (ifp->if_flags & IFF_RUNNING) {
1757                                 if ((ifp->if_flags ^ sc->jme_if_flags) &
1758                                     (IFF_PROMISC | IFF_ALLMULTI))
1759                                         jme_set_filter(sc);
1760                         } else {
1761                                 jme_init(sc);
1762                         }
1763                 } else {
1764                         if (ifp->if_flags & IFF_RUNNING)
1765                                 jme_stop(sc);
1766                 }
1767                 sc->jme_if_flags = ifp->if_flags;
1768                 break;
1769
1770         case SIOCADDMULTI:
1771         case SIOCDELMULTI:
1772                 if (ifp->if_flags & IFF_RUNNING)
1773                         jme_set_filter(sc);
1774                 break;
1775
1776         case SIOCSIFMEDIA:
1777         case SIOCGIFMEDIA:
1778                 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd);
1779                 break;
1780
1781         case SIOCSIFCAP:
1782                 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
1783
1784                 if ((mask & IFCAP_TXCSUM) && ifp->if_mtu < JME_TX_FIFO_SIZE) {
1785                         ifp->if_capenable ^= IFCAP_TXCSUM;
1786                         if (IFCAP_TXCSUM & ifp->if_capenable)
1787                                 ifp->if_hwassist |= JME_CSUM_FEATURES;
1788                         else
1789                                 ifp->if_hwassist &= ~JME_CSUM_FEATURES;
1790                 }
1791                 if (mask & IFCAP_RXCSUM) {
1792                         uint32_t reg;
1793
1794                         ifp->if_capenable ^= IFCAP_RXCSUM;
1795                         reg = CSR_READ_4(sc, JME_RXMAC);
1796                         reg &= ~RXMAC_CSUM_ENB;
1797                         if (ifp->if_capenable & IFCAP_RXCSUM)
1798                                 reg |= RXMAC_CSUM_ENB;
1799                         CSR_WRITE_4(sc, JME_RXMAC, reg);
1800                 }
1801
1802                 if (mask & IFCAP_VLAN_HWTAGGING) {
1803                         ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
1804                         jme_set_vlan(sc);
1805                 }
1806
1807                 if (mask & IFCAP_RSS) {
1808                         ifp->if_capenable ^= IFCAP_RSS;
1809                         if (ifp->if_flags & IFF_RUNNING)
1810                                 jme_init(sc);
1811                 }
1812                 break;
1813
1814         default:
1815                 error = ether_ioctl(ifp, cmd, data);
1816                 break;
1817         }
1818         return (error);
1819 }
1820
1821 static void
1822 jme_mac_config(struct jme_softc *sc)
1823 {
1824         struct mii_data *mii;
1825         uint32_t ghc, rxmac, txmac, txpause, gp1;
1826         int phyconf = JMPHY_CONF_DEFFIFO, hdx = 0;
1827
1828         mii = device_get_softc(sc->jme_miibus);
1829
1830         CSR_WRITE_4(sc, JME_GHC, GHC_RESET);
1831         DELAY(10);
1832         CSR_WRITE_4(sc, JME_GHC, 0);
1833         ghc = 0;
1834         rxmac = CSR_READ_4(sc, JME_RXMAC);
1835         rxmac &= ~RXMAC_FC_ENB;
1836         txmac = CSR_READ_4(sc, JME_TXMAC);
1837         txmac &= ~(TXMAC_CARRIER_EXT | TXMAC_FRAME_BURST);
1838         txpause = CSR_READ_4(sc, JME_TXPFC);
1839         txpause &= ~TXPFC_PAUSE_ENB;
1840         if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) {
1841                 ghc |= GHC_FULL_DUPLEX;
1842                 rxmac &= ~RXMAC_COLL_DET_ENB;
1843                 txmac &= ~(TXMAC_COLL_ENB | TXMAC_CARRIER_SENSE |
1844                     TXMAC_BACKOFF | TXMAC_CARRIER_EXT |
1845                     TXMAC_FRAME_BURST);
1846 #ifdef notyet
1847                 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0)
1848                         txpause |= TXPFC_PAUSE_ENB;
1849                 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0)
1850                         rxmac |= RXMAC_FC_ENB;
1851 #endif
1852                 /* Disable retry transmit timer/retry limit. */
1853                 CSR_WRITE_4(sc, JME_TXTRHD, CSR_READ_4(sc, JME_TXTRHD) &
1854                     ~(TXTRHD_RT_PERIOD_ENB | TXTRHD_RT_LIMIT_ENB));
1855         } else {
1856                 rxmac |= RXMAC_COLL_DET_ENB;
1857                 txmac |= TXMAC_COLL_ENB | TXMAC_CARRIER_SENSE | TXMAC_BACKOFF;
1858                 /* Enable retry transmit timer/retry limit. */
1859                 CSR_WRITE_4(sc, JME_TXTRHD, CSR_READ_4(sc, JME_TXTRHD) |
1860                     TXTRHD_RT_PERIOD_ENB | TXTRHD_RT_LIMIT_ENB);
1861         }
1862
1863         /*
1864          * Reprogram Tx/Rx MACs with resolved speed/duplex.
1865          */
1866         gp1 = CSR_READ_4(sc, JME_GPREG1);
1867         gp1 &= ~GPREG1_WA_HDX;
1868
1869         if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) == 0)
1870                 hdx = 1;
1871
1872         switch (IFM_SUBTYPE(mii->mii_media_active)) {
1873         case IFM_10_T:
1874                 ghc |= GHC_SPEED_10 | sc->jme_clksrc;
1875                 if (hdx)
1876                         gp1 |= GPREG1_WA_HDX;
1877                 break;
1878
1879         case IFM_100_TX:
1880                 ghc |= GHC_SPEED_100 | sc->jme_clksrc;
1881                 if (hdx)
1882                         gp1 |= GPREG1_WA_HDX;
1883
1884                 /*
1885                  * Use extended FIFO depth to workaround CRC errors
1886                  * emitted by chips before JMC250B
1887                  */
1888                 phyconf = JMPHY_CONF_EXTFIFO;
1889                 break;
1890
1891         case IFM_1000_T:
1892                 if (sc->jme_caps & JME_CAP_FASTETH)
1893                         break;
1894
1895                 ghc |= GHC_SPEED_1000 | sc->jme_clksrc_1000;
1896                 if (hdx)
1897                         txmac |= TXMAC_CARRIER_EXT | TXMAC_FRAME_BURST;
1898                 break;
1899
1900         default:
1901                 break;
1902         }
1903         CSR_WRITE_4(sc, JME_GHC, ghc);
1904         CSR_WRITE_4(sc, JME_RXMAC, rxmac);
1905         CSR_WRITE_4(sc, JME_TXMAC, txmac);
1906         CSR_WRITE_4(sc, JME_TXPFC, txpause);
1907
1908         if (sc->jme_workaround & JME_WA_EXTFIFO) {
1909                 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr,
1910                                     JMPHY_CONF, phyconf);
1911         }
1912         if (sc->jme_workaround & JME_WA_HDX)
1913                 CSR_WRITE_4(sc, JME_GPREG1, gp1);
1914 }
1915
1916 static void
1917 jme_intr(void *xsc)
1918 {
1919         struct jme_softc *sc = xsc;
1920         struct ifnet *ifp = &sc->arpcom.ac_if;
1921         uint32_t status;
1922         int r;
1923
1924         ASSERT_SERIALIZED(&sc->jme_serialize);
1925
1926         status = CSR_READ_4(sc, JME_INTR_REQ_STATUS);
1927         if (status == 0 || status == 0xFFFFFFFF)
1928                 return;
1929
1930         /* Disable interrupts. */
1931         CSR_WRITE_4(sc, JME_INTR_MASK_CLR, JME_INTRS);
1932
1933         status = CSR_READ_4(sc, JME_INTR_STATUS);
1934         if ((status & JME_INTRS) == 0 || status == 0xFFFFFFFF)
1935                 goto back;
1936
1937         /* Reset PCC counter/timer and Ack interrupts. */
1938         status &= ~(INTR_TXQ_COMP | INTR_RXQ_COMP);
1939
1940         if (status & (INTR_TXQ_COAL | INTR_TXQ_COAL_TO))
1941                 status |= INTR_TXQ_COAL | INTR_TXQ_COAL_TO | INTR_TXQ_COMP;
1942
1943         for (r = 0; r < sc->jme_rx_ring_inuse; ++r) {
1944                 if (status & jme_rx_status[r].jme_coal) {
1945                         status |= jme_rx_status[r].jme_coal |
1946                                   jme_rx_status[r].jme_comp;
1947                 }
1948         }
1949
1950         CSR_WRITE_4(sc, JME_INTR_STATUS, status);
1951
1952         if (ifp->if_flags & IFF_RUNNING) {
1953                 if (status & (INTR_RXQ_COAL | INTR_RXQ_COAL_TO))
1954                         jme_rx_intr(sc, status);
1955
1956                 if (status & INTR_RXQ_DESC_EMPTY) {
1957                         /*
1958                          * Notify hardware availability of new Rx buffers.
1959                          * Reading RXCSR takes very long time under heavy
1960                          * load so cache RXCSR value and writes the ORed
1961                          * value with the kick command to the RXCSR. This
1962                          * saves one register access cycle.
1963                          */
1964                         CSR_WRITE_4(sc, JME_RXCSR, sc->jme_rxcsr |
1965                             RXCSR_RX_ENB | RXCSR_RXQ_START);
1966                 }
1967
1968                 if (status & (INTR_TXQ_COAL | INTR_TXQ_COAL_TO)) {
1969                         lwkt_serialize_enter(&sc->jme_cdata.jme_tx_serialize);
1970                         jme_txeof(sc);
1971                         if (!ifq_is_empty(&ifp->if_snd))
1972                                 if_devstart(ifp);
1973                         lwkt_serialize_exit(&sc->jme_cdata.jme_tx_serialize);
1974                 }
1975         }
1976 back:
1977         /* Reenable interrupts. */
1978         CSR_WRITE_4(sc, JME_INTR_MASK_SET, JME_INTRS);
1979 }
1980
1981 static void
1982 jme_txeof(struct jme_softc *sc)
1983 {
1984         struct ifnet *ifp = &sc->arpcom.ac_if;
1985         struct jme_txdesc *txd;
1986         uint32_t status;
1987         int cons, nsegs;
1988
1989         cons = sc->jme_cdata.jme_tx_cons;
1990         if (cons == sc->jme_cdata.jme_tx_prod)
1991                 return;
1992
1993         /*
1994          * Go through our Tx list and free mbufs for those
1995          * frames which have been transmitted.
1996          */
1997         while (cons != sc->jme_cdata.jme_tx_prod) {
1998                 txd = &sc->jme_cdata.jme_txdesc[cons];
1999                 KASSERT(txd->tx_m != NULL,
2000                         ("%s: freeing NULL mbuf!\n", __func__));
2001
2002                 status = le32toh(txd->tx_desc->flags);
2003                 if ((status & JME_TD_OWN) == JME_TD_OWN)
2004                         break;
2005
2006                 if (status & (JME_TD_TMOUT | JME_TD_RETRY_EXP)) {
2007                         ifp->if_oerrors++;
2008                 } else {
2009                         ifp->if_opackets++;
2010                         if (status & JME_TD_COLLISION) {
2011                                 ifp->if_collisions +=
2012                                     le32toh(txd->tx_desc->buflen) &
2013                                     JME_TD_BUF_LEN_MASK;
2014                         }
2015                 }
2016
2017                 /*
2018                  * Only the first descriptor of multi-descriptor
2019                  * transmission is updated so driver have to skip entire
2020                  * chained buffers for the transmiited frame. In other
2021                  * words, JME_TD_OWN bit is valid only at the first
2022                  * descriptor of a multi-descriptor transmission.
2023                  */
2024                 for (nsegs = 0; nsegs < txd->tx_ndesc; nsegs++) {
2025                         sc->jme_cdata.jme_tx_ring[cons].flags = 0;
2026                         JME_DESC_INC(cons, sc->jme_tx_desc_cnt);
2027                 }
2028
2029                 /* Reclaim transferred mbufs. */
2030                 bus_dmamap_unload(sc->jme_cdata.jme_tx_tag, txd->tx_dmamap);
2031                 m_freem(txd->tx_m);
2032                 txd->tx_m = NULL;
2033                 sc->jme_cdata.jme_tx_cnt -= txd->tx_ndesc;
2034                 KASSERT(sc->jme_cdata.jme_tx_cnt >= 0,
2035                         ("%s: Active Tx desc counter was garbled\n", __func__));
2036                 txd->tx_ndesc = 0;
2037         }
2038         sc->jme_cdata.jme_tx_cons = cons;
2039
2040         if (sc->jme_cdata.jme_tx_cnt == 0)
2041                 ifp->if_timer = 0;
2042
2043         if (sc->jme_cdata.jme_tx_cnt + sc->jme_txd_spare <=
2044             sc->jme_tx_desc_cnt - JME_TXD_RSVD)
2045                 ifp->if_flags &= ~IFF_OACTIVE;
2046 }
2047
2048 static __inline void
2049 jme_discard_rxbufs(struct jme_softc *sc, int ring, int cons, int count)
2050 {
2051         struct jme_rxdata *rdata = &sc->jme_cdata.jme_rx_data[ring];
2052         int i;
2053
2054         for (i = 0; i < count; ++i) {
2055                 struct jme_desc *desc = &rdata->jme_rx_ring[cons];
2056
2057                 desc->flags = htole32(JME_RD_OWN | JME_RD_INTR | JME_RD_64BIT);
2058                 desc->buflen = htole32(MCLBYTES);
2059                 JME_DESC_INC(cons, sc->jme_rx_desc_cnt);
2060         }
2061 }
2062
2063 static __inline struct pktinfo *
2064 jme_pktinfo(struct pktinfo *pi, uint32_t flags)
2065 {
2066         if (flags & JME_RD_IPV4)
2067                 pi->pi_netisr = NETISR_IP;
2068         else if (flags & JME_RD_IPV6)
2069                 pi->pi_netisr = NETISR_IPV6;
2070         else
2071                 return NULL;
2072
2073         pi->pi_flags = 0;
2074         pi->pi_l3proto = IPPROTO_UNKNOWN;
2075
2076         if (flags & JME_RD_MORE_FRAG)
2077                 pi->pi_flags |= PKTINFO_FLAG_FRAG;
2078         else if (flags & JME_RD_TCP)
2079                 pi->pi_l3proto = IPPROTO_TCP;
2080         else if (flags & JME_RD_UDP)
2081                 pi->pi_l3proto = IPPROTO_UDP;
2082         else
2083                 pi = NULL;
2084         return pi;
2085 }
2086
2087 /* Receive a frame. */
2088 static void
2089 jme_rxpkt(struct jme_softc *sc, int ring)
2090 {
2091         struct ifnet *ifp = &sc->arpcom.ac_if;
2092         struct jme_rxdata *rdata = &sc->jme_cdata.jme_rx_data[ring];
2093         struct jme_desc *desc;
2094         struct jme_rxdesc *rxd;
2095         struct mbuf *mp, *m;
2096         uint32_t flags, status, hash, hashinfo;
2097         int cons, count, nsegs;
2098
2099         cons = rdata->jme_rx_cons;
2100         desc = &rdata->jme_rx_ring[cons];
2101         flags = le32toh(desc->flags);
2102         status = le32toh(desc->buflen);
2103         hash = le32toh(desc->addr_hi);
2104         hashinfo = le32toh(desc->addr_lo);
2105         nsegs = JME_RX_NSEGS(status);
2106
2107         JME_RSS_DPRINTF(sc, 15, "ring%d, flags 0x%08x, "
2108                         "hash 0x%08x, hash info 0x%08x\n",
2109                         ring, flags, hash, hashinfo);
2110
2111         if (status & JME_RX_ERR_STAT) {
2112                 ifp->if_ierrors++;
2113                 jme_discard_rxbufs(sc, ring, cons, nsegs);
2114 #ifdef JME_SHOW_ERRORS
2115                 device_printf(sc->jme_dev, "%s : receive error = 0x%b\n",
2116                     __func__, JME_RX_ERR(status), JME_RX_ERR_BITS);
2117 #endif
2118                 rdata->jme_rx_cons += nsegs;
2119                 rdata->jme_rx_cons %= sc->jme_rx_desc_cnt;
2120                 return;
2121         }
2122
2123         rdata->jme_rxlen = JME_RX_BYTES(status) - JME_RX_PAD_BYTES;
2124         for (count = 0; count < nsegs; count++,
2125              JME_DESC_INC(cons, sc->jme_rx_desc_cnt)) {
2126                 rxd = &rdata->jme_rxdesc[cons];
2127                 mp = rxd->rx_m;
2128
2129                 /* Add a new receive buffer to the ring. */
2130                 if (jme_newbuf(sc, ring, rxd, 0) != 0) {
2131                         ifp->if_iqdrops++;
2132                         /* Reuse buffer. */
2133                         jme_discard_rxbufs(sc, ring, cons, nsegs - count);
2134                         if (rdata->jme_rxhead != NULL) {
2135                                 m_freem(rdata->jme_rxhead);
2136                                 JME_RXCHAIN_RESET(sc, ring);
2137                         }
2138                         break;
2139                 }
2140
2141                 /*
2142                  * Assume we've received a full sized frame.
2143                  * Actual size is fixed when we encounter the end of
2144                  * multi-segmented frame.
2145                  */
2146                 mp->m_len = MCLBYTES;
2147
2148                 /* Chain received mbufs. */
2149                 if (rdata->jme_rxhead == NULL) {
2150                         rdata->jme_rxhead = mp;
2151                         rdata->jme_rxtail = mp;
2152                 } else {
2153                         /*
2154                          * Receive processor can receive a maximum frame
2155                          * size of 65535 bytes.
2156                          */
2157                         rdata->jme_rxtail->m_next = mp;
2158                         rdata->jme_rxtail = mp;
2159                 }
2160
2161                 if (count == nsegs - 1) {
2162                         struct pktinfo pi0, *pi;
2163
2164                         /* Last desc. for this frame. */
2165                         m = rdata->jme_rxhead;
2166                         m->m_pkthdr.len = rdata->jme_rxlen;
2167                         if (nsegs > 1) {
2168                                 /* Set first mbuf size. */
2169                                 m->m_len = MCLBYTES - JME_RX_PAD_BYTES;
2170                                 /* Set last mbuf size. */
2171                                 mp->m_len = rdata->jme_rxlen -
2172                                     ((MCLBYTES - JME_RX_PAD_BYTES) +
2173                                     (MCLBYTES * (nsegs - 2)));
2174                         } else {
2175                                 m->m_len = rdata->jme_rxlen;
2176                         }
2177                         m->m_pkthdr.rcvif = ifp;
2178
2179                         /*
2180                          * Account for 10bytes auto padding which is used
2181                          * to align IP header on 32bit boundary. Also note,
2182                          * CRC bytes is automatically removed by the
2183                          * hardware.
2184                          */
2185                         m->m_data += JME_RX_PAD_BYTES;
2186
2187                         /* Set checksum information. */
2188                         if ((ifp->if_capenable & IFCAP_RXCSUM) &&
2189                             (flags & JME_RD_IPV4)) {
2190                                 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
2191                                 if (flags & JME_RD_IPCSUM)
2192                                         m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
2193                                 if ((flags & JME_RD_MORE_FRAG) == 0 &&
2194                                     ((flags & (JME_RD_TCP | JME_RD_TCPCSUM)) ==
2195                                      (JME_RD_TCP | JME_RD_TCPCSUM) ||
2196                                      (flags & (JME_RD_UDP | JME_RD_UDPCSUM)) ==
2197                                      (JME_RD_UDP | JME_RD_UDPCSUM))) {
2198                                         m->m_pkthdr.csum_flags |=
2199                                             CSUM_DATA_VALID | CSUM_PSEUDO_HDR;
2200                                         m->m_pkthdr.csum_data = 0xffff;
2201                                 }
2202                         }
2203
2204                         /* Check for VLAN tagged packets. */
2205                         if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) &&
2206                             (flags & JME_RD_VLAN_TAG)) {
2207                                 m->m_pkthdr.ether_vlantag =
2208                                     flags & JME_RD_VLAN_MASK;
2209                                 m->m_flags |= M_VLANTAG;
2210                         }
2211
2212                         ifp->if_ipackets++;
2213
2214                         if (ifp->if_capenable & IFCAP_RSS)
2215                                 pi = jme_pktinfo(&pi0, flags);
2216                         else
2217                                 pi = NULL;
2218
2219                         if (pi != NULL &&
2220                             (hashinfo & JME_RD_HASH_FN_MASK) != 0) {
2221                                 m->m_flags |= M_HASH;
2222                                 m->m_pkthdr.hash = toeplitz_hash(hash);
2223                         }
2224
2225 #ifdef JME_RSS_DEBUG
2226                         if (pi != NULL) {
2227                                 JME_RSS_DPRINTF(sc, 10,
2228                                     "isr %d flags %08x, l3 %d %s\n",
2229                                     pi->pi_netisr, pi->pi_flags,
2230                                     pi->pi_l3proto,
2231                                     (m->m_flags & M_HASH) ? "hash" : "");
2232                         }
2233 #endif
2234
2235                         /* Pass it on. */
2236                         ether_input_pkt(ifp, m, pi);
2237
2238                         /* Reset mbuf chains. */
2239                         JME_RXCHAIN_RESET(sc, ring);
2240 #ifdef JME_RSS_DEBUG
2241                         sc->jme_rx_ring_pkt[ring]++;
2242 #endif
2243                 }
2244         }
2245
2246         rdata->jme_rx_cons += nsegs;
2247         rdata->jme_rx_cons %= sc->jme_rx_desc_cnt;
2248 }
2249
2250 static void
2251 jme_rxeof(struct jme_softc *sc, int ring, int count)
2252 {
2253         struct jme_rxdata *rdata = &sc->jme_cdata.jme_rx_data[ring];
2254         struct jme_desc *desc;
2255         int nsegs, pktlen;
2256
2257         for (;;) {
2258 #ifdef DEVICE_POLLING
2259                 if (count >= 0 && count-- == 0)
2260                         break;
2261 #endif
2262                 desc = &rdata->jme_rx_ring[rdata->jme_rx_cons];
2263                 if ((le32toh(desc->flags) & JME_RD_OWN) == JME_RD_OWN)
2264                         break;
2265                 if ((le32toh(desc->buflen) & JME_RD_VALID) == 0)
2266                         break;
2267
2268                 /*
2269                  * Check number of segments against received bytes.
2270                  * Non-matching value would indicate that hardware
2271                  * is still trying to update Rx descriptors. I'm not
2272                  * sure whether this check is needed.
2273                  */
2274                 nsegs = JME_RX_NSEGS(le32toh(desc->buflen));
2275                 pktlen = JME_RX_BYTES(le32toh(desc->buflen));
2276                 if (nsegs != howmany(pktlen, MCLBYTES)) {
2277                         if_printf(&sc->arpcom.ac_if, "RX fragment count(%d) "
2278                                   "and packet size(%d) mismach\n",
2279                                   nsegs, pktlen);
2280                         break;
2281                 }
2282
2283                 /* Received a frame. */
2284                 jme_rxpkt(sc, ring);
2285         }
2286 }
2287
2288 static void
2289 jme_tick(void *xsc)
2290 {
2291         struct jme_softc *sc = xsc;
2292         struct ifnet *ifp = &sc->arpcom.ac_if;
2293         struct mii_data *mii = device_get_softc(sc->jme_miibus);
2294
2295         ifnet_serialize_all(ifp);
2296
2297         mii_tick(mii);
2298         callout_reset(&sc->jme_tick_ch, hz, jme_tick, sc);
2299
2300         ifnet_deserialize_all(ifp);
2301 }
2302
2303 static void
2304 jme_reset(struct jme_softc *sc)
2305 {
2306         uint32_t val;
2307
2308         /* Make sure that TX and RX are stopped */
2309         jme_stop_tx(sc);
2310         jme_stop_rx(sc);
2311
2312         /* Start reset */
2313         CSR_WRITE_4(sc, JME_GHC, GHC_RESET);
2314         DELAY(20);
2315
2316         /*
2317          * Hold reset bit before stop reset
2318          */
2319
2320         /* Disable TXMAC and TXOFL clock sources */
2321         CSR_WRITE_4(sc, JME_GHC, GHC_RESET);
2322         /* Disable RXMAC clock source */
2323         val = CSR_READ_4(sc, JME_GPREG1);
2324         CSR_WRITE_4(sc, JME_GPREG1, val | GPREG1_DIS_RXMAC_CLKSRC);
2325         /* Flush */
2326         CSR_READ_4(sc, JME_GHC);
2327
2328         /* Stop reset */
2329         CSR_WRITE_4(sc, JME_GHC, 0);
2330         /* Flush */
2331         CSR_READ_4(sc, JME_GHC);
2332
2333         /*
2334          * Clear reset bit after stop reset
2335          */
2336
2337         /* Enable TXMAC and TXOFL clock sources */
2338         CSR_WRITE_4(sc, JME_GHC, GHC_TXOFL_CLKSRC | GHC_TXMAC_CLKSRC);
2339         /* Enable RXMAC clock source */
2340         val = CSR_READ_4(sc, JME_GPREG1);
2341         CSR_WRITE_4(sc, JME_GPREG1, val & ~GPREG1_DIS_RXMAC_CLKSRC);
2342         /* Flush */
2343         CSR_READ_4(sc, JME_GHC);
2344
2345         /* Disable TXMAC and TXOFL clock sources */
2346         CSR_WRITE_4(sc, JME_GHC, 0);
2347         /* Disable RXMAC clock source */
2348         val = CSR_READ_4(sc, JME_GPREG1);
2349         CSR_WRITE_4(sc, JME_GPREG1, val | GPREG1_DIS_RXMAC_CLKSRC);
2350         /* Flush */
2351         CSR_READ_4(sc, JME_GHC);
2352
2353         /* Enable TX and RX */
2354         val = CSR_READ_4(sc, JME_TXCSR);
2355         CSR_WRITE_4(sc, JME_TXCSR, val | TXCSR_TX_ENB);
2356         val = CSR_READ_4(sc, JME_RXCSR);
2357         CSR_WRITE_4(sc, JME_RXCSR, val | RXCSR_RX_ENB);
2358         /* Flush */
2359         CSR_READ_4(sc, JME_TXCSR);
2360         CSR_READ_4(sc, JME_RXCSR);
2361
2362         /* Enable TXMAC and TXOFL clock sources */
2363         CSR_WRITE_4(sc, JME_GHC, GHC_TXOFL_CLKSRC | GHC_TXMAC_CLKSRC);
2364         /* Eisable RXMAC clock source */
2365         val = CSR_READ_4(sc, JME_GPREG1);
2366         CSR_WRITE_4(sc, JME_GPREG1, val & ~GPREG1_DIS_RXMAC_CLKSRC);
2367         /* Flush */
2368         CSR_READ_4(sc, JME_GHC);
2369
2370         /* Stop TX and RX */
2371         jme_stop_tx(sc);
2372         jme_stop_rx(sc);
2373 }
2374
2375 static void
2376 jme_init(void *xsc)
2377 {
2378         struct jme_softc *sc = xsc;
2379         struct ifnet *ifp = &sc->arpcom.ac_if;
2380         struct mii_data *mii;
2381         uint8_t eaddr[ETHER_ADDR_LEN];
2382         bus_addr_t paddr;
2383         uint32_t reg;
2384         int error, r;
2385
2386         ASSERT_IFNET_SERIALIZED_ALL(ifp);
2387
2388         /*
2389          * Cancel any pending I/O.
2390          */
2391         jme_stop(sc);
2392
2393         /*
2394          * Reset the chip to a known state.
2395          */
2396         jme_reset(sc);
2397
2398         /*
2399          * Setup MSI/MSI-X vectors to interrupts mapping
2400          */
2401         jme_set_msinum(sc);
2402
2403         sc->jme_txd_spare =
2404         howmany(ifp->if_mtu + sizeof(struct ether_vlan_header), MCLBYTES);
2405         KKASSERT(sc->jme_txd_spare >= 1);
2406
2407         /*
2408          * If we use 64bit address mode for transmitting, each Tx request
2409          * needs one more symbol descriptor.
2410          */
2411         if (sc->jme_lowaddr != BUS_SPACE_MAXADDR_32BIT)
2412                 sc->jme_txd_spare += 1;
2413
2414         if (ifp->if_capenable & IFCAP_RSS)
2415                 jme_enable_rss(sc);
2416         else
2417                 jme_disable_rss(sc);
2418
2419         /* Init RX descriptors */
2420         for (r = 0; r < sc->jme_rx_ring_inuse; ++r) {
2421                 error = jme_init_rx_ring(sc, r);
2422                 if (error) {
2423                         if_printf(ifp, "initialization failed: "
2424                                   "no memory for %dth RX ring.\n", r);
2425                         jme_stop(sc);
2426                         return;
2427                 }
2428         }
2429
2430         /* Init TX descriptors */
2431         jme_init_tx_ring(sc);
2432
2433         /* Initialize shadow status block. */
2434         jme_init_ssb(sc);
2435
2436         /* Reprogram the station address. */
2437         bcopy(IF_LLADDR(ifp), eaddr, ETHER_ADDR_LEN);
2438         CSR_WRITE_4(sc, JME_PAR0,
2439             eaddr[3] << 24 | eaddr[2] << 16 | eaddr[1] << 8 | eaddr[0]);
2440         CSR_WRITE_4(sc, JME_PAR1, eaddr[5] << 8 | eaddr[4]);
2441
2442         /*
2443          * Configure Tx queue.
2444          *  Tx priority queue weight value : 0
2445          *  Tx FIFO threshold for processing next packet : 16QW
2446          *  Maximum Tx DMA length : 512
2447          *  Allow Tx DMA burst.
2448          */
2449         sc->jme_txcsr = TXCSR_TXQ_N_SEL(TXCSR_TXQ0);
2450         sc->jme_txcsr |= TXCSR_TXQ_WEIGHT(TXCSR_TXQ_WEIGHT_MIN);
2451         sc->jme_txcsr |= TXCSR_FIFO_THRESH_16QW;
2452         sc->jme_txcsr |= sc->jme_tx_dma_size;
2453         sc->jme_txcsr |= TXCSR_DMA_BURST;
2454         CSR_WRITE_4(sc, JME_TXCSR, sc->jme_txcsr);
2455
2456         /* Set Tx descriptor counter. */
2457         CSR_WRITE_4(sc, JME_TXQDC, sc->jme_tx_desc_cnt);
2458
2459         /* Set Tx ring address to the hardware. */
2460         paddr = sc->jme_cdata.jme_tx_ring_paddr;
2461         CSR_WRITE_4(sc, JME_TXDBA_HI, JME_ADDR_HI(paddr));
2462         CSR_WRITE_4(sc, JME_TXDBA_LO, JME_ADDR_LO(paddr));
2463
2464         /* Configure TxMAC parameters. */
2465         reg = TXMAC_IFG1_DEFAULT | TXMAC_IFG2_DEFAULT | TXMAC_IFG_ENB;
2466         reg |= TXMAC_THRESH_1_PKT;
2467         reg |= TXMAC_CRC_ENB | TXMAC_PAD_ENB;
2468         CSR_WRITE_4(sc, JME_TXMAC, reg);
2469
2470         /*
2471          * Configure Rx queue.
2472          *  FIFO full threshold for transmitting Tx pause packet : 128T
2473          *  FIFO threshold for processing next packet : 128QW
2474          *  Rx queue 0 select
2475          *  Max Rx DMA length : 128
2476          *  Rx descriptor retry : 32
2477          *  Rx descriptor retry time gap : 256ns
2478          *  Don't receive runt/bad frame.
2479          */
2480         sc->jme_rxcsr = RXCSR_FIFO_FTHRESH_128T;
2481 #if 0
2482         /*
2483          * Since Rx FIFO size is 4K bytes, receiving frames larger
2484          * than 4K bytes will suffer from Rx FIFO overruns. So
2485          * decrease FIFO threshold to reduce the FIFO overruns for
2486          * frames larger than 4000 bytes.
2487          * For best performance of standard MTU sized frames use
2488          * maximum allowable FIFO threshold, 128QW.
2489          */
2490         if ((ifp->if_mtu + ETHER_HDR_LEN + EVL_ENCAPLEN + ETHER_CRC_LEN) >
2491             JME_RX_FIFO_SIZE)
2492                 sc->jme_rxcsr |= RXCSR_FIFO_THRESH_16QW;
2493         else
2494                 sc->jme_rxcsr |= RXCSR_FIFO_THRESH_128QW;
2495 #else
2496         /* Improve PCI Express compatibility */
2497         sc->jme_rxcsr |= RXCSR_FIFO_THRESH_16QW;
2498 #endif
2499         sc->jme_rxcsr |= sc->jme_rx_dma_size;
2500         sc->jme_rxcsr |= RXCSR_DESC_RT_CNT(RXCSR_DESC_RT_CNT_DEFAULT);
2501         sc->jme_rxcsr |= RXCSR_DESC_RT_GAP_256 & RXCSR_DESC_RT_GAP_MASK;
2502         /* XXX TODO DROP_BAD */
2503
2504         for (r = 0; r < sc->jme_rx_ring_inuse; ++r) {
2505                 CSR_WRITE_4(sc, JME_RXCSR, sc->jme_rxcsr | RXCSR_RXQ_N_SEL(r));
2506
2507                 /* Set Rx descriptor counter. */
2508                 CSR_WRITE_4(sc, JME_RXQDC, sc->jme_rx_desc_cnt);
2509
2510                 /* Set Rx ring address to the hardware. */
2511                 paddr = sc->jme_cdata.jme_rx_data[r].jme_rx_ring_paddr;
2512                 CSR_WRITE_4(sc, JME_RXDBA_HI, JME_ADDR_HI(paddr));
2513                 CSR_WRITE_4(sc, JME_RXDBA_LO, JME_ADDR_LO(paddr));
2514         }
2515
2516         /* Clear receive filter. */
2517         CSR_WRITE_4(sc, JME_RXMAC, 0);
2518
2519         /* Set up the receive filter. */
2520         jme_set_filter(sc);
2521         jme_set_vlan(sc);
2522
2523         /*
2524          * Disable all WOL bits as WOL can interfere normal Rx
2525          * operation. Also clear WOL detection status bits.
2526          */
2527         reg = CSR_READ_4(sc, JME_PMCS);
2528         reg &= ~PMCS_WOL_ENB_MASK;
2529         CSR_WRITE_4(sc, JME_PMCS, reg);
2530
2531         /*
2532          * Pad 10bytes right before received frame. This will greatly
2533          * help Rx performance on strict-alignment architectures as
2534          * it does not need to copy the frame to align the payload.
2535          */
2536         reg = CSR_READ_4(sc, JME_RXMAC);
2537         reg |= RXMAC_PAD_10BYTES;
2538
2539         if (ifp->if_capenable & IFCAP_RXCSUM)
2540                 reg |= RXMAC_CSUM_ENB;
2541         CSR_WRITE_4(sc, JME_RXMAC, reg);
2542
2543         /* Configure general purpose reg0 */
2544         reg = CSR_READ_4(sc, JME_GPREG0);
2545         reg &= ~GPREG0_PCC_UNIT_MASK;
2546         /* Set PCC timer resolution to micro-seconds unit. */
2547         reg |= GPREG0_PCC_UNIT_US;
2548         /*
2549          * Disable all shadow register posting as we have to read
2550          * JME_INTR_STATUS register in jme_intr. Also it seems
2551          * that it's hard to synchronize interrupt status between
2552          * hardware and software with shadow posting due to
2553          * requirements of bus_dmamap_sync(9).
2554          */
2555         reg |= GPREG0_SH_POST_DW7_DIS | GPREG0_SH_POST_DW6_DIS |
2556             GPREG0_SH_POST_DW5_DIS | GPREG0_SH_POST_DW4_DIS |
2557             GPREG0_SH_POST_DW3_DIS | GPREG0_SH_POST_DW2_DIS |
2558             GPREG0_SH_POST_DW1_DIS | GPREG0_SH_POST_DW0_DIS;
2559         /* Disable posting of DW0. */
2560         reg &= ~GPREG0_POST_DW0_ENB;
2561         /* Clear PME message. */
2562         reg &= ~GPREG0_PME_ENB;
2563         /* Set PHY address. */
2564         reg &= ~GPREG0_PHY_ADDR_MASK;
2565         reg |= sc->jme_phyaddr;
2566         CSR_WRITE_4(sc, JME_GPREG0, reg);
2567
2568         /* Configure Tx queue 0 packet completion coalescing. */
2569         jme_set_tx_coal(sc);
2570
2571         /* Configure Rx queue 0 packet completion coalescing. */
2572         jme_set_rx_coal(sc);
2573
2574         /* Configure shadow status block but don't enable posting. */
2575         paddr = sc->jme_cdata.jme_ssb_block_paddr;
2576         CSR_WRITE_4(sc, JME_SHBASE_ADDR_HI, JME_ADDR_HI(paddr));
2577         CSR_WRITE_4(sc, JME_SHBASE_ADDR_LO, JME_ADDR_LO(paddr));
2578
2579         /* Disable Timer 1 and Timer 2. */
2580         CSR_WRITE_4(sc, JME_TIMER1, 0);
2581         CSR_WRITE_4(sc, JME_TIMER2, 0);
2582
2583         /* Configure retry transmit period, retry limit value. */
2584         CSR_WRITE_4(sc, JME_TXTRHD,
2585             ((TXTRHD_RT_PERIOD_DEFAULT << TXTRHD_RT_PERIOD_SHIFT) &
2586             TXTRHD_RT_PERIOD_MASK) |
2587             ((TXTRHD_RT_LIMIT_DEFAULT << TXTRHD_RT_LIMIT_SHIFT) &
2588             TXTRHD_RT_LIMIT_SHIFT));
2589
2590 #ifdef DEVICE_POLLING
2591         if (!(ifp->if_flags & IFF_POLLING))
2592 #endif
2593         /* Initialize the interrupt mask. */
2594         CSR_WRITE_4(sc, JME_INTR_MASK_SET, JME_INTRS);
2595         CSR_WRITE_4(sc, JME_INTR_STATUS, 0xFFFFFFFF);
2596
2597         /*
2598          * Enabling Tx/Rx DMA engines and Rx queue processing is
2599          * done after detection of valid link in jme_miibus_statchg.
2600          */
2601         sc->jme_flags &= ~JME_FLAG_LINK;
2602
2603         /* Set the current media. */
2604         mii = device_get_softc(sc->jme_miibus);
2605         mii_mediachg(mii);
2606
2607         callout_reset(&sc->jme_tick_ch, hz, jme_tick, sc);
2608
2609         ifp->if_flags |= IFF_RUNNING;
2610         ifp->if_flags &= ~IFF_OACTIVE;
2611 }
2612
2613 static void
2614 jme_stop(struct jme_softc *sc)
2615 {
2616         struct ifnet *ifp = &sc->arpcom.ac_if;
2617         struct jme_txdesc *txd;
2618         struct jme_rxdesc *rxd;
2619         struct jme_rxdata *rdata;
2620         int i, r;
2621
2622         ASSERT_IFNET_SERIALIZED_ALL(ifp);
2623
2624         /*
2625          * Mark the interface down and cancel the watchdog timer.
2626          */
2627         ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
2628         ifp->if_timer = 0;
2629
2630         callout_stop(&sc->jme_tick_ch);
2631         sc->jme_flags &= ~JME_FLAG_LINK;
2632
2633         /*
2634          * Disable interrupts.
2635          */
2636         CSR_WRITE_4(sc, JME_INTR_MASK_CLR, JME_INTRS);
2637         CSR_WRITE_4(sc, JME_INTR_STATUS, 0xFFFFFFFF);
2638
2639         /* Disable updating shadow status block. */
2640         CSR_WRITE_4(sc, JME_SHBASE_ADDR_LO,
2641             CSR_READ_4(sc, JME_SHBASE_ADDR_LO) & ~SHBASE_POST_ENB);
2642
2643         /* Stop receiver, transmitter. */
2644         jme_stop_rx(sc);
2645         jme_stop_tx(sc);
2646
2647         /*
2648          * Free partial finished RX segments
2649          */
2650         for (r = 0; r < sc->jme_rx_ring_inuse; ++r) {
2651                 rdata = &sc->jme_cdata.jme_rx_data[r];
2652                 if (rdata->jme_rxhead != NULL)
2653                         m_freem(rdata->jme_rxhead);
2654                 JME_RXCHAIN_RESET(sc, r);
2655         }
2656
2657         /*
2658          * Free RX and TX mbufs still in the queues.
2659          */
2660         for (r = 0; r < sc->jme_rx_ring_inuse; ++r) {
2661                 rdata = &sc->jme_cdata.jme_rx_data[r];
2662                 for (i = 0; i < sc->jme_rx_desc_cnt; i++) {
2663                         rxd = &rdata->jme_rxdesc[i];
2664                         if (rxd->rx_m != NULL) {
2665                                 bus_dmamap_unload(rdata->jme_rx_tag,
2666                                                   rxd->rx_dmamap);
2667                                 m_freem(rxd->rx_m);
2668                                 rxd->rx_m = NULL;
2669                         }
2670                 }
2671         }
2672         for (i = 0; i < sc->jme_tx_desc_cnt; i++) {
2673                 txd = &sc->jme_cdata.jme_txdesc[i];
2674                 if (txd->tx_m != NULL) {
2675                         bus_dmamap_unload(sc->jme_cdata.jme_tx_tag,
2676                             txd->tx_dmamap);
2677                         m_freem(txd->tx_m);
2678                         txd->tx_m = NULL;
2679                         txd->tx_ndesc = 0;
2680                 }
2681         }
2682 }
2683
2684 static void
2685 jme_stop_tx(struct jme_softc *sc)
2686 {
2687         uint32_t reg;
2688         int i;
2689
2690         reg = CSR_READ_4(sc, JME_TXCSR);
2691         if ((reg & TXCSR_TX_ENB) == 0)
2692                 return;
2693         reg &= ~TXCSR_TX_ENB;
2694         CSR_WRITE_4(sc, JME_TXCSR, reg);
2695         for (i = JME_TIMEOUT; i > 0; i--) {
2696                 DELAY(1);
2697                 if ((CSR_READ_4(sc, JME_TXCSR) & TXCSR_TX_ENB) == 0)
2698                         break;
2699         }
2700         if (i == 0)
2701                 device_printf(sc->jme_dev, "stopping transmitter timeout!\n");
2702 }
2703
2704 static void
2705 jme_stop_rx(struct jme_softc *sc)
2706 {
2707         uint32_t reg;
2708         int i;
2709
2710         reg = CSR_READ_4(sc, JME_RXCSR);
2711         if ((reg & RXCSR_RX_ENB) == 0)
2712                 return;
2713         reg &= ~RXCSR_RX_ENB;
2714         CSR_WRITE_4(sc, JME_RXCSR, reg);
2715         for (i = JME_TIMEOUT; i > 0; i--) {
2716                 DELAY(1);
2717                 if ((CSR_READ_4(sc, JME_RXCSR) & RXCSR_RX_ENB) == 0)
2718                         break;
2719         }
2720         if (i == 0)
2721                 device_printf(sc->jme_dev, "stopping recevier timeout!\n");
2722 }
2723
2724 static void
2725 jme_init_tx_ring(struct jme_softc *sc)
2726 {
2727         struct jme_chain_data *cd;
2728         struct jme_txdesc *txd;
2729         int i;
2730
2731         sc->jme_cdata.jme_tx_prod = 0;
2732         sc->jme_cdata.jme_tx_cons = 0;
2733         sc->jme_cdata.jme_tx_cnt = 0;
2734
2735         cd = &sc->jme_cdata;
2736         bzero(cd->jme_tx_ring, JME_TX_RING_SIZE(sc));
2737         for (i = 0; i < sc->jme_tx_desc_cnt; i++) {
2738                 txd = &sc->jme_cdata.jme_txdesc[i];
2739                 txd->tx_m = NULL;
2740                 txd->tx_desc = &cd->jme_tx_ring[i];
2741                 txd->tx_ndesc = 0;
2742         }
2743 }
2744
2745 static void
2746 jme_init_ssb(struct jme_softc *sc)
2747 {
2748         struct jme_chain_data *cd;
2749
2750         cd = &sc->jme_cdata;
2751         bzero(cd->jme_ssb_block, JME_SSB_SIZE);
2752 }
2753
2754 static int
2755 jme_init_rx_ring(struct jme_softc *sc, int ring)
2756 {
2757         struct jme_rxdata *rdata = &sc->jme_cdata.jme_rx_data[ring];
2758         struct jme_rxdesc *rxd;
2759         int i;
2760
2761         KKASSERT(rdata->jme_rxhead == NULL &&
2762                  rdata->jme_rxtail == NULL &&
2763                  rdata->jme_rxlen == 0);
2764         rdata->jme_rx_cons = 0;
2765
2766         bzero(rdata->jme_rx_ring, JME_RX_RING_SIZE(sc));
2767         for (i = 0; i < sc->jme_rx_desc_cnt; i++) {
2768                 int error;
2769
2770                 rxd = &rdata->jme_rxdesc[i];
2771                 rxd->rx_m = NULL;
2772                 rxd->rx_desc = &rdata->jme_rx_ring[i];
2773                 error = jme_newbuf(sc, ring, rxd, 1);
2774                 if (error)
2775                         return error;
2776         }
2777         return 0;
2778 }
2779
2780 static int
2781 jme_newbuf(struct jme_softc *sc, int ring, struct jme_rxdesc *rxd, int init)
2782 {
2783         struct jme_rxdata *rdata = &sc->jme_cdata.jme_rx_data[ring];
2784         struct jme_desc *desc;
2785         struct mbuf *m;
2786         bus_dma_segment_t segs;
2787         bus_dmamap_t map;
2788         int error, nsegs;
2789
2790         m = m_getcl(init ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR);
2791         if (m == NULL)
2792                 return ENOBUFS;
2793         /*
2794          * JMC250 has 64bit boundary alignment limitation so jme(4)
2795          * takes advantage of 10 bytes padding feature of hardware
2796          * in order not to copy entire frame to align IP header on
2797          * 32bit boundary.
2798          */
2799         m->m_len = m->m_pkthdr.len = MCLBYTES;
2800
2801         error = bus_dmamap_load_mbuf_segment(rdata->jme_rx_tag,
2802                         rdata->jme_rx_sparemap, m, &segs, 1, &nsegs,
2803                         BUS_DMA_NOWAIT);
2804         if (error) {
2805                 m_freem(m);
2806                 if (init)
2807                         if_printf(&sc->arpcom.ac_if, "can't load RX mbuf\n");
2808                 return error;
2809         }
2810
2811         if (rxd->rx_m != NULL) {
2812                 bus_dmamap_sync(rdata->jme_rx_tag, rxd->rx_dmamap,
2813                                 BUS_DMASYNC_POSTREAD);
2814                 bus_dmamap_unload(rdata->jme_rx_tag, rxd->rx_dmamap);
2815         }
2816         map = rxd->rx_dmamap;
2817         rxd->rx_dmamap = rdata->jme_rx_sparemap;
2818         rdata->jme_rx_sparemap = map;
2819         rxd->rx_m = m;
2820
2821         desc = rxd->rx_desc;
2822         desc->buflen = htole32(segs.ds_len);
2823         desc->addr_lo = htole32(JME_ADDR_LO(segs.ds_addr));
2824         desc->addr_hi = htole32(JME_ADDR_HI(segs.ds_addr));
2825         desc->flags = htole32(JME_RD_OWN | JME_RD_INTR | JME_RD_64BIT);
2826
2827         return 0;
2828 }
2829
2830 static void
2831 jme_set_vlan(struct jme_softc *sc)
2832 {
2833         struct ifnet *ifp = &sc->arpcom.ac_if;
2834         uint32_t reg;
2835
2836         ASSERT_IFNET_SERIALIZED_ALL(ifp);
2837
2838         reg = CSR_READ_4(sc, JME_RXMAC);
2839         reg &= ~RXMAC_VLAN_ENB;
2840         if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING)
2841                 reg |= RXMAC_VLAN_ENB;
2842         CSR_WRITE_4(sc, JME_RXMAC, reg);
2843 }
2844
2845 static void
2846 jme_set_filter(struct jme_softc *sc)
2847 {
2848         struct ifnet *ifp = &sc->arpcom.ac_if;
2849         struct ifmultiaddr *ifma;
2850         uint32_t crc;
2851         uint32_t mchash[2];
2852         uint32_t rxcfg;
2853
2854         ASSERT_IFNET_SERIALIZED_ALL(ifp);
2855
2856         rxcfg = CSR_READ_4(sc, JME_RXMAC);
2857         rxcfg &= ~(RXMAC_BROADCAST | RXMAC_PROMISC | RXMAC_MULTICAST |
2858             RXMAC_ALLMULTI);
2859
2860         /*
2861          * Always accept frames destined to our station address.
2862          * Always accept broadcast frames.
2863          */
2864         rxcfg |= RXMAC_UNICAST | RXMAC_BROADCAST;
2865
2866         if (ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) {
2867                 if (ifp->if_flags & IFF_PROMISC)
2868                         rxcfg |= RXMAC_PROMISC;
2869                 if (ifp->if_flags & IFF_ALLMULTI)
2870                         rxcfg |= RXMAC_ALLMULTI;
2871                 CSR_WRITE_4(sc, JME_MAR0, 0xFFFFFFFF);
2872                 CSR_WRITE_4(sc, JME_MAR1, 0xFFFFFFFF);
2873                 CSR_WRITE_4(sc, JME_RXMAC, rxcfg);
2874                 return;
2875         }
2876
2877         /*
2878          * Set up the multicast address filter by passing all multicast
2879          * addresses through a CRC generator, and then using the low-order
2880          * 6 bits as an index into the 64 bit multicast hash table.  The
2881          * high order bits select the register, while the rest of the bits
2882          * select the bit within the register.
2883          */
2884         rxcfg |= RXMAC_MULTICAST;
2885         bzero(mchash, sizeof(mchash));
2886
2887         TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
2888                 if (ifma->ifma_addr->sa_family != AF_LINK)
2889                         continue;
2890                 crc = ether_crc32_be(LLADDR((struct sockaddr_dl *)
2891                     ifma->ifma_addr), ETHER_ADDR_LEN);
2892
2893                 /* Just want the 6 least significant bits. */
2894                 crc &= 0x3f;
2895
2896                 /* Set the corresponding bit in the hash table. */
2897                 mchash[crc >> 5] |= 1 << (crc & 0x1f);
2898         }
2899
2900         CSR_WRITE_4(sc, JME_MAR0, mchash[0]);
2901         CSR_WRITE_4(sc, JME_MAR1, mchash[1]);
2902         CSR_WRITE_4(sc, JME_RXMAC, rxcfg);
2903 }
2904
2905 static int
2906 jme_sysctl_tx_coal_to(SYSCTL_HANDLER_ARGS)
2907 {
2908         struct jme_softc *sc = arg1;
2909         struct ifnet *ifp = &sc->arpcom.ac_if;
2910         int error, v;
2911
2912         ifnet_serialize_all(ifp);
2913
2914         v = sc->jme_tx_coal_to;
2915         error = sysctl_handle_int(oidp, &v, 0, req);
2916         if (error || req->newptr == NULL)
2917                 goto back;
2918
2919         if (v < PCCTX_COAL_TO_MIN || v > PCCTX_COAL_TO_MAX) {
2920                 error = EINVAL;
2921                 goto back;
2922         }
2923
2924         if (v != sc->jme_tx_coal_to) {
2925                 sc->jme_tx_coal_to = v;
2926                 if (ifp->if_flags & IFF_RUNNING)
2927                         jme_set_tx_coal(sc);
2928         }
2929 back:
2930         ifnet_deserialize_all(ifp);
2931         return error;
2932 }
2933
2934 static int
2935 jme_sysctl_tx_coal_pkt(SYSCTL_HANDLER_ARGS)
2936 {
2937         struct jme_softc *sc = arg1;
2938         struct ifnet *ifp = &sc->arpcom.ac_if;
2939         int error, v;
2940
2941         ifnet_serialize_all(ifp);
2942
2943         v = sc->jme_tx_coal_pkt;
2944         error = sysctl_handle_int(oidp, &v, 0, req);
2945         if (error || req->newptr == NULL)
2946                 goto back;
2947
2948         if (v < PCCTX_COAL_PKT_MIN || v > PCCTX_COAL_PKT_MAX) {
2949                 error = EINVAL;
2950                 goto back;
2951         }
2952
2953         if (v != sc->jme_tx_coal_pkt) {
2954                 sc->jme_tx_coal_pkt = v;
2955                 if (ifp->if_flags & IFF_RUNNING)
2956                         jme_set_tx_coal(sc);
2957         }
2958 back:
2959         ifnet_deserialize_all(ifp);
2960         return error;
2961 }
2962
2963 static int
2964 jme_sysctl_rx_coal_to(SYSCTL_HANDLER_ARGS)
2965 {
2966         struct jme_softc *sc = arg1;
2967         struct ifnet *ifp = &sc->arpcom.ac_if;
2968         int error, v;
2969
2970         ifnet_serialize_all(ifp);
2971
2972         v = sc->jme_rx_coal_to;
2973         error = sysctl_handle_int(oidp, &v, 0, req);
2974         if (error || req->newptr == NULL)
2975                 goto back;
2976
2977         if (v < PCCRX_COAL_TO_MIN || v > PCCRX_COAL_TO_MAX) {
2978                 error = EINVAL;
2979                 goto back;
2980         }
2981
2982         if (v != sc->jme_rx_coal_to) {
2983                 sc->jme_rx_coal_to = v;
2984                 if (ifp->if_flags & IFF_RUNNING)
2985                         jme_set_rx_coal(sc);
2986         }
2987 back:
2988         ifnet_deserialize_all(ifp);
2989         return error;
2990 }
2991
2992 static int
2993 jme_sysctl_rx_coal_pkt(SYSCTL_HANDLER_ARGS)
2994 {
2995         struct jme_softc *sc = arg1;
2996         struct ifnet *ifp = &sc->arpcom.ac_if;
2997         int error, v;
2998
2999         ifnet_serialize_all(ifp);
3000
3001         v = sc->jme_rx_coal_pkt;
3002         error = sysctl_handle_int(oidp, &v, 0, req);
3003         if (error || req->newptr == NULL)
3004                 goto back;
3005
3006         if (v < PCCRX_COAL_PKT_MIN || v > PCCRX_COAL_PKT_MAX) {
3007                 error = EINVAL;
3008                 goto back;
3009         }
3010
3011         if (v != sc->jme_rx_coal_pkt) {
3012                 sc->jme_rx_coal_pkt = v;
3013                 if (ifp->if_flags & IFF_RUNNING)
3014                         jme_set_rx_coal(sc);
3015         }
3016 back:
3017         ifnet_deserialize_all(ifp);
3018         return error;
3019 }
3020
3021 static void
3022 jme_set_tx_coal(struct jme_softc *sc)
3023 {
3024         uint32_t reg;
3025
3026         reg = (sc->jme_tx_coal_to << PCCTX_COAL_TO_SHIFT) &
3027             PCCTX_COAL_TO_MASK;
3028         reg |= (sc->jme_tx_coal_pkt << PCCTX_COAL_PKT_SHIFT) &
3029             PCCTX_COAL_PKT_MASK;
3030         reg |= PCCTX_COAL_TXQ0;
3031         CSR_WRITE_4(sc, JME_PCCTX, reg);
3032 }
3033
3034 static void
3035 jme_set_rx_coal(struct jme_softc *sc)
3036 {
3037         uint32_t reg;
3038         int r;
3039
3040         reg = (sc->jme_rx_coal_to << PCCRX_COAL_TO_SHIFT) &
3041             PCCRX_COAL_TO_MASK;
3042         reg |= (sc->jme_rx_coal_pkt << PCCRX_COAL_PKT_SHIFT) &
3043             PCCRX_COAL_PKT_MASK;
3044         for (r = 0; r < sc->jme_rx_ring_cnt; ++r) {
3045                 if (r < sc->jme_rx_ring_inuse)
3046                         CSR_WRITE_4(sc, JME_PCCRX(r), reg);
3047                 else
3048                         CSR_WRITE_4(sc, JME_PCCRX(r), 0);
3049         }
3050 }
3051
3052 #ifdef DEVICE_POLLING
3053
3054 static void
3055 jme_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
3056 {
3057         struct jme_softc *sc = ifp->if_softc;
3058         uint32_t status;
3059         int r;
3060
3061         ASSERT_SERIALIZED(&sc->jme_serialize);
3062
3063         switch (cmd) {
3064         case POLL_REGISTER:
3065                 CSR_WRITE_4(sc, JME_INTR_MASK_CLR, JME_INTRS);
3066                 break;
3067
3068         case POLL_DEREGISTER:
3069                 CSR_WRITE_4(sc, JME_INTR_MASK_SET, JME_INTRS);
3070                 break;
3071
3072         case POLL_AND_CHECK_STATUS:
3073         case POLL_ONLY:
3074                 status = CSR_READ_4(sc, JME_INTR_STATUS);
3075
3076                 for (r = 0; r < sc->jme_rx_ring_inuse; ++r) {
3077                         struct jme_rxdata *rdata =
3078                             &sc->jme_cdata.jme_rx_data[r];
3079
3080                         lwkt_serialize_enter(&rdata->jme_rx_serialize);
3081                         jme_rxeof(sc, r, count);
3082                         lwkt_serialize_exit(&rdata->jme_rx_serialize);
3083                 }
3084
3085                 if (status & INTR_RXQ_DESC_EMPTY) {
3086                         CSR_WRITE_4(sc, JME_INTR_STATUS, status);
3087                         CSR_WRITE_4(sc, JME_RXCSR, sc->jme_rxcsr |
3088                             RXCSR_RX_ENB | RXCSR_RXQ_START);
3089                 }
3090
3091                 lwkt_serialize_enter(&sc->jme_cdata.jme_tx_serialize);
3092                 jme_txeof(sc);
3093                 if (!ifq_is_empty(&ifp->if_snd))
3094                         if_devstart(ifp);
3095                 lwkt_serialize_exit(&sc->jme_cdata.jme_tx_serialize);
3096                 break;
3097         }
3098 }
3099
3100 #endif  /* DEVICE_POLLING */
3101
3102 static int
3103 jme_rxring_dma_alloc(struct jme_softc *sc, int ring)
3104 {
3105         struct jme_rxdata *rdata = &sc->jme_cdata.jme_rx_data[ring];
3106         bus_dmamem_t dmem;
3107         int error;
3108
3109         error = bus_dmamem_coherent(sc->jme_cdata.jme_ring_tag,
3110                         JME_RX_RING_ALIGN, 0,
3111                         BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
3112                         JME_RX_RING_SIZE(sc),
3113                         BUS_DMA_WAITOK | BUS_DMA_ZERO, &dmem);
3114         if (error) {
3115                 device_printf(sc->jme_dev,
3116                     "could not allocate %dth Rx ring.\n", ring);
3117                 return error;
3118         }
3119         rdata->jme_rx_ring_tag = dmem.dmem_tag;
3120         rdata->jme_rx_ring_map = dmem.dmem_map;
3121         rdata->jme_rx_ring = dmem.dmem_addr;
3122         rdata->jme_rx_ring_paddr = dmem.dmem_busaddr;
3123
3124         return 0;
3125 }
3126
3127 static int
3128 jme_rxbuf_dma_alloc(struct jme_softc *sc, int ring)
3129 {
3130         struct jme_rxdata *rdata = &sc->jme_cdata.jme_rx_data[ring];
3131         int i, error;
3132
3133         /* Create tag for Rx buffers. */
3134         error = bus_dma_tag_create(sc->jme_cdata.jme_buffer_tag,/* parent */
3135             JME_RX_BUF_ALIGN, 0,        /* algnmnt, boundary */
3136             BUS_SPACE_MAXADDR,          /* lowaddr */
3137             BUS_SPACE_MAXADDR,          /* highaddr */
3138             NULL, NULL,                 /* filter, filterarg */
3139             MCLBYTES,                   /* maxsize */
3140             1,                          /* nsegments */
3141             MCLBYTES,                   /* maxsegsize */
3142             BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK | BUS_DMA_ALIGNED,/* flags */
3143             &rdata->jme_rx_tag);
3144         if (error) {
3145                 device_printf(sc->jme_dev,
3146                     "could not create %dth Rx DMA tag.\n", ring);
3147                 return error;
3148         }
3149
3150         /* Create DMA maps for Rx buffers. */
3151         error = bus_dmamap_create(rdata->jme_rx_tag, BUS_DMA_WAITOK,
3152                                   &rdata->jme_rx_sparemap);
3153         if (error) {
3154                 device_printf(sc->jme_dev,
3155                     "could not create %dth spare Rx dmamap.\n", ring);
3156                 bus_dma_tag_destroy(rdata->jme_rx_tag);
3157                 rdata->jme_rx_tag = NULL;
3158                 return error;
3159         }
3160         for (i = 0; i < sc->jme_rx_desc_cnt; i++) {
3161                 struct jme_rxdesc *rxd = &rdata->jme_rxdesc[i];
3162
3163                 error = bus_dmamap_create(rdata->jme_rx_tag, BUS_DMA_WAITOK,
3164                                           &rxd->rx_dmamap);
3165                 if (error) {
3166                         int j;
3167
3168                         device_printf(sc->jme_dev,
3169                             "could not create %dth Rx dmamap "
3170                             "for %dth RX ring.\n", i, ring);
3171
3172                         for (j = 0; j < i; ++j) {
3173                                 rxd = &rdata->jme_rxdesc[j];
3174                                 bus_dmamap_destroy(rdata->jme_rx_tag,
3175                                                    rxd->rx_dmamap);
3176                         }
3177                         bus_dmamap_destroy(rdata->jme_rx_tag,
3178                                            rdata->jme_rx_sparemap);
3179                         bus_dma_tag_destroy(rdata->jme_rx_tag);
3180                         rdata->jme_rx_tag = NULL;
3181                         return error;
3182                 }
3183         }
3184         return 0;
3185 }
3186
3187 static void
3188 jme_rx_intr(struct jme_softc *sc, uint32_t status)
3189 {
3190         int r;
3191
3192         for (r = 0; r < sc->jme_rx_ring_inuse; ++r) {
3193                 if (status & jme_rx_status[r].jme_coal) {
3194                         struct jme_rxdata *rdata =
3195                             &sc->jme_cdata.jme_rx_data[r];
3196
3197                         lwkt_serialize_enter(&rdata->jme_rx_serialize);
3198                         jme_rxeof(sc, r, -1);
3199                         lwkt_serialize_exit(&rdata->jme_rx_serialize);
3200                 }
3201         }
3202 }
3203
3204 static void
3205 jme_enable_rss(struct jme_softc *sc)
3206 {
3207         uint32_t rssc, ind;
3208         uint8_t key[RSSKEY_NREGS * RSSKEY_REGSIZE];
3209         int i;
3210
3211         sc->jme_rx_ring_inuse = sc->jme_rx_ring_cnt;
3212
3213         KASSERT(sc->jme_rx_ring_inuse == JME_NRXRING_2 ||
3214                 sc->jme_rx_ring_inuse == JME_NRXRING_4,
3215                 ("%s: invalid # of RX rings (%d)\n",
3216                  sc->arpcom.ac_if.if_xname, sc->jme_rx_ring_inuse));
3217
3218         rssc = RSSC_HASH_64_ENTRY;
3219         rssc |= RSSC_HASH_IPV4 | RSSC_HASH_IPV4_TCP;
3220         rssc |= sc->jme_rx_ring_inuse >> 1;
3221         JME_RSS_DPRINTF(sc, 1, "rssc 0x%08x\n", rssc);
3222         CSR_WRITE_4(sc, JME_RSSC, rssc);
3223
3224         toeplitz_get_key(key, sizeof(key));
3225         for (i = 0; i < RSSKEY_NREGS; ++i) {
3226                 uint32_t keyreg;
3227
3228                 keyreg = RSSKEY_REGVAL(key, i);
3229                 JME_RSS_DPRINTF(sc, 5, "keyreg%d 0x%08x\n", i, keyreg);
3230
3231                 CSR_WRITE_4(sc, RSSKEY_REG(i), keyreg);
3232         }
3233
3234         /*
3235          * Create redirect table in following fashion:
3236          * (hash & ring_cnt_mask) == rdr_table[(hash & rdr_table_mask)]
3237          */
3238         ind = 0;
3239         for (i = 0; i < RSSTBL_REGSIZE; ++i) {
3240                 int q;
3241
3242                 q = i % sc->jme_rx_ring_inuse;
3243                 ind |= q << (i * 8);
3244         }
3245         JME_RSS_DPRINTF(sc, 1, "ind 0x%08x\n", ind);
3246
3247         for (i = 0; i < RSSTBL_NREGS; ++i)
3248                 CSR_WRITE_4(sc, RSSTBL_REG(i), ind);
3249 }
3250
3251 static void
3252 jme_disable_rss(struct jme_softc *sc)
3253 {
3254         sc->jme_rx_ring_inuse = JME_NRXRING_1;
3255         CSR_WRITE_4(sc, JME_RSSC, RSSC_DIS_RSS);
3256 }
3257
3258 static void
3259 jme_serialize(struct ifnet *ifp, enum ifnet_serialize slz)
3260 {
3261         struct jme_softc *sc = ifp->if_softc;
3262
3263         switch (slz) {
3264         case IFNET_SERIALIZE_ALL:
3265                 lwkt_serialize_array_enter(sc->jme_serialize_arr,
3266                     sc->jme_serialize_cnt, 0);
3267                 break;
3268
3269         case IFNET_SERIALIZE_MAIN:
3270                 lwkt_serialize_enter(&sc->jme_serialize);
3271                 break;
3272
3273         case IFNET_SERIALIZE_TX:
3274                 lwkt_serialize_enter(&sc->jme_cdata.jme_tx_serialize);
3275                 break;
3276
3277         case IFNET_SERIALIZE_RX(0):
3278                 lwkt_serialize_enter(
3279                     &sc->jme_cdata.jme_rx_data[0].jme_rx_serialize);
3280                 break;
3281
3282         case IFNET_SERIALIZE_RX(1):
3283                 lwkt_serialize_enter(
3284                     &sc->jme_cdata.jme_rx_data[1].jme_rx_serialize);
3285                 break;
3286
3287         case IFNET_SERIALIZE_RX(2):
3288                 lwkt_serialize_enter(
3289                     &sc->jme_cdata.jme_rx_data[2].jme_rx_serialize);
3290                 break;
3291
3292         case IFNET_SERIALIZE_RX(3):
3293                 lwkt_serialize_enter(
3294                     &sc->jme_cdata.jme_rx_data[3].jme_rx_serialize);
3295                 break;
3296
3297         default:
3298                 panic("%s unsupported serialize type\n", ifp->if_xname);
3299         }
3300 }
3301
3302 static void
3303 jme_deserialize(struct ifnet *ifp, enum ifnet_serialize slz)
3304 {
3305         struct jme_softc *sc = ifp->if_softc;
3306
3307         switch (slz) {
3308         case IFNET_SERIALIZE_ALL:
3309                 lwkt_serialize_array_exit(sc->jme_serialize_arr,
3310                     sc->jme_serialize_cnt, 0);
3311                 break;
3312
3313         case IFNET_SERIALIZE_MAIN:
3314                 lwkt_serialize_exit(&sc->jme_serialize);
3315                 break;
3316
3317         case IFNET_SERIALIZE_TX:
3318                 lwkt_serialize_exit(&sc->jme_cdata.jme_tx_serialize);
3319                 break;
3320
3321         case IFNET_SERIALIZE_RX(0):
3322                 lwkt_serialize_exit(
3323                     &sc->jme_cdata.jme_rx_data[0].jme_rx_serialize);
3324                 break;
3325
3326         case IFNET_SERIALIZE_RX(1):
3327                 lwkt_serialize_exit(
3328                     &sc->jme_cdata.jme_rx_data[1].jme_rx_serialize);
3329                 break;
3330
3331         case IFNET_SERIALIZE_RX(2):
3332                 lwkt_serialize_exit(
3333                     &sc->jme_cdata.jme_rx_data[2].jme_rx_serialize);
3334                 break;
3335
3336         case IFNET_SERIALIZE_RX(3):
3337                 lwkt_serialize_exit(
3338                     &sc->jme_cdata.jme_rx_data[3].jme_rx_serialize);
3339                 break;
3340
3341         default:
3342                 panic("%s unsupported serialize type\n", ifp->if_xname);
3343         }
3344 }
3345
3346 static int
3347 jme_tryserialize(struct ifnet *ifp, enum ifnet_serialize slz)
3348 {
3349         struct jme_softc *sc = ifp->if_softc;
3350
3351         switch (slz) {
3352         case IFNET_SERIALIZE_ALL:
3353                 return lwkt_serialize_array_try(sc->jme_serialize_arr,
3354                     sc->jme_serialize_cnt, 0);
3355
3356         case IFNET_SERIALIZE_MAIN:
3357                 return lwkt_serialize_try(&sc->jme_serialize);
3358
3359         case IFNET_SERIALIZE_TX:
3360                 return lwkt_serialize_try(&sc->jme_cdata.jme_tx_serialize);
3361
3362         case IFNET_SERIALIZE_RX(0):
3363                 return lwkt_serialize_try(
3364                     &sc->jme_cdata.jme_rx_data[0].jme_rx_serialize);
3365
3366         case IFNET_SERIALIZE_RX(1):
3367                 return lwkt_serialize_try(
3368                     &sc->jme_cdata.jme_rx_data[1].jme_rx_serialize);
3369
3370         case IFNET_SERIALIZE_RX(2):
3371                 return lwkt_serialize_try(
3372                     &sc->jme_cdata.jme_rx_data[2].jme_rx_serialize);
3373
3374         case IFNET_SERIALIZE_RX(3):
3375                 return lwkt_serialize_try(
3376                     &sc->jme_cdata.jme_rx_data[3].jme_rx_serialize);
3377
3378         default:
3379                 panic("%s unsupported serialize type\n", ifp->if_xname);
3380         }
3381 }
3382
3383 #ifdef INVARIANTS
3384
3385 static void
3386 jme_serialize_assert(struct ifnet *ifp, enum ifnet_serialize slz,
3387     boolean_t serialized)
3388 {
3389         struct jme_softc *sc = ifp->if_softc;
3390         struct jme_rxdata *rdata;
3391         int i;
3392
3393         switch (slz) {
3394         case IFNET_SERIALIZE_ALL:
3395                 if (serialized) {
3396                         for (i = 0; i < sc->jme_serialize_cnt; ++i)
3397                                 ASSERT_SERIALIZED(sc->jme_serialize_arr[i]);
3398                 } else {
3399                         for (i = 0; i < sc->jme_serialize_cnt; ++i)
3400                                 ASSERT_NOT_SERIALIZED(sc->jme_serialize_arr[i]);
3401                 }
3402                 break;
3403
3404         case IFNET_SERIALIZE_MAIN:
3405                 if (serialized)
3406                         ASSERT_SERIALIZED(&sc->jme_serialize);
3407                 else
3408                         ASSERT_NOT_SERIALIZED(&sc->jme_serialize);
3409                 break;
3410
3411         case IFNET_SERIALIZE_TX:
3412                 if (serialized)
3413                         ASSERT_SERIALIZED(&sc->jme_cdata.jme_tx_serialize);
3414                 else
3415                         ASSERT_NOT_SERIALIZED(&sc->jme_cdata.jme_tx_serialize);
3416                 break;
3417
3418         case IFNET_SERIALIZE_RX(0):
3419                 rdata = &sc->jme_cdata.jme_rx_data[0];
3420                 if (serialized)
3421                         ASSERT_SERIALIZED(&rdata->jme_rx_serialize);
3422                 else
3423                         ASSERT_NOT_SERIALIZED(&rdata->jme_rx_serialize);
3424                 break;
3425
3426         case IFNET_SERIALIZE_RX(1):
3427                 rdata = &sc->jme_cdata.jme_rx_data[1];
3428                 if (serialized)
3429                         ASSERT_SERIALIZED(&rdata->jme_rx_serialize);
3430                 else
3431                         ASSERT_NOT_SERIALIZED(&rdata->jme_rx_serialize);
3432                 break;
3433
3434         case IFNET_SERIALIZE_RX(2):
3435                 rdata = &sc->jme_cdata.jme_rx_data[2];
3436                 if (serialized)
3437                         ASSERT_SERIALIZED(&rdata->jme_rx_serialize);
3438                 else
3439                         ASSERT_NOT_SERIALIZED(&rdata->jme_rx_serialize);
3440                 break;
3441
3442         case IFNET_SERIALIZE_RX(3):
3443                 rdata = &sc->jme_cdata.jme_rx_data[3];
3444                 if (serialized)
3445                         ASSERT_SERIALIZED(&rdata->jme_rx_serialize);
3446                 else
3447                         ASSERT_NOT_SERIALIZED(&rdata->jme_rx_serialize);
3448                 break;
3449
3450         default:
3451                 panic("%s unsupported serialize type\n", ifp->if_xname);
3452         }
3453 }
3454
3455 #endif  /* INVARIANTS */
3456
3457 static void
3458 jme_msix_try_alloc(device_t dev)
3459 {
3460         struct jme_softc *sc = device_get_softc(dev);
3461         struct jme_msix_data *msix;
3462         int error, i, r, msix_enable, msix_count;
3463
3464         msix_count = 1 + sc->jme_rx_ring_cnt;
3465         KKASSERT(msix_count <= JME_NMSIX);
3466
3467         msix_enable = device_getenv_int(dev, "msix.enable", jme_msix_enable);
3468
3469         /*
3470          * We leave the 1st MSI-X vector unused, so we
3471          * actually need msix_count + 1 MSI-X vectors.
3472          */
3473         if (!msix_enable || pci_msix_count(dev) < (msix_count + 1))
3474                 return;
3475
3476         for (i = 0; i < msix_count; ++i)
3477                 sc->jme_msix[i].jme_msix_rid = -1;
3478
3479         i = 0;
3480
3481         msix = &sc->jme_msix[i++];
3482         msix->jme_msix_cpuid = 0;               /* XXX Put TX to cpu0 */
3483         msix->jme_msix_arg = &sc->jme_cdata;
3484         msix->jme_msix_func = jme_msix_tx;
3485         msix->jme_msix_intrs = INTR_TXQ_COAL | INTR_TXQ_COAL_TO;
3486         msix->jme_msix_serialize = &sc->jme_cdata.jme_tx_serialize;
3487         ksnprintf(msix->jme_msix_desc, sizeof(msix->jme_msix_desc), "%s tx",
3488             device_get_nameunit(dev));
3489
3490         for (r = 0; r < sc->jme_rx_ring_cnt; ++r) {
3491                 struct jme_rxdata *rdata = &sc->jme_cdata.jme_rx_data[r];
3492
3493                 msix = &sc->jme_msix[i++];
3494                 msix->jme_msix_cpuid = r;       /* XXX Put RX to cpuX */
3495                 msix->jme_msix_arg = rdata;
3496                 msix->jme_msix_func = jme_msix_rx;
3497                 msix->jme_msix_intrs = rdata->jme_rx_coal | rdata->jme_rx_empty;
3498                 msix->jme_msix_serialize = &rdata->jme_rx_serialize;
3499                 ksnprintf(msix->jme_msix_desc, sizeof(msix->jme_msix_desc),
3500                     "%s rx%d", device_get_nameunit(dev), r);
3501         }
3502
3503         KKASSERT(i == msix_count);
3504
3505         error = pci_setup_msix(dev);
3506         if (error)
3507                 return;
3508
3509         /* Setup jme_msix_cnt early, so we could cleanup */
3510         sc->jme_msix_cnt = msix_count;
3511
3512         for (i = 0; i < msix_count; ++i) {
3513                 msix = &sc->jme_msix[i];
3514
3515                 msix->jme_msix_vector = i + 1;
3516                 error = pci_alloc_msix_vector(dev, msix->jme_msix_vector,
3517                     &msix->jme_msix_rid, msix->jme_msix_cpuid);
3518                 if (error)
3519                         goto back;
3520
3521                 msix->jme_msix_res = bus_alloc_resource_any(dev, SYS_RES_IRQ,
3522                     &msix->jme_msix_rid, RF_ACTIVE);
3523                 if (msix->jme_msix_res == NULL) {
3524                         error = ENOMEM;
3525                         goto back;
3526                 }
3527         }
3528
3529         for (i = 0; i < JME_INTR_CNT; ++i) {
3530                 uint32_t intr_mask = (1 << i);
3531                 int x;
3532
3533                 if ((JME_INTRS & intr_mask) == 0)
3534                         continue;
3535
3536                 for (x = 0; x < msix_count; ++x) {
3537                         msix = &sc->jme_msix[x];
3538                         if (msix->jme_msix_intrs & intr_mask) {
3539                                 int reg, shift;
3540
3541                                 reg = i / JME_MSINUM_FACTOR;
3542                                 KKASSERT(reg < JME_MSINUM_CNT);
3543
3544                                 shift = (i % JME_MSINUM_FACTOR) * 4;
3545
3546                                 sc->jme_msinum[reg] |=
3547                                     (msix->jme_msix_vector << shift);
3548
3549                                 break;
3550                         }
3551                 }
3552         }
3553
3554         if (bootverbose) {
3555                 for (i = 0; i < JME_MSINUM_CNT; ++i) {
3556                         device_printf(dev, "MSINUM%d: %#x\n", i,
3557                             sc->jme_msinum[i]);
3558                 }
3559         }
3560
3561         pci_enable_msix(dev);
3562         sc->jme_irq_type = PCI_INTR_TYPE_MSIX;
3563
3564 back:
3565         if (error)
3566                 jme_msix_free(dev);
3567 }
3568
3569 static int
3570 jme_intr_alloc(device_t dev)
3571 {
3572         struct jme_softc *sc = device_get_softc(dev);
3573         u_int irq_flags;
3574
3575         jme_msix_try_alloc(dev);
3576
3577         if (sc->jme_irq_type != PCI_INTR_TYPE_MSIX) {
3578                 sc->jme_irq_type = pci_alloc_1intr(dev, jme_msi_enable,
3579                     &sc->jme_irq_rid, &irq_flags);
3580
3581                 sc->jme_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ,
3582                     &sc->jme_irq_rid, irq_flags);
3583                 if (sc->jme_irq_res == NULL) {
3584                         device_printf(dev, "can't allocate irq\n");
3585                         return ENXIO;
3586                 }
3587         }
3588         return 0;
3589 }
3590
3591 static void
3592 jme_msix_free(device_t dev)
3593 {
3594         struct jme_softc *sc = device_get_softc(dev);
3595         int i;
3596
3597         KKASSERT(sc->jme_msix_cnt > 1);
3598
3599         for (i = 0; i < sc->jme_msix_cnt; ++i) {
3600                 struct jme_msix_data *msix = &sc->jme_msix[i];
3601
3602                 if (msix->jme_msix_res != NULL) {
3603                         bus_release_resource(dev, SYS_RES_IRQ,
3604                             msix->jme_msix_rid, msix->jme_msix_res);
3605                         msix->jme_msix_res = NULL;
3606                 }
3607                 if (msix->jme_msix_rid >= 0) {
3608                         pci_release_msix_vector(dev, msix->jme_msix_rid);
3609                         msix->jme_msix_rid = -1;
3610                 }
3611         }
3612         pci_teardown_msix(dev);
3613 }
3614
3615 static void
3616 jme_intr_free(device_t dev)
3617 {
3618         struct jme_softc *sc = device_get_softc(dev);
3619
3620         if (sc->jme_irq_type != PCI_INTR_TYPE_MSIX) {
3621                 if (sc->jme_irq_res != NULL) {
3622                         bus_release_resource(dev, SYS_RES_IRQ, sc->jme_irq_rid,
3623                                              sc->jme_irq_res);
3624                 }
3625                 if (sc->jme_irq_type == PCI_INTR_TYPE_MSI)
3626                         pci_release_msi(dev);
3627         } else {
3628                 jme_msix_free(dev);
3629         }
3630 }
3631
3632 static void
3633 jme_msix_tx(void *xcd)
3634 {
3635         struct jme_chain_data *cd = xcd;
3636         struct jme_softc *sc = cd->jme_sc;
3637         struct ifnet *ifp = &sc->arpcom.ac_if;
3638
3639         ASSERT_SERIALIZED(&cd->jme_tx_serialize);
3640
3641         CSR_WRITE_4(sc, JME_INTR_STATUS,
3642             INTR_TXQ_COAL | INTR_TXQ_COAL_TO | INTR_TXQ_COMP);
3643
3644         if (ifp->if_flags & IFF_RUNNING) {
3645                 jme_txeof(sc);
3646                 if (!ifq_is_empty(&ifp->if_snd))
3647                         if_devstart(ifp);
3648         }
3649 }
3650
3651 static void
3652 jme_msix_rx(void *xrdata)
3653 {
3654         struct jme_rxdata *rdata = xrdata;
3655         struct jme_softc *sc = rdata->jme_sc;
3656         struct ifnet *ifp = &sc->arpcom.ac_if;
3657         uint32_t status;
3658
3659         ASSERT_SERIALIZED(&rdata->jme_rx_serialize);
3660
3661         status = CSR_READ_4(sc, JME_INTR_STATUS);
3662         status &= (rdata->jme_rx_coal | rdata->jme_rx_empty);
3663
3664         if (status & rdata->jme_rx_coal) {
3665                 status |= (rdata->jme_rx_coal | rdata->jme_rx_comp);
3666                 CSR_WRITE_4(sc, JME_INTR_STATUS, status);
3667         }
3668
3669         if (ifp->if_flags & IFF_RUNNING) {
3670                 if (status & rdata->jme_rx_coal)
3671                         jme_rxeof(sc, rdata->jme_rx_idx, -1);
3672
3673                 if (status & rdata->jme_rx_empty) {
3674                         CSR_WRITE_4(sc, JME_RXCSR, sc->jme_rxcsr |
3675                             RXCSR_RX_ENB | RXCSR_RXQ_START);
3676                 }
3677         }
3678 }
3679
3680 static void
3681 jme_set_msinum(struct jme_softc *sc)
3682 {
3683         int i;
3684
3685         for (i = 0; i < JME_MSINUM_CNT; ++i)
3686                 CSR_WRITE_4(sc, JME_MSINUM(i), sc->jme_msinum[i]);
3687 }
3688
3689 static int
3690 jme_intr_setup(device_t dev)
3691 {
3692         struct jme_softc *sc = device_get_softc(dev);
3693         struct ifnet *ifp = &sc->arpcom.ac_if;
3694         int error;
3695
3696         if (sc->jme_irq_type == PCI_INTR_TYPE_MSIX)
3697                 return jme_msix_setup(dev);
3698
3699         error = bus_setup_intr(dev, sc->jme_irq_res, INTR_MPSAFE,
3700             jme_intr, sc, &sc->jme_irq_handle, &sc->jme_serialize);
3701         if (error) {
3702                 device_printf(dev, "could not set up interrupt handler.\n");
3703                 return error;
3704         }
3705
3706         ifp->if_cpuid = rman_get_cpuid(sc->jme_irq_res);
3707         KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus);
3708         return 0;
3709 }
3710
3711 static void
3712 jme_intr_teardown(device_t dev)
3713 {
3714         struct jme_softc *sc = device_get_softc(dev);
3715
3716         if (sc->jme_irq_type == PCI_INTR_TYPE_MSIX)
3717                 jme_msix_teardown(dev, sc->jme_msix_cnt);
3718         else
3719                 bus_teardown_intr(dev, sc->jme_irq_res, sc->jme_irq_handle);
3720 }
3721
3722 static int
3723 jme_msix_setup(device_t dev)
3724 {
3725         struct jme_softc *sc = device_get_softc(dev);
3726         struct ifnet *ifp = &sc->arpcom.ac_if;
3727         int x;
3728
3729         for (x = 0; x < sc->jme_msix_cnt; ++x) {
3730                 struct jme_msix_data *msix = &sc->jme_msix[x];
3731                 int error;
3732
3733                 error = bus_setup_intr_descr(dev, msix->jme_msix_res,
3734                     INTR_MPSAFE, msix->jme_msix_func, msix->jme_msix_arg,
3735                     &msix->jme_msix_handle, msix->jme_msix_serialize,
3736                     msix->jme_msix_desc);
3737                 if (error) {
3738                         device_printf(dev, "could not set up %s "
3739                             "interrupt handler.\n", msix->jme_msix_desc);
3740                         jme_msix_teardown(dev, x);
3741                         return error;
3742                 }
3743         }
3744         ifp->if_cpuid = 0; /* XXX */
3745         return 0;
3746 }
3747
3748 static void
3749 jme_msix_teardown(device_t dev, int msix_count)
3750 {
3751         struct jme_softc *sc = device_get_softc(dev);
3752         int x;
3753
3754         for (x = 0; x < msix_count; ++x) {
3755                 struct jme_msix_data *msix = &sc->jme_msix[x];
3756
3757                 bus_teardown_intr(dev, msix->jme_msix_res,
3758                     msix->jme_msix_handle);
3759         }
3760 }