sys/dev/drm/i915/intel_ringbuffer.c

   1 /*
   2  * Copyright © 2008-2010 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *    Zou Nan hai <nanhai.zou@intel.com>
  26  *    Xiang Hai hao<haihao.xiang@intel.com>
  27  *
  28  */
  29
  30 #include <drm/drmP.h>
  31 #include <drm/i915_drm.h>
  32 #include "i915_drv.h"
  33 #include "intel_drv.h"
  34 #include "intel_ringbuffer.h"
  35
  36 /*
  37  * 965+ support PIPE_CONTROL commands, which provide finer grained control
  38  * over cache flushing.
  39  */
  40 struct pipe_control {
  41         struct drm_i915_gem_object *obj;
  42         volatile u32 *cpu_page;
  43         u32 gtt_offset;
  44 };
  45
  46 static inline int ring_space(struct intel_ring_buffer *ring)
  47 {
  48         int space = (ring->head & HEAD_ADDR) - (ring->tail + I915_RING_FREE_SPACE);
  49         if (space < 0)
  50                 space += ring->size;
  51         return space;
  52 }
  53
  54 static int
  55 gen2_render_ring_flush(struct intel_ring_buffer *ring,
  56                        u32      invalidate_domains,
  57                        u32      flush_domains)
  58 {
  59         u32 cmd;
  60         int ret;
  61
  62         cmd = MI_FLUSH;
  63         if (((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER) == 0)
  64                 cmd |= MI_NO_WRITE_FLUSH;
  65
  66         if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
  67                 cmd |= MI_READ_FLUSH;
  68
  69         ret = intel_ring_begin(ring, 2);
  70         if (ret)
  71                 return ret;
  72
  73         intel_ring_emit(ring, cmd);
  74         intel_ring_emit(ring, MI_NOOP);
  75         intel_ring_advance(ring);
  76
  77         return 0;
  78 }
  79
  80 static int
  81 gen4_render_ring_flush(struct intel_ring_buffer *ring,
  82                        u32      invalidate_domains,
  83                        u32      flush_domains)
  84 {
  85         struct drm_device *dev = ring->dev;
  86         u32 cmd;
  87         int ret;
  88
  89         /*
  90          * read/write caches:
  91          *
  92          * I915_GEM_DOMAIN_RENDER is always invalidated, but is
  93          * only flushed if MI_NO_WRITE_FLUSH is unset.  On 965, it is
  94          * also flushed at 2d versus 3d pipeline switches.
  95          *
  96          * read-only caches:
  97          *
  98          * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
  99          * MI_READ_FLUSH is set, and is always flushed on 965.
 100          *
 101          * I915_GEM_DOMAIN_COMMAND may not exist?
 102          *
 103          * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
 104          * invalidated when MI_EXE_FLUSH is set.
 105          *
 106          * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
 107          * invalidated with every MI_FLUSH.
 108          *
 109          * TLBs:
 110          *
 111          * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
 112          * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
 113          * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
 114          * are flushed at any MI_FLUSH.
 115          */
 116
 117         cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
 118         if ((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER)
 119                 cmd &= ~MI_NO_WRITE_FLUSH;
 120         if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
 121                 cmd |= MI_EXE_FLUSH;
 122
 123         if (invalidate_domains & I915_GEM_DOMAIN_COMMAND &&
 124             (IS_G4X(dev) || IS_GEN5(dev)))
 125                 cmd |= MI_INVALIDATE_ISP;
 126
 127         ret = intel_ring_begin(ring, 2);
 128         if (ret)
 129                 return ret;
 130
 131         intel_ring_emit(ring, cmd);
 132         intel_ring_emit(ring, MI_NOOP);
 133         intel_ring_advance(ring);
 134
 135         return 0;
 136 }
 137
 138 /**
 139  * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
 140  * implementing two workarounds on gen6.  From section 1.4.7.1
 141  * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1:
 142  *
 143  * [DevSNB-C+{W/A}] Before any depth stall flush (including those
 144  * produced by non-pipelined state commands), software needs to first
 145  * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
 146  * 0.
 147  *
 148  * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
 149  * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
 150  *
 151  * And the workaround for these two requires this workaround first:
 152  *
 153  * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
 154  * BEFORE the pipe-control with a post-sync op and no write-cache
 155  * flushes.
 156  *
 157  * And this last workaround is tricky because of the requirements on
 158  * that bit.  From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM
 159  * volume 2 part 1:
 160  *
 161  *     "1 of the following must also be set:
 162  *      - Render Target Cache Flush Enable ([12] of DW1)
 163  *      - Depth Cache Flush Enable ([0] of DW1)
 164  *      - Stall at Pixel Scoreboard ([1] of DW1)
 165  *      - Depth Stall ([13] of DW1)
 166  *      - Post-Sync Operation ([13] of DW1)
 167  *      - Notify Enable ([8] of DW1)"
 168  *
 169  * The cache flushes require the workaround flush that triggered this
 170  * one, so we can't use it.  Depth stall would trigger the same.
 171  * Post-sync nonzero is what triggered this second workaround, so we
 172  * can't use that one either.  Notify enable is IRQs, which aren't
 173  * really our business.  That leaves only stall at scoreboard.
 174  */
 175 static int
 176 intel_emit_post_sync_nonzero_flush(struct intel_ring_buffer *ring)
 177 {
 178         struct pipe_control *pc = ring->private;
 179         u32 scratch_addr = pc->gtt_offset + 128;
 180         int ret;
 181
 182
 183         ret = intel_ring_begin(ring, 6);
 184         if (ret)
 185                 return ret;
 186
 187         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
 188         intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
 189                         PIPE_CONTROL_STALL_AT_SCOREBOARD);
 190         intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
 191         intel_ring_emit(ring, 0); /* low dword */
 192         intel_ring_emit(ring, 0); /* high dword */
 193         intel_ring_emit(ring, MI_NOOP);
 194         intel_ring_advance(ring);
 195
 196         ret = intel_ring_begin(ring, 6);
 197         if (ret)
 198                 return ret;
 199
 200         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
 201         intel_ring_emit(ring, PIPE_CONTROL_QW_WRITE);
 202         intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
 203         intel_ring_emit(ring, 0);
 204         intel_ring_emit(ring, 0);
 205         intel_ring_emit(ring, MI_NOOP);
 206         intel_ring_advance(ring);
 207
 208         return 0;
 209 }
 210
 211 static int
 212 gen6_render_ring_flush(struct intel_ring_buffer *ring,
 213                          u32 invalidate_domains, u32 flush_domains)
 214 {
 215         u32 flags = 0;
 216         struct pipe_control *pc = ring->private;
 217         u32 scratch_addr = pc->gtt_offset + 128;
 218         int ret;
 219
 220         /* Force SNB workarounds for PIPE_CONTROL flushes */
 221         ret = intel_emit_post_sync_nonzero_flush(ring);
 222         if (ret)
 223                 return ret;
 224
 225         /* Just flush everything.  Experiments have shown that reducing the
 226          * number of bits based on the write domains has little performance
 227          * impact.
 228          */
 229         if (flush_domains) {
 230                 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
 231                 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
 232                 /*
 233                  * Ensure that any following seqno writes only happen
 234                  * when the render cache is indeed flushed.
 235                  */
 236                 flags |= PIPE_CONTROL_CS_STALL;
 237         }
 238         if (invalidate_domains) {
 239                 flags |= PIPE_CONTROL_TLB_INVALIDATE;
 240                 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
 241                 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
 242                 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
 243                 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
 244                 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
 245                 /*
 246                  * TLB invalidate requires a post-sync write.
 247                  */
 248                 flags |= PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_CS_STALL;
 249         }
 250
 251         ret = intel_ring_begin(ring, 4);
 252         if (ret)
 253                 return ret;
 254
 255         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
 256         intel_ring_emit(ring, flags);
 257         intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT);
 258         intel_ring_emit(ring, 0);
 259         intel_ring_advance(ring);
 260
 261         return 0;
 262 }
 263
 264 static int
 265 gen7_render_ring_cs_stall_wa(struct intel_ring_buffer *ring)
 266 {
 267         int ret;
 268
 269         ret = intel_ring_begin(ring, 4);
 270         if (ret)
 271                 return ret;
 272
 273         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
 274         intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
 275                               PIPE_CONTROL_STALL_AT_SCOREBOARD);
 276         intel_ring_emit(ring, 0);
 277         intel_ring_emit(ring, 0);
 278         intel_ring_advance(ring);
 279
 280         return 0;
 281 }
 282
 283 static int
 284 gen7_render_ring_flush(struct intel_ring_buffer *ring,
 285                        u32 invalidate_domains, u32 flush_domains)
 286 {
 287         u32 flags = 0;
 288         struct pipe_control *pc = ring->private;
 289         u32 scratch_addr = pc->gtt_offset + 128;
 290         int ret;
 291
 292         /*
 293          * Ensure that any following seqno writes only happen when the render
 294          * cache is indeed flushed.
 295          *
 296          * Workaround: 4th PIPE_CONTROL command (except the ones with only
 297          * read-cache invalidate bits set) must have the CS_STALL bit set. We
 298          * don't try to be clever and just set it unconditionally.
 299          */
 300         flags |= PIPE_CONTROL_CS_STALL;
 301
 302         /* Just flush everything.  Experiments have shown that reducing the
 303          * number of bits based on the write domains has little performance
 304          * impact.
 305          */
 306         if (flush_domains) {
 307                 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
 308                 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
 309         }
 310         if (invalidate_domains) {
 311                 flags |= PIPE_CONTROL_TLB_INVALIDATE;
 312                 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
 313                 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
 314                 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
 315                 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
 316                 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
 317                 /*
 318                  * TLB invalidate requires a post-sync write.
 319                  */
 320                 flags |= PIPE_CONTROL_QW_WRITE;
 321
 322                 /* Workaround: we must issue a pipe_control with CS-stall bit
 323                  * set before a pipe_control command that has the state cache
 324                  * invalidate bit set. */
 325                 gen7_render_ring_cs_stall_wa(ring);
 326         }
 327
 328         ret = intel_ring_begin(ring, 4);
 329         if (ret)
 330                 return ret;
 331
 332         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
 333         intel_ring_emit(ring, flags);
 334         intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT);
 335         intel_ring_emit(ring, 0);
 336         intel_ring_advance(ring);
 337
 338         return 0;
 339 }
 340
 341 static void ring_write_tail(struct intel_ring_buffer *ring,
 342                             u32 value)
 343 {
 344         drm_i915_private_t *dev_priv = ring->dev->dev_private;
 345         I915_WRITE_TAIL(ring, value);
 346 }
 347
 348 u32 intel_ring_get_active_head(struct intel_ring_buffer *ring)
 349 {
 350         drm_i915_private_t *dev_priv = ring->dev->dev_private;
 351         u32 acthd_reg = INTEL_INFO(ring->dev)->gen >= 4 ?
 352                         RING_ACTHD(ring->mmio_base) : ACTHD;
 353
 354         return I915_READ(acthd_reg);
 355 }
 356
 357 static int init_ring_common(struct intel_ring_buffer *ring)
 358 {
 359         struct drm_device *dev = ring->dev;
 360         drm_i915_private_t *dev_priv = dev->dev_private;
 361         struct drm_i915_gem_object *obj = ring->obj;
 362         int ret = 0;
 363         u32 head;
 364
 365         if (HAS_FORCE_WAKE(dev))
 366                 gen6_gt_force_wake_get(dev_priv);
 367
 368         /* Stop the ring if it's running. */
 369         I915_WRITE_CTL(ring, 0);
 370         I915_WRITE_HEAD(ring, 0);
 371         ring->write_tail(ring, 0);
 372
 373         head = I915_READ_HEAD(ring) & HEAD_ADDR;
 374
 375         /* G45 ring initialization fails to reset head to zero */
 376         if (head != 0) {
 377                 DRM_DEBUG_KMS("%s head not reset to zero "
 378                               "ctl %08x head %08x tail %08x start %08x\n",
 379                               ring->name,
 380                               I915_READ_CTL(ring),
 381                               I915_READ_HEAD(ring),
 382                               I915_READ_TAIL(ring),
 383                               I915_READ_START(ring));
 384
 385                 I915_WRITE_HEAD(ring, 0);
 386
 387                 if (I915_READ_HEAD(ring) & HEAD_ADDR) {
 388                         DRM_ERROR("failed to set %s head to zero "
 389                                   "ctl %08x head %08x tail %08x start %08x\n",
 390                                   ring->name,
 391                                   I915_READ_CTL(ring),
 392                                   I915_READ_HEAD(ring),
 393                                   I915_READ_TAIL(ring),
 394                                   I915_READ_START(ring));
 395                 }
 396         }
 397
 398         /* Initialize the ring. This must happen _after_ we've cleared the ring
 399          * registers with the above sequence (the readback of the HEAD registers
 400          * also enforces ordering), otherwise the hw might lose the new ring
 401          * register values. */
 402         I915_WRITE_START(ring, obj->gtt_offset);
 403         I915_WRITE_CTL(ring,
 404                         ((ring->size - PAGE_SIZE) & RING_NR_PAGES)
 405                         | RING_VALID);
 406
 407         /* If the head is still not zero, the ring is dead */
 408         if (wait_for((I915_READ_CTL(ring) & RING_VALID) != 0 &&
 409                      I915_READ_START(ring) == obj->gtt_offset &&
 410                      (I915_READ_HEAD(ring) & HEAD_ADDR) == 0, 50)) {
 411                 DRM_ERROR("%s initialization failed "
 412                                 "ctl %08x head %08x tail %08x start %08x\n",
 413                                 ring->name,
 414                                 I915_READ_CTL(ring),
 415                                 I915_READ_HEAD(ring),
 416                                 I915_READ_TAIL(ring),
 417                                 I915_READ_START(ring));
 418                 ret = -EIO;
 419                 goto out;
 420         }
 421
 422         if (!drm_core_check_feature(ring->dev, DRIVER_MODESET))
 423                 i915_kernel_lost_context(ring->dev);
 424         else {
 425                 ring->head = I915_READ_HEAD(ring);
 426                 ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
 427                 ring->space = ring_space(ring);
 428                 ring->last_retired_head = -1;
 429         }
 430
 431 out:
 432         if (HAS_FORCE_WAKE(dev))
 433                 gen6_gt_force_wake_put(dev_priv);
 434
 435         return ret;
 436 }
 437
 438 static int
 439 init_pipe_control(struct intel_ring_buffer *ring)
 440 {
 441         struct pipe_control *pc;
 442         struct drm_i915_gem_object *obj;
 443         int ret;
 444
 445         if (ring->private)
 446                 return 0;
 447
 448         pc = kmalloc(sizeof(*pc), M_DRM, M_WAITOK);
 449         if (!pc)
 450                 return -ENOMEM;
 451
 452         obj = i915_gem_alloc_object(ring->dev, 4096);
 453         if (obj == NULL) {
 454                 DRM_ERROR("Failed to allocate seqno page\n");
 455                 ret = -ENOMEM;
 456                 goto err;
 457         }
 458
 459         i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
 460
 461         ret = i915_gem_object_pin(obj, 4096, true, false);
 462         if (ret)
 463                 goto err_unref;
 464
 465         pc->gtt_offset = obj->gtt_offset;
 466         pc->cpu_page = (uint32_t *)kmem_alloc_nofault(&kernel_map, PAGE_SIZE, PAGE_SIZE);
 467         if (pc->cpu_page == NULL)
 468                 goto err_unpin;
 469         pmap_qenter((uintptr_t)pc->cpu_page, &obj->pages[0], 1);
 470         pmap_invalidate_cache_range((vm_offset_t)pc->cpu_page,
 471             (vm_offset_t)pc->cpu_page + PAGE_SIZE);
 472
 473         pc->obj = obj;
 474         ring->private = pc;
 475         return 0;
 476
 477 err_unpin:
 478         i915_gem_object_unpin(obj);
 479 err_unref:
 480         drm_gem_object_unreference(&obj->base);
 481 err:
 482         kfree(pc, M_DRM);
 483         return ret;
 484 }
 485
 486 static void
 487 cleanup_pipe_control(struct intel_ring_buffer *ring)
 488 {
 489         struct pipe_control *pc = ring->private;
 490         struct drm_i915_gem_object *obj;
 491
 492         if (!ring->private)
 493                 return;
 494
 495         obj = pc->obj;
 496         pmap_qremove((vm_offset_t)pc->cpu_page, 1);
 497         kmem_free(&kernel_map, (uintptr_t)pc->cpu_page, PAGE_SIZE);
 498         i915_gem_object_unpin(obj);
 499         drm_gem_object_unreference(&obj->base);
 500
 501         kfree(pc, M_DRM);
 502         ring->private = NULL;
 503 }
 504
 505 static int init_render_ring(struct intel_ring_buffer *ring)
 506 {
 507         struct drm_device *dev = ring->dev;
 508         struct drm_i915_private *dev_priv = dev->dev_private;
 509         int ret = init_ring_common(ring);
 510
 511         if (INTEL_INFO(dev)->gen > 3)
 512                 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH));
 513
 514         /* We need to disable the AsyncFlip performance optimisations in order
 515          * to use MI_WAIT_FOR_EVENT within the CS. It should already be
 516          * programmed to '1' on all products.
 517          */
 518         if (INTEL_INFO(dev)->gen >= 6)
 519                 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));
 520
 521         /* Required for the hardware to program scanline values for waiting */
 522         if (INTEL_INFO(dev)->gen == 6)
 523                 I915_WRITE(GFX_MODE,
 524                            _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_ALWAYS));
 525
 526         if (IS_GEN7(dev))
 527                 I915_WRITE(GFX_MODE_GEN7,
 528                            _MASKED_BIT_DISABLE(GFX_TLB_INVALIDATE_ALWAYS) |
 529                            _MASKED_BIT_ENABLE(GFX_REPLAY_MODE));
 530
 531         if (INTEL_INFO(dev)->gen >= 5) {
 532                 ret = init_pipe_control(ring);
 533                 if (ret)
 534                         return ret;
 535         }
 536
 537         if (IS_GEN6(dev)) {
 538                 /* From the Sandybridge PRM, volume 1 part 3, page 24:
 539                  * "If this bit is set, STCunit will have LRA as replacement
 540                  *  policy. [...] This bit must be reset.  LRA replacement
 541                  *  policy is not supported."
 542                  */
 543                 I915_WRITE(CACHE_MODE_0,
 544                            _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
 545
 546                 /* This is not explicitly set for GEN6, so read the register.
 547                  * see intel_ring_mi_set_context() for why we care.
 548                  * TODO: consider explicitly setting the bit for GEN5
 549                  */
 550                 ring->itlb_before_ctx_switch =
 551                         !!(I915_READ(GFX_MODE) & GFX_TLB_INVALIDATE_ALWAYS);
 552         }
 553
 554         if (INTEL_INFO(dev)->gen >= 6)
 555                 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
 556
 557         if (HAS_L3_GPU_CACHE(dev))
 558                 I915_WRITE_IMR(ring, ~GEN6_RENDER_L3_PARITY_ERROR);
 559
 560         return ret;
 561 }
 562
 563 static void render_ring_cleanup(struct intel_ring_buffer *ring)
 564 {
 565         struct drm_device *dev = ring->dev;
 566
 567         if (!ring->private)
 568                 return;
 569
 570         if (HAS_BROKEN_CS_TLB(dev))
 571                 drm_gem_object_unreference(to_gem_object(ring->private));
 572
 573         cleanup_pipe_control(ring);
 574 }
 575
 576 static void
 577 update_mboxes(struct intel_ring_buffer *ring,
 578               u32 mmio_offset)
 579 {
 580         intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
 581         intel_ring_emit(ring, mmio_offset);
 582         intel_ring_emit(ring, ring->outstanding_lazy_request);
 583 }
 584
 585 /**
 586  * gen6_add_request - Update the semaphore mailbox registers
 587  *
 588  * @ring - ring that is adding a request
 589  * @seqno - return seqno stuck into the ring
 590  *
 591  * Update the mailbox registers in the *other* rings with the current seqno.
 592  * This acts like a signal in the canonical semaphore.
 593  */
 594 static int
 595 gen6_add_request(struct intel_ring_buffer *ring)
 596 {
 597         u32 mbox1_reg;
 598         u32 mbox2_reg;
 599         int ret;
 600
 601         ret = intel_ring_begin(ring, 10);
 602         if (ret)
 603                 return ret;
 604
 605         mbox1_reg = ring->signal_mbox[0];
 606         mbox2_reg = ring->signal_mbox[1];
 607
 608         update_mboxes(ring, mbox1_reg);
 609         update_mboxes(ring, mbox2_reg);
 610         intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
 611         intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
 612         intel_ring_emit(ring, ring->outstanding_lazy_request);
 613         intel_ring_emit(ring, MI_USER_INTERRUPT);
 614         intel_ring_advance(ring);
 615
 616         return 0;
 617 }
 618
 619 /**
 620  * intel_ring_sync - sync the waiter to the signaller on seqno
 621  *
 622  * @waiter - ring that is waiting
 623  * @signaller - ring which has, or will signal
 624  * @seqno - seqno which the waiter will block on
 625  */
 626 static int
 627 gen6_ring_sync(struct intel_ring_buffer *waiter,
 628                struct intel_ring_buffer *signaller,
 629                u32 seqno)
 630 {
 631         int ret;
 632         u32 dw1 = MI_SEMAPHORE_MBOX |
 633                   MI_SEMAPHORE_COMPARE |
 634                   MI_SEMAPHORE_REGISTER;
 635
 636         /* Throughout all of the GEM code, seqno passed implies our current
 637          * seqno is >= the last seqno executed. However for hardware the
 638          * comparison is strictly greater than.
 639          */
 640         seqno -= 1;
 641
 642         WARN_ON(signaller->semaphore_register[waiter->id] ==
 643                 MI_SEMAPHORE_SYNC_INVALID);
 644
 645         ret = intel_ring_begin(waiter, 4);
 646         if (ret)
 647                 return ret;
 648
 649         intel_ring_emit(waiter,
 650                         dw1 | signaller->semaphore_register[waiter->id]);
 651         intel_ring_emit(waiter, seqno);
 652         intel_ring_emit(waiter, 0);
 653         intel_ring_emit(waiter, MI_NOOP);
 654         intel_ring_advance(waiter);
 655
 656         return 0;
 657 }
 658
 659 #define PIPE_CONTROL_FLUSH(ring__, addr__)                                      \
 660 do {                                                                    \
 661         intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |                \
 662                  PIPE_CONTROL_DEPTH_STALL);                             \
 663         intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT);                    \
 664         intel_ring_emit(ring__, 0);                                                     \
 665         intel_ring_emit(ring__, 0);                                                     \
 666 } while (0)
 667
 668 static int
 669 pc_render_add_request(struct intel_ring_buffer *ring)
 670 {
 671         struct pipe_control *pc = ring->private;
 672         u32 scratch_addr = pc->gtt_offset + 128;
 673         int ret;
 674
 675         /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently
 676          * incoherent with writes to memory, i.e. completely fubar,
 677          * so we need to use PIPE_NOTIFY instead.
 678          *
 679          * However, we also need to workaround the qword write
 680          * incoherence by flushing the 6 PIPE_NOTIFY buffers out to
 681          * memory before requesting an interrupt.
 682          */
 683         ret = intel_ring_begin(ring, 32);
 684         if (ret)
 685                 return ret;
 686
 687         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
 688                         PIPE_CONTROL_WRITE_FLUSH |
 689                         PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE);
 690         intel_ring_emit(ring, pc->gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
 691         intel_ring_emit(ring, ring->outstanding_lazy_request);
 692         intel_ring_emit(ring, 0);
 693         PIPE_CONTROL_FLUSH(ring, scratch_addr);
 694         scratch_addr += 128; /* write to separate cachelines */
 695         PIPE_CONTROL_FLUSH(ring, scratch_addr);
 696         scratch_addr += 128;
 697         PIPE_CONTROL_FLUSH(ring, scratch_addr);
 698         scratch_addr += 128;
 699         PIPE_CONTROL_FLUSH(ring, scratch_addr);
 700         scratch_addr += 128;
 701         PIPE_CONTROL_FLUSH(ring, scratch_addr);
 702         scratch_addr += 128;
 703         PIPE_CONTROL_FLUSH(ring, scratch_addr);
 704
 705         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
 706                         PIPE_CONTROL_WRITE_FLUSH |
 707                         PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
 708                         PIPE_CONTROL_NOTIFY);
 709         intel_ring_emit(ring, pc->gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
 710         intel_ring_emit(ring, ring->outstanding_lazy_request);
 711         intel_ring_emit(ring, 0);
 712         intel_ring_advance(ring);
 713
 714         return 0;
 715 }
 716
 717 static u32
 718 gen6_ring_get_seqno(struct intel_ring_buffer *ring, bool lazy_coherency)
 719 {
 720         /* Workaround to force correct ordering between irq and seqno writes on
 721          * ivb (and maybe also on snb) by reading from a CS register (like
 722          * ACTHD) before reading the status page. */
 723         if (!lazy_coherency)
 724                 intel_ring_get_active_head(ring);
 725         return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
 726 }
 727
 728 static u32
 729 ring_get_seqno(struct intel_ring_buffer *ring, bool lazy_coherency)
 730 {
 731         return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
 732 }
 733
 734 static u32
 735 pc_render_get_seqno(struct intel_ring_buffer *ring, bool lazy_coherency)
 736 {
 737         struct pipe_control *pc = ring->private;
 738         return pc->cpu_page[0];
 739 }
 740
 741 static bool
 742 gen5_ring_get_irq(struct intel_ring_buffer *ring)
 743 {
 744         struct drm_device *dev = ring->dev;
 745         drm_i915_private_t *dev_priv = dev->dev_private;
 746
 747         if (!dev->irq_enabled)
 748                 return false;
 749
 750         lockmgr(&dev_priv->irq_lock, LK_EXCLUSIVE);
 751         if (ring->irq_refcount++ == 0) {
 752                 dev_priv->gt_irq_mask &= ~ring->irq_enable_mask;
 753                 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
 754                 POSTING_READ(GTIMR);
 755         }
 756         lockmgr(&dev_priv->irq_lock, LK_RELEASE);
 757
 758         return true;
 759 }
 760
 761 static void
 762 gen5_ring_put_irq(struct intel_ring_buffer *ring)
 763 {
 764         struct drm_device *dev = ring->dev;
 765         drm_i915_private_t *dev_priv = dev->dev_private;
 766
 767         lockmgr(&dev_priv->irq_lock, LK_EXCLUSIVE);
 768         if (--ring->irq_refcount == 0) {
 769                 dev_priv->gt_irq_mask |= ring->irq_enable_mask;
 770                 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
 771                 POSTING_READ(GTIMR);
 772         }
 773         lockmgr(&dev_priv->irq_lock, LK_RELEASE);
 774 }
 775
 776 static bool
 777 i9xx_ring_get_irq(struct intel_ring_buffer *ring)
 778 {
 779         struct drm_device *dev = ring->dev;
 780         drm_i915_private_t *dev_priv = dev->dev_private;
 781
 782         if (!dev->irq_enabled)
 783                 return false;
 784
 785         lockmgr(&dev_priv->irq_lock, LK_EXCLUSIVE);
 786         if (ring->irq_refcount++ == 0) {
 787                 dev_priv->irq_mask &= ~ring->irq_enable_mask;
 788                 I915_WRITE(IMR, dev_priv->irq_mask);
 789                 POSTING_READ(IMR);
 790         }
 791         lockmgr(&dev_priv->irq_lock, LK_RELEASE);
 792
 793         return true;
 794 }
 795
 796 static void
 797 i9xx_ring_put_irq(struct intel_ring_buffer *ring)
 798 {
 799         struct drm_device *dev = ring->dev;
 800         drm_i915_private_t *dev_priv = dev->dev_private;
 801
 802         lockmgr(&dev_priv->irq_lock, LK_EXCLUSIVE);
 803         if (--ring->irq_refcount == 0) {
 804                 dev_priv->irq_mask |= ring->irq_enable_mask;
 805                 I915_WRITE(IMR, dev_priv->irq_mask);
 806                 POSTING_READ(IMR);
 807         }
 808         lockmgr(&dev_priv->irq_lock, LK_RELEASE);
 809 }
 810
 811 static bool
 812 i8xx_ring_get_irq(struct intel_ring_buffer *ring)
 813 {
 814         struct drm_device *dev = ring->dev;
 815         drm_i915_private_t *dev_priv = dev->dev_private;
 816
 817         if (!dev->irq_enabled)
 818                 return false;
 819
 820         lockmgr(&dev_priv->irq_lock, LK_EXCLUSIVE);
 821         if (ring->irq_refcount++ == 0) {
 822                 dev_priv->irq_mask &= ~ring->irq_enable_mask;
 823                 I915_WRITE16(IMR, dev_priv->irq_mask);
 824                 POSTING_READ16(IMR);
 825         }
 826         lockmgr(&dev_priv->irq_lock, LK_RELEASE);
 827
 828         return true;
 829 }
 830
 831 static void
 832 i8xx_ring_put_irq(struct intel_ring_buffer *ring)
 833 {
 834         struct drm_device *dev = ring->dev;
 835         drm_i915_private_t *dev_priv = dev->dev_private;
 836
 837         lockmgr(&dev_priv->irq_lock, LK_EXCLUSIVE);
 838         if (--ring->irq_refcount == 0) {
 839                 dev_priv->irq_mask |= ring->irq_enable_mask;
 840                 I915_WRITE16(IMR, dev_priv->irq_mask);
 841                 POSTING_READ16(IMR);
 842         }
 843         lockmgr(&dev_priv->irq_lock, LK_RELEASE);
 844 }
 845
 846 void intel_ring_setup_status_page(struct intel_ring_buffer *ring)
 847 {
 848         struct drm_device *dev = ring->dev;
 849         drm_i915_private_t *dev_priv = ring->dev->dev_private;
 850         u32 mmio = 0;
 851
 852         /* The ring status page addresses are no longer next to the rest of
 853          * the ring registers as of gen7.
 854          */
 855         if (IS_GEN7(dev)) {
 856                 switch (ring->id) {
 857                 case RCS:
 858                         mmio = RENDER_HWS_PGA_GEN7;
 859                         break;
 860                 case BCS:
 861                         mmio = BLT_HWS_PGA_GEN7;
 862                         break;
 863                 case VCS:
 864                         mmio = BSD_HWS_PGA_GEN7;
 865                         break;
 866                 }
 867         } else if (IS_GEN6(ring->dev)) {
 868                 mmio = RING_HWS_PGA_GEN6(ring->mmio_base);
 869         } else {
 870                 mmio = RING_HWS_PGA(ring->mmio_base);
 871         }
 872
 873         I915_WRITE(mmio, (u32)ring->status_page.gfx_addr);
 874         POSTING_READ(mmio);
 875 }
 876
 877 static int
 878 bsd_ring_flush(struct intel_ring_buffer *ring,
 879                u32     invalidate_domains,
 880                u32     flush_domains)
 881 {
 882         int ret;
 883
 884         ret = intel_ring_begin(ring, 2);
 885         if (ret)
 886                 return ret;
 887
 888         intel_ring_emit(ring, MI_FLUSH);
 889         intel_ring_emit(ring, MI_NOOP);
 890         intel_ring_advance(ring);
 891         return 0;
 892 }
 893
 894 static int
 895 i9xx_add_request(struct intel_ring_buffer *ring)
 896 {
 897         int ret;
 898
 899         ret = intel_ring_begin(ring, 4);
 900         if (ret)
 901                 return ret;
 902
 903         intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
 904         intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
 905         intel_ring_emit(ring, ring->outstanding_lazy_request);
 906         intel_ring_emit(ring, MI_USER_INTERRUPT);
 907         intel_ring_advance(ring);
 908
 909         return 0;
 910 }
 911
 912 static bool
 913 gen6_ring_get_irq(struct intel_ring_buffer *ring)
 914 {
 915         struct drm_device *dev = ring->dev;
 916         drm_i915_private_t *dev_priv = dev->dev_private;
 917
 918         if (!dev->irq_enabled)
 919                return false;
 920
 921         /* It looks like we need to prevent the gt from suspending while waiting
 922          * for an notifiy irq, otherwise irqs seem to get lost on at least the
 923          * blt/bsd rings on ivb. */
 924         gen6_gt_force_wake_get(dev_priv);
 925
 926         lockmgr(&dev_priv->irq_lock, LK_EXCLUSIVE);
 927         if (ring->irq_refcount++ == 0) {
 928                 if (HAS_L3_GPU_CACHE(dev) && ring->id == RCS)
 929                         I915_WRITE_IMR(ring, ~(ring->irq_enable_mask |
 930                                                 GEN6_RENDER_L3_PARITY_ERROR));
 931                 else
 932                         I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
 933                 dev_priv->gt_irq_mask &= ~ring->irq_enable_mask;
 934                 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
 935                 POSTING_READ(GTIMR);
 936         }
 937         lockmgr(&dev_priv->irq_lock, LK_RELEASE);
 938
 939         return true;
 940 }
 941
 942 static void
 943 gen6_ring_put_irq(struct intel_ring_buffer *ring)
 944 {
 945         struct drm_device *dev = ring->dev;
 946         drm_i915_private_t *dev_priv = dev->dev_private;
 947
 948         lockmgr(&dev_priv->irq_lock, LK_EXCLUSIVE);
 949         if (--ring->irq_refcount == 0) {
 950                 if (HAS_L3_GPU_CACHE(dev) && ring->id == RCS)
 951                         I915_WRITE_IMR(ring, ~GEN6_RENDER_L3_PARITY_ERROR);
 952                 else
 953                         I915_WRITE_IMR(ring, ~0);
 954                 dev_priv->gt_irq_mask |= ring->irq_enable_mask;
 955                 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
 956                 POSTING_READ(GTIMR);
 957         }
 958         lockmgr(&dev_priv->irq_lock, LK_RELEASE);
 959
 960         gen6_gt_force_wake_put(dev_priv);
 961 }
 962
 963 static int
 964 i965_dispatch_execbuffer(struct intel_ring_buffer *ring,
 965                          u32 offset, u32 length,
 966                          unsigned flags)
 967 {
 968         int ret;
 969
 970         ret = intel_ring_begin(ring, 2);
 971         if (ret)
 972                 return ret;
 973
 974         intel_ring_emit(ring,
 975                         MI_BATCH_BUFFER_START |
 976                         MI_BATCH_GTT |
 977                         (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_I965));
 978         intel_ring_emit(ring, offset);
 979         intel_ring_advance(ring);
 980
 981         return 0;
 982 }
 983
 984 /* Just userspace ABI convention to limit the wa batch bo to a resonable size */
 985 #define I830_BATCH_LIMIT (256*1024)
 986 static int
 987 i830_dispatch_execbuffer(struct intel_ring_buffer *ring,
 988                                 u32 offset, u32 len,
 989                                 unsigned flags)
 990 {
 991         int ret;
 992
 993         if (flags & I915_DISPATCH_PINNED) {
 994                 ret = intel_ring_begin(ring, 4);
 995                 if (ret)
 996                         return ret;
 997
 998                 intel_ring_emit(ring, MI_BATCH_BUFFER);
 999                 intel_ring_emit(ring, offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE));
1000                 intel_ring_emit(ring, offset + len - 8);
1001                 intel_ring_emit(ring, MI_NOOP);
1002                 intel_ring_advance(ring);
1003         } else {
1004                 struct drm_i915_gem_object *obj = ring->private;
1005                 u32 cs_offset = obj->gtt_offset;
1006
1007                 if (len > I830_BATCH_LIMIT)
1008                         return -ENOSPC;
1009
1010                 ret = intel_ring_begin(ring, 9+3);
1011                 if (ret)
1012                         return ret;
1013                 /* Blit the batch (which has now all relocs applied) to the stable batch
1014                  * scratch bo area (so that the CS never stumbles over its tlb
1015                  * invalidation bug) ... */
1016                 intel_ring_emit(ring, XY_SRC_COPY_BLT_CMD |
1017                                 XY_SRC_COPY_BLT_WRITE_ALPHA |
1018                                 XY_SRC_COPY_BLT_WRITE_RGB);
1019                 intel_ring_emit(ring, BLT_DEPTH_32 | BLT_ROP_GXCOPY | 4096);
1020                 intel_ring_emit(ring, 0);
1021                 intel_ring_emit(ring, (DIV_ROUND_UP(len, 4096) << 16) | 1024);
1022                 intel_ring_emit(ring, cs_offset);
1023                 intel_ring_emit(ring, 0);
1024                 intel_ring_emit(ring, 4096);
1025                 intel_ring_emit(ring, offset);
1026                 intel_ring_emit(ring, MI_FLUSH);
1027
1028                 /* ... and execute it. */
1029                 intel_ring_emit(ring, MI_BATCH_BUFFER);
1030                 intel_ring_emit(ring, cs_offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE));
1031                 intel_ring_emit(ring, cs_offset + len - 8);
1032                 intel_ring_advance(ring);
1033         }
1034
1035         return 0;
1036 }
1037
1038 static int
1039 i915_dispatch_execbuffer(struct intel_ring_buffer *ring,
1040                          u32 offset, u32 len,
1041                          unsigned flags)
1042 {
1043         int ret;
1044
1045         ret = intel_ring_begin(ring, 2);
1046         if (ret)
1047                 return ret;
1048
1049         intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_GTT);
1050         intel_ring_emit(ring, offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE));
1051         intel_ring_advance(ring);
1052
1053         return 0;
1054 }
1055
1056 static void cleanup_status_page(struct intel_ring_buffer *ring)
1057 {
1058         struct drm_i915_gem_object *obj;
1059
1060         obj = ring->status_page.obj;
1061         if (obj == NULL)
1062                 return;
1063
1064         pmap_qremove((vm_offset_t)ring->status_page.page_addr, 1);
1065         kmem_free(&kernel_map, (vm_offset_t)ring->status_page.page_addr,
1066             PAGE_SIZE);
1067         i915_gem_object_unpin(obj);
1068         drm_gem_object_unreference(&obj->base);
1069         ring->status_page.obj = NULL;
1070 }
1071
1072 static int init_status_page(struct intel_ring_buffer *ring)
1073 {
1074         struct drm_device *dev = ring->dev;
1075         struct drm_i915_gem_object *obj;
1076         int ret;
1077
1078         obj = i915_gem_alloc_object(dev, 4096);
1079         if (obj == NULL) {
1080                 DRM_ERROR("Failed to allocate status page\n");
1081                 ret = -ENOMEM;
1082                 goto err;
1083         }
1084
1085         i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
1086
1087         ret = i915_gem_object_pin(obj, 4096, true, false);
1088         if (ret != 0) {
1089                 goto err_unref;
1090         }
1091
1092         ring->status_page.gfx_addr = obj->gtt_offset;
1093         ring->status_page.page_addr = (void *)kmem_alloc_nofault(&kernel_map,
1094             PAGE_SIZE, PAGE_SIZE);
1095         if (ring->status_page.page_addr == NULL) {
1096                 ret = -ENOMEM;
1097                 goto err_unpin;
1098         }
1099         pmap_qenter((vm_offset_t)ring->status_page.page_addr, &obj->pages[0],
1100             1);
1101         pmap_invalidate_cache_range((vm_offset_t)ring->status_page.page_addr,
1102             (vm_offset_t)ring->status_page.page_addr + PAGE_SIZE);
1103         ring->status_page.obj = obj;
1104         memset(ring->status_page.page_addr, 0, PAGE_SIZE);
1105
1106         intel_ring_setup_status_page(ring);
1107         DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n",
1108                         ring->name, ring->status_page.gfx_addr);
1109
1110         return 0;
1111
1112 err_unpin:
1113         i915_gem_object_unpin(obj);
1114 err_unref:
1115         drm_gem_object_unreference(&obj->base);
1116 err:
1117         return ret;
1118 }
1119
1120 static int init_phys_hws_pga(struct intel_ring_buffer *ring)
1121 {
1122         struct drm_i915_private *dev_priv = ring->dev->dev_private;
1123         u32 addr;
1124
1125         if (!dev_priv->status_page_dmah) {
1126                 dev_priv->status_page_dmah =
1127                         drm_pci_alloc(ring->dev, PAGE_SIZE, PAGE_SIZE, ~0);
1128                 if (!dev_priv->status_page_dmah)
1129                         return -ENOMEM;
1130         }
1131
1132         addr = dev_priv->status_page_dmah->busaddr;
1133         if (INTEL_INFO(ring->dev)->gen >= 4)
1134                 addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0;
1135         I915_WRITE(HWS_PGA, addr);
1136
1137         ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr;
1138         memset(ring->status_page.page_addr, 0, PAGE_SIZE);
1139
1140         return 0;
1141 }
1142
1143 static inline void __iomem *ioremap_wc(resource_size_t phys_addr, unsigned long size)
1144 {
1145         return pmap_mapdev_attr(phys_addr, size, VM_MEMATTR_WRITE_COMBINING);
1146 }
1147
1148 static int intel_init_ring_buffer(struct drm_device *dev,
1149                                   struct intel_ring_buffer *ring)
1150 {
1151         struct drm_i915_gem_object *obj;
1152         int ret;
1153
1154         ring->dev = dev;
1155         INIT_LIST_HEAD(&ring->active_list);
1156         INIT_LIST_HEAD(&ring->request_list);
1157         ring->size = 32 * PAGE_SIZE;
1158         memset(ring->sync_seqno, 0, sizeof(ring->sync_seqno));
1159
1160         init_waitqueue_head(&ring->irq_queue);
1161
1162         if (I915_NEED_GFX_HWS(dev)) {
1163                 ret = init_status_page(ring);
1164                 if (ret)
1165                         return ret;
1166         } else {
1167                 BUG_ON(ring->id != RCS);
1168                 ret = init_phys_hws_pga(ring);
1169                 if (ret)
1170                         return ret;
1171         }
1172
1173         obj = i915_gem_alloc_object(dev, ring->size);
1174         if (obj == NULL) {
1175                 DRM_ERROR("Failed to allocate ringbuffer\n");
1176                 ret = -ENOMEM;
1177                 goto err_hws;
1178         }
1179
1180         ring->obj = obj;
1181
1182         ret = i915_gem_object_pin(obj, PAGE_SIZE, true, false);
1183         if (ret)
1184                 goto err_unref;
1185
1186         ret = i915_gem_object_set_to_gtt_domain(obj, true);
1187         if (ret)
1188                 goto err_unpin;
1189
1190         ring->virtual_start = ioremap_wc(dev->agp->base + obj->gtt_offset,
1191                                          ring->size);
1192         if (ring->virtual_start == NULL) {
1193                 DRM_ERROR("Failed to map ringbuffer.\n");
1194                 ret = -EINVAL;
1195                 goto err_unpin;
1196         }
1197
1198         ret = ring->init(ring);
1199         if (ret)
1200                 goto err_unmap;
1201
1202         /* Workaround an erratum on the i830 which causes a hang if
1203          * the TAIL pointer points to within the last 2 cachelines
1204          * of the buffer.
1205          */
1206         ring->effective_size = ring->size;
1207         if (IS_I830(ring->dev) || IS_845G(ring->dev))
1208                 ring->effective_size -= 128;
1209
1210         return 0;
1211
1212 err_unmap:
1213         pmap_unmapdev((vm_offset_t)ring->virtual_start, ring->size);
1214 err_unpin:
1215         i915_gem_object_unpin(obj);
1216 err_unref:
1217         drm_gem_object_unreference(&obj->base);
1218         ring->obj = NULL;
1219 err_hws:
1220         cleanup_status_page(ring);
1221         return ret;
1222 }
1223
1224 void intel_cleanup_ring_buffer(struct intel_ring_buffer *ring)
1225 {
1226         struct drm_i915_private *dev_priv;
1227         int ret;
1228
1229         if (ring->obj == NULL)
1230                 return;
1231
1232         /* Disable the ring buffer. The ring must be idle at this point */
1233         dev_priv = ring->dev->dev_private;
1234         ret = intel_ring_idle(ring);
1235         if (ret)
1236                 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
1237                           ring->name, ret);
1238
1239         I915_WRITE_CTL(ring, 0);
1240
1241         pmap_unmapdev((vm_offset_t)ring->virtual_start, ring->size);
1242
1243         i915_gem_object_unpin(ring->obj);
1244         drm_gem_object_unreference(&ring->obj->base);
1245         ring->obj = NULL;
1246
1247         if (ring->cleanup)
1248                 ring->cleanup(ring);
1249
1250         cleanup_status_page(ring);
1251 }
1252
1253 static int intel_ring_wait_seqno(struct intel_ring_buffer *ring, u32 seqno)
1254 {
1255         int ret;
1256
1257         ret = i915_wait_seqno(ring, seqno);
1258         if (!ret)
1259                 i915_gem_retire_requests_ring(ring);
1260
1261         return ret;
1262 }
1263
1264 static int intel_ring_wait_request(struct intel_ring_buffer *ring, int n)
1265 {
1266         struct drm_i915_gem_request *request;
1267         u32 seqno = 0;
1268         int ret;
1269
1270         i915_gem_retire_requests_ring(ring);
1271
1272         if (ring->last_retired_head != -1) {
1273                 ring->head = ring->last_retired_head;
1274                 ring->last_retired_head = -1;
1275                 ring->space = ring_space(ring);
1276                 if (ring->space >= n)
1277                         return 0;
1278         }
1279
1280         list_for_each_entry(request, &ring->request_list, list) {
1281                 int space;
1282
1283                 if (request->tail == -1)
1284                         continue;
1285
1286                 space = request->tail - (ring->tail + I915_RING_FREE_SPACE);
1287                 if (space < 0)
1288                         space += ring->size;
1289                 if (space >= n) {
1290                         seqno = request->seqno;
1291                         break;
1292                 }
1293
1294                 /* Consume this request in case we need more space than
1295                  * is available and so need to prevent a race between
1296                  * updating last_retired_head and direct reads of
1297                  * I915_RING_HEAD. It also provides a nice sanity check.
1298                  */
1299                 request->tail = -1;
1300         }
1301
1302         if (seqno == 0)
1303                 return -ENOSPC;
1304
1305         ret = intel_ring_wait_seqno(ring, seqno);
1306         if (ret)
1307                 return ret;
1308
1309         if (WARN_ON(ring->last_retired_head == -1))
1310                 return -ENOSPC;
1311
1312         ring->head = ring->last_retired_head;
1313         ring->last_retired_head = -1;
1314         ring->space = ring_space(ring);
1315         if (WARN_ON(ring->space < n))
1316                 return -ENOSPC;
1317
1318         return 0;
1319 }
1320
1321 static int ring_wait_for_space(struct intel_ring_buffer *ring, int n)
1322 {
1323         struct drm_device *dev = ring->dev;
1324         struct drm_i915_private *dev_priv = dev->dev_private;
1325         unsigned long end;
1326         int ret;
1327
1328         ret = intel_ring_wait_request(ring, n);
1329         if (ret != -ENOSPC)
1330                 return ret;
1331
1332         /* With GEM the hangcheck timer should kick us out of the loop,
1333          * leaving it early runs the risk of corrupting GEM state (due
1334          * to running on almost untested codepaths). But on resume
1335          * timers don't work yet, so prevent a complete hang in that
1336          * case by choosing an insanely large timeout. */
1337         end = jiffies + 60 * HZ;
1338
1339         do {
1340                 ring->head = I915_READ_HEAD(ring);
1341                 ring->space = ring_space(ring);
1342                 if (ring->space >= n) {
1343                         return 0;
1344                 }
1345
1346 #if 0
1347                 if (dev->primary->master) {
1348                         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
1349                         if (master_priv->sarea_priv)
1350                                 master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
1351                 }
1352 #else
1353                 if (dev_priv->sarea_priv)
1354                         dev_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
1355 #endif
1356
1357                 msleep(1);
1358
1359                 ret = i915_gem_check_wedge(dev_priv, dev_priv->mm.interruptible);
1360                 if (ret)
1361                         return ret;
1362         } while (!time_after(jiffies, end));
1363         return -EBUSY;
1364 }
1365
1366 static int intel_wrap_ring_buffer(struct intel_ring_buffer *ring)
1367 {
1368         uint32_t __iomem *virt;
1369         int rem = ring->size - ring->tail;
1370
1371         if (ring->space < rem) {
1372                 int ret = ring_wait_for_space(ring, rem);
1373                 if (ret)
1374                         return ret;
1375         }
1376
1377         virt = (unsigned int *)((char *)ring->virtual_start + ring->tail);
1378         rem /= 4;
1379         while (rem--)
1380                 iowrite32(MI_NOOP, virt++);
1381
1382         ring->tail = 0;
1383         ring->space = ring_space(ring);
1384
1385         return 0;
1386 }
1387
1388 int intel_ring_idle(struct intel_ring_buffer *ring)
1389 {
1390         u32 seqno;
1391         int ret;
1392
1393         /* We need to add any requests required to flush the objects and ring */
1394         if (ring->outstanding_lazy_request) {
1395                 ret = i915_add_request(ring, NULL, NULL);
1396                 if (ret)
1397                         return ret;
1398         }
1399
1400         /* Wait upon the last request to be completed */
1401         if (list_empty(&ring->request_list))
1402                 return 0;
1403
1404         seqno = list_entry(ring->request_list.prev,
1405                            struct drm_i915_gem_request,
1406                            list)->seqno;
1407
1408         return i915_wait_seqno(ring, seqno);
1409 }
1410
1411 static int
1412 intel_ring_alloc_seqno(struct intel_ring_buffer *ring)
1413 {
1414         if (ring->outstanding_lazy_request)
1415                 return 0;
1416
1417         return i915_gem_get_seqno(ring->dev, &ring->outstanding_lazy_request);
1418 }
1419
1420 int intel_ring_begin(struct intel_ring_buffer *ring,
1421                      int num_dwords)
1422 {
1423         drm_i915_private_t *dev_priv = ring->dev->dev_private;
1424         int n = 4*num_dwords;
1425         int ret;
1426
1427         ret = i915_gem_check_wedge(dev_priv, dev_priv->mm.interruptible);
1428         if (ret)
1429                 return ret;
1430
1431         /* Preallocate the olr before touching the ring */
1432         ret = intel_ring_alloc_seqno(ring);
1433         if (ret)
1434                 return ret;
1435
1436         if (unlikely(ring->tail + n > ring->effective_size)) {
1437                 ret = intel_wrap_ring_buffer(ring);
1438                 if (unlikely(ret))
1439                         return ret;
1440         }
1441
1442         if (unlikely(ring->space < n)) {
1443                 ret = ring_wait_for_space(ring, n);
1444                 if (unlikely(ret))
1445                         return ret;
1446         }
1447
1448         ring->space -= n;
1449         return 0;
1450 }
1451
1452 void intel_ring_advance(struct intel_ring_buffer *ring)
1453 {
1454         struct drm_i915_private *dev_priv = ring->dev->dev_private;
1455
1456         ring->tail &= ring->size - 1;
1457         if (dev_priv->stop_rings & intel_ring_flag(ring))
1458                 return;
1459         ring->write_tail(ring, ring->tail);
1460 }
1461
1462
1463 static void gen6_bsd_ring_write_tail(struct intel_ring_buffer *ring,
1464                                      u32 value)
1465 {
1466         drm_i915_private_t *dev_priv = ring->dev->dev_private;
1467
1468        /* Every tail move must follow the sequence below */
1469
1470         /* Disable notification that the ring is IDLE. The GT
1471          * will then assume that it is busy and bring it out of rc6.
1472          */
1473         I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
1474                    _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
1475
1476         /* Clear the context id. Here be magic! */
1477         I915_WRITE64(GEN6_BSD_RNCID, 0x0);
1478
1479         /* Wait for the ring not to be idle, i.e. for it to wake up. */
1480         if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) &
1481                       GEN6_BSD_SLEEP_INDICATOR) == 0,
1482                      50))
1483                 DRM_ERROR("timed out waiting for the BSD ring to wake up\n");
1484
1485         /* Now that the ring is fully powered up, update the tail */
1486         I915_WRITE_TAIL(ring, value);
1487         POSTING_READ(RING_TAIL(ring->mmio_base));
1488
1489         /* Let the ring send IDLE messages to the GT again,
1490          * and so let it sleep to conserve power when idle.
1491          */
1492         I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
1493                    _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
1494 }
1495
1496 static int gen6_ring_flush(struct intel_ring_buffer *ring,
1497                            u32 invalidate, u32 flush)
1498 {
1499         uint32_t cmd;
1500         int ret;
1501
1502         ret = intel_ring_begin(ring, 4);
1503         if (ret)
1504                 return ret;
1505
1506         cmd = MI_FLUSH_DW;
1507         /*
1508          * Bspec vol 1c.5 - video engine command streamer:
1509          * "If ENABLED, all TLBs will be invalidated once the flush
1510          * operation is complete. This bit is only valid when the
1511          * Post-Sync Operation field is a value of 1h or 3h."
1512          */
1513         if (invalidate & I915_GEM_GPU_DOMAINS)
1514                 cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD |
1515                         MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
1516         intel_ring_emit(ring, cmd);
1517         intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
1518         intel_ring_emit(ring, 0);
1519         intel_ring_emit(ring, MI_NOOP);
1520         intel_ring_advance(ring);
1521         return 0;
1522 }
1523
1524 static int
1525 hsw_ring_dispatch_execbuffer(struct intel_ring_buffer *ring,
1526                               u32 offset, u32 len,
1527                               unsigned flags)
1528 {
1529         int ret;
1530
1531         ret = intel_ring_begin(ring, 2);
1532         if (ret)
1533                 return ret;
1534
1535         intel_ring_emit(ring,
1536                         MI_BATCH_BUFFER_START | MI_BATCH_PPGTT_HSW |
1537                         (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_HSW));
1538         /* bit0-7 is the length on GEN6+ */
1539         intel_ring_emit(ring, offset);
1540         intel_ring_advance(ring);
1541
1542         return 0;
1543 }
1544
1545 static int
1546 gen6_ring_dispatch_execbuffer(struct intel_ring_buffer *ring,
1547                               u32 offset, u32 len,
1548                               unsigned flags)
1549 {
1550         int ret;
1551
1552         ret = intel_ring_begin(ring, 2);
1553         if (ret)
1554                 return ret;
1555
1556         intel_ring_emit(ring,
1557                         MI_BATCH_BUFFER_START |
1558                         (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_I965));
1559         /* bit0-7 is the length on GEN6+ */
1560         intel_ring_emit(ring, offset);
1561         intel_ring_advance(ring);
1562
1563         return 0;
1564 }
1565
1566 /* Blitter support (SandyBridge+) */
1567
1568 static int blt_ring_flush(struct intel_ring_buffer *ring,
1569                           u32 invalidate, u32 flush)
1570 {
1571         uint32_t cmd;
1572         int ret;
1573
1574         ret = intel_ring_begin(ring, 4);
1575         if (ret)
1576                 return ret;
1577
1578         cmd = MI_FLUSH_DW;
1579         /*
1580          * Bspec vol 1c.3 - blitter engine command streamer:
1581          * "If ENABLED, all TLBs will be invalidated once the flush
1582          * operation is complete. This bit is only valid when the
1583          * Post-Sync Operation field is a value of 1h or 3h."
1584          */
1585         if (invalidate & I915_GEM_DOMAIN_RENDER)
1586                 cmd |= MI_INVALIDATE_TLB | MI_FLUSH_DW_STORE_INDEX |
1587                         MI_FLUSH_DW_OP_STOREDW;
1588         intel_ring_emit(ring, cmd);
1589         intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
1590         intel_ring_emit(ring, 0);
1591         intel_ring_emit(ring, MI_NOOP);
1592         intel_ring_advance(ring);
1593         return 0;
1594 }
1595
1596 int intel_init_render_ring_buffer(struct drm_device *dev)
1597 {
1598         drm_i915_private_t *dev_priv = dev->dev_private;
1599         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
1600
1601         ring->name = "render ring";
1602         ring->id = RCS;
1603         ring->mmio_base = RENDER_RING_BASE;
1604
1605         if (INTEL_INFO(dev)->gen >= 6) {
1606                 ring->add_request = gen6_add_request;
1607                 ring->flush = gen7_render_ring_flush;
1608                 if (INTEL_INFO(dev)->gen == 6)
1609                         ring->flush = gen6_render_ring_flush;
1610                 ring->irq_get = gen6_ring_get_irq;
1611                 ring->irq_put = gen6_ring_put_irq;
1612                 ring->irq_enable_mask = GT_USER_INTERRUPT;
1613                 ring->get_seqno = gen6_ring_get_seqno;
1614                 ring->sync_to = gen6_ring_sync;
1615                 ring->semaphore_register[0] = MI_SEMAPHORE_SYNC_INVALID;
1616                 ring->semaphore_register[1] = MI_SEMAPHORE_SYNC_RV;
1617                 ring->semaphore_register[2] = MI_SEMAPHORE_SYNC_RB;
1618                 ring->signal_mbox[0] = GEN6_VRSYNC;
1619                 ring->signal_mbox[1] = GEN6_BRSYNC;
1620         } else if (IS_GEN5(dev)) {
1621                 ring->add_request = pc_render_add_request;
1622                 ring->flush = gen4_render_ring_flush;
1623                 ring->get_seqno = pc_render_get_seqno;
1624                 ring->irq_get = gen5_ring_get_irq;
1625                 ring->irq_put = gen5_ring_put_irq;
1626                 ring->irq_enable_mask = GT_USER_INTERRUPT | GT_PIPE_NOTIFY;
1627         } else {
1628                 ring->add_request = i9xx_add_request;
1629                 if (INTEL_INFO(dev)->gen < 4)
1630                         ring->flush = gen2_render_ring_flush;
1631                 else
1632                         ring->flush = gen4_render_ring_flush;
1633                 ring->get_seqno = ring_get_seqno;
1634                 if (IS_GEN2(dev)) {
1635                         ring->irq_get = i8xx_ring_get_irq;
1636                         ring->irq_put = i8xx_ring_put_irq;
1637                 } else {
1638                         ring->irq_get = i9xx_ring_get_irq;
1639                         ring->irq_put = i9xx_ring_put_irq;
1640                 }
1641                 ring->irq_enable_mask = I915_USER_INTERRUPT;
1642         }
1643         ring->write_tail = ring_write_tail;
1644         if (IS_HASWELL(dev))
1645                 ring->dispatch_execbuffer = hsw_ring_dispatch_execbuffer;
1646         else if (INTEL_INFO(dev)->gen >= 6)
1647                 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
1648         else if (INTEL_INFO(dev)->gen >= 4)
1649                 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
1650         else if (IS_I830(dev) || IS_845G(dev))
1651                 ring->dispatch_execbuffer = i830_dispatch_execbuffer;
1652         else
1653                 ring->dispatch_execbuffer = i915_dispatch_execbuffer;
1654         ring->init = init_render_ring;
1655         ring->cleanup = render_ring_cleanup;
1656
1657         /* Workaround batchbuffer to combat CS tlb bug. */
1658         if (HAS_BROKEN_CS_TLB(dev)) {
1659                 struct drm_i915_gem_object *obj;
1660                 int ret;
1661
1662                 obj = i915_gem_alloc_object(dev, I830_BATCH_LIMIT);
1663                 if (obj == NULL) {
1664                         DRM_ERROR("Failed to allocate batch bo\n");
1665                         return -ENOMEM;
1666                 }
1667
1668                 ret = i915_gem_object_pin(obj, 0, true, false);
1669                 if (ret != 0) {
1670                         drm_gem_object_unreference(&obj->base);
1671                         DRM_ERROR("Failed to ping batch bo\n");
1672                         return ret;
1673                 }
1674
1675                 ring->private = obj;
1676         }
1677
1678         return intel_init_ring_buffer(dev, ring);
1679 }
1680
1681 int intel_render_ring_init_dri(struct drm_device *dev, u64 start, u32 size)
1682 {
1683         drm_i915_private_t *dev_priv = dev->dev_private;
1684         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
1685         int ret;
1686
1687         ring->name = "render ring";
1688         ring->id = RCS;
1689         ring->mmio_base = RENDER_RING_BASE;
1690
1691         if (INTEL_INFO(dev)->gen >= 6) {
1692                 /* non-kms not supported on gen6+ */
1693                 return -ENODEV;
1694         }
1695
1696         /* Note: gem is not supported on gen5/ilk without kms (the corresponding
1697          * gem_init ioctl returns with -ENODEV). Hence we do not need to set up
1698          * the special gen5 functions. */
1699         ring->add_request = i9xx_add_request;
1700         if (INTEL_INFO(dev)->gen < 4)
1701                 ring->flush = gen2_render_ring_flush;
1702         else
1703                 ring->flush = gen4_render_ring_flush;
1704         ring->get_seqno = ring_get_seqno;
1705         if (IS_GEN2(dev)) {
1706                 ring->irq_get = i8xx_ring_get_irq;
1707                 ring->irq_put = i8xx_ring_put_irq;
1708         } else {
1709                 ring->irq_get = i9xx_ring_get_irq;
1710                 ring->irq_put = i9xx_ring_put_irq;
1711         }
1712         ring->irq_enable_mask = I915_USER_INTERRUPT;
1713         ring->write_tail = ring_write_tail;
1714         if (INTEL_INFO(dev)->gen >= 4)
1715                 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
1716         else if (IS_I830(dev) || IS_845G(dev))
1717                 ring->dispatch_execbuffer = i830_dispatch_execbuffer;
1718         else
1719                 ring->dispatch_execbuffer = i915_dispatch_execbuffer;
1720         ring->init = init_render_ring;
1721         ring->cleanup = render_ring_cleanup;
1722
1723         ring->dev = dev;
1724         INIT_LIST_HEAD(&ring->active_list);
1725         INIT_LIST_HEAD(&ring->request_list);
1726
1727         ring->size = size;
1728         ring->effective_size = ring->size;
1729         if (IS_I830(ring->dev) || IS_845G(ring->dev))
1730                 ring->effective_size -= 128;
1731
1732         ring->virtual_start = ioremap_wc(start, size);
1733         if (ring->virtual_start == NULL) {
1734                 DRM_ERROR("can not ioremap virtual address for"
1735                           " ring buffer\n");
1736                 return -ENOMEM;
1737         }
1738
1739         if (!I915_NEED_GFX_HWS(dev)) {
1740                 ret = init_phys_hws_pga(ring);
1741                 if (ret)
1742                         return ret;
1743         }
1744
1745         return 0;
1746 }
1747
1748 int intel_init_bsd_ring_buffer(struct drm_device *dev)
1749 {
1750         drm_i915_private_t *dev_priv = dev->dev_private;
1751         struct intel_ring_buffer *ring = &dev_priv->ring[VCS];
1752
1753         ring->name = "bsd ring";
1754         ring->id = VCS;
1755
1756         ring->write_tail = ring_write_tail;
1757         if (IS_GEN6(dev) || IS_GEN7(dev)) {
1758                 ring->mmio_base = GEN6_BSD_RING_BASE;
1759                 /* gen6 bsd needs a special wa for tail updates */
1760                 if (IS_GEN6(dev))
1761                         ring->write_tail = gen6_bsd_ring_write_tail;
1762                 ring->flush = gen6_ring_flush;
1763                 ring->add_request = gen6_add_request;
1764                 ring->get_seqno = gen6_ring_get_seqno;
1765                 ring->irq_enable_mask = GEN6_BSD_USER_INTERRUPT;
1766                 ring->irq_get = gen6_ring_get_irq;
1767                 ring->irq_put = gen6_ring_put_irq;
1768                 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
1769                 ring->sync_to = gen6_ring_sync;
1770                 ring->semaphore_register[0] = MI_SEMAPHORE_SYNC_VR;
1771                 ring->semaphore_register[1] = MI_SEMAPHORE_SYNC_INVALID;
1772                 ring->semaphore_register[2] = MI_SEMAPHORE_SYNC_VB;
1773                 ring->signal_mbox[0] = GEN6_RVSYNC;
1774                 ring->signal_mbox[1] = GEN6_BVSYNC;
1775         } else {
1776                 ring->mmio_base = BSD_RING_BASE;
1777                 ring->flush = bsd_ring_flush;
1778                 ring->add_request = i9xx_add_request;
1779                 ring->get_seqno = ring_get_seqno;
1780                 if (IS_GEN5(dev)) {
1781                         ring->irq_enable_mask = GT_BSD_USER_INTERRUPT;
1782                         ring->irq_get = gen5_ring_get_irq;
1783                         ring->irq_put = gen5_ring_put_irq;
1784                 } else {
1785                         ring->irq_enable_mask = I915_BSD_USER_INTERRUPT;
1786                         ring->irq_get = i9xx_ring_get_irq;
1787                         ring->irq_put = i9xx_ring_put_irq;
1788                 }
1789                 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
1790         }
1791         ring->init = init_ring_common;
1792
1793         return intel_init_ring_buffer(dev, ring);
1794 }
1795
1796 int intel_init_blt_ring_buffer(struct drm_device *dev)
1797 {
1798         drm_i915_private_t *dev_priv = dev->dev_private;
1799         struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
1800
1801         ring->name = "blitter ring";
1802         ring->id = BCS;
1803
1804         ring->mmio_base = BLT_RING_BASE;
1805         ring->write_tail = ring_write_tail;
1806         ring->flush = blt_ring_flush;
1807         ring->add_request = gen6_add_request;
1808         ring->get_seqno = gen6_ring_get_seqno;
1809         ring->irq_enable_mask = GEN6_BLITTER_USER_INTERRUPT;
1810         ring->irq_get = gen6_ring_get_irq;
1811         ring->irq_put = gen6_ring_put_irq;
1812         ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
1813         ring->sync_to = gen6_ring_sync;
1814         ring->semaphore_register[0] = MI_SEMAPHORE_SYNC_BR;
1815         ring->semaphore_register[1] = MI_SEMAPHORE_SYNC_BV;
1816         ring->semaphore_register[2] = MI_SEMAPHORE_SYNC_INVALID;
1817         ring->signal_mbox[0] = GEN6_RBSYNC;
1818         ring->signal_mbox[1] = GEN6_VBSYNC;
1819         ring->init = init_ring_common;
1820
1821         return intel_init_ring_buffer(dev, ring);
1822 }
1823
1824 int
1825 intel_ring_flush_all_caches(struct intel_ring_buffer *ring)
1826 {
1827         int ret;
1828
1829         if (!ring->gpu_caches_dirty)
1830                 return 0;
1831
1832         ret = ring->flush(ring, 0, I915_GEM_GPU_DOMAINS);
1833         if (ret)
1834                 return ret;
1835
1836         ring->gpu_caches_dirty = false;
1837         return 0;
1838 }
1839
1840 int
1841 intel_ring_invalidate_all_caches(struct intel_ring_buffer *ring)
1842 {
1843         uint32_t flush_domains;
1844         int ret;
1845
1846         flush_domains = 0;
1847         if (ring->gpu_caches_dirty)
1848                 flush_domains = I915_GEM_GPU_DOMAINS;
1849
1850         ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, flush_domains);
1851         if (ret)
1852                 return ret;
1853
1854         ring->gpu_caches_dirty = false;
1855         return 0;
1856 }