sys/dev/disk/aic7xxx/aic79xx_pci.c

   1 /*
   2  * Product specific probe and attach routines for:
   3  *      aic7901 and aic7902 SCSI controllers
   4  *
   5  * Copyright (c) 1994-2001 Justin T. Gibbs.
   6  * Copyright (c) 2000-2002 Adaptec Inc.
   7  * All rights reserved.
   8  *
   9  * Redistribution and use in source and binary forms, with or without
  10  * modification, are permitted provided that the following conditions
  11  * are met:
  12  * 1. Redistributions of source code must retain the above copyright
  13  *    notice, this list of conditions, and the following disclaimer,
  14  *    without modification.
  15  * 2. Redistributions in binary form must reproduce at minimum a disclaimer
  16  *    substantially similar to the "NO WARRANTY" disclaimer below
  17  *    ("Disclaimer") and any redistribution must be conditioned upon
  18  *    including a substantially similar Disclaimer requirement for further
  19  *    binary redistribution.
  20  * 3. Neither the names of the above-listed copyright holders nor the names
  21  *    of any contributors may be used to endorse or promote products derived
  22  *    from this software without specific prior written permission.
  23  *
  24  * Alternatively, this software may be distributed under the terms of the
  25  * GNU General Public License ("GPL") version 2 as published by the Free
  26  * Software Foundation.
  27  *
  28  * NO WARRANTY
  29  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  30  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  31  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
  32  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  33  * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  34  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  35  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  36  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
  37  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
  38  * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  39  * POSSIBILITY OF SUCH DAMAGES.
  40  *
  41  * $Id: //depot/aic7xxx/aic7xxx/aic79xx_pci.c#88 $
  42  *
  43  * $FreeBSD: src/sys/dev/aic7xxx/aic79xx_pci.c,v 1.24 2005/12/04 02:12:40 ru Exp $
  44  */
  45
  46 #ifdef __linux__
  47 #include "aic79xx_osm.h"
  48 #include "aic79xx_inline.h"
  49 #else
  50 #include "aic79xx_osm.h"
  51 #include "aic79xx_inline.h"
  52 #endif
  53
  54 static __inline uint64_t
  55 ahd_compose_id(u_int device, u_int vendor, u_int subdevice, u_int subvendor)
  56 {
  57         uint64_t id;
  58
  59         id = subvendor
  60            | (subdevice << 16)
  61            | ((uint64_t)vendor << 32)
  62            | ((uint64_t)device << 48);
  63
  64         return (id);
  65 }
  66
  67 #define ID_ALL_MASK                     0xFFFFFFFFFFFFFFFFull
  68 #define ID_ALL_IROC_MASK                0xFF7FFFFFFFFFFFFFull
  69 #define ID_DEV_VENDOR_MASK              0xFFFFFFFF00000000ull
  70 #define ID_9005_GENERIC_MASK            0xFFF0FFFF00000000ull
  71 #define ID_9005_GENERIC_IROC_MASK       0xFF70FFFF00000000ull
  72
  73 #define ID_AIC7901                      0x800F9005FFFF9005ull
  74 #define ID_AHA_29320A                   0x8000900500609005ull
  75 #define ID_AHA_29320ALP                 0x8017900500449005ull
  76
  77 #define ID_AIC7901A                     0x801E9005FFFF9005ull
  78 #define ID_AHA_29320LP                  0x8014900500449005ull
  79
  80 #define ID_AIC7902                      0x801F9005FFFF9005ull
  81 #define ID_AIC7902_B                    0x801D9005FFFF9005ull
  82 #define ID_AHA_39320                    0x8010900500409005ull
  83 #define ID_AHA_29320                    0x8012900500429005ull
  84 #define ID_AHA_29320B                   0x8013900500439005ull
  85 #define ID_AHA_39320_B                  0x8015900500409005ull
  86 #define ID_AHA_39320_B_DELL             0x8015900501681028ull
  87 #define ID_AHA_39320A                   0x8016900500409005ull
  88 #define ID_AHA_39320D                   0x8011900500419005ull
  89 #define ID_AHA_39320D_B                 0x801C900500419005ull
  90 #define ID_AHA_39320D_HP                0x8011900500AC0E11ull
  91 #define ID_AHA_39320D_B_HP              0x801C900500AC0E11ull
  92 #define ID_AIC7902_PCI_REV_A4           0x3
  93 #define ID_AIC7902_PCI_REV_B0           0x10
  94 #define SUBID_HP                        0x0E11
  95
  96 #define DEVID_9005_HOSTRAID(id) ((id) & 0x80)
  97
  98 #define DEVID_9005_TYPE(id) ((id) & 0xF)
  99 #define         DEVID_9005_TYPE_HBA             0x0     /* Standard Card */
 100 #define         DEVID_9005_TYPE_HBA_2EXT        0x1     /* 2 External Ports */
 101 #define         DEVID_9005_TYPE_MB              0xF     /* On Motherboard */
 102
 103 #define DEVID_9005_MFUNC(id) ((id) & 0x10)
 104
 105 #define DEVID_9005_PACKETIZED(id) ((id) & 0x8000)
 106
 107 #define SUBID_9005_TYPE(id) ((id) & 0xF)
 108 #define         SUBID_9005_TYPE_HBA             0x0     /* Standard Card */
 109 #define         SUBID_9005_TYPE_MB              0xF     /* On Motherboard */
 110
 111 #define SUBID_9005_AUTOTERM(id) (((id) & 0x10) == 0)
 112
 113 #define SUBID_9005_LEGACYCONN_FUNC(id) ((id) & 0x20)
 114
 115 #define SUBID_9005_SEEPTYPE(id) ((id) & 0x0C0) >> 6)
 116 #define         SUBID_9005_SEEPTYPE_NONE        0x0
 117 #define         SUBID_9005_SEEPTYPE_4K          0x1
 118
 119 static ahd_device_setup_t ahd_aic7901_setup;
 120 static ahd_device_setup_t ahd_aic7901A_setup;
 121 static ahd_device_setup_t ahd_aic7902_setup;
 122 static ahd_device_setup_t ahd_aic790X_setup;
 123
 124 struct ahd_pci_identity ahd_pci_ident_table [] =
 125 {
 126         /* aic7901 based controllers */
 127         {
 128                 ID_AHA_29320A,
 129                 ID_ALL_MASK,
 130                 "Adaptec 29320A Ultra320 SCSI adapter",
 131                 ahd_aic7901_setup
 132         },
 133         {
 134                 ID_AHA_29320ALP,
 135                 ID_ALL_MASK,
 136                 "Adaptec 29320ALP Ultra320 SCSI adapter",
 137                 ahd_aic7901_setup
 138         },
 139         /* aic7901A based controllers */
 140         {
 141                 ID_AHA_29320LP,
 142                 ID_ALL_MASK,
 143                 "Adaptec 29320LP Ultra320 SCSI adapter",
 144                 ahd_aic7901A_setup
 145         },
 146         /* aic7902 based controllers */
 147         {
 148                 ID_AHA_29320,
 149                 ID_ALL_MASK,
 150                 "Adaptec 29320 Ultra320 SCSI adapter",
 151                 ahd_aic7902_setup
 152         },
 153         {
 154                 ID_AHA_29320B,
 155                 ID_ALL_MASK,
 156                 "Adaptec 29320B Ultra320 SCSI adapter",
 157                 ahd_aic7902_setup
 158         },
 159         {
 160                 ID_AHA_39320,
 161                 ID_ALL_MASK,
 162                 "Adaptec 39320 Ultra320 SCSI adapter",
 163                 ahd_aic7902_setup
 164         },
 165         {
 166                 ID_AHA_39320_B,
 167                 ID_ALL_MASK,
 168                 "Adaptec 39320 Ultra320 SCSI adapter",
 169                 ahd_aic7902_setup
 170         },
 171         {
 172                 ID_AHA_39320_B_DELL,
 173                 ID_ALL_MASK,
 174                 "Adaptec (Dell OEM) 39320 Ultra320 SCSI adapter",
 175                 ahd_aic7902_setup
 176         },
 177         {
 178                 ID_AHA_39320A,
 179                 ID_ALL_MASK,
 180                 "Adaptec 39320A Ultra320 SCSI adapter",
 181                 ahd_aic7902_setup
 182         },
 183         {
 184                 ID_AHA_39320D,
 185                 ID_ALL_MASK,
 186                 "Adaptec 39320D Ultra320 SCSI adapter",
 187                 ahd_aic7902_setup
 188         },
 189         {
 190                 ID_AHA_39320D_HP,
 191                 ID_ALL_MASK,
 192                 "Adaptec (HP OEM) 39320D Ultra320 SCSI adapter",
 193                 ahd_aic7902_setup
 194         },
 195         {
 196                 ID_AHA_39320D_B,
 197                 ID_ALL_MASK,
 198                 "Adaptec 39320D Ultra320 SCSI adapter",
 199                 ahd_aic7902_setup
 200         },
 201         {
 202                 ID_AHA_39320D_B_HP,
 203                 ID_ALL_MASK,
 204                 "Adaptec (HP OEM) 39320D Ultra320 SCSI adapter",
 205                 ahd_aic7902_setup
 206         },
 207         /* Generic chip probes for devices we don't know 'exactly' */
 208         {
 209                 ID_AIC7901 & ID_9005_GENERIC_MASK,
 210                 ID_9005_GENERIC_MASK,
 211                 "Adaptec AIC7901 Ultra320 SCSI adapter",
 212                 ahd_aic7901_setup
 213         },
 214         {
 215                 ID_AIC7901A & ID_DEV_VENDOR_MASK,
 216                 ID_DEV_VENDOR_MASK,
 217                 "Adaptec AIC7901A Ultra320 SCSI adapter",
 218                 ahd_aic7901A_setup
 219         },
 220         {
 221                 ID_AIC7902 & ID_9005_GENERIC_MASK,
 222                 ID_9005_GENERIC_MASK,
 223                 "Adaptec AIC7902 Ultra320 SCSI adapter",
 224                 ahd_aic7902_setup
 225         }
 226 };
 227
 228 const u_int ahd_num_pci_devs = NUM_ELEMENTS(ahd_pci_ident_table);
 229
 230 #define DEVCONFIG               0x40
 231 #define         PCIXINITPAT     0x0000E000ul
 232 #define                 PCIXINIT_PCI33_66       0x0000E000ul
 233 #define                 PCIXINIT_PCIX50_66      0x0000C000ul
 234 #define                 PCIXINIT_PCIX66_100     0x0000A000ul
 235 #define                 PCIXINIT_PCIX100_133    0x00008000ul
 236 #define PCI_BUS_MODES_INDEX(devconfig)  \
 237         (((devconfig) & PCIXINITPAT) >> 13)
 238 static const char *pci_bus_modes[] =
 239 {
 240         "PCI bus mode unknown",
 241         "PCI bus mode unknown",
 242         "PCI bus mode unknown",
 243         "PCI bus mode unknown",
 244         "PCI-X 101-133Mhz",
 245         "PCI-X 67-100Mhz",
 246         "PCI-X 50-66Mhz",
 247         "PCI 33 or 66Mhz"
 248 };
 249
 250 #define         TESTMODE        0x00000800ul
 251 #define         IRDY_RST        0x00000200ul
 252 #define         FRAME_RST       0x00000100ul
 253 #define         PCI64BIT        0x00000080ul
 254 #define         MRDCEN          0x00000040ul
 255 #define         ENDIANSEL       0x00000020ul
 256 #define         MIXQWENDIANEN   0x00000008ul
 257 #define         DACEN           0x00000004ul
 258 #define         STPWLEVEL       0x00000002ul
 259 #define         QWENDIANSEL     0x00000001ul
 260
 261 #define DEVCONFIG1              0x44
 262 #define         PREQDIS         0x01
 263
 264 #define CSIZE_LATTIME           0x0c
 265 #define         CACHESIZE       0x000000fful
 266 #define         LATTIME         0x0000ff00ul
 267
 268 static int      ahd_check_extport(struct ahd_softc *ahd);
 269 static void     ahd_configure_termination(struct ahd_softc *ahd,
 270                                           u_int adapter_control);
 271 static void     ahd_pci_split_intr(struct ahd_softc *ahd, u_int intstat);
 272
 273 struct ahd_pci_identity *
 274 ahd_find_pci_device(aic_dev_softc_t pci)
 275 {
 276         uint64_t  full_id;
 277         uint16_t  device;
 278         uint16_t  vendor;
 279         uint16_t  subdevice;
 280         uint16_t  subvendor;
 281         struct    ahd_pci_identity *entry;
 282         u_int     i;
 283
 284         vendor = aic_pci_read_config(pci, PCIR_DEVVENDOR, /*bytes*/2);
 285         device = aic_pci_read_config(pci, PCIR_DEVICE, /*bytes*/2);
 286         subvendor = aic_pci_read_config(pci, PCIR_SUBVEND_0, /*bytes*/2);
 287         subdevice = aic_pci_read_config(pci, PCIR_SUBDEV_0, /*bytes*/2);
 288         full_id = ahd_compose_id(device,
 289                                  vendor,
 290                                  subdevice,
 291                                  subvendor);
 292
 293         /*
 294          * If we are configured to attach to HostRAID
 295          * controllers, mask out the IROC/HostRAID bit
 296          * in the
 297          */
 298         if (ahd_attach_to_HostRAID_controllers)
 299                 full_id &= ID_ALL_IROC_MASK;
 300
 301         for (i = 0; i < ahd_num_pci_devs; i++) {
 302                 entry = &ahd_pci_ident_table[i];
 303                 if (entry->full_id == (full_id & entry->id_mask)) {
 304                         /* Honor exclusion entries. */
 305                         if (entry->name == NULL)
 306                                 return (NULL);
 307                         return (entry);
 308                 }
 309         }
 310         return (NULL);
 311 }
 312
 313 int
 314 ahd_pci_config(struct ahd_softc *ahd, struct ahd_pci_identity *entry)
 315 {
 316         u_int            command;
 317         uint32_t         devconfig;
 318         uint16_t         device;
 319         uint16_t         subvendor;
 320         int              error;
 321
 322         ahd->description = entry->name;
 323         /*
 324          * Record if this is a HostRAID board.
 325          */
 326         device = aic_pci_read_config(ahd->dev_softc,
 327                                      PCIR_DEVICE, /*bytes*/2);
 328         if (DEVID_9005_HOSTRAID(device))
 329                 ahd->flags |= AHD_HOSTRAID_BOARD;
 330
 331         /*
 332          * Record if this is an HP board.
 333          */
 334         subvendor = aic_pci_read_config(ahd->dev_softc,
 335                                         PCIR_SUBVEND_0, /*bytes*/2);
 336         if (subvendor == SUBID_HP)
 337                 ahd->flags |= AHD_HP_BOARD;
 338
 339         error = entry->setup(ahd);
 340         if (error != 0)
 341                 return (error);
 342
 343         devconfig = aic_pci_read_config(ahd->dev_softc, DEVCONFIG, /*bytes*/4);
 344         if ((devconfig & PCIXINITPAT) == PCIXINIT_PCI33_66) {
 345                 ahd->chip |= AHD_PCI;
 346                 /* Disable PCIX workarounds when running in PCI mode. */
 347                 ahd->bugs &= ~AHD_PCIX_BUG_MASK;
 348         } else {
 349                 ahd->chip |= AHD_PCIX;
 350         }
 351         ahd->bus_description = pci_bus_modes[PCI_BUS_MODES_INDEX(devconfig)];
 352
 353         aic_power_state_change(ahd, AIC_POWER_STATE_D0);
 354
 355         error = ahd_pci_map_registers(ahd);
 356         if (error != 0)
 357                 return (error);
 358
 359         /*
 360          * If we need to support high memory, enable dual
 361          * address cycles.  This bit must be set to enable
 362          * high address bit generation even if we are on a
 363          * 64bit bus (PCI64BIT set in devconfig).
 364          */
 365         if ((ahd->flags & (AHD_39BIT_ADDRESSING|AHD_64BIT_ADDRESSING)) != 0) {
 366                 uint32_t devconfig;
 367
 368                 if (bootverbose)
 369                         kprintf("%s: Enabling 39Bit Addressing\n",
 370                                ahd_name(ahd));
 371                 devconfig = aic_pci_read_config(ahd->dev_softc,
 372                                                 DEVCONFIG, /*bytes*/4);
 373                 devconfig |= DACEN;
 374                 aic_pci_write_config(ahd->dev_softc, DEVCONFIG,
 375                                      devconfig, /*bytes*/4);
 376         }
 377
 378         /* Ensure busmastering is enabled */
 379         command = aic_pci_read_config(ahd->dev_softc, PCIR_COMMAND, /*bytes*/2);
 380         command |= PCIM_CMD_BUSMASTEREN;
 381         aic_pci_write_config(ahd->dev_softc, PCIR_COMMAND, command, /*bytes*/2);
 382
 383         error = ahd_softc_init(ahd);
 384         if (error != 0)
 385                 return (error);
 386
 387         ahd->bus_intr = ahd_pci_intr;
 388
 389         error = ahd_reset(ahd, /*reinit*/FALSE);
 390         if (error != 0)
 391                 return (ENXIO);
 392
 393         ahd->pci_cachesize =
 394             aic_pci_read_config(ahd->dev_softc, CSIZE_LATTIME,
 395                                 /*bytes*/1) & CACHESIZE;
 396         ahd->pci_cachesize *= 4;
 397
 398         ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
 399         /* See if we have a SEEPROM and perform auto-term */
 400         error = ahd_check_extport(ahd);
 401         if (error != 0)
 402                 return (error);
 403
 404         /* Core initialization */
 405         error = ahd_init(ahd);
 406         if (error != 0)
 407                 return (error);
 408
 409         /*
 410          * Allow interrupts now that we are completely setup.
 411          */
 412         error = ahd_pci_map_int(ahd);
 413         if (error != 0)
 414                 return (error);
 415
 416         ahd_lock(ahd);
 417         /*
 418          * Link this softc in with all other ahd instances.
 419          */
 420         ahd_softc_insert(ahd);
 421         ahd_unlock(ahd);
 422         return (0);
 423 }
 424
 425 /*
 426  * Perform some simple tests that should catch situations where
 427  * our registers are invalidly mapped.
 428  */
 429 int
 430 ahd_pci_test_register_access(struct ahd_softc *ahd)
 431 {
 432         uint32_t cmd;
 433         u_int    targpcistat;
 434         u_int    pci_status1;
 435         int      error;
 436         uint8_t  hcntrl;
 437
 438         error = EIO;
 439
 440         /*
 441          * Enable PCI error interrupt status, but suppress NMIs
 442          * generated by SERR raised due to target aborts.
 443          */
 444         cmd = aic_pci_read_config(ahd->dev_softc, PCIR_COMMAND, /*bytes*/2);
 445         aic_pci_write_config(ahd->dev_softc, PCIR_COMMAND,
 446                              cmd & ~PCIM_CMD_SERRESPEN, /*bytes*/2);
 447
 448         /*
 449          * First a simple test to see if any
 450          * registers can be read.  Reading
 451          * HCNTRL has no side effects and has
 452          * at least one bit that is guaranteed to
 453          * be zero so it is a good register to
 454          * use for this test.
 455          */
 456         hcntrl = ahd_inb(ahd, HCNTRL);
 457         if (hcntrl == 0xFF)
 458                 goto fail;
 459
 460         /*
 461          * Next create a situation where write combining
 462          * or read prefetching could be initiated by the
 463          * CPU or host bridge.  Our device does not support
 464          * either, so look for data corruption and/or flaged
 465          * PCI errors.  First pause without causing another
 466          * chip reset.
 467          */
 468         hcntrl &= ~CHIPRST;
 469         ahd_outb(ahd, HCNTRL, hcntrl|PAUSE);
 470         while (ahd_is_paused(ahd) == 0)
 471                 ;
 472
 473         /* Clear any PCI errors that occurred before our driver attached. */
 474         ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG);
 475         targpcistat = ahd_inb(ahd, TARGPCISTAT);
 476         ahd_outb(ahd, TARGPCISTAT, targpcistat);
 477         pci_status1 = aic_pci_read_config(ahd->dev_softc,
 478                                           PCIR_STATUS + 1, /*bytes*/1);
 479         aic_pci_write_config(ahd->dev_softc, PCIR_STATUS + 1,
 480                              pci_status1, /*bytes*/1);
 481         ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
 482         ahd_outb(ahd, CLRINT, CLRPCIINT);
 483
 484         ahd_outb(ahd, SEQCTL0, PERRORDIS);
 485         ahd_outl(ahd, SRAM_BASE, 0x5aa555aa);
 486         if (ahd_inl(ahd, SRAM_BASE) != 0x5aa555aa)
 487                 goto fail;
 488
 489         if ((ahd_inb(ahd, INTSTAT) & PCIINT) != 0) {
 490                 u_int targpcistat;
 491
 492                 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG);
 493                 targpcistat = ahd_inb(ahd, TARGPCISTAT);
 494                 if ((targpcistat & STA) != 0)
 495                         goto fail;
 496         }
 497
 498         error = 0;
 499
 500 fail:
 501         if ((ahd_inb(ahd, INTSTAT) & PCIINT) != 0) {
 502
 503                 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG);
 504                 targpcistat = ahd_inb(ahd, TARGPCISTAT);
 505
 506                 /* Silently clear any latched errors. */
 507                 ahd_outb(ahd, TARGPCISTAT, targpcistat);
 508                 pci_status1 = aic_pci_read_config(ahd->dev_softc,
 509                                                   PCIR_STATUS + 1, /*bytes*/1);
 510                 aic_pci_write_config(ahd->dev_softc, PCIR_STATUS + 1,
 511                                      pci_status1, /*bytes*/1);
 512                 ahd_outb(ahd, CLRINT, CLRPCIINT);
 513         }
 514         ahd_outb(ahd, SEQCTL0, PERRORDIS|FAILDIS);
 515         aic_pci_write_config(ahd->dev_softc, PCIR_COMMAND, cmd, /*bytes*/2);
 516         return (error);
 517 }
 518
 519 /*
 520  * Check the external port logic for a serial eeprom
 521  * and termination/cable detection contrls.
 522  */
 523 static int
 524 ahd_check_extport(struct ahd_softc *ahd)
 525 {
 526         struct  vpd_config vpd;
 527         struct  seeprom_config *sc;
 528         u_int   adapter_control;
 529         int     have_seeprom;
 530         int     error;
 531
 532         sc = ahd->seep_config;
 533         have_seeprom = ahd_acquire_seeprom(ahd);
 534         if (have_seeprom) {
 535                 u_int start_addr;
 536
 537                 /*
 538                  * Fetch VPD for this function and parse it.
 539                  */
 540                 if (bootverbose)
 541                         kprintf("%s: Reading VPD from SEEPROM...",
 542                                ahd_name(ahd));
 543
 544                 /* Address is always in units of 16bit words */
 545                 start_addr = ((2 * sizeof(*sc))
 546                             + (sizeof(vpd) * (ahd->channel - 'A'))) / 2;
 547
 548                 error = ahd_read_seeprom(ahd, (uint16_t *)&vpd,
 549                                          start_addr, sizeof(vpd)/2,
 550                                          /*bytestream*/TRUE);
 551                 if (error == 0)
 552                         error = ahd_parse_vpddata(ahd, &vpd);
 553                 if (bootverbose)
 554                         kprintf("%s: VPD parsing %s\n",
 555                                ahd_name(ahd),
 556                                error == 0 ? "successful" : "failed");
 557
 558                 if (bootverbose)
 559                         kprintf("%s: Reading SEEPROM...", ahd_name(ahd));
 560
 561                 /* Address is always in units of 16bit words */
 562                 start_addr = (sizeof(*sc) / 2) * (ahd->channel - 'A');
 563
 564                 error = ahd_read_seeprom(ahd, (uint16_t *)sc,
 565                                          start_addr, sizeof(*sc)/2,
 566                                          /*bytestream*/FALSE);
 567
 568                 if (error != 0) {
 569                         kprintf("Unable to read SEEPROM\n");
 570                         have_seeprom = 0;
 571                 } else {
 572                         have_seeprom = ahd_verify_cksum(sc);
 573
 574                         if (bootverbose) {
 575                                 if (have_seeprom == 0)
 576                                         kprintf ("checksum error\n");
 577                                 else
 578                                         kprintf ("done.\n");
 579                         }
 580                 }
 581                 ahd_release_seeprom(ahd);
 582         }
 583
 584         if (!have_seeprom) {
 585                 u_int     nvram_scb;
 586
 587                 /*
 588                  * Pull scratch ram settings and treat them as
 589                  * if they are the contents of an seeprom if
 590                  * the 'ADPT', 'BIOS', or 'ASPI' signature is found
 591                  * in SCB 0xFF.  We manually compose the data as 16bit
 592                  * values to avoid endian issues.
 593                  */
 594                 ahd_set_scbptr(ahd, 0xFF);
 595                 nvram_scb = ahd_inb_scbram(ahd, SCB_BASE + NVRAM_SCB_OFFSET);
 596                 if (nvram_scb != 0xFF
 597                  && ((ahd_inb_scbram(ahd, SCB_BASE + 0) == 'A'
 598                    && ahd_inb_scbram(ahd, SCB_BASE + 1) == 'D'
 599                    && ahd_inb_scbram(ahd, SCB_BASE + 2) == 'P'
 600                    && ahd_inb_scbram(ahd, SCB_BASE + 3) == 'T')
 601                   || (ahd_inb_scbram(ahd, SCB_BASE + 0) == 'B'
 602                    && ahd_inb_scbram(ahd, SCB_BASE + 1) == 'I'
 603                    && ahd_inb_scbram(ahd, SCB_BASE + 2) == 'O'
 604                    && ahd_inb_scbram(ahd, SCB_BASE + 3) == 'S')
 605                   || (ahd_inb_scbram(ahd, SCB_BASE + 0) == 'A'
 606                    && ahd_inb_scbram(ahd, SCB_BASE + 1) == 'S'
 607                    && ahd_inb_scbram(ahd, SCB_BASE + 2) == 'P'
 608                    && ahd_inb_scbram(ahd, SCB_BASE + 3) == 'I'))) {
 609                         uint16_t *sc_data;
 610                         int       i;
 611
 612                         ahd_set_scbptr(ahd, nvram_scb);
 613                         sc_data = (uint16_t *)sc;
 614                         for (i = 0; i < 64; i += 2)
 615                                 *sc_data++ = ahd_inw_scbram(ahd, SCB_BASE+i);
 616                         have_seeprom = ahd_verify_cksum(sc);
 617                         if (have_seeprom)
 618                                 ahd->flags |= AHD_SCB_CONFIG_USED;
 619                 }
 620         }
 621
 622 #ifdef AHD_DEBUG
 623         if (have_seeprom != 0
 624          && (ahd_debug & AHD_DUMP_SEEPROM) != 0) {
 625                 uint16_t *sc_data;
 626                 int       i;
 627
 628                 kprintf("%s: Seeprom Contents:", ahd_name(ahd));
 629                 sc_data = (uint16_t *)sc;
 630                 for (i = 0; i < (sizeof(*sc)); i += 2)
 631                         kprintf("\n\t0x%.4x", sc_data[i]);
 632                 kprintf("\n");
 633         }
 634 #endif
 635
 636         if (!have_seeprom) {
 637                 if (bootverbose)
 638                         kprintf("%s: No SEEPROM available.\n", ahd_name(ahd));
 639                 ahd->flags |= AHD_USEDEFAULTS;
 640                 error = ahd_default_config(ahd);
 641                 adapter_control = CFAUTOTERM|CFSEAUTOTERM;
 642                 kfree(ahd->seep_config, M_DEVBUF);
 643                 ahd->seep_config = NULL;
 644         } else {
 645                 error = ahd_parse_cfgdata(ahd, sc);
 646                 adapter_control = sc->adapter_control;
 647         }
 648         if (error != 0)
 649                 return (error);
 650
 651         ahd_configure_termination(ahd, adapter_control);
 652
 653         return (0);
 654 }
 655
 656 static void
 657 ahd_configure_termination(struct ahd_softc *ahd, u_int adapter_control)
 658 {
 659         int      error;
 660         u_int    sxfrctl1;
 661         uint8_t  termctl;
 662         uint32_t devconfig;
 663
 664         devconfig = aic_pci_read_config(ahd->dev_softc, DEVCONFIG, /*bytes*/4);
 665         devconfig &= ~STPWLEVEL;
 666         if ((ahd->flags & AHD_STPWLEVEL_A) != 0)
 667                 devconfig |= STPWLEVEL;
 668         if (bootverbose)
 669                 kprintf("%s: STPWLEVEL is %s\n",
 670                        ahd_name(ahd), (devconfig & STPWLEVEL) ? "on" : "off");
 671         aic_pci_write_config(ahd->dev_softc, DEVCONFIG, devconfig, /*bytes*/4);
 672
 673         /* Make sure current sensing is off. */
 674         if ((ahd->flags & AHD_CURRENT_SENSING) != 0) {
 675                 (void)ahd_write_flexport(ahd, FLXADDR_ROMSTAT_CURSENSECTL, 0);
 676         }
 677
 678         /*
 679          * Read to sense.  Write to set.
 680          */
 681         error = ahd_read_flexport(ahd, FLXADDR_TERMCTL, &termctl);
 682         if ((adapter_control & CFAUTOTERM) == 0) {
 683                 if (bootverbose)
 684                         kprintf("%s: Manual Primary Termination\n",
 685                                ahd_name(ahd));
 686                 termctl &= ~(FLX_TERMCTL_ENPRILOW|FLX_TERMCTL_ENPRIHIGH);
 687                 if ((adapter_control & CFSTERM) != 0)
 688                         termctl |= FLX_TERMCTL_ENPRILOW;
 689                 if ((adapter_control & CFWSTERM) != 0)
 690                         termctl |= FLX_TERMCTL_ENPRIHIGH;
 691         } else if (error != 0) {
 692                 kprintf("%s: Primary Auto-Term Sensing failed! "
 693                        "Using Defaults.\n", ahd_name(ahd));
 694                 termctl = FLX_TERMCTL_ENPRILOW|FLX_TERMCTL_ENPRIHIGH;
 695         }
 696
 697         if ((adapter_control & CFSEAUTOTERM) == 0) {
 698                 if (bootverbose)
 699                         kprintf("%s: Manual Secondary Termination\n",
 700                                ahd_name(ahd));
 701                 termctl &= ~(FLX_TERMCTL_ENSECLOW|FLX_TERMCTL_ENSECHIGH);
 702                 if ((adapter_control & CFSELOWTERM) != 0)
 703                         termctl |= FLX_TERMCTL_ENSECLOW;
 704                 if ((adapter_control & CFSEHIGHTERM) != 0)
 705                         termctl |= FLX_TERMCTL_ENSECHIGH;
 706         } else if (error != 0) {
 707                 kprintf("%s: Secondary Auto-Term Sensing failed! "
 708                        "Using Defaults.\n", ahd_name(ahd));
 709                 termctl |= FLX_TERMCTL_ENSECLOW|FLX_TERMCTL_ENSECHIGH;
 710         }
 711
 712         /*
 713          * Now set the termination based on what we found.
 714          */
 715         sxfrctl1 = ahd_inb(ahd, SXFRCTL1) & ~STPWEN;
 716         ahd->flags &= ~AHD_TERM_ENB_A;
 717         if ((termctl & FLX_TERMCTL_ENPRILOW) != 0) {
 718                 ahd->flags |= AHD_TERM_ENB_A;
 719                 sxfrctl1 |= STPWEN;
 720         }
 721         /* Must set the latch once in order to be effective. */
 722         ahd_outb(ahd, SXFRCTL1, sxfrctl1|STPWEN);
 723         ahd_outb(ahd, SXFRCTL1, sxfrctl1);
 724
 725         error = ahd_write_flexport(ahd, FLXADDR_TERMCTL, termctl);
 726         if (error != 0) {
 727                 kprintf("%s: Unable to set termination settings!\n",
 728                        ahd_name(ahd));
 729         } else if (bootverbose) {
 730                 kprintf("%s: Primary High byte termination %sabled\n",
 731                        ahd_name(ahd),
 732                        (termctl & FLX_TERMCTL_ENPRIHIGH) ? "En" : "Dis");
 733
 734                 kprintf("%s: Primary Low byte termination %sabled\n",
 735                        ahd_name(ahd),
 736                        (termctl & FLX_TERMCTL_ENPRILOW) ? "En" : "Dis");
 737
 738                 kprintf("%s: Secondary High byte termination %sabled\n",
 739                        ahd_name(ahd),
 740                        (termctl & FLX_TERMCTL_ENSECHIGH) ? "En" : "Dis");
 741
 742                 kprintf("%s: Secondary Low byte termination %sabled\n",
 743                        ahd_name(ahd),
 744                        (termctl & FLX_TERMCTL_ENSECLOW) ? "En" : "Dis");
 745         }
 746         return;
 747 }
 748
 749 #define DPE     0x80
 750 #define SSE     0x40
 751 #define RMA     0x20
 752 #define RTA     0x10
 753 #define STA     0x08
 754 #define DPR     0x01
 755
 756 static const char *split_status_source[] =
 757 {
 758         "DFF0",
 759         "DFF1",
 760         "OVLY",
 761         "CMC",
 762 };
 763
 764 static const char *pci_status_source[] =
 765 {
 766         "DFF0",
 767         "DFF1",
 768         "SG",
 769         "CMC",
 770         "OVLY",
 771         "NONE",
 772         "MSI",
 773         "TARG"
 774 };
 775
 776 static const char *split_status_strings[] =
 777 {
 778         "%s: Received split response in %s.\n",
 779         "%s: Received split completion error message in %s\n",
 780         "%s: Receive overrun in %s\n",
 781         "%s: Count not complete in %s\n",
 782         "%s: Split completion data bucket in %s\n",
 783         "%s: Split completion address error in %s\n",
 784         "%s: Split completion byte count error in %s\n",
 785         "%s: Signaled Target-abort to early terminate a split in %s\n"
 786 };
 787
 788 static const char *pci_status_strings[] =
 789 {
 790         "%s: Data Parity Error has been reported via PERR# in %s\n",
 791         "%s: Target initial wait state error in %s\n",
 792         "%s: Split completion read data parity error in %s\n",
 793         "%s: Split completion address attribute parity error in %s\n",
 794         "%s: Received a Target Abort in %s\n",
 795         "%s: Received a Master Abort in %s\n",
 796         "%s: Signal System Error Detected in %s\n",
 797         "%s: Address or Write Phase Parity Error Detected in %s.\n"
 798 };
 799
 800 void
 801 ahd_pci_intr(struct ahd_softc *ahd)
 802 {
 803         uint8_t         pci_status[8];
 804         ahd_mode_state  saved_modes;
 805         u_int           pci_status1;
 806         u_int           intstat;
 807         u_int           i;
 808         u_int           reg;
 809
 810         intstat = ahd_inb(ahd, INTSTAT);
 811
 812         if ((intstat & SPLTINT) != 0)
 813                 ahd_pci_split_intr(ahd, intstat);
 814
 815         if ((intstat & PCIINT) == 0)
 816                 return;
 817
 818         kprintf("%s: PCI error Interrupt\n", ahd_name(ahd));
 819         saved_modes = ahd_save_modes(ahd);
 820         ahd_dump_card_state(ahd);
 821         ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG);
 822         for (i = 0, reg = DF0PCISTAT; i < 8; i++, reg++) {
 823
 824                 if (i == 5)
 825                         continue;
 826                 pci_status[i] = ahd_inb(ahd, reg);
 827                 /* Clear latched errors.  So our interrupt deasserts. */
 828                 ahd_outb(ahd, reg, pci_status[i]);
 829         }
 830
 831         for (i = 0; i < 8; i++) {
 832                 u_int bit;
 833
 834                 if (i == 5)
 835                         continue;
 836
 837                 for (bit = 0; bit < 8; bit++) {
 838
 839                         if ((pci_status[i] & (0x1 << bit)) != 0) {
 840                                 static const char *s;
 841
 842                                 s = pci_status_strings[bit];
 843                                 if (i == 7/*TARG*/ && bit == 3)
 844                                         s = "%s: Signaled Target Abort\n";
 845                                 kprintf(s, ahd_name(ahd), pci_status_source[i]);
 846                         }
 847                 }
 848         }
 849         pci_status1 = aic_pci_read_config(ahd->dev_softc,
 850                                           PCIR_STATUS + 1, /*bytes*/1);
 851         aic_pci_write_config(ahd->dev_softc, PCIR_STATUS + 1,
 852                              pci_status1, /*bytes*/1);
 853         ahd_restore_modes(ahd, saved_modes);
 854         ahd_outb(ahd, CLRINT, CLRPCIINT);
 855         ahd_unpause(ahd);
 856 }
 857
 858 static void
 859 ahd_pci_split_intr(struct ahd_softc *ahd, u_int intstat)
 860 {
 861         uint8_t         split_status[4];
 862         uint8_t         split_status1[4];
 863         uint8_t         sg_split_status[2];
 864         uint8_t         sg_split_status1[2];
 865         ahd_mode_state  saved_modes;
 866         u_int           i;
 867         uint16_t        pcix_status;
 868
 869         /*
 870          * Check for splits in all modes.  Modes 0 and 1
 871          * additionally have SG engine splits to look at.
 872          */
 873         pcix_status = aic_pci_read_config(ahd->dev_softc, PCIXR_STATUS,
 874                                           /*bytes*/2);
 875         kprintf("%s: PCI Split Interrupt - PCI-X status = 0x%x\n",
 876                ahd_name(ahd), pcix_status);
 877         saved_modes = ahd_save_modes(ahd);
 878         for (i = 0; i < 4; i++) {
 879                 ahd_set_modes(ahd, i, i);
 880
 881                 split_status[i] = ahd_inb(ahd, DCHSPLTSTAT0);
 882                 split_status1[i] = ahd_inb(ahd, DCHSPLTSTAT1);
 883                 /* Clear latched errors.  So our interrupt deasserts. */
 884                 ahd_outb(ahd, DCHSPLTSTAT0, split_status[i]);
 885                 ahd_outb(ahd, DCHSPLTSTAT1, split_status1[i]);
 886                 if (i > 1)
 887                         continue;
 888                 sg_split_status[i] = ahd_inb(ahd, SGSPLTSTAT0);
 889                 sg_split_status1[i] = ahd_inb(ahd, SGSPLTSTAT1);
 890                 /* Clear latched errors.  So our interrupt deasserts. */
 891                 ahd_outb(ahd, SGSPLTSTAT0, sg_split_status[i]);
 892                 ahd_outb(ahd, SGSPLTSTAT1, sg_split_status1[i]);
 893         }
 894
 895         for (i = 0; i < 4; i++) {
 896                 u_int bit;
 897
 898                 for (bit = 0; bit < 8; bit++) {
 899
 900                         if ((split_status[i] & (0x1 << bit)) != 0) {
 901                                 static const char *s;
 902
 903                                 s = split_status_strings[bit];
 904                                 kprintf(s, ahd_name(ahd),
 905                                        split_status_source[i]);
 906                         }
 907
 908                         if (i > 1)
 909                                 continue;
 910
 911                         if ((sg_split_status[i] & (0x1 << bit)) != 0) {
 912                                 static const char *s;
 913
 914                                 s = split_status_strings[bit];
 915                                 kprintf(s, ahd_name(ahd), "SG");
 916                         }
 917                 }
 918         }
 919         /*
 920          * Clear PCI-X status bits.
 921          */
 922         aic_pci_write_config(ahd->dev_softc, PCIXR_STATUS,
 923                              pcix_status, /*bytes*/2);
 924         ahd_outb(ahd, CLRINT, CLRSPLTINT);
 925         ahd_restore_modes(ahd, saved_modes);
 926 }
 927
 928 static int
 929 ahd_aic7901_setup(struct ahd_softc *ahd)
 930 {
 931
 932         ahd->chip = AHD_AIC7901;
 933         ahd->features = AHD_AIC7901_FE;
 934         return (ahd_aic790X_setup(ahd));
 935 }
 936
 937 static int
 938 ahd_aic7901A_setup(struct ahd_softc *ahd)
 939 {
 940
 941         ahd->chip = AHD_AIC7901A;
 942         ahd->features = AHD_AIC7901A_FE;
 943         return (ahd_aic790X_setup(ahd));
 944 }
 945
 946 static int
 947 ahd_aic7902_setup(struct ahd_softc *ahd)
 948 {
 949         ahd->chip = AHD_AIC7902;
 950         ahd->features = AHD_AIC7902_FE;
 951         return (ahd_aic790X_setup(ahd));
 952 }
 953
 954 static int
 955 ahd_aic790X_setup(struct ahd_softc *ahd)
 956 {
 957         aic_dev_softc_t pci;
 958         u_int rev;
 959
 960         pci = ahd->dev_softc;
 961         rev = aic_pci_read_config(pci, PCIR_REVID, /*bytes*/1);
 962         if (rev < ID_AIC7902_PCI_REV_A4) {
 963                 kprintf("%s: Unable to attach to unsupported chip revision %d\n",
 964                        ahd_name(ahd), rev);
 965                 aic_pci_write_config(pci, PCIR_COMMAND, 0, /*bytes*/2);
 966                 return (ENXIO);
 967         }
 968         ahd->channel = aic_get_pci_function(pci) + 'A';
 969         if (rev < ID_AIC7902_PCI_REV_B0) {
 970                 /*
 971                  * Enable A series workarounds.
 972                  */
 973                 ahd->bugs |= AHD_SENT_SCB_UPDATE_BUG|AHD_ABORT_LQI_BUG
 974                           |  AHD_PKT_BITBUCKET_BUG|AHD_LONG_SETIMO_BUG
 975                           |  AHD_NLQICRC_DELAYED_BUG|AHD_SCSIRST_BUG
 976                           |  AHD_LQO_ATNO_BUG|AHD_AUTOFLUSH_BUG
 977                           |  AHD_CLRLQO_AUTOCLR_BUG|AHD_PCIX_MMAPIO_BUG
 978                           |  AHD_PCIX_CHIPRST_BUG|AHD_PCIX_SCBRAM_RD_BUG
 979                           |  AHD_PKTIZED_STATUS_BUG|AHD_PKT_LUN_BUG
 980                           |  AHD_MDFF_WSCBPTR_BUG|AHD_REG_SLOW_SETTLE_BUG
 981                           |  AHD_SET_MODE_BUG|AHD_BUSFREEREV_BUG
 982                           |  AHD_NONPACKFIFO_BUG|AHD_PACED_NEGTABLE_BUG
 983                           |  AHD_FAINT_LED_BUG;
 984
 985                 /*
 986                  * IO Cell paramter setup.
 987                  */
 988                 AHD_SET_PRECOMP(ahd, AHD_PRECOMP_CUTBACK_29);
 989
 990                 if ((ahd->flags & AHD_HP_BOARD) == 0)
 991                         AHD_SET_SLEWRATE(ahd, AHD_SLEWRATE_DEF_REVA);
 992         } else {
 993                 u_int devconfig1;
 994
 995                 ahd->features |= AHD_RTI|AHD_NEW_IOCELL_OPTS
 996                               |  AHD_NEW_DFCNTRL_OPTS|AHD_FAST_CDB_DELIVERY;
 997                 ahd->bugs |= AHD_LQOOVERRUN_BUG|AHD_EARLY_REQ_BUG;
 998
 999                 /*
1000                  * Some issues have been resolved in the 7901B.
1001                  */
1002                 if ((ahd->features & AHD_MULTI_FUNC) != 0)
1003                         ahd->bugs |= AHD_INTCOLLISION_BUG|AHD_ABORT_LQI_BUG
1004                                   |  AHD_BUSFREEREV_BUG;
1005
1006                 /*
1007                  * IO Cell paramter setup.
1008                  */
1009                 AHD_SET_PRECOMP(ahd, AHD_PRECOMP_CUTBACK_29);
1010                 AHD_SET_SLEWRATE(ahd, AHD_SLEWRATE_DEF_REVB);
1011                 AHD_SET_AMPLITUDE(ahd, AHD_AMPLITUDE_DEF);
1012
1013                 /*
1014                  * Set the PREQDIS bit for H2B which disables some workaround
1015                  * that doesn't work on regular PCI busses.
1016                  * XXX - Find out exactly what this does from the hardware
1017                  *       folks!
1018                  */
1019                 devconfig1 = aic_pci_read_config(pci, DEVCONFIG1, /*bytes*/1);
1020                 aic_pci_write_config(pci, DEVCONFIG1,
1021                                      devconfig1|PREQDIS, /*bytes*/1);
1022                 devconfig1 = aic_pci_read_config(pci, DEVCONFIG1, /*bytes*/1);
1023         }
1024
1025         return (0);
1026 }