4 * Copyright (c) 2006 David Gwynne <dlg@openbsd.org>
6 * Permission to use, copy, modify, and distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
19 * Copyright (c) 2009 The DragonFly Project. All rights reserved.
21 * This code is derived from software contributed to The DragonFly Project
22 * by Matthew Dillon <dillon@backplane.com>
24 * Redistribution and use in source and binary forms, with or without
25 * modification, are permitted provided that the following conditions
28 * 1. Redistributions of source code must retain the above copyright
29 * notice, this list of conditions and the following disclaimer.
30 * 2. Redistributions in binary form must reproduce the above copyright
31 * notice, this list of conditions and the following disclaimer in
32 * the documentation and/or other materials provided with the
34 * 3. Neither the name of The DragonFly Project nor the names of its
35 * contributors may be used to endorse or promote products derived
36 * from this software without specific, prior written permission.
38 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
39 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
40 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
41 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
42 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
43 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
44 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
45 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
46 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
47 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
48 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
51 * $OpenBSD: ahci.c,v 1.147 2009/02/16 21:19:07 miod Exp $
56 static int ahci_vt8251_attach(device_t);
57 static int ahci_ati_sb600_attach(device_t);
58 static int ahci_nvidia_mcp_attach(device_t);
59 static int ahci_pci_attach(device_t);
60 static int ahci_pci_detach(device_t);
62 static const struct ahci_device ahci_devices[] = {
63 { PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VT8251_SATA,
64 ahci_vt8251_attach, ahci_pci_detach, "ViaTech-VT8251-SATA" },
65 { PCI_VENDOR_ATI, PCI_PRODUCT_ATI_SB600_SATA,
66 ahci_ati_sb600_attach, ahci_pci_detach, "ATI-SB600-SATA" },
67 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_AHCI_2,
68 ahci_nvidia_mcp_attach, ahci_pci_detach, "NVidia-MCP65-SATA" },
69 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_AHCI_1,
70 ahci_nvidia_mcp_attach, ahci_pci_detach, "NVidia-MCP67-SATA" },
71 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_AHCI_5,
72 ahci_nvidia_mcp_attach, ahci_pci_detach, "NVidia-MCP77-SATA" },
74 ahci_pci_attach, ahci_pci_detach, "AHCI-PCI-SATA" }
78 * Match during probe and attach. The device does not yet have a softc.
80 const struct ahci_device *
81 ahci_lookup_device(device_t dev)
83 const struct ahci_device *ad;
84 u_int16_t vendor = pci_get_vendor(dev);
85 u_int16_t product = pci_get_device(dev);
86 u_int8_t class = pci_get_class(dev);
87 u_int8_t subclass = pci_get_subclass(dev);
88 u_int8_t progif = pci_read_config(dev, PCIR_PROGIF, 1);
92 * Generally speaking if the pci device does not identify as
95 if (class == PCIC_STORAGE && subclass == PCIS_STORAGE_SATA &&
96 progif == PCIP_STORAGE_SATA_AHCI_1_0) {
102 for (ad = &ahci_devices[0]; ad->ad_vendor; ++ad) {
103 if (ad->ad_vendor == vendor && ad->ad_product == product)
108 * Last ad is the default match if the PCI device matches SATA.
116 * Attach functions. They all eventually fall through to ahci_pci_attach().
119 ahci_vt8251_attach(device_t dev)
121 struct ahci_softc *sc = device_get_softc(dev);
123 sc->sc_flags |= AHCI_F_NO_NCQ;
124 return (ahci_pci_attach(dev));
128 ahci_ati_sb600_attach(device_t dev)
130 struct ahci_softc *sc = device_get_softc(dev);
132 u_int8_t subclass = pci_get_subclass(dev);
135 if (subclass == PCIS_STORAGE_IDE) {
136 revid = pci_read_config(dev, PCIR_REVID, 1);
137 magic = pci_read_config(dev, AHCI_PCI_ATI_SB600_MAGIC, 4);
138 pci_write_config(dev, AHCI_PCI_ATI_SB600_MAGIC,
139 magic | AHCI_PCI_ATI_SB600_LOCKED, 4);
140 pci_write_config(dev, PCIR_REVID,
141 (PCIC_STORAGE << 24) |
142 (PCIS_STORAGE_SATA << 16) |
143 (PCIP_STORAGE_SATA_AHCI_1_0 << 8) |
145 pci_write_config(dev, AHCI_PCI_ATI_SB600_MAGIC, magic, 4);
148 sc->sc_flags |= AHCI_F_IGN_FR;
149 return (ahci_pci_attach(dev));
153 ahci_nvidia_mcp_attach(device_t dev)
155 struct ahci_softc *sc = device_get_softc(dev);
157 sc->sc_flags |= AHCI_F_IGN_FR;
158 return (ahci_pci_attach(dev));
162 ahci_pci_attach(device_t dev)
164 struct ahci_softc *sc = device_get_softc(dev);
165 struct ahci_port *ap;
167 u_int32_t cap, pi, reg;
171 const char *revision;
173 if (pci_read_config(dev, PCIR_COMMAND, 2) & 0x0400) {
174 device_printf(dev, "BIOS disabled PCI interrupt, "
176 pci_write_config(dev, PCIR_COMMAND,
177 pci_read_config(dev, PCIR_COMMAND, 2) & ~0x0400, 2);
182 * Map the AHCI controller's IRQ and BAR(5) (hardware registers)
185 sc->sc_rid_irq = AHCI_IRQ_RID;
186 sc->sc_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->sc_rid_irq,
187 RF_SHAREABLE | RF_ACTIVE);
188 if (sc->sc_irq == NULL) {
189 device_printf(dev, "unable to map interrupt\n");
190 ahci_pci_detach(dev);
195 * When mapping the register window store the tag and handle
196 * separately so we can use the tag with per-port bus handle
199 sc->sc_rid_regs = PCIR_BAR(5);
200 sc->sc_regs = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
201 &sc->sc_rid_regs, RF_ACTIVE);
202 if (sc->sc_regs == NULL) {
203 device_printf(dev, "unable to map registers\n");
204 ahci_pci_detach(dev);
207 sc->sc_iot = rman_get_bustag(sc->sc_regs);
208 sc->sc_ioh = rman_get_bushandle(sc->sc_regs);
211 * Initialize the chipset and then set the interrupt vector up
213 error = ahci_init(sc);
215 ahci_pci_detach(dev);
220 * Get the AHCI capabilities and max number of concurrent
221 * command tags and set up the DMA tags.
223 cap = ahci_read(sc, AHCI_REG_CAP);
224 if (sc->sc_flags & AHCI_F_NO_NCQ)
225 cap &= ~AHCI_REG_CAP_SNCQ;
229 * We assume at least 4 commands.
231 sc->sc_ncmds = AHCI_REG_CAP_NCS(cap);
232 if (sc->sc_ncmds < 4) {
233 device_printf(dev, "NCS must probe a value >= 4\n");
234 ahci_pci_detach(dev);
238 addr = (cap & AHCI_REG_CAP_S64A) ?
239 BUS_SPACE_MAXADDR : BUS_SPACE_MAXADDR_32BIT;
242 * DMA tags for allocation of DMA memory buffers, lists, and so
243 * forth. These are typically per-port.
246 error += bus_dma_tag_create(
247 NULL, /* parent tag */
249 PAGE_SIZE, /* boundary */
251 BUS_SPACE_MAXADDR, /* hiaddr */
253 NULL, /* filterarg */
254 sizeof(struct ahci_rfis), /* [max]size */
256 sizeof(struct ahci_rfis), /* maxsegsz */
258 &sc->sc_tag_rfis); /* return tag */
260 error += bus_dma_tag_create(
261 NULL, /* parent tag */
263 4096 * 1024, /* boundary */
265 BUS_SPACE_MAXADDR, /* hiaddr */
267 NULL, /* filterarg */
268 sc->sc_ncmds * sizeof(struct ahci_cmd_hdr),
270 sc->sc_ncmds * sizeof(struct ahci_cmd_hdr),
272 &sc->sc_tag_cmdh); /* return tag */
275 * NOTE: ahci_cmd_table is sized to a power of 2
277 error += bus_dma_tag_create(
278 NULL, /* parent tag */
279 sizeof(struct ahci_cmd_table), /* alignment */
280 4096 * 1024, /* boundary */
282 BUS_SPACE_MAXADDR, /* hiaddr */
284 NULL, /* filterarg */
285 sc->sc_ncmds * sizeof(struct ahci_cmd_table),
287 sc->sc_ncmds * sizeof(struct ahci_cmd_table),
289 &sc->sc_tag_cmdt); /* return tag */
292 * The data tag is used for later dmamaps and not immediately
295 error += bus_dma_tag_create(
296 NULL, /* parent tag */
300 BUS_SPACE_MAXADDR, /* hiaddr */
302 NULL, /* filterarg */
303 4096 * 1024, /* maxiosize */
304 AHCI_MAX_PRDT, /* maxsegs */
305 65536, /* maxsegsz */
307 &sc->sc_tag_data); /* return tag */
310 device_printf(dev, "unable to create dma tags\n");
311 ahci_pci_detach(dev);
315 switch (cap & AHCI_REG_CAP_ISS) {
316 case AHCI_REG_CAP_ISS_G1:
319 case AHCI_REG_CAP_ISS_G2:
322 case AHCI_REG_CAP_ISS_G3:
330 /* check the revision */
331 reg = ahci_read(sc, AHCI_REG_VS);
333 case AHCI_REG_VS_0_95:
334 revision = "AHCI 0.95";
336 case AHCI_REG_VS_1_0:
337 revision = "AHCI 1.0";
339 case AHCI_REG_VS_1_1:
340 revision = "AHCI 1.1";
342 case AHCI_REG_VS_1_2:
343 revision = "AHCI 1.2";
345 case AHCI_REG_VS_1_3:
346 revision = "AHCI 1.3";
348 case AHCI_REG_VS_1_4:
349 revision = "AHCI 1.4";
351 case AHCI_REG_VS_1_5:
352 revision = "AHCI 1.5"; /* future will catch up to us */
355 device_printf(sc->sc_dev,
356 "Warning: Unknown AHCI revision 0x%08x\n", reg);
357 revision = "AHCI <unknown>";
362 "%s capabilities 0x%b, %d ports, %d tags/port, gen %s\n",
365 AHCI_REG_CAP_NP(cap), sc->sc_ncmds, gen);
367 pi = ahci_read(sc, AHCI_REG_PI);
368 DPRINTF(AHCI_D_VERBOSE, "%s: ports implemented: 0x%08x\n",
372 /* Naive coalescing support - enable for all ports. */
373 if (cap & AHCI_REG_CAP_CCCS) {
374 u_int16_t ccc_timeout = 20;
375 u_int8_t ccc_numcomplete = 12;
378 /* disable coalescing during reconfiguration. */
379 ccc_ctl = ahci_read(sc, AHCI_REG_CCC_CTL);
380 ccc_ctl &= ~0x00000001;
381 ahci_write(sc, AHCI_REG_CCC_CTL, ccc_ctl);
383 sc->sc_ccc_mask = 1 << AHCI_REG_CCC_CTL_INT(ccc_ctl);
384 if (pi & sc->sc_ccc_mask) {
385 /* A conflict with the implemented port list? */
386 printf("%s: coalescing interrupt/implemented port list "
387 "conflict, PI: %08x, ccc_mask: %08x\n",
388 DEVNAME(sc), pi, sc->sc_ccc_mask);
393 /* ahci_port_start will enable each port when it starts. */
394 sc->sc_ccc_ports = pi;
395 sc->sc_ccc_ports_cur = 0;
397 /* program thresholds and enable overall coalescing. */
398 ccc_ctl &= ~0xffffff00;
399 ccc_ctl |= (ccc_timeout << 16) | (ccc_numcomplete << 8);
400 ahci_write(sc, AHCI_REG_CCC_CTL, ccc_ctl);
401 ahci_write(sc, AHCI_REG_CCC_PORTS, 0);
402 ahci_write(sc, AHCI_REG_CCC_CTL, ccc_ctl | 1);
407 * Allocate per-port resources
409 * Ignore attach errors, leave the port intact for
410 * rescan and continue the loop.
412 * All ports are attached in parallel but the CAM scan-bus
413 * is held up until all ports are attached so we get a deterministic
416 for (i = 0; error == 0 && i < AHCI_MAX_PORTS; i++) {
417 if ((pi & (1 << i)) == 0) {
418 /* dont allocate stuff if the port isnt implemented */
421 error = ahci_port_alloc(sc, i);
425 * Setup the interrupt vector and enable interrupts. Note that
426 * since the irq may be shared we do not set it up until we are
430 error = bus_setup_intr(dev, sc->sc_irq, INTR_MPSAFE,
432 &sc->sc_irq_handle, NULL);
436 device_printf(dev, "unable to install interrupt\n");
437 ahci_pci_detach(dev);
442 * Before marking the sc as good, which allows the interrupt
443 * subsystem to operate on the ports, wait for all the port threads
444 * to get past their initial pre-probe init. Otherwise an interrupt
445 * may try to process the port before it has been initialized.
447 for (i = 0; i < AHCI_MAX_PORTS; i++) {
448 if ((ap = sc->sc_ports[i]) != NULL) {
449 while (ap->ap_signal & AP_SIGF_THREAD_SYNC)
450 tsleep(&ap->ap_signal, 0, "ahprb1", hz);
455 * Master interrupt enable, and call ahci_intr() in case we race
456 * our AHCI_F_INT_GOOD flag.
459 ahci_write(sc, AHCI_REG_GHC, AHCI_REG_GHC_AE | AHCI_REG_GHC_IE);
460 sc->sc_flags |= AHCI_F_INT_GOOD;
465 * All ports are probing in parallel. Wait for them to finish
466 * and then issue the cam attachment and bus scan serially so
467 * the 'da' assignments are deterministic.
469 for (i = 0; i < AHCI_MAX_PORTS; i++) {
470 if ((ap = sc->sc_ports[i]) != NULL) {
471 while (ap->ap_signal & AP_SIGF_INIT)
472 tsleep(&ap->ap_signal, 0, "ahprb2", hz);
473 ahci_os_lock_port(ap);
474 if (ahci_cam_attach(ap) == 0) {
475 ahci_cam_changed(ap, NULL, -1);
476 ahci_os_unlock_port(ap);
477 while ((ap->ap_flags & AP_F_SCAN_COMPLETED) == 0) {
478 tsleep(&ap->ap_flags, 0, "ahprb2", hz);
481 ahci_os_unlock_port(ap);
490 * Device unload / detachment
493 ahci_pci_detach(device_t dev)
495 struct ahci_softc *sc = device_get_softc(dev);
496 struct ahci_port *ap;
500 * Disable the controller and de-register the interrupt, if any.
502 * XXX interlock last interrupt?
504 sc->sc_flags &= ~AHCI_F_INT_GOOD;
506 ahci_write(sc, AHCI_REG_GHC, 0);
508 if (sc->sc_irq_handle) {
509 bus_teardown_intr(dev, sc->sc_irq, sc->sc_irq_handle);
510 sc->sc_irq_handle = NULL;
514 * Free port structures and DMA memory
516 for (i = 0; i < AHCI_MAX_PORTS; i++) {
517 ap = sc->sc_ports[i];
520 ahci_port_free(sc, i);
525 * Clean up the bus space
528 bus_release_resource(dev, SYS_RES_IRQ,
529 sc->sc_rid_irq, sc->sc_irq);
533 bus_release_resource(dev, SYS_RES_MEMORY,
534 sc->sc_rid_regs, sc->sc_regs);
538 if (sc->sc_tag_rfis) {
539 bus_dma_tag_destroy(sc->sc_tag_rfis);
540 sc->sc_tag_rfis = NULL;
542 if (sc->sc_tag_cmdh) {
543 bus_dma_tag_destroy(sc->sc_tag_cmdh);
544 sc->sc_tag_cmdh = NULL;
546 if (sc->sc_tag_cmdt) {
547 bus_dma_tag_destroy(sc->sc_tag_cmdt);
548 sc->sc_tag_cmdt = NULL;
550 if (sc->sc_tag_data) {
551 bus_dma_tag_destroy(sc->sc_tag_data);
552 sc->sc_tag_data = NULL;