2 * Copyright (c) 1996, by Steve Passe
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. The name of the developer may NOT be used to endorse or promote products
11 * derived from this software without specific prior written permission.
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * $FreeBSD: src/sys/i386/i386/mp_machdep.c,v 1.115.2.15 2003/03/14 21:22:35 jhb Exp $
30 #include <sys/param.h>
31 #include <sys/systm.h>
32 #include <sys/kernel.h>
33 #include <sys/sysctl.h>
34 #include <sys/malloc.h>
35 #include <sys/memrange.h>
36 #include <sys/cons.h> /* cngetc() */
37 #include <sys/machintr.h>
38 #include <sys/cpu_topology.h>
40 #include <sys/mplock2.h>
43 #include <vm/vm_param.h>
45 #include <vm/vm_kern.h>
46 #include <vm/vm_extern.h>
48 #include <vm/vm_map.h>
54 #include <machine/smp.h>
55 #include <machine_base/apic/apicreg.h>
56 #include <machine/atomic.h>
57 #include <machine/cpufunc.h>
58 #include <machine/cputypes.h>
59 #include <machine_base/apic/lapic.h>
60 #include <machine_base/apic/ioapic.h>
61 #include <machine_base/acpica/acpi_md_cpu.h>
62 #include <machine/psl.h>
63 #include <machine/segments.h>
64 #include <machine/tss.h>
65 #include <machine/specialreg.h>
66 #include <machine/globaldata.h>
67 #include <machine/pmap_inval.h>
69 #include <machine/md_var.h> /* setidt() */
70 #include <machine_base/icu/icu.h> /* IPIs */
71 #include <machine_base/icu/icu_var.h>
72 #include <machine_base/apic/ioapic_abi.h>
73 #include <machine/intr_machdep.h> /* IPIs */
75 #define WARMBOOT_TARGET 0
76 #define WARMBOOT_OFF (KERNBASE + 0x0467)
77 #define WARMBOOT_SEG (KERNBASE + 0x0469)
79 #define CMOS_REG (0x70)
80 #define CMOS_DATA (0x71)
81 #define BIOS_RESET (0x0f)
82 #define BIOS_WARM (0x0a)
85 * this code MUST be enabled here and in mpboot.s.
86 * it follows the very early stages of AP boot by placing values in CMOS ram.
87 * it NORMALLY will never be needed and thus the primitive method for enabling.
90 #if defined(CHECK_POINTS)
91 #define CHECK_READ(A) (outb(CMOS_REG, (A)), inb(CMOS_DATA))
92 #define CHECK_WRITE(A,D) (outb(CMOS_REG, (A)), outb(CMOS_DATA, (D)))
94 #define CHECK_INIT(D); \
95 CHECK_WRITE(0x34, (D)); \
96 CHECK_WRITE(0x35, (D)); \
97 CHECK_WRITE(0x36, (D)); \
98 CHECK_WRITE(0x37, (D)); \
99 CHECK_WRITE(0x38, (D)); \
100 CHECK_WRITE(0x39, (D));
102 #define CHECK_PRINT(S); \
103 kprintf("%s: %d, %d, %d, %d, %d, %d\n", \
112 #else /* CHECK_POINTS */
114 #define CHECK_INIT(D)
115 #define CHECK_PRINT(S)
117 #endif /* CHECK_POINTS */
120 * Values to send to the POST hardware.
122 #define MP_BOOTADDRESS_POST 0x10
123 #define MP_PROBE_POST 0x11
124 #define MPTABLE_PASS1_POST 0x12
126 #define MP_START_POST 0x13
127 #define MP_ENABLE_POST 0x14
128 #define MPTABLE_PASS2_POST 0x15
130 #define START_ALL_APS_POST 0x16
131 #define INSTALL_AP_TRAMP_POST 0x17
132 #define START_AP_POST 0x18
134 #define MP_ANNOUNCE_POST 0x19
136 /** XXX FIXME: where does this really belong, isa.h/isa.c perhaps? */
137 int current_postcode;
139 /** XXX FIXME: what system files declare these??? */
140 extern struct region_descriptor r_gdt;
146 extern int64_t tsc_offsets[];
148 /* AP uses this during bootstrap. Do not staticize. */
152 struct pcb stoppcbs[MAXCPU];
154 extern inthand_t IDTVEC(fast_syscall), IDTVEC(fast_syscall32);
157 * Local data and functions.
160 static u_int boot_address;
161 static int mp_finish;
162 static int mp_finish_lapic;
164 static int start_all_aps(u_int boot_addr);
166 static void install_ap_tramp(u_int boot_addr);
168 static int start_ap(struct mdglobaldata *gd, u_int boot_addr, int smibest);
169 static int smitest(void);
170 static void mp_bsp_simple_setup(void);
172 /* which cpus have been started */
173 static cpumask_t smp_startup_mask = CPUMASK_INITIALIZER_ONLYONE;
174 /* which cpus have lapic been inited */
175 static cpumask_t smp_lapic_mask = CPUMASK_INITIALIZER_ONLYONE;
176 /* which cpus are ready for IPIs etc? */
177 cpumask_t smp_active_mask = CPUMASK_INITIALIZER_ONLYONE;
178 cpumask_t smp_finalize_mask = CPUMASK_INITIALIZER_ONLYONE;
180 SYSCTL_INT(_machdep, OID_AUTO, smp_active, CTLFLAG_RD, &smp_active_mask, 0, "");
181 static u_int bootMP_size;
182 static u_int report_invlpg_src;
183 SYSCTL_INT(_machdep, OID_AUTO, report_invlpg_src, CTLFLAG_RW,
184 &report_invlpg_src, 0, "");
185 static u_int report_invltlb_src;
186 SYSCTL_INT(_machdep, OID_AUTO, report_invltlb_src, CTLFLAG_RW,
187 &report_invltlb_src, 0, "");
189 /* Local data for detecting CPU TOPOLOGY */
190 static int core_bits = 0;
191 static int logical_CPU_bits = 0;
195 * Calculate usable address in base memory for AP trampoline code.
198 mp_bootaddress(u_int basemem)
200 POSTCODE(MP_BOOTADDRESS_POST);
202 bootMP_size = mptramp_end - mptramp_start;
203 boot_address = trunc_page(basemem * 1024); /* round down to 4k boundary */
204 if (((basemem * 1024) - boot_address) < bootMP_size)
205 boot_address -= PAGE_SIZE; /* not enough, lower by 4k */
206 /* 3 levels of page table pages */
207 mptramp_pagetables = boot_address - (PAGE_SIZE * 3);
209 return mptramp_pagetables;
213 * Print various information about the SMP system hardware and setup.
220 POSTCODE(MP_ANNOUNCE_POST);
222 kprintf("DragonFly/MP: Multiprocessor motherboard\n");
223 kprintf(" cpu0 (BSP): apic id: %2d\n", CPUID_TO_APICID(0));
224 for (x = 1; x <= naps; ++x)
225 kprintf(" cpu%d (AP): apic id: %2d\n", x, CPUID_TO_APICID(x));
228 kprintf(" Warning: APIC I/O disabled\n");
232 * AP cpu's call this to sync up protected mode.
234 * WARNING! %gs is not set up on entry. This routine sets up %gs.
240 int x, myid = bootAP;
242 struct mdglobaldata *md;
243 struct privatespace *ps;
245 ps = CPU_prvspace[myid];
247 gdt_segs[GPROC0_SEL].ssd_base =
248 (long) &ps->mdglobaldata.gd_common_tss;
249 ps->mdglobaldata.mi.gd_prvspace = ps;
251 /* We fill the 32-bit segment descriptors */
252 for (x = 0; x < NGDT; x++) {
253 if (x != GPROC0_SEL && x != (GPROC0_SEL + 1))
254 ssdtosd(&gdt_segs[x], &gdt[myid * NGDT + x]);
256 /* And now a 64-bit one */
257 ssdtosyssd(&gdt_segs[GPROC0_SEL],
258 (struct system_segment_descriptor *)&gdt[myid * NGDT + GPROC0_SEL]);
260 r_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1;
261 r_gdt.rd_base = (long) &gdt[myid * NGDT];
262 lgdt(&r_gdt); /* does magic intra-segment return */
264 /* lgdt() destroys the GSBASE value, so we load GSBASE after lgdt() */
265 wrmsr(MSR_FSBASE, 0); /* User value */
266 wrmsr(MSR_GSBASE, (u_int64_t)ps);
267 wrmsr(MSR_KGSBASE, 0); /* XXX User value while we're in the kernel */
269 lidt(&r_idt_arr[mdcpu->mi.gd_cpuid]);
273 mdcpu->gd_currentldt = _default_ldt;
276 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL);
277 gdt[myid * NGDT + GPROC0_SEL].sd_type = SDT_SYSTSS;
279 md = mdcpu; /* loaded through %gs:0 (mdglobaldata.mi.gd_prvspace)*/
281 md->gd_common_tss.tss_rsp0 = 0; /* not used until after switch */
283 md->gd_common_tss.tss_ioopt = (sizeof md->gd_common_tss) << 16;
285 md->gd_tss_gdt = &gdt[myid * NGDT + GPROC0_SEL];
286 md->gd_common_tssd = *md->gd_tss_gdt;
288 /* double fault stack */
289 md->gd_common_tss.tss_ist1 =
290 (long)&md->mi.gd_prvspace->idlestack[
291 sizeof(md->mi.gd_prvspace->idlestack)];
296 * Set to a known state:
297 * Set by mpboot.s: CR0_PG, CR0_PE
298 * Set by cpu_setregs: CR0_NE, CR0_MP, CR0_TS, CR0_WP, CR0_AM
301 cr0 &= ~(CR0_CD | CR0_NW | CR0_EM);
304 /* Set up the fast syscall stuff */
305 msr = rdmsr(MSR_EFER) | EFER_SCE;
306 wrmsr(MSR_EFER, msr);
307 wrmsr(MSR_LSTAR, (u_int64_t)IDTVEC(fast_syscall));
308 wrmsr(MSR_CSTAR, (u_int64_t)IDTVEC(fast_syscall32));
309 msr = ((u_int64_t)GSEL(GCODE_SEL, SEL_KPL) << 32) |
310 ((u_int64_t)GSEL(GUCODE32_SEL, SEL_UPL) << 48);
311 wrmsr(MSR_STAR, msr);
312 wrmsr(MSR_SF_MASK, PSL_NT|PSL_T|PSL_I|PSL_C|PSL_D|PSL_IOPL);
314 pmap_set_opt(); /* PSE/4MB pages, etc */
315 pmap_init_pat(); /* Page Attribute Table */
317 /* set up CPU registers and state */
320 /* set up SSE/NX registers */
323 /* set up FPU state on the AP */
326 /* disable the APIC, just to be SURE */
327 lapic->svr &= ~APIC_SVR_ENABLE;
330 /*******************************************************************
331 * local functions and data
335 * Start the SMP system
338 mp_start_aps(void *dummy __unused)
341 /* start each Application Processor */
342 start_all_aps(boot_address);
344 mp_bsp_simple_setup();
347 SYSINIT(startaps, SI_BOOT2_START_APS, SI_ORDER_FIRST, mp_start_aps, NULL);
350 * start each AP in our list
353 start_all_aps(u_int boot_addr)
355 vm_offset_t va = boot_address + KERNBASE;
356 u_int64_t *pt4, *pt3, *pt2;
364 u_long mpbioswarmvec;
365 struct mdglobaldata *gd;
366 struct privatespace *ps;
369 POSTCODE(START_ALL_APS_POST);
371 /* install the AP 1st level boot code */
372 pmap_kenter(va, boot_address);
373 cpu_invlpg((void *)va); /* JG XXX */
374 bcopy(mptramp_start, (void *)va, bootMP_size);
376 /* Locate the page tables, they'll be below the trampoline */
377 pt4 = (u_int64_t *)(uintptr_t)(mptramp_pagetables + KERNBASE);
378 pt3 = pt4 + (PAGE_SIZE) / sizeof(u_int64_t);
379 pt2 = pt3 + (PAGE_SIZE) / sizeof(u_int64_t);
381 /* Create the initial 1GB replicated page tables */
382 for (i = 0; i < 512; i++) {
383 /* Each slot of the level 4 pages points to the same level 3 page */
384 pt4[i] = (u_int64_t)(uintptr_t)(mptramp_pagetables + PAGE_SIZE);
385 pt4[i] |= kernel_pmap.pmap_bits[PG_V_IDX] |
386 kernel_pmap.pmap_bits[PG_RW_IDX] |
387 kernel_pmap.pmap_bits[PG_U_IDX];
389 /* Each slot of the level 3 pages points to the same level 2 page */
390 pt3[i] = (u_int64_t)(uintptr_t)(mptramp_pagetables + (2 * PAGE_SIZE));
391 pt3[i] |= kernel_pmap.pmap_bits[PG_V_IDX] |
392 kernel_pmap.pmap_bits[PG_RW_IDX] |
393 kernel_pmap.pmap_bits[PG_U_IDX];
395 /* The level 2 page slots are mapped with 2MB pages for 1GB. */
396 pt2[i] = i * (2 * 1024 * 1024);
397 pt2[i] |= kernel_pmap.pmap_bits[PG_V_IDX] |
398 kernel_pmap.pmap_bits[PG_RW_IDX] |
399 kernel_pmap.pmap_bits[PG_PS_IDX] |
400 kernel_pmap.pmap_bits[PG_U_IDX];
403 /* save the current value of the warm-start vector */
404 mpbioswarmvec = *((u_int32_t *) WARMBOOT_OFF);
405 outb(CMOS_REG, BIOS_RESET);
406 mpbiosreason = inb(CMOS_DATA);
408 /* setup a vector to our boot code */
409 *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET;
410 *((volatile u_short *) WARMBOOT_SEG) = (boot_address >> 4);
411 outb(CMOS_REG, BIOS_RESET);
412 outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */
415 * If we have a TSC we can figure out the SMI interrupt rate.
416 * The SMI does not necessarily use a constant rate. Spend
417 * up to 250ms trying to figure it out.
420 if (cpu_feature & CPUID_TSC) {
421 set_apic_timer(275000);
422 smilast = read_apic_timer();
423 for (x = 0; x < 20 && read_apic_timer(); ++x) {
424 smicount = smitest();
425 if (smibest == 0 || smilast - smicount < smibest)
426 smibest = smilast - smicount;
429 if (smibest > 250000)
432 smibest = smibest * (int64_t)1000000 /
433 get_apic_timer_frequency();
437 kprintf("SMI Frequency (worst case): %d Hz (%d us)\n",
438 1000000 / smibest, smibest);
441 for (x = 1; x <= naps; ++x) {
442 /* This is a bit verbose, it will go away soon. */
444 pssize = sizeof(struct privatespace);
445 ps = (void *)kmem_alloc(&kernel_map, pssize);
446 CPU_prvspace[x] = ps;
448 kprintf("ps %d %p %d\n", x, ps, pssize);
451 gd = &ps->mdglobaldata;
452 gd->mi.gd_prvspace = ps;
454 /* prime data page for it to use */
455 mi_gdinit(&gd->mi, x);
457 ipiq_size = sizeof(struct lwkt_ipiq) * (naps + 1);
458 gd->mi.gd_ipiq = (void *)kmem_alloc(&kernel_map, ipiq_size);
459 bzero(gd->mi.gd_ipiq, ipiq_size);
461 gd->gd_acpi_id = CPUID_TO_ACPIID(gd->mi.gd_cpuid);
463 /* setup a vector to our boot code */
464 *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET;
465 *((volatile u_short *) WARMBOOT_SEG) = (boot_addr >> 4);
466 outb(CMOS_REG, BIOS_RESET);
467 outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */
470 * Setup the AP boot stack
472 bootSTK = &ps->idlestack[UPAGES * PAGE_SIZE - PAGE_SIZE];
475 /* attempt to start the Application Processor */
476 CHECK_INIT(99); /* setup checkpoints */
477 if (!start_ap(gd, boot_addr, smibest)) {
478 kprintf("\nAP #%d (PHY# %d) failed!\n",
479 x, CPUID_TO_APICID(x));
480 CHECK_PRINT("trace"); /* show checkpoints */
481 /* better panic as the AP may be running loose */
482 kprintf("panic y/n? [y] ");
488 CHECK_PRINT("trace"); /* show checkpoints */
491 /* set ncpus to 1 + highest logical cpu. Not all may have come up */
494 /* ncpus2 -- ncpus rounded down to the nearest power of 2 */
495 for (shift = 0; (1 << shift) <= ncpus; ++shift)
498 ncpus2_shift = shift;
500 ncpus2_mask = ncpus2 - 1;
502 /* ncpus_fit -- ncpus rounded up to the nearest power of 2 */
503 if ((1 << shift) < ncpus)
505 ncpus_fit = 1 << shift;
506 ncpus_fit_mask = ncpus_fit - 1;
508 /* build our map of 'other' CPUs */
509 mycpu->gd_other_cpus = smp_startup_mask;
510 CPUMASK_NANDBIT(mycpu->gd_other_cpus, mycpu->gd_cpuid);
512 gd = (struct mdglobaldata *)mycpu;
513 gd->gd_acpi_id = CPUID_TO_ACPIID(mycpu->gd_cpuid);
515 ipiq_size = sizeof(struct lwkt_ipiq) * ncpus;
516 mycpu->gd_ipiq = (void *)kmem_alloc(&kernel_map, ipiq_size);
517 bzero(mycpu->gd_ipiq, ipiq_size);
519 /* restore the warmstart vector */
520 *(u_long *) WARMBOOT_OFF = mpbioswarmvec;
521 outb(CMOS_REG, BIOS_RESET);
522 outb(CMOS_DATA, mpbiosreason);
525 * NOTE! The idlestack for the BSP was setup by locore. Finish
526 * up, clean out the P==V mapping we did earlier.
531 * Wait all APs to finish initializing LAPIC
534 kprintf("SMP: Waiting APs LAPIC initialization\n");
535 if (cpu_feature & CPUID_TSC)
536 tsc0_offset = rdtsc();
541 while (CPUMASK_CMPMASKNEQ(smp_lapic_mask, smp_startup_mask)) {
544 if (cpu_feature & CPUID_TSC)
545 tsc0_offset = rdtsc();
547 while (try_mplock() == 0) {
552 /* number of APs actually started */
558 * load the 1st level AP boot code into base memory.
561 /* targets for relocation */
562 extern void bigJump(void);
563 extern void bootCodeSeg(void);
564 extern void bootDataSeg(void);
565 extern void MPentry(void);
567 extern u_int mp_gdtbase;
572 install_ap_tramp(u_int boot_addr)
575 int size = *(int *) ((u_long) & bootMP_size);
576 u_char *src = (u_char *) ((u_long) bootMP);
577 u_char *dst = (u_char *) boot_addr + KERNBASE;
578 u_int boot_base = (u_int) bootMP;
583 POSTCODE(INSTALL_AP_TRAMP_POST);
585 for (x = 0; x < size; ++x)
589 * modify addresses in code we just moved to basemem. unfortunately we
590 * need fairly detailed info about mpboot.s for this to work. changes
591 * to mpboot.s might require changes here.
594 /* boot code is located in KERNEL space */
595 dst = (u_char *) boot_addr + KERNBASE;
597 /* modify the lgdt arg */
598 dst32 = (u_int32_t *) (dst + ((u_int) & mp_gdtbase - boot_base));
599 *dst32 = boot_addr + ((u_int) & MP_GDT - boot_base);
601 /* modify the ljmp target for MPentry() */
602 dst32 = (u_int32_t *) (dst + ((u_int) bigJump - boot_base) + 1);
603 *dst32 = ((u_int) MPentry - KERNBASE);
605 /* modify the target for boot code segment */
606 dst16 = (u_int16_t *) (dst + ((u_int) bootCodeSeg - boot_base));
607 dst8 = (u_int8_t *) (dst16 + 1);
608 *dst16 = (u_int) boot_addr & 0xffff;
609 *dst8 = ((u_int) boot_addr >> 16) & 0xff;
611 /* modify the target for boot data segment */
612 dst16 = (u_int16_t *) (dst + ((u_int) bootDataSeg - boot_base));
613 dst8 = (u_int8_t *) (dst16 + 1);
614 *dst16 = (u_int) boot_addr & 0xffff;
615 *dst8 = ((u_int) boot_addr >> 16) & 0xff;
621 * This function starts the AP (application processor) identified
622 * by the APIC ID 'physicalCpu'. It does quite a "song and dance"
623 * to accomplish this. This is necessary because of the nuances
624 * of the different hardware we might encounter. It ain't pretty,
625 * but it seems to work.
627 * NOTE: eventually an AP gets to ap_init(), which is called just
628 * before the AP goes into the LWKT scheduler's idle loop.
631 start_ap(struct mdglobaldata *gd, u_int boot_addr, int smibest)
635 u_long icr_lo, icr_hi;
637 POSTCODE(START_AP_POST);
639 /* get the PHYSICAL APIC ID# */
640 physical_cpu = CPUID_TO_APICID(gd->mi.gd_cpuid);
642 /* calculate the vector */
643 vector = (boot_addr >> 12) & 0xff;
645 /* We don't want anything interfering */
648 /* Make sure the target cpu sees everything */
652 * Try to detect when a SMI has occurred, wait up to 200ms.
654 * If a SMI occurs during an AP reset but before we issue
655 * the STARTUP command, the AP may brick. To work around
656 * this problem we hold off doing the AP startup until
657 * after we have detected the SMI. Hopefully another SMI
658 * will not occur before we finish the AP startup.
660 * Retries don't seem to help. SMIs have a window of opportunity
661 * and if USB->legacy keyboard emulation is enabled in the BIOS
662 * the interrupt rate can be quite high.
664 * NOTE: Don't worry about the L1 cache load, it might bloat
665 * ldelta a little but ndelta will be so huge when the SMI
666 * occurs the detection logic will still work fine.
669 set_apic_timer(200000);
674 * first we do an INIT/RESET IPI this INIT IPI might be run, reseting
675 * and running the target CPU. OR this INIT IPI might be latched (P5
676 * bug), CPU waiting for STARTUP IPI. OR this INIT IPI might be
679 * see apic/apicreg.h for icr bit definitions.
681 * TIME CRITICAL CODE, DO NOT DO ANY KPRINTFS IN THE HOT PATH.
685 * Setup the address for the target AP. We can setup
686 * icr_hi once and then just trigger operations with
689 icr_hi = lapic->icr_hi & ~APIC_ID_MASK;
690 icr_hi |= (physical_cpu << 24);
691 icr_lo = lapic->icr_lo & 0xfff00000;
692 lapic->icr_hi = icr_hi;
695 * Do an INIT IPI: assert RESET
697 * Use edge triggered mode to assert INIT
699 lapic->icr_lo = icr_lo | 0x00004500;
700 while (lapic->icr_lo & APIC_DELSTAT_MASK)
704 * The spec calls for a 10ms delay but we may have to use a
705 * MUCH lower delay to avoid bricking an AP due to a fast SMI
706 * interrupt. We have other loops here too and dividing by 2
707 * doesn't seem to be enough even after subtracting 350us,
710 * Our minimum delay is 150uS, maximum is 10ms. If no SMI
711 * interrupt was detected we use the full 10ms.
715 else if (smibest < 150 * 4 + 350)
717 else if ((smibest - 350) / 4 < 10000)
718 u_sleep((smibest - 350) / 4);
723 * Do an INIT IPI: deassert RESET
725 * Use level triggered mode to deassert. It is unclear
726 * why we need to do this.
728 lapic->icr_lo = icr_lo | 0x00008500;
729 while (lapic->icr_lo & APIC_DELSTAT_MASK)
731 u_sleep(150); /* wait 150us */
734 * Next we do a STARTUP IPI: the previous INIT IPI might still be
735 * latched, (P5 bug) this 1st STARTUP would then terminate
736 * immediately, and the previously started INIT IPI would continue. OR
737 * the previous INIT IPI has already run. and this STARTUP IPI will
738 * run. OR the previous INIT IPI was ignored. and this STARTUP IPI
741 lapic->icr_lo = icr_lo | 0x00000600 | vector;
742 while (lapic->icr_lo & APIC_DELSTAT_MASK)
744 u_sleep(200); /* wait ~200uS */
747 * Finally we do a 2nd STARTUP IPI: this 2nd STARTUP IPI should run IF
748 * the previous STARTUP IPI was cancelled by a latched INIT IPI. OR
749 * this STARTUP IPI will be ignored, as only ONE STARTUP IPI is
750 * recognized after hardware RESET or INIT IPI.
752 lapic->icr_lo = icr_lo | 0x00000600 | vector;
753 while (lapic->icr_lo & APIC_DELSTAT_MASK)
756 /* Resume normal operation */
759 /* wait for it to start, see ap_init() */
760 set_apic_timer(5000000);/* == 5 seconds */
761 while (read_apic_timer()) {
762 if (CPUMASK_TESTBIT(smp_startup_mask, gd->mi.gd_cpuid))
763 return 1; /* return SUCCESS */
766 return 0; /* return FAILURE */
781 while (read_apic_timer()) {
783 for (count = 0; count < 100; ++count)
784 ntsc = rdtsc(); /* force loop to occur */
786 ndelta = ntsc - ltsc;
789 if (ndelta > ldelta * 2)
792 ldelta = ntsc - ltsc;
795 return(read_apic_timer());
799 * Synchronously flush the TLB on all other CPU's. The current cpu's
800 * TLB is not flushed. If the caller wishes to flush the current cpu's
801 * TLB the caller must call cpu_invltlb() in addition to smp_invltlb().
803 * This routine may be called concurrently from multiple cpus. When this
804 * happens, smp_invltlb() can wind up sticking around in the confirmation
805 * while() loop at the end as additional cpus are added to the global
806 * cpumask, until they are acknowledged by another IPI.
808 * NOTE: If for some reason we were unable to start all cpus we cannot
809 * safely use broadcast IPIs.
812 cpumask_t smp_smurf_mask;
813 static cpumask_t smp_invltlb_mask;
814 #define LOOPMASK (/* 32 * */ 16 * 128 * 1024 - 1)
816 cpumask_t smp_in_mask;
818 cpumask_t smp_invmask;
819 extern cpumask_t smp_idleinvl_mask;
820 extern cpumask_t smp_idleinvl_reqs;
823 * Atomically OR bits in *mask to smp_smurf_mask. Adjust *mask to remove
824 * bits that do not need to be IPId. These bits are still part of the command,
825 * but the target cpus have already been signalled and do not need to be
828 #include <sys/spinlock.h>
829 #include <sys/spinlock2.h>
833 smp_smurf_fetchset(cpumask_t *mask, int frompg)
841 while (i < CPUMASK_ELEMENTS) {
842 obits = smp_smurf_mask.ary[i];
844 nbits = obits | mask->ary[i];
845 if (atomic_cmpset_long(&smp_smurf_mask.ary[i], obits, nbits)) {
846 omask.ary[i] = obits;
850 CPUMASK_NANDMASK(*mask, omask);
854 * This is a mechanism which guarantees that cpu_invltlb() will be executed
855 * on idle cpus without having to signal or wake them up. The invltlb will be
856 * executed when they wake up, prior to any scheduling or interrupt thread.
858 * (*mask) is modified to remove the cpus we successfully negotiate this
859 * function with. This function may only be used with semi-synchronous
860 * commands (typically invltlb's or semi-synchronous invalidations which
861 * are usually associated only with kernel memory).
864 smp_smurf_idleinvlclr(cpumask_t *mask)
866 ATOMIC_CPUMASK_ORMASK(smp_idleinvl_reqs, *mask);
867 /* cpu_lfence() not needed */
868 CPUMASK_NANDMASK(*mask, smp_idleinvl_mask);
872 * Issue cpu_invltlb() across all cpus except the current cpu.
874 * This function will arrange to avoid idle cpus, but still gurantee that
875 * invltlb is run on them when they wake up prior to any scheduling or
881 struct mdglobaldata *md = mdcpu;
883 unsigned long rflags;
888 if (report_invltlb_src > 0) {
889 if (--report_invltlb_src <= 0)
893 * Disallow normal interrupts, set all active cpus except our own
894 * in the global smp_invltlb_mask.
896 ++md->mi.gd_cnt.v_smpinvltlb;
897 crit_enter_gd(&md->mi);
900 * Bits we want to set in smp_invltlb_mask. We do not want to signal
901 * our own cpu. Also try to remove bits associated with idle cpus
902 * that we can flag for auto-invltlb.
904 mask = smp_active_mask;
905 CPUMASK_NANDBIT(mask, md->mi.gd_cpuid);
906 smp_smurf_idleinvlclr(&mask);
908 rflags = read_rflags();
910 ATOMIC_CPUMASK_ORMASK(smp_invltlb_mask, mask);
913 * IPI non-idle cpus represented by mask. The omask calculation
914 * removes cpus from the mask which already have a Xinvltlb IPI
915 * pending (avoid double-queueing the IPI).
917 * We must disable real interrupts when setting the smurf flags or
918 * we might race a XINVLTLB before we manage to send the ipi's for
921 * NOTE: We are not signalling ourselves, mask already does NOT
922 * include our own cpu.
924 smp_smurf_fetchset(&mask, 0);
927 * Issue the IPI. Note that the XINVLTLB IPI runs regardless of
928 * the critical section count on the target cpus.
930 CPUMASK_ORMASK(mask, md->mi.gd_cpumask);
931 if (CPUMASK_CMPMASKEQ(smp_startup_mask, mask)) {
932 all_but_self_ipi(XINVLTLB_OFFSET);
934 CPUMASK_NANDMASK(mask, md->mi.gd_cpumask);
935 selected_apic_ipi(mask, XINVLTLB_OFFSET, APIC_DELMODE_FIXED);
939 * Wait for acknowledgement by all cpus. smp_inval_intr() will
940 * temporarily enable interrupts to avoid deadlocking the lapic,
941 * and will also handle running cpu_invltlb() and remote invlpg
942 * command son our cpu if some other cpu requests it of us.
944 * WARNING! I originally tried to implement this as a hard loop
945 * checking only smp_invltlb_mask (and issuing a local
946 * cpu_invltlb() if requested), with interrupts enabled
947 * and without calling smp_inval_intr(). This DID NOT WORK.
948 * It resulted in weird races where smurf bits would get
949 * cleared without any action being taken.
952 CPUMASK_ASSZERO(mask);
953 while (CPUMASK_CMPMASKNEQ(smp_invltlb_mask, mask)) {
957 if (++loops == 1000000) {
958 kprintf("smp_invltlb: waited too long\n");
959 mdcpu->gd_xinvaltlb = 0;
960 smp_invlpg(&smp_active_mask);
962 if (++loops == 2000000) {
963 kprintf("smp_invltlb: giving up\n");
965 CPUMASK_ASSZERO(smp_invltlb_mask);
969 write_rflags(rflags);
970 crit_exit_gd(&md->mi);
974 * Should only be called from pmap_inval.c, issues the XINVLTLB IPI which
975 * causes callbacks to be made to pmap_inval_intr() on multiple cpus, as
976 * specified by the cpumask. Used for interlocked page invalidations.
978 * NOTE: Caller has already called smp_smurf_idleinvlclr(&mask) if the
979 * command it setup was semi-synchronous-safe.
982 smp_invlpg(cpumask_t *cmdmask)
984 struct mdglobaldata *md = mdcpu;
986 unsigned long rflags;
988 if (report_invlpg_src > 0) {
989 if (--report_invlpg_src <= 0)
994 * Disallow normal interrupts, set all active cpus in the pmap,
995 * plus our own for completion processing (it might or might not
996 * be part of the set).
998 crit_enter_gd(&md->mi);
999 mask = smp_active_mask;
1000 CPUMASK_ANDMASK(mask, *cmdmask);
1001 CPUMASK_ORMASK(mask, md->mi.gd_cpumask);
1004 * Avoid double-queuing IPIs, which can deadlock us. We must disable
1005 * real interrupts when setting the smurf flags or we might race a
1006 * XINVLTLB before we manage to send the ipi's for the bits we set.
1008 * NOTE: We might be including our own cpu in the smurf mask.
1010 rflags = read_rflags();
1012 smp_smurf_fetchset(&mask, 1);
1015 * Issue the IPI. Note that the XINVLTLB IPI runs regardless of
1016 * the critical section count on the target cpus.
1018 * We do not include our own cpu when issuing the IPI.
1020 if (CPUMASK_CMPMASKEQ(smp_startup_mask, mask)) {
1021 all_but_self_ipi(XINVLTLB_OFFSET);
1023 CPUMASK_NANDMASK(mask, md->mi.gd_cpumask);
1024 selected_apic_ipi(mask, XINVLTLB_OFFSET, APIC_DELMODE_FIXED);
1028 * This will synchronously wait for our command to complete,
1029 * as well as process commands from other cpus. It also handles
1034 write_rflags(rflags);
1035 crit_exit_gd(&md->mi);
1041 globaldata_t gd = mycpu;
1044 all_but_self_ipi(XSNIFF_OFFSET);
1045 gd->gd_sample_pc = smp_sniff;
1046 gd->gd_sample_sp = &dummy;
1050 * Called from Xinvltlb assembly with interrupts hard-disabled. The
1051 * assembly doesn't check for or mess with the critical section count.
1053 * THIS CODE IS INTENDED TO EXPLICITLY IGNORE THE CRITICAL SECTION COUNT.
1054 * THAT IS, THE INTERRUPT IS INTENDED TO FUNCTION EVEN WHEN MAINLINE CODE
1055 * IS IN A CRITICAL SECTION.
1058 smp_inval_intr(void)
1060 struct mdglobaldata *md = mdcpu;
1064 * This is a real mess. I'd like to just leave interrupts disabled
1065 * but it can cause the lapic to deadlock if too many interrupts queue
1066 * to it, due to the idiotic design of the lapic. So instead we have
1067 * to enter a critical section so normal interrupts are made pending
1068 * and track whether this one was reentered.
1070 if (md->gd_xinvaltlb) { /* reentrant on cpu */
1071 md->gd_xinvaltlb = 2;
1074 md->gd_xinvaltlb = 1;
1077 * Check only those cpus with active Xinvl* commands pending.
1079 * We are going to enable interrupts so make sure we are in a
1080 * critical section. This is necessary to avoid deadlocking
1081 * the lapic and to ensure that we execute our commands prior to
1082 * any nominal interrupt or preemption.
1084 cpumask = smp_invmask;
1085 crit_enter_gd(&md->mi);
1089 ATOMIC_CPUMASK_ORBIT(smp_in_mask, md->mi.gd_cpuid);
1091 ATOMIC_CPUMASK_NANDBIT(smp_smurf_mask, md->mi.gd_cpuid);
1094 * Specific page request(s), and we can't return until all bits
1099 * We can only add bits to the cpumask to test during the
1100 * loop because the smp_invmask bit is cleared once the
1101 * originator completes the command (the targets may still
1102 * be cycling their own completions in this loop, afterwords).
1104 * lfence required prior to all tests as this Xinvltlb
1105 * interrupt could race the originator (already be in progress
1106 * wnen the originator decides to issue, due to an issue by
1110 CPUMASK_ORMASK(cpumask, smp_invmask);
1111 if (CPUMASK_TESTBIT(smp_invltlb_mask, md->mi.gd_cpuid)) {
1112 ATOMIC_CPUMASK_NANDBIT(smp_invltlb_mask,
1117 cpumask = smp_active_mask; /* XXX */
1118 if (pmap_inval_intr(&cpumask) == 0) {
1120 * Clear our smurf mask to allow new IPIs, but deal
1121 * with potential races.
1125 ATOMIC_CPUMASK_NANDBIT(smp_smurf_mask,
1128 if (pmap_inval_intr(&cpumask) == 0)
1132 * Still looping (race), re-set the smurf bit. If
1133 * another race occurred and set it before we could,
1134 * stop here to avoid deadlocking on the hardware
1135 * IPI (another IPI will occur).
1137 smp_smurf_fetchset(&md->mi.gd_cpumask XXX
1138 if (CPUMASK_TESTBIT(omask, md->mi.gd_cpuid)) {
1145 * Test if someone sent us another invalidation IPI, break
1146 * out so we can take it to avoid deadlocking the lapic
1147 * interrupt queue (? stupid intel, amd).
1149 if (md->gd_xinvaltlb == 2)
1152 if (CPUMASK_TESTBIT(smp_smurf_mask, md->mi.gd_cpuid))
1158 * Full invalidation request
1160 if (CPUMASK_TESTBIT(smp_invltlb_mask, md->mi.gd_cpuid)) {
1161 ATOMIC_CPUMASK_NANDBIT(smp_invltlb_mask,
1167 ATOMIC_CPUMASK_NANDBIT(smp_in_mask, md->mi.gd_cpuid);
1170 * Check to see if another Xinvltlb interrupt occurred and loop up
1174 if (md->gd_xinvaltlb == 2) {
1175 md->gd_xinvaltlb = 1;
1178 md->gd_xinvaltlb = 0;
1181 * We will return via doreti, do not try to stack pending ints
1183 crit_exit_noyield(md->mi.gd_curthread);
1187 cpu_wbinvd_on_all_cpus_callback(void *arg)
1193 * When called the executing CPU will send an IPI to all other CPUs
1194 * requesting that they halt execution.
1196 * Usually (but not necessarily) called with 'other_cpus' as its arg.
1198 * - Signals all CPUs in map to stop.
1199 * - Waits for each to stop.
1206 * XXX FIXME: this is not MP-safe, needs a lock to prevent multiple CPUs
1207 * from executing at same time.
1210 stop_cpus(cpumask_t map)
1214 CPUMASK_ANDMASK(map, smp_active_mask);
1216 /* send the Xcpustop IPI to all CPUs in map */
1217 selected_apic_ipi(map, XCPUSTOP_OFFSET, APIC_DELMODE_FIXED);
1220 mask = stopped_cpus;
1221 CPUMASK_ANDMASK(mask, map);
1223 } while (CPUMASK_CMPMASKNEQ(mask, map));
1230 * Called by a CPU to restart stopped CPUs.
1232 * Usually (but not necessarily) called with 'stopped_cpus' as its arg.
1234 * - Signals all CPUs in map to restart.
1235 * - Waits for each to restart.
1243 restart_cpus(cpumask_t map)
1247 /* signal other cpus to restart */
1249 CPUMASK_ANDMASK(mask, smp_active_mask);
1251 started_cpus = mask;
1254 /* wait for each to clear its bit */
1255 while (CPUMASK_CMPMASKNEQ(stopped_cpus, map))
1262 * This is called once the mpboot code has gotten us properly relocated
1263 * and the MMU turned on, etc. ap_init() is actually the idle thread,
1264 * and when it returns the scheduler will call the real cpu_idle() main
1265 * loop for the idlethread. Interrupts are disabled on entry and should
1266 * remain disabled at return.
1274 * Adjust smp_startup_mask to signal the BSP that we have started
1275 * up successfully. Note that we do not yet hold the BGL. The BSP
1276 * is waiting for our signal.
1278 * We can't set our bit in smp_active_mask yet because we are holding
1279 * interrupts physically disabled and remote cpus could deadlock
1280 * trying to send us an IPI.
1282 ATOMIC_CPUMASK_ORBIT(smp_startup_mask, mycpu->gd_cpuid);
1286 * Interlock for LAPIC initialization. Wait until mp_finish_lapic is
1287 * non-zero, then get the MP lock.
1289 * Note: We are in a critical section.
1291 * Note: we are the idle thread, we can only spin.
1293 * Note: The load fence is memory volatile and prevents the compiler
1294 * from improperly caching mp_finish_lapic, and the cpu from improperly
1297 while (mp_finish_lapic == 0) {
1302 while (try_mplock() == 0) {
1308 if (cpu_feature & CPUID_TSC) {
1310 * The BSP is constantly updating tsc0_offset, figure out
1311 * the relative difference to synchronize ktrdump.
1313 tsc_offsets[mycpu->gd_cpuid] = rdtsc() - tsc0_offset;
1316 /* BSP may have changed PTD while we're waiting for the lock */
1319 /* Build our map of 'other' CPUs. */
1320 mycpu->gd_other_cpus = smp_startup_mask;
1321 ATOMIC_CPUMASK_NANDBIT(mycpu->gd_other_cpus, mycpu->gd_cpuid);
1323 /* A quick check from sanity claus */
1324 cpu_id = APICID_TO_CPUID((lapic->id & 0xff000000) >> 24);
1325 if (mycpu->gd_cpuid != cpu_id) {
1326 kprintf("SMP: assigned cpuid = %d\n", mycpu->gd_cpuid);
1327 kprintf("SMP: actual cpuid = %d lapicid %d\n",
1328 cpu_id, (lapic->id & 0xff000000) >> 24);
1330 kprintf("PTD[MPPTDI] = %p\n", (void *)PTD[MPPTDI]);
1332 panic("cpuid mismatch! boom!!");
1335 /* Initialize AP's local APIC for irq's */
1338 /* LAPIC initialization is done */
1339 ATOMIC_CPUMASK_ORBIT(smp_lapic_mask, mycpu->gd_cpuid);
1343 /* Let BSP move onto the next initialization stage */
1348 * Interlock for finalization. Wait until mp_finish is non-zero,
1349 * then get the MP lock.
1351 * Note: We are in a critical section.
1353 * Note: we are the idle thread, we can only spin.
1355 * Note: The load fence is memory volatile and prevents the compiler
1356 * from improperly caching mp_finish, and the cpu from improperly
1359 while (mp_finish == 0) {
1364 /* BSP may have changed PTD while we're waiting for the lock */
1367 /* Set memory range attributes for this CPU to match the BSP */
1368 mem_range_AP_init();
1371 * Once we go active we must process any IPIQ messages that may
1372 * have been queued, because no actual IPI will occur until we
1373 * set our bit in the smp_active_mask. If we don't the IPI
1374 * message interlock could be left set which would also prevent
1377 * The idle loop doesn't expect the BGL to be held and while
1378 * lwkt_switch() normally cleans things up this is a special case
1379 * because we returning almost directly into the idle loop.
1381 * The idle thread is never placed on the runq, make sure
1382 * nothing we've done put it there.
1386 * Hold a critical section and allow real interrupts to occur. Zero
1387 * any spurious interrupts which have accumulated, then set our
1388 * smp_active_mask indicating that we are fully operational.
1391 __asm __volatile("sti; pause; pause"::);
1392 bzero(mdcpu->gd_ipending, sizeof(mdcpu->gd_ipending));
1393 ATOMIC_CPUMASK_ORBIT(smp_active_mask, mycpu->gd_cpuid);
1396 * Wait until all cpus have set their smp_active_mask and have fully
1397 * operational interrupts before proceeding.
1399 * We need a final cpu_invltlb() because we would not have received
1400 * any until we set our bit in smp_active_mask.
1402 while (mp_finish == 1) {
1409 * Initialize per-cpu clocks and do other per-cpu initialization.
1410 * At this point code is expected to be able to use the full kernel
1413 initclocks_pcpu(); /* clock interrupts (via IPIs) */
1416 * Since we may have cleaned up the interrupt triggers, manually
1417 * process any pending IPIs before exiting our critical section.
1418 * Once the critical section has exited, normal interrupt processing
1421 lwkt_process_ipiq();
1422 crit_exit_noyield(mycpu->gd_curthread);
1425 * Final final, allow the waiting BSP to resume the boot process,
1426 * return 'into' the idle thread bootstrap.
1428 ATOMIC_CPUMASK_ORBIT(smp_finalize_mask, mycpu->gd_cpuid);
1429 KKASSERT((curthread->td_flags & TDF_RUNQ) == 0);
1433 * Get SMP fully working before we start initializing devices.
1440 kprintf("Finish MP startup\n");
1444 * Wait for the active mask to complete, after which all cpus will
1445 * be accepting interrupts.
1448 while (CPUMASK_CMPMASKNEQ(smp_active_mask, smp_startup_mask)) {
1454 * Wait for the finalization mask to complete, after which all cpus
1455 * have completely finished initializing and are entering or are in
1456 * their idle thread.
1458 * BSP should have received all required invltlbs but do another
1463 while (CPUMASK_CMPMASKNEQ(smp_finalize_mask, smp_startup_mask)) {
1468 while (try_mplock() == 0) {
1474 kprintf("Active CPU Mask: %016jx\n",
1475 (uintmax_t)CPUMASK_LOWMASK(smp_active_mask));
1479 SYSINIT(finishsmp, SI_BOOT2_FINISH_SMP, SI_ORDER_FIRST, ap_finish, NULL);
1482 cpu_send_ipiq(int dcpu)
1484 if (CPUMASK_TESTBIT(smp_active_mask, dcpu))
1485 single_apic_ipi(dcpu, XIPIQ_OFFSET, APIC_DELMODE_FIXED);
1488 #if 0 /* single_apic_ipi_passive() not working yet */
1490 * Returns 0 on failure, 1 on success
1493 cpu_send_ipiq_passive(int dcpu)
1496 if (CPUMASK_TESTBIT(smp_active_mask, dcpu)) {
1497 r = single_apic_ipi_passive(dcpu, XIPIQ_OFFSET,
1498 APIC_DELMODE_FIXED);
1505 mp_bsp_simple_setup(void)
1507 struct mdglobaldata *gd;
1510 /* build our map of 'other' CPUs */
1511 mycpu->gd_other_cpus = smp_startup_mask;
1512 CPUMASK_NANDBIT(mycpu->gd_other_cpus, mycpu->gd_cpuid);
1514 gd = (struct mdglobaldata *)mycpu;
1515 gd->gd_acpi_id = CPUID_TO_ACPIID(mycpu->gd_cpuid);
1517 ipiq_size = sizeof(struct lwkt_ipiq) * ncpus;
1518 mycpu->gd_ipiq = (void *)kmem_alloc(&kernel_map, ipiq_size);
1519 bzero(mycpu->gd_ipiq, ipiq_size);
1523 if (cpu_feature & CPUID_TSC)
1524 tsc0_offset = rdtsc();
1529 * CPU TOPOLOGY DETECTION FUNCTIONS
1532 /* Detect intel topology using CPUID
1533 * Ref: http://www.intel.com/Assets/PDF/appnote/241618.pdf, pg 41
1536 detect_intel_topology(int count_htt_cores)
1540 int core_plus_logical_bits = 0;
1541 int cores_per_package;
1542 int logical_per_package;
1543 int logical_per_core;
1546 if (cpu_high >= 0xb) {
1549 } else if (cpu_high >= 0x4) {
1554 for (shift = 0; (1 << shift) < count_htt_cores; ++shift)
1556 logical_CPU_bits = 1 << shift;
1561 cpuid_count(0xb, FUNC_B_THREAD_LEVEL, p);
1563 /* if 0xb not supported - fallback to 0x4 */
1564 if (p[1] == 0 || (FUNC_B_TYPE(p[2]) != FUNC_B_THREAD_TYPE)) {
1568 logical_CPU_bits = FUNC_B_BITS_SHIFT_NEXT_LEVEL(p[0]);
1570 ecx_index = FUNC_B_THREAD_LEVEL + 1;
1572 cpuid_count(0xb, ecx_index, p);
1574 /* Check for the Core type in the implemented sub leaves. */
1575 if (FUNC_B_TYPE(p[2]) == FUNC_B_CORE_TYPE) {
1576 core_plus_logical_bits = FUNC_B_BITS_SHIFT_NEXT_LEVEL(p[0]);
1582 } while (FUNC_B_TYPE(p[2]) != FUNC_B_INVALID_TYPE);
1584 core_bits = core_plus_logical_bits - logical_CPU_bits;
1589 cpuid_count(0x4, 0, p);
1590 cores_per_package = FUNC_4_MAX_CORE_NO(p[0]) + 1;
1592 logical_per_package = count_htt_cores;
1593 logical_per_core = logical_per_package / cores_per_package;
1595 for (shift = 0; (1 << shift) < logical_per_core; ++shift)
1597 logical_CPU_bits = shift;
1599 for (shift = 0; (1 << shift) < cores_per_package; ++shift)
1606 /* Detect AMD topology using CPUID
1607 * Ref: http://support.amd.com/us/Embedded_TechDocs/25481.pdf, last page
1610 detect_amd_topology(int count_htt_cores)
1613 if ((cpu_feature & CPUID_HTT)
1614 && (amd_feature2 & AMDID2_CMP)) {
1616 if (cpu_procinfo2 & AMDID_COREID_SIZE) {
1617 core_bits = (cpu_procinfo2 & AMDID_COREID_SIZE)
1618 >> AMDID_COREID_SIZE_SHIFT;
1620 core_bits = (cpu_procinfo2 & AMDID_CMP_CORES) + 1;
1621 for (shift = 0; (1 << shift) < core_bits; ++shift)
1626 logical_CPU_bits = count_htt_cores >> core_bits;
1627 for (shift = 0; (1 << shift) < logical_CPU_bits; ++shift)
1629 logical_CPU_bits = shift;
1631 for (shift = 0; (1 << shift) < count_htt_cores; ++shift)
1634 logical_CPU_bits = 0;
1639 amd_get_compute_unit_id(void *arg)
1643 do_cpuid(0x8000001e, regs);
1644 cpu_node_t * mynode = get_cpu_node_by_cpuid(mycpuid);
1646 * AMD - CPUID Specification September 2010
1647 * page 34 - //ComputeUnitID = ebx[0:7]//
1649 mynode->compute_unit_id = regs[1] & 0xff;
1653 fix_amd_topology(void)
1657 if (cpu_vendor_id != CPU_VENDOR_AMD)
1659 if ((amd_feature2 & AMDID2_TOPOEXT) == 0)
1662 CPUMASK_ASSALLONES(mask);
1663 lwkt_cpusync_simple(mask, amd_get_compute_unit_id, NULL);
1665 kprintf("Compute unit iDS:\n");
1667 for (i = 0; i < ncpus; i++) {
1668 kprintf("%d-%d; \n",
1669 i, get_cpu_node_by_cpuid(i)->compute_unit_id);
1676 * - logical_CPU_bits
1678 * With the values above (for AMD or INTEL) we are able to generally
1679 * detect the CPU topology (number of cores for each level):
1680 * Ref: http://wiki.osdev.org/Detecting_CPU_Topology_(80x86)
1681 * Ref: http://www.multicoreinfo.com/research/papers/whitepapers/Intel-detect-topology.pdf
1684 detect_cpu_topology(void)
1686 static int topology_detected = 0;
1689 if (topology_detected)
1691 if ((cpu_feature & CPUID_HTT) == 0) {
1693 logical_CPU_bits = 0;
1696 count = (cpu_procinfo & CPUID_HTT_CORES) >> CPUID_HTT_CORE_SHIFT;
1698 if (cpu_vendor_id == CPU_VENDOR_INTEL)
1699 detect_intel_topology(count);
1700 else if (cpu_vendor_id == CPU_VENDOR_AMD)
1701 detect_amd_topology(count);
1702 topology_detected = 1;
1706 kprintf("Bits within APICID: logical_CPU_bits: %d; core_bits: %d\n",
1707 logical_CPU_bits, core_bits);
1710 /* Interface functions to calculate chip_ID,
1711 * core_number and logical_number
1712 * Ref: http://wiki.osdev.org/Detecting_CPU_Topology_(80x86)
1715 get_chip_ID(int cpuid)
1717 return get_apicid_from_cpuid(cpuid) >>
1718 (logical_CPU_bits + core_bits);
1722 get_core_number_within_chip(int cpuid)
1724 return (get_apicid_from_cpuid(cpuid) >> logical_CPU_bits) &
1725 ( (1 << core_bits) -1);
1729 get_logical_CPU_number_within_core(int cpuid)
1731 return get_apicid_from_cpuid(cpuid) &
1732 ( (1 << logical_CPU_bits) -1);