sys/dev/drm/i915/i915_debug.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *    Keith Packard <keithp@keithp.com>
  26  *
  27  * $FreeBSD: src/sys/dev/drm2/i915/i915_debug.c,v 1.1 2012/05/22 11:07:44 kib Exp $
  28  */
  29
  30 #include <dev/drm/drmP.h>
  31 #include <dev/drm/drm.h>
  32 #include "i915_drm.h"
  33 #include "i915_drv.h"
  34 #include "intel_drv.h"
  35 #include "intel_ringbuffer.h"
  36
  37 #include <sys/sysctl.h>
  38
  39 enum {
  40         ACTIVE_LIST,
  41         FLUSHING_LIST,
  42         INACTIVE_LIST,
  43         PINNED_LIST,
  44         DEFERRED_FREE_LIST,
  45 };
  46
  47 static const char *
  48 yesno(int v)
  49 {
  50         return (v ? "yes" : "no");
  51 }
  52
  53 static int
  54 i915_capabilities(struct drm_device *dev, struct sbuf *m, void *data)
  55 {
  56         const struct intel_device_info *info = INTEL_INFO(dev);
  57
  58         sbuf_printf(m, "gen: %d\n", info->gen);
  59         if (HAS_PCH_SPLIT(dev))
  60                 sbuf_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev));
  61 #define B(x) sbuf_printf(m, #x ": %s\n", yesno(info->x))
  62         B(is_mobile);
  63         B(is_i85x);
  64         B(is_i915g);
  65         B(is_i945gm);
  66         B(is_g33);
  67         B(need_gfx_hws);
  68         B(is_g4x);
  69         B(is_pineview);
  70         B(has_fbc);
  71         B(has_pipe_cxsr);
  72         B(has_hotplug);
  73         B(cursor_needs_physical);
  74         B(has_overlay);
  75         B(overlay_needs_physical);
  76         B(supports_tv);
  77         B(has_bsd_ring);
  78         B(has_blt_ring);
  79         B(has_llc);
  80 #undef B
  81
  82         return (0);
  83 }
  84
  85 static const char *
  86 get_pin_flag(struct drm_i915_gem_object *obj)
  87 {
  88         if (obj->user_pin_count > 0)
  89                 return "P";
  90         else if (obj->pin_count > 0)
  91                 return "p";
  92         else
  93                 return " ";
  94 }
  95
  96 static const char *
  97 get_tiling_flag(struct drm_i915_gem_object *obj)
  98 {
  99         switch (obj->tiling_mode) {
 100         default:
 101         case I915_TILING_NONE: return (" ");
 102         case I915_TILING_X: return ("X");
 103         case I915_TILING_Y: return ("Y");
 104         }
 105 }
 106
 107 static const char *
 108 cache_level_str(int type)
 109 {
 110         switch (type) {
 111         case I915_CACHE_NONE: return " uncached";
 112         case I915_CACHE_LLC: return " snooped (LLC)";
 113         case I915_CACHE_LLC_MLC: return " snooped (LLC+MLC)";
 114         default: return ("");
 115         }
 116 }
 117
 118 static void
 119 describe_obj(struct sbuf *m, struct drm_i915_gem_object *obj)
 120 {
 121
 122         sbuf_printf(m, "%p: %s%s %8zdKiB %04x %04x %d %d%s%s%s",
 123                    &obj->base,
 124                    get_pin_flag(obj),
 125                    get_tiling_flag(obj),
 126                    obj->base.size / 1024,
 127                    obj->base.read_domains,
 128                    obj->base.write_domain,
 129                    obj->last_rendering_seqno,
 130                    obj->last_fenced_seqno,
 131                    cache_level_str(obj->cache_level),
 132                    obj->dirty ? " dirty" : "",
 133                    obj->madv == I915_MADV_DONTNEED ? " purgeable" : "");
 134         if (obj->base.name)
 135                 sbuf_printf(m, " (name: %d)", obj->base.name);
 136         if (obj->fence_reg != I915_FENCE_REG_NONE)
 137                 sbuf_printf(m, " (fence: %d)", obj->fence_reg);
 138         if (obj->gtt_space != NULL)
 139                 sbuf_printf(m, " (gtt offset: %08x, size: %08x)",
 140                            obj->gtt_offset, (unsigned int)obj->gtt_space->size);
 141         if (obj->pin_mappable || obj->fault_mappable) {
 142                 char s[3], *t = s;
 143                 if (obj->pin_mappable)
 144                         *t++ = 'p';
 145                 if (obj->fault_mappable)
 146                         *t++ = 'f';
 147                 *t = '\0';
 148                 sbuf_printf(m, " (%s mappable)", s);
 149         }
 150         if (obj->ring != NULL)
 151                 sbuf_printf(m, " (%s)", obj->ring->name);
 152 }
 153
 154 static int
 155 i915_gem_object_list_info(struct drm_device *dev, struct sbuf *m, void *data)
 156 {
 157         uintptr_t list = (uintptr_t)data;
 158         struct list_head *head;
 159         drm_i915_private_t *dev_priv = dev->dev_private;
 160         struct drm_i915_gem_object *obj;
 161         size_t total_obj_size, total_gtt_size;
 162         int count;
 163
 164         if (lockmgr(&dev->dev_struct_lock, LK_EXCLUSIVE|LK_SLEEPFAIL))
 165                 return (EINTR);
 166
 167         switch (list) {
 168         case ACTIVE_LIST:
 169                 sbuf_printf(m, "Active:\n");
 170                 head = &dev_priv->mm.active_list;
 171                 break;
 172         case INACTIVE_LIST:
 173                 sbuf_printf(m, "Inactive:\n");
 174                 head = &dev_priv->mm.inactive_list;
 175                 break;
 176         case PINNED_LIST:
 177                 sbuf_printf(m, "Pinned:\n");
 178                 head = &dev_priv->mm.pinned_list;
 179                 break;
 180         case FLUSHING_LIST:
 181                 sbuf_printf(m, "Flushing:\n");
 182                 head = &dev_priv->mm.flushing_list;
 183                 break;
 184         case DEFERRED_FREE_LIST:
 185                 sbuf_printf(m, "Deferred free:\n");
 186                 head = &dev_priv->mm.deferred_free_list;
 187                 break;
 188         default:
 189                 DRM_UNLOCK(dev);
 190                 return (EINVAL);
 191         }
 192
 193         total_obj_size = total_gtt_size = count = 0;
 194         list_for_each_entry(obj, head, mm_list) {
 195                 sbuf_printf(m, "   ");
 196                 describe_obj(m, obj);
 197                 sbuf_printf(m, "\n");
 198                 total_obj_size += obj->base.size;
 199                 total_gtt_size += obj->gtt_space->size;
 200                 count++;
 201         }
 202         DRM_UNLOCK(dev);
 203
 204         sbuf_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
 205                    count, total_obj_size, total_gtt_size);
 206         return (0);
 207 }
 208
 209 #define count_objects(list, member) do { \
 210         list_for_each_entry(obj, list, member) { \
 211                 size += obj->gtt_space->size; \
 212                 ++count; \
 213                 if (obj->map_and_fenceable) { \
 214                         mappable_size += obj->gtt_space->size; \
 215                         ++mappable_count; \
 216                 } \
 217         } \
 218 } while (0)
 219
 220 static int
 221 i915_gem_object_info(struct drm_device *dev, struct sbuf *m, void *data)
 222 {
 223         struct drm_i915_private *dev_priv = dev->dev_private;
 224         u32 count, mappable_count;
 225         size_t size, mappable_size;
 226         struct drm_i915_gem_object *obj;
 227
 228         if (lockmgr(&dev->dev_struct_lock, LK_EXCLUSIVE|LK_SLEEPFAIL))
 229                 return (EINTR);
 230         sbuf_printf(m, "%u objects, %zu bytes\n",
 231                    dev_priv->mm.object_count,
 232                    dev_priv->mm.object_memory);
 233
 234         size = count = mappable_size = mappable_count = 0;
 235         count_objects(&dev_priv->mm.gtt_list, gtt_list);
 236         sbuf_printf(m, "%u [%u] objects, %zu [%zu] bytes in gtt\n",
 237                    count, mappable_count, size, mappable_size);
 238
 239         size = count = mappable_size = mappable_count = 0;
 240         count_objects(&dev_priv->mm.active_list, mm_list);
 241         count_objects(&dev_priv->mm.flushing_list, mm_list);
 242         sbuf_printf(m, "  %u [%u] active objects, %zu [%zu] bytes\n",
 243                    count, mappable_count, size, mappable_size);
 244
 245         size = count = mappable_size = mappable_count = 0;
 246         count_objects(&dev_priv->mm.pinned_list, mm_list);
 247         sbuf_printf(m, "  %u [%u] pinned objects, %zu [%zu] bytes\n",
 248                    count, mappable_count, size, mappable_size);
 249
 250         size = count = mappable_size = mappable_count = 0;
 251         count_objects(&dev_priv->mm.inactive_list, mm_list);
 252         sbuf_printf(m, "  %u [%u] inactive objects, %zu [%zu] bytes\n",
 253                    count, mappable_count, size, mappable_size);
 254
 255         size = count = mappable_size = mappable_count = 0;
 256         count_objects(&dev_priv->mm.deferred_free_list, mm_list);
 257         sbuf_printf(m, "  %u [%u] freed objects, %zu [%zu] bytes\n",
 258                    count, mappable_count, size, mappable_size);
 259
 260         size = count = mappable_size = mappable_count = 0;
 261         list_for_each_entry(obj, &dev_priv->mm.gtt_list, gtt_list) {
 262                 if (obj->fault_mappable) {
 263                         size += obj->gtt_space->size;
 264                         ++count;
 265                 }
 266                 if (obj->pin_mappable) {
 267                         mappable_size += obj->gtt_space->size;
 268                         ++mappable_count;
 269                 }
 270         }
 271         sbuf_printf(m, "%u pinned mappable objects, %zu bytes\n",
 272                    mappable_count, mappable_size);
 273         sbuf_printf(m, "%u fault mappable objects, %zu bytes\n",
 274                    count, size);
 275
 276         sbuf_printf(m, "%zu [%zu] gtt total\n",
 277                    dev_priv->mm.gtt_total, dev_priv->mm.mappable_gtt_total);
 278         DRM_UNLOCK(dev);
 279
 280         return (0);
 281 }
 282
 283 static int
 284 i915_gem_gtt_info(struct drm_device *dev, struct sbuf *m, void* data)
 285 {
 286         struct drm_i915_private *dev_priv = dev->dev_private;
 287         struct drm_i915_gem_object *obj;
 288         size_t total_obj_size, total_gtt_size;
 289         int count;
 290
 291         if (lockmgr(&dev->dev_struct_lock, LK_EXCLUSIVE|LK_SLEEPFAIL))
 292                 return (EINTR);
 293
 294         total_obj_size = total_gtt_size = count = 0;
 295         list_for_each_entry(obj, &dev_priv->mm.gtt_list, gtt_list) {
 296                 sbuf_printf(m, "   ");
 297                 describe_obj(m, obj);
 298                 sbuf_printf(m, "\n");
 299                 total_obj_size += obj->base.size;
 300                 total_gtt_size += obj->gtt_space->size;
 301                 count++;
 302         }
 303
 304         DRM_UNLOCK(dev);
 305
 306         sbuf_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
 307                    count, total_obj_size, total_gtt_size);
 308
 309         return (0);
 310 }
 311
 312 static int
 313 i915_gem_pageflip_info(struct drm_device *dev, struct sbuf *m, void *data)
 314 {
 315         struct intel_crtc *crtc;
 316         struct drm_i915_gem_object *obj;
 317         struct intel_unpin_work *work;
 318         char pipe;
 319         char plane;
 320
 321         if ((dev->driver->driver_features & DRIVER_MODESET) == 0)
 322                 return (0);
 323         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
 324                 pipe = pipe_name(crtc->pipe);
 325                 plane = plane_name(crtc->plane);
 326
 327                 lockmgr(&dev->event_lock, LK_EXCLUSIVE);
 328                 work = crtc->unpin_work;
 329                 if (work == NULL) {
 330                         sbuf_printf(m, "No flip due on pipe %c (plane %c)\n",
 331                                    pipe, plane);
 332                 } else {
 333                         if (!work->pending) {
 334                                 sbuf_printf(m, "Flip queued on pipe %c (plane %c)\n",
 335                                            pipe, plane);
 336                         } else {
 337                                 sbuf_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n",
 338                                            pipe, plane);
 339                         }
 340                         if (work->enable_stall_check)
 341                                 sbuf_printf(m, "Stall check enabled, ");
 342                         else
 343                                 sbuf_printf(m, "Stall check waiting for page flip ioctl, ");
 344                         sbuf_printf(m, "%d prepares\n", work->pending);
 345
 346                         if (work->old_fb_obj) {
 347                                 obj = work->old_fb_obj;
 348                                 if (obj)
 349                                         sbuf_printf(m, "Old framebuffer gtt_offset 0x%08x\n", obj->gtt_offset);
 350                         }
 351                         if (work->pending_flip_obj) {
 352                                 obj = work->pending_flip_obj;
 353                                 if (obj)
 354                                         sbuf_printf(m, "New framebuffer gtt_offset 0x%08x\n", obj->gtt_offset);
 355                         }
 356                 }
 357                 lockmgr(&dev->event_lock, LK_RELEASE);
 358         }
 359
 360         return (0);
 361 }
 362
 363 static int
 364 i915_gem_request_info(struct drm_device *dev, struct sbuf *m, void *data)
 365 {
 366         drm_i915_private_t *dev_priv = dev->dev_private;
 367         struct drm_i915_gem_request *gem_request;
 368         int count;
 369
 370         if (lockmgr(&dev->dev_struct_lock, LK_EXCLUSIVE|LK_SLEEPFAIL))
 371                 return (EINTR);
 372
 373         count = 0;
 374         if (!list_empty(&dev_priv->rings[RCS].request_list)) {
 375                 sbuf_printf(m, "Render requests:\n");
 376                 list_for_each_entry(gem_request,
 377                                     &dev_priv->rings[RCS].request_list,
 378                                     list) {
 379                         sbuf_printf(m, "    %d @ %d\n",
 380                                    gem_request->seqno,
 381                                    (int) (jiffies - gem_request->emitted_jiffies));
 382                 }
 383                 count++;
 384         }
 385         if (!list_empty(&dev_priv->rings[VCS].request_list)) {
 386                 sbuf_printf(m, "BSD requests:\n");
 387                 list_for_each_entry(gem_request,
 388                                     &dev_priv->rings[VCS].request_list,
 389                                     list) {
 390                         sbuf_printf(m, "    %d @ %d\n",
 391                                    gem_request->seqno,
 392                                    (int) (jiffies - gem_request->emitted_jiffies));
 393                 }
 394                 count++;
 395         }
 396         if (!list_empty(&dev_priv->rings[BCS].request_list)) {
 397                 sbuf_printf(m, "BLT requests:\n");
 398                 list_for_each_entry(gem_request,
 399                                     &dev_priv->rings[BCS].request_list,
 400                                     list) {
 401                         sbuf_printf(m, "    %d @ %d\n",
 402                                    gem_request->seqno,
 403                                    (int) (jiffies - gem_request->emitted_jiffies));
 404                 }
 405                 count++;
 406         }
 407         DRM_UNLOCK(dev);
 408
 409         if (count == 0)
 410                 sbuf_printf(m, "No requests\n");
 411
 412         return 0;
 413 }
 414
 415 static void
 416 i915_ring_seqno_info(struct sbuf *m, struct intel_ring_buffer *ring)
 417 {
 418         if (ring->get_seqno) {
 419                 sbuf_printf(m, "Current sequence (%s): %d\n",
 420                            ring->name, ring->get_seqno(ring));
 421                 sbuf_printf(m, "Waiter sequence (%s):  %d\n",
 422                            ring->name, ring->waiting_seqno);
 423                 sbuf_printf(m, "IRQ sequence (%s):     %d\n",
 424                            ring->name, ring->irq_seqno);
 425         }
 426 }
 427
 428 static int
 429 i915_gem_seqno_info(struct drm_device *dev, struct sbuf *m, void *data)
 430 {
 431         drm_i915_private_t *dev_priv = dev->dev_private;
 432         int i;
 433
 434         if (lockmgr(&dev->dev_struct_lock, LK_EXCLUSIVE|LK_SLEEPFAIL))
 435                 return (EINTR);
 436         for (i = 0; i < I915_NUM_RINGS; i++)
 437                 i915_ring_seqno_info(m, &dev_priv->rings[i]);
 438         DRM_UNLOCK(dev);
 439         return (0);
 440 }
 441
 442
 443 static int
 444 i915_interrupt_info(struct drm_device *dev, struct sbuf *m, void *data)
 445 {
 446         drm_i915_private_t *dev_priv = dev->dev_private;
 447         int i, pipe;
 448
 449         if (lockmgr(&dev->dev_struct_lock, LK_EXCLUSIVE|LK_SLEEPFAIL))
 450                 return (EINTR);
 451
 452         if (!HAS_PCH_SPLIT(dev)) {
 453                 sbuf_printf(m, "Interrupt enable:    %08x\n",
 454                            I915_READ(IER));
 455                 sbuf_printf(m, "Interrupt identity:  %08x\n",
 456                            I915_READ(IIR));
 457                 sbuf_printf(m, "Interrupt mask:      %08x\n",
 458                            I915_READ(IMR));
 459                 for_each_pipe(pipe)
 460                         sbuf_printf(m, "Pipe %c stat:         %08x\n",
 461                                    pipe_name(pipe),
 462                                    I915_READ(PIPESTAT(pipe)));
 463         } else {
 464                 sbuf_printf(m, "North Display Interrupt enable:         %08x\n",
 465                            I915_READ(DEIER));
 466                 sbuf_printf(m, "North Display Interrupt identity:       %08x\n",
 467                            I915_READ(DEIIR));
 468                 sbuf_printf(m, "North Display Interrupt mask:           %08x\n",
 469                            I915_READ(DEIMR));
 470                 sbuf_printf(m, "South Display Interrupt enable:         %08x\n",
 471                            I915_READ(SDEIER));
 472                 sbuf_printf(m, "South Display Interrupt identity:       %08x\n",
 473                            I915_READ(SDEIIR));
 474                 sbuf_printf(m, "South Display Interrupt mask:           %08x\n",
 475                            I915_READ(SDEIMR));
 476                 sbuf_printf(m, "Graphics Interrupt enable:              %08x\n",
 477                            I915_READ(GTIER));
 478                 sbuf_printf(m, "Graphics Interrupt identity:            %08x\n",
 479                            I915_READ(GTIIR));
 480                 sbuf_printf(m, "Graphics Interrupt mask:                %08x\n",
 481                            I915_READ(GTIMR));
 482         }
 483         sbuf_printf(m, "Interrupts received: %d\n",
 484                    atomic_read(&dev_priv->irq_received));
 485         for (i = 0; i < I915_NUM_RINGS; i++) {
 486                 if (IS_GEN6(dev) || IS_GEN7(dev)) {
 487                         sbuf_printf(m, "Graphics Interrupt mask (%s):   %08x\n",
 488                                    dev_priv->rings[i].name,
 489                                    I915_READ_IMR(&dev_priv->rings[i]));
 490                 }
 491                 i915_ring_seqno_info(m, &dev_priv->rings[i]);
 492         }
 493         DRM_UNLOCK(dev);
 494
 495         return (0);
 496 }
 497
 498 static int
 499 i915_gem_fence_regs_info(struct drm_device *dev, struct sbuf *m, void *data)
 500 {
 501         drm_i915_private_t *dev_priv = dev->dev_private;
 502         int i;
 503
 504         if (lockmgr(&dev->dev_struct_lock, LK_EXCLUSIVE|LK_SLEEPFAIL))
 505                 return (EINTR);
 506
 507         sbuf_printf(m, "Reserved fences = %d\n", dev_priv->fence_reg_start);
 508         sbuf_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs);
 509         for (i = 0; i < dev_priv->num_fence_regs; i++) {
 510                 struct drm_i915_gem_object *obj = dev_priv->fence_regs[i].obj;
 511
 512                 sbuf_printf(m, "Fenced object[%2d] = ", i);
 513                 if (obj == NULL)
 514                         sbuf_printf(m, "unused");
 515                 else
 516                         describe_obj(m, obj);
 517                 sbuf_printf(m, "\n");
 518         }
 519
 520         DRM_UNLOCK(dev);
 521         return (0);
 522 }
 523
 524 static int
 525 i915_hws_info(struct drm_device *dev, struct sbuf *m, void *data)
 526 {
 527         drm_i915_private_t *dev_priv = dev->dev_private;
 528         struct intel_ring_buffer *ring;
 529         const volatile u32 *hws;
 530         int i;
 531
 532         ring = &dev_priv->rings[(uintptr_t)data];
 533         hws = (volatile u32 *)ring->status_page.page_addr;
 534         if (hws == NULL)
 535                 return (0);
 536
 537         for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) {
 538                 sbuf_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n",
 539                            i * 4,
 540                            hws[i], hws[i + 1], hws[i + 2], hws[i + 3]);
 541         }
 542         return (0);
 543 }
 544
 545 static int
 546 i915_ringbuffer_data(struct drm_device *dev, struct sbuf *m, void *data)
 547 {
 548         drm_i915_private_t *dev_priv = dev->dev_private;
 549         struct intel_ring_buffer *ring;
 550
 551         if (lockmgr(&dev->dev_struct_lock, LK_EXCLUSIVE|LK_SLEEPFAIL))
 552                 return (EINTR);
 553         ring = &dev_priv->rings[(uintptr_t)data];
 554         if (!ring->obj) {
 555                 sbuf_printf(m, "No ringbuffer setup\n");
 556         } else {
 557                 u8 *virt = ring->virtual_start;
 558                 uint32_t off;
 559
 560                 for (off = 0; off < ring->size; off += 4) {
 561                         uint32_t *ptr = (uint32_t *)(virt + off);
 562                         sbuf_printf(m, "%08x :  %08x\n", off, *ptr);
 563                 }
 564         }
 565         DRM_UNLOCK(dev);
 566         return (0);
 567 }
 568
 569 static int
 570 i915_ringbuffer_info(struct drm_device *dev, struct sbuf *m, void *data)
 571 {
 572         drm_i915_private_t *dev_priv = dev->dev_private;
 573         struct intel_ring_buffer *ring;
 574
 575         ring = &dev_priv->rings[(uintptr_t)data];
 576         if (ring->size == 0)
 577                 return (0);
 578
 579         if (lockmgr(&dev->dev_struct_lock, LK_EXCLUSIVE|LK_SLEEPFAIL))
 580                 return (EINTR);
 581
 582         sbuf_printf(m, "Ring %s:\n", ring->name);
 583         sbuf_printf(m, "  Head :    %08x\n", I915_READ_HEAD(ring) & HEAD_ADDR);
 584         sbuf_printf(m, "  Tail :    %08x\n", I915_READ_TAIL(ring) & TAIL_ADDR);
 585         sbuf_printf(m, "  Size :    %08x\n", ring->size);
 586         sbuf_printf(m, "  Active :  %08x\n", intel_ring_get_active_head(ring));
 587         sbuf_printf(m, "  NOPID :   %08x\n", I915_READ_NOPID(ring));
 588         if (IS_GEN6(dev) || IS_GEN7(dev)) {
 589                 sbuf_printf(m, "  Sync 0 :   %08x\n", I915_READ_SYNC_0(ring));
 590                 sbuf_printf(m, "  Sync 1 :   %08x\n", I915_READ_SYNC_1(ring));
 591         }
 592         sbuf_printf(m, "  Control : %08x\n", I915_READ_CTL(ring));
 593         sbuf_printf(m, "  Start :   %08x\n", I915_READ_START(ring));
 594
 595         DRM_UNLOCK(dev);
 596
 597         return (0);
 598 }
 599
 600 static const char *
 601 ring_str(int ring)
 602 {
 603         switch (ring) {
 604         case RCS: return (" render");
 605         case VCS: return (" bsd");
 606         case BCS: return (" blt");
 607         default: return ("");
 608         }
 609 }
 610
 611 static const char *
 612 pin_flag(int pinned)
 613 {
 614         if (pinned > 0)
 615                 return (" P");
 616         else if (pinned < 0)
 617                 return (" p");
 618         else
 619                 return ("");
 620 }
 621
 622 static const char *tiling_flag(int tiling)
 623 {
 624         switch (tiling) {
 625         default:
 626         case I915_TILING_NONE: return "";
 627         case I915_TILING_X: return " X";
 628         case I915_TILING_Y: return " Y";
 629         }
 630 }
 631
 632 static const char *dirty_flag(int dirty)
 633 {
 634         return dirty ? " dirty" : "";
 635 }
 636
 637 static const char *purgeable_flag(int purgeable)
 638 {
 639         return purgeable ? " purgeable" : "";
 640 }
 641
 642 static void print_error_buffers(struct sbuf *m, const char *name,
 643     struct drm_i915_error_buffer *err, int count)
 644 {
 645
 646         sbuf_printf(m, "%s [%d]:\n", name, count);
 647
 648         while (count--) {
 649                 sbuf_printf(m, "  %08x %8u %04x %04x %08x%s%s%s%s%s%s%s",
 650                            err->gtt_offset,
 651                            err->size,
 652                            err->read_domains,
 653                            err->write_domain,
 654                            err->seqno,
 655                            pin_flag(err->pinned),
 656                            tiling_flag(err->tiling),
 657                            dirty_flag(err->dirty),
 658                            purgeable_flag(err->purgeable),
 659                            err->ring != -1 ? " " : "",
 660                            ring_str(err->ring),
 661                            cache_level_str(err->cache_level));
 662
 663                 if (err->name)
 664                         sbuf_printf(m, " (name: %d)", err->name);
 665                 if (err->fence_reg != I915_FENCE_REG_NONE)
 666                         sbuf_printf(m, " (fence: %d)", err->fence_reg);
 667
 668                 sbuf_printf(m, "\n");
 669                 err++;
 670         }
 671 }
 672
 673 static void
 674 i915_ring_error_state(struct sbuf *m, struct drm_device *dev,
 675     struct drm_i915_error_state *error, unsigned ring)
 676 {
 677
 678         sbuf_printf(m, "%s command stream:\n", ring_str(ring));
 679         sbuf_printf(m, "  HEAD: 0x%08x\n", error->head[ring]);
 680         sbuf_printf(m, "  TAIL: 0x%08x\n", error->tail[ring]);
 681         sbuf_printf(m, "  ACTHD: 0x%08x\n", error->acthd[ring]);
 682         sbuf_printf(m, "  IPEIR: 0x%08x\n", error->ipeir[ring]);
 683         sbuf_printf(m, "  IPEHR: 0x%08x\n", error->ipehr[ring]);
 684         sbuf_printf(m, "  INSTDONE: 0x%08x\n", error->instdone[ring]);
 685         if (ring == RCS && INTEL_INFO(dev)->gen >= 4) {
 686                 sbuf_printf(m, "  INSTDONE1: 0x%08x\n", error->instdone1);
 687                 sbuf_printf(m, "  BBADDR: 0x%08jx\n", (uintmax_t)error->bbaddr);
 688         }
 689         if (INTEL_INFO(dev)->gen >= 4)
 690                 sbuf_printf(m, "  INSTPS: 0x%08x\n", error->instps[ring]);
 691         sbuf_printf(m, "  INSTPM: 0x%08x\n", error->instpm[ring]);
 692         if (INTEL_INFO(dev)->gen >= 6) {
 693                 sbuf_printf(m, "  FADDR: 0x%08x\n", error->faddr[ring]);
 694                 sbuf_printf(m, "  FAULT_REG: 0x%08x\n", error->fault_reg[ring]);
 695                 sbuf_printf(m, "  SYNC_0: 0x%08x\n",
 696                            error->semaphore_mboxes[ring][0]);
 697                 sbuf_printf(m, "  SYNC_1: 0x%08x\n",
 698                            error->semaphore_mboxes[ring][1]);
 699         }
 700         sbuf_printf(m, "  seqno: 0x%08x\n", error->seqno[ring]);
 701         sbuf_printf(m, "  ring->head: 0x%08x\n", error->cpu_ring_head[ring]);
 702         sbuf_printf(m, "  ring->tail: 0x%08x\n", error->cpu_ring_tail[ring]);
 703 }
 704
 705 static int i915_error_state(struct drm_device *dev, struct sbuf *m,
 706     void *unused)
 707 {
 708         drm_i915_private_t *dev_priv = dev->dev_private;
 709         struct drm_i915_error_state *error;
 710         int i, j, page, offset, elt;
 711
 712         lockmgr(&dev_priv->error_lock, LK_EXCLUSIVE);
 713         if (!dev_priv->first_error) {
 714                 sbuf_printf(m, "no error state collected\n");
 715                 goto out;
 716         }
 717
 718         error = dev_priv->first_error;
 719
 720         sbuf_printf(m, "Time: %jd s %jd us\n", (intmax_t)error->time.tv_sec,
 721             (intmax_t)error->time.tv_usec);
 722         sbuf_printf(m, "PCI ID: 0x%04x\n", dev->pci_device);
 723         sbuf_printf(m, "EIR: 0x%08x\n", error->eir);
 724         sbuf_printf(m, "PGTBL_ER: 0x%08x\n", error->pgtbl_er);
 725
 726         for (i = 0; i < dev_priv->num_fence_regs; i++)
 727                 sbuf_printf(m, "  fence[%d] = %08jx\n", i,
 728                     (uintmax_t)error->fence[i]);
 729
 730         if (INTEL_INFO(dev)->gen >= 6) {
 731                 sbuf_printf(m, "ERROR: 0x%08x\n", error->error);
 732                 sbuf_printf(m, "DONE_REG: 0x%08x\n", error->done_reg);
 733         }
 734
 735         i915_ring_error_state(m, dev, error, RCS);
 736         if (HAS_BLT(dev))
 737                 i915_ring_error_state(m, dev, error, BCS);
 738         if (HAS_BSD(dev))
 739                 i915_ring_error_state(m, dev, error, VCS);
 740
 741         if (error->active_bo)
 742                 print_error_buffers(m, "Active",
 743                                     error->active_bo,
 744                                     error->active_bo_count);
 745
 746         if (error->pinned_bo)
 747                 print_error_buffers(m, "Pinned",
 748                                     error->pinned_bo,
 749                                     error->pinned_bo_count);
 750
 751         for (i = 0; i < DRM_ARRAY_SIZE(error->ring); i++) {
 752                 struct drm_i915_error_object *obj;
 753
 754                 if ((obj = error->ring[i].batchbuffer)) {
 755                         sbuf_printf(m, "%s --- gtt_offset = 0x%08x\n",
 756                                    dev_priv->rings[i].name,
 757                                    obj->gtt_offset);
 758                         offset = 0;
 759                         for (page = 0; page < obj->page_count; page++) {
 760                                 for (elt = 0; elt < PAGE_SIZE/4; elt++) {
 761                                         sbuf_printf(m, "%08x :  %08x\n",
 762                                             offset, obj->pages[page][elt]);
 763                                         offset += 4;
 764                                 }
 765                         }
 766                 }
 767
 768                 if (error->ring[i].num_requests) {
 769                         sbuf_printf(m, "%s --- %d requests\n",
 770                                    dev_priv->rings[i].name,
 771                                    error->ring[i].num_requests);
 772                         for (j = 0; j < error->ring[i].num_requests; j++) {
 773                                 sbuf_printf(m, "  seqno 0x%08x, emitted %ld, tail 0x%08x\n",
 774                                            error->ring[i].requests[j].seqno,
 775                                            error->ring[i].requests[j].jiffies,
 776                                            error->ring[i].requests[j].tail);
 777                         }
 778                 }
 779
 780                 if ((obj = error->ring[i].ringbuffer)) {
 781                         sbuf_printf(m, "%s --- ringbuffer = 0x%08x\n",
 782                                    dev_priv->rings[i].name,
 783                                    obj->gtt_offset);
 784                         offset = 0;
 785                         for (page = 0; page < obj->page_count; page++) {
 786                                 for (elt = 0; elt < PAGE_SIZE/4; elt++) {
 787                                         sbuf_printf(m, "%08x :  %08x\n",
 788                                                    offset,
 789                                                    obj->pages[page][elt]);
 790                                         offset += 4;
 791                                 }
 792                         }
 793                 }
 794         }
 795
 796         if (error->overlay)
 797                 intel_overlay_print_error_state(m, error->overlay);
 798
 799         if (error->display)
 800                 intel_display_print_error_state(m, dev, error->display);
 801
 802 out:
 803         lockmgr(&dev_priv->error_lock, LK_RELEASE);
 804
 805         return (0);
 806 }
 807
 808 static int
 809 i915_rstdby_delays(struct drm_device *dev, struct sbuf *m, void *unused)
 810 {
 811         drm_i915_private_t *dev_priv = dev->dev_private;
 812         u16 crstanddelay;
 813
 814         if (lockmgr(&dev->dev_struct_lock, LK_EXCLUSIVE|LK_SLEEPFAIL))
 815                 return (EINTR);
 816         crstanddelay = I915_READ16(CRSTANDVID);
 817         DRM_UNLOCK(dev);
 818
 819         sbuf_printf(m, "w/ctx: %d, w/o ctx: %d\n",
 820             (crstanddelay >> 8) & 0x3f, (crstanddelay & 0x3f));
 821
 822         return 0;
 823 }
 824
 825 static int
 826 i915_cur_delayinfo(struct drm_device *dev, struct sbuf *m, void *unused)
 827 {
 828         drm_i915_private_t *dev_priv = dev->dev_private;
 829
 830         if (IS_GEN5(dev)) {
 831                 u16 rgvswctl = I915_READ16(MEMSWCTL);
 832                 u16 rgvstat = I915_READ16(MEMSTAT_ILK);
 833
 834                 sbuf_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf);
 835                 sbuf_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f);
 836                 sbuf_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >>
 837                            MEMSTAT_VID_SHIFT);
 838                 sbuf_printf(m, "Current P-state: %d\n",
 839                            (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
 840         } else if (IS_GEN6(dev)) {
 841                 u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
 842                 u32 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
 843                 u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
 844                 u32 rpstat;
 845                 u32 rpupei, rpcurup, rpprevup;
 846                 u32 rpdownei, rpcurdown, rpprevdown;
 847                 int max_freq;
 848
 849                 /* RPSTAT1 is in the GT power well */
 850                 if (lockmgr(&dev->dev_struct_lock, LK_EXCLUSIVE|LK_SLEEPFAIL))
 851                         return (EINTR);
 852                 gen6_gt_force_wake_get(dev_priv);
 853
 854                 rpstat = I915_READ(GEN6_RPSTAT1);
 855                 rpupei = I915_READ(GEN6_RP_CUR_UP_EI);
 856                 rpcurup = I915_READ(GEN6_RP_CUR_UP);
 857                 rpprevup = I915_READ(GEN6_RP_PREV_UP);
 858                 rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI);
 859                 rpcurdown = I915_READ(GEN6_RP_CUR_DOWN);
 860                 rpprevdown = I915_READ(GEN6_RP_PREV_DOWN);
 861
 862                 gen6_gt_force_wake_put(dev_priv);
 863                 DRM_UNLOCK(dev);
 864
 865                 sbuf_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
 866                 sbuf_printf(m, "RPSTAT1: 0x%08x\n", rpstat);
 867                 sbuf_printf(m, "Render p-state ratio: %d\n",
 868                            (gt_perf_status & 0xff00) >> 8);
 869                 sbuf_printf(m, "Render p-state VID: %d\n",
 870                            gt_perf_status & 0xff);
 871                 sbuf_printf(m, "Render p-state limit: %d\n",
 872                            rp_state_limits & 0xff);
 873                 sbuf_printf(m, "CAGF: %dMHz\n", ((rpstat & GEN6_CAGF_MASK) >>
 874                                                 GEN6_CAGF_SHIFT) * 50);
 875                 sbuf_printf(m, "RP CUR UP EI: %dus\n", rpupei &
 876                            GEN6_CURICONT_MASK);
 877                 sbuf_printf(m, "RP CUR UP: %dus\n", rpcurup &
 878                            GEN6_CURBSYTAVG_MASK);
 879                 sbuf_printf(m, "RP PREV UP: %dus\n", rpprevup &
 880                            GEN6_CURBSYTAVG_MASK);
 881                 sbuf_printf(m, "RP CUR DOWN EI: %dus\n", rpdownei &
 882                            GEN6_CURIAVG_MASK);
 883                 sbuf_printf(m, "RP CUR DOWN: %dus\n", rpcurdown &
 884                            GEN6_CURBSYTAVG_MASK);
 885                 sbuf_printf(m, "RP PREV DOWN: %dus\n", rpprevdown &
 886                            GEN6_CURBSYTAVG_MASK);
 887
 888                 max_freq = (rp_state_cap & 0xff0000) >> 16;
 889                 sbuf_printf(m, "Lowest (RPN) frequency: %dMHz\n",
 890                            max_freq * 50);
 891
 892                 max_freq = (rp_state_cap & 0xff00) >> 8;
 893                 sbuf_printf(m, "Nominal (RP1) frequency: %dMHz\n",
 894                            max_freq * 50);
 895
 896                 max_freq = rp_state_cap & 0xff;
 897                 sbuf_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
 898                            max_freq * 50);
 899         } else {
 900                 sbuf_printf(m, "no P-state info available\n");
 901         }
 902
 903         return 0;
 904 }
 905
 906 static int
 907 i915_delayfreq_table(struct drm_device *dev, struct sbuf *m, void *unused)
 908 {
 909         drm_i915_private_t *dev_priv = dev->dev_private;
 910         u32 delayfreq;
 911         int i;
 912
 913         if (lockmgr(&dev->dev_struct_lock, LK_EXCLUSIVE|LK_SLEEPFAIL))
 914                 return (EINTR);
 915         for (i = 0; i < 16; i++) {
 916                 delayfreq = I915_READ(PXVFREQ_BASE + i * 4);
 917                 sbuf_printf(m, "P%02dVIDFREQ: 0x%08x (VID: %d)\n", i, delayfreq,
 918                            (delayfreq & PXVFREQ_PX_MASK) >> PXVFREQ_PX_SHIFT);
 919         }
 920         DRM_UNLOCK(dev);
 921         return (0);
 922 }
 923
 924 static inline int
 925 MAP_TO_MV(int map)
 926 {
 927         return 1250 - (map * 25);
 928 }
 929
 930 static int
 931 i915_inttoext_table(struct drm_device *dev, struct sbuf *m, void *unused)
 932 {
 933         drm_i915_private_t *dev_priv = dev->dev_private;
 934         u32 inttoext;
 935         int i;
 936
 937         if (lockmgr(&dev->dev_struct_lock, LK_EXCLUSIVE|LK_SLEEPFAIL))
 938                 return (EINTR);
 939         for (i = 1; i <= 32; i++) {
 940                 inttoext = I915_READ(INTTOEXT_BASE_ILK + i * 4);
 941                 sbuf_printf(m, "INTTOEXT%02d: 0x%08x\n", i, inttoext);
 942         }
 943         DRM_UNLOCK(dev);
 944
 945         return (0);
 946 }
 947
 948 static int
 949 ironlake_drpc_info(struct drm_device *dev, struct sbuf *m)
 950 {
 951         drm_i915_private_t *dev_priv = dev->dev_private;
 952         u32 rgvmodectl;
 953         u32 rstdbyctl;
 954         u16 crstandvid;
 955
 956         if (lockmgr(&dev->dev_struct_lock, LK_EXCLUSIVE|LK_SLEEPFAIL))
 957                 return (EINTR);
 958         rgvmodectl = I915_READ(MEMMODECTL);
 959         rstdbyctl = I915_READ(RSTDBYCTL);
 960         crstandvid = I915_READ16(CRSTANDVID);
 961         DRM_UNLOCK(dev);
 962
 963         sbuf_printf(m, "HD boost: %s\n", (rgvmodectl & MEMMODE_BOOST_EN) ?
 964                    "yes" : "no");
 965         sbuf_printf(m, "Boost freq: %d\n",
 966                    (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >>
 967                    MEMMODE_BOOST_FREQ_SHIFT);
 968         sbuf_printf(m, "HW control enabled: %s\n",
 969                    rgvmodectl & MEMMODE_HWIDLE_EN ? "yes" : "no");
 970         sbuf_printf(m, "SW control enabled: %s\n",
 971                    rgvmodectl & MEMMODE_SWMODE_EN ? "yes" : "no");
 972         sbuf_printf(m, "Gated voltage change: %s\n",
 973                    rgvmodectl & MEMMODE_RCLK_GATE ? "yes" : "no");
 974         sbuf_printf(m, "Starting frequency: P%d\n",
 975                    (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT);
 976         sbuf_printf(m, "Max P-state: P%d\n",
 977                    (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT);
 978         sbuf_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK));
 979         sbuf_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f));
 980         sbuf_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f));
 981         sbuf_printf(m, "Render standby enabled: %s\n",
 982                    (rstdbyctl & RCX_SW_EXIT) ? "no" : "yes");
 983         sbuf_printf(m, "Current RS state: ");
 984         switch (rstdbyctl & RSX_STATUS_MASK) {
 985         case RSX_STATUS_ON:
 986                 sbuf_printf(m, "on\n");
 987                 break;
 988         case RSX_STATUS_RC1:
 989                 sbuf_printf(m, "RC1\n");
 990                 break;
 991         case RSX_STATUS_RC1E:
 992                 sbuf_printf(m, "RC1E\n");
 993                 break;
 994         case RSX_STATUS_RS1:
 995                 sbuf_printf(m, "RS1\n");
 996                 break;
 997         case RSX_STATUS_RS2:
 998                 sbuf_printf(m, "RS2 (RC6)\n");
 999                 break;
1000         case RSX_STATUS_RS3:
1001                 sbuf_printf(m, "RC3 (RC6+)\n");
1002                 break;
1003         default:
1004                 sbuf_printf(m, "unknown\n");
1005                 break;
1006         }
1007
1008         return 0;
1009 }
1010
1011 static int
1012 gen6_drpc_info(struct drm_device *dev, struct sbuf *m)
1013 {
1014         drm_i915_private_t *dev_priv = dev->dev_private;
1015         u32 rpmodectl1, gt_core_status, rcctl1;
1016         unsigned forcewake_count;
1017         int count=0;
1018
1019         if (lockmgr(&dev->dev_struct_lock, LK_EXCLUSIVE|LK_SLEEPFAIL))
1020                 return (EINTR);
1021
1022         lockmgr(&dev_priv->gt_lock, LK_EXCLUSIVE);
1023         forcewake_count = dev_priv->forcewake_count;
1024         lockmgr(&dev_priv->gt_lock, LK_RELEASE);
1025
1026         if (forcewake_count) {
1027                 sbuf_printf(m, "RC information inaccurate because userspace "
1028                               "holds a reference \n");
1029         } else {
1030                 /* NB: we cannot use forcewake, else we read the wrong values */
1031                 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1))
1032                         DRM_UDELAY(10);
1033                 sbuf_printf(m, "RC information accurate: %s\n", yesno(count < 51));
1034         }
1035
1036         gt_core_status = DRM_READ32(dev_priv->mmio_map, GEN6_GT_CORE_STATUS);
1037         trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4);
1038
1039         rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1040         rcctl1 = I915_READ(GEN6_RC_CONTROL);
1041         DRM_UNLOCK(dev);
1042
1043         sbuf_printf(m, "Video Turbo Mode: %s\n",
1044                    yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1045         sbuf_printf(m, "HW control enabled: %s\n",
1046                    yesno(rpmodectl1 & GEN6_RP_ENABLE));
1047         sbuf_printf(m, "SW control enabled: %s\n",
1048                    yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1049                           GEN6_RP_MEDIA_SW_MODE));
1050         sbuf_printf(m, "RC1e Enabled: %s\n",
1051                    yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE));
1052         sbuf_printf(m, "RC6 Enabled: %s\n",
1053                    yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE));
1054         sbuf_printf(m, "Deep RC6 Enabled: %s\n",
1055                    yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE));
1056         sbuf_printf(m, "Deepest RC6 Enabled: %s\n",
1057                    yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE));
1058         sbuf_printf(m, "Current RC state: ");
1059         switch (gt_core_status & GEN6_RCn_MASK) {
1060         case GEN6_RC0:
1061                 if (gt_core_status & GEN6_CORE_CPD_STATE_MASK)
1062                         sbuf_printf(m, "Core Power Down\n");
1063                 else
1064                         sbuf_printf(m, "on\n");
1065                 break;
1066         case GEN6_RC3:
1067                 sbuf_printf(m, "RC3\n");
1068                 break;
1069         case GEN6_RC6:
1070                 sbuf_printf(m, "RC6\n");
1071                 break;
1072         case GEN6_RC7:
1073                 sbuf_printf(m, "RC7\n");
1074                 break;
1075         default:
1076                 sbuf_printf(m, "Unknown\n");
1077                 break;
1078         }
1079
1080         sbuf_printf(m, "Core Power Down: %s\n",
1081                    yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK));
1082         return 0;
1083 }
1084
1085 static int i915_drpc_info(struct drm_device *dev, struct sbuf *m, void *unused)
1086 {
1087
1088         if (IS_GEN6(dev) || IS_GEN7(dev))
1089                 return (gen6_drpc_info(dev, m));
1090         else
1091                 return (ironlake_drpc_info(dev, m));
1092 }
1093 static int
1094 i915_fbc_status(struct drm_device *dev, struct sbuf *m, void *unused)
1095 {
1096         drm_i915_private_t *dev_priv = dev->dev_private;
1097
1098         if (!I915_HAS_FBC(dev)) {
1099                 sbuf_printf(m, "FBC unsupported on this chipset");
1100                 return 0;
1101         }
1102
1103         if (intel_fbc_enabled(dev)) {
1104                 sbuf_printf(m, "FBC enabled");
1105         } else {
1106                 sbuf_printf(m, "FBC disabled: ");
1107                 switch (dev_priv->no_fbc_reason) {
1108                 case FBC_NO_OUTPUT:
1109                         sbuf_printf(m, "no outputs");
1110                         break;
1111                 case FBC_STOLEN_TOO_SMALL:
1112                         sbuf_printf(m, "not enough stolen memory");
1113                         break;
1114                 case FBC_UNSUPPORTED_MODE:
1115                         sbuf_printf(m, "mode not supported");
1116                         break;
1117                 case FBC_MODE_TOO_LARGE:
1118                         sbuf_printf(m, "mode too large");
1119                         break;
1120                 case FBC_BAD_PLANE:
1121                         sbuf_printf(m, "FBC unsupported on plane");
1122                         break;
1123                 case FBC_NOT_TILED:
1124                         sbuf_printf(m, "scanout buffer not tiled");
1125                         break;
1126                 case FBC_MULTIPLE_PIPES:
1127                         sbuf_printf(m, "multiple pipes are enabled");
1128                         break;
1129                 default:
1130                         sbuf_printf(m, "unknown reason");
1131                 }
1132         }
1133         return 0;
1134 }
1135
1136 static int
1137 i915_sr_status(struct drm_device *dev, struct sbuf *m, void *unused)
1138 {
1139         drm_i915_private_t *dev_priv = dev->dev_private;
1140         bool sr_enabled = false;
1141
1142         if (HAS_PCH_SPLIT(dev))
1143                 sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN;
1144         else if (IS_CRESTLINE(dev) || IS_I945G(dev) || IS_I945GM(dev))
1145                 sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
1146         else if (IS_I915GM(dev))
1147                 sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
1148         else if (IS_PINEVIEW(dev))
1149                 sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN;
1150
1151         sbuf_printf(m, "self-refresh: %s",
1152                    sr_enabled ? "enabled" : "disabled");
1153
1154         return (0);
1155 }
1156
1157 static int i915_ring_freq_table(struct drm_device *dev, struct sbuf *m,
1158     void *unused)
1159 {
1160         drm_i915_private_t *dev_priv = dev->dev_private;
1161         int gpu_freq, ia_freq;
1162
1163         if (!(IS_GEN6(dev) || IS_GEN7(dev))) {
1164                 sbuf_printf(m, "unsupported on this chipset");
1165                 return (0);
1166         }
1167
1168         if (lockmgr(&dev->dev_struct_lock, LK_EXCLUSIVE|LK_SLEEPFAIL))
1169                 return (EINTR);
1170
1171         sbuf_printf(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\n");
1172
1173         for (gpu_freq = dev_priv->min_delay; gpu_freq <= dev_priv->max_delay;
1174              gpu_freq++) {
1175                 I915_WRITE(GEN6_PCODE_DATA, gpu_freq);
1176                 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY |
1177                            GEN6_PCODE_READ_MIN_FREQ_TABLE);
1178                 if (_intel_wait_for(dev,
1179                     (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
1180                     10, 1, "915frq")) {
1181                         DRM_ERROR("pcode read of freq table timed out\n");
1182                         continue;
1183                 }
1184                 ia_freq = I915_READ(GEN6_PCODE_DATA);
1185                 sbuf_printf(m, "%d\t\t%d\n", gpu_freq * 50, ia_freq * 100);
1186         }
1187
1188         DRM_UNLOCK(dev);
1189
1190         return (0);
1191 }
1192
1193 static int
1194 i915_emon_status(struct drm_device *dev, struct sbuf *m, void *unused)
1195 {
1196         drm_i915_private_t *dev_priv = dev->dev_private;
1197         unsigned long temp, chipset, gfx;
1198
1199         if (!IS_GEN5(dev)) {
1200                 sbuf_printf(m, "Not supported\n");
1201                 return (0);
1202         }
1203
1204         if (lockmgr(&dev->dev_struct_lock, LK_EXCLUSIVE|LK_SLEEPFAIL))
1205                 return (EINTR);
1206         temp = i915_mch_val(dev_priv);
1207         chipset = i915_chipset_val(dev_priv);
1208         gfx = i915_gfx_val(dev_priv);
1209         DRM_UNLOCK(dev);
1210
1211         sbuf_printf(m, "GMCH temp: %ld\n", temp);
1212         sbuf_printf(m, "Chipset power: %ld\n", chipset);
1213         sbuf_printf(m, "GFX power: %ld\n", gfx);
1214         sbuf_printf(m, "Total power: %ld\n", chipset + gfx);
1215
1216         return (0);
1217 }
1218
1219 static int
1220 i915_gfxec(struct drm_device *dev, struct sbuf *m, void *unused)
1221 {
1222         drm_i915_private_t *dev_priv = dev->dev_private;
1223
1224         if (lockmgr(&dev->dev_struct_lock, LK_EXCLUSIVE|LK_SLEEPFAIL))
1225                 return (EINTR);
1226         sbuf_printf(m, "GFXEC: %ld\n", (unsigned long)I915_READ(0x112f4));
1227         DRM_UNLOCK(dev);
1228
1229         return (0);
1230 }
1231
1232 #if 0
1233 static int
1234 i915_opregion(struct drm_device *dev, struct sbuf *m, void *unused)
1235 {
1236         drm_i915_private_t *dev_priv = dev->dev_private;
1237         struct intel_opregion *opregion = &dev_priv->opregion;
1238
1239         if (lockmgr(&dev->dev_struct_lock, LK_EXCLUSIVE|LK_SLEEPFAIL))
1240                 return (EINTR);
1241         if (opregion->header)
1242                 seq_write(m, opregion->header, OPREGION_SIZE);
1243         DRM_UNLOCK(dev);
1244
1245         return 0;
1246 }
1247 #endif
1248
1249 static int
1250 i915_gem_framebuffer_info(struct drm_device *dev, struct sbuf *m, void *data)
1251 {
1252         drm_i915_private_t *dev_priv = dev->dev_private;
1253         struct intel_fbdev *ifbdev;
1254         struct intel_framebuffer *fb;
1255
1256         if (lockmgr(&dev->dev_struct_lock, LK_EXCLUSIVE|LK_SLEEPFAIL))
1257                 return (EINTR);
1258
1259         ifbdev = dev_priv->fbdev;
1260         if (ifbdev == NULL) {
1261                 DRM_UNLOCK(dev);
1262                 return (0);
1263         }
1264         fb = to_intel_framebuffer(ifbdev->helper.fb);
1265
1266         sbuf_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, obj ",
1267                    fb->base.width,
1268                    fb->base.height,
1269                    fb->base.depth,
1270                    fb->base.bits_per_pixel);
1271         describe_obj(m, fb->obj);
1272         sbuf_printf(m, "\n");
1273
1274         list_for_each_entry(fb, &dev->mode_config.fb_list, base.head) {
1275                 if (&fb->base == ifbdev->helper.fb)
1276                         continue;
1277
1278                 sbuf_printf(m, "user size: %d x %d, depth %d, %d bpp, obj ",
1279                            fb->base.width,
1280                            fb->base.height,
1281                            fb->base.depth,
1282                            fb->base.bits_per_pixel);
1283                 describe_obj(m, fb->obj);
1284                 sbuf_printf(m, "\n");
1285         }
1286
1287         DRM_UNLOCK(dev);
1288
1289         return (0);
1290 }
1291
1292 static int
1293 i915_context_status(struct drm_device *dev, struct sbuf *m, void *data)
1294 {
1295         drm_i915_private_t *dev_priv;
1296         int ret;
1297
1298         if ((dev->driver->driver_features & DRIVER_MODESET) == 0)
1299                 return (0);
1300
1301         dev_priv = dev->dev_private;
1302         ret = lockmgr(&dev->mode_config.lock, LK_EXCLUSIVE|LK_SLEEPFAIL);
1303         if (ret != 0)
1304                 return (EINTR);
1305
1306         if (dev_priv->pwrctx != NULL) {
1307                 sbuf_printf(m, "power context ");
1308                 describe_obj(m, dev_priv->pwrctx);
1309                 sbuf_printf(m, "\n");
1310         }
1311
1312         if (dev_priv->renderctx != NULL) {
1313                 sbuf_printf(m, "render context ");
1314                 describe_obj(m, dev_priv->renderctx);
1315                 sbuf_printf(m, "\n");
1316         }
1317
1318         lockmgr(&dev->mode_config.lock, LK_RELEASE);
1319
1320         return (0);
1321 }
1322
1323 static int
1324 i915_gen6_forcewake_count_info(struct drm_device *dev, struct sbuf *m,
1325     void *data)
1326 {
1327         struct drm_i915_private *dev_priv;
1328         unsigned forcewake_count;
1329
1330         dev_priv = dev->dev_private;
1331         lockmgr(&dev_priv->gt_lock, LK_EXCLUSIVE);
1332         forcewake_count = dev_priv->forcewake_count;
1333         lockmgr(&dev_priv->gt_lock, LK_RELEASE);
1334
1335         sbuf_printf(m, "forcewake count = %u\n", forcewake_count);
1336
1337         return (0);
1338 }
1339
1340 static const char *
1341 swizzle_string(unsigned swizzle)
1342 {
1343
1344         switch(swizzle) {
1345         case I915_BIT_6_SWIZZLE_NONE:
1346                 return "none";
1347         case I915_BIT_6_SWIZZLE_9:
1348                 return "bit9";
1349         case I915_BIT_6_SWIZZLE_9_10:
1350                 return "bit9/bit10";
1351         case I915_BIT_6_SWIZZLE_9_11:
1352                 return "bit9/bit11";
1353         case I915_BIT_6_SWIZZLE_9_10_11:
1354                 return "bit9/bit10/bit11";
1355         case I915_BIT_6_SWIZZLE_9_17:
1356                 return "bit9/bit17";
1357         case I915_BIT_6_SWIZZLE_9_10_17:
1358                 return "bit9/bit10/bit17";
1359         case I915_BIT_6_SWIZZLE_UNKNOWN:
1360                 return "unknown";
1361         }
1362
1363         return "bug";
1364 }
1365
1366 static int
1367 i915_swizzle_info(struct drm_device *dev, struct sbuf *m, void *data)
1368 {
1369         struct drm_i915_private *dev_priv;
1370         int ret;
1371
1372         dev_priv = dev->dev_private;
1373         ret = lockmgr(&dev->dev_struct_lock, LK_EXCLUSIVE|LK_SLEEPFAIL);
1374         if (ret != 0)
1375                 return (EINTR);
1376
1377         sbuf_printf(m, "bit6 swizzle for X-tiling = %s\n",
1378                    swizzle_string(dev_priv->mm.bit_6_swizzle_x));
1379         sbuf_printf(m, "bit6 swizzle for Y-tiling = %s\n",
1380                    swizzle_string(dev_priv->mm.bit_6_swizzle_y));
1381
1382         if (IS_GEN3(dev) || IS_GEN4(dev)) {
1383                 sbuf_printf(m, "DDC = 0x%08x\n",
1384                            I915_READ(DCC));
1385                 sbuf_printf(m, "C0DRB3 = 0x%04x\n",
1386                            I915_READ16(C0DRB3));
1387                 sbuf_printf(m, "C1DRB3 = 0x%04x\n",
1388                            I915_READ16(C1DRB3));
1389         } else if (IS_GEN6(dev) || IS_GEN7(dev)) {
1390                 sbuf_printf(m, "MAD_DIMM_C0 = 0x%08x\n",
1391                            I915_READ(MAD_DIMM_C0));
1392                 sbuf_printf(m, "MAD_DIMM_C1 = 0x%08x\n",
1393                            I915_READ(MAD_DIMM_C1));
1394                 sbuf_printf(m, "MAD_DIMM_C2 = 0x%08x\n",
1395                            I915_READ(MAD_DIMM_C2));
1396                 sbuf_printf(m, "TILECTL = 0x%08x\n",
1397                            I915_READ(TILECTL));
1398                 sbuf_printf(m, "ARB_MODE = 0x%08x\n",
1399                            I915_READ(ARB_MODE));
1400                 sbuf_printf(m, "DISP_ARB_CTL = 0x%08x\n",
1401                            I915_READ(DISP_ARB_CTL));
1402         }
1403         DRM_UNLOCK(dev);
1404
1405         return (0);
1406 }
1407
1408 static int
1409 i915_ppgtt_info(struct drm_device *dev, struct sbuf *m, void *data)
1410 {
1411         struct drm_i915_private *dev_priv;
1412         struct intel_ring_buffer *ring;
1413         int i, ret;
1414
1415         dev_priv = dev->dev_private;
1416
1417         ret = lockmgr(&dev->dev_struct_lock, LK_EXCLUSIVE|LK_SLEEPFAIL);
1418         if (ret != 0)
1419                 return (EINTR);
1420         if (INTEL_INFO(dev)->gen == 6)
1421                 sbuf_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE));
1422
1423         for (i = 0; i < I915_NUM_RINGS; i++) {
1424                 ring = &dev_priv->rings[i];
1425
1426                 sbuf_printf(m, "%s\n", ring->name);
1427                 if (INTEL_INFO(dev)->gen == 7)
1428                         sbuf_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(RING_MODE_GEN7(ring)));
1429                 sbuf_printf(m, "PP_DIR_BASE: 0x%08x\n", I915_READ(RING_PP_DIR_BASE(ring)));
1430                 sbuf_printf(m, "PP_DIR_BASE_READ: 0x%08x\n", I915_READ(RING_PP_DIR_BASE_READ(ring)));
1431                 sbuf_printf(m, "PP_DIR_DCLV: 0x%08x\n", I915_READ(RING_PP_DIR_DCLV(ring)));
1432         }
1433         if (dev_priv->mm.aliasing_ppgtt) {
1434                 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
1435
1436                 sbuf_printf(m, "aliasing PPGTT:\n");
1437                 sbuf_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd_offset);
1438         }
1439         sbuf_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK));
1440         DRM_UNLOCK(dev);
1441
1442         return (0);
1443 }
1444
1445 static int
1446 i915_debug_set_wedged(SYSCTL_HANDLER_ARGS)
1447 {
1448         struct drm_device *dev;
1449         drm_i915_private_t *dev_priv;
1450         int error, wedged;
1451
1452         dev = arg1;
1453         dev_priv = dev->dev_private;
1454         if (dev_priv == NULL)
1455                 return (EBUSY);
1456         wedged = dev_priv->mm.wedged;
1457         error = sysctl_handle_int(oidp, &wedged, 0, req);
1458         if (error || !req->newptr)
1459                 return (error);
1460         DRM_INFO("Manually setting wedged to %d\n", wedged);
1461         i915_handle_error(dev, wedged);
1462         return (error);
1463 }
1464
1465 static int
1466 i915_max_freq(SYSCTL_HANDLER_ARGS)
1467 {
1468         struct drm_device *dev;
1469         drm_i915_private_t *dev_priv;
1470         int error, max_freq;
1471
1472         dev = arg1;
1473         dev_priv = dev->dev_private;
1474         if (dev_priv == NULL)
1475                 return (EBUSY);
1476         max_freq = dev_priv->max_delay * 50;
1477         error = sysctl_handle_int(oidp, &max_freq, 0, req);
1478         if (error || !req->newptr)
1479                 return (error);
1480         DRM_DEBUG("Manually setting max freq to %d\n", max_freq);
1481         /*
1482          * Turbo will still be enabled, but won't go above the set value.
1483          */
1484         dev_priv->max_delay = max_freq / 50;
1485         gen6_set_rps(dev, max_freq / 50);
1486         return (error);
1487 }
1488
1489 static int
1490 i915_cache_sharing(SYSCTL_HANDLER_ARGS)
1491 {
1492         struct drm_device *dev;
1493         drm_i915_private_t *dev_priv;
1494         int error, snpcr, cache_sharing;
1495
1496         dev = arg1;
1497         dev_priv = dev->dev_private;
1498         if (dev_priv == NULL)
1499                 return (EBUSY);
1500         DRM_LOCK(dev);
1501         snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
1502         DRM_UNLOCK(dev);
1503         cache_sharing = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT;
1504         error = sysctl_handle_int(oidp, &cache_sharing, 0, req);
1505         if (error || !req->newptr)
1506                 return (error);
1507         if (cache_sharing < 0 || cache_sharing > 3)
1508                 return (EINVAL);
1509         DRM_DEBUG("Manually setting uncore sharing to %d\n", cache_sharing);
1510
1511         DRM_LOCK(dev);
1512         /* Update the cache sharing policy here as well */
1513         snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
1514         snpcr &= ~GEN6_MBC_SNPCR_MASK;
1515         snpcr |= (cache_sharing << GEN6_MBC_SNPCR_SHIFT);
1516         I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
1517         DRM_UNLOCK(dev);
1518         return (0);
1519 }
1520
1521 static struct i915_info_sysctl_list {
1522         const char *name;
1523         int (*ptr)(struct drm_device *dev, struct sbuf *m, void *data);
1524         int flags;
1525         void *data;
1526 } i915_info_sysctl_list[] = {
1527         {"i915_capabilities", i915_capabilities, 0},
1528         {"i915_gem_objects", i915_gem_object_info, 0},
1529         {"i915_gem_gtt", i915_gem_gtt_info, 0},
1530         {"i915_gem_active", i915_gem_object_list_info, 0, (void *)ACTIVE_LIST},
1531         {"i915_gem_flushing", i915_gem_object_list_info, 0,
1532             (void *)FLUSHING_LIST},
1533         {"i915_gem_inactive", i915_gem_object_list_info, 0,
1534             (void *)INACTIVE_LIST},
1535         {"i915_gem_pinned", i915_gem_object_list_info, 0,
1536             (void *)PINNED_LIST},
1537         {"i915_gem_deferred_free", i915_gem_object_list_info, 0,
1538             (void *)DEFERRED_FREE_LIST},
1539         {"i915_gem_pageflip", i915_gem_pageflip_info, 0},
1540         {"i915_gem_request", i915_gem_request_info, 0},
1541         {"i915_gem_seqno", i915_gem_seqno_info, 0},
1542         {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0},
1543         {"i915_gem_interrupt", i915_interrupt_info, 0},
1544         {"i915_gem_hws", i915_hws_info, 0, (void *)RCS},
1545         {"i915_gem_hws_blt", i915_hws_info, 0, (void *)BCS},
1546         {"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS},
1547         {"i915_ringbuffer_data", i915_ringbuffer_data, 0, (void *)RCS},
1548         {"i915_ringbuffer_info", i915_ringbuffer_info, 0, (void *)RCS},
1549         {"i915_bsd_ringbuffer_data", i915_ringbuffer_data, 0, (void *)VCS},
1550         {"i915_bsd_ringbuffer_info", i915_ringbuffer_info, 0, (void *)VCS},
1551         {"i915_blt_ringbuffer_data", i915_ringbuffer_data, 0, (void *)BCS},
1552         {"i915_blt_ringbuffer_info", i915_ringbuffer_info, 0, (void *)BCS},
1553         {"i915_error_state", i915_error_state, 0},
1554         {"i915_rstdby_delays", i915_rstdby_delays, 0},
1555         {"i915_cur_delayinfo", i915_cur_delayinfo, 0},
1556         {"i915_delayfreq_table", i915_delayfreq_table, 0},
1557         {"i915_inttoext_table", i915_inttoext_table, 0},
1558         {"i915_drpc_info", i915_drpc_info, 0},
1559         {"i915_emon_status", i915_emon_status, 0},
1560         {"i915_ring_freq_table", i915_ring_freq_table, 0},
1561         {"i915_gfxec", i915_gfxec, 0},
1562         {"i915_fbc_status", i915_fbc_status, 0},
1563         {"i915_sr_status", i915_sr_status, 0},
1564 #if 0
1565         {"i915_opregion", i915_opregion, 0},
1566 #endif
1567         {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0},
1568         {"i915_context_status", i915_context_status, 0},
1569         {"i915_gen6_forcewake_count_info", i915_gen6_forcewake_count_info, 0},
1570         {"i915_swizzle_info", i915_swizzle_info, 0},
1571         {"i915_ppgtt_info", i915_ppgtt_info, 0},
1572 };
1573
1574 struct i915_info_sysctl_thunk {
1575         struct drm_device *dev;
1576         int idx;
1577         void *arg;
1578 };
1579
1580 static int
1581 i915_info_sysctl_handler(SYSCTL_HANDLER_ARGS)
1582 {
1583 #if 0
1584         struct sbuf m;
1585 #endif
1586         struct i915_info_sysctl_thunk *thunk;
1587         struct drm_device *dev;
1588         drm_i915_private_t *dev_priv;
1589         int error;
1590
1591         thunk = arg1;
1592         dev = thunk->dev;
1593         dev_priv = dev->dev_private;
1594         if (dev_priv == NULL)
1595                 return (EBUSY);
1596 #if 0
1597         error = sysctl_wire_old_buffer(req, 0);
1598         if (error != 0)
1599                 return (error);
1600         sbuf_new_for_sysctl(&m, NULL, 128, req);
1601         error = i915_info_sysctl_list[thunk->idx].ptr(dev, &m,
1602             thunk->arg);
1603         if (error == 0)
1604                 error = sbuf_finish(&m);
1605         sbuf_delete(&m);
1606 #else
1607         error = 0;
1608 #endif
1609         return (error);
1610 }
1611
1612 extern int i915_gem_sync_exec_requests;
1613 extern int i915_fix_mi_batchbuffer_end;
1614 extern int i915_intr_pf;
1615 extern long i915_gem_wired_pages_cnt;
1616
1617 int
1618 i915_sysctl_init(struct drm_device *dev, struct sysctl_ctx_list *ctx,
1619     struct sysctl_oid *top)
1620 {
1621         struct sysctl_oid *oid, *info;
1622         struct i915_info_sysctl_thunk *thunks;
1623         int i, error;
1624
1625         thunks = kmalloc(sizeof(*thunks) * DRM_ARRAY_SIZE(i915_info_sysctl_list),
1626             DRM_MEM_DRIVER, M_WAITOK | M_ZERO);
1627         for (i = 0; i < DRM_ARRAY_SIZE(i915_info_sysctl_list); i++) {
1628                 thunks[i].dev = dev;
1629                 thunks[i].idx = i;
1630                 thunks[i].arg = i915_info_sysctl_list[i].data;
1631         }
1632         dev->sysctl_private = thunks;
1633         info = SYSCTL_ADD_NODE(ctx, SYSCTL_CHILDREN(top), OID_AUTO, "info",
1634             CTLFLAG_RW, NULL, NULL);
1635         if (info == NULL)
1636                 return (ENOMEM);
1637         for (i = 0; i < DRM_ARRAY_SIZE(i915_info_sysctl_list); i++) {
1638                 oid = SYSCTL_ADD_OID(ctx, SYSCTL_CHILDREN(info), OID_AUTO,
1639                     i915_info_sysctl_list[i].name, CTLTYPE_STRING | CTLFLAG_RD,
1640                     &thunks[i], 0, i915_info_sysctl_handler, "A", NULL);
1641                 if (oid == NULL)
1642                         return (ENOMEM);
1643         }
1644         oid = SYSCTL_ADD_LONG(ctx, SYSCTL_CHILDREN(info), OID_AUTO,
1645             "i915_gem_wired_pages", CTLFLAG_RD, &i915_gem_wired_pages_cnt,
1646             NULL);
1647         oid = SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(top), OID_AUTO, "wedged",
1648             CTLTYPE_INT | CTLFLAG_RW, dev, 0,
1649             i915_debug_set_wedged, "I", NULL);
1650         if (oid == NULL)
1651                 return (ENOMEM);
1652         oid = SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(top), OID_AUTO, "max_freq",
1653             CTLTYPE_INT | CTLFLAG_RW, dev, 0, i915_max_freq,
1654             "I", NULL);
1655         if (oid == NULL)
1656                 return (ENOMEM);
1657         oid = SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(top), OID_AUTO,
1658             "cache_sharing", CTLTYPE_INT | CTLFLAG_RW, dev,
1659             0, i915_cache_sharing, "I", NULL);
1660         if (oid == NULL)
1661                 return (ENOMEM);
1662         oid = SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(top), OID_AUTO, "sync_exec",
1663             CTLFLAG_RW, &i915_gem_sync_exec_requests, 0, NULL);
1664         if (oid == NULL)
1665                 return (ENOMEM);
1666         oid = SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(top), OID_AUTO, "fix_mi",
1667             CTLFLAG_RW, &i915_fix_mi_batchbuffer_end, 0, NULL);
1668         if (oid == NULL)
1669                 return (ENOMEM);
1670         oid = SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(top), OID_AUTO, "intr_pf",
1671             CTLFLAG_RW, &i915_intr_pf, 0, NULL);
1672         if (oid == NULL)
1673                 return (ENOMEM);
1674
1675         error = drm_add_busid_modesetting(dev, ctx, top);
1676         if (error != 0)
1677                 return (error);
1678
1679         return (0);
1680 }
1681
1682 void
1683 i915_sysctl_cleanup(struct drm_device *dev)
1684 {
1685
1686         drm_free(dev->sysctl_private, DRM_MEM_DRIVER);
1687 }