1 /**************************************************************************
3 Copyright (c) 2001-2006, Intel Corporation
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7 modification, are permitted provided that the following conditions are met:
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32 ***************************************************************************/
34 /*$FreeBSD: src/sys/dev/em/if_em.h,v 1.1.2.13 2003/06/09 21:43:41 pdeuskar Exp $*/
35 /*$DragonFly: src/sys/dev/netif/em/if_em.h,v 1.19 2006/12/23 10:39:16 sephe Exp $*/
37 #ifndef _EM_H_DEFINED_
38 #define _EM_H_DEFINED_
43 * EM_TXD: Maximum number of Transmit Descriptors
44 * Valid Range: 80-256 for 82542 and 82543-based adapters
47 * This value is the number of transmit descriptors allocated by the driver.
48 * Increasing this value allows the driver to queue more transmits. Each
49 * descriptor is 16 bytes.
50 * Since TDLEN should be multiple of 128bytes, the number of transmit
51 * desscriptors should meet the following condition.
52 * (num_tx_desc * sizeof(struct em_tx_desc)) % 128 == 0
55 #define EM_MAX_TXD_82543 256
56 #define EM_MAX_TXD 4096
57 #define EM_DEFAULT_TXD EM_MAX_TXD_82543
60 * EM_RXD - Maximum number of receive Descriptors
61 * Valid Range: 80-256 for 82542 and 82543-based adapters
64 * This value is the number of receive descriptors allocated by the driver.
65 * Increasing this value allows the driver to buffer more incoming packets.
66 * Each descriptor is 16 bytes. A receive buffer is also allocated for each
67 * descriptor. The maximum MTU size is 16110.
68 * Since TDLEN should be multiple of 128bytes, the number of transmit
69 * desscriptors should meet the following condition.
70 * (num_tx_desc * sizeof(struct em_tx_desc)) % 128 == 0
73 #define EM_MAX_RXD_82543 256
74 #define EM_MAX_RXD 4096
75 #define EM_DEFAULT_RXD EM_MAX_RXD_82543
78 * EM_TIDV - Transmit Interrupt Delay Value
79 * Valid Range: 0-65535 (0=off)
81 * This value delays the generation of transmit interrupts in units of
82 * 1.024 microseconds. Transmit interrupt reduction can improve CPU
83 * efficiency if properly tuned for specific network traffic. If the
84 * system is reporting dropped transmits, this value may be set too high
85 * causing the driver to run out of available transmit descriptors.
90 * EM_TADV - Transmit Absolute Interrupt Delay Value
91 * (Not valid for 82542/82543/82544)
92 * Valid Range: 0-65535 (0=off)
94 * This value, in units of 1.024 microseconds, limits the delay in which a
95 * transmit interrupt is generated. Useful only if EM_TIDV is non-zero,
96 * this value ensures that an interrupt is generated after the initial
97 * packet is sent on the wire within the set amount of time. Proper tuning,
98 * along with EM_TIDV, may improve traffic throughput in specific
104 * EM_RDTR - Receive Interrupt Delay Timer (Packet Timer)
105 * Valid Range: 0-65535 (0=off)
107 * This value delays the generation of receive interrupts in units of 1.024
108 * microseconds. Receive interrupt reduction can improve CPU efficiency if
109 * properly tuned for specific network traffic. Increasing this value adds
110 * extra latency to frame reception and can end up decreasing the throughput
111 * of TCP traffic. If the system is reporting dropped receives, this value
112 * may be set too high, causing the driver to run out of available receive
115 * CAUTION: When setting EM_RDTR to a value other than 0, adapters
116 * may hang (stop transmitting) under certain network conditions.
117 * If this occurs a WATCHDOG message is logged in the system
118 * event log. In addition, the controller is automatically reset,
119 * restoring the network connection. To eliminate the potential
120 * for the hang ensure that EM_RDTR is set to 0.
125 * Receive Interrupt Absolute Delay Timer (Not valid for 82542/82543/82544)
126 * Valid Range: 0-65535 (0=off)
128 * This value, in units of 1.024 microseconds, limits the delay in which a
129 * receive interrupt is generated. Useful only if EM_RDTR is non-zero,
130 * this value ensures that an interrupt is generated after the initial
131 * packet is received within the set amount of time. Proper tuning,
132 * along with EM_RDTR, may improve traffic throughput in specific network
138 * Inform the stack about transmit checksum offload capabilities.
140 #define EM_CHECKSUM_FEATURES (CSUM_TCP | CSUM_UDP)
143 * This parameter controls the duration of transmit watchdog timer.
145 #define EM_TX_TIMEOUT 5 /* set to 5 seconds */
148 * This parameter controls when the driver calls the routine to reclaim
149 * transmit descriptors.
151 #define EM_TX_CLEANUP_THRESHOLD (adapter->num_tx_desc / 8)
154 * This parameter controls whether or not autonegotation is enabled.
155 * 0 - Disable autonegotiation
156 * 1 - Enable autonegotiation
158 #define DO_AUTO_NEG 1
161 * This parameter control whether or not the driver will wait for
162 * autonegotiation to complete.
163 * 1 - Wait for autonegotiation to complete
164 * 0 - Don't wait for autonegotiation to complete
166 #define WAIT_FOR_AUTO_NEG_DEFAULT 0
169 * EM_MASTER_SLAVE is only defined to enable a workaround for a known
170 * compatibility issue with 82541/82547 devices and some switches.
171 * See the "Known Limitations" section of the README file for a complete
172 * description and a list of affected switches.
174 * 0 = Hardware default
177 * 3 = Auto master/slave
179 /* #define EM_MASTER_SLAVE 2 */
181 /* Tunables -- End */
183 #define AUTONEG_ADV_DEFAULT (ADVERTISE_10_HALF | ADVERTISE_10_FULL | \
184 ADVERTISE_100_HALF | ADVERTISE_100_FULL | \
187 #define EM_VENDOR_ID 0x8086
188 #define EM_FLASH 0x0014 /* Flash memory on ICH8 */
190 #define EM_JUMBO_PBA 0x00000028
191 #define EM_DEFAULT_PBA 0x00000030
192 #define EM_SMARTSPEED_DOWNSHIFT 3
193 #define EM_SMARTSPEED_MAX 15
195 #define MAX_NUM_MULTICAST_ADDRESSES 128
196 #define PCI_ANY_ID (~0U)
200 * TDBA/RDBA should be aligned on 16 byte boundary. But TDLEN/RDLEN should be
201 * multiple of 128 bytes. So we align TDBA/RDBA on 128 byte boundary. This will
202 * also optimize cache line size effect. H/W supports up to cache line size 128.
204 #define EM_DBA_ALIGN 128
206 #define SPEED_MODE_BIT (1 << 21) /* On PCI-E MACs only */
208 /* PCI Config defines */
209 #define EM_BAR_TYPE(v) ((v) & EM_BAR_TYPE_MASK)
210 #define EM_BAR_TYPE_MASK 0x00000001
211 #define EM_BAR_TYPE_MMEM 0x00000000
212 #define EM_BAR_TYPE_IO 0x00000001
213 #define EM_BAR_MEM_TYPE(v) ((v) & EM_BAR_MEM_TYPE_MASK)
214 #define EM_BAR_MEM_TYPE_MASK 0x00000006
215 #define EM_BAR_MEM_TYPE_32BIT 0x00000000
216 #define EM_BAR_MEM_TYPE_64BIT 0x00000004
219 * Community introduced backward
220 * compatibility issue.
222 #if !defined(PCIR_CIS)
223 #define PCIR_CIS PCIR_CARDBUSCIS
226 /* Defines for printing debug information */
228 #define DEBUG_IOCTL 0
231 #define INIT_DEBUGOUT(S) if (DEBUG_INIT) kprintf(S "\n")
232 #define INIT_DEBUGOUT1(S, A) if (DEBUG_INIT) kprintf(S "\n", A)
233 #define INIT_DEBUGOUT2(S, A, B) if (DEBUG_INIT) kprintf(S "\n", A, B)
234 #define IOCTL_DEBUGOUT(S) if (DEBUG_IOCTL) kprintf(S "\n")
235 #define IOCTL_DEBUGOUT1(S, A) if (DEBUG_IOCTL) kprintf(S "\n", A)
236 #define IOCTL_DEBUGOUT2(S, A, B) if (DEBUG_IOCTL) kprintf(S "\n", A, B)
237 #define HW_DEBUGOUT(S) if (DEBUG_HW) kprintf(S "\n")
238 #define HW_DEBUGOUT1(S, A) if (DEBUG_HW) kprintf(S "\n", A)
239 #define HW_DEBUGOUT2(S, A, B) if (DEBUG_HW) kprintf(S "\n", A, B)
242 /* Supported RX Buffer Sizes */
243 #define EM_RXBUFFER_2048 2048
244 #define EM_RXBUFFER_4096 4096
245 #define EM_RXBUFFER_8192 8192
246 #define EM_RXBUFFER_16384 16384
248 #define EM_MAX_SCATTER 64
250 /* ******************************************************************************
253 * This array contains the list of Subvendor/Subdevice IDs on which the driver
256 * ******************************************************************************/
257 typedef struct _em_vendor_info_t {
258 unsigned int vendor_id;
259 unsigned int device_id;
260 unsigned int subvendor_id;
261 unsigned int subdevice_id;
267 int next_eop; /* Index of the desc to watch */
269 bus_dmamap_t map; /* bus_dma map for packet */
273 int nsegs; /* # of segments/descriptors */
274 bus_dma_segment_t segs[EM_MAX_SCATTER];
278 * Bus dma allocation structure used by
279 * em_dma_malloc and em_dma_free.
281 struct em_dma_alloc {
282 bus_addr_t dma_paddr;
284 bus_dma_tag_t dma_tag;
285 bus_dmamap_t dma_map;
286 bus_dma_segment_t dma_seg;
290 typedef enum _XSUM_CONTEXT_T {
297 struct em_int_delay_info {
298 struct adapter *adapter; /* Back-pointer to the adapter struct */
299 int offset; /* Register offset to read/write */
300 int value; /* Current value in usecs */
303 /* For 82544 PCIX Workaround */
304 typedef struct _ADDRESS_LENGTH_PAIR
308 } ADDRESS_LENGTH_PAIR, *PADDRESS_LENGTH_PAIR;
310 typedef struct _DESCRIPTOR_PAIR
312 ADDRESS_LENGTH_PAIR descriptor[4];
314 } DESC_ARRAY, *PDESC_ARRAY;
316 /* Our adapter structure */
318 struct arpcom interface_data;
321 /* Operating-system-specific structures */
322 struct em_osdep osdep;
324 struct resource *res_memory;
325 struct resource *flash_mem;
326 struct resource *res_ioport;
327 struct resource *res_interrupt;
328 void *int_handler_tag;
329 struct ifmedia media;
330 struct callout timer;
331 struct callout tx_fifo_timer;
334 int em_insert_vlan_header;
336 /* Info about the board itself */
340 uint16_t link_duplex;
342 struct em_int_delay_info tx_int_delay;
343 struct em_int_delay_info tx_abs_int_delay;
344 struct em_int_delay_info rx_int_delay;
345 struct em_int_delay_info rx_abs_int_delay;
347 XSUM_CONTEXT_T active_checksum_context;
350 * Transmit definitions
352 * We have an array of num_tx_desc descriptors (handled
353 * by the controller) paired with an array of tx_buffers
354 * (at tx_buffer_area).
355 * The index of the next available descriptor is next_avail_tx_desc.
356 * The number of remaining tx_desc is num_tx_desc_avail.
358 struct em_dma_alloc txdma; /* bus_dma glue for tx desc */
359 struct em_tx_desc *tx_desc_base;
360 uint32_t next_avail_tx_desc;
361 uint32_t next_tx_to_clean;
362 volatile uint16_t num_tx_desc_avail;
363 uint16_t num_tx_desc;
365 struct em_buffer *tx_buffer_area;
366 bus_dma_tag_t txtag; /* dma tag for tx */
369 * Receive definitions
371 * we have an array of num_rx_desc rx_desc (handled by the
372 * controller), and paired with an array of rx_buffers
373 * (at rx_buffer_area).
374 * The next pair to check on receive is at offset next_rx_desc_to_check
376 struct em_dma_alloc rxdma; /* bus_dma glue for rx desc */
377 struct em_rx_desc *rx_desc_base;
378 uint32_t next_rx_desc_to_check;
379 uint16_t num_rx_desc;
380 uint32_t rx_buffer_len;
381 struct em_buffer *rx_buffer_area;
385 * First/last mbuf pointers, for
386 * collecting multisegment RX packets.
391 struct sysctl_ctx_list sysctl_ctx;
392 struct sysctl_oid *sysctl_tree;
394 /* Misc stats maintained by the driver */
395 unsigned long dropped_pkts;
396 unsigned long mbuf_alloc_failed;
397 unsigned long mbuf_cluster_failed;
398 unsigned long no_tx_desc_avail1;
399 unsigned long no_tx_desc_avail2;
400 unsigned long no_tx_map_avail;
401 unsigned long no_tx_dma_setup;
402 unsigned long rx_overruns;
403 unsigned long watchdog_timeouts;
405 /* Used in for 82547 10Mb Half workaround */
406 uint32_t tx_fifo_size;
407 uint32_t tx_fifo_head;
408 uint32_t tx_fifo_head_addr;
409 uint64_t tx_fifo_reset_cnt;
410 uint64_t tx_fifo_wrk_cnt;
411 uint32_t tx_head_addr;
413 #define EM_PBA_BYTES_SHIFT 0xA
414 #define EM_TX_HEAD_ADDR_SHIFT 7
415 #define EM_PBA_TX_MASK 0xFFFF0000
416 #define EM_FIFO_HDR 0x10
418 #define EM_82547_PKT_THRESH 0x3e0
420 /* For 82544 PCIX Workaround */
421 boolean_t pcix_82544;
424 struct em_hw_stats stats;
427 #endif /* !_EM_H_DEFINED_ */