2 * Copyright (c) 1996, by Steve Passe
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. The name of the developer may NOT be used to endorse or promote products
11 * derived from this software without specific prior written permission.
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * $FreeBSD: src/sys/i386/i386/mp_machdep.c,v 1.115.2.15 2003/03/14 21:22:35 jhb Exp $
26 * $DragonFly: src/sys/platform/pc32/i386/mp_machdep.c,v 1.55 2006/12/28 21:24:02 dillon Exp $
31 #include <sys/param.h>
32 #include <sys/systm.h>
33 #include <sys/kernel.h>
34 #include <sys/sysctl.h>
35 #include <sys/malloc.h>
36 #include <sys/memrange.h>
37 #include <sys/cons.h> /* cngetc() */
38 #include <sys/machintr.h>
41 #include <vm/vm_param.h>
43 #include <vm/vm_kern.h>
44 #include <vm/vm_extern.h>
46 #include <vm/vm_map.h>
52 #include <machine/smp.h>
53 #include <machine_base/apic/apicreg.h>
54 #include <machine/atomic.h>
55 #include <machine/cpufunc.h>
56 #include <machine_base/apic/mpapic.h>
57 #include <machine/psl.h>
58 #include <machine/segments.h>
59 #include <machine/tss.h>
60 #include <machine/specialreg.h>
61 #include <machine/globaldata.h>
63 #include <machine/md_var.h> /* setidt() */
64 #include <machine_base/icu/icu.h> /* IPIs */
65 #include <machine_base/isa/intr_machdep.h> /* IPIs */
67 #define FIXUP_EXTRA_APIC_INTS 8 /* additional entries we may create */
69 #define WARMBOOT_TARGET 0
70 #define WARMBOOT_OFF (KERNBASE + 0x0467)
71 #define WARMBOOT_SEG (KERNBASE + 0x0469)
73 #define BIOS_BASE (0xf0000)
74 #define BIOS_SIZE (0x10000)
75 #define BIOS_COUNT (BIOS_SIZE/4)
77 #define CMOS_REG (0x70)
78 #define CMOS_DATA (0x71)
79 #define BIOS_RESET (0x0f)
80 #define BIOS_WARM (0x0a)
82 #define PROCENTRY_FLAG_EN 0x01
83 #define PROCENTRY_FLAG_BP 0x02
84 #define IOAPICENTRY_FLAG_EN 0x01
87 /* MP Floating Pointer Structure */
88 typedef struct MPFPS {
101 /* MP Configuration Table Header */
102 typedef struct MPCTH {
104 u_short base_table_length;
108 u_char product_id[12];
109 void *oem_table_pointer;
110 u_short oem_table_size;
113 u_short extended_table_length;
114 u_char extended_table_checksum;
119 typedef struct PROCENTRY {
124 u_long cpu_signature;
125 u_long feature_flags;
130 typedef struct BUSENTRY {
136 typedef struct IOAPICENTRY {
142 } *io_apic_entry_ptr;
144 typedef struct INTENTRY {
154 /* descriptions of MP basetable entries */
155 typedef struct BASETABLE_ENTRY {
162 * this code MUST be enabled here and in mpboot.s.
163 * it follows the very early stages of AP boot by placing values in CMOS ram.
164 * it NORMALLY will never be needed and thus the primitive method for enabling.
167 #if defined(CHECK_POINTS)
168 #define CHECK_READ(A) (outb(CMOS_REG, (A)), inb(CMOS_DATA))
169 #define CHECK_WRITE(A,D) (outb(CMOS_REG, (A)), outb(CMOS_DATA, (D)))
171 #define CHECK_INIT(D); \
172 CHECK_WRITE(0x34, (D)); \
173 CHECK_WRITE(0x35, (D)); \
174 CHECK_WRITE(0x36, (D)); \
175 CHECK_WRITE(0x37, (D)); \
176 CHECK_WRITE(0x38, (D)); \
177 CHECK_WRITE(0x39, (D));
179 #define CHECK_PRINT(S); \
180 kprintf("%s: %d, %d, %d, %d, %d, %d\n", \
189 #else /* CHECK_POINTS */
191 #define CHECK_INIT(D)
192 #define CHECK_PRINT(S)
194 #endif /* CHECK_POINTS */
197 * Values to send to the POST hardware.
199 #define MP_BOOTADDRESS_POST 0x10
200 #define MP_PROBE_POST 0x11
201 #define MPTABLE_PASS1_POST 0x12
203 #define MP_START_POST 0x13
204 #define MP_ENABLE_POST 0x14
205 #define MPTABLE_PASS2_POST 0x15
207 #define START_ALL_APS_POST 0x16
208 #define INSTALL_AP_TRAMP_POST 0x17
209 #define START_AP_POST 0x18
211 #define MP_ANNOUNCE_POST 0x19
213 static int need_hyperthreading_fixup;
214 static u_int logical_cpus;
215 u_int logical_cpus_mask;
217 /** XXX FIXME: where does this really belong, isa.h/isa.c perhaps? */
218 int current_postcode;
220 /** XXX FIXME: what system files declare these??? */
221 extern struct region_descriptor r_gdt, r_idt;
223 int bsp_apic_ready = 0; /* flags useability of BSP apic */
224 int mp_naps; /* # of Applications processors */
225 int mp_nbusses; /* # of busses */
227 int mp_napics; /* # of IO APICs */
229 int boot_cpu_id; /* designated BSP */
230 vm_offset_t cpu_apic_address;
232 vm_offset_t io_apic_address[NAPICID]; /* NAPICID is more than enough */
233 u_int32_t *io_apic_versions;
237 u_int32_t cpu_apic_versions[MAXCPU];
239 extern int64_t tsc_offsets[];
242 struct apic_intmapinfo int_to_apicintpin[APIC_INTMAPSIZE];
246 * APIC ID logical/physical mapping structures.
247 * We oversize these to simplify boot-time config.
249 int cpu_num_to_apic_id[NAPICID];
251 int io_num_to_apic_id[NAPICID];
253 int apic_id_to_logical[NAPICID];
255 /* AP uses this during bootstrap. Do not staticize. */
259 /* Hotwire a 0->4MB V==P mapping */
260 extern pt_entry_t *KPTphys;
263 * SMP page table page. Setup by locore to point to a page table
264 * page from which we allocate per-cpu privatespace areas io_apics,
268 #define IO_MAPPING_START_INDEX \
269 (SMP_MAXCPU * sizeof(struct privatespace) / PAGE_SIZE)
271 extern pt_entry_t *SMPpt;
272 static int SMPpt_alloc_index = IO_MAPPING_START_INDEX;
274 struct pcb stoppcbs[MAXCPU];
277 * Local data and functions.
280 static int mp_capable;
281 static u_int boot_address;
282 static u_int base_memory;
283 static int mp_finish;
285 static mpfps_t mpfps;
286 static int search_for_sig(u_int32_t target, int count);
287 static void mp_enable(u_int boot_addr);
289 static void mptable_hyperthread_fixup(u_int id_mask);
290 static void mptable_pass1(void);
291 static int mptable_pass2(void);
292 static void default_mp_table(int type);
293 static void fix_mp_table(void);
295 static void setup_apic_irq_mapping(void);
296 static int apic_int_is_bus_type(int intr, int bus_type);
298 static int start_all_aps(u_int boot_addr);
299 static void install_ap_tramp(u_int boot_addr);
300 static int start_ap(struct mdglobaldata *gd, u_int boot_addr);
302 static cpumask_t smp_startup_mask = 1; /* which cpus have been started */
303 cpumask_t smp_active_mask = 1; /* which cpus are ready for IPIs etc? */
304 SYSCTL_INT(_machdep, OID_AUTO, smp_active, CTLFLAG_RD, &smp_active_mask, 0, "");
307 * Calculate usable address in base memory for AP trampoline code.
310 mp_bootaddress(u_int basemem)
312 POSTCODE(MP_BOOTADDRESS_POST);
314 base_memory = basemem * 1024; /* convert to bytes */
316 boot_address = base_memory & ~0xfff; /* round down to 4k boundary */
317 if ((base_memory - boot_address) < bootMP_size)
318 boot_address -= 4096; /* not enough, lower by 4k */
325 * Look for an Intel MP spec table (ie, SMP capable hardware).
335 * Make sure our SMPpt[] page table is big enough to hold all the
338 KKASSERT(IO_MAPPING_START_INDEX < NPTEPG - 2);
340 POSTCODE(MP_PROBE_POST);
342 /* see if EBDA exists */
343 if ((segment = (u_long) * (u_short *) (KERNBASE + 0x40e)) != 0) {
344 /* search first 1K of EBDA */
345 target = (u_int32_t) (segment << 4);
346 if ((x = search_for_sig(target, 1024 / 4)) >= 0)
349 /* last 1K of base memory, effective 'top of base' passed in */
350 target = (u_int32_t) (base_memory - 0x400);
351 if ((x = search_for_sig(target, 1024 / 4)) >= 0)
355 /* search the BIOS */
356 target = (u_int32_t) BIOS_BASE;
357 if ((x = search_for_sig(target, BIOS_COUNT)) >= 0)
367 * Calculate needed resources. We can safely map physical
368 * memory into SMPpt after mptable_pass1() completes.
373 /* flag fact that we are running multiple processors */
380 * Startup the SMP processors.
385 POSTCODE(MP_START_POST);
387 /* look for MP capable motherboard */
389 mp_enable(boot_address);
391 panic("MP hardware not found!");
396 * Print various information about the SMP system hardware and setup.
403 POSTCODE(MP_ANNOUNCE_POST);
405 kprintf("DragonFly/MP: Multiprocessor motherboard\n");
406 kprintf(" cpu0 (BSP): apic id: %2d", CPU_TO_ID(0));
407 kprintf(", version: 0x%08x", cpu_apic_versions[0]);
408 kprintf(", at 0x%08x\n", cpu_apic_address);
409 for (x = 1; x <= mp_naps; ++x) {
410 kprintf(" cpu%d (AP): apic id: %2d", x, CPU_TO_ID(x));
411 kprintf(", version: 0x%08x", cpu_apic_versions[x]);
412 kprintf(", at 0x%08x\n", cpu_apic_address);
416 for (x = 0; x < mp_napics; ++x) {
417 kprintf(" io%d (APIC): apic id: %2d", x, IO_TO_ID(x));
418 kprintf(", version: 0x%08x", io_apic_versions[x]);
419 kprintf(", at 0x%08x\n", io_apic_address[x]);
422 kprintf(" Warning: APIC I/O disabled\n");
427 * AP cpu's call this to sync up protected mode.
429 * WARNING! We must ensure that the cpu is sufficiently initialized to
430 * be able to use to the FP for our optimized bzero/bcopy code before
431 * we enter more mainstream C code.
433 * WARNING! %fs is not set up on entry. This routine sets up %fs.
439 int x, myid = bootAP;
441 struct mdglobaldata *md;
442 struct privatespace *ps;
444 ps = &CPU_prvspace[myid];
446 gdt_segs[GPRIV_SEL].ssd_base = (int)ps;
447 gdt_segs[GPROC0_SEL].ssd_base =
448 (int) &ps->mdglobaldata.gd_common_tss;
449 ps->mdglobaldata.mi.gd_prvspace = ps;
451 for (x = 0; x < NGDT; x++) {
452 ssdtosd(&gdt_segs[x], &gdt[myid * NGDT + x].sd);
455 r_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1;
456 r_gdt.rd_base = (int) &gdt[myid * NGDT];
457 lgdt(&r_gdt); /* does magic intra-segment return */
462 mdcpu->gd_currentldt = _default_ldt;
464 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL);
465 gdt[myid * NGDT + GPROC0_SEL].sd.sd_type = SDT_SYS386TSS;
467 md = mdcpu; /* loaded through %fs:0 (mdglobaldata.mi.gd_prvspace)*/
469 md->gd_common_tss.tss_esp0 = 0; /* not used until after switch */
470 md->gd_common_tss.tss_ss0 = GSEL(GDATA_SEL, SEL_KPL);
471 md->gd_common_tss.tss_ioopt = (sizeof md->gd_common_tss) << 16;
472 md->gd_tss_gdt = &gdt[myid * NGDT + GPROC0_SEL].sd;
473 md->gd_common_tssd = *md->gd_tss_gdt;
477 * Set to a known state:
478 * Set by mpboot.s: CR0_PG, CR0_PE
479 * Set by cpu_setregs: CR0_NE, CR0_MP, CR0_TS, CR0_WP, CR0_AM
482 cr0 &= ~(CR0_CD | CR0_NW | CR0_EM);
484 pmap_set_opt(); /* PSE/4MB pages, etc */
486 /* set up CPU registers and state */
489 /* set up FPU state on the AP */
490 npxinit(__INITIAL_NPXCW__);
492 /* set up SSE registers */
496 /*******************************************************************
497 * local functions and data
501 * start the SMP system
504 mp_enable(u_int boot_addr)
512 POSTCODE(MP_ENABLE_POST);
514 /* turn on 4MB of V == P addressing so we can get to MP table */
515 *(int *)PTD = PG_V | PG_RW | ((uintptr_t)(void *)KPTphys & PG_FRAME);
518 /* examine the MP table for needed info, uses physical addresses */
524 /* can't process default configs till the CPU APIC is pmapped */
528 /* post scan cleanup */
533 setup_apic_irq_mapping();
535 /* fill the LOGICAL io_apic_versions table */
536 for (apic = 0; apic < mp_napics; ++apic) {
537 ux = io_apic_read(apic, IOAPIC_VER);
538 io_apic_versions[apic] = ux;
539 io_apic_set_id(apic, IO_TO_ID(apic));
542 /* program each IO APIC in the system */
543 for (apic = 0; apic < mp_napics; ++apic)
544 if (io_apic_setup(apic) < 0)
545 panic("IO APIC setup failure");
550 * These are required for SMP operation
553 /* install a 'Spurious INTerrupt' vector */
554 setidt(XSPURIOUSINT_OFFSET, Xspuriousint,
555 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
557 /* install an inter-CPU IPI for TLB invalidation */
558 setidt(XINVLTLB_OFFSET, Xinvltlb,
559 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
561 /* install an inter-CPU IPI for IPIQ messaging */
562 setidt(XIPIQ_OFFSET, Xipiq,
563 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
565 /* install an inter-CPU IPI for CPU stop/restart */
566 setidt(XCPUSTOP_OFFSET, Xcpustop,
567 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
569 /* start each Application Processor */
570 start_all_aps(boot_addr);
575 * look for the MP spec signature
578 /* string defined by the Intel MP Spec as identifying the MP table */
579 #define MP_SIG 0x5f504d5f /* _MP_ */
580 #define NEXT(X) ((X) += 4)
582 search_for_sig(u_int32_t target, int count)
585 u_int32_t *addr = (u_int32_t *) (KERNBASE + target);
587 for (x = 0; x < count; NEXT(x))
588 if (addr[x] == MP_SIG)
589 /* make array index a byte index */
590 return (target + (x * sizeof(u_int32_t)));
596 static basetable_entry basetable_entry_types[] =
598 {0, 20, "Processor"},
605 typedef struct BUSDATA {
607 enum busTypes bus_type;
610 typedef struct INTDATA {
620 typedef struct BUSTYPENAME {
625 static bus_type_name bus_type_table[] =
631 {UNKNOWN_BUSTYPE, "---"},
634 {UNKNOWN_BUSTYPE, "---"},
635 {UNKNOWN_BUSTYPE, "---"},
636 {UNKNOWN_BUSTYPE, "---"},
637 {UNKNOWN_BUSTYPE, "---"},
638 {UNKNOWN_BUSTYPE, "---"},
640 {UNKNOWN_BUSTYPE, "---"},
641 {UNKNOWN_BUSTYPE, "---"},
642 {UNKNOWN_BUSTYPE, "---"},
643 {UNKNOWN_BUSTYPE, "---"},
645 {UNKNOWN_BUSTYPE, "---"}
647 /* from MP spec v1.4, table 5-1 */
648 static int default_data[7][5] =
650 /* nbus, id0, type0, id1, type1 */
651 {1, 0, ISA, 255, 255},
652 {1, 0, EISA, 255, 255},
653 {1, 0, EISA, 255, 255},
654 {1, 0, MCA, 255, 255},
656 {2, 0, EISA, 1, PCI},
662 static bus_datum *bus_data;
665 /* the IO INT data, one entry per possible APIC INTerrupt */
666 static io_int *io_apic_ints;
670 static int processor_entry (proc_entry_ptr entry, int cpu);
671 static int bus_entry (bus_entry_ptr entry, int bus);
673 static int io_apic_entry (io_apic_entry_ptr entry, int apic);
674 static int int_entry (int_entry_ptr entry, int intr);
676 static int lookup_bus_type (char *name);
680 * 1st pass on motherboard's Intel MP specification table.
686 * cpu_apic_address (common to all CPUs)
706 POSTCODE(MPTABLE_PASS1_POST);
709 /* clear various tables */
710 for (x = 0; x < NAPICID; ++x) {
711 io_apic_address[x] = ~0; /* IO APIC address table */
715 /* init everything to empty */
724 /* check for use of 'default' configuration */
725 if (mpfps->mpfb1 != 0) {
726 /* use default addresses */
727 cpu_apic_address = DEFAULT_APIC_BASE;
729 io_apic_address[0] = DEFAULT_IO_APIC_BASE;
732 /* fill in with defaults */
733 mp_naps = 2; /* includes BSP */
734 mp_nbusses = default_data[mpfps->mpfb1 - 1][0];
741 if ((cth = mpfps->pap) == 0)
742 panic("MP Configuration Table Header MISSING!");
744 cpu_apic_address = (vm_offset_t) cth->apic_address;
746 /* walk the table, recording info of interest */
747 totalSize = cth->base_table_length - sizeof(struct MPCTH);
748 position = (u_char *) cth + sizeof(struct MPCTH);
749 count = cth->entry_count;
752 switch (type = *(u_char *) position) {
753 case 0: /* processor_entry */
754 if (((proc_entry_ptr)position)->cpu_flags
755 & PROCENTRY_FLAG_EN) {
758 ((proc_entry_ptr)position)->apic_id;
761 case 1: /* bus_entry */
764 case 2: /* io_apic_entry */
766 if (((io_apic_entry_ptr)position)->apic_flags
767 & IOAPICENTRY_FLAG_EN)
768 io_apic_address[mp_napics++] =
769 (vm_offset_t)((io_apic_entry_ptr)
770 position)->apic_address;
773 case 3: /* int_entry */
778 case 4: /* int_entry */
781 panic("mpfps Base Table HOSED!");
785 totalSize -= basetable_entry_types[type].length;
786 position = (uint8_t *)position +
787 basetable_entry_types[type].length;
791 /* qualify the numbers */
792 if (mp_naps > MAXCPU) {
793 kprintf("Warning: only using %d of %d available CPUs!\n",
798 /* See if we need to fixup HT logical CPUs. */
799 mptable_hyperthread_fixup(id_mask);
803 * This is also used as a counter while starting the APs.
807 --mp_naps; /* subtract the BSP */
812 * 2nd pass on motherboard's Intel MP specification table.
816 * ID_TO_IO(N), phy APIC ID to log CPU/IO table
817 * CPU_TO_ID(N), logical CPU to APIC ID table
818 * IO_TO_ID(N), logical IO to APIC ID table
825 struct PROCENTRY proc;
832 int apic, bus, cpu, intr;
835 POSTCODE(MPTABLE_PASS2_POST);
837 /* Initialize fake proc entry for use with HT fixup. */
838 bzero(&proc, sizeof(proc));
840 proc.cpu_flags = PROCENTRY_FLAG_EN;
843 MALLOC(io_apic_versions, u_int32_t *, sizeof(u_int32_t) * mp_napics,
845 MALLOC(ioapic, volatile ioapic_t **, sizeof(ioapic_t *) * mp_napics,
847 MALLOC(io_apic_ints, io_int *, sizeof(io_int) * (nintrs + FIXUP_EXTRA_APIC_INTS),
850 MALLOC(bus_data, bus_datum *, sizeof(bus_datum) * mp_nbusses,
854 bzero(ioapic, sizeof(ioapic_t *) * mp_napics);
856 for (i = 0; i < mp_napics; i++) {
857 ioapic[i] = permanent_io_mapping(io_apic_address[i]);
861 /* clear various tables */
862 for (x = 0; x < NAPICID; ++x) {
863 CPU_TO_ID(x) = -1; /* logical CPU to APIC ID table */
865 ID_TO_IO(x) = -1; /* phy APIC ID to log CPU/IO table */
866 IO_TO_ID(x) = -1; /* logical IO to APIC ID table */
870 /* clear bus data table */
871 for (x = 0; x < mp_nbusses; ++x)
872 bus_data[x].bus_id = 0xff;
875 /* clear IO APIC INT table */
876 for (x = 0; x < (nintrs + 1); ++x) {
877 io_apic_ints[x].int_type = 0xff;
878 io_apic_ints[x].int_vector = 0xff;
882 /* setup the cpu/apic mapping arrays */
885 /* record whether PIC or virtual-wire mode */
886 machintr_setvar_simple(MACHINTR_VAR_IMCR_PRESENT, mpfps->mpfb2 & 0x80);
888 /* check for use of 'default' configuration */
889 if (mpfps->mpfb1 != 0)
890 return mpfps->mpfb1; /* return default configuration type */
892 if ((cth = mpfps->pap) == 0)
893 panic("MP Configuration Table Header MISSING!");
895 /* walk the table, recording info of interest */
896 totalSize = cth->base_table_length - sizeof(struct MPCTH);
897 position = (u_char *) cth + sizeof(struct MPCTH);
898 count = cth->entry_count;
899 apic = bus = intr = 0;
900 cpu = 1; /* pre-count the BSP */
903 switch (type = *(u_char *) position) {
905 if (processor_entry(position, cpu))
908 if (need_hyperthreading_fixup) {
910 * Create fake mptable processor entries
911 * and feed them to processor_entry() to
912 * enumerate the logical CPUs.
914 proc.apic_id = ((proc_entry_ptr)position)->apic_id;
915 for (i = 1; i < logical_cpus; i++) {
917 processor_entry(&proc, cpu);
918 logical_cpus_mask |= (1 << cpu);
924 if (bus_entry(position, bus))
929 if (io_apic_entry(position, apic))
935 if (int_entry(position, intr))
940 /* int_entry(position); */
943 panic("mpfps Base Table HOSED!");
947 totalSize -= basetable_entry_types[type].length;
948 position = (uint8_t *)position + basetable_entry_types[type].length;
951 if (boot_cpu_id == -1)
952 panic("NO BSP found!");
954 /* report fact that its NOT a default configuration */
959 * Check if we should perform a hyperthreading "fix-up" to
960 * enumerate any logical CPU's that aren't already listed
963 * XXX: We assume that all of the physical CPUs in the
964 * system have the same number of logical CPUs.
966 * XXX: We assume that APIC ID's are allocated such that
967 * the APIC ID's for a physical processor are aligned
968 * with the number of logical CPU's in the processor.
971 mptable_hyperthread_fixup(u_int id_mask)
975 /* Nothing to do if there is no HTT support. */
976 if ((cpu_feature & CPUID_HTT) == 0)
978 logical_cpus = (cpu_procinfo & CPUID_HTT_CORES) >> 16;
979 if (logical_cpus <= 1)
983 * For each APIC ID of a CPU that is set in the mask,
984 * scan the other candidate APIC ID's for this
985 * physical processor. If any of those ID's are
986 * already in the table, then kill the fixup.
988 for (id = 0; id <= MAXCPU; id++) {
989 if ((id_mask & 1 << id) == 0)
991 /* First, make sure we are on a logical_cpus boundary. */
992 if (id % logical_cpus != 0)
994 for (i = id + 1; i < id + logical_cpus; i++)
995 if ((id_mask & 1 << i) != 0)
1000 * Ok, the ID's checked out, so enable the fixup. We have to fixup
1001 * mp_naps right now.
1003 need_hyperthreading_fixup = 1;
1004 mp_naps *= logical_cpus;
1010 assign_apic_irq(int apic, int intpin, int irq)
1014 if (int_to_apicintpin[irq].ioapic != -1)
1015 panic("assign_apic_irq: inconsistent table");
1017 int_to_apicintpin[irq].ioapic = apic;
1018 int_to_apicintpin[irq].int_pin = intpin;
1019 int_to_apicintpin[irq].apic_address = ioapic[apic];
1020 int_to_apicintpin[irq].redirindex = IOAPIC_REDTBL + 2 * intpin;
1022 for (x = 0; x < nintrs; x++) {
1023 if ((io_apic_ints[x].int_type == 0 ||
1024 io_apic_ints[x].int_type == 3) &&
1025 io_apic_ints[x].int_vector == 0xff &&
1026 io_apic_ints[x].dst_apic_id == IO_TO_ID(apic) &&
1027 io_apic_ints[x].dst_apic_int == intpin)
1028 io_apic_ints[x].int_vector = irq;
1033 revoke_apic_irq(int irq)
1039 if (int_to_apicintpin[irq].ioapic == -1)
1040 panic("revoke_apic_irq: inconsistent table");
1042 oldapic = int_to_apicintpin[irq].ioapic;
1043 oldintpin = int_to_apicintpin[irq].int_pin;
1045 int_to_apicintpin[irq].ioapic = -1;
1046 int_to_apicintpin[irq].int_pin = 0;
1047 int_to_apicintpin[irq].apic_address = NULL;
1048 int_to_apicintpin[irq].redirindex = 0;
1050 for (x = 0; x < nintrs; x++) {
1051 if ((io_apic_ints[x].int_type == 0 ||
1052 io_apic_ints[x].int_type == 3) &&
1053 io_apic_ints[x].int_vector != 0xff &&
1054 io_apic_ints[x].dst_apic_id == IO_TO_ID(oldapic) &&
1055 io_apic_ints[x].dst_apic_int == oldintpin)
1056 io_apic_ints[x].int_vector = 0xff;
1064 allocate_apic_irq(int intr)
1070 if (io_apic_ints[intr].int_vector != 0xff)
1071 return; /* Interrupt handler already assigned */
1073 if (io_apic_ints[intr].int_type != 0 &&
1074 (io_apic_ints[intr].int_type != 3 ||
1075 (io_apic_ints[intr].dst_apic_id == IO_TO_ID(0) &&
1076 io_apic_ints[intr].dst_apic_int == 0)))
1077 return; /* Not INT or ExtInt on != (0, 0) */
1080 while (irq < APIC_INTMAPSIZE &&
1081 int_to_apicintpin[irq].ioapic != -1)
1084 if (irq >= APIC_INTMAPSIZE)
1085 return; /* No free interrupt handlers */
1087 apic = ID_TO_IO(io_apic_ints[intr].dst_apic_id);
1088 intpin = io_apic_ints[intr].dst_apic_int;
1090 assign_apic_irq(apic, intpin, irq);
1091 io_apic_setup_intpin(apic, intpin);
1096 swap_apic_id(int apic, int oldid, int newid)
1103 return; /* Nothing to do */
1105 kprintf("Changing APIC ID for IO APIC #%d from %d to %d in MP table\n",
1106 apic, oldid, newid);
1108 /* Swap physical APIC IDs in interrupt entries */
1109 for (x = 0; x < nintrs; x++) {
1110 if (io_apic_ints[x].dst_apic_id == oldid)
1111 io_apic_ints[x].dst_apic_id = newid;
1112 else if (io_apic_ints[x].dst_apic_id == newid)
1113 io_apic_ints[x].dst_apic_id = oldid;
1116 /* Swap physical APIC IDs in IO_TO_ID mappings */
1117 for (oapic = 0; oapic < mp_napics; oapic++)
1118 if (IO_TO_ID(oapic) == newid)
1121 if (oapic < mp_napics) {
1122 kprintf("Changing APIC ID for IO APIC #%d from "
1123 "%d to %d in MP table\n",
1124 oapic, newid, oldid);
1125 IO_TO_ID(oapic) = oldid;
1127 IO_TO_ID(apic) = newid;
1132 fix_id_to_io_mapping(void)
1136 for (x = 0; x < NAPICID; x++)
1139 for (x = 0; x <= mp_naps; x++)
1140 if (CPU_TO_ID(x) < NAPICID)
1141 ID_TO_IO(CPU_TO_ID(x)) = x;
1143 for (x = 0; x < mp_napics; x++)
1144 if (IO_TO_ID(x) < NAPICID)
1145 ID_TO_IO(IO_TO_ID(x)) = x;
1150 first_free_apic_id(void)
1154 for (freeid = 0; freeid < NAPICID; freeid++) {
1155 for (x = 0; x <= mp_naps; x++)
1156 if (CPU_TO_ID(x) == freeid)
1160 for (x = 0; x < mp_napics; x++)
1161 if (IO_TO_ID(x) == freeid)
1172 io_apic_id_acceptable(int apic, int id)
1174 int cpu; /* Logical CPU number */
1175 int oapic; /* Logical IO APIC number for other IO APIC */
1178 return 0; /* Out of range */
1180 for (cpu = 0; cpu <= mp_naps; cpu++)
1181 if (CPU_TO_ID(cpu) == id)
1182 return 0; /* Conflict with CPU */
1184 for (oapic = 0; oapic < mp_napics && oapic < apic; oapic++)
1185 if (IO_TO_ID(oapic) == id)
1186 return 0; /* Conflict with other APIC */
1188 return 1; /* ID is acceptable for IO APIC */
1193 io_apic_find_int_entry(int apic, int pin)
1197 /* search each of the possible INTerrupt sources */
1198 for (x = 0; x < nintrs; ++x) {
1199 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1200 (pin == io_apic_ints[x].dst_apic_int))
1201 return (&io_apic_ints[x]);
1209 * parse an Intel MP specification table
1217 int apic; /* IO APIC unit number */
1218 int freeid; /* Free physical APIC ID */
1219 int physid; /* Current physical IO APIC ID */
1222 int bus_0 = 0; /* Stop GCC warning */
1223 int bus_pci = 0; /* Stop GCC warning */
1227 * Fix mis-numbering of the PCI bus and its INT entries if the BIOS
1228 * did it wrong. The MP spec says that when more than 1 PCI bus
1229 * exists the BIOS must begin with bus entries for the PCI bus and use
1230 * actual PCI bus numbering. This implies that when only 1 PCI bus
1231 * exists the BIOS can choose to ignore this ordering, and indeed many
1232 * MP motherboards do ignore it. This causes a problem when the PCI
1233 * sub-system makes requests of the MP sub-system based on PCI bus
1234 * numbers. So here we look for the situation and renumber the
1235 * busses and associated INTs in an effort to "make it right".
1238 /* find bus 0, PCI bus, count the number of PCI busses */
1239 for (num_pci_bus = 0, x = 0; x < mp_nbusses; ++x) {
1240 if (bus_data[x].bus_id == 0) {
1243 if (bus_data[x].bus_type == PCI) {
1249 * bus_0 == slot of bus with ID of 0
1250 * bus_pci == slot of last PCI bus encountered
1253 /* check the 1 PCI bus case for sanity */
1254 /* if it is number 0 all is well */
1255 if (num_pci_bus == 1 &&
1256 bus_data[bus_pci].bus_id != 0) {
1258 /* mis-numbered, swap with whichever bus uses slot 0 */
1260 /* swap the bus entry types */
1261 bus_data[bus_pci].bus_type = bus_data[bus_0].bus_type;
1262 bus_data[bus_0].bus_type = PCI;
1265 /* swap each relavant INTerrupt entry */
1266 id = bus_data[bus_pci].bus_id;
1267 for (x = 0; x < nintrs; ++x) {
1268 if (io_apic_ints[x].src_bus_id == id) {
1269 io_apic_ints[x].src_bus_id = 0;
1271 else if (io_apic_ints[x].src_bus_id == 0) {
1272 io_apic_ints[x].src_bus_id = id;
1279 /* Assign IO APIC IDs.
1281 * First try the existing ID. If a conflict is detected, try
1282 * the ID in the MP table. If a conflict is still detected, find
1285 * We cannot use the ID_TO_IO table before all conflicts has been
1286 * resolved and the table has been corrected.
1288 for (apic = 0; apic < mp_napics; ++apic) { /* For all IO APICs */
1290 /* First try to use the value set by the BIOS */
1291 physid = io_apic_get_id(apic);
1292 if (io_apic_id_acceptable(apic, physid)) {
1293 if (IO_TO_ID(apic) != physid)
1294 swap_apic_id(apic, IO_TO_ID(apic), physid);
1298 /* Then check if the value in the MP table is acceptable */
1299 if (io_apic_id_acceptable(apic, IO_TO_ID(apic)))
1302 /* Last resort, find a free APIC ID and use it */
1303 freeid = first_free_apic_id();
1304 if (freeid >= NAPICID)
1305 panic("No free physical APIC IDs found");
1307 if (io_apic_id_acceptable(apic, freeid)) {
1308 swap_apic_id(apic, IO_TO_ID(apic), freeid);
1311 panic("Free physical APIC ID not usable");
1313 fix_id_to_io_mapping();
1317 /* detect and fix broken Compaq MP table */
1318 if (apic_int_type(0, 0) == -1) {
1319 kprintf("APIC_IO: MP table broken: 8259->APIC entry missing!\n");
1320 io_apic_ints[nintrs].int_type = 3; /* ExtInt */
1321 io_apic_ints[nintrs].int_vector = 0xff; /* Unassigned */
1322 /* XXX fixme, set src bus id etc, but it doesn't seem to hurt */
1323 io_apic_ints[nintrs].dst_apic_id = IO_TO_ID(0);
1324 io_apic_ints[nintrs].dst_apic_int = 0; /* Pin 0 */
1326 } else if (apic_int_type(0, 0) == 0) {
1327 kprintf("APIC_IO: MP table broken: ExtINT entry corrupt!\n");
1328 for (x = 0; x < nintrs; ++x)
1329 if ((0 == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1330 (0 == io_apic_ints[x].dst_apic_int)) {
1331 io_apic_ints[x].int_type = 3;
1332 io_apic_ints[x].int_vector = 0xff;
1338 * Fix missing IRQ 15 when IRQ 14 is an ISA interrupt. IDE
1339 * controllers universally come in pairs. If IRQ 14 is specified
1340 * as an ISA interrupt, then IRQ 15 had better be too.
1342 * [ Shuttle XPC / AMD Athlon X2 ]
1343 * The MPTable is missing an entry for IRQ 15. Note that the
1344 * ACPI table has an entry for both 14 and 15.
1346 if (apic_int_type(0, 14) == 0 && apic_int_type(0, 15) == -1) {
1347 kprintf("APIC_IO: MP table broken: IRQ 15 not ISA when IRQ 14 is!\n");
1348 io14 = io_apic_find_int_entry(0, 14);
1349 io_apic_ints[nintrs] = *io14;
1350 io_apic_ints[nintrs].src_bus_irq = 15;
1351 io_apic_ints[nintrs].dst_apic_int = 15;
1359 /* Assign low level interrupt handlers */
1361 setup_apic_irq_mapping(void)
1367 for (x = 0; x < APIC_INTMAPSIZE; x++) {
1368 int_to_apicintpin[x].ioapic = -1;
1369 int_to_apicintpin[x].int_pin = 0;
1370 int_to_apicintpin[x].apic_address = NULL;
1371 int_to_apicintpin[x].redirindex = 0;
1374 /* First assign ISA/EISA interrupts */
1375 for (x = 0; x < nintrs; x++) {
1376 int_vector = io_apic_ints[x].src_bus_irq;
1377 if (int_vector < APIC_INTMAPSIZE &&
1378 io_apic_ints[x].int_vector == 0xff &&
1379 int_to_apicintpin[int_vector].ioapic == -1 &&
1380 (apic_int_is_bus_type(x, ISA) ||
1381 apic_int_is_bus_type(x, EISA)) &&
1382 io_apic_ints[x].int_type == 0) {
1383 assign_apic_irq(ID_TO_IO(io_apic_ints[x].dst_apic_id),
1384 io_apic_ints[x].dst_apic_int,
1389 /* Assign ExtInt entry if no ISA/EISA interrupt 0 entry */
1390 for (x = 0; x < nintrs; x++) {
1391 if (io_apic_ints[x].dst_apic_int == 0 &&
1392 io_apic_ints[x].dst_apic_id == IO_TO_ID(0) &&
1393 io_apic_ints[x].int_vector == 0xff &&
1394 int_to_apicintpin[0].ioapic == -1 &&
1395 io_apic_ints[x].int_type == 3) {
1396 assign_apic_irq(0, 0, 0);
1400 /* PCI interrupt assignment is deferred */
1406 processor_entry(proc_entry_ptr entry, int cpu)
1408 /* check for usability */
1409 if (!(entry->cpu_flags & PROCENTRY_FLAG_EN))
1412 if(entry->apic_id >= NAPICID)
1413 panic("CPU APIC ID out of range (0..%d)", NAPICID - 1);
1414 /* check for BSP flag */
1415 if (entry->cpu_flags & PROCENTRY_FLAG_BP) {
1416 boot_cpu_id = entry->apic_id;
1417 CPU_TO_ID(0) = entry->apic_id;
1418 ID_TO_CPU(entry->apic_id) = 0;
1419 return 0; /* its already been counted */
1422 /* add another AP to list, if less than max number of CPUs */
1423 else if (cpu < MAXCPU) {
1424 CPU_TO_ID(cpu) = entry->apic_id;
1425 ID_TO_CPU(entry->apic_id) = cpu;
1434 bus_entry(bus_entry_ptr entry, int bus)
1439 /* encode the name into an index */
1440 for (x = 0; x < 6; ++x) {
1441 if ((c = entry->bus_type[x]) == ' ')
1447 if ((x = lookup_bus_type(name)) == UNKNOWN_BUSTYPE)
1448 panic("unknown bus type: '%s'", name);
1450 bus_data[bus].bus_id = entry->bus_id;
1451 bus_data[bus].bus_type = x;
1459 io_apic_entry(io_apic_entry_ptr entry, int apic)
1461 if (!(entry->apic_flags & IOAPICENTRY_FLAG_EN))
1464 IO_TO_ID(apic) = entry->apic_id;
1465 if (entry->apic_id < NAPICID)
1466 ID_TO_IO(entry->apic_id) = apic;
1474 lookup_bus_type(char *name)
1478 for (x = 0; x < MAX_BUSTYPE; ++x)
1479 if (strcmp(bus_type_table[x].name, name) == 0)
1480 return bus_type_table[x].type;
1482 return UNKNOWN_BUSTYPE;
1488 int_entry(int_entry_ptr entry, int intr)
1492 io_apic_ints[intr].int_type = entry->int_type;
1493 io_apic_ints[intr].int_flags = entry->int_flags;
1494 io_apic_ints[intr].src_bus_id = entry->src_bus_id;
1495 io_apic_ints[intr].src_bus_irq = entry->src_bus_irq;
1496 if (entry->dst_apic_id == 255) {
1497 /* This signal goes to all IO APICS. Select an IO APIC
1498 with sufficient number of interrupt pins */
1499 for (apic = 0; apic < mp_napics; apic++)
1500 if (((io_apic_read(apic, IOAPIC_VER) &
1501 IOART_VER_MAXREDIR) >> MAXREDIRSHIFT) >=
1502 entry->dst_apic_int)
1504 if (apic < mp_napics)
1505 io_apic_ints[intr].dst_apic_id = IO_TO_ID(apic);
1507 io_apic_ints[intr].dst_apic_id = entry->dst_apic_id;
1509 io_apic_ints[intr].dst_apic_id = entry->dst_apic_id;
1510 io_apic_ints[intr].dst_apic_int = entry->dst_apic_int;
1516 apic_int_is_bus_type(int intr, int bus_type)
1520 for (bus = 0; bus < mp_nbusses; ++bus)
1521 if ((bus_data[bus].bus_id == io_apic_ints[intr].src_bus_id)
1522 && ((int) bus_data[bus].bus_type == bus_type))
1529 * Given a traditional ISA INT mask, return an APIC mask.
1532 isa_apic_mask(u_int isa_mask)
1537 #if defined(SKIP_IRQ15_REDIRECT)
1538 if (isa_mask == (1 << 15)) {
1539 kprintf("skipping ISA IRQ15 redirect\n");
1542 #endif /* SKIP_IRQ15_REDIRECT */
1544 isa_irq = ffs(isa_mask); /* find its bit position */
1545 if (isa_irq == 0) /* doesn't exist */
1547 --isa_irq; /* make it zero based */
1549 apic_pin = isa_apic_irq(isa_irq); /* look for APIC connection */
1553 return (1 << apic_pin); /* convert pin# to a mask */
1557 * Determine which APIC pin an ISA/EISA INT is attached to.
1559 #define INTTYPE(I) (io_apic_ints[(I)].int_type)
1560 #define INTPIN(I) (io_apic_ints[(I)].dst_apic_int)
1561 #define INTIRQ(I) (io_apic_ints[(I)].int_vector)
1562 #define INTAPIC(I) (ID_TO_IO(io_apic_ints[(I)].dst_apic_id))
1564 #define SRCBUSIRQ(I) (io_apic_ints[(I)].src_bus_irq)
1566 isa_apic_irq(int isa_irq)
1570 for (intr = 0; intr < nintrs; ++intr) { /* check each record */
1571 if (INTTYPE(intr) == 0) { /* standard INT */
1572 if (SRCBUSIRQ(intr) == isa_irq) {
1573 if (apic_int_is_bus_type(intr, ISA) ||
1574 apic_int_is_bus_type(intr, EISA)) {
1575 if (INTIRQ(intr) == 0xff)
1576 return -1; /* unassigned */
1577 return INTIRQ(intr); /* found */
1582 return -1; /* NOT found */
1587 * Determine which APIC pin a PCI INT is attached to.
1589 #define SRCBUSID(I) (io_apic_ints[(I)].src_bus_id)
1590 #define SRCBUSDEVICE(I) ((io_apic_ints[(I)].src_bus_irq >> 2) & 0x1f)
1591 #define SRCBUSLINE(I) (io_apic_ints[(I)].src_bus_irq & 0x03)
1593 pci_apic_irq(int pciBus, int pciDevice, int pciInt)
1597 --pciInt; /* zero based */
1599 for (intr = 0; intr < nintrs; ++intr) { /* check each record */
1600 if ((INTTYPE(intr) == 0) /* standard INT */
1601 && (SRCBUSID(intr) == pciBus)
1602 && (SRCBUSDEVICE(intr) == pciDevice)
1603 && (SRCBUSLINE(intr) == pciInt)) { /* a candidate IRQ */
1604 if (apic_int_is_bus_type(intr, PCI)) {
1605 if (INTIRQ(intr) == 0xff)
1606 allocate_apic_irq(intr);
1607 if (INTIRQ(intr) == 0xff)
1608 return -1; /* unassigned */
1609 return INTIRQ(intr); /* exact match */
1614 return -1; /* NOT found */
1618 next_apic_irq(int irq)
1625 for (intr = 0; intr < nintrs; intr++) {
1626 if (INTIRQ(intr) != irq || INTTYPE(intr) != 0)
1628 bus = SRCBUSID(intr);
1629 bustype = apic_bus_type(bus);
1630 if (bustype != ISA &&
1636 if (intr >= nintrs) {
1639 for (ointr = intr + 1; ointr < nintrs; ointr++) {
1640 if (INTTYPE(ointr) != 0)
1642 if (bus != SRCBUSID(ointr))
1644 if (bustype == PCI) {
1645 if (SRCBUSDEVICE(intr) != SRCBUSDEVICE(ointr))
1647 if (SRCBUSLINE(intr) != SRCBUSLINE(ointr))
1650 if (bustype == ISA || bustype == EISA) {
1651 if (SRCBUSIRQ(intr) != SRCBUSIRQ(ointr))
1654 if (INTPIN(intr) == INTPIN(ointr))
1658 if (ointr >= nintrs) {
1661 return INTIRQ(ointr);
1676 * Reprogram the MB chipset to NOT redirect an ISA INTerrupt.
1679 * Exactly what this means is unclear at this point. It is a solution
1680 * for motherboards that redirect the MBIRQ0 pin. Generically a motherboard
1681 * could route any of the ISA INTs to upper (>15) IRQ values. But most would
1682 * NOT be redirected via MBIRQ0, thus "undirect()ing" them would NOT be an
1686 undirect_isa_irq(int rirq)
1690 kprintf("Freeing redirected ISA irq %d.\n", rirq);
1691 /** FIXME: tickle the MB redirector chip */
1695 kprintf("Freeing (NOT implemented) redirected ISA irq %d.\n", rirq);
1702 * Reprogram the MB chipset to NOT redirect a PCI INTerrupt
1705 undirect_pci_irq(int rirq)
1709 kprintf("Freeing redirected PCI irq %d.\n", rirq);
1711 /** FIXME: tickle the MB redirector chip */
1715 kprintf("Freeing (NOT implemented) redirected PCI irq %d.\n",
1723 * given a bus ID, return:
1724 * the bus type if found
1728 apic_bus_type(int id)
1732 for (x = 0; x < mp_nbusses; ++x)
1733 if (bus_data[x].bus_id == id)
1734 return bus_data[x].bus_type;
1742 * given a LOGICAL APIC# and pin#, return:
1743 * the associated src bus ID if found
1747 apic_src_bus_id(int apic, int pin)
1751 /* search each of the possible INTerrupt sources */
1752 for (x = 0; x < nintrs; ++x)
1753 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1754 (pin == io_apic_ints[x].dst_apic_int))
1755 return (io_apic_ints[x].src_bus_id);
1757 return -1; /* NOT found */
1761 * given a LOGICAL APIC# and pin#, return:
1762 * the associated src bus IRQ if found
1766 apic_src_bus_irq(int apic, int pin)
1770 for (x = 0; x < nintrs; x++)
1771 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1772 (pin == io_apic_ints[x].dst_apic_int))
1773 return (io_apic_ints[x].src_bus_irq);
1775 return -1; /* NOT found */
1780 * given a LOGICAL APIC# and pin#, return:
1781 * the associated INTerrupt type if found
1785 apic_int_type(int apic, int pin)
1789 /* search each of the possible INTerrupt sources */
1790 for (x = 0; x < nintrs; ++x) {
1791 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1792 (pin == io_apic_ints[x].dst_apic_int))
1793 return (io_apic_ints[x].int_type);
1795 return -1; /* NOT found */
1799 * Return the IRQ associated with an APIC pin
1802 apic_irq(int apic, int pin)
1807 for (x = 0; x < nintrs; ++x) {
1808 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1809 (pin == io_apic_ints[x].dst_apic_int)) {
1810 res = io_apic_ints[x].int_vector;
1813 if (apic != int_to_apicintpin[res].ioapic)
1814 panic("apic_irq: inconsistent table %d/%d", apic, int_to_apicintpin[res].ioapic);
1815 if (pin != int_to_apicintpin[res].int_pin)
1816 panic("apic_irq inconsistent table (2)");
1825 * given a LOGICAL APIC# and pin#, return:
1826 * the associated trigger mode if found
1830 apic_trigger(int apic, int pin)
1834 /* search each of the possible INTerrupt sources */
1835 for (x = 0; x < nintrs; ++x)
1836 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1837 (pin == io_apic_ints[x].dst_apic_int))
1838 return ((io_apic_ints[x].int_flags >> 2) & 0x03);
1840 return -1; /* NOT found */
1845 * given a LOGICAL APIC# and pin#, return:
1846 * the associated 'active' level if found
1850 apic_polarity(int apic, int pin)
1854 /* search each of the possible INTerrupt sources */
1855 for (x = 0; x < nintrs; ++x)
1856 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1857 (pin == io_apic_ints[x].dst_apic_int))
1858 return (io_apic_ints[x].int_flags & 0x03);
1860 return -1; /* NOT found */
1866 * set data according to MP defaults
1867 * FIXME: probably not complete yet...
1870 default_mp_table(int type)
1873 #if defined(APIC_IO)
1876 #endif /* APIC_IO */
1879 kprintf(" MP default config type: %d\n", type);
1882 kprintf(" bus: ISA, APIC: 82489DX\n");
1885 kprintf(" bus: EISA, APIC: 82489DX\n");
1888 kprintf(" bus: EISA, APIC: 82489DX\n");
1891 kprintf(" bus: MCA, APIC: 82489DX\n");
1894 kprintf(" bus: ISA+PCI, APIC: Integrated\n");
1897 kprintf(" bus: EISA+PCI, APIC: Integrated\n");
1900 kprintf(" bus: MCA+PCI, APIC: Integrated\n");
1903 kprintf(" future type\n");
1909 boot_cpu_id = (lapic.id & APIC_ID_MASK) >> 24;
1910 ap_cpu_id = (boot_cpu_id == 0) ? 1 : 0;
1913 CPU_TO_ID(0) = boot_cpu_id;
1914 ID_TO_CPU(boot_cpu_id) = 0;
1916 /* one and only AP */
1917 CPU_TO_ID(1) = ap_cpu_id;
1918 ID_TO_CPU(ap_cpu_id) = 1;
1920 #if defined(APIC_IO)
1921 /* one and only IO APIC */
1922 io_apic_id = (io_apic_read(0, IOAPIC_ID) & APIC_ID_MASK) >> 24;
1925 * sanity check, refer to MP spec section 3.6.6, last paragraph
1926 * necessary as some hardware isn't properly setting up the IO APIC
1928 #if defined(REALLY_ANAL_IOAPICID_VALUE)
1929 if (io_apic_id != 2) {
1931 if ((io_apic_id == 0) || (io_apic_id == 1) || (io_apic_id == 15)) {
1932 #endif /* REALLY_ANAL_IOAPICID_VALUE */
1933 io_apic_set_id(0, 2);
1936 IO_TO_ID(0) = io_apic_id;
1937 ID_TO_IO(io_apic_id) = 0;
1938 #endif /* APIC_IO */
1940 /* fill out bus entries */
1949 bus_data[0].bus_id = default_data[type - 1][1];
1950 bus_data[0].bus_type = default_data[type - 1][2];
1951 bus_data[1].bus_id = default_data[type - 1][3];
1952 bus_data[1].bus_type = default_data[type - 1][4];
1955 /* case 4: case 7: MCA NOT supported */
1956 default: /* illegal/reserved */
1957 panic("BAD default MP config: %d", type);
1961 #if defined(APIC_IO)
1962 /* general cases from MP v1.4, table 5-2 */
1963 for (pin = 0; pin < 16; ++pin) {
1964 io_apic_ints[pin].int_type = 0;
1965 io_apic_ints[pin].int_flags = 0x05; /* edge/active-hi */
1966 io_apic_ints[pin].src_bus_id = 0;
1967 io_apic_ints[pin].src_bus_irq = pin; /* IRQ2 caught below */
1968 io_apic_ints[pin].dst_apic_id = io_apic_id;
1969 io_apic_ints[pin].dst_apic_int = pin; /* 1-to-1 */
1972 /* special cases from MP v1.4, table 5-2 */
1974 io_apic_ints[2].int_type = 0xff; /* N/C */
1975 io_apic_ints[13].int_type = 0xff; /* N/C */
1976 #if !defined(APIC_MIXED_MODE)
1978 panic("sorry, can't support type 2 default yet");
1979 #endif /* APIC_MIXED_MODE */
1982 io_apic_ints[2].src_bus_irq = 0; /* ISA IRQ0 is on APIC INT 2 */
1985 io_apic_ints[0].int_type = 0xff; /* N/C */
1987 io_apic_ints[0].int_type = 3; /* vectored 8259 */
1988 #endif /* APIC_IO */
1992 * Map a physical memory address representing I/O into KVA. The I/O
1993 * block is assumed not to cross a page boundary.
1996 permanent_io_mapping(vm_paddr_t pa)
2002 KKASSERT(pa < 0x100000000LL);
2004 pgeflag = 0; /* not used for SMP yet */
2007 * If the requested physical address has already been incidently
2008 * mapped, just use the existing mapping. Otherwise create a new
2011 for (i = IO_MAPPING_START_INDEX; i < SMPpt_alloc_index; ++i) {
2012 if (((vm_offset_t)SMPpt[i] & PG_FRAME) ==
2013 ((vm_offset_t)pa & PG_FRAME)) {
2017 if (i == SMPpt_alloc_index) {
2018 if (i == NPTEPG - 2) {
2019 panic("permanent_io_mapping: We ran out of space"
2022 SMPpt[i] = (pt_entry_t)(PG_V | PG_RW | pgeflag |
2023 ((vm_offset_t)pa & PG_FRAME));
2024 ++SMPpt_alloc_index;
2026 vaddr = (vm_offset_t)CPU_prvspace + (i * PAGE_SIZE) +
2027 ((vm_offset_t)pa & PAGE_MASK);
2028 return ((void *)vaddr);
2032 * start each AP in our list
2035 start_all_aps(u_int boot_addr)
2038 u_char mpbiosreason;
2039 u_long mpbioswarmvec;
2040 struct mdglobaldata *gd;
2041 struct privatespace *ps;
2045 POSTCODE(START_ALL_APS_POST);
2047 /* initialize BSP's local APIC */
2051 /* install the AP 1st level boot code */
2052 install_ap_tramp(boot_addr);
2055 /* save the current value of the warm-start vector */
2056 mpbioswarmvec = *((u_long *) WARMBOOT_OFF);
2057 outb(CMOS_REG, BIOS_RESET);
2058 mpbiosreason = inb(CMOS_DATA);
2060 /* set up temporary P==V mapping for AP boot */
2061 /* XXX this is a hack, we should boot the AP on its own stack/PTD */
2062 kptbase = (uintptr_t)(void *)KPTphys;
2063 for (x = 0; x < NKPT; x++) {
2064 PTD[x] = (pd_entry_t)(PG_V | PG_RW |
2065 ((kptbase + x * PAGE_SIZE) & PG_FRAME));
2070 for (x = 1; x <= mp_naps; ++x) {
2072 /* This is a bit verbose, it will go away soon. */
2074 /* first page of AP's private space */
2075 pg = x * i386_btop(sizeof(struct privatespace));
2077 /* allocate new private data page(s) */
2078 gd = (struct mdglobaldata *)kmem_alloc(&kernel_map,
2079 MDGLOBALDATA_BASEALLOC_SIZE);
2080 /* wire it into the private page table page */
2081 for (i = 0; i < MDGLOBALDATA_BASEALLOC_SIZE; i += PAGE_SIZE) {
2082 SMPpt[pg + i / PAGE_SIZE] = (pt_entry_t)
2083 (PG_V | PG_RW | vtophys_pte((char *)gd + i));
2085 pg += MDGLOBALDATA_BASEALLOC_PAGES;
2087 SMPpt[pg + 0] = 0; /* *gd_CMAP1 */
2088 SMPpt[pg + 1] = 0; /* *gd_CMAP2 */
2089 SMPpt[pg + 2] = 0; /* *gd_CMAP3 */
2090 SMPpt[pg + 3] = 0; /* *gd_PMAP1 */
2092 /* allocate and set up an idle stack data page */
2093 stack = (char *)kmem_alloc(&kernel_map, UPAGES*PAGE_SIZE);
2094 for (i = 0; i < UPAGES; i++) {
2095 SMPpt[pg + 4 + i] = (pt_entry_t)
2096 (PG_V | PG_RW | vtophys_pte(PAGE_SIZE * i + stack));
2099 gd = &CPU_prvspace[x].mdglobaldata; /* official location */
2100 bzero(gd, sizeof(*gd));
2101 gd->mi.gd_prvspace = ps = &CPU_prvspace[x];
2103 /* prime data page for it to use */
2104 mi_gdinit(&gd->mi, x);
2106 gd->gd_CMAP1 = &SMPpt[pg + 0];
2107 gd->gd_CMAP2 = &SMPpt[pg + 1];
2108 gd->gd_CMAP3 = &SMPpt[pg + 2];
2109 gd->gd_PMAP1 = &SMPpt[pg + 3];
2110 gd->gd_CADDR1 = ps->CPAGE1;
2111 gd->gd_CADDR2 = ps->CPAGE2;
2112 gd->gd_CADDR3 = ps->CPAGE3;
2113 gd->gd_PADDR1 = (unsigned *)ps->PPAGE1;
2114 gd->mi.gd_ipiq = (void *)kmem_alloc(&kernel_map, sizeof(lwkt_ipiq) * (mp_naps + 1));
2115 bzero(gd->mi.gd_ipiq, sizeof(lwkt_ipiq) * (mp_naps + 1));
2117 /* setup a vector to our boot code */
2118 *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET;
2119 *((volatile u_short *) WARMBOOT_SEG) = (boot_addr >> 4);
2120 outb(CMOS_REG, BIOS_RESET);
2121 outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */
2124 * Setup the AP boot stack
2126 bootSTK = &ps->idlestack[UPAGES*PAGE_SIZE/2];
2129 /* attempt to start the Application Processor */
2130 CHECK_INIT(99); /* setup checkpoints */
2131 if (!start_ap(gd, boot_addr)) {
2132 kprintf("AP #%d (PHY# %d) failed!\n", x, CPU_TO_ID(x));
2133 CHECK_PRINT("trace"); /* show checkpoints */
2134 /* better panic as the AP may be running loose */
2135 kprintf("panic y/n? [y] ");
2136 if (cngetc() != 'n')
2139 CHECK_PRINT("trace"); /* show checkpoints */
2141 /* record its version info */
2142 cpu_apic_versions[x] = cpu_apic_versions[0];
2145 /* set ncpus to 1 + highest logical cpu. Not all may have come up */
2148 /* round ncpus down to power of 2 */
2152 ncpus2 = 1 << ncpus2_shift;
2153 ncpus2_mask = ncpus2 - 1;
2155 /* build our map of 'other' CPUs */
2156 mycpu->gd_other_cpus = smp_startup_mask & ~(1 << mycpu->gd_cpuid);
2157 mycpu->gd_ipiq = (void *)kmem_alloc(&kernel_map, sizeof(lwkt_ipiq) * ncpus);
2158 bzero(mycpu->gd_ipiq, sizeof(lwkt_ipiq) * ncpus);
2160 /* fill in our (BSP) APIC version */
2161 cpu_apic_versions[0] = lapic.version;
2163 /* restore the warmstart vector */
2164 *(u_long *) WARMBOOT_OFF = mpbioswarmvec;
2165 outb(CMOS_REG, BIOS_RESET);
2166 outb(CMOS_DATA, mpbiosreason);
2169 * NOTE! The idlestack for the BSP was setup by locore. Finish
2170 * up, clean out the P==V mapping we did earlier.
2172 for (x = 0; x < NKPT; x++)
2176 /* number of APs actually started */
2182 * load the 1st level AP boot code into base memory.
2185 /* targets for relocation */
2186 extern void bigJump(void);
2187 extern void bootCodeSeg(void);
2188 extern void bootDataSeg(void);
2189 extern void MPentry(void);
2190 extern u_int MP_GDT;
2191 extern u_int mp_gdtbase;
2194 install_ap_tramp(u_int boot_addr)
2197 int size = *(int *) ((u_long) & bootMP_size);
2198 u_char *src = (u_char *) ((u_long) bootMP);
2199 u_char *dst = (u_char *) boot_addr + KERNBASE;
2200 u_int boot_base = (u_int) bootMP;
2205 POSTCODE(INSTALL_AP_TRAMP_POST);
2207 for (x = 0; x < size; ++x)
2211 * modify addresses in code we just moved to basemem. unfortunately we
2212 * need fairly detailed info about mpboot.s for this to work. changes
2213 * to mpboot.s might require changes here.
2216 /* boot code is located in KERNEL space */
2217 dst = (u_char *) boot_addr + KERNBASE;
2219 /* modify the lgdt arg */
2220 dst32 = (u_int32_t *) (dst + ((u_int) & mp_gdtbase - boot_base));
2221 *dst32 = boot_addr + ((u_int) & MP_GDT - boot_base);
2223 /* modify the ljmp target for MPentry() */
2224 dst32 = (u_int32_t *) (dst + ((u_int) bigJump - boot_base) + 1);
2225 *dst32 = ((u_int) MPentry - KERNBASE);
2227 /* modify the target for boot code segment */
2228 dst16 = (u_int16_t *) (dst + ((u_int) bootCodeSeg - boot_base));
2229 dst8 = (u_int8_t *) (dst16 + 1);
2230 *dst16 = (u_int) boot_addr & 0xffff;
2231 *dst8 = ((u_int) boot_addr >> 16) & 0xff;
2233 /* modify the target for boot data segment */
2234 dst16 = (u_int16_t *) (dst + ((u_int) bootDataSeg - boot_base));
2235 dst8 = (u_int8_t *) (dst16 + 1);
2236 *dst16 = (u_int) boot_addr & 0xffff;
2237 *dst8 = ((u_int) boot_addr >> 16) & 0xff;
2242 * this function starts the AP (application processor) identified
2243 * by the APIC ID 'physicalCpu'. It does quite a "song and dance"
2244 * to accomplish this. This is necessary because of the nuances
2245 * of the different hardware we might encounter. It ain't pretty,
2246 * but it seems to work.
2248 * NOTE: eventually an AP gets to ap_init(), which is called just
2249 * before the AP goes into the LWKT scheduler's idle loop.
2252 start_ap(struct mdglobaldata *gd, u_int boot_addr)
2256 u_long icr_lo, icr_hi;
2258 POSTCODE(START_AP_POST);
2260 /* get the PHYSICAL APIC ID# */
2261 physical_cpu = CPU_TO_ID(gd->mi.gd_cpuid);
2263 /* calculate the vector */
2264 vector = (boot_addr >> 12) & 0xff;
2266 /* Make sure the target cpu sees everything */
2270 * first we do an INIT/RESET IPI this INIT IPI might be run, reseting
2271 * and running the target CPU. OR this INIT IPI might be latched (P5
2272 * bug), CPU waiting for STARTUP IPI. OR this INIT IPI might be
2276 /* setup the address for the target AP */
2277 icr_hi = lapic.icr_hi & ~APIC_ID_MASK;
2278 icr_hi |= (physical_cpu << 24);
2279 lapic.icr_hi = icr_hi;
2281 /* do an INIT IPI: assert RESET */
2282 icr_lo = lapic.icr_lo & 0xfff00000;
2283 lapic.icr_lo = icr_lo | 0x0000c500;
2285 /* wait for pending status end */
2286 while (lapic.icr_lo & APIC_DELSTAT_MASK)
2289 /* do an INIT IPI: deassert RESET */
2290 lapic.icr_lo = icr_lo | 0x00008500;
2292 /* wait for pending status end */
2293 u_sleep(10000); /* wait ~10mS */
2294 while (lapic.icr_lo & APIC_DELSTAT_MASK)
2298 * next we do a STARTUP IPI: the previous INIT IPI might still be
2299 * latched, (P5 bug) this 1st STARTUP would then terminate
2300 * immediately, and the previously started INIT IPI would continue. OR
2301 * the previous INIT IPI has already run. and this STARTUP IPI will
2302 * run. OR the previous INIT IPI was ignored. and this STARTUP IPI
2306 /* do a STARTUP IPI */
2307 lapic.icr_lo = icr_lo | 0x00000600 | vector;
2308 while (lapic.icr_lo & APIC_DELSTAT_MASK)
2310 u_sleep(200); /* wait ~200uS */
2313 * finally we do a 2nd STARTUP IPI: this 2nd STARTUP IPI should run IF
2314 * the previous STARTUP IPI was cancelled by a latched INIT IPI. OR
2315 * this STARTUP IPI will be ignored, as only ONE STARTUP IPI is
2316 * recognized after hardware RESET or INIT IPI.
2319 lapic.icr_lo = icr_lo | 0x00000600 | vector;
2320 while (lapic.icr_lo & APIC_DELSTAT_MASK)
2322 u_sleep(200); /* wait ~200uS */
2324 /* wait for it to start, see ap_init() */
2325 set_apic_timer(5000000);/* == 5 seconds */
2326 while (read_apic_timer()) {
2327 if (smp_startup_mask & (1 << gd->mi.gd_cpuid))
2328 return 1; /* return SUCCESS */
2330 return 0; /* return FAILURE */
2335 * Lazy flush the TLB on all other CPU's. DEPRECATED.
2337 * If for some reason we were unable to start all cpus we cannot safely
2338 * use broadcast IPIs.
2344 if (smp_startup_mask == smp_active_mask) {
2345 all_but_self_ipi(XINVLTLB_OFFSET);
2347 selected_apic_ipi(smp_active_mask, XINVLTLB_OFFSET,
2348 APIC_DELMODE_FIXED);
2354 * When called the executing CPU will send an IPI to all other CPUs
2355 * requesting that they halt execution.
2357 * Usually (but not necessarily) called with 'other_cpus' as its arg.
2359 * - Signals all CPUs in map to stop.
2360 * - Waits for each to stop.
2367 * XXX FIXME: this is not MP-safe, needs a lock to prevent multiple CPUs
2368 * from executing at same time.
2371 stop_cpus(u_int map)
2373 map &= smp_active_mask;
2375 /* send the Xcpustop IPI to all CPUs in map */
2376 selected_apic_ipi(map, XCPUSTOP_OFFSET, APIC_DELMODE_FIXED);
2378 while ((stopped_cpus & map) != map)
2386 * Called by a CPU to restart stopped CPUs.
2388 * Usually (but not necessarily) called with 'stopped_cpus' as its arg.
2390 * - Signals all CPUs in map to restart.
2391 * - Waits for each to restart.
2399 restart_cpus(u_int map)
2401 /* signal other cpus to restart */
2402 started_cpus = map & smp_active_mask;
2404 while ((stopped_cpus & map) != 0) /* wait for each to clear its bit */
2411 * This is called once the mpboot code has gotten us properly relocated
2412 * and the MMU turned on, etc. ap_init() is actually the idle thread,
2413 * and when it returns the scheduler will call the real cpu_idle() main
2414 * loop for the idlethread. Interrupts are disabled on entry and should
2415 * remain disabled at return.
2423 * Adjust smp_startup_mask to signal the BSP that we have started
2424 * up successfully. Note that we do not yet hold the BGL. The BSP
2425 * is waiting for our signal.
2427 * We can't set our bit in smp_active_mask yet because we are holding
2428 * interrupts physically disabled and remote cpus could deadlock
2429 * trying to send us an IPI.
2431 smp_startup_mask |= 1 << mycpu->gd_cpuid;
2435 * Interlock for finalization. Wait until mp_finish is non-zero,
2436 * then get the MP lock.
2438 * Note: We are in a critical section.
2440 * Note: We have to synchronize td_mpcount to our desired MP state
2441 * before calling cpu_try_mplock().
2443 * Note: we are the idle thread, we can only spin.
2445 * Note: The load fence is memory volatile and prevents the compiler
2446 * from improperly caching mp_finish, and the cpu from improperly
2449 while (mp_finish == 0)
2451 ++curthread->td_mpcount;
2452 while (cpu_try_mplock() == 0)
2455 if (cpu_feature & CPUID_TSC) {
2457 * The BSP is constantly updating tsc0_offset, figure out the
2458 * relative difference to synchronize ktrdump.
2460 tsc_offsets[mycpu->gd_cpuid] = rdtsc() - tsc0_offset;
2463 /* BSP may have changed PTD while we're waiting for the lock */
2466 #if defined(I586_CPU) && !defined(NO_F00F_HACK)
2470 /* Build our map of 'other' CPUs. */
2471 mycpu->gd_other_cpus = smp_startup_mask & ~(1 << mycpu->gd_cpuid);
2473 kprintf("SMP: AP CPU #%d Launched!\n", mycpu->gd_cpuid);
2475 /* A quick check from sanity claus */
2476 apic_id = (apic_id_to_logical[(lapic.id & 0x0f000000) >> 24]);
2477 if (mycpu->gd_cpuid != apic_id) {
2478 kprintf("SMP: cpuid = %d\n", mycpu->gd_cpuid);
2479 kprintf("SMP: apic_id = %d\n", apic_id);
2480 kprintf("PTD[MPPTDI] = %p\n", (void *)PTD[MPPTDI]);
2481 panic("cpuid mismatch! boom!!");
2484 /* Init local apic for irq's */
2487 /* Set memory range attributes for this CPU to match the BSP */
2488 mem_range_AP_init();
2491 * Once we go active we must process any IPIQ messages that may
2492 * have been queued, because no actual IPI will occur until we
2493 * set our bit in the smp_active_mask. If we don't the IPI
2494 * message interlock could be left set which would also prevent
2497 * The idle loop doesn't expect the BGL to be held and while
2498 * lwkt_switch() normally cleans things up this is a special case
2499 * because we returning almost directly into the idle loop.
2501 * The idle thread is never placed on the runq, make sure
2502 * nothing we've done put it there.
2504 KKASSERT(curthread->td_mpcount == 1);
2505 smp_active_mask |= 1 << mycpu->gd_cpuid;
2506 initclocks_pcpu(); /* clock interrupts (via IPIs) */
2507 lwkt_process_ipiq();
2509 KKASSERT((curthread->td_flags & TDF_RUNQ) == 0);
2513 * Get SMP fully working before we start initializing devices.
2521 kprintf("Finish MP startup\n");
2522 if (cpu_feature & CPUID_TSC)
2523 tsc0_offset = rdtsc();
2526 while (smp_active_mask != smp_startup_mask) {
2528 if (cpu_feature & CPUID_TSC)
2529 tsc0_offset = rdtsc();
2531 while (try_mplock() == 0)
2534 kprintf("Active CPU Mask: %08x\n", smp_active_mask);
2537 SYSINIT(finishsmp, SI_SUB_FINISH_SMP, SI_ORDER_FIRST, ap_finish, NULL)
2540 cpu_send_ipiq(int dcpu)
2542 if ((1 << dcpu) & smp_active_mask)
2543 single_apic_ipi(dcpu, XIPIQ_OFFSET, APIC_DELMODE_FIXED);
2546 #if 0 /* single_apic_ipi_passive() not working yet */
2548 * Returns 0 on failure, 1 on success
2551 cpu_send_ipiq_passive(int dcpu)
2554 if ((1 << dcpu) & smp_active_mask) {
2555 r = single_apic_ipi_passive(dcpu, XIPIQ_OFFSET,
2556 APIC_DELMODE_FIXED);