2 * Copyright (c) 1996, by Steve Passe
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. The name of the developer may NOT be used to endorse or promote products
11 * derived from this software without specific prior written permission.
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * $FreeBSD: src/sys/i386/i386/mpapic.c,v 1.37.2.7 2003/01/25 02:31:47 peter Exp $
26 * $DragonFly: src/sys/platform/pc32/apic/mpapic.c,v 1.22 2008/04/20 13:44:26 swildner Exp $
29 #include <sys/param.h>
30 #include <sys/systm.h>
31 #include <sys/kernel.h>
32 #include <machine/globaldata.h>
33 #include <machine/smp.h>
34 #include <machine/md_var.h>
35 #include <machine_base/apic/mpapic.h>
36 #include <machine/segments.h>
37 #include <sys/thread2.h>
39 #include <machine_base/isa/intr_machdep.h> /* Xspuriousint() */
41 /* EISA Edge/Level trigger control registers */
42 #define ELCR0 0x4d0 /* eisa irq 0-7 */
43 #define ELCR1 0x4d1 /* eisa irq 8-15 */
45 static void lapic_timer_calibrate(void);
46 static void lapic_timer_set_divisor(int);
47 static void lapic_timer_fixup_handler(void *);
48 static void lapic_timer_restart_handler(void *);
50 void lapic_timer_process(void);
51 void lapic_timer_process_frame(struct intrframe *);
53 static int lapic_timer_enable = 1;
54 TUNABLE_INT("hw.lapic_timer_enable", &lapic_timer_enable);
56 static void lapic_timer_intr_reload(struct cputimer_intr *, sysclock_t);
57 static void lapic_timer_intr_enable(struct cputimer_intr *);
58 static void lapic_timer_intr_restart(struct cputimer_intr *);
59 static void lapic_timer_intr_pmfixup(struct cputimer_intr *);
61 static struct cputimer_intr lapic_cputimer_intr = {
63 .reload = lapic_timer_intr_reload,
64 .enable = lapic_timer_intr_enable,
65 .config = cputimer_intr_default_config,
66 .restart = lapic_timer_intr_restart,
67 .pmfixup = lapic_timer_intr_pmfixup,
68 .initclock = cputimer_intr_default_initclock,
69 .next = SLIST_ENTRY_INITIALIZER,
71 .type = CPUTIMER_INTR_LAPIC,
72 .prio = CPUTIMER_INTR_PRIO_LAPIC,
73 .caps = CPUTIMER_INTR_CAP_NONE
77 * pointers to pmapped apic hardware.
80 volatile ioapic_t **ioapic;
82 static int lapic_timer_divisor_idx = -1;
83 static const uint32_t lapic_timer_divisors[] = {
84 APIC_TDCR_2, APIC_TDCR_4, APIC_TDCR_8, APIC_TDCR_16,
85 APIC_TDCR_32, APIC_TDCR_64, APIC_TDCR_128, APIC_TDCR_1
87 #define APIC_TIMER_NDIVISORS \
88 (int)(sizeof(lapic_timer_divisors) / sizeof(lapic_timer_divisors[0]))
92 * Enable APIC, configure interrupts.
95 apic_initialize(boolean_t bsp)
101 * setup LVT1 as ExtINT on the BSP. This is theoretically an
102 * aggregate interrupt input from the 8259. The INTA cycle
103 * will be routed to the external controller (the 8259) which
104 * is expected to supply the vector.
106 * Must be setup edge triggered, active high.
108 * Disable LVT1 on the APs. It doesn't matter what delivery
109 * mode we use because we leave it masked.
111 temp = lapic.lvt_lint0;
112 temp &= ~(APIC_LVT_MASKED | APIC_LVT_TRIG_MASK |
113 APIC_LVT_POLARITY_MASK | APIC_LVT_DM_MASK);
114 if (mycpu->gd_cpuid == 0)
115 temp |= APIC_LVT_DM_EXTINT;
117 temp |= APIC_LVT_DM_FIXED | APIC_LVT_MASKED;
118 lapic.lvt_lint0 = temp;
121 * setup LVT2 as NMI, masked till later. Edge trigger, active high.
123 temp = lapic.lvt_lint1;
124 temp &= ~(APIC_LVT_MASKED | APIC_LVT_TRIG_MASK |
125 APIC_LVT_POLARITY_MASK | APIC_LVT_DM_MASK);
126 temp |= APIC_LVT_MASKED | APIC_LVT_DM_NMI;
127 lapic.lvt_lint1 = temp;
130 * Mask the apic error interrupt, apic performance counter
133 lapic.lvt_error = lapic.lvt_error | APIC_LVT_MASKED;
134 lapic.lvt_pcint = lapic.lvt_pcint | APIC_LVT_MASKED;
136 /* Set apic timer vector and mask the apic timer interrupt. */
137 timer = lapic.lvt_timer;
138 timer &= ~APIC_LVTT_VECTOR;
139 timer |= XTIMER_OFFSET;
140 timer |= APIC_LVTT_MASKED;
141 lapic.lvt_timer = timer;
144 * Set the Task Priority Register as needed. At the moment allow
145 * interrupts on all cpus (the APs will remain CLId until they are
146 * ready to deal). We could disable all but IPIs by setting
147 * temp |= TPR_IPI_ONLY for cpu != 0.
150 temp &= ~APIC_TPR_PRIO; /* clear priority field */
153 * If we are NOT running the IO APICs, the LAPIC will only be used
154 * for IPIs. Set the TPR to prevent any unintentional interrupts.
156 temp |= TPR_IPI_ONLY;
162 * enable the local APIC
165 temp |= APIC_SVR_ENABLE; /* enable the APIC */
166 temp &= ~APIC_SVR_FOCUS_DISABLE; /* enable lopri focus processor */
169 * Set the spurious interrupt vector. The low 4 bits of the vector
172 if ((XSPURIOUSINT_OFFSET & 0x0F) != 0x0F)
173 panic("bad XSPURIOUSINT_OFFSET: 0x%08x", XSPURIOUSINT_OFFSET);
174 temp &= ~APIC_SVR_VECTOR;
175 temp |= XSPURIOUSINT_OFFSET;
180 * Pump out a few EOIs to clean out interrupts that got through
181 * before we were able to set the TPR.
188 lapic_timer_calibrate();
189 if (lapic_timer_enable) {
190 cputimer_intr_register(&lapic_cputimer_intr);
191 cputimer_intr_select(&lapic_cputimer_intr, 0);
194 lapic_timer_set_divisor(lapic_timer_divisor_idx);
198 apic_dump("apic_initialize()");
203 lapic_timer_set_divisor(int divisor_idx)
205 KKASSERT(divisor_idx >= 0 && divisor_idx < APIC_TIMER_NDIVISORS);
206 lapic.dcr_timer = lapic_timer_divisors[divisor_idx];
210 lapic_timer_oneshot(u_int count)
214 value = lapic.lvt_timer;
215 value &= ~APIC_LVTT_PERIODIC;
216 lapic.lvt_timer = value;
217 lapic.icr_timer = count;
221 lapic_timer_oneshot_quick(u_int count)
223 lapic.icr_timer = count;
227 lapic_timer_calibrate(void)
231 /* Try to calibrate the local APIC timer. */
232 for (lapic_timer_divisor_idx = 0;
233 lapic_timer_divisor_idx < APIC_TIMER_NDIVISORS;
234 lapic_timer_divisor_idx++) {
235 lapic_timer_set_divisor(lapic_timer_divisor_idx);
236 lapic_timer_oneshot(APIC_TIMER_MAX_COUNT);
238 value = APIC_TIMER_MAX_COUNT - lapic.ccr_timer;
239 if (value != APIC_TIMER_MAX_COUNT)
242 if (lapic_timer_divisor_idx >= APIC_TIMER_NDIVISORS)
243 panic("lapic: no proper timer divisor?!\n");
244 lapic_cputimer_intr.freq = value / 2;
246 kprintf("lapic: divisor index %d, frequency %u Hz\n",
247 lapic_timer_divisor_idx, lapic_cputimer_intr.freq);
251 lapic_timer_process_oncpu(struct globaldata *gd, struct intrframe *frame)
255 gd->gd_timer_running = 0;
257 count = sys_cputimer->count();
258 if (TAILQ_FIRST(&gd->gd_systimerq) != NULL)
259 systimer_intr(&count, 0, frame);
263 lapic_timer_process(void)
265 lapic_timer_process_oncpu(mycpu, NULL);
269 lapic_timer_process_frame(struct intrframe *frame)
271 lapic_timer_process_oncpu(mycpu, frame);
275 lapic_timer_intr_reload(struct cputimer_intr *cti, sysclock_t reload)
277 struct globaldata *gd = mycpu;
279 reload = (int64_t)reload * cti->freq / sys_cputimer->freq;
283 if (gd->gd_timer_running) {
284 if (reload < lapic.ccr_timer)
285 lapic_timer_oneshot_quick(reload);
287 gd->gd_timer_running = 1;
288 lapic_timer_oneshot_quick(reload);
293 lapic_timer_intr_enable(struct cputimer_intr *cti __unused)
297 timer = lapic.lvt_timer;
298 timer &= ~(APIC_LVTT_MASKED | APIC_LVTT_PERIODIC);
299 lapic.lvt_timer = timer;
301 lapic_timer_fixup_handler(NULL);
305 lapic_timer_fixup_handler(void *arg)
312 if (strcmp(cpu_vendor, "AuthenticAMD") == 0) {
314 * Detect the presence of C1E capability mostly on latest
315 * dual-cores (or future) k8 family. This feature renders
316 * the local APIC timer dead, so we disable it by reading
317 * the Interrupt Pending Message register and clearing both
318 * C1eOnCmpHalt (bit 28) and SmiOnCmpHalt (bit 27).
321 * "BIOS and Kernel Developer's Guide for AMD NPT
322 * Family 0Fh Processors"
323 * #32559 revision 3.00
325 if ((cpu_id & 0x00000f00) == 0x00000f00 &&
326 (cpu_id & 0x0fff0000) >= 0x00040000) {
329 msr = rdmsr(0xc0010055);
330 if (msr & 0x18000000) {
331 struct globaldata *gd = mycpu;
333 kprintf("cpu%d: AMD C1E detected\n",
335 wrmsr(0xc0010055, msr & ~0x18000000ULL);
338 * We are kinda stalled;
341 gd->gd_timer_running = 1;
342 lapic_timer_oneshot_quick(2);
352 lapic_timer_restart_handler(void *dummy __unused)
356 lapic_timer_fixup_handler(&started);
358 struct globaldata *gd = mycpu;
360 gd->gd_timer_running = 1;
361 lapic_timer_oneshot_quick(2);
366 * This function is called only by ACPI-CA code currently:
367 * - AMD C1E fixup. AMD C1E only seems to happen after ACPI
368 * module controls PM. So once ACPI-CA is attached, we try
369 * to apply the fixup to prevent LAPIC timer from hanging.
372 lapic_timer_intr_pmfixup(struct cputimer_intr *cti __unused)
374 lwkt_send_ipiq_mask(smp_active_mask,
375 lapic_timer_fixup_handler, NULL);
379 lapic_timer_intr_restart(struct cputimer_intr *cti __unused)
381 lwkt_send_ipiq_mask(smp_active_mask, lapic_timer_restart_handler, NULL);
386 * dump contents of local APIC registers
391 kprintf("SMP: CPU%d %s:\n", mycpu->gd_cpuid, str);
392 kprintf(" lint0: 0x%08x lint1: 0x%08x TPR: 0x%08x SVR: 0x%08x\n",
393 lapic.lvt_lint0, lapic.lvt_lint1, lapic.tpr, lapic.svr);
403 #define IOAPIC_ISA_INTS 16
404 #define REDIRCNT_IOAPIC(A) \
405 ((int)((io_apic_versions[(A)] & IOART_VER_MAXREDIR) >> MAXREDIRSHIFT) + 1)
407 static int trigger (int apic, int pin, u_int32_t * flags);
408 static void polarity (int apic, int pin, u_int32_t * flags, int level);
410 #define DEFAULT_FLAGS \
416 #define DEFAULT_ISA_FLAGS \
425 io_apic_set_id(int apic, int id)
429 ux = io_apic_read(apic, IOAPIC_ID); /* get current contents */
430 if (((ux & APIC_ID_MASK) >> 24) != id) {
431 kprintf("Changing APIC ID for IO APIC #%d"
432 " from %d to %d on chip\n",
433 apic, ((ux & APIC_ID_MASK) >> 24), id);
434 ux &= ~APIC_ID_MASK; /* clear the ID field */
436 io_apic_write(apic, IOAPIC_ID, ux); /* write new value */
437 ux = io_apic_read(apic, IOAPIC_ID); /* re-read && test */
438 if (((ux & APIC_ID_MASK) >> 24) != id)
439 panic("can't control IO APIC #%d ID, reg: 0x%08x",
446 io_apic_get_id(int apic)
448 return (io_apic_read(apic, IOAPIC_ID) & APIC_ID_MASK) >> 24;
457 extern int apic_pin_trigger; /* 'opaque' */
460 io_apic_setup_intpin(int apic, int pin)
462 int bus, bustype, irq;
463 u_char select; /* the select register is 8 bits */
464 u_int32_t flags; /* the window register is 32 bits */
465 u_int32_t target; /* the window register is 32 bits */
466 u_int32_t vector; /* the window register is 32 bits */
469 select = pin * 2 + IOAPIC_REDTBL0; /* register */
472 * Always clear an IO APIC pin before [re]programming it. This is
473 * particularly important if the pin is set up for a level interrupt
474 * as the IOART_REM_IRR bit might be set. When we reprogram the
475 * vector any EOI from pending ints on this pin could be lost and
476 * IRR might never get reset.
478 * To fix this problem, clear the vector and make sure it is
479 * programmed as an edge interrupt. This should theoretically
480 * clear IRR so we can later, safely program it as a level
485 flags = io_apic_read(apic, select) & IOART_RESV;
486 flags |= IOART_INTMSET | IOART_TRGREDG | IOART_INTAHI;
487 flags |= IOART_DESTPHY | IOART_DELFIXED;
489 target = io_apic_read(apic, select + 1) & IOART_HI_DEST_RESV;
490 target |= 0; /* fixed mode cpu mask of 0 - don't deliver anywhere */
494 io_apic_write(apic, select, flags | vector);
495 io_apic_write(apic, select + 1, target);
500 * We only deal with vectored interrupts here. ? documentation is
501 * lacking, I'm guessing an interrupt type of 0 is the 'INT' type,
504 * This test also catches unconfigured pins.
506 if (apic_int_type(apic, pin) != 0)
510 * Leave the pin unprogrammed if it does not correspond to
513 irq = apic_irq(apic, pin);
517 /* determine the bus type for this pin */
518 bus = apic_src_bus_id(apic, pin);
521 bustype = apic_bus_type(bus);
523 if ((bustype == ISA) &&
524 (pin < IOAPIC_ISA_INTS) &&
526 (apic_polarity(apic, pin) == 0x1) &&
527 (apic_trigger(apic, pin) == 0x3)) {
529 * A broken BIOS might describe some ISA
530 * interrupts as active-high level-triggered.
531 * Use default ISA flags for those interrupts.
533 flags = DEFAULT_ISA_FLAGS;
536 * Program polarity and trigger mode according to
539 flags = DEFAULT_FLAGS;
540 level = trigger(apic, pin, &flags);
542 apic_pin_trigger |= (1 << irq);
543 polarity(apic, pin, &flags, level);
547 kprintf("IOAPIC #%d intpin %d -> irq %d\n",
552 * Program the appropriate registers. This routing may be
553 * overridden when an interrupt handler for a device is
554 * actually added (see register_int(), which calls through
555 * the MACHINTR ABI to set up an interrupt handler/vector).
557 * The order in which we must program the two registers for
558 * safety is unclear! XXX
562 vector = IDT_OFFSET + irq; /* IDT vec */
563 target = io_apic_read(apic, select + 1) & IOART_HI_DEST_RESV;
564 target |= IOART_HI_DEST_BROADCAST;
565 flags |= io_apic_read(apic, select) & IOART_RESV;
566 io_apic_write(apic, select, flags | vector);
567 io_apic_write(apic, select + 1, target);
573 io_apic_setup(int apic)
579 apic_pin_trigger = 0; /* default to edge-triggered */
581 maxpin = REDIRCNT_IOAPIC(apic); /* pins in APIC */
582 kprintf("Programming %d pins in IOAPIC #%d\n", maxpin, apic);
584 for (pin = 0; pin < maxpin; ++pin) {
585 io_apic_setup_intpin(apic, pin);
588 if (apic_int_type(apic, pin) >= 0) {
589 kprintf("Warning: IOAPIC #%d pin %d does not exist,"
590 " cannot program!\n", apic, pin);
595 /* return GOOD status */
598 #undef DEFAULT_ISA_FLAGS
602 #define DEFAULT_EXTINT_FLAGS \
611 * Setup the source of External INTerrupts.
614 ext_int_setup(int apic, int intr)
616 u_char select; /* the select register is 8 bits */
617 u_int32_t flags; /* the window register is 32 bits */
618 u_int32_t target; /* the window register is 32 bits */
619 u_int32_t vector; /* the window register is 32 bits */
621 if (apic_int_type(apic, intr) != 3)
624 target = IOART_HI_DEST_BROADCAST;
625 select = IOAPIC_REDTBL0 + (2 * intr);
626 vector = IDT_OFFSET + intr;
627 flags = DEFAULT_EXTINT_FLAGS;
629 io_apic_write(apic, select, flags | vector);
630 io_apic_write(apic, select + 1, target);
634 #undef DEFAULT_EXTINT_FLAGS
638 * Set the trigger level for an IO APIC pin.
641 trigger(int apic, int pin, u_int32_t * flags)
646 static int intcontrol = -1;
648 switch (apic_trigger(apic, pin)) {
654 *flags &= ~IOART_TRGRLVL; /* *flags |= IOART_TRGREDG */
658 *flags |= IOART_TRGRLVL;
666 if ((id = apic_src_bus_id(apic, pin)) == -1)
669 switch (apic_bus_type(id)) {
671 *flags &= ~IOART_TRGRLVL; /* *flags |= IOART_TRGREDG; */
675 eirq = apic_src_bus_irq(apic, pin);
677 if (eirq < 0 || eirq > 15) {
678 kprintf("EISA IRQ %d?!?!\n", eirq);
682 if (intcontrol == -1) {
683 intcontrol = inb(ELCR1) << 8;
684 intcontrol |= inb(ELCR0);
685 kprintf("EISA INTCONTROL = %08x\n", intcontrol);
688 /* Use ELCR settings to determine level or edge mode */
689 level = (intcontrol >> eirq) & 1;
692 * Note that on older Neptune chipset based systems, any
693 * pci interrupts often show up here and in the ELCR as well
694 * as level sensitive interrupts attributed to the EISA bus.
698 *flags |= IOART_TRGRLVL;
700 *flags &= ~IOART_TRGRLVL;
705 *flags |= IOART_TRGRLVL;
714 panic("bad APIC IO INT flags");
719 * Set the polarity value for an IO APIC pin.
722 polarity(int apic, int pin, u_int32_t * flags, int level)
726 switch (apic_polarity(apic, pin)) {
732 *flags &= ~IOART_INTALO; /* *flags |= IOART_INTAHI */
736 *flags |= IOART_INTALO;
744 if ((id = apic_src_bus_id(apic, pin)) == -1)
747 switch (apic_bus_type(id)) {
749 *flags &= ~IOART_INTALO; /* *flags |= IOART_INTAHI */
753 /* polarity converter always gives active high */
754 *flags &= ~IOART_INTALO;
758 *flags |= IOART_INTALO;
767 panic("bad APIC IO INT flags");
772 * Print contents of apic_imen.
774 extern u_int apic_imen; /* keep apic_imen 'opaque' */
780 kprintf("SMP: enabled INTs: ");
781 for (x = 0; x < 24; ++x)
782 if ((apic_imen & (1 << x)) == 0)
784 kprintf("apic_imen: 0x%08x\n", apic_imen);
789 * Inter Processor Interrupt functions.
795 * Send APIC IPI 'vector' to 'destType' via 'deliveryMode'.
797 * destType is 1 of: APIC_DEST_SELF, APIC_DEST_ALLISELF, APIC_DEST_ALLESELF
798 * vector is any valid SYSTEM INT vector
799 * delivery_mode is 1 of: APIC_DELMODE_FIXED, APIC_DELMODE_LOWPRIO
801 * A backlog of requests can create a deadlock between cpus. To avoid this
802 * we have to be able to accept IPIs at the same time we are trying to send
803 * them. The critical section prevents us from attempting to send additional
804 * IPIs reentrantly, but also prevents IPIQ processing so we have to call
805 * lwkt_process_ipiq() manually. It's rather messy and expensive for this
806 * to occur but fortunately it does not happen too often.
809 apic_ipi(int dest_type, int vector, int delivery_mode)
814 if ((lapic.icr_lo & APIC_DELSTAT_MASK) != 0) {
815 unsigned int eflags = read_eflags();
817 while ((lapic.icr_lo & APIC_DELSTAT_MASK) != 0) {
820 write_eflags(eflags);
823 icr_lo = (lapic.icr_lo & APIC_ICRLO_RESV_MASK) | dest_type |
824 delivery_mode | vector;
825 lapic.icr_lo = icr_lo;
831 single_apic_ipi(int cpu, int vector, int delivery_mode)
837 if ((lapic.icr_lo & APIC_DELSTAT_MASK) != 0) {
838 unsigned int eflags = read_eflags();
840 while ((lapic.icr_lo & APIC_DELSTAT_MASK) != 0) {
843 write_eflags(eflags);
845 icr_hi = lapic.icr_hi & ~APIC_ID_MASK;
846 icr_hi |= (CPU_TO_ID(cpu) << 24);
847 lapic.icr_hi = icr_hi;
850 icr_lo = (lapic.icr_lo & APIC_ICRLO_RESV_MASK)
851 | APIC_DEST_DESTFLD | delivery_mode | vector;
854 lapic.icr_lo = icr_lo;
861 * Returns 0 if the apic is busy, 1 if we were able to queue the request.
863 * NOT WORKING YET! The code as-is may end up not queueing an IPI at all
864 * to the target, and the scheduler does not 'poll' for IPI messages.
867 single_apic_ipi_passive(int cpu, int vector, int delivery_mode)
873 if ((lapic.icr_lo & APIC_DELSTAT_MASK) != 0) {
877 icr_hi = lapic.icr_hi & ~APIC_ID_MASK;
878 icr_hi |= (CPU_TO_ID(cpu) << 24);
879 lapic.icr_hi = icr_hi;
882 icr_lo = (lapic.icr_lo & APIC_RESV2_MASK)
883 | APIC_DEST_DESTFLD | delivery_mode | vector;
886 lapic.icr_lo = icr_lo;
894 * Send APIC IPI 'vector' to 'target's via 'delivery_mode'.
896 * target is a bitmask of destination cpus. Vector is any
897 * valid system INT vector. Delivery mode may be either
898 * APIC_DELMODE_FIXED or APIC_DELMODE_LOWPRIO.
901 selected_apic_ipi(u_int target, int vector, int delivery_mode)
905 int n = bsfl(target);
907 single_apic_ipi(n, vector, delivery_mode);
913 * Timer code, in development...
914 * - suggested by rgrimes@gndrsh.aac.dev.com
918 * Load a 'downcount time' in uSeconds.
921 set_apic_timer(int us)
926 * When we reach here, lapic timer's frequency
927 * must have been calculated as well as the
928 * divisor (lapic.dcr_timer is setup during the
929 * divisor calculation).
931 KKASSERT(lapic_cputimer_intr.freq != 0 &&
932 lapic_timer_divisor_idx >= 0);
934 count = ((us * (int64_t)lapic_cputimer_intr.freq) + 999999) / 1000000;
935 lapic_timer_oneshot(count);
940 * Read remaining time in timer.
943 read_apic_timer(void)
946 /** XXX FIXME: we need to return the actual remaining time,
947 * for now we just return the remaining count.
950 return lapic.ccr_timer;
956 * Spin-style delay, set delay time in uS, spin till it drains.
961 set_apic_timer(count);
962 while (read_apic_timer())