1 /* $OpenBSD: if_nfe.c,v 1.63 2006/06/17 18:00:43 brad Exp $ */
2 /* $DragonFly: src/sys/dev/netif/nfe/if_nfe.c,v 1.3 2006/09/16 06:37:11 sephe Exp $ */
5 * Copyright (c) 2006 The DragonFly Project. All rights reserved.
7 * This code is derived from software contributed to The DragonFly Project
8 * by Sepherosa Ziehau <sepherosa@gmail.com> and
9 * Matthew Dillon <dillon@apollo.backplane.com>
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in
19 * the documentation and/or other materials provided with the
21 * 3. Neither the name of The DragonFly Project nor the names of its
22 * contributors may be used to endorse or promote products derived
23 * from this software without specific, prior written permission.
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
28 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
29 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
30 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
31 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
32 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
33 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
34 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
35 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
40 * Copyright (c) 2006 Damien Bergamini <damien.bergamini@free.fr>
41 * Copyright (c) 2005, 2006 Jonathan Gray <jsg@openbsd.org>
43 * Permission to use, copy, modify, and distribute this software for any
44 * purpose with or without fee is hereby granted, provided that the above
45 * copyright notice and this permission notice appear in all copies.
47 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
48 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
49 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
50 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
51 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
52 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
53 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
56 /* Driver for NVIDIA nForce MCP Fast Ethernet and Gigabit Ethernet */
58 #include "opt_polling.h"
60 #include <sys/param.h>
61 #include <sys/endian.h>
62 #include <sys/kernel.h>
66 #include <sys/serialize.h>
67 #include <sys/socket.h>
68 #include <sys/sockio.h>
69 #include <sys/sysctl.h>
71 #include <machine/bus.h>
72 #include <machine/resource.h>
74 #include <net/ethernet.h>
77 #include <net/if_arp.h>
78 #include <net/if_dl.h>
79 #include <net/if_media.h>
80 #include <net/ifq_var.h>
81 #include <net/if_types.h>
82 #include <net/if_var.h>
83 #include <net/vlan/if_vlan_var.h>
85 #include <bus/pci/pcireg.h>
86 #include <bus/pci/pcivar.h>
87 #include <bus/pci/pcidevs.h>
89 #include <dev/netif/mii_layer/mii.h>
90 #include <dev/netif/mii_layer/miivar.h>
92 #include "miibus_if.h"
94 #include "if_nfereg.h"
95 #include "if_nfevar.h"
97 static int nfe_probe(device_t);
98 static int nfe_attach(device_t);
99 static int nfe_detach(device_t);
100 static void nfe_shutdown(device_t);
101 static int nfe_resume(device_t);
102 static int nfe_suspend(device_t);
104 static int nfe_miibus_readreg(device_t, int, int);
105 static void nfe_miibus_writereg(device_t, int, int, int);
106 static void nfe_miibus_statchg(device_t);
108 #ifdef DEVICE_POLLING
109 static void nfe_poll(struct ifnet *, enum poll_cmd, int);
111 static void nfe_intr(void *);
112 static int nfe_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
113 static void nfe_rxeof(struct nfe_softc *);
114 static void nfe_txeof(struct nfe_softc *);
115 static int nfe_encap(struct nfe_softc *, struct nfe_tx_ring *,
117 static void nfe_start(struct ifnet *);
118 static void nfe_watchdog(struct ifnet *);
119 static void nfe_init(void *);
120 static void nfe_stop(struct nfe_softc *);
121 static struct nfe_jbuf *nfe_jalloc(struct nfe_softc *);
122 static void nfe_jfree(void *);
123 static void nfe_jref(void *);
124 static int nfe_jpool_alloc(struct nfe_softc *, struct nfe_rx_ring *);
125 static void nfe_jpool_free(struct nfe_softc *, struct nfe_rx_ring *);
126 static int nfe_alloc_rx_ring(struct nfe_softc *, struct nfe_rx_ring *);
127 static void nfe_reset_rx_ring(struct nfe_softc *, struct nfe_rx_ring *);
128 static int nfe_init_rx_ring(struct nfe_softc *, struct nfe_rx_ring *);
129 static void nfe_free_rx_ring(struct nfe_softc *, struct nfe_rx_ring *);
130 static int nfe_alloc_tx_ring(struct nfe_softc *, struct nfe_tx_ring *);
131 static void nfe_reset_tx_ring(struct nfe_softc *, struct nfe_tx_ring *);
132 static int nfe_init_tx_ring(struct nfe_softc *, struct nfe_tx_ring *);
133 static void nfe_free_tx_ring(struct nfe_softc *, struct nfe_tx_ring *);
134 static int nfe_ifmedia_upd(struct ifnet *);
135 static void nfe_ifmedia_sts(struct ifnet *, struct ifmediareq *);
136 static void nfe_setmulti(struct nfe_softc *);
137 static void nfe_get_macaddr(struct nfe_softc *, uint8_t *);
138 static void nfe_set_macaddr(struct nfe_softc *, const uint8_t *);
139 static void nfe_tick(void *);
140 static void nfe_ring_dma_addr(void *, bus_dma_segment_t *, int, int);
141 static void nfe_buf_dma_addr(void *, bus_dma_segment_t *, int, bus_size_t,
143 static void nfe_set_paddr_rxdesc(struct nfe_softc *, struct nfe_rx_ring *,
145 static void nfe_set_ready_rxdesc(struct nfe_softc *, struct nfe_rx_ring *,
147 static int nfe_newbuf_std(struct nfe_softc *, struct nfe_rx_ring *, int,
149 static int nfe_newbuf_jumbo(struct nfe_softc *, struct nfe_rx_ring *, int,
155 static int nfe_debug = 0;
157 SYSCTL_NODE(_hw, OID_AUTO, nfe, CTLFLAG_RD, 0, "nVidia GigE parameters");
158 SYSCTL_INT(_hw_nfe, OID_AUTO, debug, CTLFLAG_RW, &nfe_debug, 0,
159 "control debugging printfs");
161 #define DPRINTF(sc, fmt, ...) do { \
163 if_printf(&(sc)->arpcom.ac_if, \
168 #define DPRINTFN(sc, lv, fmt, ...) do { \
169 if (nfe_debug >= (lv)) { \
170 if_printf(&(sc)->arpcom.ac_if, \
175 #else /* !NFE_DEBUG */
177 #define DPRINTF(sc, fmt, ...)
178 #define DPRINTFN(sc, lv, fmt, ...)
180 #endif /* NFE_DEBUG */
184 bus_dma_segment_t *segs;
187 static const struct nfe_dev {
192 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE_LAN,
193 "NVIDIA nForce Gigabit Ethernet" },
195 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE2_LAN,
196 "NVIDIA nForce2 Gigabit Ethernet" },
198 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN1,
199 "NVIDIA nForce3 Gigabit Ethernet" },
201 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN2,
202 "NVIDIA nForce3 Gigabit Ethernet" },
204 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN3,
205 "NVIDIA nForce3 Gigabit Ethernet" },
207 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN4,
208 "NVIDIA nForce3 Gigabit Ethernet" },
210 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN5,
211 "NVIDIA nForce3 Gigabit Ethernet" },
213 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_CK804_LAN1,
214 "NVIDIA CK804 Gigabit Ethernet" },
216 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_CK804_LAN2,
217 "NVIDIA CK804 Gigabit Ethernet" },
219 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP04_LAN1,
220 "NVIDIA MCP04 Gigabit Ethernet" },
222 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP04_LAN2,
223 "NVIDIA MCP04 Gigabit Ethernet" },
225 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP51_LAN1,
226 "NVIDIA MCP51 Gigabit Ethernet" },
228 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP51_LAN2,
229 "NVIDIA MCP51 Gigabit Ethernet" },
231 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP55_LAN1,
232 "NVIDIA MCP55 Gigabit Ethernet" },
234 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP55_LAN2,
235 "NVIDIA MCP55 Gigabit Ethernet" },
237 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN1,
238 "NVIDIA MCP61 Gigabit Ethernet" },
240 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN2,
241 "NVIDIA MCP61 Gigabit Ethernet" },
243 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN3,
244 "NVIDIA MCP61 Gigabit Ethernet" },
246 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN4,
247 "NVIDIA MCP61 Gigabit Ethernet" },
249 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN1,
250 "NVIDIA MCP65 Gigabit Ethernet" },
252 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN2,
253 "NVIDIA MCP65 Gigabit Ethernet" },
255 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN3,
256 "NVIDIA MCP65 Gigabit Ethernet" },
258 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN4,
259 "NVIDIA MCP65 Gigabit Ethernet" }
262 static device_method_t nfe_methods[] = {
263 /* Device interface */
264 DEVMETHOD(device_probe, nfe_probe),
265 DEVMETHOD(device_attach, nfe_attach),
266 DEVMETHOD(device_detach, nfe_detach),
267 DEVMETHOD(device_suspend, nfe_suspend),
268 DEVMETHOD(device_resume, nfe_resume),
269 DEVMETHOD(device_shutdown, nfe_shutdown),
272 DEVMETHOD(bus_print_child, bus_generic_print_child),
273 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
276 DEVMETHOD(miibus_readreg, nfe_miibus_readreg),
277 DEVMETHOD(miibus_writereg, nfe_miibus_writereg),
278 DEVMETHOD(miibus_statchg, nfe_miibus_statchg),
283 static driver_t nfe_driver = {
286 sizeof(struct nfe_softc)
289 static devclass_t nfe_devclass;
291 DECLARE_DUMMY_MODULE(if_nfe);
292 MODULE_DEPEND(if_nfe, miibus, 1, 1, 1);
293 DRIVER_MODULE(if_nfe, pci, nfe_driver, nfe_devclass, 0, 0);
294 DRIVER_MODULE(miibus, nfe, miibus_driver, miibus_devclass, 0, 0);
297 nfe_probe(device_t dev)
299 const struct nfe_dev *n;
302 vid = pci_get_vendor(dev);
303 did = pci_get_device(dev);
304 for (n = nfe_devices; n->desc != NULL; ++n) {
305 if (vid == n->vid && did == n->did) {
306 struct nfe_softc *sc = device_get_softc(dev);
309 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN2:
310 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN3:
311 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN4:
312 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN5:
313 sc->sc_flags = NFE_JUMBO_SUP |
316 case PCI_PRODUCT_NVIDIA_MCP51_LAN1:
317 case PCI_PRODUCT_NVIDIA_MCP51_LAN2:
318 case PCI_PRODUCT_NVIDIA_MCP61_LAN1:
319 case PCI_PRODUCT_NVIDIA_MCP61_LAN2:
320 case PCI_PRODUCT_NVIDIA_MCP61_LAN3:
321 case PCI_PRODUCT_NVIDIA_MCP61_LAN4:
322 sc->sc_flags = NFE_40BIT_ADDR;
324 case PCI_PRODUCT_NVIDIA_CK804_LAN1:
325 case PCI_PRODUCT_NVIDIA_CK804_LAN2:
326 case PCI_PRODUCT_NVIDIA_MCP04_LAN1:
327 case PCI_PRODUCT_NVIDIA_MCP04_LAN2:
328 case PCI_PRODUCT_NVIDIA_MCP65_LAN1:
329 case PCI_PRODUCT_NVIDIA_MCP65_LAN2:
330 case PCI_PRODUCT_NVIDIA_MCP65_LAN3:
331 case PCI_PRODUCT_NVIDIA_MCP65_LAN4:
332 sc->sc_flags = NFE_JUMBO_SUP |
336 case PCI_PRODUCT_NVIDIA_MCP55_LAN1:
337 case PCI_PRODUCT_NVIDIA_MCP55_LAN2:
338 sc->sc_flags = NFE_JUMBO_SUP |
345 /* Enable jumbo frames for adapters that support it */
346 if (sc->sc_flags & NFE_JUMBO_SUP)
347 sc->sc_flags |= NFE_USE_JUMBO;
349 device_set_desc(dev, n->desc);
357 nfe_attach(device_t dev)
359 struct nfe_softc *sc = device_get_softc(dev);
360 struct ifnet *ifp = &sc->arpcom.ac_if;
361 uint8_t eaddr[ETHER_ADDR_LEN];
364 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
365 lwkt_serialize_init(&sc->sc_jbuf_serializer);
367 sc->sc_mem_rid = PCIR_BAR(0);
370 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
373 mem = pci_read_config(dev, sc->sc_mem_rid, 4);
374 irq = pci_read_config(dev, PCIR_INTLINE, 4);
376 device_printf(dev, "chip is in D%d power mode "
377 "-- setting to D0\n", pci_get_powerstate(dev));
379 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
381 pci_write_config(dev, sc->sc_mem_rid, mem, 4);
382 pci_write_config(dev, PCIR_INTLINE, irq, 4);
384 #endif /* !BURN_BRIDGE */
386 /* Enable bus mastering */
387 pci_enable_busmaster(dev);
389 /* Allocate IO memory */
390 sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
391 &sc->sc_mem_rid, RF_ACTIVE);
392 if (sc->sc_mem_res == NULL) {
393 device_printf(dev, "cound not allocate io memory\n");
396 sc->sc_memh = rman_get_bushandle(sc->sc_mem_res);
397 sc->sc_memt = rman_get_bustag(sc->sc_mem_res);
401 sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ,
403 RF_SHAREABLE | RF_ACTIVE);
404 if (sc->sc_irq_res == NULL) {
405 device_printf(dev, "could not allocate irq\n");
410 nfe_get_macaddr(sc, eaddr);
413 * Allocate Tx and Rx rings.
415 error = nfe_alloc_tx_ring(sc, &sc->txq);
417 device_printf(dev, "could not allocate Tx ring\n");
421 error = nfe_alloc_rx_ring(sc, &sc->rxq);
423 device_printf(dev, "could not allocate Rx ring\n");
427 error = mii_phy_probe(dev, &sc->sc_miibus, nfe_ifmedia_upd,
430 device_printf(dev, "MII without any phy\n");
435 ifp->if_mtu = ETHERMTU;
436 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
437 ifp->if_ioctl = nfe_ioctl;
438 ifp->if_start = nfe_start;
439 #ifdef DEVICE_POLLING
440 ifp->if_poll = nfe_poll;
442 ifp->if_watchdog = nfe_watchdog;
443 ifp->if_init = nfe_init;
444 ifq_set_maxlen(&ifp->if_snd, NFE_IFQ_MAXLEN);
445 ifq_set_ready(&ifp->if_snd);
447 ifp->if_capabilities = IFCAP_VLAN_MTU;
450 if (sc->sc_flags & NFE_USE_JUMBO)
451 ifp->if_hardmtu = NFE_JUMBO_MTU;
454 if (sc->sc_flags & NFE_HW_VLAN)
455 ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING;
458 if (sc->sc_flags & NFE_HW_CSUM) {
460 ifp->if_capabilities |= IFCAP_CSUM_IPv4 | IFCAP_CSUM_TCPv4 |
463 ifp->if_capabilities = IFCAP_HWCSUM;
464 ifp->if_hwassist = CSUM_IP | CSUM_TCP | CSUM_UDP;
468 ifp->if_capenable = ifp->if_capabilities;
470 callout_init(&sc->sc_tick_ch);
472 ether_ifattach(ifp, eaddr, NULL);
474 error = bus_setup_intr(dev, sc->sc_irq_res, INTR_MPSAFE, nfe_intr, sc,
475 &sc->sc_ih, ifp->if_serializer);
477 device_printf(dev, "could not setup intr\n");
489 nfe_detach(device_t dev)
491 struct nfe_softc *sc = device_get_softc(dev);
493 if (device_is_attached(dev)) {
494 struct ifnet *ifp = &sc->arpcom.ac_if;
496 lwkt_serialize_enter(ifp->if_serializer);
498 bus_teardown_intr(dev, sc->sc_irq_res, sc->sc_ih);
499 lwkt_serialize_exit(ifp->if_serializer);
504 if (sc->sc_miibus != NULL)
505 device_delete_child(dev, sc->sc_miibus);
506 bus_generic_detach(dev);
508 if (sc->sc_irq_res != NULL) {
509 bus_release_resource(dev, SYS_RES_IRQ, sc->sc_irq_rid,
513 if (sc->sc_mem_res != NULL) {
514 bus_release_resource(dev, SYS_RES_MEMORY, sc->sc_mem_rid,
518 nfe_free_tx_ring(sc, &sc->txq);
519 nfe_free_rx_ring(sc, &sc->rxq);
525 nfe_shutdown(device_t dev)
527 struct nfe_softc *sc = device_get_softc(dev);
528 struct ifnet *ifp = &sc->arpcom.ac_if;
530 lwkt_serialize_enter(ifp->if_serializer);
532 lwkt_serialize_exit(ifp->if_serializer);
536 nfe_suspend(device_t dev)
538 struct nfe_softc *sc = device_get_softc(dev);
539 struct ifnet *ifp = &sc->arpcom.ac_if;
541 lwkt_serialize_enter(ifp->if_serializer);
543 lwkt_serialize_exit(ifp->if_serializer);
549 nfe_resume(device_t dev)
551 struct nfe_softc *sc = device_get_softc(dev);
552 struct ifnet *ifp = &sc->arpcom.ac_if;
554 lwkt_serialize_enter(ifp->if_serializer);
555 if (ifp->if_flags & IFF_UP) {
557 if (ifp->if_flags & IFF_RUNNING)
560 lwkt_serialize_exit(ifp->if_serializer);
566 nfe_miibus_statchg(device_t dev)
568 struct nfe_softc *sc = device_get_softc(dev);
569 struct mii_data *mii = device_get_softc(sc->sc_miibus);
570 uint32_t phy, seed, misc = NFE_MISC1_MAGIC, link = NFE_MEDIA_SET;
572 phy = NFE_READ(sc, NFE_PHY_IFACE);
573 phy &= ~(NFE_PHY_HDX | NFE_PHY_100TX | NFE_PHY_1000T);
575 seed = NFE_READ(sc, NFE_RNDSEED);
576 seed &= ~NFE_SEED_MASK;
578 if ((mii->mii_media_active & IFM_GMASK) == IFM_HDX) {
579 phy |= NFE_PHY_HDX; /* half-duplex */
580 misc |= NFE_MISC1_HDX;
583 switch (IFM_SUBTYPE(mii->mii_media_active)) {
584 case IFM_1000_T: /* full-duplex only */
585 link |= NFE_MEDIA_1000T;
586 seed |= NFE_SEED_1000T;
587 phy |= NFE_PHY_1000T;
590 link |= NFE_MEDIA_100TX;
591 seed |= NFE_SEED_100TX;
592 phy |= NFE_PHY_100TX;
595 link |= NFE_MEDIA_10T;
596 seed |= NFE_SEED_10T;
600 NFE_WRITE(sc, NFE_RNDSEED, seed); /* XXX: gigabit NICs only? */
602 NFE_WRITE(sc, NFE_PHY_IFACE, phy);
603 NFE_WRITE(sc, NFE_MISC1, misc);
604 NFE_WRITE(sc, NFE_LINKSPEED, link);
608 nfe_miibus_readreg(device_t dev, int phy, int reg)
610 struct nfe_softc *sc = device_get_softc(dev);
614 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf);
616 if (NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY) {
617 NFE_WRITE(sc, NFE_PHY_CTL, NFE_PHY_BUSY);
621 NFE_WRITE(sc, NFE_PHY_CTL, (phy << NFE_PHYADD_SHIFT) | reg);
623 for (ntries = 0; ntries < 1000; ntries++) {
625 if (!(NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY))
628 if (ntries == 1000) {
629 DPRINTFN(sc, 2, "timeout waiting for PHY %s\n", "");
633 if (NFE_READ(sc, NFE_PHY_STATUS) & NFE_PHY_ERROR) {
634 DPRINTFN(sc, 2, "could not read PHY %s\n", "");
638 val = NFE_READ(sc, NFE_PHY_DATA);
639 if (val != 0xffffffff && val != 0)
640 sc->mii_phyaddr = phy;
642 DPRINTFN(sc, 2, "mii read phy %d reg 0x%x ret 0x%x\n", phy, reg, val);
648 nfe_miibus_writereg(device_t dev, int phy, int reg, int val)
650 struct nfe_softc *sc = device_get_softc(dev);
654 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf);
656 if (NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY) {
657 NFE_WRITE(sc, NFE_PHY_CTL, NFE_PHY_BUSY);
661 NFE_WRITE(sc, NFE_PHY_DATA, val);
662 ctl = NFE_PHY_WRITE | (phy << NFE_PHYADD_SHIFT) | reg;
663 NFE_WRITE(sc, NFE_PHY_CTL, ctl);
665 for (ntries = 0; ntries < 1000; ntries++) {
667 if (!(NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY))
673 DPRINTFN(sc, 2, "could not write to PHY %s\n", "");
677 #ifdef DEVICE_POLLING
680 nfe_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
682 struct nfe_softc *sc = ifp->if_softc;
686 /* Disable interrupts */
687 NFE_WRITE(sc, NFE_IRQ_MASK, 0);
689 case POLL_DEREGISTER:
690 /* enable interrupts */
691 NFE_WRITE(sc, NFE_IRQ_MASK, NFE_IRQ_WANTED);
693 case POLL_AND_CHECK_STATUS:
696 if (ifp->if_flags & IFF_RUNNING) {
709 struct nfe_softc *sc = arg;
710 struct ifnet *ifp = &sc->arpcom.ac_if;
713 r = NFE_READ(sc, NFE_IRQ_STATUS);
715 return; /* not for us */
716 NFE_WRITE(sc, NFE_IRQ_STATUS, r);
718 DPRINTFN(sc, 5, "%s: interrupt register %x\n", __func__, r);
720 if (r & NFE_IRQ_LINK) {
721 NFE_READ(sc, NFE_PHY_STATUS);
722 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf);
723 DPRINTF(sc, "link state changed %s\n", "");
726 if (ifp->if_flags & IFF_RUNNING) {
736 nfe_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data, struct ucred *cr)
738 struct nfe_softc *sc = ifp->if_softc;
739 struct ifreq *ifr = (struct ifreq *)data;
740 struct mii_data *mii;
745 /* XXX NFE_USE_JUMBO should be set here */
748 if (ifp->if_flags & IFF_UP) {
750 * If only the PROMISC or ALLMULTI flag changes, then
751 * don't do a full re-init of the chip, just update
754 if ((ifp->if_flags & IFF_RUNNING) &&
755 ((ifp->if_flags ^ sc->sc_if_flags) &
756 (IFF_ALLMULTI | IFF_PROMISC)) != 0) {
759 if (!(ifp->if_flags & IFF_RUNNING))
763 if (ifp->if_flags & IFF_RUNNING)
766 sc->sc_if_flags = ifp->if_flags;
770 if (ifp->if_flags & IFF_RUNNING)
775 mii = device_get_softc(sc->sc_miibus);
776 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd);
779 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
780 if (mask & IFCAP_HWCSUM) {
781 if (IFCAP_HWCSUM & ifp->if_capenable)
782 ifp->if_capenable &= ~IFCAP_HWCSUM;
784 ifp->if_capenable |= IFCAP_HWCSUM;
788 error = ether_ioctl(ifp, cmd, data);
795 nfe_rxeof(struct nfe_softc *sc)
797 struct ifnet *ifp = &sc->arpcom.ac_if;
798 struct nfe_rx_ring *ring = &sc->rxq;
802 bus_dmamap_sync(ring->tag, ring->map, BUS_DMASYNC_POSTREAD);
805 struct nfe_rx_data *data = &ring->data[ring->cur];
810 if (sc->sc_flags & NFE_40BIT_ADDR) {
811 struct nfe_desc64 *desc64 = &ring->desc64[ring->cur];
813 flags = le16toh(desc64->flags);
814 len = le16toh(desc64->length) & 0x3fff;
816 struct nfe_desc32 *desc32 = &ring->desc32[ring->cur];
818 flags = le16toh(desc32->flags);
819 len = le16toh(desc32->length) & 0x3fff;
822 if (flags & NFE_RX_READY)
827 if ((sc->sc_flags & (NFE_JUMBO_SUP | NFE_40BIT_ADDR)) == 0) {
828 if (!(flags & NFE_RX_VALID_V1))
831 if ((flags & NFE_RX_FIXME_V1) == NFE_RX_FIXME_V1) {
832 flags &= ~NFE_RX_ERROR;
833 len--; /* fix buffer length */
836 if (!(flags & NFE_RX_VALID_V2))
839 if ((flags & NFE_RX_FIXME_V2) == NFE_RX_FIXME_V2) {
840 flags &= ~NFE_RX_ERROR;
841 len--; /* fix buffer length */
845 if (flags & NFE_RX_ERROR) {
852 if (sc->sc_flags & NFE_USE_JUMBO)
853 error = nfe_newbuf_jumbo(sc, ring, ring->cur, 0);
855 error = nfe_newbuf_std(sc, ring, ring->cur, 0);
862 m->m_pkthdr.len = m->m_len = len;
863 m->m_pkthdr.rcvif = ifp;
866 if (sc->sc_flags & NFE_HW_CSUM) {
867 if (flags & NFE_RX_IP_CSUMOK)
868 m->m_pkthdr.csum_flags |= M_IPV4_CSUM_IN_OK;
869 if (flags & NFE_RX_UDP_CSUMOK)
870 m->m_pkthdr.csum_flags |= M_UDP_CSUM_IN_OK;
871 if (flags & NFE_RX_TCP_CSUMOK)
872 m->m_pkthdr.csum_flags |= M_TCP_CSUM_IN_OK;
874 #elif defined(NFE_CSUM)
875 if ((sc->sc_flags & NFE_HW_CSUM) && (flags & NFE_RX_CSUMOK))
876 m->m_pkthdr.csum_flags = M_IPV4_CSUM_IN_OK;
880 ifp->if_input(ifp, m);
882 nfe_set_ready_rxdesc(sc, ring, ring->cur);
883 sc->rxq.cur = (sc->rxq.cur + 1) % NFE_RX_RING_COUNT;
887 bus_dmamap_sync(ring->tag, ring->map, BUS_DMASYNC_PREWRITE);
891 nfe_txeof(struct nfe_softc *sc)
893 struct ifnet *ifp = &sc->arpcom.ac_if;
894 struct nfe_tx_ring *ring = &sc->txq;
895 struct nfe_tx_data *data = NULL;
897 bus_dmamap_sync(ring->tag, ring->map, BUS_DMASYNC_POSTREAD);
898 while (ring->next != ring->cur) {
901 if (sc->sc_flags & NFE_40BIT_ADDR)
902 flags = le16toh(ring->desc64[ring->next].flags);
904 flags = le16toh(ring->desc32[ring->next].flags);
906 if (flags & NFE_TX_VALID)
909 data = &ring->data[ring->next];
911 if ((sc->sc_flags & (NFE_JUMBO_SUP | NFE_40BIT_ADDR)) == 0) {
912 if (!(flags & NFE_TX_LASTFRAG_V1) && data->m == NULL)
915 if ((flags & NFE_TX_ERROR_V1) != 0) {
916 if_printf(ifp, "tx v1 error 0x%4b\n", flags,
923 if (!(flags & NFE_TX_LASTFRAG_V2) && data->m == NULL)
926 if ((flags & NFE_TX_ERROR_V2) != 0) {
927 if_printf(ifp, "tx v2 error 0x%4b\n", flags,
935 if (data->m == NULL) { /* should not get there */
937 "last fragment bit w/o associated mbuf!\n");
941 /* last fragment of the mbuf chain transmitted */
942 bus_dmamap_sync(ring->data_tag, data->map,
943 BUS_DMASYNC_POSTWRITE);
944 bus_dmamap_unload(ring->data_tag, data->map);
951 KKASSERT(ring->queued >= 0);
952 ring->next = (ring->next + 1) % NFE_TX_RING_COUNT;
955 if (data != NULL) { /* at least one slot freed */
956 ifp->if_flags &= ~IFF_OACTIVE;
962 nfe_encap(struct nfe_softc *sc, struct nfe_tx_ring *ring, struct mbuf *m0)
964 struct nfe_dma_ctx ctx;
965 bus_dma_segment_t segs[NFE_MAX_SCATTER];
966 struct nfe_tx_data *data, *data_map;
968 struct nfe_desc64 *desc64 = NULL;
969 struct nfe_desc32 *desc32 = NULL;
974 data = &ring->data[ring->cur];
976 data_map = data; /* Remember who owns the DMA map */
978 ctx.nsegs = NFE_MAX_SCATTER;
980 error = bus_dmamap_load_mbuf(ring->data_tag, map, m0,
981 nfe_buf_dma_addr, &ctx, BUS_DMA_NOWAIT);
982 if (error && error != EFBIG) {
983 if_printf(&sc->arpcom.ac_if, "could not map TX mbuf\n");
987 if (error) { /* error == EFBIG */
990 m_new = m_defrag(m0, MB_DONTWAIT);
992 if_printf(&sc->arpcom.ac_if,
993 "could not defrag TX mbuf\n");
1000 ctx.nsegs = NFE_MAX_SCATTER;
1002 error = bus_dmamap_load_mbuf(ring->data_tag, map, m0,
1003 nfe_buf_dma_addr, &ctx,
1006 if_printf(&sc->arpcom.ac_if,
1007 "could not map defraged TX mbuf\n");
1014 if (ring->queued + ctx.nsegs >= NFE_TX_RING_COUNT - 1) {
1015 bus_dmamap_unload(ring->data_tag, map);
1020 /* setup h/w VLAN tagging */
1021 if ((m0->m_flags & (M_PROTO1 | M_PKTHDR)) == (M_PROTO1 | M_PKTHDR) &&
1022 m0->m_pkthdr.rcvif != NULL &&
1023 m0->m_pkthdr.rcvif->if_type == IFT_L2VLAN) {
1024 struct ifvlan *ifv = m0->m_pkthdr.rcvif->if_softc;
1027 vtag = NFE_TX_VTAG | htons(ifv->ifv_tag);
1031 if (m0->m_pkthdr.csum_flags & M_IPV4_CSUM_OUT)
1032 flags |= NFE_TX_IP_CSUM;
1033 if (m0->m_pkthdr.csum_flags & (M_TCPV4_CSUM_OUT | M_UDPV4_CSUM_OUT))
1034 flags |= NFE_TX_TCP_CSUM;
1038 * XXX urm. somebody is unaware of how hardware works. You
1039 * absolutely CANNOT set NFE_TX_VALID on the next descriptor in
1040 * the ring until the entire chain is actually *VALID*. Otherwise
1041 * the hardware may encounter a partially initialized chain that
1042 * is marked as being ready to go when it in fact is not ready to
1046 for (i = 0; i < ctx.nsegs; i++) {
1047 j = (ring->cur + i) % NFE_TX_RING_COUNT;
1048 data = &ring->data[j];
1050 if (sc->sc_flags & NFE_40BIT_ADDR) {
1051 desc64 = &ring->desc64[j];
1052 #if defined(__LP64__)
1053 desc64->physaddr[0] =
1054 htole32(segs[i].ds_addr >> 32);
1056 desc64->physaddr[1] =
1057 htole32(segs[i].ds_addr & 0xffffffff);
1058 desc64->length = htole16(segs[i].ds_len - 1);
1059 desc64->vtag = htole32(vtag);
1060 desc64->flags = htole16(flags);
1062 desc32 = &ring->desc32[j];
1063 desc32->physaddr = htole32(segs[i].ds_addr);
1064 desc32->length = htole16(segs[i].ds_len - 1);
1065 desc32->flags = htole16(flags);
1068 /* csum flags and vtag belong to the first fragment only */
1069 flags &= ~(NFE_TX_IP_CSUM | NFE_TX_TCP_CSUM);
1073 KKASSERT(ring->queued <= NFE_TX_RING_COUNT);
1076 /* the whole mbuf chain has been DMA mapped, fix last descriptor */
1077 if (sc->sc_flags & NFE_40BIT_ADDR) {
1078 desc64->flags |= htole16(NFE_TX_LASTFRAG_V2);
1080 if (sc->sc_flags & NFE_JUMBO_SUP)
1081 flags = NFE_TX_LASTFRAG_V2;
1083 flags = NFE_TX_LASTFRAG_V1;
1084 desc32->flags |= htole16(flags);
1088 * Set NFE_TX_VALID backwards so the hardware doesn't see the
1089 * whole mess until the first descriptor in the map is flagged.
1091 for (i = ctx.nsegs - 1; i >= 0; --i) {
1092 j = (ring->cur + i) % NFE_TX_RING_COUNT;
1093 if (sc->sc_flags & NFE_40BIT_ADDR) {
1094 desc64 = &ring->desc64[j];
1095 desc64->flags |= htole16(NFE_TX_VALID);
1097 desc32 = &ring->desc32[j];
1098 desc32->flags |= htole16(NFE_TX_VALID);
1101 ring->cur = (ring->cur + ctx.nsegs) % NFE_TX_RING_COUNT;
1103 /* Exchange DMA map */
1104 data_map->map = data->map;
1108 bus_dmamap_sync(ring->data_tag, map, BUS_DMASYNC_PREWRITE);
1116 nfe_start(struct ifnet *ifp)
1118 struct nfe_softc *sc = ifp->if_softc;
1119 struct nfe_tx_ring *ring = &sc->txq;
1123 if (ifp->if_flags & IFF_OACTIVE)
1126 if (ifq_is_empty(&ifp->if_snd))
1130 m0 = ifq_dequeue(&ifp->if_snd, NULL);
1136 if (nfe_encap(sc, ring, m0) != 0) {
1137 ifp->if_flags |= IFF_OACTIVE;
1144 * `m0' may be freed in nfe_encap(), so
1145 * it should not be touched any more.
1148 if (count == 0) /* nothing sent */
1151 /* Sync TX descriptor ring */
1152 bus_dmamap_sync(ring->tag, ring->map, BUS_DMASYNC_PREWRITE);
1155 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_KICKTX | sc->rxtxctl);
1158 * Set a timeout in case the chip goes out to lunch.
1164 nfe_watchdog(struct ifnet *ifp)
1166 struct nfe_softc *sc = ifp->if_softc;
1168 if (ifp->if_flags & IFF_RUNNING) {
1169 if_printf(ifp, "watchdog timeout - lost interrupt recovered\n");
1174 if_printf(ifp, "watchdog timeout\n");
1176 nfe_init(ifp->if_softc);
1180 if (!ifq_is_empty(&ifp->if_snd))
1187 struct nfe_softc *sc = xsc;
1188 struct ifnet *ifp = &sc->arpcom.ac_if;
1194 error = nfe_init_tx_ring(sc, &sc->txq);
1200 error = nfe_init_rx_ring(sc, &sc->rxq);
1206 NFE_WRITE(sc, NFE_TX_UNK, 0);
1207 NFE_WRITE(sc, NFE_STATUS, 0);
1209 sc->rxtxctl = NFE_RXTX_BIT2;
1210 if (sc->sc_flags & NFE_40BIT_ADDR)
1211 sc->rxtxctl |= NFE_RXTX_V3MAGIC;
1212 else if (sc->sc_flags & NFE_JUMBO_SUP)
1213 sc->rxtxctl |= NFE_RXTX_V2MAGIC;
1215 if (sc->sc_flags & NFE_HW_CSUM)
1216 sc->rxtxctl |= NFE_RXTX_RXCSUM;
1220 * Although the adapter is capable of stripping VLAN tags from received
1221 * frames (NFE_RXTX_VTAG_STRIP), we do not enable this functionality on
1222 * purpose. This will be done in software by our network stack.
1224 if (sc->sc_flags & NFE_HW_VLAN)
1225 sc->rxtxctl |= NFE_RXTX_VTAG_INSERT;
1227 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_RESET | sc->rxtxctl);
1229 NFE_WRITE(sc, NFE_RXTX_CTL, sc->rxtxctl);
1231 if (sc->sc_flags & NFE_HW_VLAN)
1232 NFE_WRITE(sc, NFE_VTAG_CTL, NFE_VTAG_ENABLE);
1234 NFE_WRITE(sc, NFE_SETUP_R6, 0);
1236 /* set MAC address */
1237 nfe_set_macaddr(sc, sc->arpcom.ac_enaddr);
1239 /* tell MAC where rings are in memory */
1241 NFE_WRITE(sc, NFE_RX_RING_ADDR_HI, sc->rxq.physaddr >> 32);
1243 NFE_WRITE(sc, NFE_RX_RING_ADDR_LO, sc->rxq.physaddr & 0xffffffff);
1245 NFE_WRITE(sc, NFE_TX_RING_ADDR_HI, sc->txq.physaddr >> 32);
1247 NFE_WRITE(sc, NFE_TX_RING_ADDR_LO, sc->txq.physaddr & 0xffffffff);
1249 NFE_WRITE(sc, NFE_RING_SIZE,
1250 (NFE_RX_RING_COUNT - 1) << 16 |
1251 (NFE_TX_RING_COUNT - 1));
1253 NFE_WRITE(sc, NFE_RXBUFSZ, sc->rxq.bufsz);
1255 /* force MAC to wakeup */
1256 tmp = NFE_READ(sc, NFE_PWR_STATE);
1257 NFE_WRITE(sc, NFE_PWR_STATE, tmp | NFE_PWR_WAKEUP);
1259 tmp = NFE_READ(sc, NFE_PWR_STATE);
1260 NFE_WRITE(sc, NFE_PWR_STATE, tmp | NFE_PWR_VALID);
1263 /* configure interrupts coalescing/mitigation */
1264 NFE_WRITE(sc, NFE_IMTIMER, NFE_IM_DEFAULT);
1266 /* no interrupt mitigation: one interrupt per packet */
1267 NFE_WRITE(sc, NFE_IMTIMER, 970);
1270 NFE_WRITE(sc, NFE_SETUP_R1, NFE_R1_MAGIC);
1271 NFE_WRITE(sc, NFE_SETUP_R2, NFE_R2_MAGIC);
1272 NFE_WRITE(sc, NFE_SETUP_R6, NFE_R6_MAGIC);
1274 /* update MAC knowledge of PHY; generates a NFE_IRQ_LINK interrupt */
1275 NFE_WRITE(sc, NFE_STATUS, sc->mii_phyaddr << 24 | NFE_STATUS_MAGIC);
1277 NFE_WRITE(sc, NFE_SETUP_R4, NFE_R4_MAGIC);
1278 NFE_WRITE(sc, NFE_WOL_CTL, NFE_WOL_MAGIC);
1280 sc->rxtxctl &= ~NFE_RXTX_BIT2;
1281 NFE_WRITE(sc, NFE_RXTX_CTL, sc->rxtxctl);
1283 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_BIT1 | sc->rxtxctl);
1288 nfe_ifmedia_upd(ifp);
1291 NFE_WRITE(sc, NFE_RX_CTL, NFE_RX_START);
1294 NFE_WRITE(sc, NFE_TX_CTL, NFE_TX_START);
1296 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf);
1298 #ifdef DEVICE_POLLING
1299 if ((ifp->if_flags & IFF_POLLING) == 0)
1301 /* enable interrupts */
1302 NFE_WRITE(sc, NFE_IRQ_MASK, NFE_IRQ_WANTED);
1304 callout_reset(&sc->sc_tick_ch, hz, nfe_tick, sc);
1306 ifp->if_flags |= IFF_RUNNING;
1307 ifp->if_flags &= ~IFF_OACTIVE;
1311 nfe_stop(struct nfe_softc *sc)
1313 struct ifnet *ifp = &sc->arpcom.ac_if;
1315 callout_stop(&sc->sc_tick_ch);
1318 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1321 NFE_WRITE(sc, NFE_TX_CTL, 0);
1324 NFE_WRITE(sc, NFE_RX_CTL, 0);
1326 /* Disable interrupts */
1327 NFE_WRITE(sc, NFE_IRQ_MASK, 0);
1329 /* Reset Tx and Rx rings */
1330 nfe_reset_tx_ring(sc, &sc->txq);
1331 nfe_reset_rx_ring(sc, &sc->rxq);
1335 nfe_alloc_rx_ring(struct nfe_softc *sc, struct nfe_rx_ring *ring)
1337 int i, j, error, descsize;
1340 if (sc->sc_flags & NFE_40BIT_ADDR) {
1341 desc = (void **)&ring->desc64;
1342 descsize = sizeof(struct nfe_desc64);
1344 desc = (void **)&ring->desc32;
1345 descsize = sizeof(struct nfe_desc32);
1348 ring->bufsz = MCLBYTES;
1349 ring->cur = ring->next = 0;
1351 error = bus_dma_tag_create(NULL, PAGE_SIZE, 0,
1352 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR,
1354 NFE_RX_RING_COUNT * descsize, 1,
1355 NFE_RX_RING_COUNT * descsize,
1358 if_printf(&sc->arpcom.ac_if,
1359 "could not create desc RX DMA tag\n");
1363 error = bus_dmamem_alloc(ring->tag, desc, BUS_DMA_WAITOK | BUS_DMA_ZERO,
1366 if_printf(&sc->arpcom.ac_if,
1367 "could not allocate RX desc DMA memory\n");
1368 bus_dma_tag_destroy(ring->tag);
1373 error = bus_dmamap_load(ring->tag, ring->map, *desc,
1374 NFE_RX_RING_COUNT * descsize,
1375 nfe_ring_dma_addr, &ring->physaddr,
1378 if_printf(&sc->arpcom.ac_if,
1379 "could not load RX desc DMA map\n");
1380 bus_dmamem_free(ring->tag, *desc, ring->map);
1381 bus_dma_tag_destroy(ring->tag);
1386 if (sc->sc_flags & NFE_USE_JUMBO) {
1387 ring->bufsz = NFE_JBYTES;
1389 error = nfe_jpool_alloc(sc, ring);
1391 if_printf(&sc->arpcom.ac_if,
1392 "could not allocate jumbo frames\n");
1397 error = bus_dma_tag_create(NULL, 1, 0,
1398 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR,
1400 MCLBYTES, 1, MCLBYTES,
1401 0, &ring->data_tag);
1403 if_printf(&sc->arpcom.ac_if,
1404 "could not create RX mbuf DMA tag\n");
1408 /* Create a spare RX mbuf DMA map */
1409 error = bus_dmamap_create(ring->data_tag, 0, &ring->data_tmpmap);
1411 if_printf(&sc->arpcom.ac_if,
1412 "could not create spare RX mbuf DMA map\n");
1413 bus_dma_tag_destroy(ring->data_tag);
1414 ring->data_tag = NULL;
1418 for (i = 0; i < NFE_RX_RING_COUNT; i++) {
1419 error = bus_dmamap_create(ring->data_tag, 0,
1420 &ring->data[i].map);
1422 if_printf(&sc->arpcom.ac_if,
1423 "could not create %dth RX mbuf DMA mapn", i);
1429 for (j = 0; j < i; ++j)
1430 bus_dmamap_destroy(ring->data_tag, ring->data[i].map);
1431 bus_dmamap_destroy(ring->data_tag, ring->data_tmpmap);
1432 bus_dma_tag_destroy(ring->data_tag);
1433 ring->data_tag = NULL;
1438 nfe_reset_rx_ring(struct nfe_softc *sc, struct nfe_rx_ring *ring)
1442 for (i = 0; i < NFE_RX_RING_COUNT; i++) {
1443 struct nfe_rx_data *data = &ring->data[i];
1445 if (data->m != NULL) {
1446 bus_dmamap_unload(ring->data_tag, data->map);
1451 bus_dmamap_sync(ring->tag, ring->map, BUS_DMASYNC_PREWRITE);
1453 ring->cur = ring->next = 0;
1457 nfe_init_rx_ring(struct nfe_softc *sc, struct nfe_rx_ring *ring)
1461 for (i = 0; i < NFE_RX_RING_COUNT; ++i) {
1464 /* XXX should use a function pointer */
1465 if (sc->sc_flags & NFE_USE_JUMBO)
1466 error = nfe_newbuf_jumbo(sc, ring, i, 1);
1468 error = nfe_newbuf_std(sc, ring, i, 1);
1470 if_printf(&sc->arpcom.ac_if,
1471 "could not allocate RX buffer\n");
1475 nfe_set_ready_rxdesc(sc, ring, i);
1477 bus_dmamap_sync(ring->tag, ring->map, BUS_DMASYNC_PREWRITE);
1483 nfe_free_rx_ring(struct nfe_softc *sc, struct nfe_rx_ring *ring)
1485 if (ring->data_tag != NULL) {
1486 struct nfe_rx_data *data;
1489 for (i = 0; i < NFE_RX_RING_COUNT; i++) {
1490 data = &ring->data[i];
1492 if (data->m != NULL) {
1493 bus_dmamap_unload(ring->data_tag, data->map);
1496 bus_dmamap_destroy(ring->data_tag, data->map);
1498 bus_dmamap_destroy(ring->data_tag, ring->data_tmpmap);
1499 bus_dma_tag_destroy(ring->data_tag);
1502 nfe_jpool_free(sc, ring);
1504 if (ring->tag != NULL) {
1507 if (sc->sc_flags & NFE_40BIT_ADDR)
1508 desc = ring->desc64;
1510 desc = ring->desc32;
1512 bus_dmamap_unload(ring->tag, ring->map);
1513 bus_dmamem_free(ring->tag, desc, ring->map);
1514 bus_dma_tag_destroy(ring->tag);
1518 static struct nfe_jbuf *
1519 nfe_jalloc(struct nfe_softc *sc)
1521 struct ifnet *ifp = &sc->arpcom.ac_if;
1522 struct nfe_jbuf *jbuf;
1524 lwkt_serialize_enter(&sc->sc_jbuf_serializer);
1526 jbuf = SLIST_FIRST(&sc->rxq.jfreelist);
1528 SLIST_REMOVE_HEAD(&sc->rxq.jfreelist, jnext);
1531 if_printf(ifp, "no free jumbo buffer\n");
1534 lwkt_serialize_exit(&sc->sc_jbuf_serializer);
1540 nfe_jfree(void *arg)
1542 struct nfe_jbuf *jbuf = arg;
1543 struct nfe_softc *sc = jbuf->sc;
1544 struct nfe_rx_ring *ring = jbuf->ring;
1546 if (&ring->jbuf[jbuf->slot] != jbuf)
1547 panic("%s: free wrong jumbo buffer\n", __func__);
1548 else if (jbuf->inuse == 0)
1549 panic("%s: jumbo buffer already freed\n", __func__);
1551 lwkt_serialize_enter(&sc->sc_jbuf_serializer);
1552 atomic_subtract_int(&jbuf->inuse, 1);
1553 if (jbuf->inuse == 0)
1554 SLIST_INSERT_HEAD(&ring->jfreelist, jbuf, jnext);
1555 lwkt_serialize_exit(&sc->sc_jbuf_serializer);
1561 struct nfe_jbuf *jbuf = arg;
1562 struct nfe_rx_ring *ring = jbuf->ring;
1564 if (&ring->jbuf[jbuf->slot] != jbuf)
1565 panic("%s: ref wrong jumbo buffer\n", __func__);
1566 else if (jbuf->inuse == 0)
1567 panic("%s: jumbo buffer already freed\n", __func__);
1569 atomic_add_int(&jbuf->inuse, 1);
1573 nfe_jpool_alloc(struct nfe_softc *sc, struct nfe_rx_ring *ring)
1575 struct nfe_jbuf *jbuf;
1576 bus_addr_t physaddr;
1581 * Allocate a big chunk of DMA'able memory.
1583 error = bus_dma_tag_create(NULL, PAGE_SIZE, 0,
1584 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR,
1586 NFE_JPOOL_SIZE, 1, NFE_JPOOL_SIZE,
1589 if_printf(&sc->arpcom.ac_if,
1590 "could not create jumbo DMA tag\n");
1594 error = bus_dmamem_alloc(ring->jtag, (void **)&ring->jpool,
1595 BUS_DMA_WAITOK, &ring->jmap);
1597 if_printf(&sc->arpcom.ac_if,
1598 "could not allocate jumbo DMA memory\n");
1599 bus_dma_tag_destroy(ring->jtag);
1604 error = bus_dmamap_load(ring->jtag, ring->jmap, ring->jpool,
1605 NFE_JPOOL_SIZE, nfe_ring_dma_addr, &physaddr,
1608 if_printf(&sc->arpcom.ac_if,
1609 "could not load jumbo DMA map\n");
1610 bus_dmamem_free(ring->jtag, ring->jpool, ring->jmap);
1611 bus_dma_tag_destroy(ring->jtag);
1616 /* ..and split it into 9KB chunks */
1617 SLIST_INIT(&ring->jfreelist);
1620 for (i = 0; i < NFE_JPOOL_COUNT; i++) {
1621 jbuf = &ring->jbuf[i];
1628 jbuf->physaddr = physaddr;
1630 SLIST_INSERT_HEAD(&ring->jfreelist, jbuf, jnext);
1633 physaddr += NFE_JBYTES;
1640 nfe_jpool_free(struct nfe_softc *sc, struct nfe_rx_ring *ring)
1642 if (ring->jtag != NULL) {
1643 bus_dmamap_unload(ring->jtag, ring->jmap);
1644 bus_dmamem_free(ring->jtag, ring->jpool, ring->jmap);
1645 bus_dma_tag_destroy(ring->jtag);
1650 nfe_alloc_tx_ring(struct nfe_softc *sc, struct nfe_tx_ring *ring)
1652 int i, j, error, descsize;
1655 if (sc->sc_flags & NFE_40BIT_ADDR) {
1656 desc = (void **)&ring->desc64;
1657 descsize = sizeof(struct nfe_desc64);
1659 desc = (void **)&ring->desc32;
1660 descsize = sizeof(struct nfe_desc32);
1664 ring->cur = ring->next = 0;
1666 error = bus_dma_tag_create(NULL, PAGE_SIZE, 0,
1667 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR,
1669 NFE_TX_RING_COUNT * descsize, 1,
1670 NFE_TX_RING_COUNT * descsize,
1673 if_printf(&sc->arpcom.ac_if,
1674 "could not create TX desc DMA map\n");
1678 error = bus_dmamem_alloc(ring->tag, desc, BUS_DMA_WAITOK | BUS_DMA_ZERO,
1681 if_printf(&sc->arpcom.ac_if,
1682 "could not allocate TX desc DMA memory\n");
1683 bus_dma_tag_destroy(ring->tag);
1688 error = bus_dmamap_load(ring->tag, ring->map, *desc,
1689 NFE_TX_RING_COUNT * descsize,
1690 nfe_ring_dma_addr, &ring->physaddr,
1693 if_printf(&sc->arpcom.ac_if,
1694 "could not load TX desc DMA map\n");
1695 bus_dmamem_free(ring->tag, *desc, ring->map);
1696 bus_dma_tag_destroy(ring->tag);
1701 error = bus_dma_tag_create(NULL, PAGE_SIZE, 0,
1702 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR,
1704 NFE_JBYTES * NFE_MAX_SCATTER,
1705 NFE_MAX_SCATTER, NFE_JBYTES,
1706 0, &ring->data_tag);
1708 if_printf(&sc->arpcom.ac_if,
1709 "could not create TX buf DMA tag\n");
1713 for (i = 0; i < NFE_TX_RING_COUNT; i++) {
1714 error = bus_dmamap_create(ring->data_tag, 0,
1715 &ring->data[i].map);
1717 if_printf(&sc->arpcom.ac_if,
1718 "could not create %dth TX buf DMA map\n", i);
1725 for (j = 0; j < i; ++j)
1726 bus_dmamap_destroy(ring->data_tag, ring->data[i].map);
1727 bus_dma_tag_destroy(ring->data_tag);
1728 ring->data_tag = NULL;
1733 nfe_reset_tx_ring(struct nfe_softc *sc, struct nfe_tx_ring *ring)
1737 for (i = 0; i < NFE_TX_RING_COUNT; i++) {
1738 struct nfe_tx_data *data = &ring->data[i];
1740 if (sc->sc_flags & NFE_40BIT_ADDR)
1741 ring->desc64[i].flags = 0;
1743 ring->desc32[i].flags = 0;
1745 if (data->m != NULL) {
1746 bus_dmamap_sync(ring->data_tag, data->map,
1747 BUS_DMASYNC_POSTWRITE);
1748 bus_dmamap_unload(ring->data_tag, data->map);
1753 bus_dmamap_sync(ring->tag, ring->map, BUS_DMASYNC_PREWRITE);
1756 ring->cur = ring->next = 0;
1760 nfe_init_tx_ring(struct nfe_softc *sc __unused,
1761 struct nfe_tx_ring *ring __unused)
1767 nfe_free_tx_ring(struct nfe_softc *sc, struct nfe_tx_ring *ring)
1769 if (ring->data_tag != NULL) {
1770 struct nfe_tx_data *data;
1773 for (i = 0; i < NFE_TX_RING_COUNT; ++i) {
1774 data = &ring->data[i];
1776 if (data->m != NULL) {
1777 bus_dmamap_unload(ring->data_tag, data->map);
1780 bus_dmamap_destroy(ring->data_tag, data->map);
1783 bus_dma_tag_destroy(ring->data_tag);
1786 if (ring->tag != NULL) {
1789 if (sc->sc_flags & NFE_40BIT_ADDR)
1790 desc = ring->desc64;
1792 desc = ring->desc32;
1794 bus_dmamap_unload(ring->tag, ring->map);
1795 bus_dmamem_free(ring->tag, desc, ring->map);
1796 bus_dma_tag_destroy(ring->tag);
1801 nfe_ifmedia_upd(struct ifnet *ifp)
1803 struct nfe_softc *sc = ifp->if_softc;
1804 struct mii_data *mii = device_get_softc(sc->sc_miibus);
1806 if (mii->mii_instance != 0) {
1807 struct mii_softc *miisc;
1809 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
1810 mii_phy_reset(miisc);
1818 nfe_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
1820 struct nfe_softc *sc = ifp->if_softc;
1821 struct mii_data *mii = device_get_softc(sc->sc_miibus);
1824 ifmr->ifm_status = mii->mii_media_status;
1825 ifmr->ifm_active = mii->mii_media_active;
1829 nfe_setmulti(struct nfe_softc *sc)
1831 struct ifnet *ifp = &sc->arpcom.ac_if;
1832 struct ifmultiaddr *ifma;
1833 uint8_t addr[ETHER_ADDR_LEN], mask[ETHER_ADDR_LEN];
1834 uint32_t filter = NFE_RXFILTER_MAGIC;
1837 if ((ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) != 0) {
1838 bzero(addr, ETHER_ADDR_LEN);
1839 bzero(mask, ETHER_ADDR_LEN);
1843 bcopy(etherbroadcastaddr, addr, ETHER_ADDR_LEN);
1844 bcopy(etherbroadcastaddr, mask, ETHER_ADDR_LEN);
1846 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1849 if (ifma->ifma_addr->sa_family != AF_LINK)
1852 maddr = LLADDR((struct sockaddr_dl *)ifma->ifma_addr);
1853 for (i = 0; i < ETHER_ADDR_LEN; i++) {
1854 addr[i] &= maddr[i];
1855 mask[i] &= ~maddr[i];
1859 for (i = 0; i < ETHER_ADDR_LEN; i++)
1863 addr[0] |= 0x01; /* make sure multicast bit is set */
1865 NFE_WRITE(sc, NFE_MULTIADDR_HI,
1866 addr[3] << 24 | addr[2] << 16 | addr[1] << 8 | addr[0]);
1867 NFE_WRITE(sc, NFE_MULTIADDR_LO,
1868 addr[5] << 8 | addr[4]);
1869 NFE_WRITE(sc, NFE_MULTIMASK_HI,
1870 mask[3] << 24 | mask[2] << 16 | mask[1] << 8 | mask[0]);
1871 NFE_WRITE(sc, NFE_MULTIMASK_LO,
1872 mask[5] << 8 | mask[4]);
1874 filter |= (ifp->if_flags & IFF_PROMISC) ? NFE_PROMISC : NFE_U2M;
1875 NFE_WRITE(sc, NFE_RXFILTER, filter);
1879 nfe_get_macaddr(struct nfe_softc *sc, uint8_t *addr)
1883 tmp = NFE_READ(sc, NFE_MACADDR_LO);
1884 addr[0] = (tmp >> 8) & 0xff;
1885 addr[1] = (tmp & 0xff);
1887 tmp = NFE_READ(sc, NFE_MACADDR_HI);
1888 addr[2] = (tmp >> 24) & 0xff;
1889 addr[3] = (tmp >> 16) & 0xff;
1890 addr[4] = (tmp >> 8) & 0xff;
1891 addr[5] = (tmp & 0xff);
1895 nfe_set_macaddr(struct nfe_softc *sc, const uint8_t *addr)
1897 NFE_WRITE(sc, NFE_MACADDR_LO,
1898 addr[5] << 8 | addr[4]);
1899 NFE_WRITE(sc, NFE_MACADDR_HI,
1900 addr[3] << 24 | addr[2] << 16 | addr[1] << 8 | addr[0]);
1906 struct nfe_softc *sc = arg;
1907 struct ifnet *ifp = &sc->arpcom.ac_if;
1908 struct mii_data *mii = device_get_softc(sc->sc_miibus);
1910 lwkt_serialize_enter(ifp->if_serializer);
1913 callout_reset(&sc->sc_tick_ch, hz, nfe_tick, sc);
1915 lwkt_serialize_exit(ifp->if_serializer);
1919 nfe_ring_dma_addr(void *arg, bus_dma_segment_t *seg, int nseg, int error)
1924 KASSERT(nseg == 1, ("too many segments, should be 1\n"));
1926 *((uint32_t *)arg) = seg->ds_addr;
1930 nfe_buf_dma_addr(void *arg, bus_dma_segment_t *segs, int nsegs,
1931 bus_size_t mapsz __unused, int error)
1933 struct nfe_dma_ctx *ctx = arg;
1939 KASSERT(nsegs <= ctx->nsegs,
1940 ("too many segments(%d), should be <= %d\n",
1941 nsegs, ctx->nsegs));
1944 for (i = 0; i < nsegs; ++i)
1945 ctx->segs[i] = segs[i];
1949 nfe_newbuf_std(struct nfe_softc *sc, struct nfe_rx_ring *ring, int idx,
1952 struct nfe_rx_data *data = &ring->data[idx];
1953 struct nfe_dma_ctx ctx;
1954 bus_dma_segment_t seg;
1959 m = m_getcl(wait ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR);
1962 m->m_len = m->m_pkthdr.len = MCLBYTES;
1966 error = bus_dmamap_load_mbuf(ring->data_tag, ring->data_tmpmap,
1967 m, nfe_buf_dma_addr, &ctx,
1968 wait ? BUS_DMA_WAITOK : BUS_DMA_NOWAIT);
1971 if_printf(&sc->arpcom.ac_if, "could map RX mbuf %d\n", error);
1975 /* Unload originally mapped mbuf */
1976 bus_dmamap_unload(ring->data_tag, data->map);
1978 /* Swap this DMA map with tmp DMA map */
1980 data->map = ring->data_tmpmap;
1981 ring->data_tmpmap = map;
1983 /* Caller is assumed to have collected the old mbuf */
1986 nfe_set_paddr_rxdesc(sc, ring, idx, seg.ds_addr);
1988 bus_dmamap_sync(ring->data_tag, data->map, BUS_DMASYNC_PREREAD);
1993 nfe_newbuf_jumbo(struct nfe_softc *sc, struct nfe_rx_ring *ring, int idx,
1996 struct nfe_rx_data *data = &ring->data[idx];
1997 struct nfe_jbuf *jbuf;
2000 MGETHDR(m, wait ? MB_WAIT : MB_DONTWAIT, MT_DATA);
2004 jbuf = nfe_jalloc(sc);
2007 if_printf(&sc->arpcom.ac_if, "jumbo allocation failed "
2008 "-- packet dropped!\n");
2012 m->m_ext.ext_arg = jbuf;
2013 m->m_ext.ext_buf = jbuf->buf;
2014 m->m_ext.ext_free = nfe_jfree;
2015 m->m_ext.ext_ref = nfe_jref;
2016 m->m_ext.ext_size = NFE_JBYTES;
2018 m->m_data = m->m_ext.ext_buf;
2019 m->m_flags |= M_EXT;
2020 m->m_len = m->m_pkthdr.len = m->m_ext.ext_size;
2022 /* Caller is assumed to have collected the old mbuf */
2025 nfe_set_paddr_rxdesc(sc, ring, idx, jbuf->physaddr);
2027 bus_dmamap_sync(ring->jtag, ring->jmap, BUS_DMASYNC_PREREAD);
2032 nfe_set_paddr_rxdesc(struct nfe_softc *sc, struct nfe_rx_ring *ring, int idx,
2033 bus_addr_t physaddr)
2035 if (sc->sc_flags & NFE_40BIT_ADDR) {
2036 struct nfe_desc64 *desc64 = &ring->desc64[idx];
2038 #if defined(__LP64__)
2039 desc64->physaddr[0] = htole32(physaddr >> 32);
2041 desc64->physaddr[1] = htole32(physaddr & 0xffffffff);
2043 struct nfe_desc32 *desc32 = &ring->desc32[idx];
2045 desc32->physaddr = htole32(physaddr);
2050 nfe_set_ready_rxdesc(struct nfe_softc *sc, struct nfe_rx_ring *ring, int idx)
2052 if (sc->sc_flags & NFE_40BIT_ADDR) {
2053 struct nfe_desc64 *desc64 = &ring->desc64[idx];
2055 desc64->length = htole16(ring->bufsz);
2056 desc64->flags = htole16(NFE_RX_READY);
2058 struct nfe_desc32 *desc32 = &ring->desc32[idx];
2060 desc32->length = htole16(ring->bufsz);
2061 desc32->flags = htole16(NFE_RX_READY);