2 * Copyright (c) 2000 Berkeley Software Design, Inc.
3 * Copyright (c) 1997, 1998, 1999, 2000
4 * Bill Paul <wpaul@osd.bsdi.com>. All rights reserved.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. All advertising materials mentioning features or use of this software
15 * must display the following acknowledgement:
16 * This product includes software developed by Bill Paul.
17 * 4. Neither the name of the author nor the names of any co-contributors
18 * may be used to endorse or promote products derived from this software
19 * without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
31 * THE POSSIBILITY OF SUCH DAMAGE.
33 * $FreeBSD: src/sys/pci/if_pcn.c,v 1.5.2.10 2003/03/05 18:42:33 njl Exp $
34 * $DragonFly: src/sys/dev/netif/pcn/if_pcn.c,v 1.19 2005/05/24 20:59:02 dillon Exp $
38 * AMD Am79c972 fast ethernet PCI NIC driver. Datatheets are available
39 * from http://www.amd.com.
41 * Written by Bill Paul <wpaul@osd.bsdi.com>
45 * The AMD PCnet/PCI controllers are more advanced and functional
46 * versions of the venerable 7990 LANCE. The PCnet/PCI chips retain
47 * backwards compatibility with the LANCE and thus can be made
48 * to work with older LANCE drivers. This is in fact how the
49 * PCnet/PCI chips were supported in FreeBSD originally. The trouble
50 * is that the PCnet/PCI devices offer several performance enhancements
51 * which can't be exploited in LANCE compatibility mode. Chief among
52 * these enhancements is the ability to perform PCI DMA operations
53 * using 32-bit addressing (which eliminates the need for ISA
54 * bounce-buffering), and special receive buffer alignment (which
55 * allows the receive handler to pass packets to the upper protocol
56 * layers without copying on both the x86 and alpha platforms).
59 #include <sys/param.h>
60 #include <sys/systm.h>
61 #include <sys/sockio.h>
63 #include <sys/malloc.h>
64 #include <sys/kernel.h>
65 #include <sys/socket.h>
68 #include <net/ifq_var.h>
69 #include <net/if_arp.h>
70 #include <net/ethernet.h>
71 #include <net/if_dl.h>
72 #include <net/if_media.h>
76 #include <vm/vm.h> /* for vtophys */
77 #include <vm/pmap.h> /* for vtophys */
78 #include <machine/clock.h> /* for DELAY */
79 #include <machine/bus_pio.h>
80 #include <machine/bus_memio.h>
81 #include <machine/bus.h>
82 #include <machine/resource.h>
86 #include "../mii_layer/mii.h"
87 #include "../mii_layer/miivar.h"
89 #include <bus/pci/pcireg.h>
90 #include <bus/pci/pcivar.h>
92 #define PCN_USEIOSPACE
94 #include "if_pcnreg.h"
96 /* "controller miibus0" required. See GENERIC if you get errors here. */
97 #include "miibus_if.h"
100 * Various supported device vendors/types and their names.
102 static struct pcn_type pcn_devs[] = {
103 { PCN_VENDORID, PCN_DEVICEID_PCNET, "AMD PCnet/PCI 10/100BaseTX" },
104 { PCN_VENDORID, PCN_DEVICEID_HOME, "AMD PCnet/Home HomePNA" },
108 static u_int32_t pcn_csr_read (struct pcn_softc *, int);
109 static u_int16_t pcn_csr_read16 (struct pcn_softc *, int);
110 static u_int16_t pcn_bcr_read16 (struct pcn_softc *, int);
111 static void pcn_csr_write (struct pcn_softc *, int, int);
112 static u_int32_t pcn_bcr_read (struct pcn_softc *, int);
113 static void pcn_bcr_write (struct pcn_softc *, int, int);
115 static int pcn_probe (device_t);
116 static int pcn_attach (device_t);
117 static int pcn_detach (device_t);
119 static int pcn_newbuf (struct pcn_softc *, int, struct mbuf *);
120 static int pcn_encap (struct pcn_softc *,
121 struct mbuf *, u_int32_t *);
122 static void pcn_rxeof (struct pcn_softc *);
123 static void pcn_txeof (struct pcn_softc *);
124 static void pcn_intr (void *);
125 static void pcn_tick (void *);
126 static void pcn_start (struct ifnet *);
127 static int pcn_ioctl (struct ifnet *, u_long, caddr_t,
129 static void pcn_init (void *);
130 static void pcn_stop (struct pcn_softc *);
131 static void pcn_watchdog (struct ifnet *);
132 static void pcn_shutdown (device_t);
133 static int pcn_ifmedia_upd (struct ifnet *);
134 static void pcn_ifmedia_sts (struct ifnet *, struct ifmediareq *);
136 static int pcn_miibus_readreg (device_t, int, int);
137 static int pcn_miibus_writereg (device_t, int, int, int);
138 static void pcn_miibus_statchg (device_t);
140 static void pcn_setfilt (struct ifnet *);
141 static void pcn_setmulti (struct pcn_softc *);
142 static u_int32_t pcn_crc (caddr_t);
143 static void pcn_reset (struct pcn_softc *);
144 static int pcn_list_rx_init (struct pcn_softc *);
145 static int pcn_list_tx_init (struct pcn_softc *);
147 #ifdef PCN_USEIOSPACE
148 #define PCN_RES SYS_RES_IOPORT
149 #define PCN_RID PCN_PCI_LOIO
151 #define PCN_RES SYS_RES_MEMORY
152 #define PCN_RID PCN_PCI_LOMEM
155 static device_method_t pcn_methods[] = {
156 /* Device interface */
157 DEVMETHOD(device_probe, pcn_probe),
158 DEVMETHOD(device_attach, pcn_attach),
159 DEVMETHOD(device_detach, pcn_detach),
160 DEVMETHOD(device_shutdown, pcn_shutdown),
163 DEVMETHOD(bus_print_child, bus_generic_print_child),
164 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
167 DEVMETHOD(miibus_readreg, pcn_miibus_readreg),
168 DEVMETHOD(miibus_writereg, pcn_miibus_writereg),
169 DEVMETHOD(miibus_statchg, pcn_miibus_statchg),
174 static driver_t pcn_driver = {
177 sizeof(struct pcn_softc)
180 static devclass_t pcn_devclass;
182 DECLARE_DUMMY_MODULE(if_pcn);
183 DRIVER_MODULE(if_pcn, pci, pcn_driver, pcn_devclass, 0, 0);
184 DRIVER_MODULE(miibus, pcn, miibus_driver, miibus_devclass, 0, 0);
186 #define PCN_CSR_SETBIT(sc, reg, x) \
187 pcn_csr_write(sc, reg, pcn_csr_read(sc, reg) | (x))
189 #define PCN_CSR_CLRBIT(sc, reg, x) \
190 pcn_csr_write(sc, reg, pcn_csr_read(sc, reg) & ~(x))
192 #define PCN_BCR_SETBIT(sc, reg, x) \
193 pcn_bcr_write(sc, reg, pcn_bcr_read(sc, reg) | (x))
195 #define PCN_BCR_CLRBIT(sc, reg, x) \
196 pcn_bcr_write(sc, reg, pcn_bcr_read(sc, reg) & ~(x))
198 static u_int32_t pcn_csr_read(sc, reg)
199 struct pcn_softc *sc;
202 CSR_WRITE_4(sc, PCN_IO32_RAP, reg);
203 return(CSR_READ_4(sc, PCN_IO32_RDP));
206 static u_int16_t pcn_csr_read16(sc, reg)
207 struct pcn_softc *sc;
210 CSR_WRITE_2(sc, PCN_IO16_RAP, reg);
211 return(CSR_READ_2(sc, PCN_IO16_RDP));
214 static void pcn_csr_write(sc, reg, val)
215 struct pcn_softc *sc;
218 CSR_WRITE_4(sc, PCN_IO32_RAP, reg);
219 CSR_WRITE_4(sc, PCN_IO32_RDP, val);
223 static u_int32_t pcn_bcr_read(sc, reg)
224 struct pcn_softc *sc;
227 CSR_WRITE_4(sc, PCN_IO32_RAP, reg);
228 return(CSR_READ_4(sc, PCN_IO32_BDP));
231 static u_int16_t pcn_bcr_read16(sc, reg)
232 struct pcn_softc *sc;
235 CSR_WRITE_2(sc, PCN_IO16_RAP, reg);
236 return(CSR_READ_2(sc, PCN_IO16_BDP));
239 static void pcn_bcr_write(sc, reg, val)
240 struct pcn_softc *sc;
243 CSR_WRITE_4(sc, PCN_IO32_RAP, reg);
244 CSR_WRITE_4(sc, PCN_IO32_BDP, val);
248 static int pcn_miibus_readreg(dev, phy, reg)
252 struct pcn_softc *sc;
255 sc = device_get_softc(dev);
257 if (sc->pcn_phyaddr && phy > sc->pcn_phyaddr)
260 pcn_bcr_write(sc, PCN_BCR_MIIADDR, reg | (phy << 5));
261 val = pcn_bcr_read(sc, PCN_BCR_MIIDATA) & 0xFFFF;
265 sc->pcn_phyaddr = phy;
270 static int pcn_miibus_writereg(dev, phy, reg, data)
274 struct pcn_softc *sc;
276 sc = device_get_softc(dev);
278 pcn_bcr_write(sc, PCN_BCR_MIIADDR, reg | (phy << 5));
279 pcn_bcr_write(sc, PCN_BCR_MIIDATA, data);
284 static void pcn_miibus_statchg(dev)
287 struct pcn_softc *sc;
288 struct mii_data *mii;
290 sc = device_get_softc(dev);
291 mii = device_get_softc(sc->pcn_miibus);
293 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
294 PCN_BCR_SETBIT(sc, PCN_BCR_DUPLEX, PCN_DUPLEX_FDEN);
296 PCN_BCR_CLRBIT(sc, PCN_BCR_DUPLEX, PCN_DUPLEX_FDEN);
302 #define DC_POLY 0xEDB88320
304 static u_int32_t pcn_crc(addr)
307 u_int32_t idx, bit, data, crc;
309 /* Compute CRC for the address value. */
310 crc = 0xFFFFFFFF; /* initial value */
312 for (idx = 0; idx < 6; idx++) {
313 for (data = *addr++, bit = 0; bit < 8; bit++, data >>= 1)
314 crc = (crc >> 1) ^ (((crc ^ data) & 1) ? DC_POLY : 0);
317 return ((crc >> 26) & 0x3F);
320 static void pcn_setmulti(sc)
321 struct pcn_softc *sc;
324 struct ifmultiaddr *ifma;
326 u_int16_t hashes[4] = { 0, 0, 0, 0 };
328 ifp = &sc->arpcom.ac_if;
330 PCN_CSR_SETBIT(sc, PCN_CSR_EXTCTL1, PCN_EXTCTL1_SPND);
332 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
333 for (i = 0; i < 4; i++)
334 pcn_csr_write(sc, PCN_CSR_MAR0 + i, 0xFFFF);
335 PCN_CSR_CLRBIT(sc, PCN_CSR_EXTCTL1, PCN_EXTCTL1_SPND);
339 /* first, zot all the existing hash bits */
340 for (i = 0; i < 4; i++)
341 pcn_csr_write(sc, PCN_CSR_MAR0 + i, 0);
343 /* now program new ones */
344 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL;
345 ifma = ifma->ifma_link.le_next) {
346 if (ifma->ifma_addr->sa_family != AF_LINK)
348 h = pcn_crc(LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
349 hashes[h >> 4] |= 1 << (h & 0xF);
352 for (i = 0; i < 4; i++)
353 pcn_csr_write(sc, PCN_CSR_MAR0 + i, hashes[i]);
355 PCN_CSR_CLRBIT(sc, PCN_CSR_EXTCTL1, PCN_EXTCTL1_SPND);
360 static void pcn_reset(sc)
361 struct pcn_softc *sc;
364 * Issue a reset by reading from the RESET register.
365 * Note that we don't know if the chip is operating in
366 * 16-bit or 32-bit mode at this point, so we attempt
367 * to reset the chip both ways. If one fails, the other
370 CSR_READ_2(sc, PCN_IO16_RESET);
371 CSR_READ_4(sc, PCN_IO32_RESET);
373 /* Wait a little while for the chip to get its brains in order. */
376 /* Select 32-bit (DWIO) mode */
377 CSR_WRITE_4(sc, PCN_IO32_RDP, 0);
379 /* Select software style 3. */
380 pcn_bcr_write(sc, PCN_BCR_SSTYLE, PCN_SWSTYLE_PCNETPCI_BURST);
386 * Probe for an AMD chip. Check the PCI vendor and device
387 * IDs against our list and return a device name if we find a match.
389 static int pcn_probe(dev)
393 struct pcn_softc *sc;
398 sc = device_get_softc(dev);
400 while(t->pcn_name != NULL) {
401 if ((pci_get_vendor(dev) == t->pcn_vid) &&
402 (pci_get_device(dev) == t->pcn_did)) {
404 * Temporarily map the I/O space
405 * so we can read the chip ID register.
408 sc->pcn_res = bus_alloc_resource_any(dev, PCN_RES,
410 if (sc->pcn_res == NULL) {
412 "couldn't map ports/memory\n");
415 sc->pcn_btag = rman_get_bustag(sc->pcn_res);
416 sc->pcn_bhandle = rman_get_bushandle(sc->pcn_res);
418 * Note: we can *NOT* put the chip into
419 * 32-bit mode yet. The lnc driver will only
420 * work in 16-bit mode, and once the chip
421 * goes into 32-bit mode, the only way to
422 * get it out again is with a hardware reset.
423 * So if pcn_probe() is called before the
424 * lnc driver's probe routine, the chip will
425 * be locked into 32-bit operation and the lnc
426 * driver will be unable to attach to it.
427 * Note II: if the chip happens to already
428 * be in 32-bit mode, we still need to check
429 * the chip ID, but first we have to detect
430 * 32-bit mode using only 16-bit operations.
431 * The safest way to do this is to read the
432 * PCI subsystem ID from BCR23/24 and compare
433 * that with the value read from PCI config
436 chip_id = pcn_bcr_read16(sc, PCN_BCR_PCISUBSYSID);
438 chip_id |= pcn_bcr_read16(sc, PCN_BCR_PCISUBVENID);
440 * Note III: the test for 0x10001000 is a hack to
441 * pacify VMware, who's pseudo-PCnet interface is
442 * broken. Reading the subsystem register from PCI
443 * config space yeilds 0x00000000 while reading the
444 * same value from I/O space yeilds 0x10001000. It's
445 * not supposed to be that way.
447 if (chip_id == pci_read_config(dev,
448 PCIR_SUBVEND_0, 4) || chip_id == 0x10001000) {
449 /* We're in 16-bit mode. */
450 chip_id = pcn_csr_read16(sc, PCN_CSR_CHIPID1);
452 chip_id |= pcn_csr_read16(sc, PCN_CSR_CHIPID0);
454 /* We're in 32-bit mode. */
455 chip_id = pcn_csr_read(sc, PCN_CSR_CHIPID1);
457 chip_id |= pcn_csr_read(sc, PCN_CSR_CHIPID0);
459 bus_release_resource(dev, PCN_RES,
460 PCN_RID, sc->pcn_res);
462 sc->pcn_type = chip_id & PART_MASK;
463 switch(sc->pcn_type) {
475 device_set_desc(dev, t->pcn_name);
485 * Attach the interface. Allocate softc structures, do ifmedia
486 * setup and ethernet/BPF attach.
488 static int pcn_attach(dev)
492 uint8_t eaddr[ETHER_ADDR_LEN];
494 struct pcn_softc *sc;
496 int unit, error = 0, rid;
500 sc = device_get_softc(dev);
501 unit = device_get_unit(dev);
504 * Handle power management nonsense.
507 command = pci_read_config(dev, PCN_PCI_CAPID, 4) & 0x000000FF;
508 if (command == 0x01) {
510 command = pci_read_config(dev, PCN_PCI_PWRMGMTCTRL, 4);
511 if (command & PCN_PSTATE_MASK) {
512 u_int32_t iobase, membase, irq;
514 /* Save important PCI config data. */
515 iobase = pci_read_config(dev, PCN_PCI_LOIO, 4);
516 membase = pci_read_config(dev, PCN_PCI_LOMEM, 4);
517 irq = pci_read_config(dev, PCN_PCI_INTLINE, 4);
519 /* Reset the power state. */
520 printf("pcn%d: chip is in D%d power mode "
521 "-- setting to D0\n", unit, command & PCN_PSTATE_MASK);
522 command &= 0xFFFFFFFC;
523 pci_write_config(dev, PCN_PCI_PWRMGMTCTRL, command, 4);
525 /* Restore PCI config data. */
526 pci_write_config(dev, PCN_PCI_LOIO, iobase, 4);
527 pci_write_config(dev, PCN_PCI_LOMEM, membase, 4);
528 pci_write_config(dev, PCN_PCI_INTLINE, irq, 4);
533 * Map control/status registers.
535 command = pci_read_config(dev, PCIR_COMMAND, 4);
536 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN);
537 pci_write_config(dev, PCIR_COMMAND, command, 4);
538 command = pci_read_config(dev, PCIR_COMMAND, 4);
540 #ifdef PCN_USEIOSPACE
541 if (!(command & PCIM_CMD_PORTEN)) {
542 printf("pcn%d: failed to enable I/O ports!\n", unit);
547 if (!(command & PCIM_CMD_MEMEN)) {
548 printf("pcn%d: failed to enable memory mapping!\n", unit);
555 sc->pcn_res = bus_alloc_resource_any(dev, PCN_RES, &rid, RF_ACTIVE);
557 if (sc->pcn_res == NULL) {
558 printf("pcn%d: couldn't map ports/memory\n", unit);
563 sc->pcn_btag = rman_get_bustag(sc->pcn_res);
564 sc->pcn_bhandle = rman_get_bushandle(sc->pcn_res);
566 /* Allocate interrupt */
568 sc->pcn_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
569 RF_SHAREABLE | RF_ACTIVE);
571 if (sc->pcn_irq == NULL) {
572 printf("pcn%d: couldn't map interrupt\n", unit);
573 bus_release_resource(dev, PCN_RES, PCN_RID, sc->pcn_res);
578 error = bus_setup_intr(dev, sc->pcn_irq, INTR_TYPE_NET,
579 pcn_intr, sc, &sc->pcn_intrhand, NULL);
582 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->pcn_res);
583 bus_release_resource(dev, PCN_RES, PCN_RID, sc->pcn_res);
584 printf("pcn%d: couldn't set up irq\n", unit);
588 /* Reset the adapter. */
592 * Get station address from the EEPROM.
594 *(uint32_t *)eaddr = CSR_READ_4(sc, PCN_IO32_APROM00);
595 *(uint16_t *)(eaddr + 4) = CSR_READ_2(sc, PCN_IO32_APROM01);
598 callout_init(&sc->pcn_stat_timer);
600 sc->pcn_ldata = contigmalloc(sizeof(struct pcn_list_data), M_DEVBUF,
601 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
603 if (sc->pcn_ldata == NULL) {
604 printf("pcn%d: no memory for list buffers!\n", unit);
605 bus_teardown_intr(dev, sc->pcn_irq, sc->pcn_intrhand);
606 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->pcn_irq);
607 bus_release_resource(dev, PCN_RES, PCN_RID, sc->pcn_res);
611 bzero(sc->pcn_ldata, sizeof(struct pcn_list_data));
613 ifp = &sc->arpcom.ac_if;
615 if_initname(ifp, "pcn", unit);
616 ifp->if_mtu = ETHERMTU;
617 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
618 ifp->if_ioctl = pcn_ioctl;
619 ifp->if_start = pcn_start;
620 ifp->if_watchdog = pcn_watchdog;
621 ifp->if_init = pcn_init;
622 ifp->if_baudrate = 10000000;
623 ifq_set_maxlen(&ifp->if_snd, PCN_TX_LIST_CNT - 1);
624 ifq_set_ready(&ifp->if_snd);
629 if (mii_phy_probe(dev, &sc->pcn_miibus,
630 pcn_ifmedia_upd, pcn_ifmedia_sts)) {
631 printf("pcn%d: MII without any PHY!\n", sc->pcn_unit);
632 contigfree(sc->pcn_ldata, sizeof(struct pcn_list_data),
634 bus_teardown_intr(dev, sc->pcn_irq, sc->pcn_intrhand);
635 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->pcn_irq);
636 bus_release_resource(dev, PCN_RES, PCN_RID, sc->pcn_res);
642 * Call MI attach routine.
644 ether_ifattach(ifp, eaddr);
651 static int pcn_detach(dev)
654 struct pcn_softc *sc;
660 sc = device_get_softc(dev);
661 ifp = &sc->arpcom.ac_if;
667 if (sc->pcn_miibus != NULL) {
668 bus_generic_detach(dev);
669 device_delete_child(dev, sc->pcn_miibus);
672 bus_teardown_intr(dev, sc->pcn_irq, sc->pcn_intrhand);
673 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->pcn_irq);
674 bus_release_resource(dev, PCN_RES, PCN_RID, sc->pcn_res);
676 contigfree(sc->pcn_ldata, sizeof(struct pcn_list_data), M_DEVBUF);
684 * Initialize the transmit descriptors.
686 static int pcn_list_tx_init(sc)
687 struct pcn_softc *sc;
689 struct pcn_list_data *ld;
690 struct pcn_ring_data *cd;
696 for (i = 0; i < PCN_TX_LIST_CNT; i++) {
697 cd->pcn_tx_chain[i] = NULL;
698 ld->pcn_tx_list[i].pcn_tbaddr = 0;
699 ld->pcn_tx_list[i].pcn_txctl = 0;
700 ld->pcn_tx_list[i].pcn_txstat = 0;
703 cd->pcn_tx_prod = cd->pcn_tx_cons = cd->pcn_tx_cnt = 0;
710 * Initialize the RX descriptors and allocate mbufs for them.
712 static int pcn_list_rx_init(sc)
713 struct pcn_softc *sc;
715 struct pcn_list_data *ld;
716 struct pcn_ring_data *cd;
722 for (i = 0; i < PCN_RX_LIST_CNT; i++) {
723 if (pcn_newbuf(sc, i, NULL) == ENOBUFS)
733 * Initialize an RX descriptor and attach an MBUF cluster.
735 static int pcn_newbuf(sc, idx, m)
736 struct pcn_softc *sc;
740 struct mbuf *m_new = NULL;
741 struct pcn_rx_desc *c;
743 c = &sc->pcn_ldata->pcn_rx_list[idx];
746 MGETHDR(m_new, MB_DONTWAIT, MT_DATA);
750 MCLGET(m_new, MB_DONTWAIT);
751 if (!(m_new->m_flags & M_EXT)) {
755 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
758 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
759 m_new->m_data = m_new->m_ext.ext_buf;
762 m_adj(m_new, ETHER_ALIGN);
764 sc->pcn_cdata.pcn_rx_chain[idx] = m_new;
765 c->pcn_rbaddr = vtophys(mtod(m_new, caddr_t));
766 c->pcn_bufsz = (~(PCN_RXLEN) + 1) & PCN_RXLEN_BUFSZ;
767 c->pcn_bufsz |= PCN_RXLEN_MBO;
768 c->pcn_rxstat = PCN_RXSTAT_STP|PCN_RXSTAT_ENP|PCN_RXSTAT_OWN;
774 * A frame has been uploaded: pass the resulting mbuf chain up to
775 * the higher level protocols.
777 static void pcn_rxeof(sc)
778 struct pcn_softc *sc;
782 struct pcn_rx_desc *cur_rx;
785 ifp = &sc->arpcom.ac_if;
786 i = sc->pcn_cdata.pcn_rx_prod;
788 while(PCN_OWN_RXDESC(&sc->pcn_ldata->pcn_rx_list[i])) {
789 cur_rx = &sc->pcn_ldata->pcn_rx_list[i];
790 m = sc->pcn_cdata.pcn_rx_chain[i];
791 sc->pcn_cdata.pcn_rx_chain[i] = NULL;
794 * If an error occurs, update stats, clear the
795 * status word and leave the mbuf cluster in place:
796 * it should simply get re-used next time this descriptor
797 * comes up in the ring.
799 if (cur_rx->pcn_rxstat & PCN_RXSTAT_ERR) {
801 pcn_newbuf(sc, i, m);
802 PCN_INC(i, PCN_RX_LIST_CNT);
806 if (pcn_newbuf(sc, i, NULL)) {
807 /* Ran out of mbufs; recycle this one. */
808 pcn_newbuf(sc, i, m);
810 PCN_INC(i, PCN_RX_LIST_CNT);
814 PCN_INC(i, PCN_RX_LIST_CNT);
816 /* No errors; receive the packet. */
818 m->m_len = m->m_pkthdr.len =
819 cur_rx->pcn_rxlen - ETHER_CRC_LEN;
820 m->m_pkthdr.rcvif = ifp;
822 (*ifp->if_input)(ifp, m);
825 sc->pcn_cdata.pcn_rx_prod = i;
831 * A frame was downloaded to the chip. It's safe for us to clean up
835 static void pcn_txeof(sc)
836 struct pcn_softc *sc;
838 struct pcn_tx_desc *cur_tx = NULL;
842 ifp = &sc->arpcom.ac_if;
845 * Go through our tx list and free mbufs for those
846 * frames that have been transmitted.
848 idx = sc->pcn_cdata.pcn_tx_cons;
849 while (idx != sc->pcn_cdata.pcn_tx_prod) {
850 cur_tx = &sc->pcn_ldata->pcn_tx_list[idx];
852 if (!PCN_OWN_TXDESC(cur_tx))
855 if (!(cur_tx->pcn_txctl & PCN_TXCTL_ENP)) {
856 sc->pcn_cdata.pcn_tx_cnt--;
857 PCN_INC(idx, PCN_TX_LIST_CNT);
861 if (cur_tx->pcn_txctl & PCN_TXCTL_ERR) {
863 if (cur_tx->pcn_txstat & PCN_TXSTAT_EXDEF)
864 ifp->if_collisions++;
865 if (cur_tx->pcn_txstat & PCN_TXSTAT_RTRY)
866 ifp->if_collisions++;
869 ifp->if_collisions +=
870 cur_tx->pcn_txstat & PCN_TXSTAT_TRC;
873 if (sc->pcn_cdata.pcn_tx_chain[idx] != NULL) {
874 m_freem(sc->pcn_cdata.pcn_tx_chain[idx]);
875 sc->pcn_cdata.pcn_tx_chain[idx] = NULL;
878 sc->pcn_cdata.pcn_tx_cnt--;
879 PCN_INC(idx, PCN_TX_LIST_CNT);
882 if (idx != sc->pcn_cdata.pcn_tx_cons) {
883 /* Some buffers have been freed. */
884 sc->pcn_cdata.pcn_tx_cons = idx;
885 ifp->if_flags &= ~IFF_OACTIVE;
887 ifp->if_timer = (sc->pcn_cdata.pcn_tx_cnt == 0) ? 0 : 5;
892 static void pcn_tick(xsc)
895 struct pcn_softc *sc;
896 struct mii_data *mii;
903 ifp = &sc->arpcom.ac_if;
905 mii = device_get_softc(sc->pcn_miibus);
908 if (sc->pcn_link & !(mii->mii_media_status & IFM_ACTIVE))
913 if (mii->mii_media_status & IFM_ACTIVE &&
914 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE)
916 if (!ifq_is_empty(&ifp->if_snd))
920 callout_reset(&sc->pcn_stat_timer, hz, pcn_tick, sc);
927 static void pcn_intr(arg)
930 struct pcn_softc *sc;
935 ifp = &sc->arpcom.ac_if;
937 /* Supress unwanted interrupts */
938 if (!(ifp->if_flags & IFF_UP)) {
943 CSR_WRITE_4(sc, PCN_IO32_RAP, PCN_CSR_CSR);
945 while ((status = CSR_READ_4(sc, PCN_IO32_RDP)) & PCN_CSR_INTR) {
946 CSR_WRITE_4(sc, PCN_IO32_RDP, status);
948 if (status & PCN_CSR_RINT)
951 if (status & PCN_CSR_TINT)
954 if (status & PCN_CSR_ERR) {
960 if (!ifq_is_empty(&ifp->if_snd))
967 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
968 * pointers to the fragment pointers.
970 static int pcn_encap(sc, m_head, txidx)
971 struct pcn_softc *sc;
975 struct pcn_tx_desc *f = NULL;
977 int frag, cur, cnt = 0;
980 * Start packing the mbufs in this chain into
981 * the fragment pointers. Stop when we run out
982 * of fragments or hit the end of the mbuf chain.
987 for (m = m_head; m != NULL; m = m->m_next) {
989 if ((PCN_TX_LIST_CNT -
990 (sc->pcn_cdata.pcn_tx_cnt + cnt)) < 2)
992 f = &sc->pcn_ldata->pcn_tx_list[frag];
993 f->pcn_txctl = (~(m->m_len) + 1) & PCN_TXCTL_BUFSZ;
994 f->pcn_txctl |= PCN_TXCTL_MBO;
995 f->pcn_tbaddr = vtophys(mtod(m, vm_offset_t));
997 f->pcn_txctl |= PCN_TXCTL_STP;
999 f->pcn_txctl |= PCN_TXCTL_OWN;
1001 PCN_INC(frag, PCN_TX_LIST_CNT);
1009 sc->pcn_cdata.pcn_tx_chain[cur] = m_head;
1010 sc->pcn_ldata->pcn_tx_list[cur].pcn_txctl |=
1011 PCN_TXCTL_ENP|PCN_TXCTL_ADD_FCS|PCN_TXCTL_MORE_LTINT;
1012 sc->pcn_ldata->pcn_tx_list[*txidx].pcn_txctl |= PCN_TXCTL_OWN;
1013 sc->pcn_cdata.pcn_tx_cnt += cnt;
1020 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
1021 * to the mbuf data regions directly in the transmit lists. We also save a
1022 * copy of the pointers since the transmit list fragment pointers are
1023 * physical addresses.
1025 static void pcn_start(ifp)
1028 struct pcn_softc *sc;
1029 struct mbuf *m_head = NULL;
1037 idx = sc->pcn_cdata.pcn_tx_prod;
1039 if (ifp->if_flags & IFF_OACTIVE)
1042 while(sc->pcn_cdata.pcn_tx_chain[idx] == NULL) {
1043 m_head = ifq_poll(&ifp->if_snd);
1047 if (pcn_encap(sc, m_head, &idx)) {
1048 ifp->if_flags |= IFF_OACTIVE;
1051 m_head = ifq_dequeue(&ifp->if_snd);
1053 BPF_MTAP(ifp, m_head);
1057 sc->pcn_cdata.pcn_tx_prod = idx;
1058 pcn_csr_write(sc, PCN_CSR_CSR, PCN_CSR_TX|PCN_CSR_INTEN);
1061 * Set a timeout in case the chip goes out to lunch.
1068 void pcn_setfilt(ifp)
1071 struct pcn_softc *sc;
1075 /* If we want promiscuous mode, set the allframes bit. */
1076 if (ifp->if_flags & IFF_PROMISC) {
1077 PCN_CSR_SETBIT(sc, PCN_CSR_MODE, PCN_MODE_PROMISC);
1079 PCN_CSR_CLRBIT(sc, PCN_CSR_MODE, PCN_MODE_PROMISC);
1082 /* Set the capture broadcast bit to capture broadcast frames. */
1083 if (ifp->if_flags & IFF_BROADCAST) {
1084 PCN_CSR_CLRBIT(sc, PCN_CSR_MODE, PCN_MODE_RXNOBROAD);
1086 PCN_CSR_SETBIT(sc, PCN_CSR_MODE, PCN_MODE_RXNOBROAD);
1092 static void pcn_init(xsc)
1095 struct pcn_softc *sc = xsc;
1096 struct ifnet *ifp = &sc->arpcom.ac_if;
1097 struct mii_data *mii = NULL;
1103 * Cancel pending I/O and free all RX/TX buffers.
1108 mii = device_get_softc(sc->pcn_miibus);
1110 /* Set MAC address */
1111 pcn_csr_write(sc, PCN_CSR_PAR0,
1112 ((u_int16_t *)sc->arpcom.ac_enaddr)[0]);
1113 pcn_csr_write(sc, PCN_CSR_PAR1,
1114 ((u_int16_t *)sc->arpcom.ac_enaddr)[1]);
1115 pcn_csr_write(sc, PCN_CSR_PAR2,
1116 ((u_int16_t *)sc->arpcom.ac_enaddr)[2]);
1118 /* Init circular RX list. */
1119 if (pcn_list_rx_init(sc) == ENOBUFS) {
1120 printf("pcn%d: initialization failed: no "
1121 "memory for rx buffers\n", sc->pcn_unit);
1127 /* Set up RX filter. */
1131 * Init tx descriptors.
1133 pcn_list_tx_init(sc);
1135 /* Set up the mode register. */
1136 pcn_csr_write(sc, PCN_CSR_MODE, PCN_PORT_MII);
1139 * Load the multicast filter.
1144 * Load the addresses of the RX and TX lists.
1146 pcn_csr_write(sc, PCN_CSR_RXADDR0,
1147 vtophys(&sc->pcn_ldata->pcn_rx_list[0]) & 0xFFFF);
1148 pcn_csr_write(sc, PCN_CSR_RXADDR1,
1149 (vtophys(&sc->pcn_ldata->pcn_rx_list[0]) >> 16) & 0xFFFF);
1150 pcn_csr_write(sc, PCN_CSR_TXADDR0,
1151 vtophys(&sc->pcn_ldata->pcn_tx_list[0]) & 0xFFFF);
1152 pcn_csr_write(sc, PCN_CSR_TXADDR1,
1153 (vtophys(&sc->pcn_ldata->pcn_tx_list[0]) >> 16) & 0xFFFF);
1155 /* Set the RX and TX ring sizes. */
1156 pcn_csr_write(sc, PCN_CSR_RXRINGLEN, (~PCN_RX_LIST_CNT) + 1);
1157 pcn_csr_write(sc, PCN_CSR_TXRINGLEN, (~PCN_TX_LIST_CNT) + 1);
1159 /* We're not using the initialization block. */
1160 pcn_csr_write(sc, PCN_CSR_IAB1, 0);
1162 /* Enable fast suspend mode. */
1163 PCN_CSR_SETBIT(sc, PCN_CSR_EXTCTL2, PCN_EXTCTL2_FASTSPNDE);
1166 * Enable burst read and write. Also set the no underflow
1167 * bit. This will avoid transmit underruns in certain
1168 * conditions while still providing decent performance.
1170 PCN_BCR_SETBIT(sc, PCN_BCR_BUSCTL, PCN_BUSCTL_NOUFLOW|
1171 PCN_BUSCTL_BREAD|PCN_BUSCTL_BWRITE);
1173 /* Enable graceful recovery from underflow. */
1174 PCN_CSR_SETBIT(sc, PCN_CSR_IMR, PCN_IMR_DXSUFLO);
1176 /* Enable auto-padding of short TX frames. */
1177 PCN_CSR_SETBIT(sc, PCN_CSR_TFEAT, PCN_TFEAT_PAD_TX);
1179 /* Disable MII autoneg (we handle this ourselves). */
1180 PCN_BCR_SETBIT(sc, PCN_BCR_MIICTL, PCN_MIICTL_DANAS);
1182 if (sc->pcn_type == Am79C978)
1183 pcn_bcr_write(sc, PCN_BCR_PHYSEL,
1184 PCN_PHYSEL_PCNET|PCN_PHY_HOMEPNA);
1186 /* Enable interrupts and start the controller running. */
1187 pcn_csr_write(sc, PCN_CSR_CSR, PCN_CSR_INTEN|PCN_CSR_START);
1191 ifp->if_flags |= IFF_RUNNING;
1192 ifp->if_flags &= ~IFF_OACTIVE;
1195 callout_reset(&sc->pcn_stat_timer, hz, pcn_tick, sc);
1199 * Set media options.
1201 static int pcn_ifmedia_upd(ifp)
1204 struct pcn_softc *sc;
1205 struct mii_data *mii;
1208 mii = device_get_softc(sc->pcn_miibus);
1211 if (mii->mii_instance) {
1212 struct mii_softc *miisc;
1213 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL;
1214 miisc = LIST_NEXT(miisc, mii_list))
1215 mii_phy_reset(miisc);
1223 * Report current media status.
1225 static void pcn_ifmedia_sts(ifp, ifmr)
1227 struct ifmediareq *ifmr;
1229 struct pcn_softc *sc;
1230 struct mii_data *mii;
1234 mii = device_get_softc(sc->pcn_miibus);
1236 ifmr->ifm_active = mii->mii_media_active;
1237 ifmr->ifm_status = mii->mii_media_status;
1242 static int pcn_ioctl(ifp, command, data, cr)
1248 struct pcn_softc *sc = ifp->if_softc;
1249 struct ifreq *ifr = (struct ifreq *) data;
1250 struct mii_data *mii = NULL;
1259 error = ether_ioctl(ifp, command, data);
1262 if (ifp->if_flags & IFF_UP) {
1263 if (ifp->if_flags & IFF_RUNNING &&
1264 ifp->if_flags & IFF_PROMISC &&
1265 !(sc->pcn_if_flags & IFF_PROMISC)) {
1266 PCN_CSR_SETBIT(sc, PCN_CSR_EXTCTL1,
1269 PCN_CSR_CLRBIT(sc, PCN_CSR_EXTCTL1,
1271 pcn_csr_write(sc, PCN_CSR_CSR,
1272 PCN_CSR_INTEN|PCN_CSR_START);
1273 } else if (ifp->if_flags & IFF_RUNNING &&
1274 !(ifp->if_flags & IFF_PROMISC) &&
1275 sc->pcn_if_flags & IFF_PROMISC) {
1276 PCN_CSR_SETBIT(sc, PCN_CSR_EXTCTL1,
1279 PCN_CSR_CLRBIT(sc, PCN_CSR_EXTCTL1,
1281 pcn_csr_write(sc, PCN_CSR_CSR,
1282 PCN_CSR_INTEN|PCN_CSR_START);
1283 } else if (!(ifp->if_flags & IFF_RUNNING))
1286 if (ifp->if_flags & IFF_RUNNING)
1289 sc->pcn_if_flags = ifp->if_flags;
1299 mii = device_get_softc(sc->pcn_miibus);
1300 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
1312 static void pcn_watchdog(ifp)
1315 struct pcn_softc *sc;
1320 printf("pcn%d: watchdog timeout\n", sc->pcn_unit);
1326 if (!ifq_is_empty(&ifp->if_snd))
1333 * Stop the adapter and free any mbufs allocated to the
1336 static void pcn_stop(sc)
1337 struct pcn_softc *sc;
1342 ifp = &sc->arpcom.ac_if;
1345 callout_stop(&sc->pcn_stat_timer);
1346 PCN_CSR_SETBIT(sc, PCN_CSR_CSR, PCN_CSR_STOP);
1350 * Free data in the RX lists.
1352 for (i = 0; i < PCN_RX_LIST_CNT; i++) {
1353 if (sc->pcn_cdata.pcn_rx_chain[i] != NULL) {
1354 m_freem(sc->pcn_cdata.pcn_rx_chain[i]);
1355 sc->pcn_cdata.pcn_rx_chain[i] = NULL;
1358 bzero((char *)&sc->pcn_ldata->pcn_rx_list,
1359 sizeof(sc->pcn_ldata->pcn_rx_list));
1362 * Free the TX list buffers.
1364 for (i = 0; i < PCN_TX_LIST_CNT; i++) {
1365 if (sc->pcn_cdata.pcn_tx_chain[i] != NULL) {
1366 m_freem(sc->pcn_cdata.pcn_tx_chain[i]);
1367 sc->pcn_cdata.pcn_tx_chain[i] = NULL;
1371 bzero((char *)&sc->pcn_ldata->pcn_tx_list,
1372 sizeof(sc->pcn_ldata->pcn_tx_list));
1374 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1380 * Stop all chip I/O so that the kernel's probe routines don't
1381 * get confused by errant DMAs when rebooting.
1383 static void pcn_shutdown(dev)
1386 struct pcn_softc *sc;
1388 sc = device_get_softc(dev);