2 * Copyright (c) 2004 Joerg Sonnenberger <joerg@bec.de>. All rights reserved.
4 * Copyright (c) 2001-2008, Intel Corporation
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:
10 * 1. Redistributions of source code must retain the above copyright notice,
11 * this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * 3. Neither the name of the Intel Corporation nor the names of its
18 * contributors may be used to endorse or promote products derived from
19 * this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
34 * Copyright (c) 2005 The DragonFly Project. All rights reserved.
36 * This code is derived from software contributed to The DragonFly Project
37 * by Matthew Dillon <dillon@backplane.com>
39 * Redistribution and use in source and binary forms, with or without
40 * modification, are permitted provided that the following conditions
43 * 1. Redistributions of source code must retain the above copyright
44 * notice, this list of conditions and the following disclaimer.
45 * 2. Redistributions in binary form must reproduce the above copyright
46 * notice, this list of conditions and the following disclaimer in
47 * the documentation and/or other materials provided with the
49 * 3. Neither the name of The DragonFly Project nor the names of its
50 * contributors may be used to endorse or promote products derived
51 * from this software without specific, prior written permission.
53 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
54 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
55 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
56 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
57 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
58 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
59 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
60 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
61 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
62 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
63 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
67 #include "opt_polling.h"
68 #include "opt_serializer.h"
72 #include <sys/param.h>
74 #include <sys/endian.h>
75 #include <sys/interrupt.h>
76 #include <sys/kernel.h>
78 #include <sys/malloc.h>
82 #include <sys/serialize.h>
83 #include <sys/socket.h>
84 #include <sys/sockio.h>
85 #include <sys/sysctl.h>
86 #include <sys/systm.h>
89 #include <net/ethernet.h>
91 #include <net/if_arp.h>
92 #include <net/if_dl.h>
93 #include <net/if_media.h>
94 #include <net/ifq_var.h>
95 #include <net/toeplitz.h>
96 #include <net/toeplitz2.h>
97 #include <net/vlan/if_vlan_var.h>
98 #include <net/vlan/if_vlan_ether.h>
100 #include <netinet/in_systm.h>
101 #include <netinet/in.h>
102 #include <netinet/ip.h>
103 #include <netinet/tcp.h>
104 #include <netinet/udp.h>
106 #include <bus/pci/pcivar.h>
107 #include <bus/pci/pcireg.h>
109 #include <dev/netif/ig_hal/e1000_api.h>
110 #include <dev/netif/ig_hal/e1000_82571.h>
111 #include <dev/netif/emx/if_emx.h>
114 #define EMX_RSS_DPRINTF(sc, lvl, fmt, ...) \
116 if (sc->rss_debug >= lvl) \
117 if_printf(&sc->arpcom.ac_if, fmt, __VA_ARGS__); \
119 #else /* !EMX_RSS_DEBUG */
120 #define EMX_RSS_DPRINTF(sc, lvl, fmt, ...) ((void)0)
121 #endif /* EMX_RSS_DEBUG */
123 #define EMX_NAME "Intel(R) PRO/1000 "
125 #define EMX_DEVICE(id) \
126 { EMX_VENDOR_ID, E1000_DEV_ID_##id, EMX_NAME #id }
127 #define EMX_DEVICE_NULL { 0, 0, NULL }
129 static const struct emx_device {
134 EMX_DEVICE(82571EB_COPPER),
135 EMX_DEVICE(82571EB_FIBER),
136 EMX_DEVICE(82571EB_SERDES),
137 EMX_DEVICE(82571EB_SERDES_DUAL),
138 EMX_DEVICE(82571EB_SERDES_QUAD),
139 EMX_DEVICE(82571EB_QUAD_COPPER),
140 EMX_DEVICE(82571EB_QUAD_COPPER_BP),
141 EMX_DEVICE(82571EB_QUAD_COPPER_LP),
142 EMX_DEVICE(82571EB_QUAD_FIBER),
143 EMX_DEVICE(82571PT_QUAD_COPPER),
145 EMX_DEVICE(82572EI_COPPER),
146 EMX_DEVICE(82572EI_FIBER),
147 EMX_DEVICE(82572EI_SERDES),
151 EMX_DEVICE(82573E_IAMT),
154 EMX_DEVICE(80003ES2LAN_COPPER_SPT),
155 EMX_DEVICE(80003ES2LAN_SERDES_SPT),
156 EMX_DEVICE(80003ES2LAN_COPPER_DPT),
157 EMX_DEVICE(80003ES2LAN_SERDES_DPT),
161 /* required last entry */
165 static int emx_probe(device_t);
166 static int emx_attach(device_t);
167 static int emx_detach(device_t);
168 static int emx_shutdown(device_t);
169 static int emx_suspend(device_t);
170 static int emx_resume(device_t);
172 static void emx_init(void *);
173 static void emx_stop(struct emx_softc *);
174 static int emx_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
175 static void emx_start(struct ifnet *);
176 #ifdef DEVICE_POLLING
177 static void emx_poll(struct ifnet *, enum poll_cmd, int);
179 static void emx_watchdog(struct ifnet *);
180 static void emx_media_status(struct ifnet *, struct ifmediareq *);
181 static int emx_media_change(struct ifnet *);
182 static void emx_timer(void *);
183 static void emx_serialize(struct ifnet *, enum ifnet_serialize);
184 static void emx_deserialize(struct ifnet *, enum ifnet_serialize);
185 static int emx_tryserialize(struct ifnet *, enum ifnet_serialize);
187 static void emx_serialize_assert(struct ifnet *, enum ifnet_serialize,
191 static void emx_intr(void *);
192 static void emx_rxeof(struct emx_softc *, int, int);
193 static void emx_txeof(struct emx_softc *);
194 static void emx_tx_collect(struct emx_softc *);
195 static void emx_tx_purge(struct emx_softc *);
196 static void emx_enable_intr(struct emx_softc *);
197 static void emx_disable_intr(struct emx_softc *);
199 static int emx_dma_alloc(struct emx_softc *);
200 static void emx_dma_free(struct emx_softc *);
201 static void emx_init_tx_ring(struct emx_softc *);
202 static int emx_init_rx_ring(struct emx_softc *, struct emx_rxdata *);
203 static void emx_free_rx_ring(struct emx_softc *, struct emx_rxdata *);
204 static int emx_create_tx_ring(struct emx_softc *);
205 static int emx_create_rx_ring(struct emx_softc *, struct emx_rxdata *);
206 static void emx_destroy_tx_ring(struct emx_softc *, int);
207 static void emx_destroy_rx_ring(struct emx_softc *,
208 struct emx_rxdata *, int);
209 static int emx_newbuf(struct emx_softc *, struct emx_rxdata *, int, int);
210 static int emx_encap(struct emx_softc *, struct mbuf **);
211 static int emx_txcsum_pullup(struct emx_softc *, struct mbuf **);
212 static int emx_txcsum(struct emx_softc *, struct mbuf *,
213 uint32_t *, uint32_t *);
215 static int emx_is_valid_eaddr(const uint8_t *);
216 static int emx_hw_init(struct emx_softc *);
217 static void emx_setup_ifp(struct emx_softc *);
218 static void emx_init_tx_unit(struct emx_softc *);
219 static void emx_init_rx_unit(struct emx_softc *);
220 static void emx_update_stats(struct emx_softc *);
221 static void emx_set_promisc(struct emx_softc *);
222 static void emx_disable_promisc(struct emx_softc *);
223 static void emx_set_multi(struct emx_softc *);
224 static void emx_update_link_status(struct emx_softc *);
225 static void emx_smartspeed(struct emx_softc *);
227 static void emx_print_debug_info(struct emx_softc *);
228 static void emx_print_nvm_info(struct emx_softc *);
229 static void emx_print_hw_stats(struct emx_softc *);
231 static int emx_sysctl_stats(SYSCTL_HANDLER_ARGS);
232 static int emx_sysctl_debug_info(SYSCTL_HANDLER_ARGS);
233 static int emx_sysctl_int_throttle(SYSCTL_HANDLER_ARGS);
234 static int emx_sysctl_int_tx_nsegs(SYSCTL_HANDLER_ARGS);
235 static void emx_add_sysctl(struct emx_softc *);
237 static void emx_serialize_skipmain(struct emx_softc *);
238 static void emx_deserialize_skipmain(struct emx_softc *);
239 static int emx_tryserialize_skipmain(struct emx_softc *);
241 /* Management and WOL Support */
242 static void emx_get_mgmt(struct emx_softc *);
243 static void emx_rel_mgmt(struct emx_softc *);
244 static void emx_get_hw_control(struct emx_softc *);
245 static void emx_rel_hw_control(struct emx_softc *);
246 static void emx_enable_wol(device_t);
248 static device_method_t emx_methods[] = {
249 /* Device interface */
250 DEVMETHOD(device_probe, emx_probe),
251 DEVMETHOD(device_attach, emx_attach),
252 DEVMETHOD(device_detach, emx_detach),
253 DEVMETHOD(device_shutdown, emx_shutdown),
254 DEVMETHOD(device_suspend, emx_suspend),
255 DEVMETHOD(device_resume, emx_resume),
259 static driver_t emx_driver = {
262 sizeof(struct emx_softc),
265 static devclass_t emx_devclass;
267 DECLARE_DUMMY_MODULE(if_emx);
268 MODULE_DEPEND(emx, ig_hal, 1, 1, 1);
269 DRIVER_MODULE(if_emx, pci, emx_driver, emx_devclass, 0, 0);
274 static int emx_int_throttle_ceil = EMX_DEFAULT_ITR;
275 static int emx_rxd = EMX_DEFAULT_RXD;
276 static int emx_txd = EMX_DEFAULT_TXD;
277 static int emx_smart_pwr_down = FALSE;
279 /* Controls whether promiscuous also shows bad packets */
280 static int emx_debug_sbp = FALSE;
282 static int emx_82573_workaround = TRUE;
284 TUNABLE_INT("hw.emx.int_throttle_ceil", &emx_int_throttle_ceil);
285 TUNABLE_INT("hw.emx.rxd", &emx_rxd);
286 TUNABLE_INT("hw.emx.txd", &emx_txd);
287 TUNABLE_INT("hw.emx.smart_pwr_down", &emx_smart_pwr_down);
288 TUNABLE_INT("hw.emx.sbp", &emx_debug_sbp);
289 TUNABLE_INT("hw.emx.82573_workaround", &emx_82573_workaround);
291 /* Global used in WOL setup with multiport cards */
292 static int emx_global_quad_port_a = 0;
294 /* Set this to one to display debug statistics */
295 static int emx_display_debug_stats = 0;
297 #if !defined(KTR_IF_EMX)
298 #define KTR_IF_EMX KTR_ALL
300 KTR_INFO_MASTER(if_emx);
301 KTR_INFO(KTR_IF_EMX, if_emx, intr_beg, 0, "intr begin", 0);
302 KTR_INFO(KTR_IF_EMX, if_emx, intr_end, 1, "intr end", 0);
303 KTR_INFO(KTR_IF_EMX, if_emx, pkt_receive, 4, "rx packet", 0);
304 KTR_INFO(KTR_IF_EMX, if_emx, pkt_txqueue, 5, "tx packet", 0);
305 KTR_INFO(KTR_IF_EMX, if_emx, pkt_txclean, 6, "tx clean", 0);
306 #define logif(name) KTR_LOG(if_emx_ ## name)
309 emx_setup_rxdesc(emx_rxdesc_t *rxd, const struct emx_rxbuf *rxbuf)
311 rxd->rxd_bufaddr = htole64(rxbuf->paddr);
312 /* DD bit must be cleared */
313 rxd->rxd_staterr = 0;
317 emx_rxcsum(uint32_t staterr, struct mbuf *mp)
319 /* Ignore Checksum bit is set */
320 if (staterr & E1000_RXD_STAT_IXSM)
323 if ((staterr & (E1000_RXD_STAT_IPCS | E1000_RXDEXT_STATERR_IPE)) ==
325 mp->m_pkthdr.csum_flags |= CSUM_IP_CHECKED | CSUM_IP_VALID;
327 if ((staterr & (E1000_RXD_STAT_TCPCS | E1000_RXDEXT_STATERR_TCPE)) ==
328 E1000_RXD_STAT_TCPCS) {
329 mp->m_pkthdr.csum_flags |= CSUM_DATA_VALID |
331 CSUM_FRAG_NOT_CHECKED;
332 mp->m_pkthdr.csum_data = htons(0xffff);
336 static __inline struct pktinfo *
337 emx_rssinfo(struct mbuf *m, struct pktinfo *pi,
338 uint32_t mrq, uint32_t hash, uint32_t staterr)
340 switch (mrq & EMX_RXDMRQ_RSSTYPE_MASK) {
341 case EMX_RXDMRQ_IPV4_TCP:
342 pi->pi_netisr = NETISR_IP;
344 pi->pi_l3proto = IPPROTO_TCP;
347 case EMX_RXDMRQ_IPV6_TCP:
348 pi->pi_netisr = NETISR_IPV6;
350 pi->pi_l3proto = IPPROTO_TCP;
353 case EMX_RXDMRQ_IPV4:
354 if (staterr & E1000_RXD_STAT_IXSM)
358 (E1000_RXD_STAT_TCPCS | E1000_RXDEXT_STATERR_TCPE)) ==
359 E1000_RXD_STAT_TCPCS) {
360 pi->pi_netisr = NETISR_IP;
362 pi->pi_l3proto = IPPROTO_UDP;
370 m->m_flags |= M_HASH;
371 m->m_pkthdr.hash = toeplitz_hash(hash);
376 emx_probe(device_t dev)
378 const struct emx_device *d;
381 vid = pci_get_vendor(dev);
382 did = pci_get_device(dev);
384 for (d = emx_devices; d->desc != NULL; ++d) {
385 if (vid == d->vid && did == d->did) {
386 device_set_desc(dev, d->desc);
387 device_set_async_attach(dev, TRUE);
395 emx_attach(device_t dev)
397 struct emx_softc *sc = device_get_softc(dev);
398 struct ifnet *ifp = &sc->arpcom.ac_if;
400 uint16_t eeprom_data, device_id;
402 lwkt_serialize_init(&sc->main_serialize);
403 lwkt_serialize_init(&sc->tx_serialize);
404 for (i = 0; i < EMX_NRX_RING; ++i)
405 lwkt_serialize_init(&sc->rx_data[i].rx_serialize);
408 sc->serializes[i++] = &sc->main_serialize;
409 sc->serializes[i++] = &sc->tx_serialize;
410 sc->serializes[i++] = &sc->rx_data[0].rx_serialize;
411 sc->serializes[i++] = &sc->rx_data[1].rx_serialize;
412 KKASSERT(i == EMX_NSERIALIZE);
414 callout_init(&sc->timer);
416 sc->dev = sc->osdep.dev = dev;
419 * Determine hardware and mac type
421 sc->hw.vendor_id = pci_get_vendor(dev);
422 sc->hw.device_id = pci_get_device(dev);
423 sc->hw.revision_id = pci_get_revid(dev);
424 sc->hw.subsystem_vendor_id = pci_get_subvendor(dev);
425 sc->hw.subsystem_device_id = pci_get_subdevice(dev);
427 if (e1000_set_mac_type(&sc->hw))
430 /* Enable bus mastering */
431 pci_enable_busmaster(dev);
436 sc->memory_rid = EMX_BAR_MEM;
437 sc->memory = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
438 &sc->memory_rid, RF_ACTIVE);
439 if (sc->memory == NULL) {
440 device_printf(dev, "Unable to allocate bus resource: memory\n");
444 sc->osdep.mem_bus_space_tag = rman_get_bustag(sc->memory);
445 sc->osdep.mem_bus_space_handle = rman_get_bushandle(sc->memory);
447 /* XXX This is quite goofy, it is not actually used */
448 sc->hw.hw_addr = (uint8_t *)&sc->osdep.mem_bus_space_handle;
454 sc->intr_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->intr_rid,
455 RF_SHAREABLE | RF_ACTIVE);
456 if (sc->intr_res == NULL) {
457 device_printf(dev, "Unable to allocate bus resource: "
463 /* Save PCI command register for Shared Code */
464 sc->hw.bus.pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2);
465 sc->hw.back = &sc->osdep;
467 /* Do Shared Code initialization */
468 if (e1000_setup_init_funcs(&sc->hw, TRUE)) {
469 device_printf(dev, "Setup of Shared code failed\n");
473 e1000_get_bus_info(&sc->hw);
475 sc->hw.mac.autoneg = EMX_DO_AUTO_NEG;
476 sc->hw.phy.autoneg_wait_to_complete = FALSE;
477 sc->hw.phy.autoneg_advertised = EMX_AUTONEG_ADV_DEFAULT;
480 * Interrupt throttle rate
482 if (emx_int_throttle_ceil == 0) {
483 sc->int_throttle_ceil = 0;
485 int throttle = emx_int_throttle_ceil;
488 throttle = EMX_DEFAULT_ITR;
490 /* Recalculate the tunable value to get the exact frequency. */
491 throttle = 1000000000 / 256 / throttle;
493 /* Upper 16bits of ITR is reserved and should be zero */
494 if (throttle & 0xffff0000)
495 throttle = 1000000000 / 256 / EMX_DEFAULT_ITR;
497 sc->int_throttle_ceil = 1000000000 / 256 / throttle;
500 e1000_init_script_state_82541(&sc->hw, TRUE);
501 e1000_set_tbi_compatibility_82543(&sc->hw, TRUE);
504 if (sc->hw.phy.media_type == e1000_media_type_copper) {
505 sc->hw.phy.mdix = EMX_AUTO_ALL_MODES;
506 sc->hw.phy.disable_polarity_correction = FALSE;
507 sc->hw.phy.ms_type = EMX_MASTER_SLAVE;
510 /* Set the frame limits assuming standard ethernet sized frames. */
511 sc->max_frame_size = ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN;
512 sc->min_frame_size = ETHER_MIN_LEN;
514 /* This controls when hardware reports transmit completion status. */
515 sc->hw.mac.report_tx_early = 1;
518 /* Calculate # of RX rings */
520 sc->rx_ring_cnt = EMX_NRX_RING;
524 sc->rx_ring_inuse = sc->rx_ring_cnt;
526 /* Allocate RX/TX rings' busdma(9) stuffs */
527 error = emx_dma_alloc(sc);
531 /* Make sure we have a good EEPROM before we read from it */
532 if (e1000_validate_nvm_checksum(&sc->hw) < 0) {
534 * Some PCI-E parts fail the first check due to
535 * the link being in sleep state, call it again,
536 * if it fails a second time its a real issue.
538 if (e1000_validate_nvm_checksum(&sc->hw) < 0) {
540 "The EEPROM Checksum Is Not Valid\n");
546 /* Initialize the hardware */
547 error = emx_hw_init(sc);
549 device_printf(dev, "Unable to initialize the hardware\n");
553 /* Copy the permanent MAC address out of the EEPROM */
554 if (e1000_read_mac_addr(&sc->hw) < 0) {
555 device_printf(dev, "EEPROM read error while reading MAC"
560 if (!emx_is_valid_eaddr(sc->hw.mac.addr)) {
561 device_printf(dev, "Invalid MAC address\n");
566 /* Manually turn off all interrupts */
567 E1000_WRITE_REG(&sc->hw, E1000_IMC, 0xffffffff);
569 /* Setup OS specific network interface */
572 /* Add sysctl tree, must after emx_setup_ifp() */
575 /* Initialize statistics */
576 emx_update_stats(sc);
578 sc->hw.mac.get_link_status = 1;
579 emx_update_link_status(sc);
581 /* Indicate SOL/IDER usage */
582 if (e1000_check_reset_block(&sc->hw)) {
584 "PHY reset is blocked due to SOL/IDER session.\n");
587 /* Determine if we have to control management hardware */
588 sc->has_manage = e1000_enable_mng_pass_thru(&sc->hw);
593 switch (sc->hw.mac.type) {
595 case e1000_80003es2lan:
596 if (sc->hw.bus.func == 1) {
597 e1000_read_nvm(&sc->hw,
598 NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
600 e1000_read_nvm(&sc->hw,
601 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
603 eeprom_data &= EMX_EEPROM_APME;
607 /* APME bit in EEPROM is mapped to WUC.APME */
609 E1000_READ_REG(&sc->hw, E1000_WUC) & E1000_WUC_APME;
613 sc->wol = E1000_WUFC_MAG;
615 * We have the eeprom settings, now apply the special cases
616 * where the eeprom may be wrong or the board won't support
617 * wake on lan on a particular port
619 device_id = pci_get_device(dev);
621 case E1000_DEV_ID_82571EB_FIBER:
623 * Wake events only supported on port A for dual fiber
624 * regardless of eeprom setting
626 if (E1000_READ_REG(&sc->hw, E1000_STATUS) &
631 case E1000_DEV_ID_82571EB_QUAD_COPPER:
632 case E1000_DEV_ID_82571EB_QUAD_FIBER:
633 case E1000_DEV_ID_82571EB_QUAD_COPPER_LP:
634 /* if quad port sc, disable WoL on all but port A */
635 if (emx_global_quad_port_a != 0)
637 /* Reset for multiple quad port adapters */
638 if (++emx_global_quad_port_a == 4)
639 emx_global_quad_port_a = 0;
643 /* XXX disable wol */
646 sc->spare_tx_desc = EMX_TX_SPARE;
649 * Keep following relationship between spare_tx_desc, oact_tx_desc
651 * (spare_tx_desc + EMX_TX_RESERVED) <=
652 * oact_tx_desc <= EMX_TX_OACTIVE_MAX <= tx_int_nsegs
654 sc->oact_tx_desc = sc->num_tx_desc / 8;
655 if (sc->oact_tx_desc > EMX_TX_OACTIVE_MAX)
656 sc->oact_tx_desc = EMX_TX_OACTIVE_MAX;
657 if (sc->oact_tx_desc < sc->spare_tx_desc + EMX_TX_RESERVED)
658 sc->oact_tx_desc = sc->spare_tx_desc + EMX_TX_RESERVED;
660 sc->tx_int_nsegs = sc->num_tx_desc / 16;
661 if (sc->tx_int_nsegs < sc->oact_tx_desc)
662 sc->tx_int_nsegs = sc->oact_tx_desc;
664 error = bus_setup_intr(dev, sc->intr_res, INTR_MPSAFE, emx_intr, sc,
665 &sc->intr_tag, &sc->main_serialize);
667 device_printf(dev, "Failed to register interrupt handler");
668 ether_ifdetach(&sc->arpcom.ac_if);
672 ifp->if_cpuid = ithread_cpuid(rman_get_start(sc->intr_res));
673 KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus);
681 emx_detach(device_t dev)
683 struct emx_softc *sc = device_get_softc(dev);
685 if (device_is_attached(dev)) {
686 struct ifnet *ifp = &sc->arpcom.ac_if;
688 ifnet_serialize_all(ifp);
692 e1000_phy_hw_reset(&sc->hw);
696 if (sc->hw.mac.type == e1000_82573 &&
697 e1000_check_mng_mode(&sc->hw))
698 emx_rel_hw_control(sc);
701 E1000_WRITE_REG(&sc->hw, E1000_WUC, E1000_WUC_PME_EN);
702 E1000_WRITE_REG(&sc->hw, E1000_WUFC, sc->wol);
706 bus_teardown_intr(dev, sc->intr_res, sc->intr_tag);
708 ifnet_deserialize_all(ifp);
712 bus_generic_detach(dev);
714 if (sc->intr_res != NULL) {
715 bus_release_resource(dev, SYS_RES_IRQ, sc->intr_rid,
719 if (sc->memory != NULL) {
720 bus_release_resource(dev, SYS_RES_MEMORY, sc->memory_rid,
726 /* Free sysctl tree */
727 if (sc->sysctl_tree != NULL)
728 sysctl_ctx_free(&sc->sysctl_ctx);
734 emx_shutdown(device_t dev)
736 return emx_suspend(dev);
740 emx_suspend(device_t dev)
742 struct emx_softc *sc = device_get_softc(dev);
743 struct ifnet *ifp = &sc->arpcom.ac_if;
745 ifnet_serialize_all(ifp);
751 if (sc->hw.mac.type == e1000_82573 &&
752 e1000_check_mng_mode(&sc->hw))
753 emx_rel_hw_control(sc);
756 E1000_WRITE_REG(&sc->hw, E1000_WUC, E1000_WUC_PME_EN);
757 E1000_WRITE_REG(&sc->hw, E1000_WUFC, sc->wol);
761 ifnet_deserialize_all(ifp);
763 return bus_generic_suspend(dev);
767 emx_resume(device_t dev)
769 struct emx_softc *sc = device_get_softc(dev);
770 struct ifnet *ifp = &sc->arpcom.ac_if;
772 ifnet_serialize_all(ifp);
778 ifnet_deserialize_all(ifp);
780 return bus_generic_resume(dev);
784 emx_start(struct ifnet *ifp)
786 struct emx_softc *sc = ifp->if_softc;
789 ASSERT_SERIALIZED(&sc->tx_serialize);
791 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING)
794 if (!sc->link_active) {
795 ifq_purge(&ifp->if_snd);
799 while (!ifq_is_empty(&ifp->if_snd)) {
800 /* Now do we at least have a minimal? */
801 if (EMX_IS_OACTIVE(sc)) {
803 if (EMX_IS_OACTIVE(sc)) {
804 ifp->if_flags |= IFF_OACTIVE;
805 sc->no_tx_desc_avail1++;
811 m_head = ifq_dequeue(&ifp->if_snd, NULL);
815 if (emx_encap(sc, &m_head)) {
821 /* Send a copy of the frame to the BPF listener */
822 ETHER_BPF_MTAP(ifp, m_head);
824 /* Set timeout in case hardware has problems transmitting. */
825 ifp->if_timer = EMX_TX_TIMEOUT;
830 emx_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
832 struct emx_softc *sc = ifp->if_softc;
833 struct ifreq *ifr = (struct ifreq *)data;
834 uint16_t eeprom_data = 0;
835 int max_frame_size, mask, reinit;
838 ASSERT_IFNET_SERIALIZED_ALL(ifp);
842 switch (sc->hw.mac.type) {
845 * 82573 only supports jumbo frames
846 * if ASPM is disabled.
848 e1000_read_nvm(&sc->hw, NVM_INIT_3GIO_3, 1,
850 if (eeprom_data & NVM_WORD1A_ASPM_MASK) {
851 max_frame_size = ETHER_MAX_LEN;
856 /* Limit Jumbo Frame size */
860 case e1000_80003es2lan:
861 max_frame_size = 9234;
865 max_frame_size = MAX_JUMBO_FRAME_SIZE;
868 if (ifr->ifr_mtu > max_frame_size - ETHER_HDR_LEN -
874 ifp->if_mtu = ifr->ifr_mtu;
875 sc->max_frame_size = ifp->if_mtu + ETHER_HDR_LEN +
878 if (ifp->if_flags & IFF_RUNNING)
883 if (ifp->if_flags & IFF_UP) {
884 if ((ifp->if_flags & IFF_RUNNING)) {
885 if ((ifp->if_flags ^ sc->if_flags) &
886 (IFF_PROMISC | IFF_ALLMULTI)) {
887 emx_disable_promisc(sc);
893 } else if (ifp->if_flags & IFF_RUNNING) {
896 sc->if_flags = ifp->if_flags;
901 if (ifp->if_flags & IFF_RUNNING) {
902 emx_disable_intr(sc);
904 #ifdef DEVICE_POLLING
905 if (!(ifp->if_flags & IFF_POLLING))
912 /* Check SOL/IDER usage */
913 if (e1000_check_reset_block(&sc->hw)) {
914 device_printf(sc->dev, "Media change is"
915 " blocked due to SOL/IDER session.\n");
921 error = ifmedia_ioctl(ifp, ifr, &sc->media, command);
926 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
927 if (mask & IFCAP_HWCSUM) {
928 ifp->if_capenable ^= (mask & IFCAP_HWCSUM);
931 if (mask & IFCAP_VLAN_HWTAGGING) {
932 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
935 if (mask & IFCAP_RSS) {
936 ifp->if_capenable ^= IFCAP_RSS;
939 if (reinit && (ifp->if_flags & IFF_RUNNING))
944 error = ether_ioctl(ifp, command, data);
951 emx_watchdog(struct ifnet *ifp)
953 struct emx_softc *sc = ifp->if_softc;
955 ASSERT_IFNET_SERIALIZED_ALL(ifp);
958 * The timer is set to 5 every time start queues a packet.
959 * Then txeof keeps resetting it as long as it cleans at
960 * least one descriptor.
961 * Finally, anytime all descriptors are clean the timer is
965 if (E1000_READ_REG(&sc->hw, E1000_TDT(0)) ==
966 E1000_READ_REG(&sc->hw, E1000_TDH(0))) {
968 * If we reach here, all TX jobs are completed and
969 * the TX engine should have been idled for some time.
970 * We don't need to call if_devstart() here.
972 ifp->if_flags &= ~IFF_OACTIVE;
978 * If we are in this routine because of pause frames, then
979 * don't reset the hardware.
981 if (E1000_READ_REG(&sc->hw, E1000_STATUS) & E1000_STATUS_TXOFF) {
982 ifp->if_timer = EMX_TX_TIMEOUT;
986 if (e1000_check_for_link(&sc->hw) == 0)
987 if_printf(ifp, "watchdog timeout -- resetting\n");
990 sc->watchdog_events++;
994 if (!ifq_is_empty(&ifp->if_snd))
1001 struct emx_softc *sc = xsc;
1002 struct ifnet *ifp = &sc->arpcom.ac_if;
1003 device_t dev = sc->dev;
1007 ASSERT_IFNET_SERIALIZED_ALL(ifp);
1012 * Packet Buffer Allocation (PBA)
1013 * Writing PBA sets the receive portion of the buffer
1014 * the remainder is used for the transmit buffer.
1016 switch (sc->hw.mac.type) {
1017 /* Total Packet Buffer on these is 48K */
1020 case e1000_80003es2lan:
1021 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
1024 case e1000_82573: /* 82573: Total Packet Buffer is 32K */
1025 pba = E1000_PBA_12K; /* 12K for Rx, 20K for Tx */
1029 pba = E1000_PBA_20K; /* 20K for Rx, 20K for Tx */
1033 /* Devices before 82547 had a Packet Buffer of 64K. */
1034 if (sc->max_frame_size > 8192)
1035 pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */
1037 pba = E1000_PBA_48K; /* 48K for Rx, 16K for Tx */
1039 E1000_WRITE_REG(&sc->hw, E1000_PBA, pba);
1041 /* Get the latest mac address, User can use a LAA */
1042 bcopy(IF_LLADDR(ifp), sc->hw.mac.addr, ETHER_ADDR_LEN);
1044 /* Put the address into the Receive Address Array */
1045 e1000_rar_set(&sc->hw, sc->hw.mac.addr, 0);
1048 * With the 82571 sc, RAR[0] may be overwritten
1049 * when the other port is reset, we make a duplicate
1050 * in RAR[14] for that eventuality, this assures
1051 * the interface continues to function.
1053 if (sc->hw.mac.type == e1000_82571) {
1054 e1000_set_laa_state_82571(&sc->hw, TRUE);
1055 e1000_rar_set(&sc->hw, sc->hw.mac.addr,
1056 E1000_RAR_ENTRIES - 1);
1059 /* Initialize the hardware */
1060 if (emx_hw_init(sc)) {
1061 device_printf(dev, "Unable to initialize the hardware\n");
1062 /* XXX emx_stop()? */
1065 emx_update_link_status(sc);
1067 /* Setup VLAN support, basic and offload if available */
1068 E1000_WRITE_REG(&sc->hw, E1000_VET, ETHERTYPE_VLAN);
1070 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) {
1073 ctrl = E1000_READ_REG(&sc->hw, E1000_CTRL);
1074 ctrl |= E1000_CTRL_VME;
1075 E1000_WRITE_REG(&sc->hw, E1000_CTRL, ctrl);
1078 /* Set hardware offload abilities */
1079 if (ifp->if_capenable & IFCAP_TXCSUM)
1080 ifp->if_hwassist = EMX_CSUM_FEATURES;
1082 ifp->if_hwassist = 0;
1084 /* Configure for OS presence */
1087 /* Prepare transmit descriptors and buffers */
1088 emx_init_tx_ring(sc);
1089 emx_init_tx_unit(sc);
1091 /* Setup Multicast table */
1095 * Adjust # of RX ring to be used based on IFCAP_RSS
1097 if (ifp->if_capenable & IFCAP_RSS)
1098 sc->rx_ring_inuse = sc->rx_ring_cnt;
1100 sc->rx_ring_inuse = 1;
1102 /* Prepare receive descriptors and buffers */
1103 for (i = 0; i < sc->rx_ring_inuse; ++i) {
1104 if (emx_init_rx_ring(sc, &sc->rx_data[i])) {
1106 "Could not setup receive structures\n");
1111 emx_init_rx_unit(sc);
1113 /* Don't lose promiscuous settings */
1114 emx_set_promisc(sc);
1116 ifp->if_flags |= IFF_RUNNING;
1117 ifp->if_flags &= ~IFF_OACTIVE;
1119 callout_reset(&sc->timer, hz, emx_timer, sc);
1120 e1000_clear_hw_cntrs_base_generic(&sc->hw);
1122 /* MSI/X configuration for 82574 */
1123 if (sc->hw.mac.type == e1000_82574) {
1126 tmp = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT);
1127 tmp |= E1000_CTRL_EXT_PBA_CLR;
1128 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT, tmp);
1130 * Set the IVAR - interrupt vector routing.
1131 * Each nibble represents a vector, high bit
1132 * is enable, other 3 bits are the MSIX table
1133 * entry, we map RXQ0 to 0, TXQ0 to 1, and
1134 * Link (other) to 2, hence the magic number.
1136 E1000_WRITE_REG(&sc->hw, E1000_IVAR, 0x800A0908);
1139 #ifdef DEVICE_POLLING
1141 * Only enable interrupts if we are not polling, make sure
1142 * they are off otherwise.
1144 if (ifp->if_flags & IFF_POLLING)
1145 emx_disable_intr(sc);
1147 #endif /* DEVICE_POLLING */
1148 emx_enable_intr(sc);
1150 /* Don't reset the phy next time init gets called */
1151 sc->hw.phy.reset_disable = TRUE;
1154 #ifdef DEVICE_POLLING
1157 emx_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
1159 struct emx_softc *sc = ifp->if_softc;
1162 ASSERT_IFNET_SERIALIZED_MAIN(ifp);
1166 emx_disable_intr(sc);
1169 case POLL_DEREGISTER:
1170 emx_enable_intr(sc);
1173 case POLL_AND_CHECK_STATUS:
1174 reg_icr = E1000_READ_REG(&sc->hw, E1000_ICR);
1175 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
1176 if (emx_tryserialize_skipmain(sc)) {
1177 callout_stop(&sc->timer);
1178 sc->hw.mac.get_link_status = 1;
1179 emx_update_link_status(sc);
1180 callout_reset(&sc->timer, hz, emx_timer, sc);
1181 emx_deserialize_skipmain(sc);
1186 if (ifp->if_flags & IFF_RUNNING) {
1189 for (i = 0; i < sc->rx_ring_inuse; ++i) {
1190 if (lwkt_serialize_try(
1191 &sc->rx_data[i].rx_serialize)) {
1192 emx_rxeof(sc, i, count);
1193 lwkt_serialize_exit(
1194 &sc->rx_data[i].rx_serialize);
1198 if (lwkt_serialize_try(&sc->tx_serialize)) {
1200 if (!ifq_is_empty(&ifp->if_snd))
1202 lwkt_serialize_exit(&sc->tx_serialize);
1209 #endif /* DEVICE_POLLING */
1214 struct emx_softc *sc = xsc;
1215 struct ifnet *ifp = &sc->arpcom.ac_if;
1219 ASSERT_SERIALIZED(&sc->main_serialize);
1221 reg_icr = E1000_READ_REG(&sc->hw, E1000_ICR);
1223 if ((reg_icr & E1000_ICR_INT_ASSERTED) == 0) {
1229 * XXX: some laptops trigger several spurious interrupts
1230 * on emx(4) when in the resume cycle. The ICR register
1231 * reports all-ones value in this case. Processing such
1232 * interrupts would lead to a freeze. I don't know why.
1234 if (reg_icr == 0xffffffff) {
1239 if (ifp->if_flags & IFF_RUNNING) {
1241 (E1000_ICR_RXT0 | E1000_ICR_RXDMT0 | E1000_ICR_RXO)) {
1244 for (i = 0; i < sc->rx_ring_inuse; ++i) {
1245 lwkt_serialize_enter(
1246 &sc->rx_data[i].rx_serialize);
1247 emx_rxeof(sc, i, -1);
1248 lwkt_serialize_exit(
1249 &sc->rx_data[i].rx_serialize);
1252 if (reg_icr & E1000_ICR_TXDW) {
1253 lwkt_serialize_enter(&sc->tx_serialize);
1255 if (!ifq_is_empty(&ifp->if_snd))
1257 lwkt_serialize_exit(&sc->tx_serialize);
1261 /* Link status change */
1262 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
1263 emx_serialize_skipmain(sc);
1265 callout_stop(&sc->timer);
1266 sc->hw.mac.get_link_status = 1;
1267 emx_update_link_status(sc);
1269 /* Deal with TX cruft when link lost */
1272 callout_reset(&sc->timer, hz, emx_timer, sc);
1274 emx_deserialize_skipmain(sc);
1277 if (reg_icr & E1000_ICR_RXO)
1284 emx_media_status(struct ifnet *ifp, struct ifmediareq *ifmr)
1286 struct emx_softc *sc = ifp->if_softc;
1288 ASSERT_IFNET_SERIALIZED_ALL(ifp);
1290 emx_update_link_status(sc);
1292 ifmr->ifm_status = IFM_AVALID;
1293 ifmr->ifm_active = IFM_ETHER;
1295 if (!sc->link_active)
1298 ifmr->ifm_status |= IFM_ACTIVE;
1300 if (sc->hw.phy.media_type == e1000_media_type_fiber ||
1301 sc->hw.phy.media_type == e1000_media_type_internal_serdes) {
1302 ifmr->ifm_active |= IFM_1000_SX | IFM_FDX;
1304 switch (sc->link_speed) {
1306 ifmr->ifm_active |= IFM_10_T;
1309 ifmr->ifm_active |= IFM_100_TX;
1313 ifmr->ifm_active |= IFM_1000_T;
1316 if (sc->link_duplex == FULL_DUPLEX)
1317 ifmr->ifm_active |= IFM_FDX;
1319 ifmr->ifm_active |= IFM_HDX;
1324 emx_media_change(struct ifnet *ifp)
1326 struct emx_softc *sc = ifp->if_softc;
1327 struct ifmedia *ifm = &sc->media;
1329 ASSERT_IFNET_SERIALIZED_ALL(ifp);
1331 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
1334 switch (IFM_SUBTYPE(ifm->ifm_media)) {
1336 sc->hw.mac.autoneg = EMX_DO_AUTO_NEG;
1337 sc->hw.phy.autoneg_advertised = EMX_AUTONEG_ADV_DEFAULT;
1343 sc->hw.mac.autoneg = EMX_DO_AUTO_NEG;
1344 sc->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
1348 sc->hw.mac.autoneg = FALSE;
1349 sc->hw.phy.autoneg_advertised = 0;
1350 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
1351 sc->hw.mac.forced_speed_duplex = ADVERTISE_100_FULL;
1353 sc->hw.mac.forced_speed_duplex = ADVERTISE_100_HALF;
1357 sc->hw.mac.autoneg = FALSE;
1358 sc->hw.phy.autoneg_advertised = 0;
1359 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
1360 sc->hw.mac.forced_speed_duplex = ADVERTISE_10_FULL;
1362 sc->hw.mac.forced_speed_duplex = ADVERTISE_10_HALF;
1366 if_printf(ifp, "Unsupported media type\n");
1371 * As the speed/duplex settings my have changed we need to
1374 sc->hw.phy.reset_disable = FALSE;
1382 emx_encap(struct emx_softc *sc, struct mbuf **m_headp)
1384 bus_dma_segment_t segs[EMX_MAX_SCATTER];
1386 struct emx_txbuf *tx_buffer, *tx_buffer_mapped;
1387 struct e1000_tx_desc *ctxd = NULL;
1388 struct mbuf *m_head = *m_headp;
1389 uint32_t txd_upper, txd_lower, cmd = 0;
1390 int maxsegs, nsegs, i, j, first, last = 0, error;
1392 if (m_head->m_len < EMX_TXCSUM_MINHL &&
1393 (m_head->m_flags & EMX_CSUM_FEATURES)) {
1395 * Make sure that ethernet header and ip.ip_hl are in
1396 * contiguous memory, since if TXCSUM is enabled, later
1397 * TX context descriptor's setup need to access ip.ip_hl.
1399 error = emx_txcsum_pullup(sc, m_headp);
1401 KKASSERT(*m_headp == NULL);
1407 txd_upper = txd_lower = 0;
1410 * Capture the first descriptor index, this descriptor
1411 * will have the index of the EOP which is the only one
1412 * that now gets a DONE bit writeback.
1414 first = sc->next_avail_tx_desc;
1415 tx_buffer = &sc->tx_buf[first];
1416 tx_buffer_mapped = tx_buffer;
1417 map = tx_buffer->map;
1419 maxsegs = sc->num_tx_desc_avail - EMX_TX_RESERVED;
1420 KASSERT(maxsegs >= sc->spare_tx_desc, ("not enough spare TX desc\n"));
1421 if (maxsegs > EMX_MAX_SCATTER)
1422 maxsegs = EMX_MAX_SCATTER;
1424 error = bus_dmamap_load_mbuf_defrag(sc->txtag, map, m_headp,
1425 segs, maxsegs, &nsegs, BUS_DMA_NOWAIT);
1427 if (error == ENOBUFS)
1428 sc->mbuf_alloc_failed++;
1430 sc->no_tx_dma_setup++;
1436 bus_dmamap_sync(sc->txtag, map, BUS_DMASYNC_PREWRITE);
1439 sc->tx_nsegs += nsegs;
1441 if (m_head->m_pkthdr.csum_flags & EMX_CSUM_FEATURES) {
1442 /* TX csum offloading will consume one TX desc */
1443 sc->tx_nsegs += emx_txcsum(sc, m_head, &txd_upper, &txd_lower);
1445 i = sc->next_avail_tx_desc;
1447 /* Set up our transmit descriptors */
1448 for (j = 0; j < nsegs; j++) {
1449 tx_buffer = &sc->tx_buf[i];
1450 ctxd = &sc->tx_desc_base[i];
1452 ctxd->buffer_addr = htole64(segs[j].ds_addr);
1453 ctxd->lower.data = htole32(E1000_TXD_CMD_IFCS |
1454 txd_lower | segs[j].ds_len);
1455 ctxd->upper.data = htole32(txd_upper);
1458 if (++i == sc->num_tx_desc)
1462 sc->next_avail_tx_desc = i;
1464 KKASSERT(sc->num_tx_desc_avail > nsegs);
1465 sc->num_tx_desc_avail -= nsegs;
1467 /* Handle VLAN tag */
1468 if (m_head->m_flags & M_VLANTAG) {
1469 /* Set the vlan id. */
1470 ctxd->upper.fields.special =
1471 htole16(m_head->m_pkthdr.ether_vlantag);
1473 /* Tell hardware to add tag */
1474 ctxd->lower.data |= htole32(E1000_TXD_CMD_VLE);
1477 tx_buffer->m_head = m_head;
1478 tx_buffer_mapped->map = tx_buffer->map;
1479 tx_buffer->map = map;
1481 if (sc->tx_nsegs >= sc->tx_int_nsegs) {
1485 * Report Status (RS) is turned on
1486 * every tx_int_nsegs descriptors.
1488 cmd = E1000_TXD_CMD_RS;
1491 * Keep track of the descriptor, which will
1492 * be written back by hardware.
1494 sc->tx_dd[sc->tx_dd_tail] = last;
1495 EMX_INC_TXDD_IDX(sc->tx_dd_tail);
1496 KKASSERT(sc->tx_dd_tail != sc->tx_dd_head);
1500 * Last Descriptor of Packet needs End Of Packet (EOP)
1502 ctxd->lower.data |= htole32(E1000_TXD_CMD_EOP | cmd);
1505 * Advance the Transmit Descriptor Tail (TDT), this tells
1506 * the E1000 that this frame is available to transmit.
1508 E1000_WRITE_REG(&sc->hw, E1000_TDT(0), i);
1514 emx_set_promisc(struct emx_softc *sc)
1516 struct ifnet *ifp = &sc->arpcom.ac_if;
1519 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL);
1521 if (ifp->if_flags & IFF_PROMISC) {
1522 reg_rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
1523 /* Turn this on if you want to see bad packets */
1525 reg_rctl |= E1000_RCTL_SBP;
1526 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl);
1527 } else if (ifp->if_flags & IFF_ALLMULTI) {
1528 reg_rctl |= E1000_RCTL_MPE;
1529 reg_rctl &= ~E1000_RCTL_UPE;
1530 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl);
1535 emx_disable_promisc(struct emx_softc *sc)
1539 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL);
1541 reg_rctl &= ~E1000_RCTL_UPE;
1542 reg_rctl &= ~E1000_RCTL_MPE;
1543 reg_rctl &= ~E1000_RCTL_SBP;
1544 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl);
1548 emx_set_multi(struct emx_softc *sc)
1550 struct ifnet *ifp = &sc->arpcom.ac_if;
1551 struct ifmultiaddr *ifma;
1552 uint32_t reg_rctl = 0;
1553 uint8_t mta[512]; /* Largest MTS is 4096 bits */
1556 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1557 if (ifma->ifma_addr->sa_family != AF_LINK)
1560 if (mcnt == EMX_MCAST_ADDR_MAX)
1563 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
1564 &mta[mcnt * ETHER_ADDR_LEN], ETHER_ADDR_LEN);
1568 if (mcnt >= EMX_MCAST_ADDR_MAX) {
1569 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL);
1570 reg_rctl |= E1000_RCTL_MPE;
1571 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl);
1573 e1000_update_mc_addr_list(&sc->hw, mta,
1574 mcnt, 1, sc->hw.mac.rar_entry_count);
1579 * This routine checks for link status and updates statistics.
1582 emx_timer(void *xsc)
1584 struct emx_softc *sc = xsc;
1585 struct ifnet *ifp = &sc->arpcom.ac_if;
1587 ifnet_serialize_all(ifp);
1589 emx_update_link_status(sc);
1590 emx_update_stats(sc);
1592 /* Reset LAA into RAR[0] on 82571 */
1593 if (e1000_get_laa_state_82571(&sc->hw) == TRUE)
1594 e1000_rar_set(&sc->hw, sc->hw.mac.addr, 0);
1596 if (emx_display_debug_stats && (ifp->if_flags & IFF_RUNNING))
1597 emx_print_hw_stats(sc);
1601 callout_reset(&sc->timer, hz, emx_timer, sc);
1603 ifnet_deserialize_all(ifp);
1607 emx_update_link_status(struct emx_softc *sc)
1609 struct e1000_hw *hw = &sc->hw;
1610 struct ifnet *ifp = &sc->arpcom.ac_if;
1611 device_t dev = sc->dev;
1612 uint32_t link_check = 0;
1614 /* Get the cached link value or read phy for real */
1615 switch (hw->phy.media_type) {
1616 case e1000_media_type_copper:
1617 if (hw->mac.get_link_status) {
1618 /* Do the work to read phy */
1619 e1000_check_for_link(hw);
1620 link_check = !hw->mac.get_link_status;
1621 if (link_check) /* ESB2 fix */
1622 e1000_cfg_on_link_up(hw);
1628 case e1000_media_type_fiber:
1629 e1000_check_for_link(hw);
1630 link_check = E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU;
1633 case e1000_media_type_internal_serdes:
1634 e1000_check_for_link(hw);
1635 link_check = sc->hw.mac.serdes_has_link;
1638 case e1000_media_type_unknown:
1643 /* Now check for a transition */
1644 if (link_check && sc->link_active == 0) {
1645 e1000_get_speed_and_duplex(hw, &sc->link_speed,
1649 * Check if we should enable/disable SPEED_MODE bit on
1652 if (hw->mac.type == e1000_82571 ||
1653 hw->mac.type == e1000_82572) {
1656 tarc0 = E1000_READ_REG(hw, E1000_TARC(0));
1657 if (sc->link_speed != SPEED_1000)
1658 tarc0 &= ~EMX_TARC_SPEED_MODE;
1660 tarc0 |= EMX_TARC_SPEED_MODE;
1661 E1000_WRITE_REG(hw, E1000_TARC(0), tarc0);
1664 device_printf(dev, "Link is up %d Mbps %s\n",
1666 ((sc->link_duplex == FULL_DUPLEX) ?
1667 "Full Duplex" : "Half Duplex"));
1669 sc->link_active = 1;
1671 ifp->if_baudrate = sc->link_speed * 1000000;
1672 ifp->if_link_state = LINK_STATE_UP;
1673 if_link_state_change(ifp);
1674 } else if (!link_check && sc->link_active == 1) {
1675 ifp->if_baudrate = sc->link_speed = 0;
1676 sc->link_duplex = 0;
1678 device_printf(dev, "Link is Down\n");
1679 sc->link_active = 0;
1681 /* Link down, disable watchdog */
1684 ifp->if_link_state = LINK_STATE_DOWN;
1685 if_link_state_change(ifp);
1690 emx_stop(struct emx_softc *sc)
1692 struct ifnet *ifp = &sc->arpcom.ac_if;
1695 ASSERT_IFNET_SERIALIZED_ALL(ifp);
1697 emx_disable_intr(sc);
1699 callout_stop(&sc->timer);
1701 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1705 * Disable multiple receive queues.
1708 * We should disable multiple receive queues before
1709 * resetting the hardware.
1711 E1000_WRITE_REG(&sc->hw, E1000_MRQC, 0);
1713 e1000_reset_hw(&sc->hw);
1714 E1000_WRITE_REG(&sc->hw, E1000_WUC, 0);
1716 for (i = 0; i < sc->num_tx_desc; i++) {
1717 struct emx_txbuf *tx_buffer = &sc->tx_buf[i];
1719 if (tx_buffer->m_head != NULL) {
1720 bus_dmamap_unload(sc->txtag, tx_buffer->map);
1721 m_freem(tx_buffer->m_head);
1722 tx_buffer->m_head = NULL;
1726 for (i = 0; i < sc->rx_ring_inuse; ++i)
1727 emx_free_rx_ring(sc, &sc->rx_data[i]);
1731 sc->csum_iphlen = 0;
1739 emx_hw_init(struct emx_softc *sc)
1741 device_t dev = sc->dev;
1742 uint16_t rx_buffer_size;
1744 /* Issue a global reset */
1745 e1000_reset_hw(&sc->hw);
1747 /* Get control from any management/hw control */
1748 if (sc->hw.mac.type == e1000_82573 &&
1749 e1000_check_mng_mode(&sc->hw))
1750 emx_get_hw_control(sc);
1752 /* Set up smart power down as default off on newer adapters. */
1753 if (!emx_smart_pwr_down &&
1754 (sc->hw.mac.type == e1000_82571 ||
1755 sc->hw.mac.type == e1000_82572)) {
1756 uint16_t phy_tmp = 0;
1758 /* Speed up time to link by disabling smart power down. */
1759 e1000_read_phy_reg(&sc->hw,
1760 IGP02E1000_PHY_POWER_MGMT, &phy_tmp);
1761 phy_tmp &= ~IGP02E1000_PM_SPD;
1762 e1000_write_phy_reg(&sc->hw,
1763 IGP02E1000_PHY_POWER_MGMT, phy_tmp);
1767 * These parameters control the automatic generation (Tx) and
1768 * response (Rx) to Ethernet PAUSE frames.
1769 * - High water mark should allow for at least two frames to be
1770 * received after sending an XOFF.
1771 * - Low water mark works best when it is very near the high water mark.
1772 * This allows the receiver to restart by sending XON when it has
1773 * drained a bit. Here we use an arbitary value of 1500 which will
1774 * restart after one full frame is pulled from the buffer. There
1775 * could be several smaller frames in the buffer and if so they will
1776 * not trigger the XON until their total number reduces the buffer
1778 * - The pause time is fairly large at 1000 x 512ns = 512 usec.
1780 rx_buffer_size = (E1000_READ_REG(&sc->hw, E1000_PBA) & 0xffff) << 10;
1782 sc->hw.fc.high_water = rx_buffer_size -
1783 roundup2(sc->max_frame_size, 1024);
1784 sc->hw.fc.low_water = sc->hw.fc.high_water - 1500;
1786 if (sc->hw.mac.type == e1000_80003es2lan)
1787 sc->hw.fc.pause_time = 0xFFFF;
1789 sc->hw.fc.pause_time = EMX_FC_PAUSE_TIME;
1790 sc->hw.fc.send_xon = TRUE;
1791 sc->hw.fc.requested_mode = e1000_fc_full;
1793 if (e1000_init_hw(&sc->hw) < 0) {
1794 device_printf(dev, "Hardware Initialization Failed\n");
1798 e1000_check_for_link(&sc->hw);
1804 emx_setup_ifp(struct emx_softc *sc)
1806 struct ifnet *ifp = &sc->arpcom.ac_if;
1808 if_initname(ifp, device_get_name(sc->dev),
1809 device_get_unit(sc->dev));
1811 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1812 ifp->if_init = emx_init;
1813 ifp->if_ioctl = emx_ioctl;
1814 ifp->if_start = emx_start;
1815 #ifdef DEVICE_POLLING
1816 ifp->if_poll = emx_poll;
1818 ifp->if_watchdog = emx_watchdog;
1819 ifp->if_serialize = emx_serialize;
1820 ifp->if_deserialize = emx_deserialize;
1821 ifp->if_tryserialize = emx_tryserialize;
1823 ifp->if_serialize_assert = emx_serialize_assert;
1825 ifq_set_maxlen(&ifp->if_snd, sc->num_tx_desc - 1);
1826 ifq_set_ready(&ifp->if_snd);
1828 ether_ifattach(ifp, sc->hw.mac.addr, NULL);
1830 ifp->if_capabilities = IFCAP_HWCSUM |
1831 IFCAP_VLAN_HWTAGGING |
1833 if (sc->rx_ring_cnt > 1)
1834 ifp->if_capabilities |= IFCAP_RSS;
1835 ifp->if_capenable = ifp->if_capabilities;
1836 ifp->if_hwassist = EMX_CSUM_FEATURES;
1839 * Tell the upper layer(s) we support long frames.
1841 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
1844 * Specify the media types supported by this sc and register
1845 * callbacks to update media and link information
1847 ifmedia_init(&sc->media, IFM_IMASK,
1848 emx_media_change, emx_media_status);
1849 if (sc->hw.phy.media_type == e1000_media_type_fiber ||
1850 sc->hw.phy.media_type == e1000_media_type_internal_serdes) {
1851 ifmedia_add(&sc->media, IFM_ETHER | IFM_1000_SX | IFM_FDX,
1853 ifmedia_add(&sc->media, IFM_ETHER | IFM_1000_SX, 0, NULL);
1855 ifmedia_add(&sc->media, IFM_ETHER | IFM_10_T, 0, NULL);
1856 ifmedia_add(&sc->media, IFM_ETHER | IFM_10_T | IFM_FDX,
1858 ifmedia_add(&sc->media, IFM_ETHER | IFM_100_TX, 0, NULL);
1859 ifmedia_add(&sc->media, IFM_ETHER | IFM_100_TX | IFM_FDX,
1861 if (sc->hw.phy.type != e1000_phy_ife) {
1862 ifmedia_add(&sc->media,
1863 IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL);
1864 ifmedia_add(&sc->media,
1865 IFM_ETHER | IFM_1000_T, 0, NULL);
1868 ifmedia_add(&sc->media, IFM_ETHER | IFM_AUTO, 0, NULL);
1869 ifmedia_set(&sc->media, IFM_ETHER | IFM_AUTO);
1873 * Workaround for SmartSpeed on 82541 and 82547 controllers
1876 emx_smartspeed(struct emx_softc *sc)
1880 if (sc->link_active || sc->hw.phy.type != e1000_phy_igp ||
1881 sc->hw.mac.autoneg == 0 ||
1882 (sc->hw.phy.autoneg_advertised & ADVERTISE_1000_FULL) == 0)
1885 if (sc->smartspeed == 0) {
1887 * If Master/Slave config fault is asserted twice,
1888 * we assume back-to-back
1890 e1000_read_phy_reg(&sc->hw, PHY_1000T_STATUS, &phy_tmp);
1891 if (!(phy_tmp & SR_1000T_MS_CONFIG_FAULT))
1893 e1000_read_phy_reg(&sc->hw, PHY_1000T_STATUS, &phy_tmp);
1894 if (phy_tmp & SR_1000T_MS_CONFIG_FAULT) {
1895 e1000_read_phy_reg(&sc->hw,
1896 PHY_1000T_CTRL, &phy_tmp);
1897 if (phy_tmp & CR_1000T_MS_ENABLE) {
1898 phy_tmp &= ~CR_1000T_MS_ENABLE;
1899 e1000_write_phy_reg(&sc->hw,
1900 PHY_1000T_CTRL, phy_tmp);
1902 if (sc->hw.mac.autoneg &&
1903 !e1000_phy_setup_autoneg(&sc->hw) &&
1904 !e1000_read_phy_reg(&sc->hw,
1905 PHY_CONTROL, &phy_tmp)) {
1906 phy_tmp |= MII_CR_AUTO_NEG_EN |
1907 MII_CR_RESTART_AUTO_NEG;
1908 e1000_write_phy_reg(&sc->hw,
1909 PHY_CONTROL, phy_tmp);
1914 } else if (sc->smartspeed == EMX_SMARTSPEED_DOWNSHIFT) {
1915 /* If still no link, perhaps using 2/3 pair cable */
1916 e1000_read_phy_reg(&sc->hw, PHY_1000T_CTRL, &phy_tmp);
1917 phy_tmp |= CR_1000T_MS_ENABLE;
1918 e1000_write_phy_reg(&sc->hw, PHY_1000T_CTRL, phy_tmp);
1919 if (sc->hw.mac.autoneg &&
1920 !e1000_phy_setup_autoneg(&sc->hw) &&
1921 !e1000_read_phy_reg(&sc->hw, PHY_CONTROL, &phy_tmp)) {
1922 phy_tmp |= MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG;
1923 e1000_write_phy_reg(&sc->hw, PHY_CONTROL, phy_tmp);
1927 /* Restart process after EMX_SMARTSPEED_MAX iterations */
1928 if (sc->smartspeed++ == EMX_SMARTSPEED_MAX)
1933 emx_create_tx_ring(struct emx_softc *sc)
1935 device_t dev = sc->dev;
1936 struct emx_txbuf *tx_buffer;
1937 int error, i, tsize;
1940 * Validate number of transmit descriptors. It must not exceed
1941 * hardware maximum, and must be multiple of E1000_DBA_ALIGN.
1943 if ((emx_txd * sizeof(struct e1000_tx_desc)) % EMX_DBA_ALIGN != 0 ||
1944 emx_txd > EMX_MAX_TXD || emx_txd < EMX_MIN_TXD) {
1945 device_printf(dev, "Using %d TX descriptors instead of %d!\n",
1946 EMX_DEFAULT_TXD, emx_txd);
1947 sc->num_tx_desc = EMX_DEFAULT_TXD;
1949 sc->num_tx_desc = emx_txd;
1953 * Allocate Transmit Descriptor ring
1955 tsize = roundup2(sc->num_tx_desc * sizeof(struct e1000_tx_desc),
1957 sc->tx_desc_base = bus_dmamem_coherent_any(sc->parent_dtag,
1958 EMX_DBA_ALIGN, tsize, BUS_DMA_WAITOK,
1959 &sc->tx_desc_dtag, &sc->tx_desc_dmap,
1960 &sc->tx_desc_paddr);
1961 if (sc->tx_desc_base == NULL) {
1962 device_printf(dev, "Unable to allocate tx_desc memory\n");
1966 sc->tx_buf = kmalloc(sizeof(struct emx_txbuf) * sc->num_tx_desc,
1967 M_DEVBUF, M_WAITOK | M_ZERO);
1970 * Create DMA tags for tx buffers
1972 error = bus_dma_tag_create(sc->parent_dtag, /* parent */
1973 1, 0, /* alignment, bounds */
1974 BUS_SPACE_MAXADDR, /* lowaddr */
1975 BUS_SPACE_MAXADDR, /* highaddr */
1976 NULL, NULL, /* filter, filterarg */
1977 EMX_TSO_SIZE, /* maxsize */
1978 EMX_MAX_SCATTER, /* nsegments */
1979 EMX_MAX_SEGSIZE, /* maxsegsize */
1980 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW |
1981 BUS_DMA_ONEBPAGE, /* flags */
1984 device_printf(dev, "Unable to allocate TX DMA tag\n");
1985 kfree(sc->tx_buf, M_DEVBUF);
1991 * Create DMA maps for tx buffers
1993 for (i = 0; i < sc->num_tx_desc; i++) {
1994 tx_buffer = &sc->tx_buf[i];
1996 error = bus_dmamap_create(sc->txtag,
1997 BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE,
2000 device_printf(dev, "Unable to create TX DMA map\n");
2001 emx_destroy_tx_ring(sc, i);
2009 emx_init_tx_ring(struct emx_softc *sc)
2011 /* Clear the old ring contents */
2012 bzero(sc->tx_desc_base,
2013 sizeof(struct e1000_tx_desc) * sc->num_tx_desc);
2016 sc->next_avail_tx_desc = 0;
2017 sc->next_tx_to_clean = 0;
2018 sc->num_tx_desc_avail = sc->num_tx_desc;
2022 emx_init_tx_unit(struct emx_softc *sc)
2024 uint32_t tctl, tarc, tipg = 0;
2027 /* Setup the Base and Length of the Tx Descriptor Ring */
2028 bus_addr = sc->tx_desc_paddr;
2029 E1000_WRITE_REG(&sc->hw, E1000_TDLEN(0),
2030 sc->num_tx_desc * sizeof(struct e1000_tx_desc));
2031 E1000_WRITE_REG(&sc->hw, E1000_TDBAH(0),
2032 (uint32_t)(bus_addr >> 32));
2033 E1000_WRITE_REG(&sc->hw, E1000_TDBAL(0),
2034 (uint32_t)bus_addr);
2035 /* Setup the HW Tx Head and Tail descriptor pointers */
2036 E1000_WRITE_REG(&sc->hw, E1000_TDT(0), 0);
2037 E1000_WRITE_REG(&sc->hw, E1000_TDH(0), 0);
2039 /* Set the default values for the Tx Inter Packet Gap timer */
2040 switch (sc->hw.mac.type) {
2041 case e1000_80003es2lan:
2042 tipg = DEFAULT_82543_TIPG_IPGR1;
2043 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGR2 <<
2044 E1000_TIPG_IPGR2_SHIFT;
2048 if (sc->hw.phy.media_type == e1000_media_type_fiber ||
2049 sc->hw.phy.media_type == e1000_media_type_internal_serdes)
2050 tipg = DEFAULT_82543_TIPG_IPGT_FIBER;
2052 tipg = DEFAULT_82543_TIPG_IPGT_COPPER;
2053 tipg |= DEFAULT_82543_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT;
2054 tipg |= DEFAULT_82543_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT;
2058 E1000_WRITE_REG(&sc->hw, E1000_TIPG, tipg);
2060 /* NOTE: 0 is not allowed for TIDV */
2061 E1000_WRITE_REG(&sc->hw, E1000_TIDV, 1);
2062 E1000_WRITE_REG(&sc->hw, E1000_TADV, 0);
2064 if (sc->hw.mac.type == e1000_82571 ||
2065 sc->hw.mac.type == e1000_82572) {
2066 tarc = E1000_READ_REG(&sc->hw, E1000_TARC(0));
2067 tarc |= EMX_TARC_SPEED_MODE;
2068 E1000_WRITE_REG(&sc->hw, E1000_TARC(0), tarc);
2069 } else if (sc->hw.mac.type == e1000_80003es2lan) {
2070 tarc = E1000_READ_REG(&sc->hw, E1000_TARC(0));
2072 E1000_WRITE_REG(&sc->hw, E1000_TARC(0), tarc);
2073 tarc = E1000_READ_REG(&sc->hw, E1000_TARC(1));
2075 E1000_WRITE_REG(&sc->hw, E1000_TARC(1), tarc);
2078 /* Program the Transmit Control Register */
2079 tctl = E1000_READ_REG(&sc->hw, E1000_TCTL);
2080 tctl &= ~E1000_TCTL_CT;
2081 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC | E1000_TCTL_EN |
2082 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
2083 tctl |= E1000_TCTL_MULR;
2085 /* This write will effectively turn on the transmit unit. */
2086 E1000_WRITE_REG(&sc->hw, E1000_TCTL, tctl);
2090 emx_destroy_tx_ring(struct emx_softc *sc, int ndesc)
2092 struct emx_txbuf *tx_buffer;
2095 /* Free Transmit Descriptor ring */
2096 if (sc->tx_desc_base) {
2097 bus_dmamap_unload(sc->tx_desc_dtag, sc->tx_desc_dmap);
2098 bus_dmamem_free(sc->tx_desc_dtag, sc->tx_desc_base,
2100 bus_dma_tag_destroy(sc->tx_desc_dtag);
2102 sc->tx_desc_base = NULL;
2105 if (sc->tx_buf == NULL)
2108 for (i = 0; i < ndesc; i++) {
2109 tx_buffer = &sc->tx_buf[i];
2111 KKASSERT(tx_buffer->m_head == NULL);
2112 bus_dmamap_destroy(sc->txtag, tx_buffer->map);
2114 bus_dma_tag_destroy(sc->txtag);
2116 kfree(sc->tx_buf, M_DEVBUF);
2121 * The offload context needs to be set when we transfer the first
2122 * packet of a particular protocol (TCP/UDP). This routine has been
2123 * enhanced to deal with inserted VLAN headers.
2125 * If the new packet's ether header length, ip header length and
2126 * csum offloading type are same as the previous packet, we should
2127 * avoid allocating a new csum context descriptor; mainly to take
2128 * advantage of the pipeline effect of the TX data read request.
2130 * This function returns number of TX descrptors allocated for
2134 emx_txcsum(struct emx_softc *sc, struct mbuf *mp,
2135 uint32_t *txd_upper, uint32_t *txd_lower)
2137 struct e1000_context_desc *TXD;
2138 struct emx_txbuf *tx_buffer;
2139 struct ether_vlan_header *eh;
2141 int curr_txd, ehdrlen, csum_flags;
2142 uint32_t cmd, hdr_len, ip_hlen;
2146 * Determine where frame payload starts.
2147 * Jump over vlan headers if already present,
2148 * helpful for QinQ too.
2150 KASSERT(mp->m_len >= ETHER_HDR_LEN,
2151 ("emx_txcsum_pullup is not called (eh)?\n"));
2152 eh = mtod(mp, struct ether_vlan_header *);
2153 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) {
2154 KASSERT(mp->m_len >= ETHER_HDR_LEN + EVL_ENCAPLEN,
2155 ("emx_txcsum_pullup is not called (evh)?\n"));
2156 etype = ntohs(eh->evl_proto);
2157 ehdrlen = ETHER_HDR_LEN + EVL_ENCAPLEN;
2159 etype = ntohs(eh->evl_encap_proto);
2160 ehdrlen = ETHER_HDR_LEN;
2164 * We only support TCP/UDP for IPv4 for the moment.
2165 * TODO: Support SCTP too when it hits the tree.
2167 if (etype != ETHERTYPE_IP)
2170 KASSERT(mp->m_len >= ehdrlen + EMX_IPVHL_SIZE,
2171 ("emx_txcsum_pullup is not called (eh+ip_vhl)?\n"));
2173 /* NOTE: We could only safely access ip.ip_vhl part */
2174 ip = (struct ip *)(mp->m_data + ehdrlen);
2175 ip_hlen = ip->ip_hl << 2;
2177 csum_flags = mp->m_pkthdr.csum_flags & EMX_CSUM_FEATURES;
2179 if (sc->csum_ehlen == ehdrlen && sc->csum_iphlen == ip_hlen &&
2180 sc->csum_flags == csum_flags) {
2182 * Same csum offload context as the previous packets;
2185 *txd_upper = sc->csum_txd_upper;
2186 *txd_lower = sc->csum_txd_lower;
2191 * Setup a new csum offload context.
2194 curr_txd = sc->next_avail_tx_desc;
2195 tx_buffer = &sc->tx_buf[curr_txd];
2196 TXD = (struct e1000_context_desc *)&sc->tx_desc_base[curr_txd];
2200 /* Setup of IP header checksum. */
2201 if (csum_flags & CSUM_IP) {
2203 * Start offset for header checksum calculation.
2204 * End offset for header checksum calculation.
2205 * Offset of place to put the checksum.
2207 TXD->lower_setup.ip_fields.ipcss = ehdrlen;
2208 TXD->lower_setup.ip_fields.ipcse =
2209 htole16(ehdrlen + ip_hlen - 1);
2210 TXD->lower_setup.ip_fields.ipcso =
2211 ehdrlen + offsetof(struct ip, ip_sum);
2212 cmd |= E1000_TXD_CMD_IP;
2213 *txd_upper |= E1000_TXD_POPTS_IXSM << 8;
2215 hdr_len = ehdrlen + ip_hlen;
2217 if (csum_flags & CSUM_TCP) {
2219 * Start offset for payload checksum calculation.
2220 * End offset for payload checksum calculation.
2221 * Offset of place to put the checksum.
2223 TXD->upper_setup.tcp_fields.tucss = hdr_len;
2224 TXD->upper_setup.tcp_fields.tucse = htole16(0);
2225 TXD->upper_setup.tcp_fields.tucso =
2226 hdr_len + offsetof(struct tcphdr, th_sum);
2227 cmd |= E1000_TXD_CMD_TCP;
2228 *txd_upper |= E1000_TXD_POPTS_TXSM << 8;
2229 } else if (csum_flags & CSUM_UDP) {
2231 * Start offset for header checksum calculation.
2232 * End offset for header checksum calculation.
2233 * Offset of place to put the checksum.
2235 TXD->upper_setup.tcp_fields.tucss = hdr_len;
2236 TXD->upper_setup.tcp_fields.tucse = htole16(0);
2237 TXD->upper_setup.tcp_fields.tucso =
2238 hdr_len + offsetof(struct udphdr, uh_sum);
2239 *txd_upper |= E1000_TXD_POPTS_TXSM << 8;
2242 *txd_lower = E1000_TXD_CMD_DEXT | /* Extended descr type */
2243 E1000_TXD_DTYP_D; /* Data descr */
2245 /* Save the information for this csum offloading context */
2246 sc->csum_ehlen = ehdrlen;
2247 sc->csum_iphlen = ip_hlen;
2248 sc->csum_flags = csum_flags;
2249 sc->csum_txd_upper = *txd_upper;
2250 sc->csum_txd_lower = *txd_lower;
2252 TXD->tcp_seg_setup.data = htole32(0);
2253 TXD->cmd_and_length =
2254 htole32(E1000_TXD_CMD_IFCS | E1000_TXD_CMD_DEXT | cmd);
2256 if (++curr_txd == sc->num_tx_desc)
2259 KKASSERT(sc->num_tx_desc_avail > 0);
2260 sc->num_tx_desc_avail--;
2262 sc->next_avail_tx_desc = curr_txd;
2267 emx_txcsum_pullup(struct emx_softc *sc, struct mbuf **m0)
2269 struct mbuf *m = *m0;
2270 struct ether_header *eh;
2273 sc->tx_csum_try_pullup++;
2275 len = ETHER_HDR_LEN + EMX_IPVHL_SIZE;
2277 if (__predict_false(!M_WRITABLE(m))) {
2278 if (__predict_false(m->m_len < ETHER_HDR_LEN)) {
2279 sc->tx_csum_drop1++;
2284 eh = mtod(m, struct ether_header *);
2286 if (eh->ether_type == htons(ETHERTYPE_VLAN))
2287 len += EVL_ENCAPLEN;
2289 if (m->m_len < len) {
2290 sc->tx_csum_drop2++;
2298 if (__predict_false(m->m_len < ETHER_HDR_LEN)) {
2299 sc->tx_csum_pullup1++;
2300 m = m_pullup(m, ETHER_HDR_LEN);
2302 sc->tx_csum_pullup1_failed++;
2308 eh = mtod(m, struct ether_header *);
2310 if (eh->ether_type == htons(ETHERTYPE_VLAN))
2311 len += EVL_ENCAPLEN;
2313 if (m->m_len < len) {
2314 sc->tx_csum_pullup2++;
2315 m = m_pullup(m, len);
2317 sc->tx_csum_pullup2_failed++;
2327 emx_txeof(struct emx_softc *sc)
2329 struct ifnet *ifp = &sc->arpcom.ac_if;
2330 struct emx_txbuf *tx_buffer;
2331 int first, num_avail;
2333 if (sc->tx_dd_head == sc->tx_dd_tail)
2336 if (sc->num_tx_desc_avail == sc->num_tx_desc)
2339 num_avail = sc->num_tx_desc_avail;
2340 first = sc->next_tx_to_clean;
2342 while (sc->tx_dd_head != sc->tx_dd_tail) {
2343 int dd_idx = sc->tx_dd[sc->tx_dd_head];
2344 struct e1000_tx_desc *tx_desc;
2346 tx_desc = &sc->tx_desc_base[dd_idx];
2347 if (tx_desc->upper.fields.status & E1000_TXD_STAT_DD) {
2348 EMX_INC_TXDD_IDX(sc->tx_dd_head);
2350 if (++dd_idx == sc->num_tx_desc)
2353 while (first != dd_idx) {
2358 tx_buffer = &sc->tx_buf[first];
2359 if (tx_buffer->m_head) {
2361 bus_dmamap_unload(sc->txtag,
2363 m_freem(tx_buffer->m_head);
2364 tx_buffer->m_head = NULL;
2367 if (++first == sc->num_tx_desc)
2374 sc->next_tx_to_clean = first;
2375 sc->num_tx_desc_avail = num_avail;
2377 if (sc->tx_dd_head == sc->tx_dd_tail) {
2382 if (!EMX_IS_OACTIVE(sc)) {
2383 ifp->if_flags &= ~IFF_OACTIVE;
2385 /* All clean, turn off the timer */
2386 if (sc->num_tx_desc_avail == sc->num_tx_desc)
2392 emx_tx_collect(struct emx_softc *sc)
2394 struct ifnet *ifp = &sc->arpcom.ac_if;
2395 struct emx_txbuf *tx_buffer;
2396 int tdh, first, num_avail, dd_idx = -1;
2398 if (sc->num_tx_desc_avail == sc->num_tx_desc)
2401 tdh = E1000_READ_REG(&sc->hw, E1000_TDH(0));
2402 if (tdh == sc->next_tx_to_clean)
2405 if (sc->tx_dd_head != sc->tx_dd_tail)
2406 dd_idx = sc->tx_dd[sc->tx_dd_head];
2408 num_avail = sc->num_tx_desc_avail;
2409 first = sc->next_tx_to_clean;
2411 while (first != tdh) {
2416 tx_buffer = &sc->tx_buf[first];
2417 if (tx_buffer->m_head) {
2419 bus_dmamap_unload(sc->txtag,
2421 m_freem(tx_buffer->m_head);
2422 tx_buffer->m_head = NULL;
2425 if (first == dd_idx) {
2426 EMX_INC_TXDD_IDX(sc->tx_dd_head);
2427 if (sc->tx_dd_head == sc->tx_dd_tail) {
2432 dd_idx = sc->tx_dd[sc->tx_dd_head];
2436 if (++first == sc->num_tx_desc)
2439 sc->next_tx_to_clean = first;
2440 sc->num_tx_desc_avail = num_avail;
2442 if (!EMX_IS_OACTIVE(sc)) {
2443 ifp->if_flags &= ~IFF_OACTIVE;
2445 /* All clean, turn off the timer */
2446 if (sc->num_tx_desc_avail == sc->num_tx_desc)
2452 * When Link is lost sometimes there is work still in the TX ring
2453 * which will result in a watchdog, rather than allow that do an
2454 * attempted cleanup and then reinit here. Note that this has been
2455 * seens mostly with fiber adapters.
2458 emx_tx_purge(struct emx_softc *sc)
2460 struct ifnet *ifp = &sc->arpcom.ac_if;
2462 if (!sc->link_active && ifp->if_timer) {
2464 if (ifp->if_timer) {
2465 if_printf(ifp, "Link lost, TX pending, reinit\n");
2473 emx_newbuf(struct emx_softc *sc, struct emx_rxdata *rdata, int i, int init)
2476 bus_dma_segment_t seg;
2478 struct emx_rxbuf *rx_buffer;
2481 m = m_getcl(init ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR);
2483 rdata->mbuf_cluster_failed++;
2485 if_printf(&sc->arpcom.ac_if,
2486 "Unable to allocate RX mbuf\n");
2490 m->m_len = m->m_pkthdr.len = MCLBYTES;
2492 if (sc->max_frame_size <= MCLBYTES - ETHER_ALIGN)
2493 m_adj(m, ETHER_ALIGN);
2495 error = bus_dmamap_load_mbuf_segment(rdata->rxtag,
2496 rdata->rx_sparemap, m,
2497 &seg, 1, &nseg, BUS_DMA_NOWAIT);
2501 if_printf(&sc->arpcom.ac_if,
2502 "Unable to load RX mbuf\n");
2507 rx_buffer = &rdata->rx_buf[i];
2508 if (rx_buffer->m_head != NULL)
2509 bus_dmamap_unload(rdata->rxtag, rx_buffer->map);
2511 map = rx_buffer->map;
2512 rx_buffer->map = rdata->rx_sparemap;
2513 rdata->rx_sparemap = map;
2515 rx_buffer->m_head = m;
2516 rx_buffer->paddr = seg.ds_addr;
2518 emx_setup_rxdesc(&rdata->rx_desc[i], rx_buffer);
2523 emx_create_rx_ring(struct emx_softc *sc, struct emx_rxdata *rdata)
2525 device_t dev = sc->dev;
2526 struct emx_rxbuf *rx_buffer;
2527 int i, error, rsize;
2530 * Validate number of receive descriptors. It must not exceed
2531 * hardware maximum, and must be multiple of E1000_DBA_ALIGN.
2533 if ((emx_rxd * sizeof(emx_rxdesc_t)) % EMX_DBA_ALIGN != 0 ||
2534 emx_rxd > EMX_MAX_RXD || emx_rxd < EMX_MIN_RXD) {
2535 device_printf(dev, "Using %d RX descriptors instead of %d!\n",
2536 EMX_DEFAULT_RXD, emx_rxd);
2537 rdata->num_rx_desc = EMX_DEFAULT_RXD;
2539 rdata->num_rx_desc = emx_rxd;
2543 * Allocate Receive Descriptor ring
2545 rsize = roundup2(rdata->num_rx_desc * sizeof(emx_rxdesc_t),
2547 rdata->rx_desc = bus_dmamem_coherent_any(sc->parent_dtag,
2548 EMX_DBA_ALIGN, rsize, BUS_DMA_WAITOK,
2549 &rdata->rx_desc_dtag, &rdata->rx_desc_dmap,
2550 &rdata->rx_desc_paddr);
2551 if (rdata->rx_desc == NULL) {
2552 device_printf(dev, "Unable to allocate rx_desc memory\n");
2556 rdata->rx_buf = kmalloc(sizeof(struct emx_rxbuf) * rdata->num_rx_desc,
2557 M_DEVBUF, M_WAITOK | M_ZERO);
2560 * Create DMA tag for rx buffers
2562 error = bus_dma_tag_create(sc->parent_dtag, /* parent */
2563 1, 0, /* alignment, bounds */
2564 BUS_SPACE_MAXADDR, /* lowaddr */
2565 BUS_SPACE_MAXADDR, /* highaddr */
2566 NULL, NULL, /* filter, filterarg */
2567 MCLBYTES, /* maxsize */
2569 MCLBYTES, /* maxsegsize */
2570 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, /* flags */
2573 device_printf(dev, "Unable to allocate RX DMA tag\n");
2574 kfree(rdata->rx_buf, M_DEVBUF);
2575 rdata->rx_buf = NULL;
2580 * Create spare DMA map for rx buffers
2582 error = bus_dmamap_create(rdata->rxtag, BUS_DMA_WAITOK,
2583 &rdata->rx_sparemap);
2585 device_printf(dev, "Unable to create spare RX DMA map\n");
2586 bus_dma_tag_destroy(rdata->rxtag);
2587 kfree(rdata->rx_buf, M_DEVBUF);
2588 rdata->rx_buf = NULL;
2593 * Create DMA maps for rx buffers
2595 for (i = 0; i < rdata->num_rx_desc; i++) {
2596 rx_buffer = &rdata->rx_buf[i];
2598 error = bus_dmamap_create(rdata->rxtag, BUS_DMA_WAITOK,
2601 device_printf(dev, "Unable to create RX DMA map\n");
2602 emx_destroy_rx_ring(sc, rdata, i);
2610 emx_free_rx_ring(struct emx_softc *sc, struct emx_rxdata *rdata)
2614 for (i = 0; i < rdata->num_rx_desc; i++) {
2615 struct emx_rxbuf *rx_buffer = &rdata->rx_buf[i];
2617 if (rx_buffer->m_head != NULL) {
2618 bus_dmamap_unload(rdata->rxtag, rx_buffer->map);
2619 m_freem(rx_buffer->m_head);
2620 rx_buffer->m_head = NULL;
2624 if (rdata->fmp != NULL)
2625 m_freem(rdata->fmp);
2631 emx_init_rx_ring(struct emx_softc *sc, struct emx_rxdata *rdata)
2635 /* Reset descriptor ring */
2636 bzero(rdata->rx_desc, sizeof(emx_rxdesc_t) * rdata->num_rx_desc);
2638 /* Allocate new ones. */
2639 for (i = 0; i < rdata->num_rx_desc; i++) {
2640 error = emx_newbuf(sc, rdata, i, 1);
2645 /* Setup our descriptor pointers */
2646 rdata->next_rx_desc_to_check = 0;
2652 emx_init_rx_unit(struct emx_softc *sc)
2654 struct ifnet *ifp = &sc->arpcom.ac_if;
2656 uint32_t rctl, rxcsum, rfctl;
2660 * Make sure receives are disabled while setting
2661 * up the descriptor ring
2663 rctl = E1000_READ_REG(&sc->hw, E1000_RCTL);
2664 E1000_WRITE_REG(&sc->hw, E1000_RCTL, rctl & ~E1000_RCTL_EN);
2667 * Set the interrupt throttling rate. Value is calculated
2668 * as ITR = 1 / (INT_THROTTLE_CEIL * 256ns)
2670 if (sc->int_throttle_ceil) {
2671 E1000_WRITE_REG(&sc->hw, E1000_ITR,
2672 1000000000 / 256 / sc->int_throttle_ceil);
2674 E1000_WRITE_REG(&sc->hw, E1000_ITR, 0);
2677 /* Use extended RX descriptor */
2678 rfctl = E1000_RFCTL_EXTEN;
2680 /* Disable accelerated ackknowledge */
2681 if (sc->hw.mac.type == e1000_82574)
2682 rfctl |= E1000_RFCTL_ACK_DIS;
2684 E1000_WRITE_REG(&sc->hw, E1000_RFCTL, rfctl);
2686 /* Setup the Base and Length of the Rx Descriptor Ring */
2687 for (i = 0; i < sc->rx_ring_inuse; ++i) {
2688 struct emx_rxdata *rdata = &sc->rx_data[i];
2690 bus_addr = rdata->rx_desc_paddr;
2691 E1000_WRITE_REG(&sc->hw, E1000_RDLEN(i),
2692 rdata->num_rx_desc * sizeof(emx_rxdesc_t));
2693 E1000_WRITE_REG(&sc->hw, E1000_RDBAH(i),
2694 (uint32_t)(bus_addr >> 32));
2695 E1000_WRITE_REG(&sc->hw, E1000_RDBAL(i),
2696 (uint32_t)bus_addr);
2699 /* Setup the Receive Control Register */
2700 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
2701 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_LBM_NO |
2702 E1000_RCTL_RDMTS_HALF | E1000_RCTL_SECRC |
2703 (sc->hw.mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
2705 /* Make sure VLAN Filters are off */
2706 rctl &= ~E1000_RCTL_VFE;
2708 /* Don't store bad paket */
2709 rctl &= ~E1000_RCTL_SBP;
2712 rctl |= E1000_RCTL_SZ_2048;
2714 if (ifp->if_mtu > ETHERMTU)
2715 rctl |= E1000_RCTL_LPE;
2717 rctl &= ~E1000_RCTL_LPE;
2720 * Receive Checksum Offload for TCP and UDP
2722 * Checksum offloading is also enabled if multiple receive
2723 * queue is to be supported, since we need it to figure out
2726 if (ifp->if_capenable & (IFCAP_RSS | IFCAP_RXCSUM)) {
2727 rxcsum = E1000_READ_REG(&sc->hw, E1000_RXCSUM);
2731 * PCSD must be enabled to enable multiple
2734 rxcsum |= E1000_RXCSUM_IPOFL | E1000_RXCSUM_TUOFL |
2736 E1000_WRITE_REG(&sc->hw, E1000_RXCSUM, rxcsum);
2740 * Configure multiple receive queue (RSS)
2742 if (ifp->if_capenable & IFCAP_RSS) {
2743 uint8_t key[EMX_NRSSRK * EMX_RSSRK_SIZE];
2746 KASSERT(sc->rx_ring_inuse == EMX_NRX_RING,
2747 ("invalid number of RX ring (%d)",
2748 sc->rx_ring_inuse));
2752 * When we reach here, RSS has already been disabled
2753 * in emx_stop(), so we could safely configure RSS key
2754 * and redirect table.
2760 toeplitz_get_key(key, sizeof(key));
2761 for (i = 0; i < EMX_NRSSRK; ++i) {
2764 rssrk = EMX_RSSRK_VAL(key, i);
2765 EMX_RSS_DPRINTF(sc, 1, "rssrk%d 0x%08x\n", i, rssrk);
2767 E1000_WRITE_REG(&sc->hw, E1000_RSSRK(i), rssrk);
2771 * Configure RSS redirect table in following fashion:
2772 * (hash & ring_cnt_mask) == rdr_table[(hash & rdr_table_mask)]
2775 for (i = 0; i < EMX_RETA_SIZE; ++i) {
2778 q = (i % sc->rx_ring_inuse) << EMX_RETA_RINGIDX_SHIFT;
2779 reta |= q << (8 * i);
2781 EMX_RSS_DPRINTF(sc, 1, "reta 0x%08x\n", reta);
2783 for (i = 0; i < EMX_NRETA; ++i)
2784 E1000_WRITE_REG(&sc->hw, E1000_RETA(i), reta);
2787 * Enable multiple receive queues.
2788 * Enable IPv4 RSS standard hash functions.
2789 * Disable RSS interrupt.
2791 E1000_WRITE_REG(&sc->hw, E1000_MRQC,
2792 E1000_MRQC_ENABLE_RSS_2Q |
2793 E1000_MRQC_RSS_FIELD_IPV4_TCP |
2794 E1000_MRQC_RSS_FIELD_IPV4);
2798 * XXX TEMPORARY WORKAROUND: on some systems with 82573
2799 * long latencies are observed, like Lenovo X60. This
2800 * change eliminates the problem, but since having positive
2801 * values in RDTR is a known source of problems on other
2802 * platforms another solution is being sought.
2804 if (emx_82573_workaround && sc->hw.mac.type == e1000_82573) {
2805 E1000_WRITE_REG(&sc->hw, E1000_RADV, EMX_RADV_82573);
2806 E1000_WRITE_REG(&sc->hw, E1000_RDTR, EMX_RDTR_82573);
2810 * Setup the HW Rx Head and Tail Descriptor Pointers
2812 for (i = 0; i < sc->rx_ring_inuse; ++i) {
2813 E1000_WRITE_REG(&sc->hw, E1000_RDH(i), 0);
2814 E1000_WRITE_REG(&sc->hw, E1000_RDT(i),
2815 sc->rx_data[i].num_rx_desc - 1);
2818 /* Enable Receives */
2819 E1000_WRITE_REG(&sc->hw, E1000_RCTL, rctl);
2823 emx_destroy_rx_ring(struct emx_softc *sc, struct emx_rxdata *rdata, int ndesc)
2825 struct emx_rxbuf *rx_buffer;
2828 /* Free Receive Descriptor ring */
2829 if (rdata->rx_desc) {
2830 bus_dmamap_unload(rdata->rx_desc_dtag, rdata->rx_desc_dmap);
2831 bus_dmamem_free(rdata->rx_desc_dtag, rdata->rx_desc,
2832 rdata->rx_desc_dmap);
2833 bus_dma_tag_destroy(rdata->rx_desc_dtag);
2835 rdata->rx_desc = NULL;
2838 if (rdata->rx_buf == NULL)
2841 for (i = 0; i < ndesc; i++) {
2842 rx_buffer = &rdata->rx_buf[i];
2844 KKASSERT(rx_buffer->m_head == NULL);
2845 bus_dmamap_destroy(rdata->rxtag, rx_buffer->map);
2847 bus_dmamap_destroy(rdata->rxtag, rdata->rx_sparemap);
2848 bus_dma_tag_destroy(rdata->rxtag);
2850 kfree(rdata->rx_buf, M_DEVBUF);
2851 rdata->rx_buf = NULL;
2855 emx_rxeof(struct emx_softc *sc, int ring_idx, int count)
2857 struct emx_rxdata *rdata = &sc->rx_data[ring_idx];
2858 struct ifnet *ifp = &sc->arpcom.ac_if;
2860 emx_rxdesc_t *current_desc;
2863 struct mbuf_chain chain[MAXCPU];
2865 i = rdata->next_rx_desc_to_check;
2866 current_desc = &rdata->rx_desc[i];
2867 staterr = le32toh(current_desc->rxd_staterr);
2869 if (!(staterr & E1000_RXD_STAT_DD))
2872 ether_input_chain_init(chain);
2874 while ((staterr & E1000_RXD_STAT_DD) && count != 0) {
2875 struct pktinfo *pi = NULL, pi0;
2876 struct emx_rxbuf *rx_buf = &rdata->rx_buf[i];
2877 struct mbuf *m = NULL;
2882 mp = rx_buf->m_head;
2885 * Can't defer bus_dmamap_sync(9) because TBI_ACCEPT
2886 * needs to access the last received byte in the mbuf.
2888 bus_dmamap_sync(rdata->rxtag, rx_buf->map,
2889 BUS_DMASYNC_POSTREAD);
2891 len = le16toh(current_desc->rxd_length);
2892 if (staterr & E1000_RXD_STAT_EOP) {
2899 if (!(staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK)) {
2901 uint32_t mrq, rss_hash;
2904 * Save several necessary information,
2905 * before emx_newbuf() destroy it.
2907 if ((staterr & E1000_RXD_STAT_VP) && eop)
2908 vlan = le16toh(current_desc->rxd_vlan);
2910 mrq = le32toh(current_desc->rxd_mrq);
2911 rss_hash = le32toh(current_desc->rxd_rss);
2913 EMX_RSS_DPRINTF(sc, 10,
2914 "ring%d, mrq 0x%08x, rss_hash 0x%08x\n",
2915 ring_idx, mrq, rss_hash);
2917 if (emx_newbuf(sc, rdata, i, 0) != 0) {
2922 /* Assign correct length to the current fragment */
2925 if (rdata->fmp == NULL) {
2926 mp->m_pkthdr.len = len;
2927 rdata->fmp = mp; /* Store the first mbuf */
2931 * Chain mbuf's together
2933 rdata->lmp->m_next = mp;
2934 rdata->lmp = rdata->lmp->m_next;
2935 rdata->fmp->m_pkthdr.len += len;
2939 rdata->fmp->m_pkthdr.rcvif = ifp;
2942 if (ifp->if_capenable & IFCAP_RXCSUM)
2943 emx_rxcsum(staterr, rdata->fmp);
2945 if (staterr & E1000_RXD_STAT_VP) {
2946 rdata->fmp->m_pkthdr.ether_vlantag =
2948 rdata->fmp->m_flags |= M_VLANTAG;
2954 if (ifp->if_capenable & IFCAP_RSS) {
2955 pi = emx_rssinfo(m, &pi0, mrq,
2958 #ifdef EMX_RSS_DEBUG
2965 emx_setup_rxdesc(current_desc, rx_buf);
2966 if (rdata->fmp != NULL) {
2967 m_freem(rdata->fmp);
2975 ether_input_chain(ifp, m, pi, chain);
2977 /* Advance our pointers to the next descriptor. */
2978 if (++i == rdata->num_rx_desc)
2981 current_desc = &rdata->rx_desc[i];
2982 staterr = le32toh(current_desc->rxd_staterr);
2984 rdata->next_rx_desc_to_check = i;
2986 ether_input_dispatch(chain);
2988 /* Advance the E1000's Receive Queue "Tail Pointer". */
2990 i = rdata->num_rx_desc - 1;
2991 E1000_WRITE_REG(&sc->hw, E1000_RDT(ring_idx), i);
2995 emx_enable_intr(struct emx_softc *sc)
2997 lwkt_serialize_handler_enable(&sc->main_serialize);
2998 E1000_WRITE_REG(&sc->hw, E1000_IMS, IMS_ENABLE_MASK);
3002 emx_disable_intr(struct emx_softc *sc)
3004 E1000_WRITE_REG(&sc->hw, E1000_IMC, 0xffffffff);
3005 lwkt_serialize_handler_disable(&sc->main_serialize);
3009 * Bit of a misnomer, what this really means is
3010 * to enable OS management of the system... aka
3011 * to disable special hardware management features
3014 emx_get_mgmt(struct emx_softc *sc)
3016 /* A shared code workaround */
3017 if (sc->has_manage) {
3018 int manc2h = E1000_READ_REG(&sc->hw, E1000_MANC2H);
3019 int manc = E1000_READ_REG(&sc->hw, E1000_MANC);
3021 /* disable hardware interception of ARP */
3022 manc &= ~(E1000_MANC_ARP_EN);
3024 /* enable receiving management packets to the host */
3025 manc |= E1000_MANC_EN_MNG2HOST;
3026 #define E1000_MNG2HOST_PORT_623 (1 << 5)
3027 #define E1000_MNG2HOST_PORT_664 (1 << 6)
3028 manc2h |= E1000_MNG2HOST_PORT_623;
3029 manc2h |= E1000_MNG2HOST_PORT_664;
3030 E1000_WRITE_REG(&sc->hw, E1000_MANC2H, manc2h);
3032 E1000_WRITE_REG(&sc->hw, E1000_MANC, manc);
3037 * Give control back to hardware management
3038 * controller if there is one.
3041 emx_rel_mgmt(struct emx_softc *sc)
3043 if (sc->has_manage) {
3044 int manc = E1000_READ_REG(&sc->hw, E1000_MANC);
3046 /* re-enable hardware interception of ARP */
3047 manc |= E1000_MANC_ARP_EN;
3048 manc &= ~E1000_MANC_EN_MNG2HOST;
3050 E1000_WRITE_REG(&sc->hw, E1000_MANC, manc);
3055 * emx_get_hw_control() sets {CTRL_EXT|FWSM}:DRV_LOAD bit.
3056 * For ASF and Pass Through versions of f/w this means that
3057 * the driver is loaded. For AMT version (only with 82573)
3058 * of the f/w this means that the network i/f is open.
3061 emx_get_hw_control(struct emx_softc *sc)
3063 uint32_t ctrl_ext, swsm;
3065 /* Let firmware know the driver has taken over */
3066 switch (sc->hw.mac.type) {
3068 swsm = E1000_READ_REG(&sc->hw, E1000_SWSM);
3069 E1000_WRITE_REG(&sc->hw, E1000_SWSM,
3070 swsm | E1000_SWSM_DRV_LOAD);
3075 case e1000_80003es2lan:
3076 ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT);
3077 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT,
3078 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
3087 * emx_rel_hw_control() resets {CTRL_EXT|FWSM}:DRV_LOAD bit.
3088 * For ASF and Pass Through versions of f/w this means that the
3089 * driver is no longer loaded. For AMT version (only with 82573)
3090 * of the f/w this means that the network i/f is closed.
3093 emx_rel_hw_control(struct emx_softc *sc)
3095 uint32_t ctrl_ext, swsm;
3097 /* Let firmware taken over control of h/w */
3098 switch (sc->hw.mac.type) {
3100 swsm = E1000_READ_REG(&sc->hw, E1000_SWSM);
3101 E1000_WRITE_REG(&sc->hw, E1000_SWSM,
3102 swsm & ~E1000_SWSM_DRV_LOAD);
3107 case e1000_80003es2lan:
3108 ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT);
3109 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT,
3110 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
3119 emx_is_valid_eaddr(const uint8_t *addr)
3121 char zero_addr[ETHER_ADDR_LEN] = { 0, 0, 0, 0, 0, 0 };
3123 if ((addr[0] & 1) || !bcmp(addr, zero_addr, ETHER_ADDR_LEN))
3130 * Enable PCI Wake On Lan capability
3133 emx_enable_wol(device_t dev)
3135 uint16_t cap, status;
3138 /* First find the capabilities pointer*/
3139 cap = pci_read_config(dev, PCIR_CAP_PTR, 2);
3141 /* Read the PM Capabilities */
3142 id = pci_read_config(dev, cap, 1);
3143 if (id != PCIY_PMG) /* Something wrong */
3147 * OK, we have the power capabilities,
3148 * so now get the status register
3150 cap += PCIR_POWER_STATUS;
3151 status = pci_read_config(dev, cap, 2);
3152 status |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
3153 pci_write_config(dev, cap, status, 2);
3157 emx_update_stats(struct emx_softc *sc)
3159 struct ifnet *ifp = &sc->arpcom.ac_if;
3161 if (sc->hw.phy.media_type == e1000_media_type_copper ||
3162 (E1000_READ_REG(&sc->hw, E1000_STATUS) & E1000_STATUS_LU)) {
3163 sc->stats.symerrs += E1000_READ_REG(&sc->hw, E1000_SYMERRS);
3164 sc->stats.sec += E1000_READ_REG(&sc->hw, E1000_SEC);
3166 sc->stats.crcerrs += E1000_READ_REG(&sc->hw, E1000_CRCERRS);
3167 sc->stats.mpc += E1000_READ_REG(&sc->hw, E1000_MPC);
3168 sc->stats.scc += E1000_READ_REG(&sc->hw, E1000_SCC);
3169 sc->stats.ecol += E1000_READ_REG(&sc->hw, E1000_ECOL);
3171 sc->stats.mcc += E1000_READ_REG(&sc->hw, E1000_MCC);
3172 sc->stats.latecol += E1000_READ_REG(&sc->hw, E1000_LATECOL);
3173 sc->stats.colc += E1000_READ_REG(&sc->hw, E1000_COLC);
3174 sc->stats.dc += E1000_READ_REG(&sc->hw, E1000_DC);
3175 sc->stats.rlec += E1000_READ_REG(&sc->hw, E1000_RLEC);
3176 sc->stats.xonrxc += E1000_READ_REG(&sc->hw, E1000_XONRXC);
3177 sc->stats.xontxc += E1000_READ_REG(&sc->hw, E1000_XONTXC);
3178 sc->stats.xoffrxc += E1000_READ_REG(&sc->hw, E1000_XOFFRXC);
3179 sc->stats.xofftxc += E1000_READ_REG(&sc->hw, E1000_XOFFTXC);
3180 sc->stats.fcruc += E1000_READ_REG(&sc->hw, E1000_FCRUC);
3181 sc->stats.prc64 += E1000_READ_REG(&sc->hw, E1000_PRC64);
3182 sc->stats.prc127 += E1000_READ_REG(&sc->hw, E1000_PRC127);
3183 sc->stats.prc255 += E1000_READ_REG(&sc->hw, E1000_PRC255);
3184 sc->stats.prc511 += E1000_READ_REG(&sc->hw, E1000_PRC511);
3185 sc->stats.prc1023 += E1000_READ_REG(&sc->hw, E1000_PRC1023);
3186 sc->stats.prc1522 += E1000_READ_REG(&sc->hw, E1000_PRC1522);
3187 sc->stats.gprc += E1000_READ_REG(&sc->hw, E1000_GPRC);
3188 sc->stats.bprc += E1000_READ_REG(&sc->hw, E1000_BPRC);
3189 sc->stats.mprc += E1000_READ_REG(&sc->hw, E1000_MPRC);
3190 sc->stats.gptc += E1000_READ_REG(&sc->hw, E1000_GPTC);
3192 /* For the 64-bit byte counters the low dword must be read first. */
3193 /* Both registers clear on the read of the high dword */
3195 sc->stats.gorc += E1000_READ_REG(&sc->hw, E1000_GORCH);
3196 sc->stats.gotc += E1000_READ_REG(&sc->hw, E1000_GOTCH);
3198 sc->stats.rnbc += E1000_READ_REG(&sc->hw, E1000_RNBC);
3199 sc->stats.ruc += E1000_READ_REG(&sc->hw, E1000_RUC);
3200 sc->stats.rfc += E1000_READ_REG(&sc->hw, E1000_RFC);
3201 sc->stats.roc += E1000_READ_REG(&sc->hw, E1000_ROC);
3202 sc->stats.rjc += E1000_READ_REG(&sc->hw, E1000_RJC);
3204 sc->stats.tor += E1000_READ_REG(&sc->hw, E1000_TORH);
3205 sc->stats.tot += E1000_READ_REG(&sc->hw, E1000_TOTH);
3207 sc->stats.tpr += E1000_READ_REG(&sc->hw, E1000_TPR);
3208 sc->stats.tpt += E1000_READ_REG(&sc->hw, E1000_TPT);
3209 sc->stats.ptc64 += E1000_READ_REG(&sc->hw, E1000_PTC64);
3210 sc->stats.ptc127 += E1000_READ_REG(&sc->hw, E1000_PTC127);
3211 sc->stats.ptc255 += E1000_READ_REG(&sc->hw, E1000_PTC255);
3212 sc->stats.ptc511 += E1000_READ_REG(&sc->hw, E1000_PTC511);
3213 sc->stats.ptc1023 += E1000_READ_REG(&sc->hw, E1000_PTC1023);
3214 sc->stats.ptc1522 += E1000_READ_REG(&sc->hw, E1000_PTC1522);
3215 sc->stats.mptc += E1000_READ_REG(&sc->hw, E1000_MPTC);
3216 sc->stats.bptc += E1000_READ_REG(&sc->hw, E1000_BPTC);
3218 sc->stats.algnerrc += E1000_READ_REG(&sc->hw, E1000_ALGNERRC);
3219 sc->stats.rxerrc += E1000_READ_REG(&sc->hw, E1000_RXERRC);
3220 sc->stats.tncrs += E1000_READ_REG(&sc->hw, E1000_TNCRS);
3221 sc->stats.cexterr += E1000_READ_REG(&sc->hw, E1000_CEXTERR);
3222 sc->stats.tsctc += E1000_READ_REG(&sc->hw, E1000_TSCTC);
3223 sc->stats.tsctfc += E1000_READ_REG(&sc->hw, E1000_TSCTFC);
3225 ifp->if_collisions = sc->stats.colc;
3228 ifp->if_ierrors = sc->dropped_pkts + sc->stats.rxerrc +
3229 sc->stats.crcerrs + sc->stats.algnerrc +
3230 sc->stats.ruc + sc->stats.roc +
3231 sc->stats.mpc + sc->stats.cexterr;
3234 ifp->if_oerrors = sc->stats.ecol + sc->stats.latecol +
3235 sc->watchdog_events;
3239 emx_print_debug_info(struct emx_softc *sc)
3241 device_t dev = sc->dev;
3242 uint8_t *hw_addr = sc->hw.hw_addr;
3244 device_printf(dev, "Adapter hardware address = %p \n", hw_addr);
3245 device_printf(dev, "CTRL = 0x%x RCTL = 0x%x \n",
3246 E1000_READ_REG(&sc->hw, E1000_CTRL),
3247 E1000_READ_REG(&sc->hw, E1000_RCTL));
3248 device_printf(dev, "Packet buffer = Tx=%dk Rx=%dk \n",
3249 ((E1000_READ_REG(&sc->hw, E1000_PBA) & 0xffff0000) >> 16),\
3250 (E1000_READ_REG(&sc->hw, E1000_PBA) & 0xffff) );
3251 device_printf(dev, "Flow control watermarks high = %d low = %d\n",
3252 sc->hw.fc.high_water, sc->hw.fc.low_water);
3253 device_printf(dev, "tx_int_delay = %d, tx_abs_int_delay = %d\n",
3254 E1000_READ_REG(&sc->hw, E1000_TIDV),
3255 E1000_READ_REG(&sc->hw, E1000_TADV));
3256 device_printf(dev, "rx_int_delay = %d, rx_abs_int_delay = %d\n",
3257 E1000_READ_REG(&sc->hw, E1000_RDTR),
3258 E1000_READ_REG(&sc->hw, E1000_RADV));
3259 device_printf(dev, "hw tdh = %d, hw tdt = %d\n",
3260 E1000_READ_REG(&sc->hw, E1000_TDH(0)),
3261 E1000_READ_REG(&sc->hw, E1000_TDT(0)));
3262 device_printf(dev, "hw rdh = %d, hw rdt = %d\n",
3263 E1000_READ_REG(&sc->hw, E1000_RDH(0)),
3264 E1000_READ_REG(&sc->hw, E1000_RDT(0)));
3265 device_printf(dev, "Num Tx descriptors avail = %d\n",
3266 sc->num_tx_desc_avail);
3267 device_printf(dev, "Tx Descriptors not avail1 = %ld\n",
3268 sc->no_tx_desc_avail1);
3269 device_printf(dev, "Tx Descriptors not avail2 = %ld\n",
3270 sc->no_tx_desc_avail2);
3271 device_printf(dev, "Std mbuf failed = %ld\n",
3272 sc->mbuf_alloc_failed);
3273 device_printf(dev, "Std mbuf cluster failed = %ld\n",
3274 sc->rx_data[0].mbuf_cluster_failed);
3275 device_printf(dev, "Driver dropped packets = %ld\n",
3277 device_printf(dev, "Driver tx dma failure in encap = %ld\n",
3278 sc->no_tx_dma_setup);
3280 device_printf(dev, "TXCSUM try pullup = %lu\n",
3281 sc->tx_csum_try_pullup);
3282 device_printf(dev, "TXCSUM m_pullup(eh) called = %lu\n",
3283 sc->tx_csum_pullup1);
3284 device_printf(dev, "TXCSUM m_pullup(eh) failed = %lu\n",
3285 sc->tx_csum_pullup1_failed);
3286 device_printf(dev, "TXCSUM m_pullup(eh+ip) called = %lu\n",
3287 sc->tx_csum_pullup2);
3288 device_printf(dev, "TXCSUM m_pullup(eh+ip) failed = %lu\n",
3289 sc->tx_csum_pullup2_failed);
3290 device_printf(dev, "TXCSUM non-writable(eh) droped = %lu\n",
3292 device_printf(dev, "TXCSUM non-writable(eh+ip) droped = %lu\n",
3297 emx_print_hw_stats(struct emx_softc *sc)
3299 device_t dev = sc->dev;
3301 device_printf(dev, "Excessive collisions = %lld\n",
3302 (long long)sc->stats.ecol);
3303 #if (DEBUG_HW > 0) /* Dont output these errors normally */
3304 device_printf(dev, "Symbol errors = %lld\n",
3305 (long long)sc->stats.symerrs);
3307 device_printf(dev, "Sequence errors = %lld\n",
3308 (long long)sc->stats.sec);
3309 device_printf(dev, "Defer count = %lld\n",
3310 (long long)sc->stats.dc);
3311 device_printf(dev, "Missed Packets = %lld\n",
3312 (long long)sc->stats.mpc);
3313 device_printf(dev, "Receive No Buffers = %lld\n",
3314 (long long)sc->stats.rnbc);
3315 /* RLEC is inaccurate on some hardware, calculate our own. */
3316 device_printf(dev, "Receive Length Errors = %lld\n",
3317 ((long long)sc->stats.roc + (long long)sc->stats.ruc));
3318 device_printf(dev, "Receive errors = %lld\n",
3319 (long long)sc->stats.rxerrc);
3320 device_printf(dev, "Crc errors = %lld\n",
3321 (long long)sc->stats.crcerrs);
3322 device_printf(dev, "Alignment errors = %lld\n",
3323 (long long)sc->stats.algnerrc);
3324 device_printf(dev, "Collision/Carrier extension errors = %lld\n",
3325 (long long)sc->stats.cexterr);
3326 device_printf(dev, "RX overruns = %ld\n", sc->rx_overruns);
3327 device_printf(dev, "watchdog timeouts = %ld\n",
3328 sc->watchdog_events);
3329 device_printf(dev, "XON Rcvd = %lld\n",
3330 (long long)sc->stats.xonrxc);
3331 device_printf(dev, "XON Xmtd = %lld\n",
3332 (long long)sc->stats.xontxc);
3333 device_printf(dev, "XOFF Rcvd = %lld\n",
3334 (long long)sc->stats.xoffrxc);
3335 device_printf(dev, "XOFF Xmtd = %lld\n",
3336 (long long)sc->stats.xofftxc);
3337 device_printf(dev, "Good Packets Rcvd = %lld\n",
3338 (long long)sc->stats.gprc);
3339 device_printf(dev, "Good Packets Xmtd = %lld\n",
3340 (long long)sc->stats.gptc);
3344 emx_print_nvm_info(struct emx_softc *sc)
3346 uint16_t eeprom_data;
3349 /* Its a bit crude, but it gets the job done */
3350 kprintf("\nInterface EEPROM Dump:\n");
3351 kprintf("Offset\n0x0000 ");
3352 for (i = 0, j = 0; i < 32; i++, j++) {
3353 if (j == 8) { /* Make the offset block */
3355 kprintf("\n0x00%x0 ",row);
3357 e1000_read_nvm(&sc->hw, i, 1, &eeprom_data);
3358 kprintf("%04x ", eeprom_data);
3364 emx_sysctl_debug_info(SYSCTL_HANDLER_ARGS)
3366 struct emx_softc *sc;
3371 error = sysctl_handle_int(oidp, &result, 0, req);
3372 if (error || !req->newptr)
3375 sc = (struct emx_softc *)arg1;
3376 ifp = &sc->arpcom.ac_if;
3378 ifnet_serialize_all(ifp);
3381 emx_print_debug_info(sc);
3384 * This value will cause a hex dump of the
3385 * first 32 16-bit words of the EEPROM to
3389 emx_print_nvm_info(sc);
3391 ifnet_deserialize_all(ifp);
3397 emx_sysctl_stats(SYSCTL_HANDLER_ARGS)
3402 error = sysctl_handle_int(oidp, &result, 0, req);
3403 if (error || !req->newptr)
3407 struct emx_softc *sc = (struct emx_softc *)arg1;
3408 struct ifnet *ifp = &sc->arpcom.ac_if;
3410 ifnet_serialize_all(ifp);
3411 emx_print_hw_stats(sc);
3412 ifnet_deserialize_all(ifp);
3418 emx_add_sysctl(struct emx_softc *sc)
3420 #ifdef PROFILE_SERIALIZER
3421 struct ifnet *ifp = &sc->arpcom.ac_if;
3423 #ifdef EMX_RSS_DEBUG
3428 sysctl_ctx_init(&sc->sysctl_ctx);
3429 sc->sysctl_tree = SYSCTL_ADD_NODE(&sc->sysctl_ctx,
3430 SYSCTL_STATIC_CHILDREN(_hw), OID_AUTO,
3431 device_get_nameunit(sc->dev),
3433 if (sc->sysctl_tree == NULL) {
3434 device_printf(sc->dev, "can't add sysctl node\n");
3438 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
3439 OID_AUTO, "debug", CTLTYPE_INT|CTLFLAG_RW, sc, 0,
3440 emx_sysctl_debug_info, "I", "Debug Information");
3442 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
3443 OID_AUTO, "stats", CTLTYPE_INT|CTLFLAG_RW, sc, 0,
3444 emx_sysctl_stats, "I", "Statistics");
3446 SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
3447 OID_AUTO, "rxd", CTLFLAG_RD,
3448 &sc->rx_data[0].num_rx_desc, 0, NULL);
3449 SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
3450 OID_AUTO, "txd", CTLFLAG_RD, &sc->num_tx_desc, 0, NULL);
3453 #ifdef PROFILE_SERIALIZER
3454 SYSCTL_ADD_UINT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
3455 OID_AUTO, "serializer_sleep", CTLFLAG_RW,
3456 &ifp->if_serializer->sleep_cnt, 0, NULL);
3457 SYSCTL_ADD_UINT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
3458 OID_AUTO, "serializer_tryfail", CTLFLAG_RW,
3459 &ifp->if_serializer->tryfail_cnt, 0, NULL);
3460 SYSCTL_ADD_UINT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
3461 OID_AUTO, "serializer_enter", CTLFLAG_RW,
3462 &ifp->if_serializer->enter_cnt, 0, NULL);
3463 SYSCTL_ADD_UINT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
3464 OID_AUTO, "serializer_try", CTLFLAG_RW,
3465 &ifp->if_serializer->try_cnt, 0, NULL);
3469 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
3470 OID_AUTO, "int_throttle_ceil", CTLTYPE_INT|CTLFLAG_RW,
3471 sc, 0, emx_sysctl_int_throttle, "I",
3472 "interrupt throttling rate");
3473 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
3474 OID_AUTO, "int_tx_nsegs", CTLTYPE_INT|CTLFLAG_RW,
3475 sc, 0, emx_sysctl_int_tx_nsegs, "I",
3476 "# segments per TX interrupt");
3478 SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
3479 OID_AUTO, "rx_ring_inuse", CTLFLAG_RD,
3480 &sc->rx_ring_inuse, 0, "RX ring in use");
3482 #ifdef EMX_RSS_DEBUG
3483 SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
3484 OID_AUTO, "rss_debug", CTLFLAG_RW, &sc->rss_debug,
3485 0, "RSS debug level");
3486 for (i = 0; i < sc->rx_ring_cnt; ++i) {
3487 ksnprintf(rx_pkt, sizeof(rx_pkt), "rx%d_pkt", i);
3488 SYSCTL_ADD_UINT(&sc->sysctl_ctx,
3489 SYSCTL_CHILDREN(sc->sysctl_tree), OID_AUTO,
3491 &sc->rx_data[i].rx_pkts, 0, "RXed packets");
3497 emx_sysctl_int_throttle(SYSCTL_HANDLER_ARGS)
3499 struct emx_softc *sc = (void *)arg1;
3500 struct ifnet *ifp = &sc->arpcom.ac_if;
3501 int error, throttle;
3503 throttle = sc->int_throttle_ceil;
3504 error = sysctl_handle_int(oidp, &throttle, 0, req);
3505 if (error || req->newptr == NULL)
3507 if (throttle < 0 || throttle > 1000000000 / 256)
3512 * Set the interrupt throttling rate in 256ns increments,
3513 * recalculate sysctl value assignment to get exact frequency.
3515 throttle = 1000000000 / 256 / throttle;
3517 /* Upper 16bits of ITR is reserved and should be zero */
3518 if (throttle & 0xffff0000)
3522 ifnet_serialize_all(ifp);
3525 sc->int_throttle_ceil = 1000000000 / 256 / throttle;
3527 sc->int_throttle_ceil = 0;
3529 if (ifp->if_flags & IFF_RUNNING)
3530 E1000_WRITE_REG(&sc->hw, E1000_ITR, throttle);
3532 ifnet_deserialize_all(ifp);
3535 if_printf(ifp, "Interrupt moderation set to %d/sec\n",
3536 sc->int_throttle_ceil);
3542 emx_sysctl_int_tx_nsegs(SYSCTL_HANDLER_ARGS)
3544 struct emx_softc *sc = (void *)arg1;
3545 struct ifnet *ifp = &sc->arpcom.ac_if;
3548 segs = sc->tx_int_nsegs;
3549 error = sysctl_handle_int(oidp, &segs, 0, req);
3550 if (error || req->newptr == NULL)
3555 ifnet_serialize_all(ifp);
3558 * Don't allow int_tx_nsegs to become:
3559 * o Less the oact_tx_desc
3560 * o Too large that no TX desc will cause TX interrupt to
3561 * be generated (OACTIVE will never recover)
3562 * o Too small that will cause tx_dd[] overflow
3564 if (segs < sc->oact_tx_desc ||
3565 segs >= sc->num_tx_desc - sc->oact_tx_desc ||
3566 segs < sc->num_tx_desc / EMX_TXDD_SAFE) {
3570 sc->tx_int_nsegs = segs;
3573 ifnet_deserialize_all(ifp);
3579 emx_dma_alloc(struct emx_softc *sc)
3584 * Create top level busdma tag
3586 error = bus_dma_tag_create(NULL, 1, 0,
3587 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
3589 BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT,
3590 0, &sc->parent_dtag);
3592 device_printf(sc->dev, "could not create top level DMA tag\n");
3597 * Allocate transmit descriptors ring and buffers
3599 error = emx_create_tx_ring(sc);
3601 device_printf(sc->dev, "Could not setup transmit structures\n");
3606 * Allocate receive descriptors ring and buffers
3608 for (i = 0; i < sc->rx_ring_cnt; ++i) {
3609 error = emx_create_rx_ring(sc, &sc->rx_data[i]);
3611 device_printf(sc->dev,
3612 "Could not setup receive structures\n");
3620 emx_dma_free(struct emx_softc *sc)
3624 emx_destroy_tx_ring(sc, sc->num_tx_desc);
3626 for (i = 0; i < sc->rx_ring_cnt; ++i) {
3627 emx_destroy_rx_ring(sc, &sc->rx_data[i],
3628 sc->rx_data[i].num_rx_desc);
3631 /* Free top level busdma tag */
3632 if (sc->parent_dtag != NULL)
3633 bus_dma_tag_destroy(sc->parent_dtag);
3637 emx_serialize(struct ifnet *ifp, enum ifnet_serialize slz)
3639 struct emx_softc *sc = ifp->if_softc;
3642 case IFNET_SERIALIZE_ALL:
3643 lwkt_serialize_array_enter(sc->serializes, EMX_NSERIALIZE, 0);
3646 case IFNET_SERIALIZE_MAIN:
3647 lwkt_serialize_enter(&sc->main_serialize);
3650 case IFNET_SERIALIZE_TX:
3651 lwkt_serialize_enter(&sc->tx_serialize);
3654 case IFNET_SERIALIZE_RX(0):
3655 lwkt_serialize_enter(&sc->rx_data[0].rx_serialize);
3658 case IFNET_SERIALIZE_RX(1):
3659 lwkt_serialize_enter(&sc->rx_data[1].rx_serialize);
3663 panic("%s unsupported serialize type\n", ifp->if_xname);
3668 emx_deserialize(struct ifnet *ifp, enum ifnet_serialize slz)
3670 struct emx_softc *sc = ifp->if_softc;
3673 case IFNET_SERIALIZE_ALL:
3674 lwkt_serialize_array_exit(sc->serializes, EMX_NSERIALIZE, 0);
3677 case IFNET_SERIALIZE_MAIN:
3678 lwkt_serialize_exit(&sc->main_serialize);
3681 case IFNET_SERIALIZE_TX:
3682 lwkt_serialize_exit(&sc->tx_serialize);
3685 case IFNET_SERIALIZE_RX(0):
3686 lwkt_serialize_exit(&sc->rx_data[0].rx_serialize);
3689 case IFNET_SERIALIZE_RX(1):
3690 lwkt_serialize_exit(&sc->rx_data[1].rx_serialize);
3694 panic("%s unsupported serialize type\n", ifp->if_xname);
3699 emx_tryserialize(struct ifnet *ifp, enum ifnet_serialize slz)
3701 struct emx_softc *sc = ifp->if_softc;
3704 case IFNET_SERIALIZE_ALL:
3705 return lwkt_serialize_array_try(sc->serializes,
3708 case IFNET_SERIALIZE_MAIN:
3709 return lwkt_serialize_try(&sc->main_serialize);
3711 case IFNET_SERIALIZE_TX:
3712 return lwkt_serialize_try(&sc->tx_serialize);
3714 case IFNET_SERIALIZE_RX(0):
3715 return lwkt_serialize_try(&sc->rx_data[0].rx_serialize);
3717 case IFNET_SERIALIZE_RX(1):
3718 return lwkt_serialize_try(&sc->rx_data[1].rx_serialize);
3721 panic("%s unsupported serialize type\n", ifp->if_xname);
3726 emx_serialize_skipmain(struct emx_softc *sc)
3728 lwkt_serialize_array_enter(sc->serializes, EMX_NSERIALIZE, 1);
3732 emx_tryserialize_skipmain(struct emx_softc *sc)
3734 return lwkt_serialize_array_try(sc->serializes, EMX_NSERIALIZE, 1);
3738 emx_deserialize_skipmain(struct emx_softc *sc)
3740 lwkt_serialize_array_exit(sc->serializes, EMX_NSERIALIZE, 1);
3746 emx_serialize_assert(struct ifnet *ifp, enum ifnet_serialize slz,
3747 boolean_t serialized)
3749 struct emx_softc *sc = ifp->if_softc;
3753 case IFNET_SERIALIZE_ALL:
3755 for (i = 0; i < EMX_NSERIALIZE; ++i)
3756 ASSERT_SERIALIZED(sc->serializes[i]);
3758 for (i = 0; i < EMX_NSERIALIZE; ++i)
3759 ASSERT_NOT_SERIALIZED(sc->serializes[i]);
3763 case IFNET_SERIALIZE_MAIN:
3765 ASSERT_SERIALIZED(&sc->main_serialize);
3767 ASSERT_NOT_SERIALIZED(&sc->main_serialize);
3770 case IFNET_SERIALIZE_TX:
3772 ASSERT_SERIALIZED(&sc->tx_serialize);
3774 ASSERT_NOT_SERIALIZED(&sc->tx_serialize);
3777 case IFNET_SERIALIZE_RX(0):
3779 ASSERT_SERIALIZED(&sc->rx_data[0].rx_serialize);
3781 ASSERT_NOT_SERIALIZED(&sc->rx_data[0].rx_serialize);
3784 case IFNET_SERIALIZE_RX(1):
3786 ASSERT_SERIALIZED(&sc->rx_data[1].rx_serialize);
3788 ASSERT_NOT_SERIALIZED(&sc->rx_data[1].rx_serialize);
3792 panic("%s unsupported serialize type\n", ifp->if_xname);
3796 #endif /* INVARIANTS */