2 * Copyright (c) 1997, 1998, 1999
3 * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
32 * $FreeBSD: src/sys/pci/if_dc.c,v 1.9.2.45 2003/06/08 14:31:53 mux Exp $
33 * $DragonFly: src/sys/dev/netif/dc/if_dc.c,v 1.31 2005/05/31 07:52:22 joerg Exp $
37 * DEC "tulip" clone ethernet driver. Supports the DEC/Intel 21143
38 * series chips and several workalikes including the following:
40 * Macronix 98713/98715/98725/98727/98732 PMAC (www.macronix.com)
41 * Macronix/Lite-On 82c115 PNIC II (www.macronix.com)
42 * Lite-On 82c168/82c169 PNIC (www.litecom.com)
43 * ASIX Electronics AX88140A (www.asix.com.tw)
44 * ASIX Electronics AX88141 (www.asix.com.tw)
45 * ADMtek AL981 (www.admtek.com.tw)
46 * ADMtek AN985 (www.admtek.com.tw)
47 * Davicom DM9100, DM9102, DM9102A (www.davicom8.com)
48 * Accton EN1217 (www.accton.com)
49 * Conexant LANfinity (www.conexant.com)
51 * Datasheets for the 21143 are available at developer.intel.com.
52 * Datasheets for the clone parts can be found at their respective sites.
53 * (Except for the PNIC; see www.freebsd.org/~wpaul/PNIC/pnic.ps.gz.)
54 * The PNIC II is essentially a Macronix 98715A chip; the only difference
55 * worth noting is that its multicast hash table is only 128 bits wide
58 * Written by Bill Paul <wpaul@ee.columbia.edu>
59 * Electrical Engineering Department
60 * Columbia University, New York City
64 * The Intel 21143 is the successor to the DEC 21140. It is basically
65 * the same as the 21140 but with a few new features. The 21143 supports
66 * three kinds of media attachments:
68 * o MII port, for 10Mbps and 100Mbps support and NWAY
69 * autonegotiation provided by an external PHY.
70 * o SYM port, for symbol mode 100Mbps support.
74 * The 100Mbps SYM port and 10baseT port can be used together in
75 * combination with the internal NWAY support to create a 10/100
76 * autosensing configuration.
78 * Note that not all tulip workalikes are handled in this driver: we only
79 * deal with those which are relatively well behaved. The Winbond is
80 * handled separately due to its different register offsets and the
81 * special handling needed for its various bugs. The PNIC is handled
82 * here, but I'm not thrilled about it.
84 * All of the workalike chips use some form of MII transceiver support
85 * with the exception of the Macronix chips, which also have a SYM port.
86 * The ASIX AX88140A is also documented to have a SYM port, but all
87 * the cards I've seen use an MII transceiver, probably because the
88 * AX88140A doesn't support internal NWAY.
91 #include <sys/param.h>
92 #include <sys/systm.h>
93 #include <sys/sockio.h>
95 #include <sys/malloc.h>
96 #include <sys/kernel.h>
97 #include <sys/socket.h>
98 #include <sys/sysctl.h>
101 #include <net/ifq_var.h>
102 #include <net/if_arp.h>
103 #include <net/ethernet.h>
104 #include <net/if_dl.h>
105 #include <net/if_media.h>
106 #include <net/if_types.h>
107 #include <net/vlan/if_vlan_var.h>
111 #include <vm/vm.h> /* for vtophys */
112 #include <vm/pmap.h> /* for vtophys */
113 #include <machine/bus_pio.h>
114 #include <machine/bus_memio.h>
115 #include <machine/bus.h>
116 #include <machine/resource.h>
118 #include <sys/rman.h>
120 #include "../mii_layer/mii.h"
121 #include "../mii_layer/miivar.h"
123 #include <bus/pci/pcireg.h>
124 #include <bus/pci/pcivar.h>
126 #define DC_USEIOSPACE
128 #include "if_dcreg.h"
130 /* "controller miibus0" required. See GENERIC if you get errors here. */
131 #include "miibus_if.h"
134 * Various supported device vendors/types and their names.
136 static struct dc_type dc_devs[] = {
137 { DC_VENDORID_DEC, DC_DEVICEID_21143,
138 "Intel 21143 10/100BaseTX" },
139 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9009,
140 "Davicom DM9009 10/100BaseTX" },
141 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9100,
142 "Davicom DM9100 10/100BaseTX" },
143 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102,
144 "Davicom DM9102 10/100BaseTX" },
145 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102,
146 "Davicom DM9102A 10/100BaseTX" },
147 { DC_VENDORID_ADMTEK, DC_DEVICEID_AL981,
148 "ADMtek AL981 10/100BaseTX" },
149 { DC_VENDORID_ADMTEK, DC_DEVICEID_AN985,
150 "ADMtek AN985 10/100BaseTX" },
151 { DC_VENDORID_ASIX, DC_DEVICEID_AX88140A,
152 "ASIX AX88140A 10/100BaseTX" },
153 { DC_VENDORID_ASIX, DC_DEVICEID_AX88140A,
154 "ASIX AX88141 10/100BaseTX" },
155 { DC_VENDORID_MX, DC_DEVICEID_98713,
156 "Macronix 98713 10/100BaseTX" },
157 { DC_VENDORID_MX, DC_DEVICEID_98713,
158 "Macronix 98713A 10/100BaseTX" },
159 { DC_VENDORID_CP, DC_DEVICEID_98713_CP,
160 "Compex RL100-TX 10/100BaseTX" },
161 { DC_VENDORID_CP, DC_DEVICEID_98713_CP,
162 "Compex RL100-TX 10/100BaseTX" },
163 { DC_VENDORID_MX, DC_DEVICEID_987x5,
164 "Macronix 98715/98715A 10/100BaseTX" },
165 { DC_VENDORID_MX, DC_DEVICEID_987x5,
166 "Macronix 98715AEC-C 10/100BaseTX" },
167 { DC_VENDORID_MX, DC_DEVICEID_987x5,
168 "Macronix 98725 10/100BaseTX" },
169 { DC_VENDORID_MX, DC_DEVICEID_98727,
170 "Macronix 98727/98732 10/100BaseTX" },
171 { DC_VENDORID_LO, DC_DEVICEID_82C115,
172 "LC82C115 PNIC II 10/100BaseTX" },
173 { DC_VENDORID_LO, DC_DEVICEID_82C168,
174 "82c168 PNIC 10/100BaseTX" },
175 { DC_VENDORID_LO, DC_DEVICEID_82C168,
176 "82c169 PNIC 10/100BaseTX" },
177 { DC_VENDORID_ACCTON, DC_DEVICEID_EN1217,
178 "Accton EN1217 10/100BaseTX" },
179 { DC_VENDORID_ACCTON, DC_DEVICEID_EN2242,
180 "Accton EN2242 MiniPCI 10/100BaseTX" },
181 { DC_VENDORID_CONEXANT, DC_DEVICEID_RS7112,
182 "Conexant LANfinity MiniPCI 10/100BaseTX" },
183 { DC_VENDORID_3COM, DC_DEVICEID_3CSOHOB,
184 "3Com OfficeConnect 10/100B" },
188 static int dc_probe (device_t);
189 static int dc_attach (device_t);
190 static int dc_detach (device_t);
191 static int dc_suspend (device_t);
192 static int dc_resume (device_t);
193 static void dc_acpi (device_t);
194 static struct dc_type *dc_devtype (device_t);
195 static int dc_newbuf (struct dc_softc *, int, struct mbuf *);
196 static int dc_encap (struct dc_softc *, struct mbuf *,
198 static void dc_pnic_rx_bug_war (struct dc_softc *, int);
199 static int dc_rx_resync (struct dc_softc *);
200 static void dc_rxeof (struct dc_softc *);
201 static void dc_txeof (struct dc_softc *);
202 static void dc_tick (void *);
203 static void dc_tx_underrun (struct dc_softc *);
204 static void dc_intr (void *);
205 static void dc_start (struct ifnet *);
206 static int dc_ioctl (struct ifnet *, u_long, caddr_t,
208 #ifdef DEVICE_POLLING
209 static void dc_poll (struct ifnet *ifp, enum poll_cmd cmd,
212 static void dc_init (void *);
213 static void dc_stop (struct dc_softc *);
214 static void dc_watchdog (struct ifnet *);
215 static void dc_shutdown (device_t);
216 static int dc_ifmedia_upd (struct ifnet *);
217 static void dc_ifmedia_sts (struct ifnet *, struct ifmediareq *);
219 static void dc_delay (struct dc_softc *);
220 static void dc_eeprom_idle (struct dc_softc *);
221 static void dc_eeprom_putbyte (struct dc_softc *, int);
222 static void dc_eeprom_getword (struct dc_softc *, int, u_int16_t *);
223 static void dc_eeprom_getword_pnic
224 (struct dc_softc *, int, u_int16_t *);
225 static void dc_eeprom_width (struct dc_softc *);
226 static void dc_read_eeprom (struct dc_softc *, caddr_t, int,
229 static void dc_mii_writebit (struct dc_softc *, int);
230 static int dc_mii_readbit (struct dc_softc *);
231 static void dc_mii_sync (struct dc_softc *);
232 static void dc_mii_send (struct dc_softc *, u_int32_t, int);
233 static int dc_mii_readreg (struct dc_softc *, struct dc_mii_frame *);
234 static int dc_mii_writereg (struct dc_softc *, struct dc_mii_frame *);
235 static int dc_miibus_readreg (device_t, int, int);
236 static int dc_miibus_writereg (device_t, int, int, int);
237 static void dc_miibus_statchg (device_t);
238 static void dc_miibus_mediainit (device_t);
240 static u_int32_t dc_crc_mask (struct dc_softc *);
241 static void dc_setcfg (struct dc_softc *, int);
242 static void dc_setfilt_21143 (struct dc_softc *);
243 static void dc_setfilt_asix (struct dc_softc *);
244 static void dc_setfilt_admtek (struct dc_softc *);
246 static void dc_setfilt (struct dc_softc *);
248 static void dc_reset (struct dc_softc *);
249 static int dc_list_rx_init (struct dc_softc *);
250 static int dc_list_tx_init (struct dc_softc *);
252 static void dc_read_srom (struct dc_softc *, int);
253 static void dc_parse_21143_srom (struct dc_softc *);
254 static void dc_decode_leaf_sia (struct dc_softc *,
255 struct dc_eblock_sia *);
256 static void dc_decode_leaf_mii (struct dc_softc *,
257 struct dc_eblock_mii *);
258 static void dc_decode_leaf_sym (struct dc_softc *,
259 struct dc_eblock_sym *);
260 static void dc_apply_fixup (struct dc_softc *, int);
263 #define DC_RES SYS_RES_IOPORT
264 #define DC_RID DC_PCI_CFBIO
266 #define DC_RES SYS_RES_MEMORY
267 #define DC_RID DC_PCI_CFBMA
270 static device_method_t dc_methods[] = {
271 /* Device interface */
272 DEVMETHOD(device_probe, dc_probe),
273 DEVMETHOD(device_attach, dc_attach),
274 DEVMETHOD(device_detach, dc_detach),
275 DEVMETHOD(device_suspend, dc_suspend),
276 DEVMETHOD(device_resume, dc_resume),
277 DEVMETHOD(device_shutdown, dc_shutdown),
280 DEVMETHOD(bus_print_child, bus_generic_print_child),
281 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
284 DEVMETHOD(miibus_readreg, dc_miibus_readreg),
285 DEVMETHOD(miibus_writereg, dc_miibus_writereg),
286 DEVMETHOD(miibus_statchg, dc_miibus_statchg),
287 DEVMETHOD(miibus_mediainit, dc_miibus_mediainit),
292 static driver_t dc_driver = {
295 sizeof(struct dc_softc)
298 static devclass_t dc_devclass;
301 static int dc_quick=1;
302 SYSCTL_INT(_hw, OID_AUTO, dc_quick, CTLFLAG_RW,
303 &dc_quick,0,"do not mdevget in dc driver");
306 DECLARE_DUMMY_MODULE(if_dc);
307 DRIVER_MODULE(if_dc, pci, dc_driver, dc_devclass, 0, 0);
308 DRIVER_MODULE(miibus, dc, miibus_driver, miibus_devclass, 0, 0);
310 #define DC_SETBIT(sc, reg, x) \
311 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x))
313 #define DC_CLRBIT(sc, reg, x) \
314 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x))
316 #define SIO_SET(x) DC_SETBIT(sc, DC_SIO, (x))
317 #define SIO_CLR(x) DC_CLRBIT(sc, DC_SIO, (x))
319 static void dc_delay(sc)
324 for (idx = (300 / 33) + 1; idx > 0; idx--)
325 CSR_READ_4(sc, DC_BUSCTL);
328 static void dc_eeprom_width(sc)
333 /* Force EEPROM to idle state. */
336 /* Enter EEPROM access mode. */
337 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL);
339 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ);
341 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
343 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS);
348 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_DATAIN);
350 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_DATAIN);
352 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK);
354 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
358 for (i = 1; i <= 12; i++) {
359 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK);
361 if (!(CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT)) {
362 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
366 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
370 /* Turn off EEPROM access mode. */
378 /* Enter EEPROM access mode. */
379 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL);
381 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ);
383 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
385 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS);
388 /* Turn off EEPROM access mode. */
392 static void dc_eeprom_idle(sc)
397 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL);
399 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ);
401 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
403 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS);
406 for (i = 0; i < 25; i++) {
407 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
409 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK);
413 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
415 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CS);
417 CSR_WRITE_4(sc, DC_SIO, 0x00000000);
423 * Send a read command and address to the EEPROM, check for ACK.
425 static void dc_eeprom_putbyte(sc, addr)
431 d = DC_EECMD_READ >> 6;
434 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_DATAIN);
436 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_DATAIN);
438 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK);
440 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
445 * Feed in each bit and strobe the clock.
447 for (i = sc->dc_romwidth; i--;) {
448 if (addr & (1 << i)) {
449 SIO_SET(DC_SIO_EE_DATAIN);
451 SIO_CLR(DC_SIO_EE_DATAIN);
454 SIO_SET(DC_SIO_EE_CLK);
456 SIO_CLR(DC_SIO_EE_CLK);
464 * Read a word of data stored in the EEPROM at address 'addr.'
465 * The PNIC 82c168/82c169 has its own non-standard way to read
468 static void dc_eeprom_getword_pnic(sc, addr, dest)
476 CSR_WRITE_4(sc, DC_PN_SIOCTL, DC_PN_EEOPCODE_READ|addr);
478 for (i = 0; i < DC_TIMEOUT; i++) {
480 r = CSR_READ_4(sc, DC_SIO);
481 if (!(r & DC_PN_SIOCTL_BUSY)) {
482 *dest = (u_int16_t)(r & 0xFFFF);
491 * Read a word of data stored in the EEPROM at address 'addr.'
493 static void dc_eeprom_getword(sc, addr, dest)
501 /* Force EEPROM to idle state. */
504 /* Enter EEPROM access mode. */
505 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL);
507 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ);
509 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
511 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS);
515 * Send address of word we want to read.
517 dc_eeprom_putbyte(sc, addr);
520 * Start reading bits from EEPROM.
522 for (i = 0x8000; i; i >>= 1) {
523 SIO_SET(DC_SIO_EE_CLK);
525 if (CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT)
528 SIO_CLR(DC_SIO_EE_CLK);
532 /* Turn off EEPROM access mode. */
541 * Read a sequence of words from the EEPROM.
543 static void dc_read_eeprom(sc, dest, off, cnt, swap)
551 u_int16_t word = 0, *ptr;
553 for (i = 0; i < cnt; i++) {
555 dc_eeprom_getword_pnic(sc, off + i, &word);
557 dc_eeprom_getword(sc, off + i, &word);
558 ptr = (u_int16_t *)(dest + (i * 2));
569 * The following two routines are taken from the Macronix 98713
570 * Application Notes pp.19-21.
573 * Write a bit to the MII bus.
575 static void dc_mii_writebit(sc, bit)
580 CSR_WRITE_4(sc, DC_SIO,
581 DC_SIO_ROMCTL_WRITE|DC_SIO_MII_DATAOUT);
583 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_WRITE);
585 DC_SETBIT(sc, DC_SIO, DC_SIO_MII_CLK);
586 DC_CLRBIT(sc, DC_SIO, DC_SIO_MII_CLK);
592 * Read a bit from the MII bus.
594 static int dc_mii_readbit(sc)
597 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_READ|DC_SIO_MII_DIR);
598 CSR_READ_4(sc, DC_SIO);
599 DC_SETBIT(sc, DC_SIO, DC_SIO_MII_CLK);
600 DC_CLRBIT(sc, DC_SIO, DC_SIO_MII_CLK);
601 if (CSR_READ_4(sc, DC_SIO) & DC_SIO_MII_DATAIN)
608 * Sync the PHYs by setting data bit and strobing the clock 32 times.
610 static void dc_mii_sync(sc)
615 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_WRITE);
617 for (i = 0; i < 32; i++)
618 dc_mii_writebit(sc, 1);
624 * Clock a series of bits through the MII.
626 static void dc_mii_send(sc, bits, cnt)
633 for (i = (0x1 << (cnt - 1)); i; i >>= 1)
634 dc_mii_writebit(sc, bits & i);
638 * Read an PHY register through the MII.
640 static int dc_mii_readreg(sc, frame)
642 struct dc_mii_frame *frame;
650 * Set up frame for RX.
652 frame->mii_stdelim = DC_MII_STARTDELIM;
653 frame->mii_opcode = DC_MII_READOP;
654 frame->mii_turnaround = 0;
663 * Send command/address info.
665 dc_mii_send(sc, frame->mii_stdelim, 2);
666 dc_mii_send(sc, frame->mii_opcode, 2);
667 dc_mii_send(sc, frame->mii_phyaddr, 5);
668 dc_mii_send(sc, frame->mii_regaddr, 5);
672 dc_mii_writebit(sc, 1);
673 dc_mii_writebit(sc, 0);
677 ack = dc_mii_readbit(sc);
680 * Now try reading data bits. If the ack failed, we still
681 * need to clock through 16 cycles to keep the PHY(s) in sync.
684 for(i = 0; i < 16; i++) {
690 for (i = 0x8000; i; i >>= 1) {
692 if (dc_mii_readbit(sc))
693 frame->mii_data |= i;
699 dc_mii_writebit(sc, 0);
700 dc_mii_writebit(sc, 0);
710 * Write to a PHY register through the MII.
712 static int dc_mii_writereg(sc, frame)
714 struct dc_mii_frame *frame;
721 * Set up frame for TX.
724 frame->mii_stdelim = DC_MII_STARTDELIM;
725 frame->mii_opcode = DC_MII_WRITEOP;
726 frame->mii_turnaround = DC_MII_TURNAROUND;
733 dc_mii_send(sc, frame->mii_stdelim, 2);
734 dc_mii_send(sc, frame->mii_opcode, 2);
735 dc_mii_send(sc, frame->mii_phyaddr, 5);
736 dc_mii_send(sc, frame->mii_regaddr, 5);
737 dc_mii_send(sc, frame->mii_turnaround, 2);
738 dc_mii_send(sc, frame->mii_data, 16);
741 dc_mii_writebit(sc, 0);
742 dc_mii_writebit(sc, 0);
749 static int dc_miibus_readreg(dev, phy, reg)
753 struct dc_mii_frame frame;
755 int i, rval, phy_reg = 0;
757 sc = device_get_softc(dev);
758 bzero((char *)&frame, sizeof(frame));
761 * Note: both the AL981 and AN985 have internal PHYs,
762 * however the AL981 provides direct access to the PHY
763 * registers while the AN985 uses a serial MII interface.
764 * The AN985's MII interface is also buggy in that you
765 * can read from any MII address (0 to 31), but only address 1
766 * behaves normally. To deal with both cases, we pretend
767 * that the PHY is at MII address 1.
769 if (DC_IS_ADMTEK(sc) && phy != DC_ADMTEK_PHYADDR)
773 * Note: the ukphy probes of the RS7112 report a PHY at
774 * MII address 0 (possibly HomePNA?) and 1 (ethernet)
775 * so we only respond to correct one.
777 if (DC_IS_CONEXANT(sc) && phy != DC_CONEXANT_PHYADDR)
780 if (sc->dc_pmode != DC_PMODE_MII) {
781 if (phy == (MII_NPHY - 1)) {
785 * Fake something to make the probe
786 * code think there's a PHY here.
788 return(BMSR_MEDIAMASK);
792 return(DC_VENDORID_LO);
793 return(DC_VENDORID_DEC);
797 return(DC_DEVICEID_82C168);
798 return(DC_DEVICEID_21143);
808 if (DC_IS_PNIC(sc)) {
809 CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_READ |
810 (phy << 23) | (reg << 18));
811 for (i = 0; i < DC_TIMEOUT; i++) {
813 rval = CSR_READ_4(sc, DC_PN_MII);
814 if (!(rval & DC_PN_MII_BUSY)) {
816 return(rval == 0xFFFF ? 0 : rval);
822 if (DC_IS_COMET(sc)) {
825 phy_reg = DC_AL_BMCR;
828 phy_reg = DC_AL_BMSR;
831 phy_reg = DC_AL_VENID;
834 phy_reg = DC_AL_DEVID;
837 phy_reg = DC_AL_ANAR;
840 phy_reg = DC_AL_LPAR;
843 phy_reg = DC_AL_ANER;
846 if_printf(&sc->arpcom.ac_if,
847 "phy_read: bad phy register %x\n", reg);
852 rval = CSR_READ_4(sc, phy_reg) & 0x0000FFFF;
859 frame.mii_phyaddr = phy;
860 frame.mii_regaddr = reg;
861 if (sc->dc_type == DC_TYPE_98713) {
862 phy_reg = CSR_READ_4(sc, DC_NETCFG);
863 CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL);
865 dc_mii_readreg(sc, &frame);
866 if (sc->dc_type == DC_TYPE_98713)
867 CSR_WRITE_4(sc, DC_NETCFG, phy_reg);
869 return(frame.mii_data);
872 static int dc_miibus_writereg(dev, phy, reg, data)
877 struct dc_mii_frame frame;
880 sc = device_get_softc(dev);
881 bzero((char *)&frame, sizeof(frame));
883 if (DC_IS_ADMTEK(sc) && phy != DC_ADMTEK_PHYADDR)
886 if (DC_IS_CONEXANT(sc) && phy != DC_CONEXANT_PHYADDR)
889 if (DC_IS_PNIC(sc)) {
890 CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_WRITE |
891 (phy << 23) | (reg << 10) | data);
892 for (i = 0; i < DC_TIMEOUT; i++) {
893 if (!(CSR_READ_4(sc, DC_PN_MII) & DC_PN_MII_BUSY))
899 if (DC_IS_COMET(sc)) {
902 phy_reg = DC_AL_BMCR;
905 phy_reg = DC_AL_BMSR;
908 phy_reg = DC_AL_VENID;
911 phy_reg = DC_AL_DEVID;
914 phy_reg = DC_AL_ANAR;
917 phy_reg = DC_AL_LPAR;
920 phy_reg = DC_AL_ANER;
923 if_printf(&sc->arpcom.ac_if,
924 "phy_write: bad phy register %x\n", reg);
929 CSR_WRITE_4(sc, phy_reg, data);
933 frame.mii_phyaddr = phy;
934 frame.mii_regaddr = reg;
935 frame.mii_data = data;
937 if (sc->dc_type == DC_TYPE_98713) {
938 phy_reg = CSR_READ_4(sc, DC_NETCFG);
939 CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL);
941 dc_mii_writereg(sc, &frame);
942 if (sc->dc_type == DC_TYPE_98713)
943 CSR_WRITE_4(sc, DC_NETCFG, phy_reg);
948 static void dc_miibus_statchg(dev)
952 struct mii_data *mii;
955 sc = device_get_softc(dev);
956 if (DC_IS_ADMTEK(sc))
959 mii = device_get_softc(sc->dc_miibus);
960 ifm = &mii->mii_media;
961 if (DC_IS_DAVICOM(sc) &&
962 IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) {
963 dc_setcfg(sc, ifm->ifm_media);
964 sc->dc_if_media = ifm->ifm_media;
966 dc_setcfg(sc, mii->mii_media_active);
967 sc->dc_if_media = mii->mii_media_active;
974 * Special support for DM9102A cards with HomePNA PHYs. Note:
975 * with the Davicom DM9102A/DM9801 eval board that I have, it seems
976 * to be impossible to talk to the management interface of the DM9801
977 * PHY (its MDIO pin is not connected to anything). Consequently,
978 * the driver has to just 'know' about the additional mode and deal
979 * with it itself. *sigh*
981 static void dc_miibus_mediainit(dev)
985 struct mii_data *mii;
989 rev = pci_get_revid(dev);
991 sc = device_get_softc(dev);
992 mii = device_get_softc(sc->dc_miibus);
993 ifm = &mii->mii_media;
995 if (DC_IS_DAVICOM(sc) && rev >= DC_REVISION_DM9102A)
996 ifmedia_add(ifm, IFM_ETHER | IFM_HPNA_1, 0, NULL);
1001 #define DC_BITS_512 9
1002 #define DC_BITS_128 7
1003 #define DC_BITS_64 6
1006 dc_crc_mask(struct dc_softc *sc)
1009 * The hash table on the PNIC II and the MX98715AEC-C/D/E
1010 * chips is only 128 bits wide.
1012 if (sc->dc_flags & DC_128BIT_HASH)
1013 return ((1 << DC_BITS_128) - 1);
1015 /* The hash table on the MX98715BEC is only 64 bits wide. */
1016 if (sc->dc_flags & DC_64BIT_HASH)
1017 return ((1 << DC_BITS_64) - 1);
1019 return ((1 << DC_BITS_512) - 1);
1023 * 21143-style RX filter setup routine. Filter programming is done by
1024 * downloading a special setup frame into the TX engine. 21143, Macronix,
1025 * PNIC, PNIC II and Davicom chips are programmed this way.
1027 * We always program the chip using 'hash perfect' mode, i.e. one perfect
1028 * address (our node address) and a 512-bit hash filter for multicast
1029 * frames. We also sneak the broadcast address into the hash filter since
1032 void dc_setfilt_21143(sc)
1033 struct dc_softc *sc;
1035 struct dc_desc *sframe;
1036 u_int32_t h, crc_mask, *sp;
1037 struct ifmultiaddr *ifma;
1041 ifp = &sc->arpcom.ac_if;
1043 i = sc->dc_cdata.dc_tx_prod;
1044 DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT);
1045 sc->dc_cdata.dc_tx_cnt++;
1046 sframe = &sc->dc_ldata->dc_tx_list[i];
1047 sp = (u_int32_t *)&sc->dc_cdata.dc_sbuf;
1048 bzero((char *)sp, DC_SFRAME_LEN);
1050 sframe->dc_data = vtophys(&sc->dc_cdata.dc_sbuf);
1051 sframe->dc_ctl = DC_SFRAME_LEN | DC_TXCTL_SETUP | DC_TXCTL_TLINK |
1052 DC_FILTER_HASHPERF | DC_TXCTL_FINT;
1054 sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)&sc->dc_cdata.dc_sbuf;
1056 /* If we want promiscuous mode, set the allframes bit. */
1057 if (ifp->if_flags & IFF_PROMISC)
1058 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
1060 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
1062 if (ifp->if_flags & IFF_ALLMULTI)
1063 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
1065 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
1067 crc_mask = dc_crc_mask(sc);
1068 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL;
1069 ifma = ifma->ifma_link.le_next) {
1070 if (ifma->ifma_addr->sa_family != AF_LINK)
1073 LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
1074 ETHER_ADDR_LEN) & crc_mask;
1075 sp[h >> 4] |= 1 << (h & 0xF);
1078 if (ifp->if_flags & IFF_BROADCAST) {
1079 h = ether_crc32_le(ifp->if_broadcastaddr,
1080 ETHER_ADDR_LEN) & crc_mask;
1081 sp[h >> 4] |= 1 << (h & 0xF);
1084 /* Set our MAC address */
1085 sp[39] = ((u_int16_t *)sc->arpcom.ac_enaddr)[0];
1086 sp[40] = ((u_int16_t *)sc->arpcom.ac_enaddr)[1];
1087 sp[41] = ((u_int16_t *)sc->arpcom.ac_enaddr)[2];
1089 sframe->dc_status = DC_TXSTAT_OWN;
1090 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF);
1093 * The PNIC takes an exceedingly long time to process its
1094 * setup frame; wait 10ms after posting the setup frame
1095 * before proceeding, just so it has time to swallow its
1105 void dc_setfilt_admtek(sc)
1106 struct dc_softc *sc;
1111 u_int32_t hashes[2] = { 0, 0 };
1112 struct ifmultiaddr *ifma;
1114 ifp = &sc->arpcom.ac_if;
1116 /* Init our MAC address */
1117 CSR_WRITE_4(sc, DC_AL_PAR0, *(u_int32_t *)(&sc->arpcom.ac_enaddr[0]));
1118 CSR_WRITE_4(sc, DC_AL_PAR1, *(u_int32_t *)(&sc->arpcom.ac_enaddr[4]));
1120 /* If we want promiscuous mode, set the allframes bit. */
1121 if (ifp->if_flags & IFF_PROMISC)
1122 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
1124 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
1126 if (ifp->if_flags & IFF_ALLMULTI)
1127 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
1129 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
1131 /* first, zot all the existing hash bits */
1132 CSR_WRITE_4(sc, DC_AL_MAR0, 0);
1133 CSR_WRITE_4(sc, DC_AL_MAR1, 0);
1136 * If we're already in promisc or allmulti mode, we
1137 * don't have to bother programming the multicast filter.
1139 if (ifp->if_flags & (IFF_PROMISC|IFF_ALLMULTI))
1142 /* now program new ones */
1143 if (DC_IS_CENTAUR(sc))
1144 crc_mask = dc_crc_mask(sc);
1147 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL;
1148 ifma = ifma->ifma_link.le_next) {
1149 if (ifma->ifma_addr->sa_family != AF_LINK)
1151 if (DC_IS_CENTAUR(sc)) {
1153 LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
1154 ETHER_ADDR_LEN) & crc_mask;
1157 LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
1159 h = (h >> 26) & crc_mask;
1162 hashes[0] |= (1 << h);
1164 hashes[1] |= (1 << (h - 32));
1167 CSR_WRITE_4(sc, DC_AL_MAR0, hashes[0]);
1168 CSR_WRITE_4(sc, DC_AL_MAR1, hashes[1]);
1173 void dc_setfilt_asix(sc)
1174 struct dc_softc *sc;
1178 u_int32_t hashes[2] = { 0, 0 };
1179 struct ifmultiaddr *ifma;
1181 ifp = &sc->arpcom.ac_if;
1183 /* Init our MAC address */
1184 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR0);
1185 CSR_WRITE_4(sc, DC_AX_FILTDATA,
1186 *(u_int32_t *)(&sc->arpcom.ac_enaddr[0]));
1187 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR1);
1188 CSR_WRITE_4(sc, DC_AX_FILTDATA,
1189 *(u_int32_t *)(&sc->arpcom.ac_enaddr[4]));
1191 /* If we want promiscuous mode, set the allframes bit. */
1192 if (ifp->if_flags & IFF_PROMISC)
1193 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
1195 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
1197 if (ifp->if_flags & IFF_ALLMULTI)
1198 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
1200 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
1203 * The ASIX chip has a special bit to enable reception
1204 * of broadcast frames.
1206 if (ifp->if_flags & IFF_BROADCAST)
1207 DC_SETBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD);
1209 DC_CLRBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD);
1211 /* first, zot all the existing hash bits */
1212 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0);
1213 CSR_WRITE_4(sc, DC_AX_FILTDATA, 0);
1214 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1);
1215 CSR_WRITE_4(sc, DC_AX_FILTDATA, 0);
1218 * If we're already in promisc or allmulti mode, we
1219 * don't have to bother programming the multicast filter.
1221 if (ifp->if_flags & (IFF_PROMISC|IFF_ALLMULTI))
1224 /* now program new ones */
1225 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL;
1226 ifma = ifma->ifma_link.le_next) {
1227 if (ifma->ifma_addr->sa_family != AF_LINK)
1230 LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
1232 h = (h >> 26) & 0x3f;
1234 hashes[0] |= (1 << h);
1236 hashes[1] |= (1 << (h - 32));
1239 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0);
1240 CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[0]);
1241 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1);
1242 CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[1]);
1247 static void dc_setfilt(sc)
1248 struct dc_softc *sc;
1250 if (DC_IS_INTEL(sc) || DC_IS_MACRONIX(sc) || DC_IS_PNIC(sc) ||
1251 DC_IS_PNICII(sc) || DC_IS_DAVICOM(sc) || DC_IS_CONEXANT(sc))
1252 dc_setfilt_21143(sc);
1255 dc_setfilt_asix(sc);
1257 if (DC_IS_ADMTEK(sc))
1258 dc_setfilt_admtek(sc);
1264 * In order to fiddle with the
1265 * 'full-duplex' and '100Mbps' bits in the netconfig register, we
1266 * first have to put the transmit and/or receive logic in the idle state.
1268 static void dc_setcfg(sc, media)
1269 struct dc_softc *sc;
1275 if (IFM_SUBTYPE(media) == IFM_NONE)
1278 if (CSR_READ_4(sc, DC_NETCFG) & (DC_NETCFG_TX_ON|DC_NETCFG_RX_ON)) {
1280 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_TX_ON|DC_NETCFG_RX_ON));
1282 for (i = 0; i < DC_TIMEOUT; i++) {
1283 isr = CSR_READ_4(sc, DC_ISR);
1284 if (isr & DC_ISR_TX_IDLE ||
1285 (isr & DC_ISR_RX_STATE) == DC_RXSTATE_STOPPED)
1290 if (i == DC_TIMEOUT) {
1291 if_printf(&sc->arpcom.ac_if,
1292 "failed to force tx and rx to idle state\n");
1296 if (IFM_SUBTYPE(media) == IFM_100_TX) {
1297 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL);
1298 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT);
1299 if (sc->dc_pmode == DC_PMODE_MII) {
1302 if (DC_IS_INTEL(sc)) {
1303 /* there's a write enable bit here that reads as 1 */
1304 watchdogreg = CSR_READ_4(sc, DC_WATCHDOG);
1305 watchdogreg &= ~DC_WDOG_CTLWREN;
1306 watchdogreg |= DC_WDOG_JABBERDIS;
1307 CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg);
1309 DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS);
1311 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS|
1312 DC_NETCFG_PORTSEL|DC_NETCFG_SCRAMBLER));
1313 if (sc->dc_type == DC_TYPE_98713)
1314 DC_SETBIT(sc, DC_NETCFG, (DC_NETCFG_PCS|
1315 DC_NETCFG_SCRAMBLER));
1316 if (!DC_IS_DAVICOM(sc))
1317 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL);
1318 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF);
1319 if (DC_IS_INTEL(sc))
1320 dc_apply_fixup(sc, IFM_AUTO);
1322 if (DC_IS_PNIC(sc)) {
1323 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_SPEEDSEL);
1324 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP);
1325 DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL);
1327 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL);
1328 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS);
1329 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER);
1330 if (DC_IS_INTEL(sc))
1332 (media & IFM_GMASK) == IFM_FDX ?
1333 IFM_100_TX|IFM_FDX : IFM_100_TX);
1337 if (IFM_SUBTYPE(media) == IFM_10_T) {
1338 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL);
1339 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT);
1340 if (sc->dc_pmode == DC_PMODE_MII) {
1343 /* there's a write enable bit here that reads as 1 */
1344 if (DC_IS_INTEL(sc)) {
1345 watchdogreg = CSR_READ_4(sc, DC_WATCHDOG);
1346 watchdogreg &= ~DC_WDOG_CTLWREN;
1347 watchdogreg |= DC_WDOG_JABBERDIS;
1348 CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg);
1350 DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS);
1352 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS|
1353 DC_NETCFG_PORTSEL|DC_NETCFG_SCRAMBLER));
1354 if (sc->dc_type == DC_TYPE_98713)
1355 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS);
1356 if (!DC_IS_DAVICOM(sc))
1357 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL);
1358 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF);
1359 if (DC_IS_INTEL(sc))
1360 dc_apply_fixup(sc, IFM_AUTO);
1362 if (DC_IS_PNIC(sc)) {
1363 DC_PN_GPIO_CLRBIT(sc, DC_PN_GPIO_SPEEDSEL);
1364 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP);
1365 DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL);
1367 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL);
1368 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PCS);
1369 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER);
1370 if (DC_IS_INTEL(sc)) {
1371 DC_CLRBIT(sc, DC_SIARESET, DC_SIA_RESET);
1372 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF);
1373 if ((media & IFM_GMASK) == IFM_FDX)
1374 DC_SETBIT(sc, DC_10BTCTRL, 0x7F3D);
1376 DC_SETBIT(sc, DC_10BTCTRL, 0x7F3F);
1377 DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET);
1378 DC_CLRBIT(sc, DC_10BTCTRL,
1379 DC_TCTL_AUTONEGENBL);
1381 (media & IFM_GMASK) == IFM_FDX ?
1382 IFM_10_T|IFM_FDX : IFM_10_T);
1389 * If this is a Davicom DM9102A card with a DM9801 HomePNA
1390 * PHY and we want HomePNA mode, set the portsel bit to turn
1391 * on the external MII port.
1393 if (DC_IS_DAVICOM(sc)) {
1394 if (IFM_SUBTYPE(media) == IFM_HPNA_1) {
1395 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL);
1398 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL);
1402 if ((media & IFM_GMASK) == IFM_FDX) {
1403 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX);
1404 if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc))
1405 DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX);
1407 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX);
1408 if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc))
1409 DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX);
1413 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON|DC_NETCFG_RX_ON);
1418 static void dc_reset(sc)
1419 struct dc_softc *sc;
1423 DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET);
1425 for (i = 0; i < DC_TIMEOUT; i++) {
1427 if (!(CSR_READ_4(sc, DC_BUSCTL) & DC_BUSCTL_RESET))
1431 if (DC_IS_ASIX(sc) || DC_IS_ADMTEK(sc) || DC_IS_CONEXANT(sc)) {
1433 DC_CLRBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET);
1437 if (i == DC_TIMEOUT)
1438 if_printf(&sc->arpcom.ac_if, "reset never completed!\n");
1440 /* Wait a little while for the chip to get its brains in order. */
1443 CSR_WRITE_4(sc, DC_IMR, 0x00000000);
1444 CSR_WRITE_4(sc, DC_BUSCTL, 0x00000000);
1445 CSR_WRITE_4(sc, DC_NETCFG, 0x00000000);
1448 * Bring the SIA out of reset. In some cases, it looks
1449 * like failing to unreset the SIA soon enough gets it
1450 * into a state where it will never come out of reset
1451 * until we reset the whole chip again.
1453 if (DC_IS_INTEL(sc)) {
1454 DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET);
1455 CSR_WRITE_4(sc, DC_10BTCTRL, 0);
1456 CSR_WRITE_4(sc, DC_WATCHDOG, 0);
1462 static struct dc_type *dc_devtype(dev)
1470 while(t->dc_name != NULL) {
1471 if ((pci_get_vendor(dev) == t->dc_vid) &&
1472 (pci_get_device(dev) == t->dc_did)) {
1473 /* Check the PCI revision */
1474 rev = pci_get_revid(dev);
1475 if (t->dc_did == DC_DEVICEID_98713 &&
1476 rev >= DC_REVISION_98713A)
1478 if (t->dc_did == DC_DEVICEID_98713_CP &&
1479 rev >= DC_REVISION_98713A)
1481 if (t->dc_did == DC_DEVICEID_987x5 &&
1482 rev >= DC_REVISION_98715AEC_C)
1484 if (t->dc_did == DC_DEVICEID_987x5 &&
1485 rev >= DC_REVISION_98725)
1487 if (t->dc_did == DC_DEVICEID_AX88140A &&
1488 rev >= DC_REVISION_88141)
1490 if (t->dc_did == DC_DEVICEID_82C168 &&
1491 rev >= DC_REVISION_82C169)
1493 if (t->dc_did == DC_DEVICEID_DM9102 &&
1494 rev >= DC_REVISION_DM9102A)
1505 * Probe for a 21143 or clone chip. Check the PCI vendor and device
1506 * IDs against our list and return a device name if we find a match.
1507 * We do a little bit of extra work to identify the exact type of
1508 * chip. The MX98713 and MX98713A have the same PCI vendor/device ID,
1509 * but different revision IDs. The same is true for 98715/98715A
1510 * chips and the 98725, as well as the ASIX and ADMtek chips. In some
1511 * cases, the exact chip revision affects driver behavior.
1513 static int dc_probe(dev)
1518 t = dc_devtype(dev);
1521 device_set_desc(dev, t->dc_name);
1528 static void dc_acpi(dev)
1533 /* Find the location of the capabilities block */
1534 cptr = pci_read_config(dev, DC_PCI_CCAP, 4) & 0xFF;
1536 r = pci_read_config(dev, cptr, 4) & 0xFF;
1539 r = pci_read_config(dev, cptr + 4, 4);
1540 if (r & DC_PSTATE_D3) {
1541 u_int32_t iobase, membase, irq;
1542 struct dc_softc *sc;
1544 /* Save important PCI config data. */
1545 iobase = pci_read_config(dev, DC_PCI_CFBIO, 4);
1546 membase = pci_read_config(dev, DC_PCI_CFBMA, 4);
1547 irq = pci_read_config(dev, DC_PCI_CFIT, 4);
1549 sc = device_get_softc(dev);
1550 /* Reset the power state. */
1551 if_printf(&sc->arpcom.ac_if,
1552 "chip is in D%d power mode "
1553 "-- setting to D0\n", r & DC_PSTATE_D3);
1555 pci_write_config(dev, cptr + 4, r, 4);
1557 /* Restore PCI config data. */
1558 pci_write_config(dev, DC_PCI_CFBIO, iobase, 4);
1559 pci_write_config(dev, DC_PCI_CFBMA, membase, 4);
1560 pci_write_config(dev, DC_PCI_CFIT, irq, 4);
1565 static void dc_apply_fixup(sc, media)
1566 struct dc_softc *sc;
1569 struct dc_mediainfo *m;
1577 if (m->dc_media == media)
1585 for (i = 0, p = m->dc_reset_ptr; i < m->dc_reset_len; i++, p += 2) {
1586 reg = (p[0] | (p[1] << 8)) << 16;
1587 CSR_WRITE_4(sc, DC_WATCHDOG, reg);
1590 for (i = 0, p = m->dc_gp_ptr; i < m->dc_gp_len; i++, p += 2) {
1591 reg = (p[0] | (p[1] << 8)) << 16;
1592 CSR_WRITE_4(sc, DC_WATCHDOG, reg);
1598 static void dc_decode_leaf_sia(sc, l)
1599 struct dc_softc *sc;
1600 struct dc_eblock_sia *l;
1602 struct dc_mediainfo *m;
1604 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_INTWAIT | M_ZERO);
1605 if (l->dc_sia_code == DC_SIA_CODE_10BT)
1606 m->dc_media = IFM_10_T;
1608 if (l->dc_sia_code == DC_SIA_CODE_10BT_FDX)
1609 m->dc_media = IFM_10_T|IFM_FDX;
1611 if (l->dc_sia_code == DC_SIA_CODE_10B2)
1612 m->dc_media = IFM_10_2;
1614 if (l->dc_sia_code == DC_SIA_CODE_10B5)
1615 m->dc_media = IFM_10_5;
1618 m->dc_gp_ptr = (u_int8_t *)&l->dc_sia_gpio_ctl;
1620 m->dc_next = sc->dc_mi;
1623 sc->dc_pmode = DC_PMODE_SIA;
1628 static void dc_decode_leaf_sym(sc, l)
1629 struct dc_softc *sc;
1630 struct dc_eblock_sym *l;
1632 struct dc_mediainfo *m;
1634 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_INTWAIT | M_ZERO);
1635 if (l->dc_sym_code == DC_SYM_CODE_100BT)
1636 m->dc_media = IFM_100_TX;
1638 if (l->dc_sym_code == DC_SYM_CODE_100BT_FDX)
1639 m->dc_media = IFM_100_TX|IFM_FDX;
1642 m->dc_gp_ptr = (u_int8_t *)&l->dc_sym_gpio_ctl;
1644 m->dc_next = sc->dc_mi;
1647 sc->dc_pmode = DC_PMODE_SYM;
1652 static void dc_decode_leaf_mii(sc, l)
1653 struct dc_softc *sc;
1654 struct dc_eblock_mii *l;
1657 struct dc_mediainfo *m;
1659 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_INTWAIT | M_ZERO);
1660 /* We abuse IFM_AUTO to represent MII. */
1661 m->dc_media = IFM_AUTO;
1662 m->dc_gp_len = l->dc_gpr_len;
1665 p += sizeof(struct dc_eblock_mii);
1667 p += 2 * l->dc_gpr_len;
1668 m->dc_reset_len = *p;
1670 m->dc_reset_ptr = p;
1672 m->dc_next = sc->dc_mi;
1678 static void dc_read_srom(sc, bits)
1679 struct dc_softc *sc;
1685 sc->dc_srom = malloc(size, M_DEVBUF, M_INTWAIT);
1686 dc_read_eeprom(sc, (caddr_t)sc->dc_srom, 0, (size / 2), 0);
1689 static void dc_parse_21143_srom(sc)
1690 struct dc_softc *sc;
1692 struct dc_leaf_hdr *lhdr;
1693 struct dc_eblock_hdr *hdr;
1699 loff = sc->dc_srom[27];
1700 lhdr = (struct dc_leaf_hdr *)&(sc->dc_srom[loff]);
1703 ptr += sizeof(struct dc_leaf_hdr) - 1;
1705 * Look if we got a MII media block.
1707 for (i = 0; i < lhdr->dc_mcnt; i++) {
1708 hdr = (struct dc_eblock_hdr *)ptr;
1709 if (hdr->dc_type == DC_EBLOCK_MII)
1712 ptr += (hdr->dc_len & 0x7F);
1717 * Do the same thing again. Only use SIA and SYM media
1718 * blocks if no MII media block is available.
1721 ptr += sizeof(struct dc_leaf_hdr) - 1;
1722 for (i = 0; i < lhdr->dc_mcnt; i++) {
1723 hdr = (struct dc_eblock_hdr *)ptr;
1724 switch(hdr->dc_type) {
1726 dc_decode_leaf_mii(sc, (struct dc_eblock_mii *)hdr);
1730 dc_decode_leaf_sia(sc,
1731 (struct dc_eblock_sia *)hdr);
1735 dc_decode_leaf_sym(sc,
1736 (struct dc_eblock_sym *)hdr);
1739 /* Don't care. Yet. */
1742 ptr += (hdr->dc_len & 0x7F);
1750 * Attach the interface. Allocate softc structures, do ifmedia
1751 * setup and ethernet/BPF attach.
1753 static int dc_attach(dev)
1757 u_char eaddr[ETHER_ADDR_LEN];
1759 struct dc_softc *sc;
1762 int error = 0, rid, mac_offset;
1766 sc = device_get_softc(dev);
1767 bzero(sc, sizeof(struct dc_softc));
1768 callout_init(&sc->dc_stat_timer);
1770 ifp = &sc->arpcom.ac_if;
1771 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1774 * Handle power management nonsense.
1779 * Map control/status registers.
1781 pci_enable_busmaster(dev);
1782 pci_enable_io(dev, SYS_RES_IOPORT);
1783 pci_enable_io(dev, SYS_RES_MEMORY);
1784 command = pci_read_config(dev, PCIR_COMMAND, 4);
1786 #ifdef DC_USEIOSPACE
1787 if (!(command & PCIM_CMD_PORTEN)) {
1788 device_printf(dev, "failed to enable I/O ports!\n");
1793 if (!(command & PCIM_CMD_MEMEN)) {
1794 device_printf(dev, "failed to enable memory mapping!\n");
1801 sc->dc_res = bus_alloc_resource_any(dev, DC_RES, &rid, RF_ACTIVE);
1803 if (sc->dc_res == NULL) {
1804 device_printf(dev, "couldn't map ports/memory\n");
1809 sc->dc_btag = rman_get_bustag(sc->dc_res);
1810 sc->dc_bhandle = rman_get_bushandle(sc->dc_res);
1812 /* Allocate interrupt */
1814 sc->dc_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
1815 RF_SHAREABLE | RF_ACTIVE);
1817 if (sc->dc_irq == NULL) {
1818 device_printf(dev, "couldn't map interrupt\n");
1819 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res);
1824 error = bus_setup_intr(dev, sc->dc_irq, INTR_TYPE_NET,
1825 dc_intr, sc, &sc->dc_intrhand, NULL);
1828 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq);
1829 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res);
1830 device_printf(dev, "couldn't set up irq\n");
1834 /* Need this info to decide on a chip type. */
1835 sc->dc_info = dc_devtype(dev);
1836 revision = pci_get_revid(dev);
1838 /* Get the eeprom width, but PNIC has diff eeprom */
1839 if (sc->dc_info->dc_did != DC_DEVICEID_82C168)
1840 dc_eeprom_width(sc);
1842 switch(sc->dc_info->dc_did) {
1843 case DC_DEVICEID_21143:
1844 sc->dc_type = DC_TYPE_21143;
1845 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR;
1846 sc->dc_flags |= DC_REDUCED_MII_POLL;
1847 /* Save EEPROM contents so we can parse them later. */
1848 dc_read_srom(sc, sc->dc_romwidth);
1850 case DC_DEVICEID_DM9009:
1851 case DC_DEVICEID_DM9100:
1852 case DC_DEVICEID_DM9102:
1853 sc->dc_type = DC_TYPE_DM9102;
1854 sc->dc_flags |= DC_TX_COALESCE|DC_TX_INTR_ALWAYS;
1855 sc->dc_flags |= DC_REDUCED_MII_POLL|DC_TX_STORENFWD;
1856 sc->dc_pmode = DC_PMODE_MII;
1857 /* Increase the latency timer value. */
1858 command = pci_read_config(dev, DC_PCI_CFLT, 4);
1859 command &= 0xFFFF00FF;
1860 command |= 0x00008000;
1861 pci_write_config(dev, DC_PCI_CFLT, command, 4);
1863 case DC_DEVICEID_AL981:
1864 sc->dc_type = DC_TYPE_AL981;
1865 sc->dc_flags |= DC_TX_USE_TX_INTR;
1866 sc->dc_flags |= DC_TX_ADMTEK_WAR;
1867 sc->dc_pmode = DC_PMODE_MII;
1868 dc_read_srom(sc, sc->dc_romwidth);
1870 case DC_DEVICEID_AN985:
1871 case DC_DEVICEID_EN2242:
1872 case DC_DEVICEID_3CSOHOB:
1873 sc->dc_type = DC_TYPE_AN985;
1874 sc->dc_flags |= DC_64BIT_HASH;
1875 sc->dc_flags |= DC_TX_USE_TX_INTR;
1876 sc->dc_flags |= DC_TX_ADMTEK_WAR;
1877 sc->dc_pmode = DC_PMODE_MII;
1878 dc_read_srom(sc, sc->dc_romwidth);
1880 case DC_DEVICEID_98713:
1881 case DC_DEVICEID_98713_CP:
1882 if (revision < DC_REVISION_98713A) {
1883 sc->dc_type = DC_TYPE_98713;
1885 if (revision >= DC_REVISION_98713A) {
1886 sc->dc_type = DC_TYPE_98713A;
1887 sc->dc_flags |= DC_21143_NWAY;
1889 sc->dc_flags |= DC_REDUCED_MII_POLL;
1890 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR;
1892 case DC_DEVICEID_987x5:
1893 case DC_DEVICEID_EN1217:
1895 * Macronix MX98715AEC-C/D/E parts have only a
1896 * 128-bit hash table. We need to deal with these
1897 * in the same manner as the PNIC II so that we
1898 * get the right number of bits out of the
1901 if (revision >= DC_REVISION_98715AEC_C &&
1902 revision < DC_REVISION_98725)
1903 sc->dc_flags |= DC_128BIT_HASH;
1904 sc->dc_type = DC_TYPE_987x5;
1905 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR;
1906 sc->dc_flags |= DC_REDUCED_MII_POLL|DC_21143_NWAY;
1908 case DC_DEVICEID_98727:
1909 sc->dc_type = DC_TYPE_987x5;
1910 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR;
1911 sc->dc_flags |= DC_REDUCED_MII_POLL|DC_21143_NWAY;
1913 case DC_DEVICEID_82C115:
1914 sc->dc_type = DC_TYPE_PNICII;
1915 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR|DC_128BIT_HASH;
1916 sc->dc_flags |= DC_REDUCED_MII_POLL|DC_21143_NWAY;
1918 case DC_DEVICEID_82C168:
1919 sc->dc_type = DC_TYPE_PNIC;
1920 sc->dc_flags |= DC_TX_STORENFWD|DC_TX_INTR_ALWAYS;
1921 sc->dc_flags |= DC_PNIC_RX_BUG_WAR;
1922 sc->dc_pnic_rx_buf = malloc(DC_RXLEN * 5, M_DEVBUF, M_WAITOK);
1923 if (revision < DC_REVISION_82C169)
1924 sc->dc_pmode = DC_PMODE_SYM;
1926 case DC_DEVICEID_AX88140A:
1927 sc->dc_type = DC_TYPE_ASIX;
1928 sc->dc_flags |= DC_TX_USE_TX_INTR|DC_TX_INTR_FIRSTFRAG;
1929 sc->dc_flags |= DC_REDUCED_MII_POLL;
1930 sc->dc_pmode = DC_PMODE_MII;
1932 case DC_DEVICEID_RS7112:
1933 sc->dc_type = DC_TYPE_CONEXANT;
1934 sc->dc_flags |= DC_TX_INTR_ALWAYS;
1935 sc->dc_flags |= DC_REDUCED_MII_POLL;
1936 sc->dc_pmode = DC_PMODE_MII;
1937 dc_read_srom(sc, sc->dc_romwidth);
1940 device_printf(dev, "unknown device: %x\n", sc->dc_info->dc_did);
1944 /* Save the cache line size. */
1945 if (DC_IS_DAVICOM(sc))
1946 sc->dc_cachesize = 0;
1948 sc->dc_cachesize = pci_read_config(dev,
1949 DC_PCI_CFLT, 4) & 0xFF;
1951 /* Reset the adapter. */
1954 /* Take 21143 out of snooze mode */
1955 if (DC_IS_INTEL(sc)) {
1956 command = pci_read_config(dev, DC_PCI_CFDD, 4);
1957 command &= ~(DC_CFDD_SNOOZE_MODE|DC_CFDD_SLEEP_MODE);
1958 pci_write_config(dev, DC_PCI_CFDD, command, 4);
1962 * Try to learn something about the supported media.
1963 * We know that ASIX and ADMtek and Davicom devices
1964 * will *always* be using MII media, so that's a no-brainer.
1965 * The tricky ones are the Macronix/PNIC II and the
1968 if (DC_IS_INTEL(sc))
1969 dc_parse_21143_srom(sc);
1970 else if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) {
1971 if (sc->dc_type == DC_TYPE_98713)
1972 sc->dc_pmode = DC_PMODE_MII;
1974 sc->dc_pmode = DC_PMODE_SYM;
1975 } else if (!sc->dc_pmode)
1976 sc->dc_pmode = DC_PMODE_MII;
1979 * Get station address from the EEPROM.
1981 switch(sc->dc_type) {
1983 case DC_TYPE_98713A:
1985 case DC_TYPE_PNICII:
1986 dc_read_eeprom(sc, (caddr_t)&mac_offset,
1987 (DC_EE_NODEADDR_OFFSET / 2), 1, 0);
1988 dc_read_eeprom(sc, (caddr_t)&eaddr, (mac_offset / 2), 3, 0);
1991 dc_read_eeprom(sc, (caddr_t)&eaddr, 0, 3, 1);
1993 case DC_TYPE_DM9102:
1996 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0);
2000 bcopy(&sc->dc_srom[DC_AL_EE_NODEADDR], (caddr_t)&eaddr,
2002 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_AL_EE_NODEADDR, 3, 0);
2004 case DC_TYPE_CONEXANT:
2005 bcopy(sc->dc_srom + DC_CONEXANT_EE_NODEADDR, &eaddr, 6);
2008 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0);
2012 sc->dc_ldata = contigmalloc(sizeof(struct dc_list_data), M_DEVBUF,
2013 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
2015 if (sc->dc_ldata == NULL) {
2016 device_printf(dev, "no memory for list buffers!\n");
2017 if (sc->dc_pnic_rx_buf != NULL)
2018 free(sc->dc_pnic_rx_buf, M_DEVBUF);
2019 bus_teardown_intr(dev, sc->dc_irq, sc->dc_intrhand);
2020 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq);
2021 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res);
2026 bzero(sc->dc_ldata, sizeof(struct dc_list_data));
2029 ifp->if_mtu = ETHERMTU;
2030 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
2031 ifp->if_ioctl = dc_ioctl;
2032 ifp->if_start = dc_start;
2033 #ifdef DEVICE_POLLING
2034 ifp->if_poll = dc_poll;
2036 ifp->if_watchdog = dc_watchdog;
2037 ifp->if_init = dc_init;
2038 ifp->if_baudrate = 10000000;
2039 ifq_set_maxlen(&ifp->if_snd, DC_TX_LIST_CNT - 1);
2040 ifq_set_ready(&ifp->if_snd);
2043 * Do MII setup. If this is a 21143, check for a PHY on the
2044 * MII bus after applying any necessary fixups to twiddle the
2045 * GPIO bits. If we don't end up finding a PHY, restore the
2046 * old selection (SIA only or SIA/SYM) and attach the dcphy
2049 if (DC_IS_INTEL(sc)) {
2050 dc_apply_fixup(sc, IFM_AUTO);
2052 sc->dc_pmode = DC_PMODE_MII;
2055 error = mii_phy_probe(dev, &sc->dc_miibus,
2056 dc_ifmedia_upd, dc_ifmedia_sts);
2058 if (error && DC_IS_INTEL(sc)) {
2060 if (sc->dc_pmode != DC_PMODE_SIA)
2061 sc->dc_pmode = DC_PMODE_SYM;
2062 sc->dc_flags |= DC_21143_NWAY;
2063 mii_phy_probe(dev, &sc->dc_miibus,
2064 dc_ifmedia_upd, dc_ifmedia_sts);
2066 * For non-MII cards, we need to have the 21143
2067 * drive the LEDs. Except there are some systems
2068 * like the NEC VersaPro NoteBook PC which have no
2069 * LEDs, and twiddling these bits has adverse effects
2070 * on them. (I.e. you suddenly can't get a link.)
2072 if (pci_read_config(dev, DC_PCI_CSID, 4) != 0x80281033)
2073 sc->dc_flags |= DC_TULIP_LEDS;
2078 device_printf(dev, "MII without any PHY!\n");
2079 contigfree(sc->dc_ldata, sizeof(struct dc_list_data),
2081 if (sc->dc_pnic_rx_buf != NULL)
2082 free(sc->dc_pnic_rx_buf, M_DEVBUF);
2083 bus_teardown_intr(dev, sc->dc_irq, sc->dc_intrhand);
2084 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq);
2085 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res);
2091 * Call MI attach routine.
2093 ether_ifattach(ifp, eaddr);
2095 if (DC_IS_ADMTEK(sc)) {
2097 * Set automatic TX underrun recovery for the ADMtek chips
2099 DC_SETBIT(sc, DC_AL_CR, DC_AL_CR_ATUR);
2103 * Tell the upper layer(s) we support long frames.
2105 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
2113 static int dc_detach(dev)
2116 struct dc_softc *sc;
2119 struct dc_mediainfo *m;
2123 sc = device_get_softc(dev);
2124 ifp = &sc->arpcom.ac_if;
2127 ether_ifdetach(ifp);
2129 bus_generic_detach(dev);
2130 device_delete_child(dev, sc->dc_miibus);
2132 bus_teardown_intr(dev, sc->dc_irq, sc->dc_intrhand);
2133 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq);
2134 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res);
2136 contigfree(sc->dc_ldata, sizeof(struct dc_list_data), M_DEVBUF);
2137 if (sc->dc_pnic_rx_buf != NULL)
2138 free(sc->dc_pnic_rx_buf, M_DEVBUF);
2140 while(sc->dc_mi != NULL) {
2141 m = sc->dc_mi->dc_next;
2142 free(sc->dc_mi, M_DEVBUF);
2145 free(sc->dc_srom, M_DEVBUF);
2153 * Initialize the transmit descriptors.
2155 static int dc_list_tx_init(sc)
2156 struct dc_softc *sc;
2158 struct dc_chain_data *cd;
2159 struct dc_list_data *ld;
2164 for (i = 0; i < DC_TX_LIST_CNT; i++) {
2165 if (i == (DC_TX_LIST_CNT - 1)) {
2166 ld->dc_tx_list[i].dc_next =
2167 vtophys(&ld->dc_tx_list[0]);
2169 ld->dc_tx_list[i].dc_next =
2170 vtophys(&ld->dc_tx_list[i + 1]);
2172 cd->dc_tx_chain[i] = NULL;
2173 ld->dc_tx_list[i].dc_data = 0;
2174 ld->dc_tx_list[i].dc_ctl = 0;
2177 cd->dc_tx_prod = cd->dc_tx_cons = cd->dc_tx_cnt = 0;
2184 * Initialize the RX descriptors and allocate mbufs for them. Note that
2185 * we arrange the descriptors in a closed ring, so that the last descriptor
2186 * points back to the first.
2188 static int dc_list_rx_init(sc)
2189 struct dc_softc *sc;
2191 struct dc_chain_data *cd;
2192 struct dc_list_data *ld;
2198 for (i = 0; i < DC_RX_LIST_CNT; i++) {
2199 if (dc_newbuf(sc, i, NULL) == ENOBUFS)
2201 if (i == (DC_RX_LIST_CNT - 1)) {
2202 ld->dc_rx_list[i].dc_next =
2203 vtophys(&ld->dc_rx_list[0]);
2205 ld->dc_rx_list[i].dc_next =
2206 vtophys(&ld->dc_rx_list[i + 1]);
2216 * Initialize an RX descriptor and attach an MBUF cluster.
2218 static int dc_newbuf(sc, i, m)
2219 struct dc_softc *sc;
2223 struct mbuf *m_new = NULL;
2226 c = &sc->dc_ldata->dc_rx_list[i];
2229 MGETHDR(m_new, MB_DONTWAIT, MT_DATA);
2233 MCLGET(m_new, MB_DONTWAIT);
2234 if (!(m_new->m_flags & M_EXT)) {
2238 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
2241 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
2242 m_new->m_data = m_new->m_ext.ext_buf;
2245 m_adj(m_new, sizeof(u_int64_t));
2248 * If this is a PNIC chip, zero the buffer. This is part
2249 * of the workaround for the receive bug in the 82c168 and
2252 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR)
2253 bzero((char *)mtod(m_new, char *), m_new->m_len);
2255 sc->dc_cdata.dc_rx_chain[i] = m_new;
2256 c->dc_data = vtophys(mtod(m_new, caddr_t));
2257 c->dc_ctl = DC_RXCTL_RLINK | DC_RXLEN;
2258 c->dc_status = DC_RXSTAT_OWN;
2265 * The PNIC chip has a terrible bug in it that manifests itself during
2266 * periods of heavy activity. The exact mode of failure if difficult to
2267 * pinpoint: sometimes it only happens in promiscuous mode, sometimes it
2268 * will happen on slow machines. The bug is that sometimes instead of
2269 * uploading one complete frame during reception, it uploads what looks
2270 * like the entire contents of its FIFO memory. The frame we want is at
2271 * the end of the whole mess, but we never know exactly how much data has
2272 * been uploaded, so salvaging the frame is hard.
2274 * There is only one way to do it reliably, and it's disgusting.
2275 * Here's what we know:
2277 * - We know there will always be somewhere between one and three extra
2278 * descriptors uploaded.
2280 * - We know the desired received frame will always be at the end of the
2281 * total data upload.
2283 * - We know the size of the desired received frame because it will be
2284 * provided in the length field of the status word in the last descriptor.
2286 * Here's what we do:
2288 * - When we allocate buffers for the receive ring, we bzero() them.
2289 * This means that we know that the buffer contents should be all
2290 * zeros, except for data uploaded by the chip.
2292 * - We also force the PNIC chip to upload frames that include the
2293 * ethernet CRC at the end.
2295 * - We gather all of the bogus frame data into a single buffer.
2297 * - We then position a pointer at the end of this buffer and scan
2298 * backwards until we encounter the first non-zero byte of data.
2299 * This is the end of the received frame. We know we will encounter
2300 * some data at the end of the frame because the CRC will always be
2301 * there, so even if the sender transmits a packet of all zeros,
2302 * we won't be fooled.
2304 * - We know the size of the actual received frame, so we subtract
2305 * that value from the current pointer location. This brings us
2306 * to the start of the actual received packet.
2308 * - We copy this into an mbuf and pass it on, along with the actual
2311 * The performance hit is tremendous, but it beats dropping frames all
2315 #define DC_WHOLEFRAME (DC_RXSTAT_FIRSTFRAG|DC_RXSTAT_LASTFRAG)
2316 static void dc_pnic_rx_bug_war(sc, idx)
2317 struct dc_softc *sc;
2320 struct dc_desc *cur_rx;
2321 struct dc_desc *c = NULL;
2322 struct mbuf *m = NULL;
2325 u_int32_t rxstat = 0;
2327 i = sc->dc_pnic_rx_bug_save;
2328 cur_rx = &sc->dc_ldata->dc_rx_list[idx];
2329 ptr = sc->dc_pnic_rx_buf;
2330 bzero(ptr, DC_RXLEN * 5);
2332 /* Copy all the bytes from the bogus buffers. */
2334 c = &sc->dc_ldata->dc_rx_list[i];
2335 rxstat = c->dc_status;
2336 m = sc->dc_cdata.dc_rx_chain[i];
2337 bcopy(mtod(m, char *), ptr, DC_RXLEN);
2339 /* If this is the last buffer, break out. */
2340 if (i == idx || rxstat & DC_RXSTAT_LASTFRAG)
2342 dc_newbuf(sc, i, m);
2343 DC_INC(i, DC_RX_LIST_CNT);
2346 /* Find the length of the actual receive frame. */
2347 total_len = DC_RXBYTES(rxstat);
2349 /* Scan backwards until we hit a non-zero byte. */
2354 if ((uintptr_t)(ptr) & 0x3)
2357 /* Now find the start of the frame. */
2359 if (ptr < sc->dc_pnic_rx_buf)
2360 ptr = sc->dc_pnic_rx_buf;
2363 * Now copy the salvaged frame to the last mbuf and fake up
2364 * the status word to make it look like a successful
2367 dc_newbuf(sc, i, m);
2368 bcopy(ptr, mtod(m, char *), total_len);
2369 cur_rx->dc_status = rxstat | DC_RXSTAT_FIRSTFRAG;
2375 * This routine searches the RX ring for dirty descriptors in the
2376 * event that the rxeof routine falls out of sync with the chip's
2377 * current descriptor pointer. This may happen sometimes as a result
2378 * of a "no RX buffer available" condition that happens when the chip
2379 * consumes all of the RX buffers before the driver has a chance to
2380 * process the RX ring. This routine may need to be called more than
2381 * once to bring the driver back in sync with the chip, however we
2382 * should still be getting RX DONE interrupts to drive the search
2383 * for new packets in the RX ring, so we should catch up eventually.
2385 static int dc_rx_resync(sc)
2386 struct dc_softc *sc;
2389 struct dc_desc *cur_rx;
2391 pos = sc->dc_cdata.dc_rx_prod;
2393 for (i = 0; i < DC_RX_LIST_CNT; i++) {
2394 cur_rx = &sc->dc_ldata->dc_rx_list[pos];
2395 if (!(cur_rx->dc_status & DC_RXSTAT_OWN))
2397 DC_INC(pos, DC_RX_LIST_CNT);
2400 /* If the ring really is empty, then just return. */
2401 if (i == DC_RX_LIST_CNT)
2404 /* We've fallen behing the chip: catch it. */
2405 sc->dc_cdata.dc_rx_prod = pos;
2411 * A frame has been uploaded: pass the resulting mbuf chain up to
2412 * the higher level protocols.
2414 static void dc_rxeof(sc)
2415 struct dc_softc *sc;
2419 struct dc_desc *cur_rx;
2420 int i, total_len = 0;
2423 ifp = &sc->arpcom.ac_if;
2424 i = sc->dc_cdata.dc_rx_prod;
2426 while(!(sc->dc_ldata->dc_rx_list[i].dc_status & DC_RXSTAT_OWN)) {
2428 #ifdef DEVICE_POLLING
2429 if (ifp->if_flags & IFF_POLLING) {
2430 if (sc->rxcycles <= 0)
2434 #endif /* DEVICE_POLLING */
2435 cur_rx = &sc->dc_ldata->dc_rx_list[i];
2436 rxstat = cur_rx->dc_status;
2437 m = sc->dc_cdata.dc_rx_chain[i];
2438 total_len = DC_RXBYTES(rxstat);
2440 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) {
2441 if ((rxstat & DC_WHOLEFRAME) != DC_WHOLEFRAME) {
2442 if (rxstat & DC_RXSTAT_FIRSTFRAG)
2443 sc->dc_pnic_rx_bug_save = i;
2444 if ((rxstat & DC_RXSTAT_LASTFRAG) == 0) {
2445 DC_INC(i, DC_RX_LIST_CNT);
2448 dc_pnic_rx_bug_war(sc, i);
2449 rxstat = cur_rx->dc_status;
2450 total_len = DC_RXBYTES(rxstat);
2454 sc->dc_cdata.dc_rx_chain[i] = NULL;
2457 * If an error occurs, update stats, clear the
2458 * status word and leave the mbuf cluster in place:
2459 * it should simply get re-used next time this descriptor
2460 * comes up in the ring. However, don't report long
2461 * frames as errors since they could be vlans
2463 if ((rxstat & DC_RXSTAT_RXERR)){
2464 if (!(rxstat & DC_RXSTAT_GIANT) ||
2465 (rxstat & (DC_RXSTAT_CRCERR | DC_RXSTAT_DRIBBLE |
2466 DC_RXSTAT_MIIERE | DC_RXSTAT_COLLSEEN |
2467 DC_RXSTAT_RUNT | DC_RXSTAT_DE))) {
2469 if (rxstat & DC_RXSTAT_COLLSEEN)
2470 ifp->if_collisions++;
2471 dc_newbuf(sc, i, m);
2472 if (rxstat & DC_RXSTAT_CRCERR) {
2473 DC_INC(i, DC_RX_LIST_CNT);
2482 /* No errors; receive the packet. */
2483 total_len -= ETHER_CRC_LEN;
2487 * On the x86 we do not have alignment problems, so try to
2488 * allocate a new buffer for the receive ring, and pass up
2489 * the one where the packet is already, saving the expensive
2490 * copy done in m_devget().
2491 * If we are on an architecture with alignment problems, or
2492 * if the allocation fails, then use m_devget and leave the
2493 * existing buffer in the receive ring.
2495 if (dc_quick && dc_newbuf(sc, i, NULL) == 0) {
2496 m->m_pkthdr.rcvif = ifp;
2497 m->m_pkthdr.len = m->m_len = total_len;
2498 DC_INC(i, DC_RX_LIST_CNT);
2504 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN,
2505 total_len + ETHER_ALIGN, 0, ifp, NULL);
2506 dc_newbuf(sc, i, m);
2507 DC_INC(i, DC_RX_LIST_CNT);
2512 m_adj(m0, ETHER_ALIGN);
2517 (*ifp->if_input)(ifp, m);
2520 sc->dc_cdata.dc_rx_prod = i;
2524 * A frame was downloaded to the chip. It's safe for us to clean up
2530 struct dc_softc *sc;
2532 struct dc_desc *cur_tx = NULL;
2536 ifp = &sc->arpcom.ac_if;
2539 * Go through our tx list and free mbufs for those
2540 * frames that have been transmitted.
2542 idx = sc->dc_cdata.dc_tx_cons;
2543 while(idx != sc->dc_cdata.dc_tx_prod) {
2546 cur_tx = &sc->dc_ldata->dc_tx_list[idx];
2547 txstat = cur_tx->dc_status;
2549 if (txstat & DC_TXSTAT_OWN)
2552 if (!(cur_tx->dc_ctl & DC_TXCTL_LASTFRAG) ||
2553 cur_tx->dc_ctl & DC_TXCTL_SETUP) {
2554 if (cur_tx->dc_ctl & DC_TXCTL_SETUP) {
2556 * Yes, the PNIC is so brain damaged
2557 * that it will sometimes generate a TX
2558 * underrun error while DMAing the RX
2559 * filter setup frame. If we detect this,
2560 * we have to send the setup frame again,
2561 * or else the filter won't be programmed
2564 if (DC_IS_PNIC(sc)) {
2565 if (txstat & DC_TXSTAT_ERRSUM)
2568 sc->dc_cdata.dc_tx_chain[idx] = NULL;
2570 sc->dc_cdata.dc_tx_cnt--;
2571 DC_INC(idx, DC_TX_LIST_CNT);
2575 if (DC_IS_CONEXANT(sc)) {
2577 * For some reason Conexant chips like
2578 * setting the CARRLOST flag even when
2579 * the carrier is there. In CURRENT we
2580 * have the same problem for Xircom
2583 if (/*sc->dc_type == DC_TYPE_21143 &&*/
2584 sc->dc_pmode == DC_PMODE_MII &&
2585 ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM|
2586 DC_TXSTAT_NOCARRIER)))
2587 txstat &= ~DC_TXSTAT_ERRSUM;
2589 if (/*sc->dc_type == DC_TYPE_21143 &&*/
2590 sc->dc_pmode == DC_PMODE_MII &&
2591 ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM|
2592 DC_TXSTAT_NOCARRIER|DC_TXSTAT_CARRLOST)))
2593 txstat &= ~DC_TXSTAT_ERRSUM;
2596 if (txstat & DC_TXSTAT_ERRSUM) {
2598 if (txstat & DC_TXSTAT_EXCESSCOLL)
2599 ifp->if_collisions++;
2600 if (txstat & DC_TXSTAT_LATECOLL)
2601 ifp->if_collisions++;
2602 if (!(txstat & DC_TXSTAT_UNDERRUN)) {
2608 ifp->if_collisions += (txstat & DC_TXSTAT_COLLCNT) >> 3;
2611 if (sc->dc_cdata.dc_tx_chain[idx] != NULL) {
2612 m_freem(sc->dc_cdata.dc_tx_chain[idx]);
2613 sc->dc_cdata.dc_tx_chain[idx] = NULL;
2616 sc->dc_cdata.dc_tx_cnt--;
2617 DC_INC(idx, DC_TX_LIST_CNT);
2620 if (idx != sc->dc_cdata.dc_tx_cons) {
2621 /* some buffers have been freed */
2622 sc->dc_cdata.dc_tx_cons = idx;
2623 ifp->if_flags &= ~IFF_OACTIVE;
2625 ifp->if_timer = (sc->dc_cdata.dc_tx_cnt == 0) ? 0 : 5;
2630 static void dc_tick(xsc)
2633 struct dc_softc *sc;
2634 struct mii_data *mii;
2642 ifp = &sc->arpcom.ac_if;
2643 mii = device_get_softc(sc->dc_miibus);
2645 if (sc->dc_flags & DC_REDUCED_MII_POLL) {
2646 if (sc->dc_flags & DC_21143_NWAY) {
2647 r = CSR_READ_4(sc, DC_10BTSTAT);
2648 if (IFM_SUBTYPE(mii->mii_media_active) ==
2649 IFM_100_TX && (r & DC_TSTAT_LS100)) {
2653 if (IFM_SUBTYPE(mii->mii_media_active) ==
2654 IFM_10_T && (r & DC_TSTAT_LS10)) {
2658 if (sc->dc_link == 0)
2661 r = CSR_READ_4(sc, DC_ISR);
2662 if ((r & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT &&
2663 sc->dc_cdata.dc_tx_cnt == 0)
2665 if (!(mii->mii_media_status & IFM_ACTIVE))
2672 * When the init routine completes, we expect to be able to send
2673 * packets right away, and in fact the network code will send a
2674 * gratuitous ARP the moment the init routine marks the interface
2675 * as running. However, even though the MAC may have been initialized,
2676 * there may be a delay of a few seconds before the PHY completes
2677 * autonegotiation and the link is brought up. Any transmissions
2678 * made during that delay will be lost. Dealing with this is tricky:
2679 * we can't just pause in the init routine while waiting for the
2680 * PHY to come ready since that would bring the whole system to
2681 * a screeching halt for several seconds.
2683 * What we do here is prevent the TX start routine from sending
2684 * any packets until a link has been established. After the
2685 * interface has been initialized, the tick routine will poll
2686 * the state of the PHY until the IFM_ACTIVE flag is set. Until
2687 * that time, packets will stay in the send queue, and once the
2688 * link comes up, they will be flushed out to the wire.
2692 if (mii->mii_media_status & IFM_ACTIVE &&
2693 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
2695 if (!ifq_is_empty(&ifp->if_snd))
2700 if (sc->dc_flags & DC_21143_NWAY && !sc->dc_link)
2701 callout_reset(&sc->dc_stat_timer, hz / 10, dc_tick, sc);
2703 callout_reset(&sc->dc_stat_timer, hz, dc_tick, sc);
2711 * A transmit underrun has occurred. Back off the transmit threshold,
2712 * or switch to store and forward mode if we have to.
2714 static void dc_tx_underrun(sc)
2715 struct dc_softc *sc;
2720 if (DC_IS_DAVICOM(sc))
2723 if (DC_IS_INTEL(sc)) {
2725 * The real 21143 requires that the transmitter be idle
2726 * in order to change the transmit threshold or store
2727 * and forward state.
2729 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON);
2731 for (i = 0; i < DC_TIMEOUT; i++) {
2732 isr = CSR_READ_4(sc, DC_ISR);
2733 if (isr & DC_ISR_TX_IDLE)
2737 if (i == DC_TIMEOUT) {
2738 if_printf(&sc->arpcom.ac_if,
2739 "failed to force tx to idle state\n");
2744 if_printf(&sc->arpcom.ac_if, "TX underrun -- ");
2745 sc->dc_txthresh += DC_TXTHRESH_INC;
2746 if (sc->dc_txthresh > DC_TXTHRESH_MAX) {
2747 printf("using store and forward mode\n");
2748 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD);
2750 printf("increasing TX threshold\n");
2751 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_THRESH);
2752 DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh);
2755 if (DC_IS_INTEL(sc))
2756 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON);
2761 #ifdef DEVICE_POLLING
2764 dc_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
2766 struct dc_softc *sc = ifp->if_softc;
2771 /* Disable interrupts */
2772 CSR_WRITE_4(sc, DC_IMR, 0x00000000);
2774 case POLL_DEREGISTER:
2775 /* Re-enable interrupts. */
2776 CSR_WRITE_4(sc, DC_IMR, DC_INTRS);
2779 sc->rxcycles = count;
2782 if ((ifp->if_flags & IFF_OACTIVE) == 0 && !ifq_is_empty(&ifp->if_snd))
2785 case POLL_AND_CHECK_STATUS:
2786 sc->rxcycles = count;
2789 if ((ifp->if_flags & IFF_OACTIVE) == 0 && !ifq_is_empty(&ifp->if_snd))
2791 status = CSR_READ_4(sc, DC_ISR);
2792 status &= (DC_ISR_RX_WATDOGTIMEO|DC_ISR_RX_NOBUF|
2793 DC_ISR_TX_NOBUF|DC_ISR_TX_IDLE|DC_ISR_TX_UNDERRUN|
2797 /* ack what we have */
2798 CSR_WRITE_4(sc, DC_ISR, status);
2800 if (status & (DC_ISR_RX_WATDOGTIMEO|DC_ISR_RX_NOBUF) ) {
2801 u_int32_t r = CSR_READ_4(sc, DC_FRAMESDISCARDED);
2802 ifp->if_ierrors += (r & 0xffff) + ((r >> 17) & 0x7ff);
2804 if (dc_rx_resync(sc))
2807 /* restart transmit unit if necessary */
2808 if (status & DC_ISR_TX_IDLE && sc->dc_cdata.dc_tx_cnt)
2809 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF);
2811 if (status & DC_ISR_TX_UNDERRUN)
2814 if (status & DC_ISR_BUS_ERR) {
2815 if_printf(ifp, "dc_poll: bus error\n");
2822 #endif /* DEVICE_POLLING */
2824 static void dc_intr(arg)
2827 struct dc_softc *sc;
2833 if (sc->suspended) {
2837 ifp = &sc->arpcom.ac_if;
2839 if ( (CSR_READ_4(sc, DC_ISR) & DC_INTRS) == 0)
2842 /* Suppress unwanted interrupts */
2843 if (!(ifp->if_flags & IFF_UP)) {
2844 if (CSR_READ_4(sc, DC_ISR) & DC_INTRS)
2849 /* Disable interrupts. */
2850 CSR_WRITE_4(sc, DC_IMR, 0x00000000);
2852 while((status = CSR_READ_4(sc, DC_ISR)) & DC_INTRS) {
2854 CSR_WRITE_4(sc, DC_ISR, status);
2856 if (status & DC_ISR_RX_OK) {
2858 curpkts = ifp->if_ipackets;
2860 if (curpkts == ifp->if_ipackets) {
2861 while(dc_rx_resync(sc))
2866 if (status & (DC_ISR_TX_OK|DC_ISR_TX_NOBUF))
2869 if (status & DC_ISR_TX_IDLE) {
2871 if (sc->dc_cdata.dc_tx_cnt) {
2872 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON);
2873 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF);
2877 if (status & DC_ISR_TX_UNDERRUN)
2880 if ((status & DC_ISR_RX_WATDOGTIMEO)
2881 || (status & DC_ISR_RX_NOBUF)) {
2883 curpkts = ifp->if_ipackets;
2885 if (curpkts == ifp->if_ipackets) {
2886 while(dc_rx_resync(sc))
2891 if (status & DC_ISR_BUS_ERR) {
2897 /* Re-enable interrupts. */
2898 CSR_WRITE_4(sc, DC_IMR, DC_INTRS);
2900 if (!ifq_is_empty(&ifp->if_snd))
2907 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
2908 * pointers to the fragment pointers.
2910 static int dc_encap(sc, m_head, txidx)
2911 struct dc_softc *sc;
2912 struct mbuf *m_head;
2915 struct dc_desc *f = NULL;
2917 int frag, cur, cnt = 0;
2920 * Start packing the mbufs in this chain into
2921 * the fragment pointers. Stop when we run out
2922 * of fragments or hit the end of the mbuf chain.
2925 cur = frag = *txidx;
2927 for (m = m_head; m != NULL; m = m->m_next) {
2928 if (m->m_len != 0) {
2929 if (sc->dc_flags & DC_TX_ADMTEK_WAR) {
2930 if (*txidx != sc->dc_cdata.dc_tx_prod &&
2931 frag == (DC_TX_LIST_CNT - 1))
2934 if ((DC_TX_LIST_CNT -
2935 (sc->dc_cdata.dc_tx_cnt + cnt)) < 5)
2938 f = &sc->dc_ldata->dc_tx_list[frag];
2939 f->dc_ctl = DC_TXCTL_TLINK | m->m_len;
2942 f->dc_ctl |= DC_TXCTL_FIRSTFRAG;
2944 f->dc_status = DC_TXSTAT_OWN;
2945 f->dc_data = vtophys(mtod(m, vm_offset_t));
2947 DC_INC(frag, DC_TX_LIST_CNT);
2955 sc->dc_cdata.dc_tx_cnt += cnt;
2956 sc->dc_cdata.dc_tx_chain[cur] = m_head;
2957 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= DC_TXCTL_LASTFRAG;
2958 if (sc->dc_flags & DC_TX_INTR_FIRSTFRAG)
2959 sc->dc_ldata->dc_tx_list[*txidx].dc_ctl |= DC_TXCTL_FINT;
2960 if (sc->dc_flags & DC_TX_INTR_ALWAYS)
2961 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= DC_TXCTL_FINT;
2962 if (sc->dc_flags & DC_TX_USE_TX_INTR && sc->dc_cdata.dc_tx_cnt > 64)
2963 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= DC_TXCTL_FINT;
2964 sc->dc_ldata->dc_tx_list[*txidx].dc_status = DC_TXSTAT_OWN;
2971 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
2972 * to the mbuf data regions directly in the transmit lists. We also save a
2973 * copy of the pointers since the transmit list fragment pointers are
2974 * physical addresses.
2977 static void dc_start(ifp)
2980 struct dc_softc *sc;
2981 struct mbuf *m_head = NULL, *m_new;
2982 int did_defrag, idx;
2989 if (ifp->if_flags & IFF_OACTIVE)
2992 idx = sc->dc_cdata.dc_tx_prod;
2994 while(sc->dc_cdata.dc_tx_chain[idx] == NULL) {
2996 m_head = ifq_poll(&ifp->if_snd);
3000 if (sc->dc_flags & DC_TX_COALESCE &&
3001 m_head->m_next != NULL) {
3003 * Check first if coalescing allows us to queue
3004 * the packet. We don't want to loose it if
3005 * the TX queue is full.
3007 if ((sc->dc_flags & DC_TX_ADMTEK_WAR) &&
3008 idx != sc->dc_cdata.dc_tx_prod &&
3009 idx == (DC_TX_LIST_CNT - 1)) {
3010 ifp->if_flags |= IFF_OACTIVE;
3013 if ((DC_TX_LIST_CNT - sc->dc_cdata.dc_tx_cnt) < 5) {
3014 ifp->if_flags |= IFF_OACTIVE;
3018 /* only coalesce if have >1 mbufs */
3019 m_new = m_defrag_nofree(m_head, MB_DONTWAIT);
3020 if (m_new == NULL) {
3021 ifp->if_flags |= IFF_OACTIVE;
3029 if (dc_encap(sc, m_head, &idx)) {
3032 m_new = ifq_dequeue(&ifp->if_snd);
3035 ifp->if_flags |= IFF_OACTIVE;
3039 m_new = ifq_dequeue(&ifp->if_snd);
3044 * If there's a BPF listener, bounce a copy of this frame
3047 BPF_MTAP(ifp, m_head);
3049 if (sc->dc_flags & DC_TX_ONE) {
3050 ifp->if_flags |= IFF_OACTIVE;
3056 sc->dc_cdata.dc_tx_prod = idx;
3057 if (!(sc->dc_flags & DC_TX_POLL))
3058 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF);
3061 * Set a timeout in case the chip goes out to lunch.
3068 static void dc_init(xsc)
3071 struct dc_softc *sc = xsc;
3072 struct ifnet *ifp = &sc->arpcom.ac_if;
3073 struct mii_data *mii;
3078 mii = device_get_softc(sc->dc_miibus);
3081 * Cancel pending I/O and free all RX/TX buffers.
3087 * Set cache alignment and burst length.
3089 if (DC_IS_ASIX(sc) || DC_IS_DAVICOM(sc))
3090 CSR_WRITE_4(sc, DC_BUSCTL, 0);
3092 CSR_WRITE_4(sc, DC_BUSCTL, DC_BUSCTL_MRME|DC_BUSCTL_MRLE);
3094 * Evenly share the bus between receive and transmit process.
3096 if (DC_IS_INTEL(sc))
3097 DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_ARBITRATION);
3098 if (DC_IS_DAVICOM(sc) || DC_IS_INTEL(sc)) {
3099 DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_USECA);
3101 DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_16LONG);
3103 if (sc->dc_flags & DC_TX_POLL)
3104 DC_SETBIT(sc, DC_BUSCTL, DC_TXPOLL_1);
3105 switch(sc->dc_cachesize) {
3107 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_32LONG);
3110 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_16LONG);
3113 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_8LONG);
3117 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_NONE);
3121 if (sc->dc_flags & DC_TX_STORENFWD)
3122 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD);
3124 if (sc->dc_txthresh > DC_TXTHRESH_MAX) {
3125 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD);
3127 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD);
3128 DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh);
3132 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_NO_RXCRC);
3133 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_BACKOFF);
3135 if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) {
3137 * The app notes for the 98713 and 98715A say that
3138 * in order to have the chips operate properly, a magic
3139 * number must be written to CSR16. Macronix does not
3140 * document the meaning of these bits so there's no way
3141 * to know exactly what they do. The 98713 has a magic
3142 * number all its own; the rest all use a different one.
3144 DC_CLRBIT(sc, DC_MX_MAGICPACKET, 0xFFFF0000);
3145 if (sc->dc_type == DC_TYPE_98713)
3146 DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98713);
3148 DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98715);
3151 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_THRESH);
3152 DC_SETBIT(sc, DC_NETCFG, DC_TXTHRESH_MIN);
3154 /* Init circular RX list. */
3155 if (dc_list_rx_init(sc) == ENOBUFS) {
3156 if_printf(ifp, "initialization failed: no "
3157 "memory for rx buffers\n");
3164 * Init tx descriptors.
3166 dc_list_tx_init(sc);
3169 * Load the address of the RX list.
3171 CSR_WRITE_4(sc, DC_RXADDR, vtophys(&sc->dc_ldata->dc_rx_list[0]));
3172 CSR_WRITE_4(sc, DC_TXADDR, vtophys(&sc->dc_ldata->dc_tx_list[0]));
3175 * Enable interrupts.
3177 #ifdef DEVICE_POLLING
3179 * ... but only if we are not polling, and make sure they are off in
3180 * the case of polling. Some cards (e.g. fxp) turn interrupts on
3183 if (ifp->if_flags & IFF_POLLING)
3184 CSR_WRITE_4(sc, DC_IMR, 0x00000000);
3187 CSR_WRITE_4(sc, DC_IMR, DC_INTRS);
3188 CSR_WRITE_4(sc, DC_ISR, 0xFFFFFFFF);
3190 /* Enable transmitter. */
3191 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON);
3194 * If this is an Intel 21143 and we're not using the
3195 * MII port, program the LED control pins so we get
3196 * link and activity indications.
3198 if (sc->dc_flags & DC_TULIP_LEDS) {
3199 CSR_WRITE_4(sc, DC_WATCHDOG,
3200 DC_WDOG_CTLWREN|DC_WDOG_LINK|DC_WDOG_ACTIVITY);
3201 CSR_WRITE_4(sc, DC_WATCHDOG, 0);
3205 * Load the RX/multicast filter. We do this sort of late
3206 * because the filter programming scheme on the 21143 and
3207 * some clones requires DMAing a setup frame via the TX
3208 * engine, and we need the transmitter enabled for that.
3212 /* Enable receiver. */
3213 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ON);
3214 CSR_WRITE_4(sc, DC_RXSTART, 0xFFFFFFFF);
3217 dc_setcfg(sc, sc->dc_if_media);
3219 ifp->if_flags |= IFF_RUNNING;
3220 ifp->if_flags &= ~IFF_OACTIVE;
3224 /* Don't start the ticker if this is a homePNA link. */
3225 if (IFM_SUBTYPE(mii->mii_media.ifm_media) == IFM_HPNA_1)
3228 if (sc->dc_flags & DC_21143_NWAY)
3229 callout_reset(&sc->dc_stat_timer, hz/10, dc_tick, sc);
3231 callout_reset(&sc->dc_stat_timer, hz, dc_tick, sc);
3238 * Set media options.
3240 static int dc_ifmedia_upd(ifp)
3243 struct dc_softc *sc;
3244 struct mii_data *mii;
3245 struct ifmedia *ifm;
3248 mii = device_get_softc(sc->dc_miibus);
3250 ifm = &mii->mii_media;
3252 if (DC_IS_DAVICOM(sc) &&
3253 IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1)
3254 dc_setcfg(sc, ifm->ifm_media);
3262 * Report current media status.
3264 static void dc_ifmedia_sts(ifp, ifmr)
3266 struct ifmediareq *ifmr;
3268 struct dc_softc *sc;
3269 struct mii_data *mii;
3270 struct ifmedia *ifm;
3273 mii = device_get_softc(sc->dc_miibus);
3275 ifm = &mii->mii_media;
3276 if (DC_IS_DAVICOM(sc)) {
3277 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) {
3278 ifmr->ifm_active = ifm->ifm_media;
3279 ifmr->ifm_status = 0;
3283 ifmr->ifm_active = mii->mii_media_active;
3284 ifmr->ifm_status = mii->mii_media_status;
3289 static int dc_ioctl(ifp, command, data, cr)
3295 struct dc_softc *sc = ifp->if_softc;
3296 struct ifreq *ifr = (struct ifreq *) data;
3297 struct mii_data *mii;
3304 if (ifp->if_flags & IFF_UP) {
3305 int need_setfilt = (ifp->if_flags ^ sc->dc_if_flags) &
3306 (IFF_PROMISC | IFF_ALLMULTI);
3307 if (ifp->if_flags & IFF_RUNNING) {
3311 sc->dc_txthresh = 0;
3315 if (ifp->if_flags & IFF_RUNNING)
3318 sc->dc_if_flags = ifp->if_flags;
3328 mii = device_get_softc(sc->dc_miibus);
3329 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
3332 error = ether_ioctl(ifp, command, data);
3341 static void dc_watchdog(ifp)
3344 struct dc_softc *sc;
3349 if_printf(ifp, "watchdog timeout\n");
3355 if (!ifq_is_empty(&ifp->if_snd))
3362 * Stop the adapter and free any mbufs allocated to the
3365 static void dc_stop(sc)
3366 struct dc_softc *sc;
3371 ifp = &sc->arpcom.ac_if;
3374 callout_stop(&sc->dc_stat_timer);
3376 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
3378 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_RX_ON|DC_NETCFG_TX_ON));
3379 CSR_WRITE_4(sc, DC_IMR, 0x00000000);
3380 CSR_WRITE_4(sc, DC_TXADDR, 0x00000000);
3381 CSR_WRITE_4(sc, DC_RXADDR, 0x00000000);
3385 * Free data in the RX lists.
3387 for (i = 0; i < DC_RX_LIST_CNT; i++) {
3388 if (sc->dc_cdata.dc_rx_chain[i] != NULL) {
3389 m_freem(sc->dc_cdata.dc_rx_chain[i]);
3390 sc->dc_cdata.dc_rx_chain[i] = NULL;
3393 bzero((char *)&sc->dc_ldata->dc_rx_list,
3394 sizeof(sc->dc_ldata->dc_rx_list));
3397 * Free the TX list buffers.
3399 for (i = 0; i < DC_TX_LIST_CNT; i++) {
3400 if (sc->dc_cdata.dc_tx_chain[i] != NULL) {
3401 if ((sc->dc_ldata->dc_tx_list[i].dc_ctl &
3403 !(sc->dc_ldata->dc_tx_list[i].dc_ctl &
3404 DC_TXCTL_LASTFRAG)) {
3405 sc->dc_cdata.dc_tx_chain[i] = NULL;
3408 m_freem(sc->dc_cdata.dc_tx_chain[i]);
3409 sc->dc_cdata.dc_tx_chain[i] = NULL;
3413 bzero((char *)&sc->dc_ldata->dc_tx_list,
3414 sizeof(sc->dc_ldata->dc_tx_list));
3420 * Stop all chip I/O so that the kernel's probe routines don't
3421 * get confused by errant DMAs when rebooting.
3423 static void dc_shutdown(dev)
3426 struct dc_softc *sc;
3428 sc = device_get_softc(dev);
3436 * Device suspend routine. Stop the interface and save some PCI
3437 * settings in case the BIOS doesn't restore them properly on
3440 static int dc_suspend(dev)
3445 struct dc_softc *sc;
3449 sc = device_get_softc(dev);
3453 for (i = 0; i < 5; i++)
3454 sc->saved_maps[i] = pci_read_config(dev, PCIR_MAPS + i * 4, 4);
3455 sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4);
3456 sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1);
3457 sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1);
3458 sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1);
3467 * Device resume routine. Restore some PCI settings in case the BIOS
3468 * doesn't, re-enable busmastering, and restart the interface if
3471 static int dc_resume(dev)
3476 struct dc_softc *sc;
3481 sc = device_get_softc(dev);
3482 ifp = &sc->arpcom.ac_if;
3486 /* better way to do this? */
3487 for (i = 0; i < 5; i++)
3488 pci_write_config(dev, PCIR_MAPS + i * 4, sc->saved_maps[i], 4);
3489 pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4);
3490 pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1);
3491 pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1);
3492 pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1);
3494 /* reenable busmastering */
3495 pci_enable_busmaster(dev);
3496 pci_enable_io(dev, DC_RES);
3498 /* reinitialize interface if necessary */
3499 if (ifp->if_flags & IFF_UP)