2 * Copyright (c) 1997, 1998
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
32 * $FreeBSD: src/sys/pci/if_rl.c,v 1.38.2.16 2003/03/05 18:42:33 njl Exp $
33 * $DragonFly: src/sys/dev/netif/rl/if_rl.c,v 1.22 2005/05/25 01:44:28 dillon Exp $
37 * RealTek 8129/8139 PCI NIC driver
39 * Supports several extremely cheap PCI 10/100 adapters based on
40 * the RealTek chipset. Datasheets can be obtained from
43 * Written by Bill Paul <wpaul@ctr.columbia.edu>
44 * Electrical Engineering Department
45 * Columbia University, New York City
49 * The RealTek 8139 PCI NIC redefines the meaning of 'low end.' This is
50 * probably the worst PCI ethernet controller ever made, with the possible
51 * exception of the FEAST chip made by SMC. The 8139 supports bus-master
52 * DMA, but it has a terrible interface that nullifies any performance
53 * gains that bus-master DMA usually offers.
55 * For transmission, the chip offers a series of four TX descriptor
56 * registers. Each transmit frame must be in a contiguous buffer, aligned
57 * on a longword (32-bit) boundary. This means we almost always have to
58 * do mbuf copies in order to transmit a frame, except in the unlikely
59 * case where a) the packet fits into a single mbuf, and b) the packet
60 * is 32-bit aligned within the mbuf's data area. The presence of only
61 * four descriptor registers means that we can never have more than four
62 * packets queued for transmission at any one time.
64 * Reception is not much better. The driver has to allocate a single large
65 * buffer area (up to 64K in size) into which the chip will DMA received
66 * frames. Because we don't know where within this region received packets
67 * will begin or end, we have no choice but to copy data from the buffer
68 * area into mbufs in order to pass the packets up to the higher protocol
71 * It's impossible given this rotten design to really achieve decent
72 * performance at 100Mbps, unless you happen to have a 400Mhz PII or
73 * some equally overmuscled CPU to drive it.
75 * On the bright side, the 8139 does have a built-in PHY, although
76 * rather than using an MDIO serial interface like most other NICs, the
77 * PHY registers are directly accessible through the 8139's register
78 * space. The 8139 supports autonegotiation, as well as a 64-bit multicast
81 * The 8129 chip is an older version of the 8139 that uses an external PHY
82 * chip. The 8129 has a serial MDIO interface for accessing the MII where
83 * the 8139 lets you directly access the on-board PHY registers. We need
84 * to select which interface to use depending on the chip type.
87 #include <sys/param.h>
88 #include <sys/endian.h>
89 #include <sys/systm.h>
90 #include <sys/sockio.h>
92 #include <sys/malloc.h>
93 #include <sys/kernel.h>
94 #include <sys/module.h>
95 #include <sys/socket.h>
98 #include <net/ifq_var.h>
99 #include <net/if_arp.h>
100 #include <net/ethernet.h>
101 #include <net/if_dl.h>
102 #include <net/if_media.h>
106 #include <machine/bus_pio.h>
107 #include <machine/bus_memio.h>
108 #include <machine/bus.h>
109 #include <machine/resource.h>
111 #include <sys/rman.h>
113 #include <dev/netif/mii_layer/mii.h>
114 #include <dev/netif/mii_layer/miivar.h>
116 #include <bus/pci/pcireg.h>
117 #include <bus/pci/pcivar.h>
119 /* "controller miibus0" required. See GENERIC if you get errors here. */
120 #include "miibus_if.h"
123 * Default to using PIO access for this driver. On SMP systems,
124 * there appear to be problems with memory mapped mode: it looks like
125 * doing too many memory mapped access back to back in rapid succession
126 * can hang the bus. I'm inclined to blame this on crummy design/construction
127 * on the part of RealTek. Memory mapped mode does appear to work on
128 * uniprocessor systems though.
130 #define RL_USEIOSPACE
132 #include <dev/netif/rl/if_rlreg.h>
135 * Various supported device vendors/types and their names.
137 static struct rl_type {
142 { RT_VENDORID, RT_DEVICEID_8129,
143 "RealTek 8129 10/100BaseTX" },
144 { RT_VENDORID, RT_DEVICEID_8139,
145 "RealTek 8139 10/100BaseTX" },
146 { RT_VENDORID, RT_DEVICEID_8138,
147 "RealTek 8139 10/100BaseTX CardBus" },
148 { ACCTON_VENDORID, ACCTON_DEVICEID_5030,
149 "Accton MPX 5030/5038 10/100BaseTX" },
150 { DELTA_VENDORID, DELTA_DEVICEID_8139,
151 "Delta Electronics 8139 10/100BaseTX" },
152 { ADDTRON_VENDORID, ADDTRON_DEVICEID_8139,
153 "Addtron Technolgy 8139 10/100BaseTX" },
154 { DLINK_VENDORID, DLINK_DEVICEID_530TXPLUS,
155 "D-Link DFE-530TX+ 10/100BaseTX" },
156 { DLINK_VENDORID, DLINK_DEVICEID_690TXD,
157 "D-Link DFE-690TX 10/100BaseTX" },
158 { NORTEL_VENDORID, ACCTON_DEVICEID_5030,
159 "Nortel Networks 10/100BaseTX" },
160 { PEPPERCON_VENDORID, PEPPERCON_DEVICEID_ROLF,
161 "Peppercon AG ROL/F" },
162 { COREGA_VENDORID, COREGA_DEVICEID_FETHERCBTXD,
163 "Corega FEther CB-TXD" },
164 { COREGA_VENDORID, COREGA_DEVICEID_FETHERIICBTXD,
165 "Corega FEtherII CB-TXD" },
166 { PLANEX_VENDORID, PLANEX_DEVICEID_FNW3800TX,
167 "Planex FNW-3800-TX" },
171 static int rl_probe(device_t);
172 static int rl_attach(device_t);
173 static int rl_detach(device_t);
175 static int rl_encap(struct rl_softc *, struct mbuf * );
177 static void rl_rxeof(struct rl_softc *);
178 static void rl_txeof(struct rl_softc *);
179 static void rl_intr(void *);
180 static void rl_tick(void *);
181 static void rl_start(struct ifnet *);
182 static int rl_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
183 static void rl_init(void *);
184 static void rl_stop (struct rl_softc *);
185 static void rl_watchdog(struct ifnet *);
186 static int rl_suspend(device_t);
187 static int rl_resume(device_t);
188 static void rl_shutdown(device_t);
189 static int rl_ifmedia_upd(struct ifnet *);
190 static void rl_ifmedia_sts(struct ifnet *, struct ifmediareq *);
192 static void rl_eeprom_putbyte(struct rl_softc *, int);
193 static void rl_eeprom_getword(struct rl_softc *, int, uint16_t *);
194 static void rl_read_eeprom(struct rl_softc *, caddr_t, int, int, int);
195 static void rl_mii_sync(struct rl_softc *);
196 static void rl_mii_send(struct rl_softc *, uint32_t, int);
197 static int rl_mii_readreg(struct rl_softc *, struct rl_mii_frame *);
198 static int rl_mii_writereg(struct rl_softc *, struct rl_mii_frame *);
200 static int rl_miibus_readreg(device_t, int, int);
201 static int rl_miibus_writereg(device_t, int, int, int);
202 static void rl_miibus_statchg(device_t);
204 static void rl_setmulti(struct rl_softc *);
205 static void rl_reset(struct rl_softc *);
206 static void rl_list_tx_init(struct rl_softc *);
208 static void rl_dma_map_rxbuf(void *, bus_dma_segment_t *, int, int);
209 static void rl_dma_map_txbuf(void *, bus_dma_segment_t *, int, int);
210 #ifdef DEVICE_POLLING
211 static poll_handler_t rl_poll;
215 #define RL_RES SYS_RES_IOPORT
216 #define RL_RID RL_PCI_LOIO
218 #define RL_RES SYS_RES_MEMORY
219 #define RL_RID RL_PCI_LOMEM
222 static device_method_t rl_methods[] = {
223 /* Device interface */
224 DEVMETHOD(device_probe, rl_probe),
225 DEVMETHOD(device_attach, rl_attach),
226 DEVMETHOD(device_detach, rl_detach),
227 DEVMETHOD(device_suspend, rl_suspend),
228 DEVMETHOD(device_resume, rl_resume),
229 DEVMETHOD(device_shutdown, rl_shutdown),
232 DEVMETHOD(bus_print_child, bus_generic_print_child),
233 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
236 DEVMETHOD(miibus_readreg, rl_miibus_readreg),
237 DEVMETHOD(miibus_writereg, rl_miibus_writereg),
238 DEVMETHOD(miibus_statchg, rl_miibus_statchg),
243 static DEFINE_CLASS_0(rl, rl_driver, rl_methods, sizeof(struct rl_softc));
244 static devclass_t rl_devclass;
246 DECLARE_DUMMY_MODULE(if_rl);
247 DRIVER_MODULE(if_rl, pci, rl_driver, rl_devclass, 0, 0);
248 DRIVER_MODULE(if_rl, cardbus, rl_driver, rl_devclass, 0, 0);
249 DRIVER_MODULE(miibus, rl, miibus_driver, miibus_devclass, 0, 0);
250 MODULE_DEPEND(if_rl, miibus, 1, 1, 1);
253 CSR_WRITE_1(sc, RL_EECMD, CSR_READ_1(sc, RL_EECMD) | (x))
256 CSR_WRITE_1(sc, RL_EECMD, CSR_READ_1(sc, RL_EECMD) & ~(x))
259 rl_dma_map_rxbuf(void *arg, bus_dma_segment_t *segs, int nseg, int error)
261 struct rl_softc *sc = arg;
263 CSR_WRITE_4(sc, RL_RXADDR, segs->ds_addr & 0xFFFFFFFF);
267 rl_dma_map_txbuf(void *arg, bus_dma_segment_t *segs, int nseg, int error)
269 struct rl_softc *sc = arg;
271 CSR_WRITE_4(sc, RL_CUR_TXADDR(sc), segs->ds_addr & 0xFFFFFFFF);
275 * Send a read command and address to the EEPROM, check for ACK.
278 rl_eeprom_putbyte(struct rl_softc *sc, int addr)
282 d = addr | sc->rl_eecmd_read;
285 * Feed in each bit and strobe the clock.
287 for (i = 0x400; i; i >>= 1) {
289 EE_SET(RL_EE_DATAIN);
291 EE_CLR(RL_EE_DATAIN);
301 * Read a word of data stored in the EEPROM at address 'addr.'
304 rl_eeprom_getword(struct rl_softc *sc, int addr, uint16_t *dest)
309 /* Enter EEPROM access mode. */
310 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL);
313 * Send address of word we want to read.
315 rl_eeprom_putbyte(sc, addr);
317 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL);
320 * Start reading bits from EEPROM.
322 for (i = 0x8000; i; i >>= 1) {
325 if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT)
331 /* Turn off EEPROM access mode. */
332 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
338 * Read a sequence of words from the EEPROM.
341 rl_read_eeprom(struct rl_softc *sc, caddr_t dest, int off, int cnt, int swap)
344 u_int16_t word = 0, *ptr;
346 for (i = 0; i < cnt; i++) {
347 rl_eeprom_getword(sc, off + i, &word);
348 ptr = (u_int16_t *)(dest + (i * 2));
358 * MII access routines are provided for the 8129, which
359 * doesn't have a built-in PHY. For the 8139, we fake things
360 * up by diverting rl_phy_readreg()/rl_phy_writereg() to the
361 * direct access PHY registers.
364 CSR_WRITE_1(sc, RL_MII, CSR_READ_1(sc, RL_MII) | x)
367 CSR_WRITE_1(sc, RL_MII, CSR_READ_1(sc, RL_MII) & ~x)
370 * Sync the PHYs by setting data bit and strobing the clock 32 times.
373 rl_mii_sync(struct rl_softc *sc)
377 MII_SET(RL_MII_DIR|RL_MII_DATAOUT);
379 for (i = 0; i < 32; i++) {
388 * Clock a series of bits through the MII.
391 rl_mii_send(struct rl_softc *sc, uint32_t bits, int cnt)
397 for (i = (0x1 << (cnt - 1)); i; i >>= 1) {
399 MII_SET(RL_MII_DATAOUT);
401 MII_CLR(RL_MII_DATAOUT);
410 * Read an PHY register through the MII.
413 rl_mii_readreg(struct rl_softc *sc, struct rl_mii_frame *frame)
420 * Set up frame for RX.
422 frame->mii_stdelim = RL_MII_STARTDELIM;
423 frame->mii_opcode = RL_MII_READOP;
424 frame->mii_turnaround = 0;
427 CSR_WRITE_2(sc, RL_MII, 0);
437 * Send command/address info.
439 rl_mii_send(sc, frame->mii_stdelim, 2);
440 rl_mii_send(sc, frame->mii_opcode, 2);
441 rl_mii_send(sc, frame->mii_phyaddr, 5);
442 rl_mii_send(sc, frame->mii_regaddr, 5);
445 MII_CLR((RL_MII_CLK|RL_MII_DATAOUT));
456 ack = CSR_READ_2(sc, RL_MII) & RL_MII_DATAIN;
461 * Now try reading data bits. If the ack failed, we still
462 * need to clock through 16 cycles to keep the PHY(s) in sync.
465 for(i = 0; i < 16; i++) {
472 for (i = 0x8000; i; i >>= 1) {
476 if (CSR_READ_2(sc, RL_MII) & RL_MII_DATAIN)
477 frame->mii_data |= i;
496 * Write to a PHY register through the MII.
499 rl_mii_writereg(struct rl_softc *sc, struct rl_mii_frame *frame)
505 * Set up frame for TX.
508 frame->mii_stdelim = RL_MII_STARTDELIM;
509 frame->mii_opcode = RL_MII_WRITEOP;
510 frame->mii_turnaround = RL_MII_TURNAROUND;
513 * Turn on data output.
519 rl_mii_send(sc, frame->mii_stdelim, 2);
520 rl_mii_send(sc, frame->mii_opcode, 2);
521 rl_mii_send(sc, frame->mii_phyaddr, 5);
522 rl_mii_send(sc, frame->mii_regaddr, 5);
523 rl_mii_send(sc, frame->mii_turnaround, 2);
524 rl_mii_send(sc, frame->mii_data, 16);
543 rl_miibus_readreg(device_t dev, int phy, int reg)
546 struct rl_mii_frame frame;
548 uint16_t rl8139_reg = 0;
550 sc = device_get_softc(dev);
552 if (sc->rl_type == RL_8139) {
553 /* Pretend the internal PHY is only at address 0 */
558 rl8139_reg = RL_BMCR;
561 rl8139_reg = RL_BMSR;
564 rl8139_reg = RL_ANAR;
567 rl8139_reg = RL_ANER;
570 rl8139_reg = RL_LPAR;
577 * Allow the rlphy driver to read the media status
578 * register. If we have a link partner which does not
579 * support NWAY, this is the register which will tell
580 * us the results of parallel detection.
583 rval = CSR_READ_1(sc, RL_MEDIASTAT);
586 device_printf(dev, "bad phy register\n");
589 rval = CSR_READ_2(sc, rl8139_reg);
593 bzero(&frame, sizeof(frame));
595 frame.mii_phyaddr = phy;
596 frame.mii_regaddr = reg;
597 rl_mii_readreg(sc, &frame);
599 return(frame.mii_data);
603 rl_miibus_writereg(device_t dev, int phy, int reg, int data)
606 struct rl_mii_frame frame;
607 u_int16_t rl8139_reg = 0;
609 sc = device_get_softc(dev);
611 if (sc->rl_type == RL_8139) {
612 /* Pretend the internal PHY is only at address 0 */
617 rl8139_reg = RL_BMCR;
620 rl8139_reg = RL_BMSR;
623 rl8139_reg = RL_ANAR;
626 rl8139_reg = RL_ANER;
629 rl8139_reg = RL_LPAR;
635 device_printf(dev, "bad phy register\n");
638 CSR_WRITE_2(sc, rl8139_reg, data);
642 bzero(&frame, sizeof(frame));
644 frame.mii_phyaddr = phy;
645 frame.mii_regaddr = reg;
646 frame.mii_data = data;
648 rl_mii_writereg(sc, &frame);
654 rl_miibus_statchg(device_t dev)
659 * Program the 64-bit multicast hash filter.
662 rl_setmulti(struct rl_softc *sc)
666 uint32_t hashes[2] = { 0, 0 };
667 struct ifmultiaddr *ifma;
671 ifp = &sc->arpcom.ac_if;
673 rxfilt = CSR_READ_4(sc, RL_RXCFG);
675 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
676 rxfilt |= RL_RXCFG_RX_MULTI;
677 CSR_WRITE_4(sc, RL_RXCFG, rxfilt);
678 CSR_WRITE_4(sc, RL_MAR0, 0xFFFFFFFF);
679 CSR_WRITE_4(sc, RL_MAR4, 0xFFFFFFFF);
683 /* first, zot all the existing hash bits */
684 CSR_WRITE_4(sc, RL_MAR0, 0);
685 CSR_WRITE_4(sc, RL_MAR4, 0);
687 /* now program new ones */
688 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
689 if (ifma->ifma_addr->sa_family != AF_LINK)
692 LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
693 ETHER_ADDR_LEN >> 26);
695 hashes[0] |= (1 << h);
697 hashes[1] |= (1 << (h - 32));
702 rxfilt |= RL_RXCFG_RX_MULTI;
704 rxfilt &= ~RL_RXCFG_RX_MULTI;
706 CSR_WRITE_4(sc, RL_RXCFG, rxfilt);
707 CSR_WRITE_4(sc, RL_MAR0, hashes[0]);
708 CSR_WRITE_4(sc, RL_MAR4, hashes[1]);
712 rl_reset(struct rl_softc *sc)
716 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET);
718 for (i = 0; i < RL_TIMEOUT; i++) {
720 if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET))
724 device_printf(sc->rl_dev, "reset never completed!\n");
728 * Probe for a RealTek 8129/8139 chip. Check the PCI vendor and device
729 * IDs against our list and return a device name if we find a match.
731 * Return with a value < 0 to give re(4) a change to attach.
734 rl_probe(device_t dev)
737 uint16_t product = pci_get_device(dev);
738 uint16_t vendor = pci_get_vendor(dev);
740 for (t = rl_devs; t->rl_name != NULL; t++) {
741 if (vendor == t->rl_vid && product == t->rl_did) {
742 device_set_desc(dev, t->rl_name);
751 * Attach the interface. Allocate softc structures, do ifmedia
752 * setup and ethernet/BPF attach.
755 rl_attach(device_t dev)
757 uint8_t eaddr[ETHER_ADDR_LEN];
762 int error = 0, rid, i;
764 sc = device_get_softc(dev);
768 * Handle power management nonsense.
771 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
772 uint32_t iobase, membase, irq;
774 /* Save important PCI config data. */
775 iobase = pci_read_config(dev, RL_PCI_LOIO, 4);
776 membase = pci_read_config(dev, RL_PCI_LOMEM, 4);
777 irq = pci_read_config(dev, RL_PCI_INTLINE, 4);
779 /* Reset the power state. */
780 device_printf(dev, "chip is is in D%d power mode "
781 "-- setting to D0\n", pci_get_powerstate(dev));
782 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
784 /* Restore PCI config data. */
785 pci_write_config(dev, RL_PCI_LOIO, iobase, 4);
786 pci_write_config(dev, RL_PCI_LOMEM, membase, 4);
787 pci_write_config(dev, RL_PCI_INTLINE, irq, 4);
791 * Map control/status registers.
793 pci_enable_busmaster(dev);
794 pci_enable_io(dev, RL_RES);
797 sc->rl_res = bus_alloc_resource_any(dev, RL_RES, &rid, RF_ACTIVE);
799 if (sc->rl_res == NULL) {
800 device_printf(dev, "couldn't map ports/memory\n");
805 sc->rl_btag = rman_get_bustag(sc->rl_res);
806 sc->rl_bhandle = rman_get_bushandle(sc->rl_res);
809 sc->rl_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
810 RF_SHAREABLE | RF_ACTIVE);
812 if (sc->rl_irq == NULL) {
813 device_printf(dev, "couldn't map interrupt\n");
818 callout_init(&sc->rl_stat_timer);
820 /* Reset the adapter. */
823 sc->rl_eecmd_read = RL_EECMD_READ_6BIT;
824 rl_read_eeprom(sc, (uint8_t *)&rl_did, 0, 1, 0);
825 if (rl_did != 0x8129)
826 sc->rl_eecmd_read = RL_EECMD_READ_8BIT;
829 * Get station address from the EEPROM.
831 rl_read_eeprom(sc, (caddr_t)as, RL_EE_EADDR, 3, 0);
832 for (i = 0; i < 3; i++) {
833 eaddr[(i * 2) + 0] = as[i] & 0xff;
834 eaddr[(i * 2) + 1] = as[i] >> 8;
838 * Now read the exact device type from the EEPROM to find
839 * out if it's an 8129 or 8139.
841 rl_read_eeprom(sc, (caddr_t)&rl_did, RL_EE_PCI_DID, 1, 0);
843 if (rl_did == RT_DEVICEID_8139 || rl_did == ACCTON_DEVICEID_5030 ||
844 rl_did == DELTA_DEVICEID_8139 || rl_did == ADDTRON_DEVICEID_8139 ||
845 rl_did == DLINK_DEVICEID_530TXPLUS || rl_did == RT_DEVICEID_8138 ||
846 rl_did == DLINK_DEVICEID_690TXD ||
847 rl_did == COREGA_DEVICEID_FETHERCBTXD ||
848 rl_did == COREGA_DEVICEID_FETHERIICBTXD ||
849 rl_did == PLANEX_DEVICEID_FNW3800TX)
850 sc->rl_type = RL_8139;
851 else if (rl_did == RT_DEVICEID_8129)
852 sc->rl_type = RL_8129;
854 device_printf(dev, "unknown device ID: %x\n", rl_did);
859 #define RL_NSEG_NEW 32
860 error = bus_dma_tag_create(NULL, /* parent */
861 1, 0, /* alignment, boundary */
862 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
863 BUS_SPACE_MAXADDR, /* highaddr */
864 NULL, NULL, /* filter, filterarg */
865 MAXBSIZE, RL_NSEG_NEW, /* maxsize, nsegments */
866 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */
867 BUS_DMA_ALLOCNOW, /* flags */
871 device_printf(dev, "can't create parent tag\n");
876 * Now allocate a tag for the DMA descriptor lists.
877 * All of our lists are allocated as a contiguous block
880 error = bus_dma_tag_create(sc->rl_parent_tag, /* parent */
881 1, 0, /* alignment, boundary */
882 BUS_SPACE_MAXADDR, /* lowaddr */
883 BUS_SPACE_MAXADDR, /* highaddr */
884 NULL, NULL, /* filter, filterarg */
885 RL_RXBUFLEN + 1518, 1, /* maxsize, nsegments */
886 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */
891 device_printf(dev, "can't create RX tag\n");
896 * Now allocate a chunk of DMA-able memory based on the tag
899 error = bus_dmamem_alloc(sc->rl_tag, (void **)&sc->rl_cdata.rl_rx_buf,
900 BUS_DMA_WAITOK, &sc->rl_cdata.rl_rx_dmamap);
903 device_printf(dev, "can't allocate RX memory!\n");
908 /* Leave a few bytes before the start of the RX ring buffer. */
909 sc->rl_cdata.rl_rx_buf_ptr = sc->rl_cdata.rl_rx_buf;
910 sc->rl_cdata.rl_rx_buf += sizeof(u_int64_t);
913 if (mii_phy_probe(dev, &sc->rl_miibus, rl_ifmedia_upd,
915 device_printf(dev, "MII without any phy!\n");
920 ifp = &sc->arpcom.ac_if;
922 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
923 ifp->if_mtu = ETHERMTU;
924 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
925 ifp->if_ioctl = rl_ioctl;
926 ifp->if_start = rl_start;
927 ifp->if_watchdog = rl_watchdog;
928 ifp->if_init = rl_init;
929 ifp->if_baudrate = 10000000;
930 ifp->if_capabilities = IFCAP_VLAN_MTU;
931 #ifdef DEVICE_POLLING
932 ifp->if_poll = rl_poll;
934 ifq_set_maxlen(&ifp->if_snd, IFQ_MAXLEN);
935 ifq_set_ready(&ifp->if_snd);
938 * Call MI attach routine.
940 ether_ifattach(ifp, eaddr);
942 error = bus_setup_intr(dev, sc->rl_irq, INTR_TYPE_NET, rl_intr,
943 sc, &sc->rl_intrhand, NULL);
946 device_printf(dev, "couldn't set up irq\n");
959 rl_detach(device_t dev)
965 sc = device_get_softc(dev);
966 ifp = &sc->arpcom.ac_if;
970 if (device_is_attached(dev)) {
976 device_delete_child(dev, sc->rl_miibus);
977 bus_generic_detach(dev);
980 bus_teardown_intr(dev, sc->rl_irq, sc->rl_intrhand);
984 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq);
986 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res);
988 if (sc->rl_cdata.rl_rx_buf) {
989 bus_dmamap_unload(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap);
990 bus_dmamem_free(sc->rl_tag, sc->rl_cdata.rl_rx_buf,
991 sc->rl_cdata.rl_rx_dmamap);
994 bus_dma_tag_destroy(sc->rl_tag);
995 if (sc->rl_parent_tag)
996 bus_dma_tag_destroy(sc->rl_parent_tag);
1002 * Initialize the transmit descriptors.
1005 rl_list_tx_init(struct rl_softc *sc)
1007 struct rl_chain_data *cd;
1011 for (i = 0; i < RL_TX_LIST_CNT; i++) {
1012 cd->rl_tx_chain[i] = NULL;
1014 RL_TXADDR0 + (i * sizeof(uint32_t)), 0x0000000);
1017 sc->rl_cdata.cur_tx = 0;
1018 sc->rl_cdata.last_tx = 0;
1022 * A frame has been uploaded: pass the resulting mbuf chain up to
1023 * the higher level protocols.
1025 * You know there's something wrong with a PCI bus-master chip design
1026 * when you have to use m_devget().
1028 * The receive operation is badly documented in the datasheet, so I'll
1029 * attempt to document it here. The driver provides a buffer area and
1030 * places its base address in the RX buffer start address register.
1031 * The chip then begins copying frames into the RX buffer. Each frame
1032 * is preceded by a 32-bit RX status word which specifies the length
1033 * of the frame and certain other status bits. Each frame (starting with
1034 * the status word) is also 32-bit aligned. The frame length is in the
1035 * first 16 bits of the status word; the lower 15 bits correspond with
1036 * the 'rx status register' mentioned in the datasheet.
1038 * Note: to make the Alpha happy, the frame payload needs to be aligned
1039 * on a 32-bit boundary. To achieve this, we cheat a bit by copying from
1040 * the ring buffer starting at an address two bytes before the actual
1041 * data location. We can then shave off the first two bytes using m_adj().
1042 * The reason we do this is because m_devget() doesn't let us specify an
1043 * offset into the mbuf storage space, so we have to artificially create
1044 * one. The ring is allocated in such a way that there are a few unused
1045 * bytes of space preceecing it so that it will be safe for us to do the
1046 * 2-byte backstep even if reading from the ring at offset 0.
1049 rl_rxeof(struct rl_softc *sc)
1057 uint16_t cur_rx, limit, max_bytes, rx_bytes = 0;
1059 ifp = &sc->arpcom.ac_if;
1061 bus_dmamap_sync(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap,
1062 BUS_DMASYNC_POSTREAD);
1064 cur_rx = (CSR_READ_2(sc, RL_CURRXADDR) + 16) % RL_RXBUFLEN;
1066 /* Do not try to read past this point. */
1067 limit = CSR_READ_2(sc, RL_CURRXBUF) % RL_RXBUFLEN;
1070 max_bytes = (RL_RXBUFLEN - cur_rx) + limit;
1072 max_bytes = limit - cur_rx;
1074 while((CSR_READ_1(sc, RL_COMMAND) & RL_CMD_EMPTY_RXBUF) == 0) {
1075 #ifdef DEVICE_POLLING
1076 if (ifp->if_flags & IFF_POLLING) {
1077 if (sc->rxcycles <= 0)
1081 #endif /* DEVICE_POLLING */
1082 rxbufpos = sc->rl_cdata.rl_rx_buf + cur_rx;
1083 rxstat = le32toh(*(uint32_t *)rxbufpos);
1086 * Here's a totally undocumented fact for you. When the
1087 * RealTek chip is in the process of copying a packet into
1088 * RAM for you, the length will be 0xfff0. If you spot a
1089 * packet header with this value, you need to stop. The
1090 * datasheet makes absolutely no mention of this and
1091 * RealTek should be shot for this.
1093 if ((uint16_t)(rxstat >> 16) == RL_RXSTAT_UNFINISHED)
1096 if ((rxstat & RL_RXSTAT_RXOK) == 0) {
1102 /* No errors; receive the packet. */
1103 total_len = rxstat >> 16;
1104 rx_bytes += total_len + 4;
1107 * XXX The RealTek chip includes the CRC with every
1108 * received frame, and there's no way to turn this
1109 * behavior off (at least, I can't find anything in
1110 * the manual that explains how to do it) so we have
1111 * to trim off the CRC manually.
1113 total_len -= ETHER_CRC_LEN;
1116 * Avoid trying to read more bytes than we know
1117 * the chip has prepared for us.
1119 if (rx_bytes > max_bytes)
1122 rxbufpos = sc->rl_cdata.rl_rx_buf +
1123 ((cur_rx + sizeof(uint32_t)) % RL_RXBUFLEN);
1125 if (rxbufpos == (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN))
1126 rxbufpos = sc->rl_cdata.rl_rx_buf;
1128 wrap = (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN) - rxbufpos;
1130 if (total_len > wrap) {
1132 * Fool m_devget() into thinking we want to copy
1133 * the whole buffer so we don't end up fragmenting
1136 m = m_devget(rxbufpos - RL_ETHER_ALIGN,
1137 total_len + RL_ETHER_ALIGN, 0, ifp, NULL);
1141 m_adj(m, RL_ETHER_ALIGN);
1142 m_copyback(m, wrap, total_len - wrap,
1143 sc->rl_cdata.rl_rx_buf);
1145 cur_rx = (total_len - wrap + ETHER_CRC_LEN);
1147 m = m_devget(rxbufpos - RL_ETHER_ALIGN,
1148 total_len + RL_ETHER_ALIGN, 0, ifp, NULL);
1152 m_adj(m, RL_ETHER_ALIGN);
1153 cur_rx += total_len + 4 + ETHER_CRC_LEN;
1157 * Round up to 32-bit boundary.
1159 cur_rx = (cur_rx + 3) & ~3;
1160 CSR_WRITE_2(sc, RL_CURRXADDR, cur_rx - 16);
1167 (*ifp->if_input)(ifp, m);
1172 * A frame was downloaded to the chip. It's safe for us to clean up
1176 rl_txeof(struct rl_softc *sc)
1181 ifp = &sc->arpcom.ac_if;
1184 * Go through our tx list and free mbufs for those
1185 * frames that have been uploaded.
1188 if (RL_LAST_TXMBUF(sc) == NULL)
1190 txstat = CSR_READ_4(sc, RL_LAST_TXSTAT(sc));
1191 if ((txstat & (RL_TXSTAT_TX_OK | RL_TXSTAT_TX_UNDERRUN |
1192 RL_TXSTAT_TXABRT)) == 0)
1195 ifp->if_collisions += (txstat & RL_TXSTAT_COLLCNT) >> 24;
1197 bus_dmamap_unload(sc->rl_tag, RL_LAST_DMAMAP(sc));
1198 bus_dmamap_destroy(sc->rl_tag, RL_LAST_DMAMAP(sc));
1199 m_freem(RL_LAST_TXMBUF(sc));
1200 RL_LAST_TXMBUF(sc) = NULL;
1201 RL_INC(sc->rl_cdata.last_tx);
1203 if (txstat & RL_TXSTAT_TX_UNDERRUN) {
1204 sc->rl_txthresh += 32;
1205 if (sc->rl_txthresh > RL_TX_THRESH_MAX)
1206 sc->rl_txthresh = RL_TX_THRESH_MAX;
1209 if (txstat & RL_TXSTAT_TX_OK) {
1213 if (txstat & (RL_TXSTAT_TXABRT | RL_TXSTAT_OUTOFWIN))
1214 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG);
1216 ifp->if_flags &= ~IFF_OACTIVE;
1217 } while (sc->rl_cdata.last_tx != sc->rl_cdata.cur_tx);
1219 if (RL_LAST_TXMBUF(sc) == NULL)
1221 else if (ifp->if_timer == 0)
1228 struct rl_softc *sc = xsc;
1229 struct mii_data *mii;
1234 mii = device_get_softc(sc->rl_miibus);
1239 callout_reset(&sc->rl_stat_timer, hz, rl_tick, sc);
1242 #ifdef DEVICE_POLLING
1245 rl_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
1247 struct rl_softc *sc = ifp->if_softc;
1251 /* disable interrupts */
1252 CSR_WRITE_2(sc, RL_IMR, 0x0000);
1254 case POLL_DEREGISTER:
1255 /* enable interrupts */
1256 CSR_WRITE_2(sc, RL_IMR, RL_INTRS);
1259 sc->rxcycles = count;
1262 if (!ifq_is_empty(&ifp->if_snd))
1265 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */
1268 status = CSR_READ_2(sc, RL_ISR);
1269 if (status == 0xffff)
1272 CSR_WRITE_2(sc, RL_ISR, status);
1275 * XXX check behaviour on receiver stalls.
1278 if (status & RL_ISR_SYSTEM_ERR) {
1286 #endif /* DEVICE_POLLING */
1291 struct rl_softc *sc;
1300 ifp = &sc->arpcom.ac_if;
1303 status = CSR_READ_2(sc, RL_ISR);
1304 /* If the card has gone away, the read returns 0xffff. */
1305 if (status == 0xffff)
1309 CSR_WRITE_2(sc, RL_ISR, status);
1311 if ((status & RL_INTRS) == 0)
1314 if (status & RL_ISR_RX_OK)
1317 if (status & RL_ISR_RX_ERR)
1320 if ((status & RL_ISR_TX_OK) || (status & RL_ISR_TX_ERR))
1323 if (status & RL_ISR_SYSTEM_ERR) {
1330 if (!ifq_is_empty(&ifp->if_snd))
1335 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
1336 * pointers to the fragment pointers.
1339 rl_encap(struct rl_softc *sc, struct mbuf *m_head)
1341 struct mbuf *m_new = NULL;
1344 * The RealTek is brain damaged and wants longword-aligned
1345 * TX buffers, plus we can only have one fragment buffer
1346 * per packet. We have to copy pretty much all the time.
1348 m_new = m_defrag(m_head, MB_DONTWAIT);
1350 if (m_new == NULL) {
1356 /* Pad frames to at least 60 bytes. */
1357 if (m_head->m_pkthdr.len < RL_MIN_FRAMELEN) {
1359 * Make security concious people happy: zero out the
1360 * bytes in the pad area, since we don't know what
1361 * this mbuf cluster buffer's previous user might
1364 bzero(mtod(m_head, char *) + m_head->m_pkthdr.len,
1365 RL_MIN_FRAMELEN - m_head->m_pkthdr.len);
1366 m_head->m_pkthdr.len +=
1367 (RL_MIN_FRAMELEN - m_head->m_pkthdr.len);
1368 m_head->m_len = m_head->m_pkthdr.len;
1371 RL_CUR_TXMBUF(sc) = m_head;
1377 * Main transmit routine.
1381 rl_start(struct ifnet *ifp)
1383 struct rl_softc *sc;
1384 struct mbuf *m_head = NULL;
1388 while(RL_CUR_TXMBUF(sc) == NULL) {
1389 m_head = ifq_dequeue(&ifp->if_snd);
1393 if (rl_encap(sc, m_head))
1397 * If there's a BPF listener, bounce a copy of this frame
1400 BPF_MTAP(ifp, RL_CUR_TXMBUF(sc));
1403 * Transmit the frame.
1405 bus_dmamap_create(sc->rl_tag, 0, &RL_CUR_DMAMAP(sc));
1406 bus_dmamap_load(sc->rl_tag, RL_CUR_DMAMAP(sc),
1407 mtod(RL_CUR_TXMBUF(sc), void *),
1408 RL_CUR_TXMBUF(sc)->m_pkthdr.len,
1409 rl_dma_map_txbuf, sc, 0);
1410 bus_dmamap_sync(sc->rl_tag, RL_CUR_DMAMAP(sc),
1411 BUS_DMASYNC_PREREAD);
1412 CSR_WRITE_4(sc, RL_CUR_TXSTAT(sc),
1413 RL_TXTHRESH(sc->rl_txthresh) |
1414 RL_CUR_TXMBUF(sc)->m_pkthdr.len);
1416 RL_INC(sc->rl_cdata.cur_tx);
1419 * Set a timeout in case the chip goes out to lunch.
1425 * We broke out of the loop because all our TX slots are
1426 * full. Mark the NIC as busy until it drains some of the
1427 * packets from the queue.
1429 if (RL_CUR_TXMBUF(sc) != NULL)
1430 ifp->if_flags |= IFF_OACTIVE;
1436 struct rl_softc *sc = xsc;
1437 struct ifnet *ifp = &sc->arpcom.ac_if;
1438 struct mii_data *mii;
1444 mii = device_get_softc(sc->rl_miibus);
1447 * Cancel pending I/O and free all RX/TX buffers.
1452 * Init our MAC address. Even though the chipset documentation
1453 * doesn't mention it, we need to enter "Config register write enable"
1454 * mode to modify the ID registers.
1456 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG);
1457 CSR_WRITE_STREAM_4(sc, RL_IDR0,
1458 *(uint32_t *)(&sc->arpcom.ac_enaddr[0]));
1459 CSR_WRITE_STREAM_4(sc, RL_IDR4,
1460 *(uint32_t *)(&sc->arpcom.ac_enaddr[4]));
1461 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
1463 /* Init the RX buffer pointer register. */
1464 bus_dmamap_load(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap,
1465 sc->rl_cdata.rl_rx_buf, RL_RXBUFLEN, rl_dma_map_rxbuf,
1467 bus_dmamap_sync(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap,
1468 BUS_DMASYNC_PREWRITE);
1470 /* Init TX descriptors. */
1471 rl_list_tx_init(sc);
1474 * Enable transmit and receive.
1476 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB);
1479 * Set the initial TX and RX configuration.
1481 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG);
1482 CSR_WRITE_4(sc, RL_RXCFG, RL_RXCFG_CONFIG);
1484 /* Set the individual bit to receive frames for this host only. */
1485 rxcfg = CSR_READ_4(sc, RL_RXCFG);
1486 rxcfg |= RL_RXCFG_RX_INDIV;
1488 /* If we want promiscuous mode, set the allframes bit. */
1489 if (ifp->if_flags & IFF_PROMISC) {
1490 rxcfg |= RL_RXCFG_RX_ALLPHYS;
1491 CSR_WRITE_4(sc, RL_RXCFG, rxcfg);
1493 rxcfg &= ~RL_RXCFG_RX_ALLPHYS;
1494 CSR_WRITE_4(sc, RL_RXCFG, rxcfg);
1498 * Set capture broadcast bit to capture broadcast frames.
1500 if (ifp->if_flags & IFF_BROADCAST) {
1501 rxcfg |= RL_RXCFG_RX_BROAD;
1502 CSR_WRITE_4(sc, RL_RXCFG, rxcfg);
1504 rxcfg &= ~RL_RXCFG_RX_BROAD;
1505 CSR_WRITE_4(sc, RL_RXCFG, rxcfg);
1509 * Program the multicast filter, if necessary.
1513 #ifdef DEVICE_POLLING
1515 * Only enable interrupts if we are polling, keep them off otherwise.
1517 if (ifp->if_flags & IFF_POLLING)
1518 CSR_WRITE_2(sc, RL_IMR, 0);
1520 #endif /* DEVICE_POLLING */
1522 * Enable interrupts.
1524 CSR_WRITE_2(sc, RL_IMR, RL_INTRS);
1526 /* Set initial TX threshold */
1527 sc->rl_txthresh = RL_TX_THRESH_INIT;
1529 /* Start RX/TX process. */
1530 CSR_WRITE_4(sc, RL_MISSEDPKT, 0);
1532 /* Enable receiver and transmitter. */
1533 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB);
1537 CSR_WRITE_1(sc, RL_CFG1, RL_CFG1_DRVLOAD|RL_CFG1_FULLDUPLEX);
1539 ifp->if_flags |= IFF_RUNNING;
1540 ifp->if_flags &= ~IFF_OACTIVE;
1544 callout_reset(&sc->rl_stat_timer, hz, rl_tick, sc);
1548 * Set media options.
1551 rl_ifmedia_upd(struct ifnet *ifp)
1553 struct rl_softc *sc;
1554 struct mii_data *mii;
1557 mii = device_get_softc(sc->rl_miibus);
1564 * Report current media status.
1567 rl_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
1569 struct rl_softc *sc = ifp->if_softc;
1570 struct mii_data *mii = device_get_softc(sc->rl_miibus);
1573 ifmr->ifm_active = mii->mii_media_active;
1574 ifmr->ifm_status = mii->mii_media_status;
1578 rl_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
1580 struct rl_softc *sc = ifp->if_softc;
1581 struct ifreq *ifr = (struct ifreq *) data;
1582 struct mii_data *mii;
1589 if (ifp->if_flags & IFF_UP) {
1592 if (ifp->if_flags & IFF_RUNNING)
1604 mii = device_get_softc(sc->rl_miibus);
1605 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
1610 error = ether_ioctl(ifp, command, data);
1620 rl_watchdog(struct ifnet *ifp)
1622 struct rl_softc *sc = ifp->if_softc;
1627 device_printf(sc->rl_dev, "watchdog timeout\n");
1638 * Stop the adapter and free any mbufs allocated to the
1642 rl_stop(struct rl_softc *sc)
1644 struct ifnet *ifp = &sc->arpcom.ac_if;
1649 callout_stop(&sc->rl_stat_timer);
1650 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1652 CSR_WRITE_1(sc, RL_COMMAND, 0x00);
1653 CSR_WRITE_2(sc, RL_IMR, 0x0000);
1654 bus_dmamap_unload(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap);
1657 * Free the TX list buffers.
1659 for (i = 0; i < RL_TX_LIST_CNT; i++) {
1660 if (sc->rl_cdata.rl_tx_chain[i] != NULL) {
1661 bus_dmamap_unload(sc->rl_tag,
1662 sc->rl_cdata.rl_tx_dmamap[i]);
1663 bus_dmamap_destroy(sc->rl_tag,
1664 sc->rl_cdata.rl_tx_dmamap[i]);
1665 m_freem(sc->rl_cdata.rl_tx_chain[i]);
1666 sc->rl_cdata.rl_tx_chain[i] = NULL;
1667 CSR_WRITE_4(sc, RL_TXADDR0 + (i * sizeof(uint32_t)),
1674 * Stop all chip I/O so that the kernel's probe routines don't
1675 * get confused by errant DMAs when rebooting.
1678 rl_shutdown(device_t dev)
1680 struct rl_softc *sc;
1682 sc = device_get_softc(dev);
1688 * Device suspend routine. Stop the interface and save some PCI
1689 * settings in case the BIOS doesn't restore them properly on
1693 rl_suspend(device_t dev)
1695 struct rl_softc *sc = device_get_softc(dev);
1700 for (i = 0; i < 5; i++)
1701 sc->saved_maps[i] = pci_read_config(dev, PCIR_BAR(i), 4);
1702 sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4);
1703 sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1);
1704 sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1);
1705 sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1);
1713 * Device resume routine. Restore some PCI settings in case the BIOS
1714 * doesn't, re-enable busmastering, and restart the interface if
1717 static int rl_resume(device_t dev)
1719 struct rl_softc *sc = device_get_softc(dev);
1720 struct ifnet *ifp = &sc->arpcom.ac_if;
1723 /* better way to do this? */
1724 for (i = 0; i < 5; i++)
1725 pci_write_config(dev, PCIR_BAR(i), sc->saved_maps[i], 4);
1726 pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4);
1727 pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1);
1728 pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1);
1729 pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1);
1731 /* reenable busmastering */
1732 pci_enable_busmaster(dev);
1733 pci_enable_io(dev, RL_RES);
1735 /* reinitialize interface if necessary */
1736 if (ifp->if_flags & IFF_UP)