2 * Copyright (c) 1998,1999,2000,2001,2002 Søren Schmidt <sos@FreeBSD.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer,
10 * without modification, immediately at the beginning of the file.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * $FreeBSD: src/sys/dev/ata/ata-pci.c,v 1.32.2.15 2003/06/06 13:27:05 fjoe Exp $
29 * $DragonFly: src/sys/dev/disk/ata/ata-pci.c,v 1.21 2005/05/27 21:12:51 swildner Exp $
32 #include <sys/param.h>
33 #include <sys/systm.h>
34 #include <sys/kernel.h>
36 #include <sys/module.h>
39 #include <sys/malloc.h>
40 #include <sys/devicestat.h>
41 #include <sys/sysctl.h>
42 #include <machine/stdarg.h>
43 #include <machine/resource.h>
44 #include <machine/bus.h>
45 #include <machine/clock.h>
47 #include <bus/pci/pcivar.h>
48 #include <bus/pci/pcireg.h>
51 /* device structures */
52 struct ata_pci_controller {
53 struct resource *bmio;
60 #define IOMASK 0xfffffffc
61 #define GRANDPARENT(dev) device_get_parent(device_get_parent(dev))
62 #define ATA_MASTERDEV(dev) ((pci_get_progif(dev) & 0x80) && \
63 (pci_get_progif(dev) & 0x05) != 0x05)
66 ata_find_dev(device_t dev, u_int32_t devid, u_int32_t revid)
71 if (device_get_children(device_get_parent(dev), &children, &nchildren))
74 for (i = 0; i < nchildren; i++) {
75 if (pci_get_devid(children[i]) == devid &&
76 pci_get_revid(children[i]) >= revid) {
77 free(children, M_TEMP);
81 free(children, M_TEMP);
86 ata_via_southbridge_fixup(device_t dev)
91 if (device_get_children(device_get_parent(dev), &children, &nchildren))
94 for (i = 0; i < nchildren; i++) {
95 if (pci_get_devid(children[i]) == 0x03051106 || /* VIA VT8363 */
96 pci_get_devid(children[i]) == 0x03911106 || /* VIA VT8371 */
97 pci_get_devid(children[i]) == 0x31021106 || /* VIA VT8662 */
98 pci_get_devid(children[i]) == 0x31121106) { /* VIA VT8361 */
99 u_int8_t reg76 = pci_read_config(children[i], 0x76, 1);
101 if ((reg76 & 0xf0) != 0xd0) {
103 "Correcting VIA config for southbridge data corruption bug\n");
104 pci_write_config(children[i], 0x75, 0x80, 1);
105 pci_write_config(children[i], 0x76, (reg76 & 0x0f) | 0xd0, 1);
110 free(children, M_TEMP);
114 ata_pci_match(device_t dev)
116 if (pci_get_class(dev) != PCIC_STORAGE)
119 switch (pci_get_devid(dev)) {
120 /* supported chipsets */
122 return "Intel PIIX ATA controller";
125 return "Intel PIIX3 ATA controller";
130 return "Intel PIIX4 ATA33 controller";
133 return "Intel ICH0 ATA33 controller";
137 return "Intel ICH ATA66 controller";
141 return "Intel ICH2 ATA100 controller";
145 return "Intel ICH3 ATA100 controller";
149 return "Intel ICH4 ATA100 controller";
152 return "Intel ICH5 SATA150 controller";
155 return "Intel ICH5 ATA100 controller";
158 return "Intel ICH6/W SATA150 controller";
161 return "Intel ICH6R/RW SATA150 controller";
164 return "Intel ICH6R/RW ATA100 controller";
167 if (pci_get_revid(dev) >= 0xc4)
168 return "AcerLabs Aladdin ATA100 controller";
169 else if (pci_get_revid(dev) >= 0xc2)
170 return "AcerLabs Aladdin ATA66 controller";
171 else if (pci_get_revid(dev) >= 0x20)
172 return "AcerLabs Aladdin ATA33 controller";
174 return "AcerLabs Aladdin ATA controller";
177 if (ata_find_dev(dev, 0x05861106, 0x02))
178 return "VIA 82C586 ATA33 controller";
179 if (ata_find_dev(dev, 0x05861106, 0))
180 return "VIA 82C586 ATA controller";
181 if (ata_find_dev(dev, 0x05961106, 0x12))
182 return "VIA 82C596 ATA66 controller";
183 if (ata_find_dev(dev, 0x05961106, 0))
184 return "VIA 82C596 ATA33 controller";
185 if (ata_find_dev(dev, 0x06861106, 0x40))
186 return "VIA 82C686 ATA100 controller";
187 if (ata_find_dev(dev, 0x06861106, 0x10))
188 return "VIA 82C686 ATA66 controller";
189 if (ata_find_dev(dev, 0x06861106, 0))
190 return "VIA 82C686 ATA33 controller";
191 if (ata_find_dev(dev, 0x82311106, 0))
192 return "VIA 8231 ATA100 controller";
193 if (ata_find_dev(dev, 0x30741106, 0) ||
194 ata_find_dev(dev, 0x31091106, 0))
195 return "VIA 8233 ATA100 controller";
196 if (ata_find_dev(dev, 0x31471106, 0))
197 return "VIA 8233 ATA133 controller";
198 if (ata_find_dev(dev, 0x31771106, 0))
199 return "VIA 8235 ATA133 controller";
200 if (ata_find_dev(dev, 0x31491106, 0))
201 return "VIA 8237 ATA133 controller";
202 return "VIA Apollo ATA controller";
205 return "VIA 8237 SATA 150 controller";
208 if (ata_find_dev(dev, 0x07461039, 0))
209 return "SiS 5591 ATA133 controller";
210 if (ata_find_dev(dev, 0x06301039, 0x30) ||
211 ata_find_dev(dev, 0x06331039, 0) ||
212 ata_find_dev(dev, 0x06351039, 0) ||
213 ata_find_dev(dev, 0x06401039, 0) ||
214 ata_find_dev(dev, 0x06451039, 0) ||
215 ata_find_dev(dev, 0x06461039, 0) ||
216 ata_find_dev(dev, 0x06481039, 0) ||
217 ata_find_dev(dev, 0x06501039, 0) ||
218 ata_find_dev(dev, 0x07301039, 0) ||
219 ata_find_dev(dev, 0x07331039, 0) ||
220 ata_find_dev(dev, 0x07351039, 0) ||
221 ata_find_dev(dev, 0x07401039, 0) ||
222 ata_find_dev(dev, 0x07451039, 0) ||
223 ata_find_dev(dev, 0x07501039, 0))
224 return "SiS 5591 ATA100 controller";
225 else if (ata_find_dev(dev, 0x05301039, 0) ||
226 ata_find_dev(dev, 0x05401039, 0) ||
227 ata_find_dev(dev, 0x06201039, 0) ||
228 ata_find_dev(dev, 0x06301039, 0))
229 return "SiS 5591 ATA66 controller";
231 return "SiS 5591 ATA33 controller";
234 return "SiI 3512 SATA controller";
237 return "SiI 3112 SATA controller";
240 return "SiI 3114 SATA controller";
243 return "SiI 3124 SATA controller";
246 return "SiI 0680 ATA133 controller";
249 return "CMD 649 ATA100 controller";
252 return "CMD 648 ATA66 controller";
255 return "CMD 646 ATA controller";
258 if (pci_get_subclass(dev) == PCIS_STORAGE_IDE)
259 return "Cypress 82C693 ATA controller";
263 return "Cyrix 5530 ATA33 controller";
266 return "AMD 756 ATA66 controller";
269 return "AMD 766 ATA100 controller";
272 return "AMD 768 ATA100 controller";
275 return "AMD 8111 UltraATA/133 controller";
278 return "nVIDIA nForce1 ATA100 controller";
281 return "nVIDIA nForce2 ATA133 controller";
284 return "nVIDIA nForce3 ATA133 controller";
287 return "nVIDIA nForce3 PRO S1 controller";
290 return "nVIDIA nForce3 PRO controller";
293 return "ServerWorks ROSB4 ATA33 controller";
296 if (pci_get_revid(dev) >= 0x92)
297 return "ServerWorks CSB5 ATA100 controller";
299 return "ServerWorks CSB5 ATA66 controller";
302 return "ServerWorks CSB6 ATA100 controller (channel 0+1)";
305 return "ServerWorks CSB6 ATA66 controller (channel 2)";
308 return "Promise ATA33 controller";
312 return "Promise ATA66 controller";
316 return "Promise ATA100 controller";
320 if (pci_get_devid(GRANDPARENT(dev)) == 0x00221011 &&
321 pci_get_class(GRANDPARENT(dev)) == PCIC_BRIDGE) {
322 static long start = 0, end = 0;
324 /* we belive we are on a TX4, now do our (simple) magic */
325 if (pci_get_slot(dev) == 1) {
326 bus_get_resource(dev, SYS_RES_IRQ, 0, &start, &end);
327 return "Promise TX4 ATA100 controller (channel 0+1)";
329 else if (pci_get_slot(dev) == 2 && start && end) {
330 bus_set_resource(dev, SYS_RES_IRQ, 0, start, end);
332 return "Promise TX4 ATA100 controller (channel 2+3)";
337 return "Promise TX2 ATA100 controller";
343 return "Promise TX2 ATA133 controller";
346 switch (pci_get_revid(dev)) {
349 return "HighPoint HPT366 ATA66 controller";
351 return "HighPoint HPT368 ATA66 controller";
354 return "HighPoint HPT370 ATA100 controller";
356 return "HighPoint HPT372 ATA133 controller";
361 switch (pci_get_revid(dev)) {
364 return "HighPoint HPT372 ATA133 controller";
369 switch (pci_get_revid(dev)) {
371 return "HighPoint HPT374 ATA133 controller";
376 return "Cenatek Rocket Drive controller";
378 /* unsupported but known chipsets, generic DMA only */
381 return "RZ 100? ATA controller !WARNING! buggy chip data loss possible";
384 return "CMD 640 ATA controller !WARNING! buggy chip data loss possible";
386 /* unknown chipsets, try generic DMA if it seems possible */
388 if (pci_get_class(dev) == PCIC_STORAGE &&
389 (pci_get_subclass(dev) == PCIS_STORAGE_IDE))
390 return "Generic PCI ATA controller";
396 ata_pci_probe(device_t dev)
398 const char *desc = ata_pci_match(dev);
401 device_set_desc(dev, desc);
409 ata_pci_add_child(device_t dev, int unit)
413 /* check if this is located at one of the std addresses */
414 if (ATA_MASTERDEV(dev)) {
415 if (!(child = device_add_child(dev, "ata", unit)))
419 if (!(child = device_add_child(dev, "ata", 2)))
426 ata_pci_attach(device_t dev)
428 struct ata_pci_controller *controller = device_get_softc(dev);
429 u_int8_t class, subclass;
434 /* set up vendor-specific stuff */
435 type = pci_get_devid(dev);
436 class = pci_get_class(dev);
437 subclass = pci_get_subclass(dev);
438 cmd = pci_read_config(dev, PCIR_COMMAND, 4);
440 if (!(cmd & PCIM_CMD_PORTEN)) {
441 device_printf(dev, "ATA channel disabled by BIOS\n");
445 /* is busmastering supported ? */
446 if ((cmd & (PCIM_CMD_PORTEN | PCIM_CMD_BUSMASTEREN)) ==
447 (PCIM_CMD_PORTEN | PCIM_CMD_BUSMASTEREN)) {
449 /* is there a valid port range to connect to ? */
451 controller->bmio = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid,
452 0, ~0, 1, RF_ACTIVE);
453 if (!controller->bmio)
454 device_printf(dev, "Busmastering DMA not configured\n");
457 device_printf(dev, "Busmastering DMA not supported\n");
459 /* do extra chipset specific setups */
463 case 0x522910b9: /* Aladdin need to activate the ATAPI FIFO */
464 pci_write_config(dev, 0x53,
465 (pci_read_config(dev, 0x53, 1) & ~0x01) | 0x02, 1);
468 case 0x4d38105a: /* Promise 66 & 100 (before TX2) need the clock changed */
471 ATA_OUTB(controller->bmio, 0x11, ATA_INB(controller->bmio, 0x11)|0x0a);
474 case 0x4d33105a: /* Promise (before TX2) need burst mode turned on */
475 ATA_OUTB(controller->bmio, 0x1f, ATA_INB(controller->bmio, 0x1f)|0x01);
478 case 0x00041103: /* HighPoint HPT366/368/370/372 */
479 if (pci_get_revid(dev) < 2) { /* HPT 366 */
480 /* turn off interrupt prediction */
481 pci_write_config(dev, 0x51,
482 (pci_read_config(dev, 0x51, 1) & ~0x80), 1);
485 if (pci_get_revid(dev) < 5) { /* HPT368/370 */
486 /* turn off interrupt prediction */
487 pci_write_config(dev, 0x51,
488 (pci_read_config(dev, 0x51, 1) & ~0x03), 1);
489 pci_write_config(dev, 0x55,
490 (pci_read_config(dev, 0x55, 1) & ~0x03), 1);
492 /* turn on interrupts */
493 pci_write_config(dev, 0x5a,
494 (pci_read_config(dev, 0x5a, 1) & ~0x10), 1);
497 pci_write_config(dev, 0x5b, 0x22, 1);
502 case 0x00051103: /* HighPoint HPT372 */
503 case 0x00081103: /* HighPoint HPT374 */
504 /* turn off interrupt prediction */
505 pci_write_config(dev, 0x51, (pci_read_config(dev, 0x51, 1) & ~0x03), 1);
506 pci_write_config(dev, 0x55, (pci_read_config(dev, 0x55, 1) & ~0x03), 1);
508 /* turn on interrupts */
509 pci_write_config(dev, 0x5a, (pci_read_config(dev, 0x5a, 1) & ~0x10), 1);
512 pci_write_config(dev, 0x5b,
513 (pci_read_config(dev, 0x5b, 1) & 0x01) | 0x20, 1);
516 case 0x05711106: /* VIA 82C586, '596, '686 default setup */
517 /* prepare for ATA-66 on the 82C686a and 82C596b */
518 if ((ata_find_dev(dev, 0x06861106, 0x10) &&
519 !ata_find_dev(dev, 0x06861106, 0x40)) ||
520 ata_find_dev(dev, 0x05961106, 0x12))
521 pci_write_config(dev, 0x50, 0x030b030b, 4);
523 /* the southbridge might need the data corruption fix */
524 if (ata_find_dev(dev, 0x06861106, 0x40) ||
525 ata_find_dev(dev, 0x82311106, 0x10))
526 ata_via_southbridge_fixup(dev);
528 /* set fifo configuration half'n'half */
529 pci_write_config(dev, 0x43,
530 (pci_read_config(dev, 0x43, 1) & 0x90) | 0x2a, 1);
532 /* set status register read retry */
533 pci_write_config(dev, 0x44, pci_read_config(dev, 0x44, 1) | 0x08, 1);
535 /* set DMA read & end-of-sector fifo flush */
536 pci_write_config(dev, 0x46,
537 (pci_read_config(dev, 0x46, 1) & 0x0c) | 0xf0, 1);
539 /* set sector size */
540 pci_write_config(dev, 0x60, DEV_BSIZE, 2);
541 pci_write_config(dev, 0x68, DEV_BSIZE, 2);
543 case 0x74111022: /* AMD 766 default setup */
544 flags = 1; /* bugged */
546 case 0x74091022: /* AMD 756 default setup */
547 case 0x74411022: /* AMD 768 default setup */
548 case 0x746d1022: /* AMD 8111 default setup */
550 pci_write_config(dev, 0x41,
551 pci_read_config(dev, 0x41, 1) & 0x0f, 1);
553 pci_write_config(dev, 0x41,
554 pci_read_config(dev, 0x41, 1) | 0xf0, 1);
557 case 0x01bc10de: /* NVIDIA nForce1 default setup */
558 case 0x006510de: /* NVIDIA nForce2 default setup */
561 case 0x00d510de: /* NVIDIA nForce3 default setup */
563 pci_write_config(dev, 0x51,
564 pci_read_config(dev, 0x51, 1) & 0x0f, 1);
566 pci_write_config(dev, 0x51,
567 pci_read_config(dev, 0x51, 1) | 0xf0, 1);
571 case 0x02111166: /* ServerWorks ROSB4 enable UDMA33 */
572 pci_write_config(dev, 0x64,
573 (pci_read_config(dev, 0x64, 4) & ~0x00002000) |
577 case 0x02121166: /* ServerWorks CSB5 enable UDMA66/100 depending on rev */
578 pci_write_config(dev, 0x5a,
579 (pci_read_config(dev, 0x5a, 1) & ~0x40) |
580 (pci_get_revid(dev) >= 0x92) ? 0x03 : 0x02, 1);
583 case 0x06801095: /* SiI 0680 set ATA reference clock speed */
584 if ((pci_read_config(dev, 0x8a, 1) & 0x30) != 0x10)
585 pci_write_config(dev, 0x8a,
586 (pci_read_config(dev, 0x8a, 1) & 0x0F) | 0x10, 1);
587 if ((pci_read_config(dev, 0x8a, 1) & 0x30) != 0x10)
588 device_printf(dev, "SiI 0680 could not set clock\n");
593 case 0x06461095: /* CMD 646 enable interrupts, set DMA read mode */
594 pci_write_config(dev, 0x71, 0x01, 1);
597 case 0x10001042: /* RZ 100? known bad, no DMA */
599 case 0x06401095: /* CMD 640 known bad, no DMA */
600 controller->bmio = NULL;
601 device_printf(dev, "Busmastering DMA disabled\n");
604 if (controller->bmio) {
605 controller->bmaddr = rman_get_start(controller->bmio);
606 BUS_RELEASE_RESOURCE(device_get_parent(dev), dev,
607 SYS_RES_IOPORT, rid, controller->bmio);
608 controller->bmio = NULL;
612 * the Cypress chip is a mess, it contains two ATA functions, but
613 * both channels are visible on the first one.
614 * simply ignore the second function for now, as the right
615 * solution (ignoring the second channel on the first function)
616 * doesn't work with the crappy ATA interrupt setup on the alpha.
618 if (pci_get_devid(dev) == 0xc6931080 && pci_get_function(dev) > 1)
621 ata_pci_add_child(dev, 0);
623 if (ATA_MASTERDEV(dev) || pci_read_config(dev, 0x18, 4) & IOMASK)
624 ata_pci_add_child(dev, 1);
626 return bus_generic_attach(dev);
630 ata_pci_intr(struct ata_channel *ch)
635 * since we might share the IRQ with another device, and in some
636 * cases with our twin channel, we only want to process interrupts
637 * that we know this channel generated.
639 switch (ch->chiptype) {
640 case 0x00041103: /* HighPoint HPT366/368/370/372 */
641 case 0x00051103: /* HighPoint HPT372 */
642 case 0x00081103: /* HighPoint HPT374 */
643 if (((dmastat = ata_dmastatus(ch)) &
644 (ATA_BMSTAT_ACTIVE | ATA_BMSTAT_INTERRUPT)) != ATA_BMSTAT_INTERRUPT)
646 ATA_OUTB(ch->r_bmio, ATA_BMSTAT_PORT, dmastat | ATA_BMSTAT_INTERRUPT);
650 case 0x06481095: /* CMD 648 */
651 case 0x06491095: /* CMD 649 */
652 if (!(pci_read_config(device_get_parent(ch->dev), 0x71, 1) &
653 (ch->unit ? 0x08 : 0x04)))
655 #if !defined(NO_ATANG)
656 pci_write_config(device_get_parent(ch->dev), 0x71,
657 pci_read_config(device_get_parent(ch->dev), 0x71, 1) &
658 ~(ch->unit ? 0x04 : 0x08), 1);
662 case 0x06801095: /* SiI 680 */
663 if (!(pci_read_config(device_get_parent(ch->dev),
664 (ch->unit ? 0xb1 : 0xa1), 1) & 0x08))
668 case 0x4d33105a: /* Promise Ultra/Fasttrak 33 */
669 case 0x0d38105a: /* Promise Fasttrak 66 */
670 case 0x4d38105a: /* Promise Ultra/Fasttrak 66 */
671 case 0x0d30105a: /* Promise OEM ATA100 */
672 case 0x4d30105a: /* Promise Ultra/Fasttrak 100 */
673 if (!(ATA_INL(ch->r_bmio, (ch->unit ? 0x14 : 0x1c)) &
674 (ch->unit ? 0x00004000 : 0x00000400)))
678 case 0x4d68105a: /* Promise TX2 ATA100 */
679 case 0x6268105a: /* Promise TX2 ATA100 */
680 case 0x4d69105a: /* Promise TX2 ATA133 */
681 case 0x5275105a: /* Promise TX2 ATA133 */
682 case 0x6269105a: /* Promise TX2 ATA133 */
683 case 0x7275105a: /* Promise TX2 ATA133 */
684 ATA_OUTB(ch->r_bmio, ATA_BMDEVSPEC_0, 0x0b);
685 if (!(ATA_INB(ch->r_bmio, ATA_BMDEVSPEC_1) & 0x20))
689 case 0x24d18086: /* Intel ICH5 SATA150 */
690 case 0x24db8086: /* Intel ICH5 ATA100 */
691 case 0x26518086: /* Intel ICH6 SATA150 */
692 case 0x26528086: /* Intel ICH6R SATA150 */
693 dmastat = ATA_INB(ch->r_bmio, ATA_BMSTAT_PORT);
694 if ((dmastat & (ATA_BMSTAT_ACTIVE | ATA_BMSTAT_INTERRUPT)) !=
695 ATA_BMSTAT_INTERRUPT)
697 ATA_OUTB(ch->r_bmio, ATA_BMSTAT_PORT, dmastat &
698 ~(ATA_BMSTAT_DMA_SIMPLEX | ATA_BMSTAT_ERROR));
704 if (ch->flags & ATA_DMA_ACTIVE) {
705 if (!((dmastat = ata_dmastatus(ch)) & ATA_BMSTAT_INTERRUPT))
707 ATA_OUTB(ch->r_bmio, ATA_BMSTAT_PORT, dmastat | ATA_BMSTAT_INTERRUPT);
714 ata_pci_print_child(device_t dev, device_t child)
716 struct ata_channel *ch = device_get_softc(child);
719 retval += bus_print_child_header(dev, child);
720 retval += printf(": at 0x%lx", rman_get_start(ch->r_io));
722 if (ATA_MASTERDEV(dev))
723 retval += printf(" irq %d", 14 + ch->unit);
725 retval += bus_print_child_footer(dev, child);
730 static struct resource *
731 ata_pci_alloc_resource(device_t dev, device_t child, int type, int *rid,
732 u_long start, u_long end, u_long count, u_int flags)
734 struct ata_pci_controller *controller = device_get_softc(dev);
735 struct resource *res = NULL;
736 int unit = ((struct ata_channel *)device_get_softc(child))->unit;
739 if (type == SYS_RES_IOPORT) {
742 if (ATA_MASTERDEV(dev)) {
744 start = (unit ? ATA_SECONDARY : ATA_PRIMARY);
745 end = start + ATA_IOSIZE - 1;
747 res = BUS_ALLOC_RESOURCE(device_get_parent(dev), child,
748 SYS_RES_IOPORT, &myrid,
749 start, end, count, flags);
752 myrid = 0x10 + 8 * unit;
753 res = BUS_ALLOC_RESOURCE(device_get_parent(dev), dev,
754 SYS_RES_IOPORT, &myrid,
755 start, end, count, flags);
759 case ATA_ALTADDR_RID:
760 if (ATA_MASTERDEV(dev)) {
762 start = (unit ? ATA_SECONDARY : ATA_PRIMARY) + ATA_ALTOFFSET;
763 end = start + ATA_ALTIOSIZE - 1;
764 count = ATA_ALTIOSIZE;
765 res = BUS_ALLOC_RESOURCE(device_get_parent(dev), child,
766 SYS_RES_IOPORT, &myrid,
767 start, end, count, flags);
770 myrid = 0x14 + 8 * unit;
771 res = BUS_ALLOC_RESOURCE(device_get_parent(dev), dev,
772 SYS_RES_IOPORT, &myrid,
773 start, end, count, flags);
775 start = rman_get_start(res) + 2;
776 end = start + ATA_ALTIOSIZE - 1;
777 count = ATA_ALTIOSIZE;
778 BUS_RELEASE_RESOURCE(device_get_parent(dev), dev,
779 SYS_RES_IOPORT, myrid, res);
780 res = BUS_ALLOC_RESOURCE(device_get_parent(dev), dev,
781 SYS_RES_IOPORT, &myrid,
782 start, end, count, flags);
788 if (controller->bmaddr) {
791 controller->bmaddr : controller->bmaddr+ATA_BMIOSIZE);
792 end = start + ATA_BMIOSIZE - 1;
793 count = ATA_BMIOSIZE;
794 res = BUS_ALLOC_RESOURCE(device_get_parent(dev), child,
795 SYS_RES_IOPORT, &myrid,
796 start, end, count, flags);
802 if (type == SYS_RES_IRQ && *rid == ATA_IRQ_RID) {
803 if (ATA_MASTERDEV(dev)) {
804 int irq = (unit == 0 ? 14 : 15);
806 return BUS_ALLOC_RESOURCE(device_get_parent(dev), child,
807 SYS_RES_IRQ, rid, irq, irq, 1, flags);
810 /* primary and secondary channels share interrupt, keep track */
811 if (!controller->irq)
812 controller->irq = BUS_ALLOC_RESOURCE(device_get_parent(dev),
814 rid, 0, ~0, 1, flags);
815 controller->irqcnt++;
816 return controller->irq;
823 ata_pci_release_resource(device_t dev, device_t child, int type, int rid,
826 struct ata_pci_controller *controller = device_get_softc(dev);
827 int unit = ((struct ata_channel *)device_get_softc(child))->unit;
829 if (type == SYS_RES_IOPORT) {
832 if (ATA_MASTERDEV(dev))
833 return BUS_RELEASE_RESOURCE(device_get_parent(dev), child,
834 SYS_RES_IOPORT, 0x0, r);
836 return BUS_RELEASE_RESOURCE(device_get_parent(dev), dev,
837 SYS_RES_IOPORT, 0x10 + 8 * unit, r);
840 case ATA_ALTADDR_RID:
841 if (ATA_MASTERDEV(dev))
842 return BUS_RELEASE_RESOURCE(device_get_parent(dev), child,
843 SYS_RES_IOPORT, 0x0, r);
845 return BUS_RELEASE_RESOURCE(device_get_parent(dev), dev,
846 SYS_RES_IOPORT, 0x14 + 8 * unit, r);
850 return BUS_RELEASE_RESOURCE(device_get_parent(dev), child,
851 SYS_RES_IOPORT, 0x20, r);
856 if (type == SYS_RES_IRQ) {
857 if (rid != ATA_IRQ_RID)
860 if (ATA_MASTERDEV(dev)) {
861 return BUS_RELEASE_RESOURCE(device_get_parent(dev), child,
862 SYS_RES_IRQ, rid, r);
865 /* primary and secondary channels share interrupt, keep track */
866 if (--controller->irqcnt)
868 controller->irq = NULL;
869 return BUS_RELEASE_RESOURCE(device_get_parent(dev), dev,
870 SYS_RES_IRQ, rid, r);
877 ata_pci_setup_intr(device_t dev, device_t child, struct resource *irq,
878 int flags, driver_intr_t *intr, void *arg,
879 void **cookiep, lwkt_serialize_t serializer)
881 if (ATA_MASTERDEV(dev)) {
882 return BUS_SETUP_INTR(device_get_parent(dev), child, irq,
883 flags, intr, arg, cookiep, serializer);
886 return BUS_SETUP_INTR(device_get_parent(dev), dev, irq,
887 flags, intr, arg, cookiep, serializer);
891 ata_pci_teardown_intr(device_t dev, device_t child, struct resource *irq,
894 if (ATA_MASTERDEV(dev)) {
895 return BUS_TEARDOWN_INTR(device_get_parent(dev), child, irq, cookie);
898 return BUS_TEARDOWN_INTR(device_get_parent(dev), dev, irq, cookie);
901 static device_method_t ata_pci_methods[] = {
902 /* device interface */
903 DEVMETHOD(device_probe, ata_pci_probe),
904 DEVMETHOD(device_attach, ata_pci_attach),
905 DEVMETHOD(device_shutdown, bus_generic_shutdown),
906 DEVMETHOD(device_suspend, bus_generic_suspend),
907 DEVMETHOD(device_resume, bus_generic_resume),
910 DEVMETHOD(bus_print_child, ata_pci_print_child),
911 DEVMETHOD(bus_alloc_resource, ata_pci_alloc_resource),
912 DEVMETHOD(bus_release_resource, ata_pci_release_resource),
913 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
914 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
915 DEVMETHOD(bus_setup_intr, ata_pci_setup_intr),
916 DEVMETHOD(bus_teardown_intr, ata_pci_teardown_intr),
920 static driver_t ata_pci_driver = {
923 sizeof(struct ata_pci_controller),
926 static devclass_t ata_pci_devclass;
928 DRIVER_MODULE(atapci, pci, ata_pci_driver, ata_pci_devclass, 0, 0);
931 ata_pcisub_probe(device_t dev)
933 struct ata_channel *ch = device_get_softc(dev);
937 /* find channel number on this controller */
938 device_get_children(device_get_parent(dev), &children, &count);
939 for (i = 0; i < count; i++) {
940 if (children[i] == dev)
943 free(children, M_TEMP);
944 ch->chiptype = pci_get_devid(device_get_parent(dev));
945 ch->intr_func = ata_pci_intr;
946 return ata_probe(dev);
949 static device_method_t ata_pcisub_methods[] = {
950 /* device interface */
951 DEVMETHOD(device_probe, ata_pcisub_probe),
952 DEVMETHOD(device_attach, ata_attach),
953 DEVMETHOD(device_detach, ata_detach),
954 DEVMETHOD(device_resume, ata_resume),
958 static driver_t ata_pcisub_driver = {
961 sizeof(struct ata_channel),
964 DRIVER_MODULE(ata, atapci, ata_pcisub_driver, ata_devclass, 0, 0);