2 * Copyright (c) 1996, by Steve Passe
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. The name of the developer may NOT be used to endorse or promote products
11 * derived from this software without specific prior written permission.
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * $FreeBSD: src/sys/i386/include/smptests.h,v 1.33.2.1 2000/05/16 06:58:10 dillon Exp $
26 * $DragonFly: src/sys/i386/include/Attic/smptests.h,v 1.5 2004/02/21 06:37:07 dillon Exp $
29 #ifndef _MACHINE_SMPTESTS_H_
30 #define _MACHINE_SMPTESTS_H_
33 * Various 'tests in progress' and configuration parameters.
39 * Control the "giant lock" pushdown by logical steps.
41 #define PUSHDOWN_LEVEL_1
42 #define PUSHDOWN_LEVEL_2
43 #define PUSHDOWN_LEVEL_3_NOT
44 #define PUSHDOWN_LEVEL_4_NOT
47 * Put FAST_INTR() ISRs at an APIC priority above the regular INTs.
48 * Allow the mp_lock() routines to handle FAST interrupts while spinning.
50 #ifdef PUSHDOWN_LEVEL_1
56 * These defines enable critical region locking of areas that were
57 * protected via cli/sti in the UP kernel.
59 * MPINTRLOCK protects all the generic areas.
60 * COMLOCK protects the sio/cy drivers.
61 * CLOCKLOCK protects clock hardware and data
62 * known to be incomplete:
66 #ifdef PUSHDOWN_LEVEL_1
67 #define USE_MPINTRLOCK
74 * INTR_SIMPLELOCK has been removed, as the interrupt mechanism will likely
75 * not use this sort of optimization if we move to interrupt threads.
77 #ifdef PUSHDOWN_LEVEL_4
82 * CPL_AND_CML has been removed. Interrupt threads will eventually not
83 * use either mechanism so there is no point trying to optimize it.
85 #ifdef PUSHDOWN_LEVEL_3
89 * Send CPUSTOP IPI for stop/restart of other CPUs on DDB break.
91 #define VERBOSE_CPUSTOP_ON_DDBBREAK
93 #define CPUSTOP_ON_DDBBREAK
98 #define COUNT_XINVLTLB_HITS
102 * Hack to "fake-out" kernel into thinking it is running on a 'default config'.
104 * value == default type
105 #define TEST_DEFAULT_CONFIG 6
109 * Simple test code for IPI interaction, save for future...
112 #define IPI_TARGET_TEST1 1
120 * Portions of the old TEST_LOPRIO code, back from the grave!
125 * Don't assume that slow interrupt handler X is called from vector
128 #define APIC_INTR_REORDER
131 * Redirect clock interrupts to a higher priority (fast intr) vector,
132 * while still using the slow interrupt handler. Only effective when
133 * APIC_INTR_REORDER is defined.
135 #define APIC_INTR_HIGHPRI_CLOCK
139 #if 0 /* DEPRECATED */
142 * Address of POST hardware port.
143 * Defining this enables POSTCODE macros.
145 #define POST_ADDR 0x80
150 * POST hardware macros.
153 #define ASMPOSTCODE_INC \
155 movl _current_postcode, %eax ; \
158 movl %eax, _current_postcode ; \
159 outb %al, $POST_ADDR ; \
163 * Overwrite the current_postcode value.
165 #define ASMPOSTCODE(X) \
168 movl %eax, _current_postcode ; \
169 outb %al, $POST_ADDR ; \
173 * Overwrite the current_postcode low nibble.
175 #define ASMPOSTCODE_LO(X) \
177 movl _current_postcode, %eax ; \
180 movl %eax, _current_postcode ; \
181 outb %al, $POST_ADDR ; \
185 * Overwrite the current_postcode high nibble.
187 #define ASMPOSTCODE_HI(X) \
189 movl _current_postcode, %eax ; \
191 orl $(X<<4), %eax ; \
192 movl %eax, _current_postcode ; \
193 outb %al, $POST_ADDR ; \
196 #define ASMPOSTCODE_INC
197 #define ASMPOSTCODE(X)
198 #define ASMPOSTCODE_LO(X)
199 #define ASMPOSTCODE_HI(X)
200 #endif /* POST_ADDR */
202 #endif /* DEPRECATED */
204 #if 0 /* DEPRECATED */
206 * These are all temps for debugging...
212 * This macro traps unexpected INTs to a specific CPU, eg. GUARD_CPU.
216 #define MAYBE_PANIC(irq_num) \
217 cmpl $GUARD_CPU, _cpuid ; \
219 cmpl $1, _ok_test1 ; \
236 #define MAYBE_PANIC(irq_num)
237 #endif /* GUARD_INTS */
239 #endif /* DEPRECATED */
241 #endif /* _MACHINE_SMPTESTS_H_ */