1 /* i915_dma.c -- DMA support for the I915 -*- linux-c -*-
4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
29 #include <linux/async.h>
31 #include "intel_drv.h"
32 #include <drm/i915_drm.h>
33 #include <drm/drm_legacy.h>
35 #include "i915_vgpu.h"
36 #include "intel_ringbuffer.h"
37 #include <linux/workqueue.h>
40 static int i915_getparam(struct drm_device *dev, void *data,
41 struct drm_file *file_priv)
43 struct drm_i915_private *dev_priv = dev->dev_private;
44 drm_i915_getparam_t *param = data;
47 switch (param->param) {
48 case I915_PARAM_IRQ_ACTIVE:
49 case I915_PARAM_ALLOW_BATCHBUFFER:
50 case I915_PARAM_LAST_DISPATCH:
51 /* Reject all old ums/dri params. */
53 case I915_PARAM_CHIPSET_ID:
54 value = dev->pdev->device;
56 case I915_PARAM_REVISION:
57 value = dev->pdev->revision;
59 case I915_PARAM_HAS_GEM:
62 case I915_PARAM_NUM_FENCES_AVAIL:
63 value = dev_priv->num_fence_regs - dev_priv->fence_reg_start;
65 case I915_PARAM_HAS_OVERLAY:
66 value = dev_priv->overlay ? 1 : 0;
68 case I915_PARAM_HAS_PAGEFLIPPING:
71 case I915_PARAM_HAS_EXECBUF2:
75 case I915_PARAM_HAS_BSD:
76 value = intel_ring_initialized(&dev_priv->ring[VCS]);
78 case I915_PARAM_HAS_BLT:
79 value = intel_ring_initialized(&dev_priv->ring[BCS]);
81 case I915_PARAM_HAS_VEBOX:
82 value = intel_ring_initialized(&dev_priv->ring[VECS]);
84 case I915_PARAM_HAS_BSD2:
85 value = intel_ring_initialized(&dev_priv->ring[VCS2]);
87 case I915_PARAM_HAS_RELAXED_FENCING:
90 case I915_PARAM_HAS_COHERENT_RINGS:
93 case I915_PARAM_HAS_EXEC_CONSTANTS:
94 value = INTEL_INFO(dev)->gen >= 4;
96 case I915_PARAM_HAS_RELAXED_DELTA:
99 case I915_PARAM_HAS_GEN7_SOL_RESET:
102 case I915_PARAM_HAS_LLC:
103 value = HAS_LLC(dev);
105 case I915_PARAM_HAS_WT:
108 case I915_PARAM_HAS_ALIASING_PPGTT:
109 value = USES_PPGTT(dev);
111 case I915_PARAM_HAS_WAIT_TIMEOUT:
114 case I915_PARAM_HAS_SEMAPHORES:
115 value = i915_semaphore_is_enabled(dev);
117 case I915_PARAM_HAS_PINNED_BATCHES:
120 case I915_PARAM_HAS_EXEC_NO_RELOC:
123 case I915_PARAM_HAS_EXEC_HANDLE_LUT:
126 case I915_PARAM_CMD_PARSER_VERSION:
127 value = i915_cmd_parser_get_version();
129 case I915_PARAM_HAS_COHERENT_PHYS_GTT:
132 case I915_PARAM_SUBSLICE_TOTAL:
133 value = INTEL_INFO(dev)->subslice_total;
137 case I915_PARAM_EU_TOTAL:
138 value = INTEL_INFO(dev)->eu_total;
143 DRM_DEBUG("Unknown parameter %d\n", param->param);
147 if (copy_to_user(param->value, &value, sizeof(int))) {
148 DRM_ERROR("copy_to_user failed\n");
155 static int i915_setparam(struct drm_device *dev, void *data,
156 struct drm_file *file_priv)
158 struct drm_i915_private *dev_priv = dev->dev_private;
159 drm_i915_setparam_t *param = data;
161 switch (param->param) {
162 case I915_SETPARAM_USE_MI_BATCHBUFFER_START:
163 case I915_SETPARAM_TEX_LRU_LOG_GRANULARITY:
164 case I915_SETPARAM_ALLOW_BATCHBUFFER:
165 /* Reject all old ums/dri params. */
168 case I915_SETPARAM_NUM_USED_FENCES:
169 if (param->value > dev_priv->num_fence_regs ||
172 /* Userspace can use first N regs */
173 dev_priv->fence_reg_start = param->value;
176 DRM_DEBUG_DRIVER("unknown parameter %d\n",
184 static int i915_get_bridge_dev(struct drm_device *dev)
186 struct drm_i915_private *dev_priv = dev->dev_private;
187 static struct pci_dev i915_bridge_dev;
189 i915_bridge_dev.dev = pci_find_dbsf(0, 0, 0, 0);
190 if (!i915_bridge_dev.dev) {
191 DRM_ERROR("bridge device not found\n");
195 dev_priv->bridge_dev = &i915_bridge_dev;
199 #define MCHBAR_I915 0x44
200 #define MCHBAR_I965 0x48
201 #define MCHBAR_SIZE (4*4096)
203 #define DEVEN_REG 0x54
204 #define DEVEN_MCHBAR_EN (1 << 28)
206 /* Allocate space for the MCH regs if needed, return nonzero on error */
208 intel_alloc_mchbar_resource(struct drm_device *dev)
210 struct drm_i915_private *dev_priv = dev->dev_private;
211 int reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
213 u32 temp_lo, temp_hi = 0;
216 if (INTEL_INFO(dev)->gen >= 4)
217 pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);
218 pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo);
219 mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
221 /* If ACPI doesn't have it, assume we need to allocate it ourselves */
224 pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE))
228 /* Get some space for it */
229 vga = device_get_parent(dev->dev);
230 dev_priv->mch_res_rid = 0x100;
231 dev_priv->mch_res = BUS_ALLOC_RESOURCE(device_get_parent(vga),
232 dev->dev, SYS_RES_MEMORY, &dev_priv->mch_res_rid, 0, ~0UL,
233 MCHBAR_SIZE, RF_ACTIVE | RF_SHAREABLE, -1);
234 if (dev_priv->mch_res == NULL) {
235 DRM_ERROR("failed mchbar resource alloc\n");
239 if (INTEL_INFO(dev)->gen >= 4)
240 pci_write_config_dword(dev_priv->bridge_dev, reg + 4,
241 upper_32_bits(rman_get_start(dev_priv->mch_res)));
243 pci_write_config_dword(dev_priv->bridge_dev, reg,
244 lower_32_bits(rman_get_start(dev_priv->mch_res)));
248 /* Setup MCHBAR if possible, return true if we should disable it again */
250 intel_setup_mchbar(struct drm_device *dev)
252 struct drm_i915_private *dev_priv = dev->dev_private;
253 int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
257 if (IS_VALLEYVIEW(dev))
260 dev_priv->mchbar_need_disable = false;
262 if (IS_I915G(dev) || IS_I915GM(dev)) {
263 pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp);
264 enabled = !!(temp & DEVEN_MCHBAR_EN);
266 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
270 /* If it's already enabled, don't have to do anything */
274 if (intel_alloc_mchbar_resource(dev))
277 dev_priv->mchbar_need_disable = true;
279 /* Space is allocated or reserved, so enable it. */
280 if (IS_I915G(dev) || IS_I915GM(dev)) {
281 pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG,
282 temp | DEVEN_MCHBAR_EN);
284 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
285 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1);
290 intel_teardown_mchbar(struct drm_device *dev)
292 struct drm_i915_private *dev_priv = dev->dev_private;
293 int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
297 if (dev_priv->mchbar_need_disable) {
298 if (IS_I915G(dev) || IS_I915GM(dev)) {
299 pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp);
300 temp &= ~DEVEN_MCHBAR_EN;
301 pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG, temp);
303 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
305 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp);
309 if (dev_priv->mch_res != NULL) {
310 vga = device_get_parent(dev->dev);
311 BUS_DEACTIVATE_RESOURCE(device_get_parent(vga), dev->dev,
312 SYS_RES_MEMORY, dev_priv->mch_res_rid, dev_priv->mch_res);
313 BUS_RELEASE_RESOURCE(device_get_parent(vga), dev->dev,
314 SYS_RES_MEMORY, dev_priv->mch_res_rid, dev_priv->mch_res);
315 dev_priv->mch_res = NULL;
320 /* true = enable decode, false = disable decoder */
321 static unsigned int i915_vga_set_decode(void *cookie, bool state)
323 struct drm_device *dev = cookie;
325 intel_modeset_vga_set_state(dev, state);
327 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
328 VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
330 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
333 static void i915_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
335 struct drm_device *dev = pci_get_drvdata(pdev);
336 pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
338 if (state == VGA_SWITCHEROO_ON) {
339 pr_info("switched on\n");
340 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
341 /* i915 resume handler doesn't set to D0 */
342 pci_set_power_state(dev->pdev, PCI_D0);
343 i915_resume_legacy(dev);
344 dev->switch_power_state = DRM_SWITCH_POWER_ON;
346 pr_err("switched off\n");
347 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
348 i915_suspend_legacy(dev, pmm);
349 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
353 static bool i915_switcheroo_can_switch(struct pci_dev *pdev)
355 struct drm_device *dev = pci_get_drvdata(pdev);
358 * FIXME: open_count is protected by drm_global_mutex but that would lead to
359 * locking inversion with the driver load path. And the access here is
360 * completely racy anyway. So don't bother with locking for now.
362 return dev->open_count == 0;
365 static const struct vga_switcheroo_client_ops i915_switcheroo_ops = {
366 .set_gpu_state = i915_switcheroo_set_state,
368 .can_switch = i915_switcheroo_can_switch,
372 static int i915_load_modeset_init(struct drm_device *dev)
374 struct drm_i915_private *dev_priv = dev->dev_private;
377 ret = intel_parse_bios(dev);
379 DRM_INFO("failed to find VBIOS tables\n");
382 /* If we have > 1 VGA cards, then we need to arbitrate access
383 * to the common VGA resources.
385 * If we are a secondary display controller (!PCI_DISPLAY_CLASS_VGA),
386 * then we do not take part in VGA arbitration and the
387 * vga_client_register() fails with -ENODEV.
389 ret = vga_client_register(dev->pdev, dev, NULL, i915_vga_set_decode);
390 if (ret && ret != -ENODEV)
393 intel_register_dsm_handler();
395 ret = vga_switcheroo_register_client(dev->pdev, &i915_switcheroo_ops, false);
397 goto cleanup_vga_client;
399 /* Initialise stolen first so that we may reserve preallocated
400 * objects for the BIOS to KMS transition.
402 ret = i915_gem_init_stolen(dev);
404 goto cleanup_vga_switcheroo;
407 intel_power_domains_init_hw(dev_priv);
410 dev_priv->dev->pdev->irq = dev->irq;
412 ret = intel_irq_install(dev_priv);
414 goto cleanup_gem_stolen;
416 /* Important: The output setup functions called by modeset_init need
417 * working irqs for e.g. gmbus and dp aux transfers. */
418 intel_modeset_init(dev);
420 ret = i915_gem_init(dev);
424 intel_modeset_gem_init(dev);
426 /* Always safe in the mode setting case. */
427 /* FIXME: do pre/post-mode set stuff in core KMS code */
428 dev->vblank_disable_allowed = 1;
429 if (INTEL_INFO(dev)->num_pipes == 0)
432 ret = intel_fbdev_init(dev);
436 /* Only enable hotplug handling once the fbdev is fully set up. */
437 intel_hpd_init(dev_priv);
440 * Some ports require correctly set-up hpd registers for detection to
441 * work properly (leading to ghost connected connector status), e.g. VGA
442 * on gm45. Hence we can only set up the initial fbdev config after hpd
443 * irqs are fully enabled. Now we should scan for the initial config
444 * only once hotplug handling is enabled, but due to screwed-up locking
445 * around kms/fbdev init we can't protect the fdbev initial config
446 * scanning against hotplug events. Hence do this first and ignore the
447 * tiny window where we will loose hotplug notifactions.
449 async_schedule(intel_fbdev_initial_config, dev_priv);
451 drm_kms_helper_poll_init(dev);
456 mutex_lock(&dev->struct_mutex);
457 i915_gem_cleanup_ringbuffer(dev);
458 i915_gem_context_fini(dev);
459 mutex_unlock(&dev->struct_mutex);
461 drm_irq_uninstall(dev);
464 i915_gem_cleanup_stolen(dev);
465 cleanup_vga_switcheroo:
466 vga_switcheroo_unregister_client(dev->pdev);
468 vga_client_register(dev->pdev, NULL, NULL, NULL);
474 #if IS_ENABLED(CONFIG_FB)
475 static int i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv)
477 struct apertures_struct *ap;
478 struct pci_dev *pdev = dev_priv->dev->pdev;
482 ap = alloc_apertures(1);
486 ap->ranges[0].base = dev_priv->gtt.mappable_base;
487 ap->ranges[0].size = dev_priv->gtt.mappable_end;
490 pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
492 ret = remove_conflicting_framebuffers(ap, "inteldrmfb", primary);
499 static int i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv)
505 #if !defined(CONFIG_VGA_CONSOLE)
506 static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
510 #elif !defined(CONFIG_DUMMY_CONSOLE)
511 static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
516 static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
520 DRM_INFO("Replacing VGA console driver\n");
523 if (con_is_bound(&vga_con))
524 ret = do_take_over_console(&dummy_con, 0, MAX_NR_CONSOLES - 1, 1);
526 ret = do_unregister_con_driver(&vga_con);
528 /* Ignore "already unregistered". */
538 static void i915_dump_device_info(struct drm_i915_private *dev_priv)
541 const struct intel_device_info *info = &dev_priv->info;
543 #define PRINT_S(name) "%s"
545 #define PRINT_FLAG(name) info->name ? #name "," : ""
547 DRM_DEBUG_DRIVER("i915 device info: gen=%i, pciid=0x%04x rev=0x%02x flags="
548 DEV_INFO_FOR_EACH_FLAG(PRINT_S, SEP_EMPTY),
550 dev_priv->dev->pdev->device,
551 dev_priv->dev->pdev->revision,
552 DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_COMMA));
561 * Determine various intel_device_info fields at runtime.
563 * Use it when either:
564 * - it's judged too laborious to fill n static structures with the limit
565 * when a simple if statement does the job,
566 * - run-time checks (eg read fuse/strap registers) are needed.
568 * This function needs to be called:
569 * - after the MMIO has been setup as we are reading registers,
570 * - after the PCH has been detected,
571 * - before the first usage of the fields it can tweak.
573 static void intel_device_info_runtime_init(struct drm_device *dev)
575 struct drm_i915_private *dev_priv = dev->dev_private;
576 struct intel_device_info *info;
579 info = (struct intel_device_info *)&dev_priv->info;
581 if (IS_VALLEYVIEW(dev) || INTEL_INFO(dev)->gen == 9)
582 for_each_pipe(dev_priv, pipe)
583 info->num_sprites[pipe] = 2;
585 for_each_pipe(dev_priv, pipe)
586 info->num_sprites[pipe] = 1;
588 if (i915.disable_display) {
589 DRM_INFO("Display disabled (module parameter)\n");
591 } else if (info->num_pipes > 0 &&
592 (INTEL_INFO(dev)->gen == 7 || INTEL_INFO(dev)->gen == 8) &&
593 !IS_VALLEYVIEW(dev)) {
594 u32 fuse_strap = I915_READ(FUSE_STRAP);
595 u32 sfuse_strap = I915_READ(SFUSE_STRAP);
598 * SFUSE_STRAP is supposed to have a bit signalling the display
599 * is fused off. Unfortunately it seems that, at least in
600 * certain cases, fused off display means that PCH display
601 * reads don't land anywhere. In that case, we read 0s.
603 * On CPT/PPT, we can detect this case as SFUSE_STRAP_FUSE_LOCK
604 * should be set when taking over after the firmware.
606 if (fuse_strap & ILK_INTERNAL_DISPLAY_DISABLE ||
607 sfuse_strap & SFUSE_STRAP_DISPLAY_DISABLED ||
608 (dev_priv->pch_type == PCH_CPT &&
609 !(sfuse_strap & SFUSE_STRAP_FUSE_LOCK))) {
610 DRM_INFO("Display fused off, disabling\n");
615 /* Initialize slice/subslice/EU info */
616 if (IS_CHERRYVIEW(dev)) {
619 fuse = I915_READ(CHV_FUSE_GT);
621 info->slice_total = 1;
623 if (!(fuse & CHV_FGT_DISABLE_SS0)) {
624 info->subslice_per_slice++;
625 eu_dis = fuse & (CHV_FGT_EU_DIS_SS0_R0_MASK |
626 CHV_FGT_EU_DIS_SS0_R1_MASK);
627 info->eu_total += 8 - hweight32(eu_dis);
630 if (!(fuse & CHV_FGT_DISABLE_SS1)) {
631 info->subslice_per_slice++;
632 eu_dis = fuse & (CHV_FGT_EU_DIS_SS1_R0_MASK |
633 CHV_FGT_EU_DIS_SS1_R1_MASK);
634 info->eu_total += 8 - hweight32(eu_dis);
637 info->subslice_total = info->subslice_per_slice;
639 * CHV expected to always have a uniform distribution of EU
642 info->eu_per_subslice = info->subslice_total ?
643 info->eu_total / info->subslice_total :
646 * CHV supports subslice power gating on devices with more than
647 * one subslice, and supports EU power gating on devices with
648 * more than one EU pair per subslice.
650 info->has_slice_pg = 0;
651 info->has_subslice_pg = (info->subslice_total > 1);
652 info->has_eu_pg = (info->eu_per_subslice > 2);
653 } else if (IS_SKYLAKE(dev)) {
654 const int s_max = 3, ss_max = 4, eu_max = 8;
656 u32 fuse2, eu_disable[s_max], s_enable, ss_disable;
658 fuse2 = I915_READ(GEN8_FUSE2);
659 s_enable = (fuse2 & GEN8_F2_S_ENA_MASK) >>
661 ss_disable = (fuse2 & GEN9_F2_SS_DIS_MASK) >>
662 GEN9_F2_SS_DIS_SHIFT;
664 eu_disable[0] = I915_READ(GEN8_EU_DISABLE0);
665 eu_disable[1] = I915_READ(GEN8_EU_DISABLE1);
666 eu_disable[2] = I915_READ(GEN8_EU_DISABLE2);
668 info->slice_total = hweight32(s_enable);
670 * The subslice disable field is global, i.e. it applies
671 * to each of the enabled slices.
673 info->subslice_per_slice = ss_max - hweight32(ss_disable);
674 info->subslice_total = info->slice_total *
675 info->subslice_per_slice;
678 * Iterate through enabled slices and subslices to
679 * count the total enabled EU.
681 for (s = 0; s < s_max; s++) {
682 if (!(s_enable & (0x1 << s)))
683 /* skip disabled slice */
686 for (ss = 0; ss < ss_max; ss++) {
689 if (ss_disable & (0x1 << ss))
690 /* skip disabled subslice */
693 n_disabled = hweight8(eu_disable[s] >>
697 * Record which subslice(s) has(have) 7 EUs. we
698 * can tune the hash used to spread work among
699 * subslices if they are unbalanced.
701 if (eu_max - n_disabled == 7)
702 info->subslice_7eu[s] |= 1 << ss;
704 info->eu_total += eu_max - n_disabled;
709 * SKL is expected to always have a uniform distribution
710 * of EU across subslices with the exception that any one
711 * EU in any one subslice may be fused off for die
714 info->eu_per_subslice = info->subslice_total ?
715 DIV_ROUND_UP(info->eu_total,
716 info->subslice_total) : 0;
718 * SKL supports slice power gating on devices with more than
719 * one slice, and supports EU power gating on devices with
720 * more than one EU pair per subslice.
722 info->has_slice_pg = (info->slice_total > 1) ? 1 : 0;
723 info->has_subslice_pg = 0;
724 info->has_eu_pg = (info->eu_per_subslice > 2) ? 1 : 0;
726 DRM_DEBUG_DRIVER("slice total: %u\n", info->slice_total);
727 DRM_DEBUG_DRIVER("subslice total: %u\n", info->subslice_total);
728 DRM_DEBUG_DRIVER("subslice per slice: %u\n", info->subslice_per_slice);
729 DRM_DEBUG_DRIVER("EU total: %u\n", info->eu_total);
730 DRM_DEBUG_DRIVER("EU per subslice: %u\n", info->eu_per_subslice);
731 DRM_DEBUG_DRIVER("has slice power gating: %s\n",
732 info->has_slice_pg ? "y" : "n");
733 DRM_DEBUG_DRIVER("has subslice power gating: %s\n",
734 info->has_subslice_pg ? "y" : "n");
735 DRM_DEBUG_DRIVER("has EU power gating: %s\n",
736 info->has_eu_pg ? "y" : "n");
740 * i915_driver_load - setup chip and create an initial config
742 * @flags: startup flags
744 * The driver load routine has to do several things:
745 * - drive output discovery via intel_modeset_init()
746 * - initialize the memory manager
747 * - allocate initial config memory
748 * - setup the DRM framebuffer with the allocated memory
750 int i915_driver_load(struct drm_device *dev, unsigned long flags)
752 struct drm_i915_private *dev_priv = dev->dev_private;
753 struct intel_device_info *info, *device_info;
754 unsigned long base, size;
755 int ret = 0, mmio_bar, mmio_size;
756 uint32_t aperture_size;
758 /* XXX: struct pci_dev */
759 info = i915_get_device_id(dev->pdev->device);
761 dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL);
762 if (dev_priv == NULL)
765 dev->dev_private = dev_priv;
768 /* Setup the write-once "constant" device info */
769 device_info = (struct intel_device_info *)&dev_priv->info;
770 memcpy(device_info, info, sizeof(dev_priv->info));
771 device_info->device_id = dev->pdev->device;
773 lockinit(&dev_priv->irq_lock, "userirq", 0, LK_CANRECURSE);
774 lockinit(&dev_priv->gpu_error.lock, "915err", 0, LK_CANRECURSE);
775 lockinit(&dev_priv->backlight_lock, "i915bl", 0, LK_CANRECURSE);
776 lockinit(&dev_priv->uncore.lock, "915gt", 0, LK_CANRECURSE);
777 spin_init(&dev_priv->mm.object_stat_lock, "i915osl");
778 spin_init(&dev_priv->mmio_flip_lock, "i915mfl");
779 lockinit(&dev_priv->dpio_lock, "i915dpio", 0, LK_CANRECURSE);
780 lockinit(&dev_priv->modeset_restore_lock, "i915mrl", 0, LK_CANRECURSE);
784 intel_display_crc_init(dev);
786 i915_dump_device_info(dev_priv);
788 /* Not all pre-production machines fall into this category, only the
789 * very first ones. Almost everything should work, except for maybe
790 * suspend/resume. And we don't implement workarounds that affect only
791 * pre-production machines. */
792 if (IS_HSW_EARLY_SDV(dev))
793 DRM_INFO("This is an early pre-production Haswell machine. "
794 "It may not be fully functional.\n");
796 if (i915_get_bridge_dev(dev)) {
801 mmio_bar = IS_GEN2(dev) ? 1 : 0;
802 /* Before gen4, the registers and the GTT are behind different BARs.
803 * However, from gen4 onwards, the registers and the GTT are shared
804 * in the same BAR, so we want to restrict this ioremap from
805 * clobbering the GTT which we want ioremap_wc instead. Fortunately,
806 * the register BAR remains the same size for all the earlier
807 * generations up to Ironlake.
810 mmio_size = 512*1024;
812 mmio_size = 2*1024*1024;
814 dev_priv->regs = pci_iomap(dev->pdev, mmio_bar, mmio_size);
815 if (!dev_priv->regs) {
816 DRM_ERROR("failed to map registers\n");
821 base = drm_get_resource_start(dev, mmio_bar);
822 size = drm_get_resource_len(dev, mmio_bar);
824 ret = drm_legacy_addmap(dev, base, size, _DRM_REGISTERS,
825 _DRM_KERNEL | _DRM_DRIVER, &dev_priv->mmio_map);
828 /* This must be called before any calls to HAS_PCH_* */
829 intel_detect_pch(dev);
831 intel_uncore_init(dev);
833 ret = i915_gem_gtt_init(dev);
837 /* WARNING: Apparently we must kick fbdev drivers before vgacon,
838 * otherwise the vga fbdev driver falls over. */
839 ret = i915_kick_out_firmware_fb(dev_priv);
841 DRM_ERROR("failed to remove conflicting framebuffer drivers\n");
845 ret = i915_kick_out_vgacon(dev_priv);
847 DRM_ERROR("failed to remove conflicting VGA console\n");
852 pci_set_master(dev->pdev);
854 /* overlay on gen2 is broken and can't address above 1G */
856 dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(30));
858 /* 965GM sometimes incorrectly writes to hardware status page (HWS)
859 * using 32bit addressing, overwriting memory if HWS is located
862 * The documentation also mentions an issue with undefined
863 * behaviour if any general state is accessed within a page above 4GB,
864 * which also needs to be handled carefully.
866 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
867 dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(32));
870 aperture_size = dev_priv->gtt.mappable_end;
872 dev_priv->gtt.mappable =
873 io_mapping_create_wc(dev_priv->gtt.mappable_base,
875 if (dev_priv->gtt.mappable == NULL) {
880 dev_priv->gtt.mtrr = arch_phys_wc_add(dev_priv->gtt.mappable_base,
883 /* The i915 workqueue is primarily used for batched retirement of
884 * requests (and thus managing bo) once the task has been completed
885 * by the GPU. i915_gem_retire_requests() is called directly when we
886 * need high-priority retirement, such as waiting for an explicit
889 * It is also used for periodic low-priority events, such as
890 * idle-timers and recording error state.
892 * All tasks on the workqueue are expected to acquire the dev mutex
893 * so there is no point in running more than one instance of the
894 * workqueue at any time. Use an ordered one.
896 dev_priv->wq = alloc_ordered_workqueue("i915", 0);
897 if (dev_priv->wq == NULL) {
898 DRM_ERROR("Failed to create our workqueue.\n");
903 dev_priv->dp_wq = alloc_ordered_workqueue("i915-dp", 0);
904 if (dev_priv->dp_wq == NULL) {
905 DRM_ERROR("Failed to create our dp workqueue.\n");
910 dev_priv->gpu_error.hangcheck_wq =
911 alloc_ordered_workqueue("i915-hangcheck", 0);
912 if (dev_priv->gpu_error.hangcheck_wq == NULL) {
913 DRM_ERROR("Failed to create our hangcheck workqueue.\n");
918 intel_irq_init(dev_priv);
919 intel_uncore_sanitize(dev);
921 /* Try to make sure MCHBAR is enabled before poking at it */
922 intel_setup_mchbar(dev);
923 intel_setup_gmbus(dev);
924 intel_opregion_setup(dev);
926 intel_setup_bios(dev);
930 /* On the 945G/GM, the chipset reports the MSI capability on the
931 * integrated graphics even though the support isn't actually there
932 * according to the published specs. It doesn't appear to function
933 * correctly in testing on 945G.
934 * This may be a side effect of MSI having been made available for PEG
935 * and the registers being closely associated.
937 * According to chipset errata, on the 965GM, MSI interrupts may
938 * be lost or delayed, but we use them anyways to avoid
939 * stuck interrupts on some machines.
942 if (!IS_I945G(dev) && !IS_I945GM(dev))
943 pci_enable_msi(dev->pdev);
946 intel_device_info_runtime_init(dev);
948 if (INTEL_INFO(dev)->num_pipes) {
949 ret = drm_vblank_init(dev, INTEL_INFO(dev)->num_pipes);
954 intel_power_domains_init(dev_priv);
956 ret = i915_load_modeset_init(dev);
958 DRM_ERROR("failed to init modeset\n");
963 * Notify a valid surface after modesetting,
964 * when running inside a VM.
966 if (intel_vgpu_active(dev))
967 I915_WRITE(vgtif_reg(display_ready), VGT_DRV_DISPLAY_READY);
969 i915_setup_sysfs(dev);
971 if (INTEL_INFO(dev)->num_pipes) {
972 /* Must be done after probing outputs */
973 intel_opregion_init(dev);
975 acpi_video_register();
980 intel_gpu_ips_init(dev_priv);
982 intel_runtime_pm_enable(dev_priv);
984 i915_audio_component_init(dev_priv);
989 intel_power_domains_fini(dev_priv);
990 drm_vblank_cleanup(dev);
993 intel_teardown_gmbus(dev);
994 intel_teardown_mchbar(dev);
995 pm_qos_remove_request(&dev_priv->pm_qos);
996 destroy_workqueue(dev_priv->gpu_error.hangcheck_wq);
998 destroy_workqueue(dev_priv->dp_wq);
1000 destroy_workqueue(dev_priv->wq);
1002 arch_phys_wc_del(dev_priv->gtt.mtrr);
1004 io_mapping_free(dev_priv->gtt.mappable);
1007 i915_global_gtt_cleanup(dev);
1009 intel_uncore_fini(dev);
1011 pci_iounmap(dev->pdev, dev_priv->regs);
1014 pci_dev_put(dev_priv->bridge_dev);
1020 int i915_driver_unload(struct drm_device *dev)
1022 struct drm_i915_private *dev_priv = dev->dev_private;
1025 i915_audio_component_cleanup(dev_priv);
1027 ret = i915_gem_suspend(dev);
1029 DRM_ERROR("failed to idle hardware: %d\n", ret);
1033 intel_power_domains_fini(dev_priv);
1035 intel_gpu_ips_teardown();
1037 i915_teardown_sysfs(dev);
1040 WARN_ON(unregister_oom_notifier(&dev_priv->mm.oom_notifier));
1041 unregister_shrinker(&dev_priv->mm.shrinker);
1043 io_mapping_free(dev_priv->gtt.mappable);
1045 arch_phys_wc_del(dev_priv->gtt.mtrr);
1048 acpi_video_unregister();
1051 intel_fbdev_fini(dev);
1053 drm_vblank_cleanup(dev);
1055 intel_modeset_cleanup(dev);
1058 * free the memory space allocated for the child device
1059 * config parsed from VBT
1061 if (dev_priv->vbt.child_dev && dev_priv->vbt.child_dev_num) {
1062 kfree(dev_priv->vbt.child_dev);
1063 dev_priv->vbt.child_dev = NULL;
1064 dev_priv->vbt.child_dev_num = 0;
1068 vga_switcheroo_unregister_client(dev->pdev);
1069 vga_client_register(dev->pdev, NULL, NULL, NULL);
1072 /* Free error state after interrupts are fully disabled. */
1073 cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work);
1075 i915_destroy_error_state(dev);
1077 if (dev->pdev->msi_enabled)
1078 pci_disable_msi(dev->pdev);
1081 intel_opregion_fini(dev);
1083 /* Flush any outstanding unpin_work. */
1084 flush_workqueue(dev_priv->wq);
1086 mutex_lock(&dev->struct_mutex);
1087 i915_gem_cleanup_ringbuffer(dev);
1088 i915_gem_batch_pool_fini(&dev_priv->mm.batch_pool);
1089 i915_gem_context_fini(dev);
1090 mutex_unlock(&dev->struct_mutex);
1092 i915_gem_cleanup_stolen(dev);
1095 intel_teardown_gmbus(dev);
1096 intel_teardown_mchbar(dev);
1098 destroy_workqueue(dev_priv->dp_wq);
1099 destroy_workqueue(dev_priv->wq);
1100 destroy_workqueue(dev_priv->gpu_error.hangcheck_wq);
1101 pm_qos_remove_request(&dev_priv->pm_qos);
1103 i915_global_gtt_cleanup(dev);
1105 intel_uncore_fini(dev);
1107 if (dev_priv->regs != NULL)
1108 pci_iounmap(dev->pdev, dev_priv->regs);
1111 kmem_cache_destroy(dev_priv->slab);
1114 pci_dev_put(dev_priv->bridge_dev);
1120 int i915_driver_open(struct drm_device *dev, struct drm_file *file)
1124 ret = i915_gem_open(dev, file);
1132 * i915_driver_lastclose - clean up after all DRM clients have exited
1135 * Take care of cleaning up after all DRM clients have exited. In the
1136 * mode setting case, we want to restore the kernel's initial mode (just
1137 * in case the last client left us in a bad state).
1139 * Additionally, in the non-mode setting case, we'll tear down the GTT
1140 * and DMA structures, since the kernel won't be using them, and clea
1143 void i915_driver_lastclose(struct drm_device *dev)
1145 intel_fbdev_restore_mode(dev);
1147 vga_switcheroo_process_delayed_switch();
1151 void i915_driver_preclose(struct drm_device *dev, struct drm_file *file)
1153 mutex_lock(&dev->struct_mutex);
1154 i915_gem_context_close(dev, file);
1155 i915_gem_release(dev, file);
1156 mutex_unlock(&dev->struct_mutex);
1158 intel_modeset_preclose(dev, file);
1161 void i915_driver_postclose(struct drm_device *dev, struct drm_file *file)
1163 struct drm_i915_file_private *file_priv = file->driver_priv;
1165 if (file_priv && file_priv->bsd_ring)
1166 file_priv->bsd_ring = NULL;
1171 i915_gem_reject_pin_ioctl(struct drm_device *dev, void *data,
1172 struct drm_file *file)
1177 const struct drm_ioctl_desc i915_ioctls[] = {
1178 DRM_IOCTL_DEF_DRV(I915_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1179 DRM_IOCTL_DEF_DRV(I915_FLUSH, drm_noop, DRM_AUTH),
1180 DRM_IOCTL_DEF_DRV(I915_FLIP, drm_noop, DRM_AUTH),
1181 DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, drm_noop, DRM_AUTH),
1182 DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, drm_noop, DRM_AUTH),
1183 DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, drm_noop, DRM_AUTH),
1184 DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam, DRM_AUTH|DRM_RENDER_ALLOW),
1185 DRM_IOCTL_DEF_DRV(I915_SETPARAM, i915_setparam, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1186 DRM_IOCTL_DEF_DRV(I915_ALLOC, drm_noop, DRM_AUTH),
1187 DRM_IOCTL_DEF_DRV(I915_FREE, drm_noop, DRM_AUTH),
1188 DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1189 DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, drm_noop, DRM_AUTH),
1190 DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1191 DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1192 DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE, drm_noop, DRM_AUTH),
1193 DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, drm_noop, DRM_AUTH),
1194 DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1195 DRM_IOCTL_DEF_DRV(I915_GEM_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
1196 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH|DRM_UNLOCKED),
1197 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2, i915_gem_execbuffer2, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
1198 DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED),
1199 DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED),
1200 DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
1201 DRM_IOCTL_DEF_DRV(I915_GEM_SET_CACHING, i915_gem_set_caching_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1202 DRM_IOCTL_DEF_DRV(I915_GEM_GET_CACHING, i915_gem_get_caching_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1203 DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
1204 DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
1205 DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
1206 DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1207 DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1208 DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1209 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1210 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1211 DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1212 DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1213 DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1214 DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1215 DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1216 DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id, DRM_UNLOCKED),
1217 DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1218 DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
1219 DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
1220 DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
1221 DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, drm_noop, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
1222 DRM_IOCTL_DEF_DRV(I915_GEM_WAIT, i915_gem_wait_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
1223 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE, i915_gem_context_create_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1224 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY, i915_gem_context_destroy_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1225 DRM_IOCTL_DEF_DRV(I915_REG_READ, i915_reg_read_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1226 DRM_IOCTL_DEF_DRV(I915_GET_RESET_STATS, i915_get_reset_stats_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1228 DRM_IOCTL_DEF_DRV(I915_GEM_USERPTR, i915_gem_userptr_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1230 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_GETPARAM, i915_gem_context_getparam_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1231 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_SETPARAM, i915_gem_context_setparam_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1234 int i915_max_ioctl = ARRAY_SIZE(i915_ioctls);
1237 * This is really ugly: Because old userspace abused the linux agp interface to
1238 * manage the gtt, we need to claim that all intel devices are agp. For
1239 * otherwise the drm core refuses to initialize the agp support code.
1241 int i915_driver_device_is_agp(struct drm_device *dev)