2 * Copyright (c) 1997, 1998
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
32 * $FreeBSD: src/sys/pci/if_tl.c,v 1.51.2.5 2001/12/16 15:46:08 luigi Exp $
33 * $DragonFly: src/sys/dev/netif/tl/if_tl.c,v 1.15 2005/02/20 03:04:51 joerg Exp $
35 * $FreeBSD: src/sys/pci/if_tl.c,v 1.51.2.5 2001/12/16 15:46:08 luigi Exp $
39 * Texas Instruments ThunderLAN driver for FreeBSD 2.2.6 and 3.x.
40 * Supports many Compaq PCI NICs based on the ThunderLAN ethernet controller,
41 * the National Semiconductor DP83840A physical interface and the
42 * Microchip Technology 24Cxx series serial EEPROM.
44 * Written using the following four documents:
46 * Texas Instruments ThunderLAN Programmer's Guide (www.ti.com)
47 * National Semiconductor DP83840A data sheet (www.national.com)
48 * Microchip Technology 24C02C data sheet (www.microchip.com)
49 * Micro Linear ML6692 100BaseTX only PHY data sheet (www.microlinear.com)
51 * Written by Bill Paul <wpaul@ctr.columbia.edu>
52 * Electrical Engineering Department
53 * Columbia University, New York City
57 * Some notes about the ThunderLAN:
59 * The ThunderLAN controller is a single chip containing PCI controller
60 * logic, approximately 3K of on-board SRAM, a LAN controller, and media
61 * independent interface (MII) bus. The MII allows the ThunderLAN chip to
62 * control up to 32 different physical interfaces (PHYs). The ThunderLAN
63 * also has a built-in 10baseT PHY, allowing a single ThunderLAN controller
64 * to act as a complete ethernet interface.
66 * Other PHYs may be attached to the ThunderLAN; the Compaq 10/100 cards
67 * use a National Semiconductor DP83840A PHY that supports 10 or 100Mb/sec
68 * in full or half duplex. Some of the Compaq Deskpro machines use a
69 * Level 1 LXT970 PHY with the same capabilities. Certain Olicom adapters
70 * use a Micro Linear ML6692 100BaseTX only PHY, which can be used in
71 * concert with the ThunderLAN's internal PHY to provide full 10/100
72 * support. This is cheaper than using a standalone external PHY for both
73 * 10/100 modes and letting the ThunderLAN's internal PHY go to waste.
74 * A serial EEPROM is also attached to the ThunderLAN chip to provide
75 * power-up default register settings and for storing the adapter's
76 * station address. Although not supported by this driver, the ThunderLAN
77 * chip can also be connected to token ring PHYs.
79 * The ThunderLAN has a set of registers which can be used to issue
80 * commands, acknowledge interrupts, and to manipulate other internal
81 * registers on its DIO bus. The primary registers can be accessed
82 * using either programmed I/O (inb/outb) or via PCI memory mapping,
83 * depending on how the card is configured during the PCI probing
84 * phase. It is even possible to have both PIO and memory mapped
85 * access turned on at the same time.
87 * Frame reception and transmission with the ThunderLAN chip is done
88 * using frame 'lists.' A list structure looks more or less like this:
91 * u_int32_t fragment_address;
92 * u_int32_t fragment_size;
95 * u_int32_t forward_pointer;
97 * u_int16_t frame_size;
98 * struct tl_frag fragments[10];
101 * The forward pointer in the list header can be either a 0 or the address
102 * of another list, which allows several lists to be linked together. Each
103 * list contains up to 10 fragment descriptors. This means the chip allows
104 * ethernet frames to be broken up into up to 10 chunks for transfer to
105 * and from the SRAM. Note that the forward pointer and fragment buffer
106 * addresses are physical memory addresses, not virtual. Note also that
107 * a single ethernet frame can not span lists: if the host wants to
108 * transmit a frame and the frame data is split up over more than 10
109 * buffers, the frame has to collapsed before it can be transmitted.
111 * To receive frames, the driver sets up a number of lists and populates
112 * the fragment descriptors, then it sends an RX GO command to the chip.
113 * When a frame is received, the chip will DMA it into the memory regions
114 * specified by the fragment descriptors and then trigger an RX 'end of
115 * frame interrupt' when done. The driver may choose to use only one
116 * fragment per list; this may result is slighltly less efficient use
117 * of memory in exchange for improving performance.
119 * To transmit frames, the driver again sets up lists and fragment
120 * descriptors, only this time the buffers contain frame data that
121 * is to be DMA'ed into the chip instead of out of it. Once the chip
122 * has transfered the data into its on-board SRAM, it will trigger a
123 * TX 'end of frame' interrupt. It will also generate an 'end of channel'
124 * interrupt when it reaches the end of the list.
128 * Some notes about this driver:
130 * The ThunderLAN chip provides a couple of different ways to organize
131 * reception, transmission and interrupt handling. The simplest approach
132 * is to use one list each for transmission and reception. In this mode,
133 * the ThunderLAN will generate two interrupts for every received frame
134 * (one RX EOF and one RX EOC) and two for each transmitted frame (one
135 * TX EOF and one TX EOC). This may make the driver simpler but it hurts
136 * performance to have to handle so many interrupts.
138 * Initially I wanted to create a circular list of receive buffers so
139 * that the ThunderLAN chip would think there was an infinitely long
140 * receive channel and never deliver an RXEOC interrupt. However this
141 * doesn't work correctly under heavy load: while the manual says the
142 * chip will trigger an RXEOF interrupt each time a frame is copied into
143 * memory, you can't count on the chip waiting around for you to acknowledge
144 * the interrupt before it starts trying to DMA the next frame. The result
145 * is that the chip might traverse the entire circular list and then wrap
146 * around before you have a chance to do anything about it. Consequently,
147 * the receive list is terminated (with a 0 in the forward pointer in the
148 * last element). Each time an RXEOF interrupt arrives, the used list
149 * is shifted to the end of the list. This gives the appearance of an
150 * infinitely large RX chain so long as the driver doesn't fall behind
151 * the chip and allow all of the lists to be filled up.
153 * If all the lists are filled, the adapter will deliver an RX 'end of
154 * channel' interrupt when it hits the 0 forward pointer at the end of
155 * the chain. The RXEOC handler then cleans out the RX chain and resets
156 * the list head pointer in the ch_parm register and restarts the receiver.
158 * For frame transmission, it is possible to program the ThunderLAN's
159 * transmit interrupt threshold so that the chip can acknowledge multiple
160 * lists with only a single TX EOF interrupt. This allows the driver to
161 * queue several frames in one shot, and only have to handle a total
162 * two interrupts (one TX EOF and one TX EOC) no matter how many frames
163 * are transmitted. Frame transmission is done directly out of the
164 * mbufs passed to the tl_start() routine via the interface send queue.
165 * The driver simply sets up the fragment descriptors in the transmit
166 * lists to point to the mbuf data regions and sends a TX GO command.
168 * Note that since the RX and TX lists themselves are always used
169 * only by the driver, the are malloc()ed once at driver initialization
170 * time and never free()ed.
172 * Also, in order to remain as platform independent as possible, this
173 * driver uses memory mapped register access to manipulate the card
174 * as opposed to programmed I/O. This avoids the use of the inb/outb
175 * (and related) instructions which are specific to the i386 platform.
177 * Using these techniques, this driver achieves very high performance
178 * by minimizing the amount of interrupts generated during large
179 * transfers and by completely avoiding buffer copies. Frame transfer
180 * to and from the ThunderLAN chip is performed entirely by the chip
181 * itself thereby reducing the load on the host CPU.
184 #include <sys/param.h>
185 #include <sys/systm.h>
186 #include <sys/sockio.h>
187 #include <sys/mbuf.h>
188 #include <sys/malloc.h>
189 #include <sys/kernel.h>
190 #include <sys/socket.h>
193 #include <net/ifq_var.h>
194 #include <net/if_arp.h>
195 #include <net/ethernet.h>
196 #include <net/if_dl.h>
197 #include <net/if_media.h>
201 #include <vm/vm.h> /* for vtophys */
202 #include <vm/pmap.h> /* for vtophys */
203 #include <machine/clock.h> /* for DELAY */
204 #include <machine/bus_memio.h>
205 #include <machine/bus_pio.h>
206 #include <machine/bus.h>
207 #include <machine/resource.h>
209 #include <sys/rman.h>
211 #include "../mii_layer/mii.h"
212 #include "../mii_layer/miivar.h"
214 #include <bus/pci/pcireg.h>
215 #include <bus/pci/pcivar.h>
218 * Default to using PIO register access mode to pacify certain
219 * laptop docking stations with built-in ThunderLAN chips that
220 * don't seem to handle memory mapped mode properly.
222 #define TL_USEIOSPACE
224 #include "if_tlreg.h"
226 /* "controller miibus0" required. See GENERIC if you get errors here. */
227 #include "miibus_if.h"
230 * Various supported device vendors/types and their names.
233 static struct tl_type tl_devs[] = {
234 { TI_VENDORID, TI_DEVICEID_THUNDERLAN,
235 "Texas Instruments ThunderLAN" },
236 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10,
237 "Compaq Netelligent 10" },
238 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_100,
239 "Compaq Netelligent 10/100" },
240 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_100_PROLIANT,
241 "Compaq Netelligent 10/100 Proliant" },
242 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_100_DUAL,
243 "Compaq Netelligent 10/100 Dual Port" },
244 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETFLEX_3P_INTEGRATED,
245 "Compaq NetFlex-3/P Integrated" },
246 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETFLEX_3P,
247 "Compaq NetFlex-3/P" },
248 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETFLEX_3P_BNC,
249 "Compaq NetFlex 3/P w/ BNC" },
250 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_100_EMBEDDED,
251 "Compaq Netelligent 10/100 TX Embedded UTP" },
252 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_T2_UTP_COAX,
253 "Compaq Netelligent 10 T/2 PCI UTP/Coax" },
254 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_100_TX_UTP,
255 "Compaq Netelligent 10/100 TX UTP" },
256 { OLICOM_VENDORID, OLICOM_DEVICEID_OC2183,
257 "Olicom OC-2183/2185" },
258 { OLICOM_VENDORID, OLICOM_DEVICEID_OC2325,
260 { OLICOM_VENDORID, OLICOM_DEVICEID_OC2326,
261 "Olicom OC-2326 10/100 TX UTP" },
265 static int tl_probe (device_t);
266 static int tl_attach (device_t);
267 static int tl_detach (device_t);
268 static int tl_intvec_rxeoc (void *, u_int32_t);
269 static int tl_intvec_txeoc (void *, u_int32_t);
270 static int tl_intvec_txeof (void *, u_int32_t);
271 static int tl_intvec_rxeof (void *, u_int32_t);
272 static int tl_intvec_adchk (void *, u_int32_t);
273 static int tl_intvec_netsts (void *, u_int32_t);
275 static int tl_newbuf (struct tl_softc *,
276 struct tl_chain_onefrag *);
277 static void tl_stats_update (void *);
278 static int tl_encap (struct tl_softc *, struct tl_chain *,
281 static void tl_intr (void *);
282 static void tl_start (struct ifnet *);
283 static int tl_ioctl (struct ifnet *, u_long, caddr_t,
285 static void tl_init (void *);
286 static void tl_stop (struct tl_softc *);
287 static void tl_watchdog (struct ifnet *);
288 static void tl_shutdown (device_t);
289 static int tl_ifmedia_upd (struct ifnet *);
290 static void tl_ifmedia_sts (struct ifnet *, struct ifmediareq *);
292 static u_int8_t tl_eeprom_putbyte (struct tl_softc *, int);
293 static u_int8_t tl_eeprom_getbyte (struct tl_softc *,
295 static int tl_read_eeprom (struct tl_softc *, caddr_t, int, int);
297 static void tl_mii_sync (struct tl_softc *);
298 static void tl_mii_send (struct tl_softc *, u_int32_t, int);
299 static int tl_mii_readreg (struct tl_softc *, struct tl_mii_frame *);
300 static int tl_mii_writereg (struct tl_softc *, struct tl_mii_frame *);
301 static int tl_miibus_readreg (device_t, int, int);
302 static int tl_miibus_writereg (device_t, int, int, int);
303 static void tl_miibus_statchg (device_t);
305 static void tl_setmode (struct tl_softc *, int);
306 static int tl_calchash (caddr_t);
307 static void tl_setmulti (struct tl_softc *);
308 static void tl_setfilt (struct tl_softc *, caddr_t, int);
309 static void tl_softreset (struct tl_softc *, int);
310 static void tl_hardreset (device_t);
311 static int tl_list_rx_init (struct tl_softc *);
312 static int tl_list_tx_init (struct tl_softc *);
314 static u_int8_t tl_dio_read8 (struct tl_softc *, int);
315 static u_int16_t tl_dio_read16 (struct tl_softc *, int);
316 static u_int32_t tl_dio_read32 (struct tl_softc *, int);
317 static void tl_dio_write8 (struct tl_softc *, int, int);
318 static void tl_dio_write16 (struct tl_softc *, int, int);
319 static void tl_dio_write32 (struct tl_softc *, int, int);
320 static void tl_dio_setbit (struct tl_softc *, int, int);
321 static void tl_dio_clrbit (struct tl_softc *, int, int);
322 static void tl_dio_setbit16 (struct tl_softc *, int, int);
323 static void tl_dio_clrbit16 (struct tl_softc *, int, int);
326 #define TL_RES SYS_RES_IOPORT
327 #define TL_RID TL_PCI_LOIO
329 #define TL_RES SYS_RES_MEMORY
330 #define TL_RID TL_PCI_LOMEM
333 static device_method_t tl_methods[] = {
334 /* Device interface */
335 DEVMETHOD(device_probe, tl_probe),
336 DEVMETHOD(device_attach, tl_attach),
337 DEVMETHOD(device_detach, tl_detach),
338 DEVMETHOD(device_shutdown, tl_shutdown),
341 DEVMETHOD(bus_print_child, bus_generic_print_child),
342 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
345 DEVMETHOD(miibus_readreg, tl_miibus_readreg),
346 DEVMETHOD(miibus_writereg, tl_miibus_writereg),
347 DEVMETHOD(miibus_statchg, tl_miibus_statchg),
352 static driver_t tl_driver = {
355 sizeof(struct tl_softc)
358 static devclass_t tl_devclass;
360 DECLARE_DUMMY_MODULE(if_tl);
361 DRIVER_MODULE(if_tl, pci, tl_driver, tl_devclass, 0, 0);
362 DRIVER_MODULE(miibus, tl, miibus_driver, miibus_devclass, 0, 0);
364 static u_int8_t tl_dio_read8(sc, reg)
368 CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
369 return(CSR_READ_1(sc, TL_DIO_DATA + (reg & 3)));
372 static u_int16_t tl_dio_read16(sc, reg)
376 CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
377 return(CSR_READ_2(sc, TL_DIO_DATA + (reg & 3)));
380 static u_int32_t tl_dio_read32(sc, reg)
384 CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
385 return(CSR_READ_4(sc, TL_DIO_DATA + (reg & 3)));
388 static void tl_dio_write8(sc, reg, val)
393 CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
394 CSR_WRITE_1(sc, TL_DIO_DATA + (reg & 3), val);
398 static void tl_dio_write16(sc, reg, val)
403 CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
404 CSR_WRITE_2(sc, TL_DIO_DATA + (reg & 3), val);
408 static void tl_dio_write32(sc, reg, val)
413 CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
414 CSR_WRITE_4(sc, TL_DIO_DATA + (reg & 3), val);
418 static void tl_dio_setbit(sc, reg, bit)
425 CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
426 f = CSR_READ_1(sc, TL_DIO_DATA + (reg & 3));
428 CSR_WRITE_1(sc, TL_DIO_DATA + (reg & 3), f);
433 static void tl_dio_clrbit(sc, reg, bit)
440 CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
441 f = CSR_READ_1(sc, TL_DIO_DATA + (reg & 3));
443 CSR_WRITE_1(sc, TL_DIO_DATA + (reg & 3), f);
448 static void tl_dio_setbit16(sc, reg, bit)
455 CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
456 f = CSR_READ_2(sc, TL_DIO_DATA + (reg & 3));
458 CSR_WRITE_2(sc, TL_DIO_DATA + (reg & 3), f);
463 static void tl_dio_clrbit16(sc, reg, bit)
470 CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
471 f = CSR_READ_2(sc, TL_DIO_DATA + (reg & 3));
473 CSR_WRITE_2(sc, TL_DIO_DATA + (reg & 3), f);
479 * Send an instruction or address to the EEPROM, check for ACK.
481 static u_int8_t tl_eeprom_putbyte(sc, byte)
488 * Make sure we're in TX mode.
490 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_ETXEN);
493 * Feed in each bit and stobe the clock.
495 for (i = 0x80; i; i >>= 1) {
497 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_EDATA);
499 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_EDATA);
502 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_ECLOK);
504 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ECLOK);
510 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ETXEN);
515 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_ECLOK);
516 ack = tl_dio_read8(sc, TL_NETSIO) & TL_SIO_EDATA;
517 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ECLOK);
523 * Read a byte of data stored in the EEPROM at address 'addr.'
525 static u_int8_t tl_eeprom_getbyte(sc, addr, dest)
533 tl_dio_write8(sc, TL_NETSIO, 0);
538 * Send write control code to EEPROM.
540 if (tl_eeprom_putbyte(sc, EEPROM_CTL_WRITE)) {
541 printf("tl%d: failed to send write command, status: %x\n",
542 sc->tl_unit, tl_dio_read8(sc, TL_NETSIO));
547 * Send address of byte we want to read.
549 if (tl_eeprom_putbyte(sc, addr)) {
550 printf("tl%d: failed to send address, status: %x\n",
551 sc->tl_unit, tl_dio_read8(sc, TL_NETSIO));
558 * Send read control code to EEPROM.
560 if (tl_eeprom_putbyte(sc, EEPROM_CTL_READ)) {
561 printf("tl%d: failed to send write command, status: %x\n",
562 sc->tl_unit, tl_dio_read8(sc, TL_NETSIO));
567 * Start reading bits from EEPROM.
569 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ETXEN);
570 for (i = 0x80; i; i >>= 1) {
571 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_ECLOK);
573 if (tl_dio_read8(sc, TL_NETSIO) & TL_SIO_EDATA)
575 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ECLOK);
582 * No ACK generated for read, so just return byte.
591 * Read a sequence of bytes from the EEPROM.
593 static int tl_read_eeprom(sc, dest, off, cnt)
602 for (i = 0; i < cnt; i++) {
603 err = tl_eeprom_getbyte(sc, off + i, &byte);
612 static void tl_mii_sync(sc)
617 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MTXEN);
619 for (i = 0; i < 32; i++) {
620 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK);
621 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK);
627 static void tl_mii_send(sc, bits, cnt)
634 for (i = (0x1 << (cnt - 1)); i; i >>= 1) {
635 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK);
637 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MDATA);
639 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MDATA);
641 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK);
645 static int tl_mii_readreg(sc, frame)
647 struct tl_mii_frame *frame;
658 * Set up frame for RX.
660 frame->mii_stdelim = TL_MII_STARTDELIM;
661 frame->mii_opcode = TL_MII_READOP;
662 frame->mii_turnaround = 0;
666 * Turn off MII interrupt by forcing MINTEN low.
668 minten = tl_dio_read8(sc, TL_NETSIO) & TL_SIO_MINTEN;
670 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MINTEN);
676 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MTXEN);
679 * Send command/address info.
681 tl_mii_send(sc, frame->mii_stdelim, 2);
682 tl_mii_send(sc, frame->mii_opcode, 2);
683 tl_mii_send(sc, frame->mii_phyaddr, 5);
684 tl_mii_send(sc, frame->mii_regaddr, 5);
689 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MTXEN);
692 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK);
693 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK);
696 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK);
697 ack = tl_dio_read8(sc, TL_NETSIO) & TL_SIO_MDATA;
699 /* Complete the cycle */
700 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK);
703 * Now try reading data bits. If the ack failed, we still
704 * need to clock through 16 cycles to keep the PHYs in sync.
707 for(i = 0; i < 16; i++) {
708 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK);
709 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK);
714 for (i = 0x8000; i; i >>= 1) {
715 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK);
717 if (tl_dio_read8(sc, TL_NETSIO) & TL_SIO_MDATA)
718 frame->mii_data |= i;
720 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK);
725 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK);
726 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK);
728 /* Reenable interrupts */
730 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MINTEN);
740 static int tl_mii_writereg(sc, frame)
742 struct tl_mii_frame *frame;
752 * Set up frame for TX.
755 frame->mii_stdelim = TL_MII_STARTDELIM;
756 frame->mii_opcode = TL_MII_WRITEOP;
757 frame->mii_turnaround = TL_MII_TURNAROUND;
760 * Turn off MII interrupt by forcing MINTEN low.
762 minten = tl_dio_read8(sc, TL_NETSIO) & TL_SIO_MINTEN;
764 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MINTEN);
768 * Turn on data output.
770 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MTXEN);
772 tl_mii_send(sc, frame->mii_stdelim, 2);
773 tl_mii_send(sc, frame->mii_opcode, 2);
774 tl_mii_send(sc, frame->mii_phyaddr, 5);
775 tl_mii_send(sc, frame->mii_regaddr, 5);
776 tl_mii_send(sc, frame->mii_turnaround, 2);
777 tl_mii_send(sc, frame->mii_data, 16);
779 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK);
780 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK);
785 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MTXEN);
787 /* Reenable interrupts */
789 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MINTEN);
796 static int tl_miibus_readreg(dev, phy, reg)
801 struct tl_mii_frame frame;
803 sc = device_get_softc(dev);
804 bzero((char *)&frame, sizeof(frame));
806 frame.mii_phyaddr = phy;
807 frame.mii_regaddr = reg;
808 tl_mii_readreg(sc, &frame);
810 return(frame.mii_data);
813 static int tl_miibus_writereg(dev, phy, reg, data)
818 struct tl_mii_frame frame;
820 sc = device_get_softc(dev);
821 bzero((char *)&frame, sizeof(frame));
823 frame.mii_phyaddr = phy;
824 frame.mii_regaddr = reg;
825 frame.mii_data = data;
827 tl_mii_writereg(sc, &frame);
832 static void tl_miibus_statchg(dev)
836 struct mii_data *mii;
838 sc = device_get_softc(dev);
839 mii = device_get_softc(sc->tl_miibus);
841 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
842 tl_dio_setbit(sc, TL_NETCMD, TL_CMD_DUPLEX);
844 tl_dio_clrbit(sc, TL_NETCMD, TL_CMD_DUPLEX);
851 * Set modes for bitrate devices.
853 static void tl_setmode(sc, media)
857 if (IFM_SUBTYPE(media) == IFM_10_5)
858 tl_dio_setbit(sc, TL_ACOMMIT, TL_AC_MTXD1);
859 if (IFM_SUBTYPE(media) == IFM_10_T) {
860 tl_dio_clrbit(sc, TL_ACOMMIT, TL_AC_MTXD1);
861 if ((media & IFM_GMASK) == IFM_FDX) {
862 tl_dio_clrbit(sc, TL_ACOMMIT, TL_AC_MTXD3);
863 tl_dio_setbit(sc, TL_NETCMD, TL_CMD_DUPLEX);
865 tl_dio_setbit(sc, TL_ACOMMIT, TL_AC_MTXD3);
866 tl_dio_clrbit(sc, TL_NETCMD, TL_CMD_DUPLEX);
874 * Calculate the hash of a MAC address for programming the multicast hash
875 * table. This hash is simply the address split into 6-bit chunks
877 * byte: 000000|00 1111|1111 22|222222|333333|33 4444|4444 55|555555
878 * bit: 765432|10 7654|3210 76|543210|765432|10 7654|3210 76|543210
879 * Bytes 0-2 and 3-5 are symmetrical, so are folded together. Then
880 * the folded 24-bit value is split into 6-bit portions and XOR'd.
882 static int tl_calchash(addr)
887 t = (addr[0] ^ addr[3]) << 16 | (addr[1] ^ addr[4]) << 8 |
889 return ((t >> 18) ^ (t >> 12) ^ (t >> 6) ^ t) & 0x3f;
893 * The ThunderLAN has a perfect MAC address filter in addition to
894 * the multicast hash filter. The perfect filter can be programmed
895 * with up to four MAC addresses. The first one is always used to
896 * hold the station address, which leaves us free to use the other
897 * three for multicast addresses.
899 static void tl_setfilt(sc, addr, slot)
907 regaddr = TL_AREG0_B5 + (slot * ETHER_ADDR_LEN);
909 for (i = 0; i < ETHER_ADDR_LEN; i++)
910 tl_dio_write8(sc, regaddr + i, *(addr + i));
916 * XXX In FreeBSD 3.0, multicast addresses are managed using a doubly
917 * linked list. This is fine, except addresses are added from the head
918 * end of the list. We want to arrange for 224.0.0.1 (the "all hosts")
919 * group to always be in the perfect filter, but as more groups are added,
920 * the 224.0.0.1 entry (which is always added first) gets pushed down
921 * the list and ends up at the tail. So after 3 or 4 multicast groups
922 * are added, the all-hosts entry gets pushed out of the perfect filter
923 * and into the hash table.
925 * Because the multicast list is a doubly-linked list as opposed to a
926 * circular queue, we don't have the ability to just grab the tail of
927 * the list and traverse it backwards. Instead, we have to traverse
928 * the list once to find the tail, then traverse it again backwards to
929 * update the multicast filter.
931 static void tl_setmulti(sc)
935 u_int32_t hashes[2] = { 0, 0 };
937 struct ifmultiaddr *ifma;
938 u_int8_t dummy[] = { 0, 0, 0, 0, 0 ,0 };
939 ifp = &sc->arpcom.ac_if;
941 /* First, zot all the existing filters. */
942 for (i = 1; i < 4; i++)
943 tl_setfilt(sc, (caddr_t)&dummy, i);
944 tl_dio_write32(sc, TL_HASH1, 0);
945 tl_dio_write32(sc, TL_HASH2, 0);
947 /* Now program new ones. */
948 if (ifp->if_flags & IFF_ALLMULTI) {
949 hashes[0] = 0xFFFFFFFF;
950 hashes[1] = 0xFFFFFFFF;
953 /* First find the tail of the list. */
954 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL;
955 ifma = ifma->ifma_link.le_next) {
956 if (ifma->ifma_link.le_next == NULL)
959 /* Now traverse the list backwards. */
960 for (; ifma != NULL && ifma != (void *)&ifp->if_multiaddrs;
961 ifma = (struct ifmultiaddr *)ifma->ifma_link.le_prev) {
962 if (ifma->ifma_addr->sa_family != AF_LINK)
965 * Program the first three multicast groups
966 * into the perfect filter. For all others,
967 * use the hash table.
971 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), i);
977 LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
979 hashes[0] |= (1 << h);
981 hashes[1] |= (1 << (h - 32));
985 tl_dio_write32(sc, TL_HASH1, hashes[0]);
986 tl_dio_write32(sc, TL_HASH2, hashes[1]);
992 * This routine is recommended by the ThunderLAN manual to insure that
993 * the internal PHY is powered up correctly. It also recommends a one
994 * second pause at the end to 'wait for the clocks to start' but in my
995 * experience this isn't necessary.
997 static void tl_hardreset(dev)
1000 struct tl_softc *sc;
1004 sc = device_get_softc(dev);
1008 flags = BMCR_LOOP|BMCR_ISO|BMCR_PDOWN;
1010 for (i = 0; i < MII_NPHY; i++)
1011 tl_miibus_writereg(dev, i, MII_BMCR, flags);
1013 tl_miibus_writereg(dev, 31, MII_BMCR, BMCR_ISO);
1015 tl_miibus_writereg(dev, 31, MII_BMCR, BMCR_LOOP|BMCR_ISO);
1017 while(tl_miibus_readreg(dev, 31, MII_BMCR) & BMCR_RESET);
1023 static void tl_softreset(sc, internal)
1024 struct tl_softc *sc;
1027 u_int32_t cmd, dummy, i;
1029 /* Assert the adapter reset bit. */
1030 CMD_SET(sc, TL_CMD_ADRST);
1032 /* Turn off interrupts */
1033 CMD_SET(sc, TL_CMD_INTSOFF);
1035 /* First, clear the stats registers. */
1036 for (i = 0; i < 5; i++)
1037 dummy = tl_dio_read32(sc, TL_TXGOODFRAMES);
1039 /* Clear Areg and Hash registers */
1040 for (i = 0; i < 8; i++)
1041 tl_dio_write32(sc, TL_AREG0_B5, 0x00000000);
1044 * Set up Netconfig register. Enable one channel and
1045 * one fragment mode.
1047 tl_dio_setbit16(sc, TL_NETCONFIG, TL_CFG_ONECHAN|TL_CFG_ONEFRAG);
1048 if (internal && !sc->tl_bitrate) {
1049 tl_dio_setbit16(sc, TL_NETCONFIG, TL_CFG_PHYEN);
1051 tl_dio_clrbit16(sc, TL_NETCONFIG, TL_CFG_PHYEN);
1054 /* Handle cards with bitrate devices. */
1056 tl_dio_setbit16(sc, TL_NETCONFIG, TL_CFG_BITRATE);
1059 * Load adapter irq pacing timer and tx threshold.
1060 * We make the transmit threshold 1 initially but we may
1061 * change that later.
1063 cmd = CSR_READ_4(sc, TL_HOSTCMD);
1065 cmd &= ~(TL_CMD_RT|TL_CMD_EOC|TL_CMD_ACK_MASK|TL_CMD_CHSEL_MASK);
1066 CMD_PUT(sc, cmd | (TL_CMD_LDTHR | TX_THR));
1067 CMD_PUT(sc, cmd | (TL_CMD_LDTMR | 0x00000003));
1069 /* Unreset the MII */
1070 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_NMRST);
1072 /* Take the adapter out of reset */
1073 tl_dio_setbit(sc, TL_NETCMD, TL_CMD_NRESET|TL_CMD_NWRAP);
1075 /* Wait for things to settle down a little. */
1082 * Probe for a ThunderLAN chip. Check the PCI vendor and device IDs
1083 * against our list and return its name if we find a match.
1085 static int tl_probe(dev)
1092 while(t->tl_name != NULL) {
1093 if ((pci_get_vendor(dev) == t->tl_vid) &&
1094 (pci_get_device(dev) == t->tl_did)) {
1095 device_set_desc(dev, t->tl_name);
1104 static int tl_attach(dev)
1112 struct tl_softc *sc;
1113 int unit, error = 0, rid;
1117 vid = pci_get_vendor(dev);
1118 did = pci_get_device(dev);
1119 sc = device_get_softc(dev);
1120 unit = device_get_unit(dev);
1121 bzero(sc, sizeof(struct tl_softc));
1124 while(t->tl_name != NULL) {
1125 if (vid == t->tl_vid && did == t->tl_did)
1130 if (t->tl_name == NULL) {
1131 printf("tl%d: unknown device!?\n", unit);
1136 * Map control/status registers.
1138 command = pci_read_config(dev, PCIR_COMMAND, 4);
1139 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN);
1140 pci_write_config(dev, PCIR_COMMAND, command, 4);
1141 command = pci_read_config(dev, PCIR_COMMAND, 4);
1143 #ifdef TL_USEIOSPACE
1144 if (!(command & PCIM_CMD_PORTEN)) {
1145 printf("tl%d: failed to enable I/O ports!\n", unit);
1151 sc->tl_res = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid,
1152 0, ~0, 1, RF_ACTIVE);
1155 * Some cards have the I/O and memory mapped address registers
1156 * reversed. Try both combinations before giving up.
1158 if (sc->tl_res == NULL) {
1160 sc->tl_res = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid,
1161 0, ~0, 1, RF_ACTIVE);
1164 if (!(command & PCIM_CMD_MEMEN)) {
1165 printf("tl%d: failed to enable memory mapping!\n", unit);
1171 sc->tl_res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid,
1172 0, ~0, 1, RF_ACTIVE);
1173 if (sc->tl_res == NULL) {
1175 sc->tl_res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid,
1176 0, ~0, 1, RF_ACTIVE);
1180 if (sc->tl_res == NULL) {
1181 printf("tl%d: couldn't map ports/memory\n", unit);
1186 sc->tl_btag = rman_get_bustag(sc->tl_res);
1187 sc->tl_bhandle = rman_get_bushandle(sc->tl_res);
1191 * The ThunderLAN manual suggests jacking the PCI latency
1192 * timer all the way up to its maximum value. I'm not sure
1193 * if this is really necessary, but what the manual wants,
1196 command = pci_read_config(dev, TL_PCI_LATENCY_TIMER, 4);
1197 command |= 0x0000FF00;
1198 pci_write_config(dev, TL_PCI_LATENCY_TIMER, command, 4);
1201 /* Allocate interrupt */
1203 sc->tl_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1,
1204 RF_SHAREABLE | RF_ACTIVE);
1206 if (sc->tl_irq == NULL) {
1207 bus_release_resource(dev, TL_RES, TL_RID, sc->tl_res);
1208 printf("tl%d: couldn't map interrupt\n", unit);
1213 error = bus_setup_intr(dev, sc->tl_irq, INTR_TYPE_NET,
1214 tl_intr, sc, &sc->tl_intrhand);
1217 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->tl_irq);
1218 bus_release_resource(dev, TL_RES, TL_RID, sc->tl_res);
1219 printf("tl%d: couldn't set up irq\n", unit);
1224 * Now allocate memory for the TX and RX lists.
1226 sc->tl_ldata = contigmalloc(sizeof(struct tl_list_data), M_DEVBUF,
1227 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
1229 if (sc->tl_ldata == NULL) {
1230 bus_teardown_intr(dev, sc->tl_irq, sc->tl_intrhand);
1231 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->tl_irq);
1232 bus_release_resource(dev, TL_RES, TL_RID, sc->tl_res);
1233 printf("tl%d: no memory for list buffers!\n", unit);
1238 bzero(sc->tl_ldata, sizeof(struct tl_list_data));
1242 if (t->tl_vid == COMPAQ_VENDORID || t->tl_vid == TI_VENDORID)
1243 sc->tl_eeaddr = TL_EEPROM_EADDR;
1244 if (t->tl_vid == OLICOM_VENDORID)
1245 sc->tl_eeaddr = TL_EEPROM_EADDR_OC;
1247 /* Reset the adapter. */
1248 tl_softreset(sc, 1);
1250 tl_softreset(sc, 1);
1253 * Get station address from the EEPROM.
1255 if (tl_read_eeprom(sc, (caddr_t)&sc->arpcom.ac_enaddr,
1256 sc->tl_eeaddr, ETHER_ADDR_LEN)) {
1257 bus_teardown_intr(dev, sc->tl_irq, sc->tl_intrhand);
1258 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->tl_irq);
1259 bus_release_resource(dev, TL_RES, TL_RID, sc->tl_res);
1260 contigfree(sc->tl_ldata,
1261 sizeof(struct tl_list_data), M_DEVBUF);
1262 printf("tl%d: failed to read station address\n", unit);
1268 * XXX Olicom, in its desire to be different from the
1269 * rest of the world, has done strange things with the
1270 * encoding of the station address in the EEPROM. First
1271 * of all, they store the address at offset 0xF8 rather
1272 * than at 0x83 like the ThunderLAN manual suggests.
1273 * Second, they store the address in three 16-bit words in
1274 * network byte order, as opposed to storing it sequentially
1275 * like all the other ThunderLAN cards. In order to get
1276 * the station address in a form that matches what the Olicom
1277 * diagnostic utility specifies, we have to byte-swap each
1278 * word. To make things even more confusing, neither 00:00:28
1279 * nor 00:00:24 appear in the IEEE OUI database.
1281 if (sc->tl_dinfo->tl_vid == OLICOM_VENDORID) {
1282 for (i = 0; i < ETHER_ADDR_LEN; i += 2) {
1284 p = (u_int16_t *)&sc->arpcom.ac_enaddr[i];
1289 ifp = &sc->arpcom.ac_if;
1291 if_initname(ifp, "tl", sc->tl_unit);
1292 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1293 ifp->if_ioctl = tl_ioctl;
1294 ifp->if_start = tl_start;
1295 ifp->if_watchdog = tl_watchdog;
1296 ifp->if_init = tl_init;
1297 ifp->if_mtu = ETHERMTU;
1298 ifq_set_maxlen(&ifp->if_snd, TL_TX_LIST_CNT - 1);
1299 ifq_set_ready(&ifp->if_snd);
1300 callout_init(&sc->tl_stat_timer);
1302 /* Reset the adapter again. */
1303 tl_softreset(sc, 1);
1305 tl_softreset(sc, 1);
1308 * Do MII setup. If no PHYs are found, then this is a
1309 * bitrate ThunderLAN chip that only supports 10baseT
1312 if (mii_phy_probe(dev, &sc->tl_miibus,
1313 tl_ifmedia_upd, tl_ifmedia_sts)) {
1314 struct ifmedia *ifm;
1316 ifmedia_init(&sc->ifmedia, 0, tl_ifmedia_upd, tl_ifmedia_sts);
1317 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL);
1318 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T|IFM_HDX, 0, NULL);
1319 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL);
1320 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_5, 0, NULL);
1321 ifmedia_set(&sc->ifmedia, IFM_ETHER|IFM_10_T);
1322 /* Reset again, this time setting bitrate mode. */
1323 tl_softreset(sc, 1);
1325 ifm->ifm_media = ifm->ifm_cur->ifm_media;
1326 tl_ifmedia_upd(ifp);
1330 * Call MI attach routine.
1332 ether_ifattach(ifp, sc->arpcom.ac_enaddr);
1339 static int tl_detach(dev)
1342 struct tl_softc *sc;
1348 sc = device_get_softc(dev);
1349 ifp = &sc->arpcom.ac_if;
1352 ether_ifdetach(ifp);
1354 bus_generic_detach(dev);
1355 device_delete_child(dev, sc->tl_miibus);
1357 contigfree(sc->tl_ldata, sizeof(struct tl_list_data), M_DEVBUF);
1359 ifmedia_removeall(&sc->ifmedia);
1361 bus_teardown_intr(dev, sc->tl_irq, sc->tl_intrhand);
1362 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->tl_irq);
1363 bus_release_resource(dev, TL_RES, TL_RID, sc->tl_res);
1371 * Initialize the transmit lists.
1373 static int tl_list_tx_init(sc)
1374 struct tl_softc *sc;
1376 struct tl_chain_data *cd;
1377 struct tl_list_data *ld;
1382 for (i = 0; i < TL_TX_LIST_CNT; i++) {
1383 cd->tl_tx_chain[i].tl_ptr = &ld->tl_tx_list[i];
1384 if (i == (TL_TX_LIST_CNT - 1))
1385 cd->tl_tx_chain[i].tl_next = NULL;
1387 cd->tl_tx_chain[i].tl_next = &cd->tl_tx_chain[i + 1];
1390 cd->tl_tx_free = &cd->tl_tx_chain[0];
1391 cd->tl_tx_tail = cd->tl_tx_head = NULL;
1398 * Initialize the RX lists and allocate mbufs for them.
1400 static int tl_list_rx_init(sc)
1401 struct tl_softc *sc;
1403 struct tl_chain_data *cd;
1404 struct tl_list_data *ld;
1410 for (i = 0; i < TL_RX_LIST_CNT; i++) {
1411 cd->tl_rx_chain[i].tl_ptr =
1412 (struct tl_list_onefrag *)&ld->tl_rx_list[i];
1413 if (tl_newbuf(sc, &cd->tl_rx_chain[i]) == ENOBUFS)
1415 if (i == (TL_RX_LIST_CNT - 1)) {
1416 cd->tl_rx_chain[i].tl_next = NULL;
1417 ld->tl_rx_list[i].tlist_fptr = 0;
1419 cd->tl_rx_chain[i].tl_next = &cd->tl_rx_chain[i + 1];
1420 ld->tl_rx_list[i].tlist_fptr =
1421 vtophys(&ld->tl_rx_list[i + 1]);
1425 cd->tl_rx_head = &cd->tl_rx_chain[0];
1426 cd->tl_rx_tail = &cd->tl_rx_chain[TL_RX_LIST_CNT - 1];
1431 static int tl_newbuf(sc, c)
1432 struct tl_softc *sc;
1433 struct tl_chain_onefrag *c;
1435 struct mbuf *m_new = NULL;
1437 MGETHDR(m_new, MB_DONTWAIT, MT_DATA);
1441 MCLGET(m_new, MB_DONTWAIT);
1442 if (!(m_new->m_flags & M_EXT)) {
1453 c->tl_ptr->tlist_frsize = MCLBYTES;
1454 c->tl_ptr->tlist_fptr = 0;
1455 c->tl_ptr->tl_frag.tlist_dadr = vtophys(mtod(m_new, caddr_t));
1456 c->tl_ptr->tl_frag.tlist_dcnt = MCLBYTES;
1457 c->tl_ptr->tlist_cstat = TL_CSTAT_READY;
1462 * Interrupt handler for RX 'end of frame' condition (EOF). This
1463 * tells us that a full ethernet frame has been captured and we need
1466 * Reception is done using 'lists' which consist of a header and a
1467 * series of 10 data count/data address pairs that point to buffers.
1468 * Initially you're supposed to create a list, populate it with pointers
1469 * to buffers, then load the physical address of the list into the
1470 * ch_parm register. The adapter is then supposed to DMA the received
1471 * frame into the buffers for you.
1473 * To make things as fast as possible, we have the chip DMA directly
1474 * into mbufs. This saves us from having to do a buffer copy: we can
1475 * just hand the mbufs directly to ether_input(). Once the frame has
1476 * been sent on its way, the 'list' structure is assigned a new buffer
1477 * and moved to the end of the RX chain. As long we we stay ahead of
1478 * the chip, it will always think it has an endless receive channel.
1480 * If we happen to fall behind and the chip manages to fill up all of
1481 * the buffers, it will generate an end of channel interrupt and wait
1482 * for us to empty the chain and restart the receiver.
1484 static int tl_intvec_rxeof(xsc, type)
1488 struct tl_softc *sc;
1489 int r = 0, total_len = 0;
1490 struct ether_header *eh;
1493 struct tl_chain_onefrag *cur_rx;
1496 ifp = &sc->arpcom.ac_if;
1498 while(sc->tl_cdata.tl_rx_head != NULL) {
1499 cur_rx = sc->tl_cdata.tl_rx_head;
1500 if (!(cur_rx->tl_ptr->tlist_cstat & TL_CSTAT_FRAMECMP))
1503 sc->tl_cdata.tl_rx_head = cur_rx->tl_next;
1504 m = cur_rx->tl_mbuf;
1505 total_len = cur_rx->tl_ptr->tlist_frsize;
1507 if (tl_newbuf(sc, cur_rx) == ENOBUFS) {
1509 cur_rx->tl_ptr->tlist_frsize = MCLBYTES;
1510 cur_rx->tl_ptr->tlist_cstat = TL_CSTAT_READY;
1511 cur_rx->tl_ptr->tl_frag.tlist_dcnt = MCLBYTES;
1515 sc->tl_cdata.tl_rx_tail->tl_ptr->tlist_fptr =
1516 vtophys(cur_rx->tl_ptr);
1517 sc->tl_cdata.tl_rx_tail->tl_next = cur_rx;
1518 sc->tl_cdata.tl_rx_tail = cur_rx;
1520 eh = mtod(m, struct ether_header *);
1521 m->m_pkthdr.rcvif = ifp;
1524 * Note: when the ThunderLAN chip is in 'capture all
1525 * frames' mode, it will receive its own transmissions.
1526 * We drop don't need to process our own transmissions,
1527 * so we drop them here and continue.
1529 /*if (ifp->if_flags & IFF_PROMISC && */
1530 if (!bcmp(eh->ether_shost, sc->arpcom.ac_enaddr,
1536 (*ifp->if_input)(ifp, m);
1543 * The RX-EOC condition hits when the ch_parm address hasn't been
1544 * initialized or the adapter reached a list with a forward pointer
1545 * of 0 (which indicates the end of the chain). In our case, this means
1546 * the card has hit the end of the receive buffer chain and we need to
1547 * empty out the buffers and shift the pointer back to the beginning again.
1549 static int tl_intvec_rxeoc(xsc, type)
1553 struct tl_softc *sc;
1555 struct tl_chain_data *cd;
1561 /* Flush out the receive queue and ack RXEOF interrupts. */
1562 r = tl_intvec_rxeof(xsc, type);
1563 CMD_PUT(sc, TL_CMD_ACK | r | (type & ~(0x00100000)));
1565 cd->tl_rx_head = &cd->tl_rx_chain[0];
1566 cd->tl_rx_tail = &cd->tl_rx_chain[TL_RX_LIST_CNT - 1];
1567 CSR_WRITE_4(sc, TL_CH_PARM, vtophys(sc->tl_cdata.tl_rx_head->tl_ptr));
1568 r |= (TL_CMD_GO|TL_CMD_RT);
1572 static int tl_intvec_txeof(xsc, type)
1576 struct tl_softc *sc;
1578 struct tl_chain *cur_tx;
1583 * Go through our tx list and free mbufs for those
1584 * frames that have been sent.
1586 while (sc->tl_cdata.tl_tx_head != NULL) {
1587 cur_tx = sc->tl_cdata.tl_tx_head;
1588 if (!(cur_tx->tl_ptr->tlist_cstat & TL_CSTAT_FRAMECMP))
1590 sc->tl_cdata.tl_tx_head = cur_tx->tl_next;
1593 m_freem(cur_tx->tl_mbuf);
1594 cur_tx->tl_mbuf = NULL;
1596 cur_tx->tl_next = sc->tl_cdata.tl_tx_free;
1597 sc->tl_cdata.tl_tx_free = cur_tx;
1598 if (!cur_tx->tl_ptr->tlist_fptr)
1606 * The transmit end of channel interrupt. The adapter triggers this
1607 * interrupt to tell us it hit the end of the current transmit list.
1609 * A note about this: it's possible for a condition to arise where
1610 * tl_start() may try to send frames between TXEOF and TXEOC interrupts.
1611 * You have to avoid this since the chip expects things to go in a
1612 * particular order: transmit, acknowledge TXEOF, acknowledge TXEOC.
1613 * When the TXEOF handler is called, it will free all of the transmitted
1614 * frames and reset the tx_head pointer to NULL. However, a TXEOC
1615 * interrupt should be received and acknowledged before any more frames
1616 * are queued for transmission. If tl_statrt() is called after TXEOF
1617 * resets the tx_head pointer but _before_ the TXEOC interrupt arrives,
1618 * it could attempt to issue a transmit command prematurely.
1620 * To guard against this, tl_start() will only issue transmit commands
1621 * if the tl_txeoc flag is set, and only the TXEOC interrupt handler
1622 * can set this flag once tl_start() has cleared it.
1624 static int tl_intvec_txeoc(xsc, type)
1628 struct tl_softc *sc;
1633 ifp = &sc->arpcom.ac_if;
1635 /* Clear the timeout timer. */
1638 if (sc->tl_cdata.tl_tx_head == NULL) {
1639 ifp->if_flags &= ~IFF_OACTIVE;
1640 sc->tl_cdata.tl_tx_tail = NULL;
1644 /* First we have to ack the EOC interrupt. */
1645 CMD_PUT(sc, TL_CMD_ACK | 0x00000001 | type);
1646 /* Then load the address of the next TX list. */
1647 CSR_WRITE_4(sc, TL_CH_PARM,
1648 vtophys(sc->tl_cdata.tl_tx_head->tl_ptr));
1649 /* Restart TX channel. */
1650 cmd = CSR_READ_4(sc, TL_HOSTCMD);
1652 cmd |= TL_CMD_GO|TL_CMD_INTSON;
1660 static int tl_intvec_adchk(xsc, type)
1664 struct tl_softc *sc;
1669 printf("tl%d: adapter check: %x\n", sc->tl_unit,
1670 (unsigned int)CSR_READ_4(sc, TL_CH_PARM));
1672 tl_softreset(sc, 1);
1675 CMD_SET(sc, TL_CMD_INTSON);
1680 static int tl_intvec_netsts(xsc, type)
1684 struct tl_softc *sc;
1689 netsts = tl_dio_read16(sc, TL_NETSTS);
1690 tl_dio_write16(sc, TL_NETSTS, netsts);
1692 printf("tl%d: network status: %x\n", sc->tl_unit, netsts);
1697 static void tl_intr(xsc)
1700 struct tl_softc *sc;
1709 /* Disable interrupts */
1710 ints = CSR_READ_2(sc, TL_HOST_INT);
1711 CSR_WRITE_2(sc, TL_HOST_INT, ints);
1712 type = (ints << 16) & 0xFFFF0000;
1713 ivec = (ints & TL_VEC_MASK) >> 5;
1714 ints = (ints & TL_INT_MASK) >> 2;
1716 ifp = &sc->arpcom.ac_if;
1719 case (TL_INTR_INVALID):
1721 printf("tl%d: got an invalid interrupt!\n", sc->tl_unit);
1723 /* Re-enable interrupts but don't ack this one. */
1727 case (TL_INTR_TXEOF):
1728 r = tl_intvec_txeof((void *)sc, type);
1730 case (TL_INTR_TXEOC):
1731 r = tl_intvec_txeoc((void *)sc, type);
1733 case (TL_INTR_STATOFLOW):
1734 tl_stats_update(sc);
1737 case (TL_INTR_RXEOF):
1738 r = tl_intvec_rxeof((void *)sc, type);
1740 case (TL_INTR_DUMMY):
1741 printf("tl%d: got a dummy interrupt\n", sc->tl_unit);
1744 case (TL_INTR_ADCHK):
1746 r = tl_intvec_adchk((void *)sc, type);
1748 r = tl_intvec_netsts((void *)sc, type);
1750 case (TL_INTR_RXEOC):
1751 r = tl_intvec_rxeoc((void *)sc, type);
1754 printf("%s: bogus interrupt type\n", ifp->if_xname);
1758 /* Re-enable interrupts */
1760 CMD_PUT(sc, TL_CMD_ACK | r | type);
1763 if (!ifq_is_empty(&ifp->if_snd))
1769 static void tl_stats_update(xsc)
1772 struct tl_softc *sc;
1774 struct tl_stats tl_stats;
1775 struct mii_data *mii;
1781 bzero((char *)&tl_stats, sizeof(struct tl_stats));
1784 ifp = &sc->arpcom.ac_if;
1786 p = (u_int32_t *)&tl_stats;
1788 CSR_WRITE_2(sc, TL_DIO_ADDR, TL_TXGOODFRAMES|TL_DIO_ADDR_INC);
1789 *p++ = CSR_READ_4(sc, TL_DIO_DATA);
1790 *p++ = CSR_READ_4(sc, TL_DIO_DATA);
1791 *p++ = CSR_READ_4(sc, TL_DIO_DATA);
1792 *p++ = CSR_READ_4(sc, TL_DIO_DATA);
1793 *p++ = CSR_READ_4(sc, TL_DIO_DATA);
1795 ifp->if_opackets += tl_tx_goodframes(tl_stats);
1796 ifp->if_collisions += tl_stats.tl_tx_single_collision +
1797 tl_stats.tl_tx_multi_collision;
1798 ifp->if_ipackets += tl_rx_goodframes(tl_stats);
1799 ifp->if_ierrors += tl_stats.tl_crc_errors + tl_stats.tl_code_errors +
1800 tl_rx_overrun(tl_stats);
1801 ifp->if_oerrors += tl_tx_underrun(tl_stats);
1803 if (tl_tx_underrun(tl_stats)) {
1805 tx_thresh = tl_dio_read8(sc, TL_ACOMMIT) & TL_AC_TXTHRESH;
1806 if (tx_thresh != TL_AC_TXTHRESH_WHOLEPKT) {
1809 printf("tl%d: tx underrun -- increasing "
1810 "tx threshold to %d bytes\n", sc->tl_unit,
1811 (64 * (tx_thresh * 4)));
1812 tl_dio_clrbit(sc, TL_ACOMMIT, TL_AC_TXTHRESH);
1813 tl_dio_setbit(sc, TL_ACOMMIT, tx_thresh << 4);
1817 callout_reset(&sc->tl_stat_timer, hz, tl_stats_update, sc);
1819 if (!sc->tl_bitrate) {
1820 mii = device_get_softc(sc->tl_miibus);
1830 * Encapsulate an mbuf chain in a list by coupling the mbuf data
1831 * pointers to the fragment pointers.
1833 static int tl_encap(sc, c, m_head)
1834 struct tl_softc *sc;
1836 struct mbuf *m_head;
1839 struct tl_frag *f = NULL;
1844 * Start packing the mbufs in this chain into
1845 * the fragment pointers. Stop when we run out
1846 * of fragments or hit the end of the mbuf chain.
1851 for (m = m_head, frag = 0; m != NULL; m = m->m_next) {
1852 if (m->m_len != 0) {
1853 if (frag == TL_MAXFRAGS)
1855 total_len+= m->m_len;
1856 c->tl_ptr->tl_frag[frag].tlist_dadr =
1857 vtophys(mtod(m, vm_offset_t));
1858 c->tl_ptr->tl_frag[frag].tlist_dcnt = m->m_len;
1864 * Handle special cases.
1865 * Special case #1: we used up all 10 fragments, but
1866 * we have more mbufs left in the chain. Copy the
1867 * data into an mbuf cluster. Note that we don't
1868 * bother clearing the values in the other fragment
1869 * pointers/counters; it wouldn't gain us anything,
1870 * and would waste cycles.
1873 struct mbuf *m_new = NULL;
1875 MGETHDR(m_new, MB_DONTWAIT, MT_DATA);
1876 if (m_new == NULL) {
1877 printf("tl%d: no memory for tx list\n", sc->tl_unit);
1880 if (m_head->m_pkthdr.len > MHLEN) {
1881 MCLGET(m_new, MB_DONTWAIT);
1882 if (!(m_new->m_flags & M_EXT)) {
1884 printf("tl%d: no memory for tx list\n",
1889 m_copydata(m_head, 0, m_head->m_pkthdr.len,
1890 mtod(m_new, caddr_t));
1891 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len;
1894 f = &c->tl_ptr->tl_frag[0];
1895 f->tlist_dadr = vtophys(mtod(m_new, caddr_t));
1896 f->tlist_dcnt = total_len = m_new->m_len;
1901 * Special case #2: the frame is smaller than the minimum
1902 * frame size. We have to pad it to make the chip happy.
1904 if (total_len < TL_MIN_FRAMELEN) {
1905 if (frag == TL_MAXFRAGS)
1906 printf("tl%d: all frags filled but "
1907 "frame still to small!\n", sc->tl_unit);
1908 f = &c->tl_ptr->tl_frag[frag];
1909 f->tlist_dcnt = TL_MIN_FRAMELEN - total_len;
1910 f->tlist_dadr = vtophys(&sc->tl_ldata->tl_pad);
1911 total_len += f->tlist_dcnt;
1915 c->tl_mbuf = m_head;
1916 c->tl_ptr->tl_frag[frag - 1].tlist_dcnt |= TL_LAST_FRAG;
1917 c->tl_ptr->tlist_frsize = total_len;
1918 c->tl_ptr->tlist_cstat = TL_CSTAT_READY;
1919 c->tl_ptr->tlist_fptr = 0;
1925 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
1926 * to the mbuf data regions directly in the transmit lists. We also save a
1927 * copy of the pointers since the transmit list fragment pointers are
1928 * physical addresses.
1930 static void tl_start(ifp)
1933 struct tl_softc *sc;
1934 struct mbuf *m_head = NULL;
1936 struct tl_chain *prev = NULL, *cur_tx = NULL, *start_tx;
1941 * Check for an available queue slot. If there are none,
1944 if (sc->tl_cdata.tl_tx_free == NULL) {
1945 ifp->if_flags |= IFF_OACTIVE;
1949 start_tx = sc->tl_cdata.tl_tx_free;
1951 while(sc->tl_cdata.tl_tx_free != NULL) {
1952 m_head = ifq_dequeue(&ifp->if_snd);
1956 /* Pick a chain member off the free list. */
1957 cur_tx = sc->tl_cdata.tl_tx_free;
1958 sc->tl_cdata.tl_tx_free = cur_tx->tl_next;
1960 cur_tx->tl_next = NULL;
1962 /* Pack the data into the list. */
1963 tl_encap(sc, cur_tx, m_head);
1965 /* Chain it together */
1967 prev->tl_next = cur_tx;
1968 prev->tl_ptr->tlist_fptr = vtophys(cur_tx->tl_ptr);
1972 BPF_MTAP(ifp, cur_tx->tl_mbuf);
1976 * If there are no packets queued, bail.
1982 * That's all we can stands, we can't stands no more.
1983 * If there are no other transfers pending, then issue the
1984 * TX GO command to the adapter to start things moving.
1985 * Otherwise, just leave the data in the queue and let
1986 * the EOF/EOC interrupt handler send.
1988 if (sc->tl_cdata.tl_tx_head == NULL) {
1989 sc->tl_cdata.tl_tx_head = start_tx;
1990 sc->tl_cdata.tl_tx_tail = cur_tx;
1994 CSR_WRITE_4(sc, TL_CH_PARM, vtophys(start_tx->tl_ptr));
1995 cmd = CSR_READ_4(sc, TL_HOSTCMD);
1997 cmd |= TL_CMD_GO|TL_CMD_INTSON;
2001 sc->tl_cdata.tl_tx_tail->tl_next = start_tx;
2002 sc->tl_cdata.tl_tx_tail = cur_tx;
2006 * Set a timeout in case the chip goes out to lunch.
2013 static void tl_init(xsc)
2016 struct tl_softc *sc = xsc;
2017 struct ifnet *ifp = &sc->arpcom.ac_if;
2019 struct mii_data *mii;
2023 ifp = &sc->arpcom.ac_if;
2026 * Cancel pending I/O.
2030 /* Initialize TX FIFO threshold */
2031 tl_dio_clrbit(sc, TL_ACOMMIT, TL_AC_TXTHRESH);
2032 tl_dio_setbit(sc, TL_ACOMMIT, TL_AC_TXTHRESH_16LONG);
2034 /* Set PCI burst size */
2035 tl_dio_write8(sc, TL_BSIZEREG, TL_RXBURST_16LONG|TL_TXBURST_16LONG);
2038 * Set 'capture all frames' bit for promiscuous mode.
2040 if (ifp->if_flags & IFF_PROMISC)
2041 tl_dio_setbit(sc, TL_NETCMD, TL_CMD_CAF);
2043 tl_dio_clrbit(sc, TL_NETCMD, TL_CMD_CAF);
2046 * Set capture broadcast bit to capture broadcast frames.
2048 if (ifp->if_flags & IFF_BROADCAST)
2049 tl_dio_clrbit(sc, TL_NETCMD, TL_CMD_NOBRX);
2051 tl_dio_setbit(sc, TL_NETCMD, TL_CMD_NOBRX);
2053 tl_dio_write16(sc, TL_MAXRX, MCLBYTES);
2055 /* Init our MAC address */
2056 tl_setfilt(sc, (caddr_t)&sc->arpcom.ac_enaddr, 0);
2058 /* Init multicast filter, if needed. */
2061 /* Init circular RX list. */
2062 if (tl_list_rx_init(sc) == ENOBUFS) {
2063 printf("tl%d: initialization failed: no "
2064 "memory for rx buffers\n", sc->tl_unit);
2069 /* Init TX pointers. */
2070 tl_list_tx_init(sc);
2072 /* Enable PCI interrupts. */
2073 CMD_SET(sc, TL_CMD_INTSON);
2075 /* Load the address of the rx list */
2076 CMD_SET(sc, TL_CMD_RT);
2077 CSR_WRITE_4(sc, TL_CH_PARM, vtophys(&sc->tl_ldata->tl_rx_list[0]));
2079 if (!sc->tl_bitrate) {
2080 if (sc->tl_miibus != NULL) {
2081 mii = device_get_softc(sc->tl_miibus);
2086 /* Send the RX go command */
2087 CMD_SET(sc, TL_CMD_GO|TL_CMD_NES|TL_CMD_RT);
2089 ifp->if_flags |= IFF_RUNNING;
2090 ifp->if_flags &= ~IFF_OACTIVE;
2094 /* Start the stats update counter */
2095 callout_reset(&sc->tl_stat_timer, hz, tl_stats_update, sc);
2099 * Set media options.
2101 static int tl_ifmedia_upd(ifp)
2104 struct tl_softc *sc;
2105 struct mii_data *mii = NULL;
2110 tl_setmode(sc, sc->ifmedia.ifm_media);
2112 mii = device_get_softc(sc->tl_miibus);
2120 * Report current media status.
2122 static void tl_ifmedia_sts(ifp, ifmr)
2124 struct ifmediareq *ifmr;
2126 struct tl_softc *sc;
2127 struct mii_data *mii;
2131 ifmr->ifm_active = IFM_ETHER;
2133 if (sc->tl_bitrate) {
2134 if (tl_dio_read8(sc, TL_ACOMMIT) & TL_AC_MTXD1)
2135 ifmr->ifm_active = IFM_ETHER|IFM_10_5;
2137 ifmr->ifm_active = IFM_ETHER|IFM_10_T;
2138 if (tl_dio_read8(sc, TL_ACOMMIT) & TL_AC_MTXD3)
2139 ifmr->ifm_active |= IFM_HDX;
2141 ifmr->ifm_active |= IFM_FDX;
2144 mii = device_get_softc(sc->tl_miibus);
2146 ifmr->ifm_active = mii->mii_media_active;
2147 ifmr->ifm_status = mii->mii_media_status;
2153 static int tl_ioctl(ifp, command, data, cr)
2159 struct tl_softc *sc = ifp->if_softc;
2160 struct ifreq *ifr = (struct ifreq *) data;
2169 error = ether_ioctl(ifp, command, data);
2172 if (ifp->if_flags & IFF_UP) {
2173 if (ifp->if_flags & IFF_RUNNING &&
2174 ifp->if_flags & IFF_PROMISC &&
2175 !(sc->tl_if_flags & IFF_PROMISC)) {
2176 tl_dio_setbit(sc, TL_NETCMD, TL_CMD_CAF);
2178 } else if (ifp->if_flags & IFF_RUNNING &&
2179 !(ifp->if_flags & IFF_PROMISC) &&
2180 sc->tl_if_flags & IFF_PROMISC) {
2181 tl_dio_clrbit(sc, TL_NETCMD, TL_CMD_CAF);
2186 if (ifp->if_flags & IFF_RUNNING) {
2190 sc->tl_if_flags = ifp->if_flags;
2201 error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command);
2203 struct mii_data *mii;
2204 mii = device_get_softc(sc->tl_miibus);
2205 error = ifmedia_ioctl(ifp, ifr,
2206 &mii->mii_media, command);
2219 static void tl_watchdog(ifp)
2222 struct tl_softc *sc;
2226 printf("tl%d: device timeout\n", sc->tl_unit);
2230 tl_softreset(sc, 1);
2237 * Stop the adapter and free any mbufs allocated to the
2240 static void tl_stop(sc)
2241 struct tl_softc *sc;
2246 ifp = &sc->arpcom.ac_if;
2248 /* Stop the stats updater. */
2249 callout_stop(&sc->tl_stat_timer);
2251 /* Stop the transmitter */
2252 CMD_CLR(sc, TL_CMD_RT);
2253 CMD_SET(sc, TL_CMD_STOP);
2254 CSR_WRITE_4(sc, TL_CH_PARM, 0);
2256 /* Stop the receiver */
2257 CMD_SET(sc, TL_CMD_RT);
2258 CMD_SET(sc, TL_CMD_STOP);
2259 CSR_WRITE_4(sc, TL_CH_PARM, 0);
2262 * Disable host interrupts.
2264 CMD_SET(sc, TL_CMD_INTSOFF);
2267 * Clear list pointer.
2269 CSR_WRITE_4(sc, TL_CH_PARM, 0);
2272 * Free the RX lists.
2274 for (i = 0; i < TL_RX_LIST_CNT; i++) {
2275 if (sc->tl_cdata.tl_rx_chain[i].tl_mbuf != NULL) {
2276 m_freem(sc->tl_cdata.tl_rx_chain[i].tl_mbuf);
2277 sc->tl_cdata.tl_rx_chain[i].tl_mbuf = NULL;
2280 bzero((char *)&sc->tl_ldata->tl_rx_list,
2281 sizeof(sc->tl_ldata->tl_rx_list));
2284 * Free the TX list buffers.
2286 for (i = 0; i < TL_TX_LIST_CNT; i++) {
2287 if (sc->tl_cdata.tl_tx_chain[i].tl_mbuf != NULL) {
2288 m_freem(sc->tl_cdata.tl_tx_chain[i].tl_mbuf);
2289 sc->tl_cdata.tl_tx_chain[i].tl_mbuf = NULL;
2292 bzero((char *)&sc->tl_ldata->tl_tx_list,
2293 sizeof(sc->tl_ldata->tl_tx_list));
2295 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
2301 * Stop all chip I/O so that the kernel's probe routines don't
2302 * get confused by errant DMAs when rebooting.
2304 static void tl_shutdown(dev)
2307 struct tl_softc *sc;
2309 sc = device_get_softc(dev);