bce: Add TSO support
[dragonfly.git] / sys / dev / netif / bce / if_bce.c
1 /*-
2  * Copyright (c) 2006-2007 Broadcom Corporation
3  *      David Christensen <davidch@broadcom.com>.  All rights reserved.
4  *
5  * Redistribution and use in source and binary forms, with or without
6  * modification, are permitted provided that the following conditions
7  * are met:
8  *
9  * 1. Redistributions of source code must retain the above copyright
10  *    notice, this list of conditions and the following disclaimer.
11  * 2. Redistributions in binary form must reproduce the above copyright
12  *    notice, this list of conditions and the following disclaimer in the
13  *    documentation and/or other materials provided with the distribution.
14  * 3. Neither the name of Broadcom Corporation nor the name of its contributors
15  *    may be used to endorse or promote products derived from this software
16  *    without specific prior written consent.
17  *
18  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS'
19  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21  * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
22  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
28  * THE POSSIBILITY OF SUCH DAMAGE.
29  *
30  * $FreeBSD: src/sys/dev/bce/if_bce.c,v 1.31 2007/05/16 23:34:11 davidch Exp $
31  */
32
33 /*
34  * The following controllers are supported by this driver:
35  *   BCM5706C A2, A3
36  *   BCM5706S A2, A3
37  *   BCM5708C B1, B2
38  *   BCM5708S B1, B2
39  *   BCM5709C A1, C0
40  *   BCM5716  C0
41  *
42  * The following controllers are not supported by this driver:
43  *   BCM5706C A0, A1
44  *   BCM5706S A0, A1
45  *   BCM5708C A0, B0
46  *   BCM5708S A0, B0
47  *   BCM5709C A0, B0, B1
48  *   BCM5709S A0, A1, B0, B1, B2, C0
49  */
50
51 #include "opt_bce.h"
52 #include "opt_polling.h"
53
54 #include <sys/param.h>
55 #include <sys/bus.h>
56 #include <sys/endian.h>
57 #include <sys/kernel.h>
58 #include <sys/interrupt.h>
59 #include <sys/mbuf.h>
60 #include <sys/malloc.h>
61 #include <sys/queue.h>
62 #ifdef BCE_DEBUG
63 #include <sys/random.h>
64 #endif
65 #include <sys/rman.h>
66 #include <sys/serialize.h>
67 #include <sys/socket.h>
68 #include <sys/sockio.h>
69 #include <sys/sysctl.h>
70
71 #include <netinet/ip.h>
72 #include <netinet/tcp.h>
73
74 #include <net/bpf.h>
75 #include <net/ethernet.h>
76 #include <net/if.h>
77 #include <net/if_arp.h>
78 #include <net/if_dl.h>
79 #include <net/if_media.h>
80 #include <net/if_types.h>
81 #include <net/ifq_var.h>
82 #include <net/vlan/if_vlan_var.h>
83 #include <net/vlan/if_vlan_ether.h>
84
85 #include <dev/netif/mii_layer/mii.h>
86 #include <dev/netif/mii_layer/miivar.h>
87 #include <dev/netif/mii_layer/brgphyreg.h>
88
89 #include <bus/pci/pcireg.h>
90 #include <bus/pci/pcivar.h>
91
92 #include "miibus_if.h"
93
94 #include <dev/netif/bce/if_bcereg.h>
95 #include <dev/netif/bce/if_bcefw.h>
96
97 /****************************************************************************/
98 /* BCE Debug Options                                                        */
99 /****************************************************************************/
100 #ifdef BCE_DEBUG
101
102 static uint32_t bce_debug = BCE_WARN;
103
104 /*
105  *          0 = Never             
106  *          1 = 1 in 2,147,483,648
107  *        256 = 1 in     8,388,608
108  *       2048 = 1 in     1,048,576
109  *      65536 = 1 in        32,768
110  *    1048576 = 1 in         2,048
111  *  268435456 = 1 in             8
112  *  536870912 = 1 in             4
113  * 1073741824 = 1 in             2
114  *
115  * bce_debug_l2fhdr_status_check:
116  *     How often the l2_fhdr frame error check will fail.
117  *
118  * bce_debug_unexpected_attention:
119  *     How often the unexpected attention check will fail.
120  *
121  * bce_debug_mbuf_allocation_failure:
122  *     How often to simulate an mbuf allocation failure.
123  *
124  * bce_debug_dma_map_addr_failure:
125  *     How often to simulate a DMA mapping failure.
126  *
127  * bce_debug_bootcode_running_failure:
128  *     How often to simulate a bootcode failure.
129  */
130 static int      bce_debug_l2fhdr_status_check = 0;
131 static int      bce_debug_unexpected_attention = 0;
132 static int      bce_debug_mbuf_allocation_failure = 0;
133 static int      bce_debug_dma_map_addr_failure = 0;
134 static int      bce_debug_bootcode_running_failure = 0;
135
136 #endif  /* BCE_DEBUG */
137
138
139 /****************************************************************************/
140 /* PCI Device ID Table                                                      */
141 /*                                                                          */
142 /* Used by bce_probe() to identify the devices supported by this driver.    */
143 /****************************************************************************/
144 #define BCE_DEVDESC_MAX         64
145
146 static struct bce_type bce_devs[] = {
147         /* BCM5706C Controllers and OEM boards. */
148         { BRCM_VENDORID, BRCM_DEVICEID_BCM5706,  HP_VENDORID, 0x3101,
149                 "HP NC370T Multifunction Gigabit Server Adapter" },
150         { BRCM_VENDORID, BRCM_DEVICEID_BCM5706,  HP_VENDORID, 0x3106,
151                 "HP NC370i Multifunction Gigabit Server Adapter" },
152         { BRCM_VENDORID, BRCM_DEVICEID_BCM5706,  HP_VENDORID, 0x3070,
153                 "HP NC380T PCIe DP Multifunc Gig Server Adapter" },
154         { BRCM_VENDORID, BRCM_DEVICEID_BCM5706,  HP_VENDORID, 0x1709,
155                 "HP NC371i Multifunction Gigabit Server Adapter" },
156         { BRCM_VENDORID, BRCM_DEVICEID_BCM5706,  PCI_ANY_ID,  PCI_ANY_ID,
157                 "Broadcom NetXtreme II BCM5706 1000Base-T" },
158
159         /* BCM5706S controllers and OEM boards. */
160         { BRCM_VENDORID, BRCM_DEVICEID_BCM5706S, HP_VENDORID, 0x3102,
161                 "HP NC370F Multifunction Gigabit Server Adapter" },
162         { BRCM_VENDORID, BRCM_DEVICEID_BCM5706S, PCI_ANY_ID,  PCI_ANY_ID,
163                 "Broadcom NetXtreme II BCM5706 1000Base-SX" },
164
165         /* BCM5708C controllers and OEM boards. */
166         { BRCM_VENDORID, BRCM_DEVICEID_BCM5708,  HP_VENDORID, 0x7037,
167                 "HP NC373T PCIe Multifunction Gig Server Adapter" },
168         { BRCM_VENDORID, BRCM_DEVICEID_BCM5708,  HP_VENDORID, 0x7038,
169                 "HP NC373i Multifunction Gigabit Server Adapter" },
170         { BRCM_VENDORID, BRCM_DEVICEID_BCM5708,  HP_VENDORID, 0x7045,
171                 "HP NC374m PCIe Multifunction Adapter" },
172         { BRCM_VENDORID, BRCM_DEVICEID_BCM5708,  PCI_ANY_ID,  PCI_ANY_ID,
173                 "Broadcom NetXtreme II BCM5708 1000Base-T" },
174
175         /* BCM5708S controllers and OEM boards. */
176         { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S,  HP_VENDORID, 0x1706,
177                 "HP NC373m Multifunction Gigabit Server Adapter" },
178         { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S,  HP_VENDORID, 0x703b,
179                 "HP NC373i Multifunction Gigabit Server Adapter" },
180         { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S,  HP_VENDORID, 0x703d,
181                 "HP NC373F PCIe Multifunc Giga Server Adapter" },
182         { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S,  PCI_ANY_ID,  PCI_ANY_ID,
183                 "Broadcom NetXtreme II BCM5708S 1000Base-T" },
184
185         /* BCM5709C controllers and OEM boards. */
186         { BRCM_VENDORID, BRCM_DEVICEID_BCM5709,  HP_VENDORID, 0x7055,
187                 "HP NC382i DP Multifunction Gigabit Server Adapter" },
188         { BRCM_VENDORID, BRCM_DEVICEID_BCM5709,  HP_VENDORID, 0x7059,
189                 "HP NC382T PCIe DP Multifunction Gigabit Server Adapter" },
190         { BRCM_VENDORID, BRCM_DEVICEID_BCM5709,  PCI_ANY_ID,  PCI_ANY_ID,
191                 "Broadcom NetXtreme II BCM5709 1000Base-T" },
192
193         /* BCM5709S controllers and OEM boards. */
194         { BRCM_VENDORID, BRCM_DEVICEID_BCM5709S,  HP_VENDORID, 0x171d,
195                 "HP NC382m DP 1GbE Multifunction BL-c Adapter" },
196         { BRCM_VENDORID, BRCM_DEVICEID_BCM5709S,  HP_VENDORID, 0x7056,
197                 "HP NC382i DP Multifunction Gigabit Server Adapter" },
198         { BRCM_VENDORID, BRCM_DEVICEID_BCM5709S,  PCI_ANY_ID,  PCI_ANY_ID,
199                 "Broadcom NetXtreme II BCM5709 1000Base-SX" },
200
201         /* BCM5716 controllers and OEM boards. */
202         { BRCM_VENDORID, BRCM_DEVICEID_BCM5716,   PCI_ANY_ID,  PCI_ANY_ID,
203                 "Broadcom NetXtreme II BCM5716 1000Base-T" },
204
205         { 0, 0, 0, 0, NULL }
206 };
207
208
209 /****************************************************************************/
210 /* Supported Flash NVRAM device data.                                       */
211 /****************************************************************************/
212 static const struct flash_spec flash_table[] =
213 {
214 #define BUFFERED_FLAGS          (BCE_NV_BUFFERED | BCE_NV_TRANSLATE)
215 #define NONBUFFERED_FLAGS       (BCE_NV_WREN)
216
217         /* Slow EEPROM */
218         {0x00000000, 0x40830380, 0x009f0081, 0xa184a053, 0xaf000400,
219          BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
220          SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
221          "EEPROM - slow"},
222         /* Expansion entry 0001 */
223         {0x08000002, 0x4b808201, 0x00050081, 0x03840253, 0xaf020406,
224          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
225          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
226          "Entry 0001"},
227         /* Saifun SA25F010 (non-buffered flash) */
228         /* strap, cfg1, & write1 need updates */
229         {0x04000001, 0x47808201, 0x00050081, 0x03840253, 0xaf020406,
230          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
231          SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*2,
232          "Non-buffered flash (128kB)"},
233         /* Saifun SA25F020 (non-buffered flash) */
234         /* strap, cfg1, & write1 need updates */
235         {0x0c000003, 0x4f808201, 0x00050081, 0x03840253, 0xaf020406,
236          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
237          SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*4,
238          "Non-buffered flash (256kB)"},
239         /* Expansion entry 0100 */
240         {0x11000000, 0x53808201, 0x00050081, 0x03840253, 0xaf020406,
241          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
242          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
243          "Entry 0100"},
244         /* Entry 0101: ST M45PE10 (non-buffered flash, TetonII B0) */
245         {0x19000002, 0x5b808201, 0x000500db, 0x03840253, 0xaf020406,
246          NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
247          ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*2,
248          "Entry 0101: ST M45PE10 (128kB non-bufferred)"},
249         /* Entry 0110: ST M45PE20 (non-buffered flash)*/
250         {0x15000001, 0x57808201, 0x000500db, 0x03840253, 0xaf020406,
251          NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
252          ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*4,
253          "Entry 0110: ST M45PE20 (256kB non-bufferred)"},
254         /* Saifun SA25F005 (non-buffered flash) */
255         /* strap, cfg1, & write1 need updates */
256         {0x1d000003, 0x5f808201, 0x00050081, 0x03840253, 0xaf020406,
257          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
258          SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE,
259          "Non-buffered flash (64kB)"},
260         /* Fast EEPROM */
261         {0x22000000, 0x62808380, 0x009f0081, 0xa184a053, 0xaf000400,
262          BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
263          SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
264          "EEPROM - fast"},
265         /* Expansion entry 1001 */
266         {0x2a000002, 0x6b808201, 0x00050081, 0x03840253, 0xaf020406,
267          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
268          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
269          "Entry 1001"},
270         /* Expansion entry 1010 */
271         {0x26000001, 0x67808201, 0x00050081, 0x03840253, 0xaf020406,
272          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
273          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
274          "Entry 1010"},
275         /* ATMEL AT45DB011B (buffered flash) */
276         {0x2e000003, 0x6e808273, 0x00570081, 0x68848353, 0xaf000400,
277          BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
278          BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE,
279          "Buffered flash (128kB)"},
280         /* Expansion entry 1100 */
281         {0x33000000, 0x73808201, 0x00050081, 0x03840253, 0xaf020406,
282          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
283          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
284          "Entry 1100"},
285         /* Expansion entry 1101 */
286         {0x3b000002, 0x7b808201, 0x00050081, 0x03840253, 0xaf020406,
287          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
288          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
289          "Entry 1101"},
290         /* Ateml Expansion entry 1110 */
291         {0x37000001, 0x76808273, 0x00570081, 0x68848353, 0xaf000400,
292          BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
293          BUFFERED_FLASH_BYTE_ADDR_MASK, 0,
294          "Entry 1110 (Atmel)"},
295         /* ATMEL AT45DB021B (buffered flash) */
296         {0x3f000003, 0x7e808273, 0x00570081, 0x68848353, 0xaf000400,
297          BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
298          BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE*2,
299          "Buffered flash (256kB)"},
300 };
301
302 /*
303  * The BCM5709 controllers transparently handle the
304  * differences between Atmel 264 byte pages and all
305  * flash devices which use 256 byte pages, so no
306  * logical-to-physical mapping is required in the
307  * driver.
308  */
309 static struct flash_spec flash_5709 = {
310         .flags          = BCE_NV_BUFFERED,
311         .page_bits      = BCM5709_FLASH_PAGE_BITS,
312         .page_size      = BCM5709_FLASH_PAGE_SIZE,
313         .addr_mask      = BCM5709_FLASH_BYTE_ADDR_MASK,
314         .total_size     = BUFFERED_FLASH_TOTAL_SIZE * 2,
315         .name           = "5709/5716 buffered flash (256kB)",
316 };
317
318
319 /****************************************************************************/
320 /* DragonFly device entry points.                                           */
321 /****************************************************************************/
322 static int      bce_probe(device_t);
323 static int      bce_attach(device_t);
324 static int      bce_detach(device_t);
325 static void     bce_shutdown(device_t);
326
327 /****************************************************************************/
328 /* BCE Debug Data Structure Dump Routines                                   */
329 /****************************************************************************/
330 #ifdef BCE_DEBUG
331 static void     bce_dump_mbuf(struct bce_softc *, struct mbuf *);
332 static void     bce_dump_tx_mbuf_chain(struct bce_softc *, int, int);
333 static void     bce_dump_rx_mbuf_chain(struct bce_softc *, int, int);
334 static void     bce_dump_txbd(struct bce_softc *, int, struct tx_bd *);
335 static void     bce_dump_rxbd(struct bce_softc *, int, struct rx_bd *);
336 static void     bce_dump_l2fhdr(struct bce_softc *, int,
337                                 struct l2_fhdr *) __unused;
338 static void     bce_dump_tx_chain(struct bce_softc *, int, int);
339 static void     bce_dump_rx_chain(struct bce_softc *, int, int);
340 static void     bce_dump_status_block(struct bce_softc *);
341 static void     bce_dump_driver_state(struct bce_softc *);
342 static void     bce_dump_stats_block(struct bce_softc *) __unused;
343 static void     bce_dump_hw_state(struct bce_softc *);
344 static void     bce_dump_txp_state(struct bce_softc *);
345 static void     bce_dump_rxp_state(struct bce_softc *) __unused;
346 static void     bce_dump_tpat_state(struct bce_softc *) __unused;
347 static void     bce_freeze_controller(struct bce_softc *) __unused;
348 static void     bce_unfreeze_controller(struct bce_softc *) __unused;
349 static void     bce_breakpoint(struct bce_softc *);
350 #endif  /* BCE_DEBUG */
351
352
353 /****************************************************************************/
354 /* BCE Register/Memory Access Routines                                      */
355 /****************************************************************************/
356 static uint32_t bce_reg_rd_ind(struct bce_softc *, uint32_t);
357 static void     bce_reg_wr_ind(struct bce_softc *, uint32_t, uint32_t);
358 static void     bce_shmem_wr(struct bce_softc *, uint32_t, uint32_t);
359 static uint32_t bce_shmem_rd(struct bce_softc *, u32);
360 static void     bce_ctx_wr(struct bce_softc *, uint32_t, uint32_t, uint32_t);
361 static int      bce_miibus_read_reg(device_t, int, int);
362 static int      bce_miibus_write_reg(device_t, int, int, int);
363 static void     bce_miibus_statchg(device_t);
364
365
366 /****************************************************************************/
367 /* BCE NVRAM Access Routines                                                */
368 /****************************************************************************/
369 static int      bce_acquire_nvram_lock(struct bce_softc *);
370 static int      bce_release_nvram_lock(struct bce_softc *);
371 static void     bce_enable_nvram_access(struct bce_softc *);
372 static void     bce_disable_nvram_access(struct bce_softc *);
373 static int      bce_nvram_read_dword(struct bce_softc *, uint32_t, uint8_t *,
374                                      uint32_t);
375 static int      bce_init_nvram(struct bce_softc *);
376 static int      bce_nvram_read(struct bce_softc *, uint32_t, uint8_t *, int);
377 static int      bce_nvram_test(struct bce_softc *);
378
379 /****************************************************************************/
380 /* BCE DMA Allocate/Free Routines                                           */
381 /****************************************************************************/
382 static int      bce_dma_alloc(struct bce_softc *);
383 static void     bce_dma_free(struct bce_softc *);
384 static void     bce_dma_map_addr(void *, bus_dma_segment_t *, int, int);
385
386 /****************************************************************************/
387 /* BCE Firmware Synchronization and Load                                    */
388 /****************************************************************************/
389 static int      bce_fw_sync(struct bce_softc *, uint32_t);
390 static void     bce_load_rv2p_fw(struct bce_softc *, uint32_t *,
391                                  uint32_t, uint32_t);
392 static void     bce_load_cpu_fw(struct bce_softc *, struct cpu_reg *,
393                                 struct fw_info *);
394 static void     bce_start_cpu(struct bce_softc *, struct cpu_reg *);
395 static void     bce_halt_cpu(struct bce_softc *, struct cpu_reg *);
396 static void     bce_start_rxp_cpu(struct bce_softc *);
397 static void     bce_init_rxp_cpu(struct bce_softc *);
398 static void     bce_init_txp_cpu(struct bce_softc *);
399 static void     bce_init_tpat_cpu(struct bce_softc *);
400 static void     bce_init_cp_cpu(struct bce_softc *);
401 static void     bce_init_com_cpu(struct bce_softc *);
402 static void     bce_init_cpus(struct bce_softc *);
403
404 static void     bce_stop(struct bce_softc *);
405 static int      bce_reset(struct bce_softc *, uint32_t);
406 static int      bce_chipinit(struct bce_softc *);
407 static int      bce_blockinit(struct bce_softc *);
408 static int      bce_newbuf_std(struct bce_softc *, uint16_t *, uint16_t *,
409                                uint32_t *, int);
410 static void     bce_setup_rxdesc_std(struct bce_softc *, uint16_t, uint32_t *);
411 static void     bce_probe_pci_caps(struct bce_softc *);
412 static void     bce_print_adapter_info(struct bce_softc *);
413 static void     bce_get_media(struct bce_softc *);
414
415 static void     bce_init_tx_context(struct bce_softc *);
416 static int      bce_init_tx_chain(struct bce_softc *);
417 static void     bce_init_rx_context(struct bce_softc *);
418 static int      bce_init_rx_chain(struct bce_softc *);
419 static void     bce_free_rx_chain(struct bce_softc *);
420 static void     bce_free_tx_chain(struct bce_softc *);
421
422 static int      bce_encap(struct bce_softc *, struct mbuf **);
423 static int      bce_tso_setup(struct bce_softc *, struct mbuf **,
424                     uint16_t *, uint16_t *);
425 static void     bce_start(struct ifnet *);
426 static int      bce_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
427 static void     bce_watchdog(struct ifnet *);
428 static int      bce_ifmedia_upd(struct ifnet *);
429 static void     bce_ifmedia_sts(struct ifnet *, struct ifmediareq *);
430 static void     bce_init(void *);
431 static void     bce_mgmt_init(struct bce_softc *);
432
433 static int      bce_init_ctx(struct bce_softc *);
434 static void     bce_get_mac_addr(struct bce_softc *);
435 static void     bce_set_mac_addr(struct bce_softc *);
436 static void     bce_phy_intr(struct bce_softc *);
437 static void     bce_rx_intr(struct bce_softc *, int, uint16_t);
438 static void     bce_tx_intr(struct bce_softc *, uint16_t);
439 static void     bce_disable_intr(struct bce_softc *);
440 static void     bce_enable_intr(struct bce_softc *);
441 static void     bce_reenable_intr(struct bce_softc *);
442
443 #ifdef DEVICE_POLLING
444 static void     bce_poll(struct ifnet *, enum poll_cmd, int);
445 #endif
446 static void     bce_intr(struct bce_softc *);
447 static void     bce_intr_legacy(void *);
448 static void     bce_intr_msi(void *);
449 static void     bce_intr_msi_oneshot(void *);
450 static void     bce_set_rx_mode(struct bce_softc *);
451 static void     bce_stats_update(struct bce_softc *);
452 static void     bce_tick(void *);
453 static void     bce_tick_serialized(struct bce_softc *);
454 static void     bce_pulse(void *);
455 static void     bce_pulse_check_msi(struct bce_softc *);
456 static void     bce_add_sysctls(struct bce_softc *);
457
458 static void     bce_coal_change(struct bce_softc *);
459 static int      bce_sysctl_tx_bds_int(SYSCTL_HANDLER_ARGS);
460 static int      bce_sysctl_tx_bds(SYSCTL_HANDLER_ARGS);
461 static int      bce_sysctl_tx_ticks_int(SYSCTL_HANDLER_ARGS);
462 static int      bce_sysctl_tx_ticks(SYSCTL_HANDLER_ARGS);
463 static int      bce_sysctl_rx_bds_int(SYSCTL_HANDLER_ARGS);
464 static int      bce_sysctl_rx_bds(SYSCTL_HANDLER_ARGS);
465 static int      bce_sysctl_rx_ticks_int(SYSCTL_HANDLER_ARGS);
466 static int      bce_sysctl_rx_ticks(SYSCTL_HANDLER_ARGS);
467 static int      bce_sysctl_coal_change(SYSCTL_HANDLER_ARGS,
468                                        uint32_t *, uint32_t);
469
470 /*
471  * NOTE:
472  * Don't set bce_tx_ticks_int/bce_tx_ticks to 1023.  Linux's bnx2
473  * takes 1023 as the TX ticks limit.  However, using 1023 will
474  * cause 5708(B2) to generate extra interrupts (~2000/s) even when
475  * there is _no_ network activity on the NIC.
476  */
477 static uint32_t bce_tx_bds_int = 255;           /* bcm: 20 */
478 static uint32_t bce_tx_bds = 255;               /* bcm: 20 */
479 static uint32_t bce_tx_ticks_int = 1022;        /* bcm: 80 */
480 static uint32_t bce_tx_ticks = 1022;            /* bcm: 80 */
481 static uint32_t bce_rx_bds_int = 128;           /* bcm: 6 */
482 static uint32_t bce_rx_bds = 128;               /* bcm: 6 */
483 static uint32_t bce_rx_ticks_int = 150;         /* bcm: 18 */
484 static uint32_t bce_rx_ticks = 150;             /* bcm: 18 */
485
486 static int      bce_msi_enable = 1;
487
488 static int      bce_rx_pages = RX_PAGES_DEFAULT;
489 static int      bce_tx_pages = TX_PAGES_DEFAULT;
490
491 TUNABLE_INT("hw.bce.tx_bds_int", &bce_tx_bds_int);
492 TUNABLE_INT("hw.bce.tx_bds", &bce_tx_bds);
493 TUNABLE_INT("hw.bce.tx_ticks_int", &bce_tx_ticks_int);
494 TUNABLE_INT("hw.bce.tx_ticks", &bce_tx_ticks);
495 TUNABLE_INT("hw.bce.rx_bds_int", &bce_rx_bds_int);
496 TUNABLE_INT("hw.bce.rx_bds", &bce_rx_bds);
497 TUNABLE_INT("hw.bce.rx_ticks_int", &bce_rx_ticks_int);
498 TUNABLE_INT("hw.bce.rx_ticks", &bce_rx_ticks);
499 TUNABLE_INT("hw.bce.msi.enable", &bce_msi_enable);
500 TUNABLE_INT("hw.bce.rx_pages", &bce_rx_pages);
501 TUNABLE_INT("hw.bce.tx_pages", &bce_tx_pages);
502
503 /****************************************************************************/
504 /* DragonFly device dispatch table.                                         */
505 /****************************************************************************/
506 static device_method_t bce_methods[] = {
507         /* Device interface */
508         DEVMETHOD(device_probe,         bce_probe),
509         DEVMETHOD(device_attach,        bce_attach),
510         DEVMETHOD(device_detach,        bce_detach),
511         DEVMETHOD(device_shutdown,      bce_shutdown),
512
513         /* bus interface */
514         DEVMETHOD(bus_print_child,      bus_generic_print_child),
515         DEVMETHOD(bus_driver_added,     bus_generic_driver_added),
516
517         /* MII interface */
518         DEVMETHOD(miibus_readreg,       bce_miibus_read_reg),
519         DEVMETHOD(miibus_writereg,      bce_miibus_write_reg),
520         DEVMETHOD(miibus_statchg,       bce_miibus_statchg),
521
522         { 0, 0 }
523 };
524
525 static driver_t bce_driver = {
526         "bce",
527         bce_methods,
528         sizeof(struct bce_softc)
529 };
530
531 static devclass_t bce_devclass;
532
533
534 DECLARE_DUMMY_MODULE(if_bce);
535 MODULE_DEPEND(bce, miibus, 1, 1, 1);
536 DRIVER_MODULE(if_bce, pci, bce_driver, bce_devclass, NULL, NULL);
537 DRIVER_MODULE(miibus, bce, miibus_driver, miibus_devclass, NULL, NULL);
538
539
540 /****************************************************************************/
541 /* Device probe function.                                                   */
542 /*                                                                          */
543 /* Compares the device to the driver's list of supported devices and        */
544 /* reports back to the OS whether this is the right driver for the device.  */
545 /*                                                                          */
546 /* Returns:                                                                 */
547 /*   BUS_PROBE_DEFAULT on success, positive value on failure.               */
548 /****************************************************************************/
549 static int
550 bce_probe(device_t dev)
551 {
552         struct bce_type *t;
553         uint16_t vid, did, svid, sdid;
554
555         /* Get the data for the device to be probed. */
556         vid  = pci_get_vendor(dev);
557         did  = pci_get_device(dev);
558         svid = pci_get_subvendor(dev);
559         sdid = pci_get_subdevice(dev);
560
561         /* Look through the list of known devices for a match. */
562         for (t = bce_devs; t->bce_name != NULL; ++t) {
563                 if (vid == t->bce_vid && did == t->bce_did && 
564                     (svid == t->bce_svid || t->bce_svid == PCI_ANY_ID) &&
565                     (sdid == t->bce_sdid || t->bce_sdid == PCI_ANY_ID)) {
566                         uint32_t revid = pci_read_config(dev, PCIR_REVID, 4);
567                         char *descbuf;
568
569                         descbuf = kmalloc(BCE_DEVDESC_MAX, M_TEMP, M_WAITOK);
570
571                         /* Print out the device identity. */
572                         ksnprintf(descbuf, BCE_DEVDESC_MAX, "%s (%c%d)",
573                                   t->bce_name,
574                                   ((revid & 0xf0) >> 4) + 'A', revid & 0xf);
575
576                         device_set_desc_copy(dev, descbuf);
577                         kfree(descbuf, M_TEMP);
578                         return 0;
579                 }
580         }
581         return ENXIO;
582 }
583
584
585 /****************************************************************************/
586 /* PCI Capabilities Probe Function.                                         */
587 /*                                                                          */
588 /* Walks the PCI capabiites list for the device to find what features are   */
589 /* supported.                                                               */
590 /*                                                                          */
591 /* Returns:                                                                 */
592 /*   None.                                                                  */
593 /****************************************************************************/
594 static void
595 bce_print_adapter_info(struct bce_softc *sc)
596 {
597         device_printf(sc->bce_dev, "ASIC (0x%08X); ", sc->bce_chipid);
598
599         kprintf("Rev (%c%d); ", ((BCE_CHIP_ID(sc) & 0xf000) >> 12) + 'A',
600                 ((BCE_CHIP_ID(sc) & 0x0ff0) >> 4));
601
602         /* Bus info. */
603         if (sc->bce_flags & BCE_PCIE_FLAG) {
604                 kprintf("Bus (PCIe x%d, ", sc->link_width);
605                 switch (sc->link_speed) {
606                 case 1:
607                         kprintf("2.5Gbps); ");
608                         break;
609                 case 2:
610                         kprintf("5Gbps); ");
611                         break;
612                 default:
613                         kprintf("Unknown link speed); ");
614                         break;
615                 }
616         } else {
617                 kprintf("Bus (PCI%s, %s, %dMHz); ",
618                     ((sc->bce_flags & BCE_PCIX_FLAG) ? "-X" : ""),
619                     ((sc->bce_flags & BCE_PCI_32BIT_FLAG) ? "32-bit" : "64-bit"),
620                     sc->bus_speed_mhz);
621         }
622
623         /* Firmware version and device features. */
624         kprintf("B/C (%s)", sc->bce_bc_ver);
625
626         if ((sc->bce_flags & BCE_MFW_ENABLE_FLAG) ||
627             (sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG)) {
628                 kprintf("; Flags(");
629                 if (sc->bce_flags & BCE_MFW_ENABLE_FLAG)
630                         kprintf("MFW[%s]", sc->bce_mfw_ver);
631                 if (sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG)
632                         kprintf(" 2.5G");
633                 kprintf(")");
634         }
635         kprintf("\n");
636 }
637
638
639 /****************************************************************************/
640 /* PCI Capabilities Probe Function.                                         */
641 /*                                                                          */
642 /* Walks the PCI capabiites list for the device to find what features are   */
643 /* supported.                                                               */
644 /*                                                                          */
645 /* Returns:                                                                 */
646 /*   None.                                                                  */
647 /****************************************************************************/
648 static void
649 bce_probe_pci_caps(struct bce_softc *sc)
650 {
651         device_t dev = sc->bce_dev;
652         uint8_t ptr;
653
654         if (pci_is_pcix(dev))
655                 sc->bce_cap_flags |= BCE_PCIX_CAPABLE_FLAG;
656
657         ptr = pci_get_pciecap_ptr(dev);
658         if (ptr) {
659                 uint16_t link_status = pci_read_config(dev, ptr + 0x12, 2);
660
661                 sc->link_speed = link_status & 0xf;
662                 sc->link_width = (link_status >> 4) & 0x3f;
663                 sc->bce_cap_flags |= BCE_PCIE_CAPABLE_FLAG;
664                 sc->bce_flags |= BCE_PCIE_FLAG;
665         }
666 }
667
668
669 /****************************************************************************/
670 /* Device attach function.                                                  */
671 /*                                                                          */
672 /* Allocates device resources, performs secondary chip identification,      */
673 /* resets and initializes the hardware, and initializes driver instance     */
674 /* variables.                                                               */
675 /*                                                                          */
676 /* Returns:                                                                 */
677 /*   0 on success, positive value on failure.                               */
678 /****************************************************************************/
679 static int
680 bce_attach(device_t dev)
681 {
682         struct bce_softc *sc = device_get_softc(dev);
683         struct ifnet *ifp = &sc->arpcom.ac_if;
684         uint32_t val;
685         u_int irq_flags;
686         void (*irq_handle)(void *);
687         int rid, rc = 0;
688         int i, j;
689         struct mii_probe_args mii_args;
690         uintptr_t mii_priv = 0;
691
692         sc->bce_dev = dev;
693         if_initname(ifp, device_get_name(dev), device_get_unit(dev));
694
695         pci_enable_busmaster(dev);
696
697         bce_probe_pci_caps(sc);
698
699         /* Allocate PCI memory resources. */
700         rid = PCIR_BAR(0);
701         sc->bce_res_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
702                                                  RF_ACTIVE | PCI_RF_DENSE);
703         if (sc->bce_res_mem == NULL) {
704                 device_printf(dev, "PCI memory allocation failed\n");
705                 return ENXIO;
706         }
707         sc->bce_btag = rman_get_bustag(sc->bce_res_mem);
708         sc->bce_bhandle = rman_get_bushandle(sc->bce_res_mem);
709
710         /* Allocate PCI IRQ resources. */
711         sc->bce_irq_type = pci_alloc_1intr(dev, bce_msi_enable,
712             &sc->bce_irq_rid, &irq_flags);
713
714         sc->bce_res_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ,
715             &sc->bce_irq_rid, irq_flags);
716         if (sc->bce_res_irq == NULL) {
717                 device_printf(dev, "PCI map interrupt failed\n");
718                 rc = ENXIO;
719                 goto fail;
720         }
721
722         /*
723          * Configure byte swap and enable indirect register access.
724          * Rely on CPU to do target byte swapping on big endian systems.
725          * Access to registers outside of PCI configurtion space are not
726          * valid until this is done.
727          */
728         pci_write_config(dev, BCE_PCICFG_MISC_CONFIG,
729                          BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
730                          BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP, 4);
731
732         /* Save ASIC revsion info. */
733         sc->bce_chipid =  REG_RD(sc, BCE_MISC_ID);
734
735         /* Weed out any non-production controller revisions. */
736         switch (BCE_CHIP_ID(sc)) {
737         case BCE_CHIP_ID_5706_A0:
738         case BCE_CHIP_ID_5706_A1:
739         case BCE_CHIP_ID_5708_A0:
740         case BCE_CHIP_ID_5708_B0:
741         case BCE_CHIP_ID_5709_A0:
742         case BCE_CHIP_ID_5709_B0:
743         case BCE_CHIP_ID_5709_B1:
744 #ifdef foo
745         /* 5709C B2 seems to work fine */
746         case BCE_CHIP_ID_5709_B2:
747 #endif
748                 device_printf(dev, "Unsupported chip id 0x%08x!\n",
749                               BCE_CHIP_ID(sc));
750                 rc = ENODEV;
751                 goto fail;
752         }
753
754         mii_priv |= BRGPHY_FLAG_WIRESPEED;
755         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
756                 if (BCE_CHIP_REV(sc) == BCE_CHIP_REV_Ax ||
757                     BCE_CHIP_REV(sc) == BCE_CHIP_REV_Bx)
758                         mii_priv |= BRGPHY_FLAG_NO_EARLYDAC;
759         } else {
760                 mii_priv |= BRGPHY_FLAG_BER_BUG;
761         }
762
763         if (sc->bce_irq_type == PCI_INTR_TYPE_LEGACY) {
764                 irq_handle = bce_intr_legacy;
765         } else if (sc->bce_irq_type == PCI_INTR_TYPE_MSI) {
766                 irq_handle = bce_intr_msi;
767                 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
768                         irq_handle = bce_intr_msi_oneshot;
769                         sc->bce_flags |= BCE_ONESHOT_MSI_FLAG;
770                 }
771         } else {
772                 panic("%s: unsupported intr type %d",
773                     device_get_nameunit(dev), sc->bce_irq_type);
774         }
775
776         /*
777          * Find the base address for shared memory access.
778          * Newer versions of bootcode use a signature and offset
779          * while older versions use a fixed address.
780          */
781         val = REG_RD_IND(sc, BCE_SHM_HDR_SIGNATURE);
782         if ((val & BCE_SHM_HDR_SIGNATURE_SIG_MASK) ==
783             BCE_SHM_HDR_SIGNATURE_SIG) {
784                 /* Multi-port devices use different offsets in shared memory. */
785                 sc->bce_shmem_base = REG_RD_IND(sc,
786                     BCE_SHM_HDR_ADDR_0 + (pci_get_function(sc->bce_dev) << 2));
787         } else {
788                 sc->bce_shmem_base = HOST_VIEW_SHMEM_BASE;
789         }
790         DBPRINT(sc, BCE_INFO, "bce_shmem_base = 0x%08X\n", sc->bce_shmem_base);
791
792         /* Fetch the bootcode revision. */
793         val = bce_shmem_rd(sc, BCE_DEV_INFO_BC_REV);
794         for (i = 0, j = 0; i < 3; i++) {
795                 uint8_t num;
796                 int k, skip0;
797
798                 num = (uint8_t)(val >> (24 - (i * 8)));
799                 for (k = 100, skip0 = 1; k >= 1; num %= k, k /= 10) {
800                         if (num >= k || !skip0 || k == 1) {
801                                 sc->bce_bc_ver[j++] = (num / k) + '0';
802                                 skip0 = 0;
803                         }
804                 }
805                 if (i != 2)
806                         sc->bce_bc_ver[j++] = '.';
807         }
808
809         /* Check if any management firwmare is running. */
810         val = bce_shmem_rd(sc, BCE_PORT_FEATURE);
811         if (val & BCE_PORT_FEATURE_ASF_ENABLED) {
812                 sc->bce_flags |= BCE_MFW_ENABLE_FLAG;
813
814                 /* Allow time for firmware to enter the running state. */
815                 for (i = 0; i < 30; i++) {
816                         val = bce_shmem_rd(sc, BCE_BC_STATE_CONDITION);
817                         if (val & BCE_CONDITION_MFW_RUN_MASK)
818                                 break;
819                         DELAY(10000);
820                 }
821         }
822
823         /* Check the current bootcode state. */
824         val = bce_shmem_rd(sc, BCE_BC_STATE_CONDITION) &
825             BCE_CONDITION_MFW_RUN_MASK;
826         if (val != BCE_CONDITION_MFW_RUN_UNKNOWN &&
827             val != BCE_CONDITION_MFW_RUN_NONE) {
828                 uint32_t addr = bce_shmem_rd(sc, BCE_MFW_VER_PTR);
829
830                 for (i = 0, j = 0; j < 3; j++) {
831                         val = bce_reg_rd_ind(sc, addr + j * 4);
832                         val = bswap32(val);
833                         memcpy(&sc->bce_mfw_ver[i], &val, 4);
834                         i += 4;
835                 }
836         }
837
838         /* Get PCI bus information (speed and type). */
839         val = REG_RD(sc, BCE_PCICFG_MISC_STATUS);
840         if (val & BCE_PCICFG_MISC_STATUS_PCIX_DET) {
841                 uint32_t clkreg;
842
843                 sc->bce_flags |= BCE_PCIX_FLAG;
844
845                 clkreg = REG_RD(sc, BCE_PCICFG_PCI_CLOCK_CONTROL_BITS) &
846                          BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET;
847                 switch (clkreg) {
848                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ:
849                         sc->bus_speed_mhz = 133;
850                         break;
851
852                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ:
853                         sc->bus_speed_mhz = 100;
854                         break;
855
856                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ:
857                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ:
858                         sc->bus_speed_mhz = 66;
859                         break;
860
861                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ:
862                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ:
863                         sc->bus_speed_mhz = 50;
864                         break;
865
866                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW:
867                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ:
868                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ:
869                         sc->bus_speed_mhz = 33;
870                         break;
871                 }
872         } else {
873                 if (val & BCE_PCICFG_MISC_STATUS_M66EN)
874                         sc->bus_speed_mhz = 66;
875                 else
876                         sc->bus_speed_mhz = 33;
877         }
878
879         if (val & BCE_PCICFG_MISC_STATUS_32BIT_DET)
880                 sc->bce_flags |= BCE_PCI_32BIT_FLAG;
881
882         /* Reset the controller. */
883         rc = bce_reset(sc, BCE_DRV_MSG_CODE_RESET);
884         if (rc != 0)
885                 goto fail;
886
887         /* Initialize the controller. */
888         rc = bce_chipinit(sc);
889         if (rc != 0) {
890                 device_printf(dev, "Controller initialization failed!\n");
891                 goto fail;
892         }
893
894         /* Perform NVRAM test. */
895         rc = bce_nvram_test(sc);
896         if (rc != 0) {
897                 device_printf(dev, "NVRAM test failed!\n");
898                 goto fail;
899         }
900
901         /* Fetch the permanent Ethernet MAC address. */
902         bce_get_mac_addr(sc);
903
904         /*
905          * Trip points control how many BDs
906          * should be ready before generating an
907          * interrupt while ticks control how long
908          * a BD can sit in the chain before
909          * generating an interrupt.  Set the default 
910          * values for the RX and TX rings.
911          */
912
913 #ifdef BCE_DRBUG
914         /* Force more frequent interrupts. */
915         sc->bce_tx_quick_cons_trip_int = 1;
916         sc->bce_tx_quick_cons_trip     = 1;
917         sc->bce_tx_ticks_int           = 0;
918         sc->bce_tx_ticks               = 0;
919
920         sc->bce_rx_quick_cons_trip_int = 1;
921         sc->bce_rx_quick_cons_trip     = 1;
922         sc->bce_rx_ticks_int           = 0;
923         sc->bce_rx_ticks               = 0;
924 #else
925         sc->bce_tx_quick_cons_trip_int = bce_tx_bds_int;
926         sc->bce_tx_quick_cons_trip     = bce_tx_bds;
927         sc->bce_tx_ticks_int           = bce_tx_ticks_int;
928         sc->bce_tx_ticks               = bce_tx_ticks;
929
930         sc->bce_rx_quick_cons_trip_int = bce_rx_bds_int;
931         sc->bce_rx_quick_cons_trip     = bce_rx_bds;
932         sc->bce_rx_ticks_int           = bce_rx_ticks_int;
933         sc->bce_rx_ticks               = bce_rx_ticks;
934 #endif
935
936         /* Update statistics once every second. */
937         sc->bce_stats_ticks = 1000000 & 0xffff00;
938
939         /* Find the media type for the adapter. */
940         bce_get_media(sc);
941
942         /* Allocate DMA memory resources. */
943         rc = bce_dma_alloc(sc);
944         if (rc != 0) {
945                 device_printf(dev, "DMA resource allocation failed!\n");
946                 goto fail;
947         }
948
949         /* Initialize the ifnet interface. */
950         ifp->if_softc = sc;
951         ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
952         ifp->if_ioctl = bce_ioctl;
953         ifp->if_start = bce_start;
954         ifp->if_init = bce_init;
955         ifp->if_watchdog = bce_watchdog;
956 #ifdef DEVICE_POLLING
957         ifp->if_poll = bce_poll;
958 #endif
959         ifp->if_mtu = ETHERMTU;
960         ifp->if_hwassist = BCE_CSUM_FEATURES | CSUM_TSO;
961         ifp->if_capabilities = BCE_IF_CAPABILITIES;
962         ifp->if_capenable = ifp->if_capabilities;
963         ifq_set_maxlen(&ifp->if_snd, USABLE_TX_BD(sc));
964         ifq_set_ready(&ifp->if_snd);
965
966         if (sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG)
967                 ifp->if_baudrate = IF_Gbps(2.5);
968         else
969                 ifp->if_baudrate = IF_Gbps(1);
970
971         /* Assume a standard 1500 byte MTU size for mbuf allocations. */
972         sc->mbuf_alloc_size  = MCLBYTES;
973
974         /*
975          * Look for our PHY.
976          */
977         mii_probe_args_init(&mii_args, bce_ifmedia_upd, bce_ifmedia_sts);
978         mii_args.mii_probemask = 1 << sc->bce_phy_addr;
979         mii_args.mii_privtag = MII_PRIVTAG_BRGPHY;
980         mii_args.mii_priv = mii_priv;
981
982         rc = mii_probe(dev, &sc->bce_miibus, &mii_args);
983         if (rc != 0) {
984                 device_printf(dev, "PHY probe failed!\n");
985                 goto fail;
986         }
987
988         /* Attach to the Ethernet interface list. */
989         ether_ifattach(ifp, sc->eaddr, NULL);
990
991         callout_init_mp(&sc->bce_tick_callout);
992         callout_init_mp(&sc->bce_pulse_callout);
993
994         /* Hookup IRQ last. */
995         rc = bus_setup_intr(dev, sc->bce_res_irq, INTR_MPSAFE, irq_handle, sc,
996                             &sc->bce_intrhand, ifp->if_serializer);
997         if (rc != 0) {
998                 device_printf(dev, "Failed to setup IRQ!\n");
999                 ether_ifdetach(ifp);
1000                 goto fail;
1001         }
1002
1003         ifp->if_cpuid = rman_get_cpuid(sc->bce_res_irq);
1004         KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus);
1005
1006         /* Print some important debugging info. */
1007         DBRUN(BCE_INFO, bce_dump_driver_state(sc));
1008
1009         /* Add the supported sysctls to the kernel. */
1010         bce_add_sysctls(sc);
1011
1012         /*
1013          * The chip reset earlier notified the bootcode that
1014          * a driver is present.  We now need to start our pulse
1015          * routine so that the bootcode is reminded that we're
1016          * still running.
1017          */
1018         bce_pulse(sc);
1019
1020         /* Get the firmware running so IPMI still works */
1021         bce_mgmt_init(sc);
1022
1023         if (bootverbose)
1024                 bce_print_adapter_info(sc);
1025
1026         return 0;
1027 fail:
1028         bce_detach(dev);
1029         return(rc);
1030 }
1031
1032
1033 /****************************************************************************/
1034 /* Device detach function.                                                  */
1035 /*                                                                          */
1036 /* Stops the controller, resets the controller, and releases resources.     */
1037 /*                                                                          */
1038 /* Returns:                                                                 */
1039 /*   0 on success, positive value on failure.                               */
1040 /****************************************************************************/
1041 static int
1042 bce_detach(device_t dev)
1043 {
1044         struct bce_softc *sc = device_get_softc(dev);
1045
1046         if (device_is_attached(dev)) {
1047                 struct ifnet *ifp = &sc->arpcom.ac_if;
1048                 uint32_t msg;
1049
1050                 /* Stop and reset the controller. */
1051                 lwkt_serialize_enter(ifp->if_serializer);
1052                 callout_stop(&sc->bce_pulse_callout);
1053                 bce_stop(sc);
1054                 if (sc->bce_flags & BCE_NO_WOL_FLAG)
1055                         msg = BCE_DRV_MSG_CODE_UNLOAD_LNK_DN;
1056                 else
1057                         msg = BCE_DRV_MSG_CODE_UNLOAD;
1058                 bce_reset(sc, msg);
1059                 bus_teardown_intr(dev, sc->bce_res_irq, sc->bce_intrhand);
1060                 lwkt_serialize_exit(ifp->if_serializer);
1061
1062                 ether_ifdetach(ifp);
1063         }
1064
1065         /* If we have a child device on the MII bus remove it too. */
1066         if (sc->bce_miibus)
1067                 device_delete_child(dev, sc->bce_miibus);
1068         bus_generic_detach(dev);
1069
1070         if (sc->bce_res_irq != NULL) {
1071                 bus_release_resource(dev, SYS_RES_IRQ, sc->bce_irq_rid,
1072                     sc->bce_res_irq);
1073         }
1074
1075         if (sc->bce_irq_type == PCI_INTR_TYPE_MSI)
1076                 pci_release_msi(dev);
1077
1078         if (sc->bce_res_mem != NULL) {
1079                 bus_release_resource(dev, SYS_RES_MEMORY, PCIR_BAR(0),
1080                                      sc->bce_res_mem);
1081         }
1082
1083         bce_dma_free(sc);
1084
1085         if (sc->bce_sysctl_tree != NULL)
1086                 sysctl_ctx_free(&sc->bce_sysctl_ctx);
1087
1088         return 0;
1089 }
1090
1091
1092 /****************************************************************************/
1093 /* Device shutdown function.                                                */
1094 /*                                                                          */
1095 /* Stops and resets the controller.                                         */
1096 /*                                                                          */
1097 /* Returns:                                                                 */
1098 /*   Nothing                                                                */
1099 /****************************************************************************/
1100 static void
1101 bce_shutdown(device_t dev)
1102 {
1103         struct bce_softc *sc = device_get_softc(dev);
1104         struct ifnet *ifp = &sc->arpcom.ac_if;
1105         uint32_t msg;
1106
1107         lwkt_serialize_enter(ifp->if_serializer);
1108         bce_stop(sc);
1109         if (sc->bce_flags & BCE_NO_WOL_FLAG)
1110                 msg = BCE_DRV_MSG_CODE_UNLOAD_LNK_DN;
1111         else
1112                 msg = BCE_DRV_MSG_CODE_UNLOAD;
1113         bce_reset(sc, msg);
1114         lwkt_serialize_exit(ifp->if_serializer);
1115 }
1116
1117
1118 /****************************************************************************/
1119 /* Indirect register read.                                                  */
1120 /*                                                                          */
1121 /* Reads NetXtreme II registers using an index/data register pair in PCI    */
1122 /* configuration space.  Using this mechanism avoids issues with posted     */
1123 /* reads but is much slower than memory-mapped I/O.                         */
1124 /*                                                                          */
1125 /* Returns:                                                                 */
1126 /*   The value of the register.                                             */
1127 /****************************************************************************/
1128 static uint32_t
1129 bce_reg_rd_ind(struct bce_softc *sc, uint32_t offset)
1130 {
1131         device_t dev = sc->bce_dev;
1132
1133         pci_write_config(dev, BCE_PCICFG_REG_WINDOW_ADDRESS, offset, 4);
1134 #ifdef BCE_DEBUG
1135         {
1136                 uint32_t val;
1137                 val = pci_read_config(dev, BCE_PCICFG_REG_WINDOW, 4);
1138                 DBPRINT(sc, BCE_EXCESSIVE,
1139                         "%s(); offset = 0x%08X, val = 0x%08X\n",
1140                         __func__, offset, val);
1141                 return val;
1142         }
1143 #else
1144         return pci_read_config(dev, BCE_PCICFG_REG_WINDOW, 4);
1145 #endif
1146 }
1147
1148
1149 /****************************************************************************/
1150 /* Indirect register write.                                                 */
1151 /*                                                                          */
1152 /* Writes NetXtreme II registers using an index/data register pair in PCI   */
1153 /* configuration space.  Using this mechanism avoids issues with posted     */
1154 /* writes but is muchh slower than memory-mapped I/O.                       */
1155 /*                                                                          */
1156 /* Returns:                                                                 */
1157 /*   Nothing.                                                               */
1158 /****************************************************************************/
1159 static void
1160 bce_reg_wr_ind(struct bce_softc *sc, uint32_t offset, uint32_t val)
1161 {
1162         device_t dev = sc->bce_dev;
1163
1164         DBPRINT(sc, BCE_EXCESSIVE, "%s(); offset = 0x%08X, val = 0x%08X\n",
1165                 __func__, offset, val);
1166
1167         pci_write_config(dev, BCE_PCICFG_REG_WINDOW_ADDRESS, offset, 4);
1168         pci_write_config(dev, BCE_PCICFG_REG_WINDOW, val, 4);
1169 }
1170
1171
1172 /****************************************************************************/
1173 /* Shared memory write.                                                     */
1174 /*                                                                          */
1175 /* Writes NetXtreme II shared memory region.                                */
1176 /*                                                                          */
1177 /* Returns:                                                                 */
1178 /*   Nothing.                                                               */
1179 /****************************************************************************/
1180 static void
1181 bce_shmem_wr(struct bce_softc *sc, uint32_t offset, uint32_t val)
1182 {
1183         bce_reg_wr_ind(sc, sc->bce_shmem_base + offset, val);
1184 }
1185
1186
1187 /****************************************************************************/
1188 /* Shared memory read.                                                      */
1189 /*                                                                          */
1190 /* Reads NetXtreme II shared memory region.                                 */
1191 /*                                                                          */
1192 /* Returns:                                                                 */
1193 /*   The 32 bit value read.                                                 */
1194 /****************************************************************************/
1195 static u32
1196 bce_shmem_rd(struct bce_softc *sc, uint32_t offset)
1197 {
1198         return bce_reg_rd_ind(sc, sc->bce_shmem_base + offset);
1199 }
1200
1201
1202 /****************************************************************************/
1203 /* Context memory write.                                                    */
1204 /*                                                                          */
1205 /* The NetXtreme II controller uses context memory to track connection      */
1206 /* information for L2 and higher network protocols.                         */
1207 /*                                                                          */
1208 /* Returns:                                                                 */
1209 /*   Nothing.                                                               */
1210 /****************************************************************************/
1211 static void
1212 bce_ctx_wr(struct bce_softc *sc, uint32_t cid_addr, uint32_t ctx_offset,
1213     uint32_t ctx_val)
1214 {
1215         uint32_t idx, offset = ctx_offset + cid_addr;
1216         uint32_t val, retry_cnt = 5;
1217
1218         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
1219             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
1220                 REG_WR(sc, BCE_CTX_CTX_DATA, ctx_val);
1221                 REG_WR(sc, BCE_CTX_CTX_CTRL, (offset | BCE_CTX_CTX_CTRL_WRITE_REQ));
1222
1223                 for (idx = 0; idx < retry_cnt; idx++) {
1224                         val = REG_RD(sc, BCE_CTX_CTX_CTRL);
1225                         if ((val & BCE_CTX_CTX_CTRL_WRITE_REQ) == 0)
1226                                 break;
1227                         DELAY(5);
1228                 }
1229
1230                 if (val & BCE_CTX_CTX_CTRL_WRITE_REQ) {
1231                         device_printf(sc->bce_dev,
1232                             "Unable to write CTX memory: "
1233                             "cid_addr = 0x%08X, offset = 0x%08X!\n",
1234                             cid_addr, ctx_offset);
1235                 }
1236         } else {
1237                 REG_WR(sc, BCE_CTX_DATA_ADR, offset);
1238                 REG_WR(sc, BCE_CTX_DATA, ctx_val);
1239         }
1240 }
1241
1242
1243 /****************************************************************************/
1244 /* PHY register read.                                                       */
1245 /*                                                                          */
1246 /* Implements register reads on the MII bus.                                */
1247 /*                                                                          */
1248 /* Returns:                                                                 */
1249 /*   The value of the register.                                             */
1250 /****************************************************************************/
1251 static int
1252 bce_miibus_read_reg(device_t dev, int phy, int reg)
1253 {
1254         struct bce_softc *sc = device_get_softc(dev);
1255         uint32_t val;
1256         int i;
1257
1258         /* Make sure we are accessing the correct PHY address. */
1259         KASSERT(phy == sc->bce_phy_addr,
1260             ("invalid phyno %d, should be %d\n", phy, sc->bce_phy_addr));
1261
1262         if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) {
1263                 val = REG_RD(sc, BCE_EMAC_MDIO_MODE);
1264                 val &= ~BCE_EMAC_MDIO_MODE_AUTO_POLL;
1265
1266                 REG_WR(sc, BCE_EMAC_MDIO_MODE, val);
1267                 REG_RD(sc, BCE_EMAC_MDIO_MODE);
1268
1269                 DELAY(40);
1270         }
1271
1272         val = BCE_MIPHY(phy) | BCE_MIREG(reg) |
1273               BCE_EMAC_MDIO_COMM_COMMAND_READ | BCE_EMAC_MDIO_COMM_DISEXT |
1274               BCE_EMAC_MDIO_COMM_START_BUSY;
1275         REG_WR(sc, BCE_EMAC_MDIO_COMM, val);
1276
1277         for (i = 0; i < BCE_PHY_TIMEOUT; i++) {
1278                 DELAY(10);
1279
1280                 val = REG_RD(sc, BCE_EMAC_MDIO_COMM);
1281                 if (!(val & BCE_EMAC_MDIO_COMM_START_BUSY)) {
1282                         DELAY(5);
1283
1284                         val = REG_RD(sc, BCE_EMAC_MDIO_COMM);
1285                         val &= BCE_EMAC_MDIO_COMM_DATA;
1286                         break;
1287                 }
1288         }
1289
1290         if (val & BCE_EMAC_MDIO_COMM_START_BUSY) {
1291                 if_printf(&sc->arpcom.ac_if,
1292                           "Error: PHY read timeout! phy = %d, reg = 0x%04X\n",
1293                           phy, reg);
1294                 val = 0x0;
1295         } else {
1296                 val = REG_RD(sc, BCE_EMAC_MDIO_COMM);
1297         }
1298
1299         DBPRINT(sc, BCE_EXCESSIVE,
1300                 "%s(): phy = %d, reg = 0x%04X, val = 0x%04X\n",
1301                 __func__, phy, (uint16_t)reg & 0xffff, (uint16_t) val & 0xffff);
1302
1303         if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) {
1304                 val = REG_RD(sc, BCE_EMAC_MDIO_MODE);
1305                 val |= BCE_EMAC_MDIO_MODE_AUTO_POLL;
1306
1307                 REG_WR(sc, BCE_EMAC_MDIO_MODE, val);
1308                 REG_RD(sc, BCE_EMAC_MDIO_MODE);
1309
1310                 DELAY(40);
1311         }
1312         return (val & 0xffff);
1313 }
1314
1315
1316 /****************************************************************************/
1317 /* PHY register write.                                                      */
1318 /*                                                                          */
1319 /* Implements register writes on the MII bus.                               */
1320 /*                                                                          */
1321 /* Returns:                                                                 */
1322 /*   The value of the register.                                             */
1323 /****************************************************************************/
1324 static int
1325 bce_miibus_write_reg(device_t dev, int phy, int reg, int val)
1326 {
1327         struct bce_softc *sc = device_get_softc(dev);
1328         uint32_t val1;
1329         int i;
1330
1331         /* Make sure we are accessing the correct PHY address. */
1332         KASSERT(phy == sc->bce_phy_addr,
1333             ("invalid phyno %d, should be %d\n", phy, sc->bce_phy_addr));
1334
1335         DBPRINT(sc, BCE_EXCESSIVE,
1336                 "%s(): phy = %d, reg = 0x%04X, val = 0x%04X\n",
1337                 __func__, phy, (uint16_t)(reg & 0xffff),
1338                 (uint16_t)(val & 0xffff));
1339
1340         if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) {
1341                 val1 = REG_RD(sc, BCE_EMAC_MDIO_MODE);
1342                 val1 &= ~BCE_EMAC_MDIO_MODE_AUTO_POLL;
1343
1344                 REG_WR(sc, BCE_EMAC_MDIO_MODE, val1);
1345                 REG_RD(sc, BCE_EMAC_MDIO_MODE);
1346
1347                 DELAY(40);
1348         }
1349
1350         val1 = BCE_MIPHY(phy) | BCE_MIREG(reg) | val |
1351                 BCE_EMAC_MDIO_COMM_COMMAND_WRITE |
1352                 BCE_EMAC_MDIO_COMM_START_BUSY | BCE_EMAC_MDIO_COMM_DISEXT;
1353         REG_WR(sc, BCE_EMAC_MDIO_COMM, val1);
1354
1355         for (i = 0; i < BCE_PHY_TIMEOUT; i++) {
1356                 DELAY(10);
1357
1358                 val1 = REG_RD(sc, BCE_EMAC_MDIO_COMM);
1359                 if (!(val1 & BCE_EMAC_MDIO_COMM_START_BUSY)) {
1360                         DELAY(5);
1361                         break;
1362                 }
1363         }
1364
1365         if (val1 & BCE_EMAC_MDIO_COMM_START_BUSY)
1366                 if_printf(&sc->arpcom.ac_if, "PHY write timeout!\n");
1367
1368         if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) {
1369                 val1 = REG_RD(sc, BCE_EMAC_MDIO_MODE);
1370                 val1 |= BCE_EMAC_MDIO_MODE_AUTO_POLL;
1371
1372                 REG_WR(sc, BCE_EMAC_MDIO_MODE, val1);
1373                 REG_RD(sc, BCE_EMAC_MDIO_MODE);
1374
1375                 DELAY(40);
1376         }
1377         return 0;
1378 }
1379
1380
1381 /****************************************************************************/
1382 /* MII bus status change.                                                   */
1383 /*                                                                          */
1384 /* Called by the MII bus driver when the PHY establishes link to set the    */
1385 /* MAC interface registers.                                                 */
1386 /*                                                                          */
1387 /* Returns:                                                                 */
1388 /*   Nothing.                                                               */
1389 /****************************************************************************/
1390 static void
1391 bce_miibus_statchg(device_t dev)
1392 {
1393         struct bce_softc *sc = device_get_softc(dev);
1394         struct mii_data *mii = device_get_softc(sc->bce_miibus);
1395
1396         DBPRINT(sc, BCE_INFO, "mii_media_active = 0x%08X\n",
1397                 mii->mii_media_active);
1398
1399 #ifdef BCE_DEBUG
1400         /* Decode the interface media flags. */
1401         if_printf(&sc->arpcom.ac_if, "Media: ( ");
1402         switch(IFM_TYPE(mii->mii_media_active)) {
1403         case IFM_ETHER:
1404                 kprintf("Ethernet )");
1405                 break;
1406         default:
1407                 kprintf("Unknown )");
1408                 break;
1409         }
1410
1411         kprintf(" Media Options: ( ");
1412         switch(IFM_SUBTYPE(mii->mii_media_active)) {
1413         case IFM_AUTO:
1414                 kprintf("Autoselect )");
1415                 break;
1416         case IFM_MANUAL:
1417                 kprintf("Manual )");
1418                 break;
1419         case IFM_NONE:
1420                 kprintf("None )");
1421                 break;
1422         case IFM_10_T:
1423                 kprintf("10Base-T )");
1424                 break;
1425         case IFM_100_TX:
1426                 kprintf("100Base-TX )");
1427                 break;
1428         case IFM_1000_SX:
1429                 kprintf("1000Base-SX )");
1430                 break;
1431         case IFM_1000_T:
1432                 kprintf("1000Base-T )");
1433                 break;
1434         default:
1435                 kprintf("Other )");
1436                 break;
1437         }
1438
1439         kprintf(" Global Options: (");
1440         if (mii->mii_media_active & IFM_FDX)
1441                 kprintf(" FullDuplex");
1442         if (mii->mii_media_active & IFM_HDX)
1443                 kprintf(" HalfDuplex");
1444         if (mii->mii_media_active & IFM_LOOP)
1445                 kprintf(" Loopback");
1446         if (mii->mii_media_active & IFM_FLAG0)
1447                 kprintf(" Flag0");
1448         if (mii->mii_media_active & IFM_FLAG1)
1449                 kprintf(" Flag1");
1450         if (mii->mii_media_active & IFM_FLAG2)
1451                 kprintf(" Flag2");
1452         kprintf(" )\n");
1453 #endif
1454
1455         BCE_CLRBIT(sc, BCE_EMAC_MODE, BCE_EMAC_MODE_PORT);
1456
1457         /*
1458          * Set MII or GMII interface based on the speed negotiated
1459          * by the PHY.
1460          */
1461         if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T || 
1462             IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) {
1463                 DBPRINT(sc, BCE_INFO, "Setting GMII interface.\n");
1464                 BCE_SETBIT(sc, BCE_EMAC_MODE, BCE_EMAC_MODE_PORT_GMII);
1465         } else {
1466                 DBPRINT(sc, BCE_INFO, "Setting MII interface.\n");
1467                 BCE_SETBIT(sc, BCE_EMAC_MODE, BCE_EMAC_MODE_PORT_MII);
1468         }
1469
1470         /*
1471          * Set half or full duplex based on the duplicity negotiated
1472          * by the PHY.
1473          */
1474         if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
1475                 DBPRINT(sc, BCE_INFO, "Setting Full-Duplex interface.\n");
1476                 BCE_CLRBIT(sc, BCE_EMAC_MODE, BCE_EMAC_MODE_HALF_DUPLEX);
1477         } else {
1478                 DBPRINT(sc, BCE_INFO, "Setting Half-Duplex interface.\n");
1479                 BCE_SETBIT(sc, BCE_EMAC_MODE, BCE_EMAC_MODE_HALF_DUPLEX);
1480         }
1481 }
1482
1483
1484 /****************************************************************************/
1485 /* Acquire NVRAM lock.                                                      */
1486 /*                                                                          */
1487 /* Before the NVRAM can be accessed the caller must acquire an NVRAM lock.  */
1488 /* Locks 0 and 2 are reserved, lock 1 is used by firmware and lock 2 is     */
1489 /* for use by the driver.                                                   */
1490 /*                                                                          */
1491 /* Returns:                                                                 */
1492 /*   0 on success, positive value on failure.                               */
1493 /****************************************************************************/
1494 static int
1495 bce_acquire_nvram_lock(struct bce_softc *sc)
1496 {
1497         uint32_t val;
1498         int j;
1499
1500         DBPRINT(sc, BCE_VERBOSE, "Acquiring NVRAM lock.\n");
1501
1502         /* Request access to the flash interface. */
1503         REG_WR(sc, BCE_NVM_SW_ARB, BCE_NVM_SW_ARB_ARB_REQ_SET2);
1504         for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
1505                 val = REG_RD(sc, BCE_NVM_SW_ARB);
1506                 if (val & BCE_NVM_SW_ARB_ARB_ARB2)
1507                         break;
1508
1509                 DELAY(5);
1510         }
1511
1512         if (j >= NVRAM_TIMEOUT_COUNT) {
1513                 DBPRINT(sc, BCE_WARN, "Timeout acquiring NVRAM lock!\n");
1514                 return EBUSY;
1515         }
1516         return 0;
1517 }
1518
1519
1520 /****************************************************************************/
1521 /* Release NVRAM lock.                                                      */
1522 /*                                                                          */
1523 /* When the caller is finished accessing NVRAM the lock must be released.   */
1524 /* Locks 0 and 2 are reserved, lock 1 is used by firmware and lock 2 is     */
1525 /* for use by the driver.                                                   */
1526 /*                                                                          */
1527 /* Returns:                                                                 */
1528 /*   0 on success, positive value on failure.                               */
1529 /****************************************************************************/
1530 static int
1531 bce_release_nvram_lock(struct bce_softc *sc)
1532 {
1533         int j;
1534         uint32_t val;
1535
1536         DBPRINT(sc, BCE_VERBOSE, "Releasing NVRAM lock.\n");
1537
1538         /*
1539          * Relinquish nvram interface.
1540          */
1541         REG_WR(sc, BCE_NVM_SW_ARB, BCE_NVM_SW_ARB_ARB_REQ_CLR2);
1542
1543         for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
1544                 val = REG_RD(sc, BCE_NVM_SW_ARB);
1545                 if (!(val & BCE_NVM_SW_ARB_ARB_ARB2))
1546                         break;
1547
1548                 DELAY(5);
1549         }
1550
1551         if (j >= NVRAM_TIMEOUT_COUNT) {
1552                 DBPRINT(sc, BCE_WARN, "Timeout reeasing NVRAM lock!\n");
1553                 return EBUSY;
1554         }
1555         return 0;
1556 }
1557
1558
1559 /****************************************************************************/
1560 /* Enable NVRAM access.                                                     */
1561 /*                                                                          */
1562 /* Before accessing NVRAM for read or write operations the caller must      */
1563 /* enabled NVRAM access.                                                    */
1564 /*                                                                          */
1565 /* Returns:                                                                 */
1566 /*   Nothing.                                                               */
1567 /****************************************************************************/
1568 static void
1569 bce_enable_nvram_access(struct bce_softc *sc)
1570 {
1571         uint32_t val;
1572
1573         DBPRINT(sc, BCE_VERBOSE, "Enabling NVRAM access.\n");
1574
1575         val = REG_RD(sc, BCE_NVM_ACCESS_ENABLE);
1576         /* Enable both bits, even on read. */
1577         REG_WR(sc, BCE_NVM_ACCESS_ENABLE,
1578                val | BCE_NVM_ACCESS_ENABLE_EN | BCE_NVM_ACCESS_ENABLE_WR_EN);
1579 }
1580
1581
1582 /****************************************************************************/
1583 /* Disable NVRAM access.                                                    */
1584 /*                                                                          */
1585 /* When the caller is finished accessing NVRAM access must be disabled.     */
1586 /*                                                                          */
1587 /* Returns:                                                                 */
1588 /*   Nothing.                                                               */
1589 /****************************************************************************/
1590 static void
1591 bce_disable_nvram_access(struct bce_softc *sc)
1592 {
1593         uint32_t val;
1594
1595         DBPRINT(sc, BCE_VERBOSE, "Disabling NVRAM access.\n");
1596
1597         val = REG_RD(sc, BCE_NVM_ACCESS_ENABLE);
1598
1599         /* Disable both bits, even after read. */
1600         REG_WR(sc, BCE_NVM_ACCESS_ENABLE,
1601                val & ~(BCE_NVM_ACCESS_ENABLE_EN | BCE_NVM_ACCESS_ENABLE_WR_EN));
1602 }
1603
1604
1605 /****************************************************************************/
1606 /* Read a dword (32 bits) from NVRAM.                                       */
1607 /*                                                                          */
1608 /* Read a 32 bit word from NVRAM.  The caller is assumed to have already    */
1609 /* obtained the NVRAM lock and enabled the controller for NVRAM access.     */
1610 /*                                                                          */
1611 /* Returns:                                                                 */
1612 /*   0 on success and the 32 bit value read, positive value on failure.     */
1613 /****************************************************************************/
1614 static int
1615 bce_nvram_read_dword(struct bce_softc *sc, uint32_t offset, uint8_t *ret_val,
1616                      uint32_t cmd_flags)
1617 {
1618         uint32_t cmd;
1619         int i, rc = 0;
1620
1621         /* Build the command word. */
1622         cmd = BCE_NVM_COMMAND_DOIT | cmd_flags;
1623
1624         /* Calculate the offset for buffered flash. */
1625         if (sc->bce_flash_info->flags & BCE_NV_TRANSLATE) {
1626                 offset = ((offset / sc->bce_flash_info->page_size) <<
1627                           sc->bce_flash_info->page_bits) +
1628                          (offset % sc->bce_flash_info->page_size);
1629         }
1630
1631         /*
1632          * Clear the DONE bit separately, set the address to read,
1633          * and issue the read.
1634          */
1635         REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_DONE);
1636         REG_WR(sc, BCE_NVM_ADDR, offset & BCE_NVM_ADDR_NVM_ADDR_VALUE);
1637         REG_WR(sc, BCE_NVM_COMMAND, cmd);
1638
1639         /* Wait for completion. */
1640         for (i = 0; i < NVRAM_TIMEOUT_COUNT; i++) {
1641                 uint32_t val;
1642
1643                 DELAY(5);
1644
1645                 val = REG_RD(sc, BCE_NVM_COMMAND);
1646                 if (val & BCE_NVM_COMMAND_DONE) {
1647                         val = REG_RD(sc, BCE_NVM_READ);
1648
1649                         val = be32toh(val);
1650                         memcpy(ret_val, &val, 4);
1651                         break;
1652                 }
1653         }
1654
1655         /* Check for errors. */
1656         if (i >= NVRAM_TIMEOUT_COUNT) {
1657                 if_printf(&sc->arpcom.ac_if,
1658                           "Timeout error reading NVRAM at offset 0x%08X!\n",
1659                           offset);
1660                 rc = EBUSY;
1661         }
1662         return rc;
1663 }
1664
1665
1666 /****************************************************************************/
1667 /* Initialize NVRAM access.                                                 */
1668 /*                                                                          */
1669 /* Identify the NVRAM device in use and prepare the NVRAM interface to      */
1670 /* access that device.                                                      */
1671 /*                                                                          */
1672 /* Returns:                                                                 */
1673 /*   0 on success, positive value on failure.                               */
1674 /****************************************************************************/
1675 static int
1676 bce_init_nvram(struct bce_softc *sc)
1677 {
1678         uint32_t val;
1679         int j, entry_count, rc = 0;
1680         const struct flash_spec *flash;
1681
1682         DBPRINT(sc, BCE_VERBOSE_RESET, "Entering %s()\n", __func__);
1683
1684         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
1685             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
1686                 sc->bce_flash_info = &flash_5709;
1687                 goto bce_init_nvram_get_flash_size;
1688         }
1689
1690         /* Determine the selected interface. */
1691         val = REG_RD(sc, BCE_NVM_CFG1);
1692
1693         entry_count = sizeof(flash_table) / sizeof(struct flash_spec);
1694
1695         /*
1696          * Flash reconfiguration is required to support additional
1697          * NVRAM devices not directly supported in hardware.
1698          * Check if the flash interface was reconfigured
1699          * by the bootcode.
1700          */
1701
1702         if (val & 0x40000000) {
1703                 /* Flash interface reconfigured by bootcode. */
1704
1705                 DBPRINT(sc, BCE_INFO_LOAD, 
1706                         "%s(): Flash WAS reconfigured.\n", __func__);
1707
1708                 for (j = 0, flash = flash_table; j < entry_count;
1709                      j++, flash++) {
1710                         if ((val & FLASH_BACKUP_STRAP_MASK) ==
1711                             (flash->config1 & FLASH_BACKUP_STRAP_MASK)) {
1712                                 sc->bce_flash_info = flash;
1713                                 break;
1714                         }
1715                 }
1716         } else {
1717                 /* Flash interface not yet reconfigured. */
1718                 uint32_t mask;
1719
1720                 DBPRINT(sc, BCE_INFO_LOAD, 
1721                         "%s(): Flash was NOT reconfigured.\n", __func__);
1722
1723                 if (val & (1 << 23))
1724                         mask = FLASH_BACKUP_STRAP_MASK;
1725                 else
1726                         mask = FLASH_STRAP_MASK;
1727
1728                 /* Look for the matching NVRAM device configuration data. */
1729                 for (j = 0, flash = flash_table; j < entry_count;
1730                      j++, flash++) {
1731                         /* Check if the device matches any of the known devices. */
1732                         if ((val & mask) == (flash->strapping & mask)) {
1733                                 /* Found a device match. */
1734                                 sc->bce_flash_info = flash;
1735
1736                                 /* Request access to the flash interface. */
1737                                 rc = bce_acquire_nvram_lock(sc);
1738                                 if (rc != 0)
1739                                         return rc;
1740
1741                                 /* Reconfigure the flash interface. */
1742                                 bce_enable_nvram_access(sc);
1743                                 REG_WR(sc, BCE_NVM_CFG1, flash->config1);
1744                                 REG_WR(sc, BCE_NVM_CFG2, flash->config2);
1745                                 REG_WR(sc, BCE_NVM_CFG3, flash->config3);
1746                                 REG_WR(sc, BCE_NVM_WRITE1, flash->write1);
1747                                 bce_disable_nvram_access(sc);
1748                                 bce_release_nvram_lock(sc);
1749                                 break;
1750                         }
1751                 }
1752         }
1753
1754         /* Check if a matching device was found. */
1755         if (j == entry_count) {
1756                 sc->bce_flash_info = NULL;
1757                 if_printf(&sc->arpcom.ac_if, "Unknown Flash NVRAM found!\n");
1758                 return ENODEV;
1759         }
1760
1761 bce_init_nvram_get_flash_size:
1762         /* Write the flash config data to the shared memory interface. */
1763         val = bce_shmem_rd(sc, BCE_SHARED_HW_CFG_CONFIG2) &
1764             BCE_SHARED_HW_CFG2_NVM_SIZE_MASK;
1765         if (val)
1766                 sc->bce_flash_size = val;
1767         else
1768                 sc->bce_flash_size = sc->bce_flash_info->total_size;
1769
1770         DBPRINT(sc, BCE_INFO_LOAD, "%s() flash->total_size = 0x%08X\n",
1771                 __func__, sc->bce_flash_info->total_size);
1772
1773         DBPRINT(sc, BCE_VERBOSE_RESET, "Exiting %s()\n", __func__);
1774
1775         return rc;
1776 }
1777
1778
1779 /****************************************************************************/
1780 /* Read an arbitrary range of data from NVRAM.                              */
1781 /*                                                                          */
1782 /* Prepares the NVRAM interface for access and reads the requested data     */
1783 /* into the supplied buffer.                                                */
1784 /*                                                                          */
1785 /* Returns:                                                                 */
1786 /*   0 on success and the data read, positive value on failure.             */
1787 /****************************************************************************/
1788 static int
1789 bce_nvram_read(struct bce_softc *sc, uint32_t offset, uint8_t *ret_buf,
1790                int buf_size)
1791 {
1792         uint32_t cmd_flags, offset32, len32, extra;
1793         int rc = 0;
1794
1795         if (buf_size == 0)
1796                 return 0;
1797
1798         /* Request access to the flash interface. */
1799         rc = bce_acquire_nvram_lock(sc);
1800         if (rc != 0)
1801                 return rc;
1802
1803         /* Enable access to flash interface */
1804         bce_enable_nvram_access(sc);
1805
1806         len32 = buf_size;
1807         offset32 = offset;
1808         extra = 0;
1809
1810         cmd_flags = 0;
1811
1812         /* XXX should we release nvram lock if read_dword() fails? */
1813         if (offset32 & 3) {
1814                 uint8_t buf[4];
1815                 uint32_t pre_len;
1816
1817                 offset32 &= ~3;
1818                 pre_len = 4 - (offset & 3);
1819
1820                 if (pre_len >= len32) {
1821                         pre_len = len32;
1822                         cmd_flags = BCE_NVM_COMMAND_FIRST | BCE_NVM_COMMAND_LAST;
1823                 } else {
1824                         cmd_flags = BCE_NVM_COMMAND_FIRST;
1825                 }
1826
1827                 rc = bce_nvram_read_dword(sc, offset32, buf, cmd_flags);
1828                 if (rc)
1829                         return rc;
1830
1831                 memcpy(ret_buf, buf + (offset & 3), pre_len);
1832
1833                 offset32 += 4;
1834                 ret_buf += pre_len;
1835                 len32 -= pre_len;
1836         }
1837
1838         if (len32 & 3) {
1839                 extra = 4 - (len32 & 3);
1840                 len32 = (len32 + 4) & ~3;
1841         }
1842
1843         if (len32 == 4) {
1844                 uint8_t buf[4];
1845
1846                 if (cmd_flags)
1847                         cmd_flags = BCE_NVM_COMMAND_LAST;
1848                 else
1849                         cmd_flags = BCE_NVM_COMMAND_FIRST |
1850                                     BCE_NVM_COMMAND_LAST;
1851
1852                 rc = bce_nvram_read_dword(sc, offset32, buf, cmd_flags);
1853
1854                 memcpy(ret_buf, buf, 4 - extra);
1855         } else if (len32 > 0) {
1856                 uint8_t buf[4];
1857
1858                 /* Read the first word. */
1859                 if (cmd_flags)
1860                         cmd_flags = 0;
1861                 else
1862                         cmd_flags = BCE_NVM_COMMAND_FIRST;
1863
1864                 rc = bce_nvram_read_dword(sc, offset32, ret_buf, cmd_flags);
1865
1866                 /* Advance to the next dword. */
1867                 offset32 += 4;
1868                 ret_buf += 4;
1869                 len32 -= 4;
1870
1871                 while (len32 > 4 && rc == 0) {
1872                         rc = bce_nvram_read_dword(sc, offset32, ret_buf, 0);
1873
1874                         /* Advance to the next dword. */
1875                         offset32 += 4;
1876                         ret_buf += 4;
1877                         len32 -= 4;
1878                 }
1879
1880                 if (rc)
1881                         goto bce_nvram_read_locked_exit;
1882
1883                 cmd_flags = BCE_NVM_COMMAND_LAST;
1884                 rc = bce_nvram_read_dword(sc, offset32, buf, cmd_flags);
1885
1886                 memcpy(ret_buf, buf, 4 - extra);
1887         }
1888
1889 bce_nvram_read_locked_exit:
1890         /* Disable access to flash interface and release the lock. */
1891         bce_disable_nvram_access(sc);
1892         bce_release_nvram_lock(sc);
1893
1894         return rc;
1895 }
1896
1897
1898 /****************************************************************************/
1899 /* Verifies that NVRAM is accessible and contains valid data.               */
1900 /*                                                                          */
1901 /* Reads the configuration data from NVRAM and verifies that the CRC is     */
1902 /* correct.                                                                 */
1903 /*                                                                          */
1904 /* Returns:                                                                 */
1905 /*   0 on success, positive value on failure.                               */
1906 /****************************************************************************/
1907 static int
1908 bce_nvram_test(struct bce_softc *sc)
1909 {
1910         uint32_t buf[BCE_NVRAM_SIZE / 4];
1911         uint32_t magic, csum;
1912         uint8_t *data = (uint8_t *)buf;
1913         int rc = 0;
1914
1915         /*
1916          * Check that the device NVRAM is valid by reading
1917          * the magic value at offset 0.
1918          */
1919         rc = bce_nvram_read(sc, 0, data, 4);
1920         if (rc != 0)
1921                 return rc;
1922
1923         magic = be32toh(buf[0]);
1924         if (magic != BCE_NVRAM_MAGIC) {
1925                 if_printf(&sc->arpcom.ac_if,
1926                           "Invalid NVRAM magic value! Expected: 0x%08X, "
1927                           "Found: 0x%08X\n", BCE_NVRAM_MAGIC, magic);
1928                 return ENODEV;
1929         }
1930
1931         /*
1932          * Verify that the device NVRAM includes valid
1933          * configuration data.
1934          */
1935         rc = bce_nvram_read(sc, 0x100, data, BCE_NVRAM_SIZE);
1936         if (rc != 0)
1937                 return rc;
1938
1939         csum = ether_crc32_le(data, 0x100);
1940         if (csum != BCE_CRC32_RESIDUAL) {
1941                 if_printf(&sc->arpcom.ac_if,
1942                           "Invalid Manufacturing Information NVRAM CRC! "
1943                           "Expected: 0x%08X, Found: 0x%08X\n",
1944                           BCE_CRC32_RESIDUAL, csum);
1945                 return ENODEV;
1946         }
1947
1948         csum = ether_crc32_le(data + 0x100, 0x100);
1949         if (csum != BCE_CRC32_RESIDUAL) {
1950                 if_printf(&sc->arpcom.ac_if,
1951                           "Invalid Feature Configuration Information "
1952                           "NVRAM CRC! Expected: 0x%08X, Found: 08%08X\n",
1953                           BCE_CRC32_RESIDUAL, csum);
1954                 rc = ENODEV;
1955         }
1956         return rc;
1957 }
1958
1959
1960 /****************************************************************************/
1961 /* Identifies the current media type of the controller and sets the PHY     */
1962 /* address.                                                                 */
1963 /*                                                                          */
1964 /* Returns:                                                                 */
1965 /*   Nothing.                                                               */
1966 /****************************************************************************/
1967 static void
1968 bce_get_media(struct bce_softc *sc)
1969 {
1970         uint32_t val;
1971
1972         sc->bce_phy_addr = 1;
1973
1974         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
1975             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
1976                 uint32_t val = REG_RD(sc, BCE_MISC_DUAL_MEDIA_CTRL);
1977                 uint32_t bond_id = val & BCE_MISC_DUAL_MEDIA_CTRL_BOND_ID;
1978                 uint32_t strap;
1979
1980                 /*
1981                  * The BCM5709S is software configurable
1982                  * for Copper or SerDes operation.
1983                  */
1984                 if (bond_id == BCE_MISC_DUAL_MEDIA_CTRL_BOND_ID_C) {
1985                         return;
1986                 } else if (bond_id == BCE_MISC_DUAL_MEDIA_CTRL_BOND_ID_S) {
1987                         sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG;
1988                         return;
1989                 }
1990
1991                 if (val & BCE_MISC_DUAL_MEDIA_CTRL_STRAP_OVERRIDE) {
1992                         strap = (val & BCE_MISC_DUAL_MEDIA_CTRL_PHY_CTRL) >> 21;
1993                 } else {
1994                         strap =
1995                         (val & BCE_MISC_DUAL_MEDIA_CTRL_PHY_CTRL_STRAP) >> 8;
1996                 }
1997
1998                 if (pci_get_function(sc->bce_dev) == 0) {
1999                         switch (strap) {
2000                         case 0x4:
2001                         case 0x5:
2002                         case 0x6:
2003                                 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG;
2004                                 break;
2005                         }
2006                 } else {
2007                         switch (strap) {
2008                         case 0x1:
2009                         case 0x2:
2010                         case 0x4:
2011                                 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG;
2012                                 break;
2013                         }
2014                 }
2015         } else if (BCE_CHIP_BOND_ID(sc) & BCE_CHIP_BOND_ID_SERDES_BIT) {
2016                 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG;
2017         }
2018
2019         if (sc->bce_phy_flags & BCE_PHY_SERDES_FLAG) {
2020                 sc->bce_flags |= BCE_NO_WOL_FLAG;
2021                 if (BCE_CHIP_NUM(sc) != BCE_CHIP_NUM_5706) {
2022                         sc->bce_phy_addr = 2;
2023                         val = bce_shmem_rd(sc, BCE_SHARED_HW_CFG_CONFIG);
2024                         if (val & BCE_SHARED_HW_CFG_PHY_2_5G)
2025                                 sc->bce_phy_flags |= BCE_PHY_2_5G_CAPABLE_FLAG;
2026                 }
2027         } else if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5706) ||
2028             (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5708)) {
2029                 sc->bce_phy_flags |= BCE_PHY_CRC_FIX_FLAG;
2030         }
2031 }
2032
2033
2034 /****************************************************************************/
2035 /* Free any DMA memory owned by the driver.                                 */
2036 /*                                                                          */
2037 /* Scans through each data structre that requires DMA memory and frees      */
2038 /* the memory if allocated.                                                 */
2039 /*                                                                          */
2040 /* Returns:                                                                 */
2041 /*   Nothing.                                                               */
2042 /****************************************************************************/
2043 static void
2044 bce_dma_free(struct bce_softc *sc)
2045 {
2046         int i;
2047
2048         /* Destroy the status block. */
2049         if (sc->status_tag != NULL) {
2050                 if (sc->status_block != NULL) {
2051                         bus_dmamap_unload(sc->status_tag, sc->status_map);
2052                         bus_dmamem_free(sc->status_tag, sc->status_block,
2053                                         sc->status_map);
2054                 }
2055                 bus_dma_tag_destroy(sc->status_tag);
2056         }
2057
2058         /* Destroy the statistics block. */
2059         if (sc->stats_tag != NULL) {
2060                 if (sc->stats_block != NULL) {
2061                         bus_dmamap_unload(sc->stats_tag, sc->stats_map);
2062                         bus_dmamem_free(sc->stats_tag, sc->stats_block,
2063                                         sc->stats_map);
2064                 }
2065                 bus_dma_tag_destroy(sc->stats_tag);
2066         }
2067
2068         /* Destroy the CTX DMA stuffs. */
2069         if (sc->ctx_tag != NULL) {
2070                 for (i = 0; i < sc->ctx_pages; i++) {
2071                         if (sc->ctx_block[i] != NULL) {
2072                                 bus_dmamap_unload(sc->ctx_tag, sc->ctx_map[i]);
2073                                 bus_dmamem_free(sc->ctx_tag, sc->ctx_block[i],
2074                                                 sc->ctx_map[i]);
2075                         }
2076                 }
2077                 bus_dma_tag_destroy(sc->ctx_tag);
2078         }
2079
2080         /* Destroy the TX buffer descriptor DMA stuffs. */
2081         if (sc->tx_bd_chain_tag != NULL) {
2082                 for (i = 0; i < sc->tx_pages; i++) {
2083                         if (sc->tx_bd_chain[i] != NULL) {
2084                                 bus_dmamap_unload(sc->tx_bd_chain_tag,
2085                                                   sc->tx_bd_chain_map[i]);
2086                                 bus_dmamem_free(sc->tx_bd_chain_tag,
2087                                                 sc->tx_bd_chain[i],
2088                                                 sc->tx_bd_chain_map[i]);
2089                         }
2090                 }
2091                 bus_dma_tag_destroy(sc->tx_bd_chain_tag);
2092         }
2093
2094         /* Destroy the RX buffer descriptor DMA stuffs. */
2095         if (sc->rx_bd_chain_tag != NULL) {
2096                 for (i = 0; i < sc->rx_pages; i++) {
2097                         if (sc->rx_bd_chain[i] != NULL) {
2098                                 bus_dmamap_unload(sc->rx_bd_chain_tag,
2099                                                   sc->rx_bd_chain_map[i]);
2100                                 bus_dmamem_free(sc->rx_bd_chain_tag,
2101                                                 sc->rx_bd_chain[i],
2102                                                 sc->rx_bd_chain_map[i]);
2103                         }
2104                 }
2105                 bus_dma_tag_destroy(sc->rx_bd_chain_tag);
2106         }
2107
2108         /* Destroy the TX mbuf DMA stuffs. */
2109         if (sc->tx_mbuf_tag != NULL) {
2110                 for (i = 0; i < TOTAL_TX_BD(sc); i++) {
2111                         /* Must have been unloaded in bce_stop() */
2112                         KKASSERT(sc->tx_mbuf_ptr[i] == NULL);
2113                         bus_dmamap_destroy(sc->tx_mbuf_tag,
2114                                            sc->tx_mbuf_map[i]);
2115                 }
2116                 bus_dma_tag_destroy(sc->tx_mbuf_tag);
2117         }
2118
2119         /* Destroy the RX mbuf DMA stuffs. */
2120         if (sc->rx_mbuf_tag != NULL) {
2121                 for (i = 0; i < TOTAL_RX_BD(sc); i++) {
2122                         /* Must have been unloaded in bce_stop() */
2123                         KKASSERT(sc->rx_mbuf_ptr[i] == NULL);
2124                         bus_dmamap_destroy(sc->rx_mbuf_tag,
2125                                            sc->rx_mbuf_map[i]);
2126                 }
2127                 bus_dmamap_destroy(sc->rx_mbuf_tag, sc->rx_mbuf_tmpmap);
2128                 bus_dma_tag_destroy(sc->rx_mbuf_tag);
2129         }
2130
2131         /* Destroy the parent tag */
2132         if (sc->parent_tag != NULL)
2133                 bus_dma_tag_destroy(sc->parent_tag);
2134
2135         if (sc->tx_bd_chain_map != NULL)
2136                 kfree(sc->tx_bd_chain_map, M_DEVBUF);
2137         if (sc->tx_bd_chain != NULL)
2138                 kfree(sc->tx_bd_chain, M_DEVBUF);
2139         if (sc->tx_bd_chain_paddr != NULL)
2140                 kfree(sc->tx_bd_chain_paddr, M_DEVBUF);
2141
2142         if (sc->rx_bd_chain_map != NULL)
2143                 kfree(sc->rx_bd_chain_map, M_DEVBUF);
2144         if (sc->rx_bd_chain != NULL)
2145                 kfree(sc->rx_bd_chain, M_DEVBUF);
2146         if (sc->rx_bd_chain_paddr != NULL)
2147                 kfree(sc->rx_bd_chain_paddr, M_DEVBUF);
2148
2149         if (sc->tx_mbuf_map != NULL)
2150                 kfree(sc->tx_mbuf_map, M_DEVBUF);
2151         if (sc->tx_mbuf_ptr != NULL)
2152                 kfree(sc->tx_mbuf_ptr, M_DEVBUF);
2153
2154         if (sc->rx_mbuf_map != NULL)
2155                 kfree(sc->rx_mbuf_map, M_DEVBUF);
2156         if (sc->rx_mbuf_ptr != NULL)
2157                 kfree(sc->rx_mbuf_ptr, M_DEVBUF);
2158         if (sc->rx_mbuf_paddr != NULL)
2159                 kfree(sc->rx_mbuf_paddr, M_DEVBUF);
2160 }
2161
2162
2163 /****************************************************************************/
2164 /* Get DMA memory from the OS.                                              */
2165 /*                                                                          */
2166 /* Validates that the OS has provided DMA buffers in response to a          */
2167 /* bus_dmamap_load() call and saves the physical address of those buffers.  */
2168 /* When the callback is used the OS will return 0 for the mapping function  */
2169 /* (bus_dmamap_load()) so we use the value of map_arg->maxsegs to pass any  */
2170 /* failures back to the caller.                                             */
2171 /*                                                                          */
2172 /* Returns:                                                                 */
2173 /*   Nothing.                                                               */
2174 /****************************************************************************/
2175 static void
2176 bce_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
2177 {
2178         bus_addr_t *busaddr = arg;
2179
2180         /*
2181          * Simulate a mapping failure.
2182          * XXX not correct.
2183          */
2184         DBRUNIF(DB_RANDOMTRUE(bce_debug_dma_map_addr_failure),
2185                 kprintf("bce: %s(%d): Simulating DMA mapping error.\n",
2186                         __FILE__, __LINE__);
2187                 error = ENOMEM);
2188                 
2189         /* Check for an error and signal the caller that an error occurred. */
2190         if (error)
2191                 return;
2192
2193         KASSERT(nseg == 1, ("only one segment is allowed"));
2194         *busaddr = segs->ds_addr;
2195 }
2196
2197
2198 /****************************************************************************/
2199 /* Allocate any DMA memory needed by the driver.                            */
2200 /*                                                                          */
2201 /* Allocates DMA memory needed for the various global structures needed by  */
2202 /* hardware.                                                                */
2203 /*                                                                          */
2204 /* Memory alignment requirements:                                           */
2205 /* -----------------+----------+----------+----------+----------+           */
2206 /*  Data Structure  |   5706   |   5708   |   5709   |   5716   |           */
2207 /* -----------------+----------+----------+----------+----------+           */
2208 /* Status Block     | 8 bytes  | 8 bytes  | 16 bytes | 16 bytes |           */
2209 /* Statistics Block | 8 bytes  | 8 bytes  | 16 bytes | 16 bytes |           */
2210 /* RX Buffers       | 16 bytes | 16 bytes | 16 bytes | 16 bytes |           */
2211 /* PG Buffers       |   none   |   none   |   none   |   none   |           */
2212 /* TX Buffers       |   none   |   none   |   none   |   none   |           */
2213 /* Chain Pages(1)   |   4KiB   |   4KiB   |   4KiB   |   4KiB   |           */
2214 /* Context Pages(1) |   N/A    |   N/A    |   4KiB   |   4KiB   |           */
2215 /* -----------------+----------+----------+----------+----------+           */
2216 /*                                                                          */
2217 /* (1) Must align with CPU page size (BCM_PAGE_SZIE).                       */
2218 /*                                                                          */
2219 /* Returns:                                                                 */
2220 /*   0 for success, positive value for failure.                             */
2221 /****************************************************************************/
2222 static int
2223 bce_dma_alloc(struct bce_softc *sc)
2224 {
2225         struct ifnet *ifp = &sc->arpcom.ac_if;
2226         int i, j, rc = 0, pages;
2227         bus_addr_t busaddr, max_busaddr;
2228         bus_size_t status_align, stats_align;
2229
2230         pages = device_getenv_int(sc->bce_dev, "rx_pages", bce_rx_pages);
2231         if (pages <= 0 || pages > RX_PAGES_MAX || !powerof2(pages)) {
2232                 device_printf(sc->bce_dev, "invalid # of RX pages\n");
2233                 pages = RX_PAGES_DEFAULT;
2234         }
2235         sc->rx_pages = pages;
2236
2237         pages = device_getenv_int(sc->bce_dev, "tx_pages", bce_tx_pages);
2238         if (pages <= 0 || pages > TX_PAGES_MAX || !powerof2(pages)) {
2239                 device_printf(sc->bce_dev, "invalid # of TX pages\n");
2240                 pages = TX_PAGES_DEFAULT;
2241         }
2242         sc->tx_pages = pages;
2243
2244         sc->tx_bd_chain_map = kmalloc(sizeof(bus_dmamap_t) * sc->tx_pages,
2245             M_DEVBUF, M_WAITOK | M_ZERO);
2246         sc->tx_bd_chain = kmalloc(sizeof(struct tx_bd *) * sc->tx_pages,
2247             M_DEVBUF, M_WAITOK | M_ZERO);
2248         sc->tx_bd_chain_paddr = kmalloc(sizeof(bus_addr_t) * sc->tx_pages,
2249             M_DEVBUF, M_WAITOK | M_ZERO);
2250
2251         sc->rx_bd_chain_map = kmalloc(sizeof(bus_dmamap_t) * sc->rx_pages,
2252             M_DEVBUF, M_WAITOK | M_ZERO);
2253         sc->rx_bd_chain = kmalloc(sizeof(struct rx_bd *) * sc->rx_pages,
2254             M_DEVBUF, M_WAITOK | M_ZERO);
2255         sc->rx_bd_chain_paddr = kmalloc(sizeof(bus_addr_t) * sc->rx_pages,
2256             M_DEVBUF, M_WAITOK | M_ZERO);
2257
2258         sc->tx_mbuf_map = kmalloc(sizeof(bus_dmamap_t) * TOTAL_TX_BD(sc),
2259             M_DEVBUF, M_WAITOK | M_ZERO);
2260         sc->tx_mbuf_ptr = kmalloc(sizeof(struct mbuf *) * TOTAL_TX_BD(sc),
2261             M_DEVBUF, M_WAITOK | M_ZERO);
2262
2263         sc->rx_mbuf_map = kmalloc(sizeof(bus_dmamap_t) * TOTAL_RX_BD(sc),
2264             M_DEVBUF, M_WAITOK | M_ZERO);
2265         sc->rx_mbuf_ptr = kmalloc(sizeof(struct mbuf *) * TOTAL_RX_BD(sc),
2266             M_DEVBUF, M_WAITOK | M_ZERO);
2267         sc->rx_mbuf_paddr = kmalloc(sizeof(bus_addr_t) * TOTAL_RX_BD(sc),
2268             M_DEVBUF, M_WAITOK | M_ZERO);
2269
2270         /*
2271          * The embedded PCIe to PCI-X bridge (EPB) 
2272          * in the 5708 cannot address memory above 
2273          * 40 bits (E7_5708CB1_23043 & E6_5708SB1_23043). 
2274          */
2275         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5708)
2276                 max_busaddr = BCE_BUS_SPACE_MAXADDR;
2277         else
2278                 max_busaddr = BUS_SPACE_MAXADDR;
2279
2280         /*
2281          * BCM5709 and BCM5716 uses host memory as cache for context memory.
2282          */
2283         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
2284             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
2285                 sc->ctx_pages = BCE_CTX_BLK_SZ / BCM_PAGE_SIZE;
2286                 if (sc->ctx_pages == 0)
2287                         sc->ctx_pages = 1;
2288                 if (sc->ctx_pages > BCE_CTX_PAGES) {
2289                         device_printf(sc->bce_dev, "excessive ctx pages %d\n",
2290                             sc->ctx_pages);
2291                         return ENOMEM;
2292                 }
2293                 status_align = 16;
2294                 stats_align = 16;
2295         } else {
2296                 status_align = 8;
2297                 stats_align = 8;
2298         }
2299
2300         /*
2301          * Allocate the parent bus DMA tag appropriate for PCI.
2302          */
2303         rc = bus_dma_tag_create(NULL, 1, BCE_DMA_BOUNDARY,
2304                                 max_busaddr, BUS_SPACE_MAXADDR,
2305                                 NULL, NULL,
2306                                 BUS_SPACE_MAXSIZE_32BIT, 0,
2307                                 BUS_SPACE_MAXSIZE_32BIT,
2308                                 0, &sc->parent_tag);
2309         if (rc != 0) {
2310                 if_printf(ifp, "Could not allocate parent DMA tag!\n");
2311                 return rc;
2312         }
2313
2314         /*
2315          * Allocate status block.
2316          */
2317         sc->status_block = bus_dmamem_coherent_any(sc->parent_tag,
2318                                 status_align, BCE_STATUS_BLK_SZ,
2319                                 BUS_DMA_WAITOK | BUS_DMA_ZERO,
2320                                 &sc->status_tag, &sc->status_map,
2321                                 &sc->status_block_paddr);
2322         if (sc->status_block == NULL) {
2323                 if_printf(ifp, "Could not allocate status block!\n");
2324                 return ENOMEM;
2325         }
2326
2327         /*
2328          * Allocate statistics block.
2329          */
2330         sc->stats_block = bus_dmamem_coherent_any(sc->parent_tag,
2331                                 stats_align, BCE_STATS_BLK_SZ,
2332                                 BUS_DMA_WAITOK | BUS_DMA_ZERO,
2333                                 &sc->stats_tag, &sc->stats_map,
2334                                 &sc->stats_block_paddr);
2335         if (sc->stats_block == NULL) {
2336                 if_printf(ifp, "Could not allocate statistics block!\n");
2337                 return ENOMEM;
2338         }
2339
2340         /*
2341          * Allocate context block, if needed
2342          */
2343         if (sc->ctx_pages != 0) {
2344                 rc = bus_dma_tag_create(sc->parent_tag, BCM_PAGE_SIZE, 0,
2345                                         BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
2346                                         NULL, NULL,
2347                                         BCM_PAGE_SIZE, 1, BCM_PAGE_SIZE,
2348                                         0, &sc->ctx_tag);
2349                 if (rc != 0) {
2350                         if_printf(ifp, "Could not allocate "
2351                                   "context block DMA tag!\n");
2352                         return rc;
2353                 }
2354
2355                 for (i = 0; i < sc->ctx_pages; i++) {
2356                         rc = bus_dmamem_alloc(sc->ctx_tag,
2357                                               (void **)&sc->ctx_block[i],
2358                                               BUS_DMA_WAITOK | BUS_DMA_ZERO |
2359                                               BUS_DMA_COHERENT,
2360                                               &sc->ctx_map[i]);
2361                         if (rc != 0) {
2362                                 if_printf(ifp, "Could not allocate %dth context "
2363                                           "DMA memory!\n", i);
2364                                 return rc;
2365                         }
2366
2367                         rc = bus_dmamap_load(sc->ctx_tag, sc->ctx_map[i],
2368                                              sc->ctx_block[i], BCM_PAGE_SIZE,
2369                                              bce_dma_map_addr, &busaddr,
2370                                              BUS_DMA_WAITOK);
2371                         if (rc != 0) {
2372                                 if (rc == EINPROGRESS) {
2373                                         panic("%s coherent memory loading "
2374                                               "is still in progress!", ifp->if_xname);
2375                                 }
2376                                 if_printf(ifp, "Could not map %dth context "
2377                                           "DMA memory!\n", i);
2378                                 bus_dmamem_free(sc->ctx_tag, sc->ctx_block[i],
2379                                                 sc->ctx_map[i]);
2380                                 sc->ctx_block[i] = NULL;
2381                                 return rc;
2382                         }
2383                         sc->ctx_paddr[i] = busaddr;
2384                 }
2385         }
2386
2387         /*
2388          * Create a DMA tag for the TX buffer descriptor chain,
2389          * allocate and clear the  memory, and fetch the
2390          * physical address of the block.
2391          */
2392         rc = bus_dma_tag_create(sc->parent_tag, BCM_PAGE_SIZE, 0,
2393                                 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
2394                                 NULL, NULL,
2395                                 BCE_TX_CHAIN_PAGE_SZ, 1, BCE_TX_CHAIN_PAGE_SZ,
2396                                 0, &sc->tx_bd_chain_tag);
2397         if (rc != 0) {
2398                 if_printf(ifp, "Could not allocate "
2399                           "TX descriptor chain DMA tag!\n");
2400                 return rc;
2401         }
2402
2403         for (i = 0; i < sc->tx_pages; i++) {
2404                 rc = bus_dmamem_alloc(sc->tx_bd_chain_tag,
2405                                       (void **)&sc->tx_bd_chain[i],
2406                                       BUS_DMA_WAITOK | BUS_DMA_ZERO |
2407                                       BUS_DMA_COHERENT,
2408                                       &sc->tx_bd_chain_map[i]);
2409                 if (rc != 0) {
2410                         if_printf(ifp, "Could not allocate %dth TX descriptor "
2411                                   "chain DMA memory!\n", i);
2412                         return rc;
2413                 }
2414
2415                 rc = bus_dmamap_load(sc->tx_bd_chain_tag,
2416                                      sc->tx_bd_chain_map[i],
2417                                      sc->tx_bd_chain[i], BCE_TX_CHAIN_PAGE_SZ,
2418                                      bce_dma_map_addr, &busaddr,
2419                                      BUS_DMA_WAITOK);
2420                 if (rc != 0) {
2421                         if (rc == EINPROGRESS) {
2422                                 panic("%s coherent memory loading "
2423                                       "is still in progress!", ifp->if_xname);
2424                         }
2425                         if_printf(ifp, "Could not map %dth TX descriptor "
2426                                   "chain DMA memory!\n", i);
2427                         bus_dmamem_free(sc->tx_bd_chain_tag,
2428                                         sc->tx_bd_chain[i],
2429                                         sc->tx_bd_chain_map[i]);
2430                         sc->tx_bd_chain[i] = NULL;
2431                         return rc;
2432                 }
2433
2434                 sc->tx_bd_chain_paddr[i] = busaddr;
2435                 /* DRC - Fix for 64 bit systems. */
2436                 DBPRINT(sc, BCE_INFO, "tx_bd_chain_paddr[%d] = 0x%08X\n", 
2437                         i, (uint32_t)sc->tx_bd_chain_paddr[i]);
2438         }
2439
2440         /* Create a DMA tag for TX mbufs. */
2441         rc = bus_dma_tag_create(sc->parent_tag, 1, 0,
2442                                 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
2443                                 NULL, NULL,
2444                                 IP_MAXPACKET + sizeof(struct ether_vlan_header),
2445                                 BCE_MAX_SEGMENTS, PAGE_SIZE,
2446                                 BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK |
2447                                 BUS_DMA_ONEBPAGE,
2448                                 &sc->tx_mbuf_tag);
2449         if (rc != 0) {
2450                 if_printf(ifp, "Could not allocate TX mbuf DMA tag!\n");
2451                 return rc;
2452         }
2453
2454         /* Create DMA maps for the TX mbufs clusters. */
2455         for (i = 0; i < TOTAL_TX_BD(sc); i++) {
2456                 rc = bus_dmamap_create(sc->tx_mbuf_tag,
2457                                        BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE,
2458                                        &sc->tx_mbuf_map[i]);
2459                 if (rc != 0) {
2460                         for (j = 0; j < i; ++j) {
2461                                 bus_dmamap_destroy(sc->tx_mbuf_tag,
2462                                                    sc->tx_mbuf_map[i]);
2463                         }
2464                         bus_dma_tag_destroy(sc->tx_mbuf_tag);
2465                         sc->tx_mbuf_tag = NULL;
2466
2467                         if_printf(ifp, "Unable to create "
2468                                   "%dth TX mbuf DMA map!\n", i);
2469                         return rc;
2470                 }
2471         }
2472
2473         /*
2474          * Create a DMA tag for the RX buffer descriptor chain,
2475          * allocate and clear the  memory, and fetch the physical
2476          * address of the blocks.
2477          */
2478         rc = bus_dma_tag_create(sc->parent_tag, BCM_PAGE_SIZE, 0,
2479                                 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
2480                                 NULL, NULL,
2481                                 BCE_RX_CHAIN_PAGE_SZ, 1, BCE_RX_CHAIN_PAGE_SZ,
2482                                 0, &sc->rx_bd_chain_tag);
2483         if (rc != 0) {
2484                 if_printf(ifp, "Could not allocate "
2485                           "RX descriptor chain DMA tag!\n");
2486                 return rc;
2487         }
2488
2489         for (i = 0; i < sc->rx_pages; i++) {
2490                 rc = bus_dmamem_alloc(sc->rx_bd_chain_tag,
2491                                       (void **)&sc->rx_bd_chain[i],
2492                                       BUS_DMA_WAITOK | BUS_DMA_ZERO |
2493                                       BUS_DMA_COHERENT,
2494                                       &sc->rx_bd_chain_map[i]);
2495                 if (rc != 0) {
2496                         if_printf(ifp, "Could not allocate %dth RX descriptor "
2497                                   "chain DMA memory!\n", i);
2498                         return rc;
2499                 }
2500
2501                 rc = bus_dmamap_load(sc->rx_bd_chain_tag,
2502                                      sc->rx_bd_chain_map[i],
2503                                      sc->rx_bd_chain[i], BCE_RX_CHAIN_PAGE_SZ,
2504                                      bce_dma_map_addr, &busaddr,
2505                                      BUS_DMA_WAITOK);
2506                 if (rc != 0) {
2507                         if (rc == EINPROGRESS) {
2508                                 panic("%s coherent memory loading "
2509                                       "is still in progress!", ifp->if_xname);
2510                         }
2511                         if_printf(ifp, "Could not map %dth RX descriptor "
2512                                   "chain DMA memory!\n", i);
2513                         bus_dmamem_free(sc->rx_bd_chain_tag,
2514                                         sc->rx_bd_chain[i],
2515                                         sc->rx_bd_chain_map[i]);
2516                         sc->rx_bd_chain[i] = NULL;
2517                         return rc;
2518                 }
2519
2520                 sc->rx_bd_chain_paddr[i] = busaddr;
2521                 /* DRC - Fix for 64 bit systems. */
2522                 DBPRINT(sc, BCE_INFO, "rx_bd_chain_paddr[%d] = 0x%08X\n",
2523                         i, (uint32_t)sc->rx_bd_chain_paddr[i]);
2524         }
2525
2526         /* Create a DMA tag for RX mbufs. */
2527         rc = bus_dma_tag_create(sc->parent_tag, BCE_DMA_RX_ALIGN, 0,
2528                                 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
2529                                 NULL, NULL,
2530                                 MCLBYTES, 1, MCLBYTES,
2531                                 BUS_DMA_ALLOCNOW | BUS_DMA_ALIGNED |
2532                                 BUS_DMA_WAITOK,
2533                                 &sc->rx_mbuf_tag);
2534         if (rc != 0) {
2535                 if_printf(ifp, "Could not allocate RX mbuf DMA tag!\n");
2536                 return rc;
2537         }
2538
2539         /* Create tmp DMA map for RX mbuf clusters. */
2540         rc = bus_dmamap_create(sc->rx_mbuf_tag, BUS_DMA_WAITOK,
2541                                &sc->rx_mbuf_tmpmap);
2542         if (rc != 0) {
2543                 bus_dma_tag_destroy(sc->rx_mbuf_tag);
2544                 sc->rx_mbuf_tag = NULL;
2545
2546                 if_printf(ifp, "Could not create RX mbuf tmp DMA map!\n");
2547                 return rc;
2548         }
2549
2550         /* Create DMA maps for the RX mbuf clusters. */
2551         for (i = 0; i < TOTAL_RX_BD(sc); i++) {
2552                 rc = bus_dmamap_create(sc->rx_mbuf_tag, BUS_DMA_WAITOK,
2553                                        &sc->rx_mbuf_map[i]);
2554                 if (rc != 0) {
2555                         for (j = 0; j < i; ++j) {
2556                                 bus_dmamap_destroy(sc->rx_mbuf_tag,
2557                                                    sc->rx_mbuf_map[j]);
2558                         }
2559                         bus_dma_tag_destroy(sc->rx_mbuf_tag);
2560                         sc->rx_mbuf_tag = NULL;
2561
2562                         if_printf(ifp, "Unable to create "
2563                                   "%dth RX mbuf DMA map!\n", i);
2564                         return rc;
2565                 }
2566         }
2567         return 0;
2568 }
2569
2570
2571 /****************************************************************************/
2572 /* Firmware synchronization.                                                */
2573 /*                                                                          */
2574 /* Before performing certain events such as a chip reset, synchronize with  */
2575 /* the firmware first.                                                      */
2576 /*                                                                          */
2577 /* Returns:                                                                 */
2578 /*   0 for success, positive value for failure.                             */
2579 /****************************************************************************/
2580 static int
2581 bce_fw_sync(struct bce_softc *sc, uint32_t msg_data)
2582 {
2583         int i, rc = 0;
2584         uint32_t val;
2585
2586         /* Don't waste any time if we've timed out before. */
2587         if (sc->bce_fw_timed_out)
2588                 return EBUSY;
2589
2590         /* Increment the message sequence number. */
2591         sc->bce_fw_wr_seq++;
2592         msg_data |= sc->bce_fw_wr_seq;
2593
2594         DBPRINT(sc, BCE_VERBOSE, "bce_fw_sync(): msg_data = 0x%08X\n", msg_data);
2595
2596         /* Send the message to the bootcode driver mailbox. */
2597         bce_shmem_wr(sc, BCE_DRV_MB, msg_data);
2598
2599         /* Wait for the bootcode to acknowledge the message. */
2600         for (i = 0; i < FW_ACK_TIME_OUT_MS; i++) {
2601                 /* Check for a response in the bootcode firmware mailbox. */
2602                 val = bce_shmem_rd(sc, BCE_FW_MB);
2603                 if ((val & BCE_FW_MSG_ACK) == (msg_data & BCE_DRV_MSG_SEQ))
2604                         break;
2605                 DELAY(1000);
2606         }
2607
2608         /* If we've timed out, tell the bootcode that we've stopped waiting. */
2609         if ((val & BCE_FW_MSG_ACK) != (msg_data & BCE_DRV_MSG_SEQ) &&
2610             (msg_data & BCE_DRV_MSG_DATA) != BCE_DRV_MSG_DATA_WAIT0) {
2611                 if_printf(&sc->arpcom.ac_if,
2612                           "Firmware synchronization timeout! "
2613                           "msg_data = 0x%08X\n", msg_data);
2614
2615                 msg_data &= ~BCE_DRV_MSG_CODE;
2616                 msg_data |= BCE_DRV_MSG_CODE_FW_TIMEOUT;
2617
2618                 bce_shmem_wr(sc, BCE_DRV_MB, msg_data);
2619
2620                 sc->bce_fw_timed_out = 1;
2621                 rc = EBUSY;
2622         }
2623         return rc;
2624 }
2625
2626
2627 /****************************************************************************/
2628 /* Load Receive Virtual 2 Physical (RV2P) processor firmware.               */
2629 /*                                                                          */
2630 /* Returns:                                                                 */
2631 /*   Nothing.                                                               */
2632 /****************************************************************************/
2633 static void
2634 bce_load_rv2p_fw(struct bce_softc *sc, uint32_t *rv2p_code,
2635                  uint32_t rv2p_code_len, uint32_t rv2p_proc)
2636 {
2637         int i;
2638         uint32_t val;
2639
2640         for (i = 0; i < rv2p_code_len; i += 8) {
2641                 REG_WR(sc, BCE_RV2P_INSTR_HIGH, *rv2p_code);
2642                 rv2p_code++;
2643                 REG_WR(sc, BCE_RV2P_INSTR_LOW, *rv2p_code);
2644                 rv2p_code++;
2645
2646                 if (rv2p_proc == RV2P_PROC1) {
2647                         val = (i / 8) | BCE_RV2P_PROC1_ADDR_CMD_RDWR;
2648                         REG_WR(sc, BCE_RV2P_PROC1_ADDR_CMD, val);
2649                 } else {
2650                         val = (i / 8) | BCE_RV2P_PROC2_ADDR_CMD_RDWR;
2651                         REG_WR(sc, BCE_RV2P_PROC2_ADDR_CMD, val);
2652                 }
2653         }
2654
2655         /* Reset the processor, un-stall is done later. */
2656         if (rv2p_proc == RV2P_PROC1)
2657                 REG_WR(sc, BCE_RV2P_COMMAND, BCE_RV2P_COMMAND_PROC1_RESET);
2658         else
2659                 REG_WR(sc, BCE_RV2P_COMMAND, BCE_RV2P_COMMAND_PROC2_RESET);
2660 }
2661
2662
2663 /****************************************************************************/
2664 /* Load RISC processor firmware.                                            */
2665 /*                                                                          */
2666 /* Loads firmware from the file if_bcefw.h into the scratchpad memory       */
2667 /* associated with a particular processor.                                  */
2668 /*                                                                          */
2669 /* Returns:                                                                 */
2670 /*   Nothing.                                                               */
2671 /****************************************************************************/
2672 static void
2673 bce_load_cpu_fw(struct bce_softc *sc, struct cpu_reg *cpu_reg,
2674                 struct fw_info *fw)
2675 {
2676         uint32_t offset;
2677         int j;
2678
2679         bce_halt_cpu(sc, cpu_reg);
2680
2681         /* Load the Text area. */
2682         offset = cpu_reg->spad_base + (fw->text_addr - cpu_reg->mips_view_base);
2683         if (fw->text) {
2684                 for (j = 0; j < (fw->text_len / 4); j++, offset += 4)
2685                         REG_WR_IND(sc, offset, fw->text[j]);
2686         }
2687
2688         /* Load the Data area. */
2689         offset = cpu_reg->spad_base + (fw->data_addr - cpu_reg->mips_view_base);
2690         if (fw->data) {
2691                 for (j = 0; j < (fw->data_len / 4); j++, offset += 4)
2692                         REG_WR_IND(sc, offset, fw->data[j]);
2693         }
2694
2695         /* Load the SBSS area. */
2696         offset = cpu_reg->spad_base + (fw->sbss_addr - cpu_reg->mips_view_base);
2697         if (fw->sbss) {
2698                 for (j = 0; j < (fw->sbss_len / 4); j++, offset += 4)
2699                         REG_WR_IND(sc, offset, fw->sbss[j]);
2700         }
2701
2702         /* Load the BSS area. */
2703         offset = cpu_reg->spad_base + (fw->bss_addr - cpu_reg->mips_view_base);
2704         if (fw->bss) {
2705                 for (j = 0; j < (fw->bss_len/4); j++, offset += 4)
2706                         REG_WR_IND(sc, offset, fw->bss[j]);
2707         }
2708
2709         /* Load the Read-Only area. */
2710         offset = cpu_reg->spad_base +
2711                 (fw->rodata_addr - cpu_reg->mips_view_base);
2712         if (fw->rodata) {
2713                 for (j = 0; j < (fw->rodata_len / 4); j++, offset += 4)
2714                         REG_WR_IND(sc, offset, fw->rodata[j]);
2715         }
2716
2717         /* Clear the pre-fetch instruction and set the FW start address. */
2718         REG_WR_IND(sc, cpu_reg->inst, 0);
2719         REG_WR_IND(sc, cpu_reg->pc, fw->start_addr);
2720 }
2721
2722
2723 /****************************************************************************/
2724 /* Starts the RISC processor.                                               */
2725 /*                                                                          */
2726 /* Assumes the CPU starting address has already been set.                   */
2727 /*                                                                          */
2728 /* Returns:                                                                 */
2729 /*   Nothing.                                                               */
2730 /****************************************************************************/
2731 static void
2732 bce_start_cpu(struct bce_softc *sc, struct cpu_reg *cpu_reg)
2733 {
2734         uint32_t val;
2735
2736         /* Start the CPU. */
2737         val = REG_RD_IND(sc, cpu_reg->mode);
2738         val &= ~cpu_reg->mode_value_halt;
2739         REG_WR_IND(sc, cpu_reg->state, cpu_reg->state_value_clear);
2740         REG_WR_IND(sc, cpu_reg->mode, val);
2741 }
2742
2743
2744 /****************************************************************************/
2745 /* Halts the RISC processor.                                                */
2746 /*                                                                          */
2747 /* Returns:                                                                 */
2748 /*   Nothing.                                                               */
2749 /****************************************************************************/
2750 static void
2751 bce_halt_cpu(struct bce_softc *sc, struct cpu_reg *cpu_reg)
2752 {
2753         uint32_t val;
2754
2755         /* Halt the CPU. */
2756         val = REG_RD_IND(sc, cpu_reg->mode);
2757         val |= cpu_reg->mode_value_halt;
2758         REG_WR_IND(sc, cpu_reg->mode, val);
2759         REG_WR_IND(sc, cpu_reg->state, cpu_reg->state_value_clear);
2760 }
2761
2762
2763 /****************************************************************************/
2764 /* Start the RX CPU.                                                        */
2765 /*                                                                          */
2766 /* Returns:                                                                 */
2767 /*   Nothing.                                                               */
2768 /****************************************************************************/
2769 static void
2770 bce_start_rxp_cpu(struct bce_softc *sc)
2771 {
2772         struct cpu_reg cpu_reg;
2773
2774         cpu_reg.mode = BCE_RXP_CPU_MODE;
2775         cpu_reg.mode_value_halt = BCE_RXP_CPU_MODE_SOFT_HALT;
2776         cpu_reg.mode_value_sstep = BCE_RXP_CPU_MODE_STEP_ENA;
2777         cpu_reg.state = BCE_RXP_CPU_STATE;
2778         cpu_reg.state_value_clear = 0xffffff;
2779         cpu_reg.gpr0 = BCE_RXP_CPU_REG_FILE;
2780         cpu_reg.evmask = BCE_RXP_CPU_EVENT_MASK;
2781         cpu_reg.pc = BCE_RXP_CPU_PROGRAM_COUNTER;
2782         cpu_reg.inst = BCE_RXP_CPU_INSTRUCTION;
2783         cpu_reg.bp = BCE_RXP_CPU_HW_BREAKPOINT;
2784         cpu_reg.spad_base = BCE_RXP_SCRATCH;
2785         cpu_reg.mips_view_base = 0x8000000;
2786
2787         bce_start_cpu(sc, &cpu_reg);
2788 }
2789
2790
2791 /****************************************************************************/
2792 /* Initialize the RX CPU.                                                   */
2793 /*                                                                          */
2794 /* Returns:                                                                 */
2795 /*   Nothing.                                                               */
2796 /****************************************************************************/
2797 static void
2798 bce_init_rxp_cpu(struct bce_softc *sc)
2799 {
2800         struct cpu_reg cpu_reg;
2801         struct fw_info fw;
2802
2803         cpu_reg.mode = BCE_RXP_CPU_MODE;
2804         cpu_reg.mode_value_halt = BCE_RXP_CPU_MODE_SOFT_HALT;
2805         cpu_reg.mode_value_sstep = BCE_RXP_CPU_MODE_STEP_ENA;
2806         cpu_reg.state = BCE_RXP_CPU_STATE;
2807         cpu_reg.state_value_clear = 0xffffff;
2808         cpu_reg.gpr0 = BCE_RXP_CPU_REG_FILE;
2809         cpu_reg.evmask = BCE_RXP_CPU_EVENT_MASK;
2810         cpu_reg.pc = BCE_RXP_CPU_PROGRAM_COUNTER;
2811         cpu_reg.inst = BCE_RXP_CPU_INSTRUCTION;
2812         cpu_reg.bp = BCE_RXP_CPU_HW_BREAKPOINT;
2813         cpu_reg.spad_base = BCE_RXP_SCRATCH;
2814         cpu_reg.mips_view_base = 0x8000000;
2815
2816         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
2817             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
2818                 fw.ver_major = bce_RXP_b09FwReleaseMajor;
2819                 fw.ver_minor = bce_RXP_b09FwReleaseMinor;
2820                 fw.ver_fix = bce_RXP_b09FwReleaseFix;
2821                 fw.start_addr = bce_RXP_b09FwStartAddr;
2822
2823                 fw.text_addr = bce_RXP_b09FwTextAddr;
2824                 fw.text_len = bce_RXP_b09FwTextLen;
2825                 fw.text_index = 0;
2826                 fw.text = bce_RXP_b09FwText;
2827
2828                 fw.data_addr = bce_RXP_b09FwDataAddr;
2829                 fw.data_len = bce_RXP_b09FwDataLen;
2830                 fw.data_index = 0;
2831                 fw.data = bce_RXP_b09FwData;
2832
2833                 fw.sbss_addr = bce_RXP_b09FwSbssAddr;
2834                 fw.sbss_len = bce_RXP_b09FwSbssLen;
2835                 fw.sbss_index = 0;
2836                 fw.sbss = bce_RXP_b09FwSbss;
2837
2838                 fw.bss_addr = bce_RXP_b09FwBssAddr;
2839                 fw.bss_len = bce_RXP_b09FwBssLen;
2840                 fw.bss_index = 0;
2841                 fw.bss = bce_RXP_b09FwBss;
2842
2843                 fw.rodata_addr = bce_RXP_b09FwRodataAddr;
2844                 fw.rodata_len = bce_RXP_b09FwRodataLen;
2845                 fw.rodata_index = 0;
2846                 fw.rodata = bce_RXP_b09FwRodata;
2847         } else {
2848                 fw.ver_major = bce_RXP_b06FwReleaseMajor;
2849                 fw.ver_minor = bce_RXP_b06FwReleaseMinor;
2850                 fw.ver_fix = bce_RXP_b06FwReleaseFix;
2851                 fw.start_addr = bce_RXP_b06FwStartAddr;
2852
2853                 fw.text_addr = bce_RXP_b06FwTextAddr;
2854                 fw.text_len = bce_RXP_b06FwTextLen;
2855                 fw.text_index = 0;
2856                 fw.text = bce_RXP_b06FwText;
2857
2858                 fw.data_addr = bce_RXP_b06FwDataAddr;
2859                 fw.data_len = bce_RXP_b06FwDataLen;
2860                 fw.data_index = 0;
2861                 fw.data = bce_RXP_b06FwData;
2862
2863                 fw.sbss_addr = bce_RXP_b06FwSbssAddr;
2864                 fw.sbss_len = bce_RXP_b06FwSbssLen;
2865                 fw.sbss_index = 0;
2866                 fw.sbss = bce_RXP_b06FwSbss;
2867
2868                 fw.bss_addr = bce_RXP_b06FwBssAddr;
2869                 fw.bss_len = bce_RXP_b06FwBssLen;
2870                 fw.bss_index = 0;
2871                 fw.bss = bce_RXP_b06FwBss;
2872
2873                 fw.rodata_addr = bce_RXP_b06FwRodataAddr;
2874                 fw.rodata_len = bce_RXP_b06FwRodataLen;
2875                 fw.rodata_index = 0;
2876                 fw.rodata = bce_RXP_b06FwRodata;
2877         }
2878
2879         DBPRINT(sc, BCE_INFO_RESET, "Loading RX firmware.\n");
2880         bce_load_cpu_fw(sc, &cpu_reg, &fw);
2881         /* Delay RXP start until initialization is complete. */
2882 }
2883
2884
2885 /****************************************************************************/
2886 /* Initialize the TX CPU.                                                   */
2887 /*                                                                          */
2888 /* Returns:                                                                 */
2889 /*   Nothing.                                                               */
2890 /****************************************************************************/
2891 static void
2892 bce_init_txp_cpu(struct bce_softc *sc)
2893 {
2894         struct cpu_reg cpu_reg;
2895         struct fw_info fw;
2896
2897         cpu_reg.mode = BCE_TXP_CPU_MODE;
2898         cpu_reg.mode_value_halt = BCE_TXP_CPU_MODE_SOFT_HALT;
2899         cpu_reg.mode_value_sstep = BCE_TXP_CPU_MODE_STEP_ENA;
2900         cpu_reg.state = BCE_TXP_CPU_STATE;
2901         cpu_reg.state_value_clear = 0xffffff;
2902         cpu_reg.gpr0 = BCE_TXP_CPU_REG_FILE;
2903         cpu_reg.evmask = BCE_TXP_CPU_EVENT_MASK;
2904         cpu_reg.pc = BCE_TXP_CPU_PROGRAM_COUNTER;
2905         cpu_reg.inst = BCE_TXP_CPU_INSTRUCTION;
2906         cpu_reg.bp = BCE_TXP_CPU_HW_BREAKPOINT;
2907         cpu_reg.spad_base = BCE_TXP_SCRATCH;
2908         cpu_reg.mips_view_base = 0x8000000;
2909
2910         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
2911             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
2912                 fw.ver_major = bce_TXP_b09FwReleaseMajor;
2913                 fw.ver_minor = bce_TXP_b09FwReleaseMinor;
2914                 fw.ver_fix = bce_TXP_b09FwReleaseFix;
2915                 fw.start_addr = bce_TXP_b09FwStartAddr;
2916
2917                 fw.text_addr = bce_TXP_b09FwTextAddr;
2918                 fw.text_len = bce_TXP_b09FwTextLen;
2919                 fw.text_index = 0;
2920                 fw.text = bce_TXP_b09FwText;
2921
2922                 fw.data_addr = bce_TXP_b09FwDataAddr;
2923                 fw.data_len = bce_TXP_b09FwDataLen;
2924                 fw.data_index = 0;
2925                 fw.data = bce_TXP_b09FwData;
2926
2927                 fw.sbss_addr = bce_TXP_b09FwSbssAddr;
2928                 fw.sbss_len = bce_TXP_b09FwSbssLen;
2929                 fw.sbss_index = 0;
2930                 fw.sbss = bce_TXP_b09FwSbss;
2931
2932                 fw.bss_addr = bce_TXP_b09FwBssAddr;
2933                 fw.bss_len = bce_TXP_b09FwBssLen;
2934                 fw.bss_index = 0;
2935                 fw.bss = bce_TXP_b09FwBss;
2936
2937                 fw.rodata_addr = bce_TXP_b09FwRodataAddr;
2938                 fw.rodata_len = bce_TXP_b09FwRodataLen;
2939                 fw.rodata_index = 0;
2940                 fw.rodata = bce_TXP_b09FwRodata;
2941         } else {
2942                 fw.ver_major = bce_TXP_b06FwReleaseMajor;
2943                 fw.ver_minor = bce_TXP_b06FwReleaseMinor;
2944                 fw.ver_fix = bce_TXP_b06FwReleaseFix;
2945                 fw.start_addr = bce_TXP_b06FwStartAddr;
2946
2947                 fw.text_addr = bce_TXP_b06FwTextAddr;
2948                 fw.text_len = bce_TXP_b06FwTextLen;
2949                 fw.text_index = 0;
2950                 fw.text = bce_TXP_b06FwText;
2951
2952                 fw.data_addr = bce_TXP_b06FwDataAddr;
2953                 fw.data_len = bce_TXP_b06FwDataLen;
2954                 fw.data_index = 0;
2955                 fw.data = bce_TXP_b06FwData;
2956
2957                 fw.sbss_addr = bce_TXP_b06FwSbssAddr;
2958                 fw.sbss_len = bce_TXP_b06FwSbssLen;
2959                 fw.sbss_index = 0;
2960                 fw.sbss = bce_TXP_b06FwSbss;
2961
2962                 fw.bss_addr = bce_TXP_b06FwBssAddr;
2963                 fw.bss_len = bce_TXP_b06FwBssLen;
2964                 fw.bss_index = 0;
2965                 fw.bss = bce_TXP_b06FwBss;
2966
2967                 fw.rodata_addr = bce_TXP_b06FwRodataAddr;
2968                 fw.rodata_len = bce_TXP_b06FwRodataLen;
2969                 fw.rodata_index = 0;
2970                 fw.rodata = bce_TXP_b06FwRodata;
2971         }
2972
2973         DBPRINT(sc, BCE_INFO_RESET, "Loading TX firmware.\n");
2974         bce_load_cpu_fw(sc, &cpu_reg, &fw);
2975         bce_start_cpu(sc, &cpu_reg);
2976 }
2977
2978
2979 /****************************************************************************/
2980 /* Initialize the TPAT CPU.                                                 */
2981 /*                                                                          */
2982 /* Returns:                                                                 */
2983 /*   Nothing.                                                               */
2984 /****************************************************************************/
2985 static void
2986 bce_init_tpat_cpu(struct bce_softc *sc)
2987 {
2988         struct cpu_reg cpu_reg;
2989         struct fw_info fw;
2990
2991         cpu_reg.mode = BCE_TPAT_CPU_MODE;
2992         cpu_reg.mode_value_halt = BCE_TPAT_CPU_MODE_SOFT_HALT;
2993         cpu_reg.mode_value_sstep = BCE_TPAT_CPU_MODE_STEP_ENA;
2994         cpu_reg.state = BCE_TPAT_CPU_STATE;
2995         cpu_reg.state_value_clear = 0xffffff;
2996         cpu_reg.gpr0 = BCE_TPAT_CPU_REG_FILE;
2997         cpu_reg.evmask = BCE_TPAT_CPU_EVENT_MASK;
2998         cpu_reg.pc = BCE_TPAT_CPU_PROGRAM_COUNTER;
2999         cpu_reg.inst = BCE_TPAT_CPU_INSTRUCTION;
3000         cpu_reg.bp = BCE_TPAT_CPU_HW_BREAKPOINT;
3001         cpu_reg.spad_base = BCE_TPAT_SCRATCH;
3002         cpu_reg.mips_view_base = 0x8000000;
3003
3004         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3005             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3006                 fw.ver_major = bce_TPAT_b09FwReleaseMajor;
3007                 fw.ver_minor = bce_TPAT_b09FwReleaseMinor;
3008                 fw.ver_fix = bce_TPAT_b09FwReleaseFix;
3009                 fw.start_addr = bce_TPAT_b09FwStartAddr;
3010
3011                 fw.text_addr = bce_TPAT_b09FwTextAddr;
3012                 fw.text_len = bce_TPAT_b09FwTextLen;
3013                 fw.text_index = 0;
3014                 fw.text = bce_TPAT_b09FwText;
3015
3016                 fw.data_addr = bce_TPAT_b09FwDataAddr;
3017                 fw.data_len = bce_TPAT_b09FwDataLen;
3018                 fw.data_index = 0;
3019                 fw.data = bce_TPAT_b09FwData;
3020
3021                 fw.sbss_addr = bce_TPAT_b09FwSbssAddr;
3022                 fw.sbss_len = bce_TPAT_b09FwSbssLen;
3023                 fw.sbss_index = 0;
3024                 fw.sbss = bce_TPAT_b09FwSbss;
3025
3026                 fw.bss_addr = bce_TPAT_b09FwBssAddr;
3027                 fw.bss_len = bce_TPAT_b09FwBssLen;
3028                 fw.bss_index = 0;
3029                 fw.bss = bce_TPAT_b09FwBss;
3030
3031                 fw.rodata_addr = bce_TPAT_b09FwRodataAddr;
3032                 fw.rodata_len = bce_TPAT_b09FwRodataLen;
3033                 fw.rodata_index = 0;
3034                 fw.rodata = bce_TPAT_b09FwRodata;
3035         } else {
3036                 fw.ver_major = bce_TPAT_b06FwReleaseMajor;
3037                 fw.ver_minor = bce_TPAT_b06FwReleaseMinor;
3038                 fw.ver_fix = bce_TPAT_b06FwReleaseFix;
3039                 fw.start_addr = bce_TPAT_b06FwStartAddr;
3040
3041                 fw.text_addr = bce_TPAT_b06FwTextAddr;
3042                 fw.text_len = bce_TPAT_b06FwTextLen;
3043                 fw.text_index = 0;
3044                 fw.text = bce_TPAT_b06FwText;
3045
3046                 fw.data_addr = bce_TPAT_b06FwDataAddr;
3047                 fw.data_len = bce_TPAT_b06FwDataLen;
3048                 fw.data_index = 0;
3049                 fw.data = bce_TPAT_b06FwData;
3050
3051                 fw.sbss_addr = bce_TPAT_b06FwSbssAddr;
3052                 fw.sbss_len = bce_TPAT_b06FwSbssLen;
3053                 fw.sbss_index = 0;
3054                 fw.sbss = bce_TPAT_b06FwSbss;
3055
3056                 fw.bss_addr = bce_TPAT_b06FwBssAddr;
3057                 fw.bss_len = bce_TPAT_b06FwBssLen;
3058                 fw.bss_index = 0;
3059                 fw.bss = bce_TPAT_b06FwBss;
3060
3061                 fw.rodata_addr = bce_TPAT_b06FwRodataAddr;
3062                 fw.rodata_len = bce_TPAT_b06FwRodataLen;
3063                 fw.rodata_index = 0;
3064                 fw.rodata = bce_TPAT_b06FwRodata;
3065         }
3066
3067         DBPRINT(sc, BCE_INFO_RESET, "Loading TPAT firmware.\n");
3068         bce_load_cpu_fw(sc, &cpu_reg, &fw);
3069         bce_start_cpu(sc, &cpu_reg);
3070 }
3071
3072
3073 /****************************************************************************/
3074 /* Initialize the CP CPU.                                                   */
3075 /*                                                                          */
3076 /* Returns:                                                                 */
3077 /*   Nothing.                                                               */
3078 /****************************************************************************/
3079 static void
3080 bce_init_cp_cpu(struct bce_softc *sc)
3081 {
3082         struct cpu_reg cpu_reg;
3083         struct fw_info fw;
3084
3085         cpu_reg.mode = BCE_CP_CPU_MODE;
3086         cpu_reg.mode_value_halt = BCE_CP_CPU_MODE_SOFT_HALT;
3087         cpu_reg.mode_value_sstep = BCE_CP_CPU_MODE_STEP_ENA;
3088         cpu_reg.state = BCE_CP_CPU_STATE;
3089         cpu_reg.state_value_clear = 0xffffff;
3090         cpu_reg.gpr0 = BCE_CP_CPU_REG_FILE;
3091         cpu_reg.evmask = BCE_CP_CPU_EVENT_MASK;
3092         cpu_reg.pc = BCE_CP_CPU_PROGRAM_COUNTER;
3093         cpu_reg.inst = BCE_CP_CPU_INSTRUCTION;
3094         cpu_reg.bp = BCE_CP_CPU_HW_BREAKPOINT;
3095         cpu_reg.spad_base = BCE_CP_SCRATCH;
3096         cpu_reg.mips_view_base = 0x8000000;
3097
3098         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3099             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3100                 fw.ver_major = bce_CP_b09FwReleaseMajor;
3101                 fw.ver_minor = bce_CP_b09FwReleaseMinor;
3102                 fw.ver_fix = bce_CP_b09FwReleaseFix;
3103                 fw.start_addr = bce_CP_b09FwStartAddr;
3104
3105                 fw.text_addr = bce_CP_b09FwTextAddr;
3106                 fw.text_len = bce_CP_b09FwTextLen;
3107                 fw.text_index = 0;
3108                 fw.text = bce_CP_b09FwText;
3109
3110                 fw.data_addr = bce_CP_b09FwDataAddr;
3111                 fw.data_len = bce_CP_b09FwDataLen;
3112                 fw.data_index = 0;
3113                 fw.data = bce_CP_b09FwData;
3114
3115                 fw.sbss_addr = bce_CP_b09FwSbssAddr;
3116                 fw.sbss_len = bce_CP_b09FwSbssLen;
3117                 fw.sbss_index = 0;
3118                 fw.sbss = bce_CP_b09FwSbss;
3119
3120                 fw.bss_addr = bce_CP_b09FwBssAddr;
3121                 fw.bss_len = bce_CP_b09FwBssLen;
3122                 fw.bss_index = 0;
3123                 fw.bss = bce_CP_b09FwBss;
3124
3125                 fw.rodata_addr = bce_CP_b09FwRodataAddr;
3126                 fw.rodata_len = bce_CP_b09FwRodataLen;
3127                 fw.rodata_index = 0;
3128                 fw.rodata = bce_CP_b09FwRodata;
3129         } else {
3130                 fw.ver_major = bce_CP_b06FwReleaseMajor;
3131                 fw.ver_minor = bce_CP_b06FwReleaseMinor;
3132                 fw.ver_fix = bce_CP_b06FwReleaseFix;
3133                 fw.start_addr = bce_CP_b06FwStartAddr;
3134
3135                 fw.text_addr = bce_CP_b06FwTextAddr;
3136                 fw.text_len = bce_CP_b06FwTextLen;
3137                 fw.text_index = 0;
3138                 fw.text = bce_CP_b06FwText;
3139
3140                 fw.data_addr = bce_CP_b06FwDataAddr;
3141                 fw.data_len = bce_CP_b06FwDataLen;
3142                 fw.data_index = 0;
3143                 fw.data = bce_CP_b06FwData;
3144
3145                 fw.sbss_addr = bce_CP_b06FwSbssAddr;
3146                 fw.sbss_len = bce_CP_b06FwSbssLen;
3147                 fw.sbss_index = 0;
3148                 fw.sbss = bce_CP_b06FwSbss;
3149
3150                 fw.bss_addr = bce_CP_b06FwBssAddr;
3151                 fw.bss_len = bce_CP_b06FwBssLen;
3152                 fw.bss_index = 0;
3153                 fw.bss = bce_CP_b06FwBss;
3154
3155                 fw.rodata_addr = bce_CP_b06FwRodataAddr;
3156                 fw.rodata_len = bce_CP_b06FwRodataLen;
3157                 fw.rodata_index = 0;
3158                 fw.rodata = bce_CP_b06FwRodata;
3159         }
3160
3161         DBPRINT(sc, BCE_INFO_RESET, "Loading CP firmware.\n");
3162         bce_load_cpu_fw(sc, &cpu_reg, &fw);
3163         bce_start_cpu(sc, &cpu_reg);
3164 }
3165
3166
3167 /****************************************************************************/
3168 /* Initialize the COM CPU.                                                 */
3169 /*                                                                          */
3170 /* Returns:                                                                 */
3171 /*   Nothing.                                                               */
3172 /****************************************************************************/
3173 static void
3174 bce_init_com_cpu(struct bce_softc *sc)
3175 {
3176         struct cpu_reg cpu_reg;
3177         struct fw_info fw;
3178
3179         cpu_reg.mode = BCE_COM_CPU_MODE;
3180         cpu_reg.mode_value_halt = BCE_COM_CPU_MODE_SOFT_HALT;
3181         cpu_reg.mode_value_sstep = BCE_COM_CPU_MODE_STEP_ENA;
3182         cpu_reg.state = BCE_COM_CPU_STATE;
3183         cpu_reg.state_value_clear = 0xffffff;
3184         cpu_reg.gpr0 = BCE_COM_CPU_REG_FILE;
3185         cpu_reg.evmask = BCE_COM_CPU_EVENT_MASK;
3186         cpu_reg.pc = BCE_COM_CPU_PROGRAM_COUNTER;
3187         cpu_reg.inst = BCE_COM_CPU_INSTRUCTION;
3188         cpu_reg.bp = BCE_COM_CPU_HW_BREAKPOINT;
3189         cpu_reg.spad_base = BCE_COM_SCRATCH;
3190         cpu_reg.mips_view_base = 0x8000000;
3191
3192         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3193             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3194                 fw.ver_major = bce_COM_b09FwReleaseMajor;
3195                 fw.ver_minor = bce_COM_b09FwReleaseMinor;
3196                 fw.ver_fix = bce_COM_b09FwReleaseFix;
3197                 fw.start_addr = bce_COM_b09FwStartAddr;
3198
3199                 fw.text_addr = bce_COM_b09FwTextAddr;
3200                 fw.text_len = bce_COM_b09FwTextLen;
3201                 fw.text_index = 0;
3202                 fw.text = bce_COM_b09FwText;
3203
3204                 fw.data_addr = bce_COM_b09FwDataAddr;
3205                 fw.data_len = bce_COM_b09FwDataLen;
3206                 fw.data_index = 0;
3207                 fw.data = bce_COM_b09FwData;
3208
3209                 fw.sbss_addr = bce_COM_b09FwSbssAddr;
3210                 fw.sbss_len = bce_COM_b09FwSbssLen;
3211                 fw.sbss_index = 0;
3212                 fw.sbss = bce_COM_b09FwSbss;
3213
3214                 fw.bss_addr = bce_COM_b09FwBssAddr;
3215                 fw.bss_len = bce_COM_b09FwBssLen;
3216                 fw.bss_index = 0;
3217                 fw.bss = bce_COM_b09FwBss;
3218
3219                 fw.rodata_addr = bce_COM_b09FwRodataAddr;
3220                 fw.rodata_len = bce_COM_b09FwRodataLen;
3221                 fw.rodata_index = 0;
3222                 fw.rodata = bce_COM_b09FwRodata;
3223         } else {
3224                 fw.ver_major = bce_COM_b06FwReleaseMajor;
3225                 fw.ver_minor = bce_COM_b06FwReleaseMinor;
3226                 fw.ver_fix = bce_COM_b06FwReleaseFix;
3227                 fw.start_addr = bce_COM_b06FwStartAddr;
3228
3229                 fw.text_addr = bce_COM_b06FwTextAddr;
3230                 fw.text_len = bce_COM_b06FwTextLen;
3231                 fw.text_index = 0;
3232                 fw.text = bce_COM_b06FwText;
3233
3234                 fw.data_addr = bce_COM_b06FwDataAddr;
3235                 fw.data_len = bce_COM_b06FwDataLen;
3236                 fw.data_index = 0;
3237                 fw.data = bce_COM_b06FwData;
3238
3239                 fw.sbss_addr = bce_COM_b06FwSbssAddr;
3240                 fw.sbss_len = bce_COM_b06FwSbssLen;
3241                 fw.sbss_index = 0;
3242                 fw.sbss = bce_COM_b06FwSbss;
3243
3244                 fw.bss_addr = bce_COM_b06FwBssAddr;
3245                 fw.bss_len = bce_COM_b06FwBssLen;
3246                 fw.bss_index = 0;
3247                 fw.bss = bce_COM_b06FwBss;
3248
3249                 fw.rodata_addr = bce_COM_b06FwRodataAddr;
3250                 fw.rodata_len = bce_COM_b06FwRodataLen;
3251                 fw.rodata_index = 0;
3252                 fw.rodata = bce_COM_b06FwRodata;
3253         }
3254
3255         DBPRINT(sc, BCE_INFO_RESET, "Loading COM firmware.\n");
3256         bce_load_cpu_fw(sc, &cpu_reg, &fw);
3257         bce_start_cpu(sc, &cpu_reg);
3258 }
3259
3260
3261 /****************************************************************************/
3262 /* Initialize the RV2P, RX, TX, TPAT, COM, and CP CPUs.                     */
3263 /*                                                                          */
3264 /* Loads the firmware for each CPU and starts the CPU.                      */
3265 /*                                                                          */
3266 /* Returns:                                                                 */
3267 /*   Nothing.                                                               */
3268 /****************************************************************************/
3269 static void
3270 bce_init_cpus(struct bce_softc *sc)
3271 {
3272         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3273             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3274                 if (BCE_CHIP_REV(sc) == BCE_CHIP_REV_Ax) {
3275                         bce_load_rv2p_fw(sc, bce_xi90_rv2p_proc1,
3276                             sizeof(bce_xi90_rv2p_proc1), RV2P_PROC1);
3277                         bce_load_rv2p_fw(sc, bce_xi90_rv2p_proc2,
3278                             sizeof(bce_xi90_rv2p_proc2), RV2P_PROC2);
3279                 } else {
3280                         bce_load_rv2p_fw(sc, bce_xi_rv2p_proc1,
3281                             sizeof(bce_xi_rv2p_proc1), RV2P_PROC1);
3282                         bce_load_rv2p_fw(sc, bce_xi_rv2p_proc2,
3283                             sizeof(bce_xi_rv2p_proc2), RV2P_PROC2);
3284                 }
3285         } else {
3286                 bce_load_rv2p_fw(sc, bce_rv2p_proc1,
3287                     sizeof(bce_rv2p_proc1), RV2P_PROC1);
3288                 bce_load_rv2p_fw(sc, bce_rv2p_proc2,
3289                     sizeof(bce_rv2p_proc2), RV2P_PROC2);
3290         }
3291
3292         bce_init_rxp_cpu(sc);
3293         bce_init_txp_cpu(sc);
3294         bce_init_tpat_cpu(sc);
3295         bce_init_com_cpu(sc);
3296         bce_init_cp_cpu(sc);
3297 }
3298
3299
3300 /****************************************************************************/
3301 /* Initialize context memory.                                               */
3302 /*                                                                          */
3303 /* Clears the memory associated with each Context ID (CID).                 */
3304 /*                                                                          */
3305 /* Returns:                                                                 */
3306 /*   Nothing.                                                               */
3307 /****************************************************************************/
3308 static int
3309 bce_init_ctx(struct bce_softc *sc)
3310 {
3311         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3312             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3313                 /* DRC: Replace this constant value with a #define. */
3314                 int i, retry_cnt = 10;
3315                 uint32_t val;
3316
3317                 /*
3318                  * BCM5709 context memory may be cached
3319                  * in host memory so prepare the host memory
3320                  * for access.
3321                  */
3322                 val = BCE_CTX_COMMAND_ENABLED | BCE_CTX_COMMAND_MEM_INIT |
3323                     (1 << 12);
3324                 val |= (BCM_PAGE_BITS - 8) << 16;
3325                 REG_WR(sc, BCE_CTX_COMMAND, val);
3326
3327                 /* Wait for mem init command to complete. */
3328                 for (i = 0; i < retry_cnt; i++) {
3329                         val = REG_RD(sc, BCE_CTX_COMMAND);
3330                         if (!(val & BCE_CTX_COMMAND_MEM_INIT))
3331                                 break;
3332                         DELAY(2);
3333                 }
3334                 if (i == retry_cnt) {
3335                         device_printf(sc->bce_dev,
3336                             "Context memory initialization failed!\n");
3337                         return ETIMEDOUT;
3338                 }
3339
3340                 for (i = 0; i < sc->ctx_pages; i++) {
3341                         int j;
3342
3343                         /*
3344                          * Set the physical address of the context
3345                          * memory cache.
3346                          */
3347                         REG_WR(sc, BCE_CTX_HOST_PAGE_TBL_DATA0,
3348                             BCE_ADDR_LO(sc->ctx_paddr[i] & 0xfffffff0) |
3349                             BCE_CTX_HOST_PAGE_TBL_DATA0_VALID);
3350                         REG_WR(sc, BCE_CTX_HOST_PAGE_TBL_DATA1,
3351                             BCE_ADDR_HI(sc->ctx_paddr[i]));
3352                         REG_WR(sc, BCE_CTX_HOST_PAGE_TBL_CTRL,
3353                             i | BCE_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ);
3354
3355                         /*
3356                          * Verify that the context memory write was successful.
3357                          */
3358                         for (j = 0; j < retry_cnt; j++) {
3359                                 val = REG_RD(sc, BCE_CTX_HOST_PAGE_TBL_CTRL);
3360                                 if ((val &
3361                                     BCE_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) == 0)
3362                                         break;
3363                                 DELAY(5);
3364                         }
3365                         if (j == retry_cnt) {
3366                                 device_printf(sc->bce_dev,
3367                                     "Failed to initialize context page!\n");
3368                                 return ETIMEDOUT;
3369                         }
3370                 }
3371         } else {
3372                 uint32_t vcid_addr, offset;
3373
3374                 /*
3375                  * For the 5706/5708, context memory is local to
3376                  * the controller, so initialize the controller
3377                  * context memory.
3378                  */
3379
3380                 vcid_addr = GET_CID_ADDR(96);
3381                 while (vcid_addr) {
3382                         vcid_addr -= PHY_CTX_SIZE;
3383
3384                         REG_WR(sc, BCE_CTX_VIRT_ADDR, 0);
3385                         REG_WR(sc, BCE_CTX_PAGE_TBL, vcid_addr);
3386
3387                         for (offset = 0; offset < PHY_CTX_SIZE; offset += 4)
3388                                 CTX_WR(sc, 0x00, offset, 0);
3389
3390                         REG_WR(sc, BCE_CTX_VIRT_ADDR, vcid_addr);
3391                         REG_WR(sc, BCE_CTX_PAGE_TBL, vcid_addr);
3392                 }
3393         }
3394         return 0;
3395 }
3396
3397
3398 /****************************************************************************/
3399 /* Fetch the permanent MAC address of the controller.                       */
3400 /*                                                                          */
3401 /* Returns:                                                                 */
3402 /*   Nothing.                                                               */
3403 /****************************************************************************/
3404 static void
3405 bce_get_mac_addr(struct bce_softc *sc)
3406 {
3407         uint32_t mac_lo = 0, mac_hi = 0;
3408
3409         /*
3410          * The NetXtreme II bootcode populates various NIC
3411          * power-on and runtime configuration items in a
3412          * shared memory area.  The factory configured MAC
3413          * address is available from both NVRAM and the
3414          * shared memory area so we'll read the value from
3415          * shared memory for speed.
3416          */
3417
3418         mac_hi = bce_shmem_rd(sc,  BCE_PORT_HW_CFG_MAC_UPPER);
3419         mac_lo = bce_shmem_rd(sc, BCE_PORT_HW_CFG_MAC_LOWER);
3420
3421         if (mac_lo == 0 && mac_hi == 0) {
3422                 if_printf(&sc->arpcom.ac_if, "Invalid Ethernet address!\n");
3423         } else {
3424                 sc->eaddr[0] = (u_char)(mac_hi >> 8);
3425                 sc->eaddr[1] = (u_char)(mac_hi >> 0);
3426                 sc->eaddr[2] = (u_char)(mac_lo >> 24);
3427                 sc->eaddr[3] = (u_char)(mac_lo >> 16);
3428                 sc->eaddr[4] = (u_char)(mac_lo >> 8);
3429                 sc->eaddr[5] = (u_char)(mac_lo >> 0);
3430         }
3431
3432         DBPRINT(sc, BCE_INFO, "Permanent Ethernet address = %6D\n", sc->eaddr, ":");
3433 }
3434
3435
3436 /****************************************************************************/
3437 /* Program the MAC address.                                                 */
3438 /*                                                                          */
3439 /* Returns:                                                                 */
3440 /*   Nothing.                                                               */
3441 /****************************************************************************/
3442 static void
3443 bce_set_mac_addr(struct bce_softc *sc)
3444 {
3445         const uint8_t *mac_addr = sc->eaddr;
3446         uint32_t val;
3447
3448         DBPRINT(sc, BCE_INFO, "Setting Ethernet address = %6D\n",
3449                 sc->eaddr, ":");
3450
3451         val = (mac_addr[0] << 8) | mac_addr[1];
3452         REG_WR(sc, BCE_EMAC_MAC_MATCH0, val);
3453
3454         val = (mac_addr[2] << 24) |
3455               (mac_addr[3] << 16) |
3456               (mac_addr[4] << 8) |
3457               mac_addr[5];
3458         REG_WR(sc, BCE_EMAC_MAC_MATCH1, val);
3459 }
3460
3461
3462 /****************************************************************************/
3463 /* Stop the controller.                                                     */
3464 /*                                                                          */
3465 /* Returns:                                                                 */
3466 /*   Nothing.                                                               */
3467 /****************************************************************************/
3468 static void
3469 bce_stop(struct bce_softc *sc)
3470 {
3471         struct ifnet *ifp = &sc->arpcom.ac_if;
3472
3473         ASSERT_SERIALIZED(ifp->if_serializer);
3474
3475         callout_stop(&sc->bce_tick_callout);
3476
3477         /* Disable the transmit/receive blocks. */
3478         REG_WR(sc, BCE_MISC_ENABLE_CLR_BITS, BCE_MISC_ENABLE_CLR_DEFAULT);
3479         REG_RD(sc, BCE_MISC_ENABLE_CLR_BITS);
3480         DELAY(20);
3481
3482         bce_disable_intr(sc);
3483
3484         /* Free the RX lists. */
3485         bce_free_rx_chain(sc);
3486
3487         /* Free TX buffers. */
3488         bce_free_tx_chain(sc);
3489
3490         sc->bce_link = 0;
3491         sc->bce_coalchg_mask = 0;
3492
3493         ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
3494         ifp->if_timer = 0;
3495 }
3496
3497
3498 static int
3499 bce_reset(struct bce_softc *sc, uint32_t reset_code)
3500 {
3501         uint32_t val;
3502         int i, rc = 0;
3503
3504         /* Wait for pending PCI transactions to complete. */
3505         REG_WR(sc, BCE_MISC_ENABLE_CLR_BITS,
3506                BCE_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE |
3507                BCE_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE |
3508                BCE_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE |
3509                BCE_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE);
3510         val = REG_RD(sc, BCE_MISC_ENABLE_CLR_BITS);
3511         DELAY(5);
3512
3513         /* Disable DMA */
3514         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3515             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3516                 val = REG_RD(sc, BCE_MISC_NEW_CORE_CTL);
3517                 val &= ~BCE_MISC_NEW_CORE_CTL_DMA_ENABLE;
3518                 REG_WR(sc, BCE_MISC_NEW_CORE_CTL, val);
3519         }
3520
3521         /* Assume bootcode is running. */
3522         sc->bce_fw_timed_out = 0;
3523         sc->bce_drv_cardiac_arrest = 0;
3524
3525         /* Give the firmware a chance to prepare for the reset. */
3526         rc = bce_fw_sync(sc, BCE_DRV_MSG_DATA_WAIT0 | reset_code);
3527         if (rc) {
3528                 if_printf(&sc->arpcom.ac_if,
3529                           "Firmware is not ready for reset\n");
3530                 return rc;
3531         }
3532
3533         /* Set a firmware reminder that this is a soft reset. */
3534         bce_shmem_wr(sc, BCE_DRV_RESET_SIGNATURE,
3535             BCE_DRV_RESET_SIGNATURE_MAGIC);
3536
3537         /* Dummy read to force the chip to complete all current transactions. */
3538         val = REG_RD(sc, BCE_MISC_ID);
3539
3540         /* Chip reset. */
3541         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3542             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3543                 REG_WR(sc, BCE_MISC_COMMAND, BCE_MISC_COMMAND_SW_RESET);
3544                 REG_RD(sc, BCE_MISC_COMMAND);
3545                 DELAY(5);
3546
3547                 val = BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
3548                     BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
3549
3550                 pci_write_config(sc->bce_dev, BCE_PCICFG_MISC_CONFIG, val, 4);
3551         } else {
3552                 val = BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ |
3553                     BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
3554                     BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
3555                 REG_WR(sc, BCE_PCICFG_MISC_CONFIG, val);
3556
3557                 /* Allow up to 30us for reset to complete. */
3558                 for (i = 0; i < 10; i++) {
3559                         val = REG_RD(sc, BCE_PCICFG_MISC_CONFIG);
3560                         if ((val & (BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ |
3561                             BCE_PCICFG_MISC_CONFIG_CORE_RST_BSY)) == 0)
3562                                 break;
3563                         DELAY(10);
3564                 }
3565
3566                 /* Check that reset completed successfully. */
3567                 if (val & (BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ |
3568                     BCE_PCICFG_MISC_CONFIG_CORE_RST_BSY)) {
3569                         if_printf(&sc->arpcom.ac_if, "Reset failed!\n");
3570                         return EBUSY;
3571                 }
3572         }
3573
3574         /* Make sure byte swapping is properly configured. */
3575         val = REG_RD(sc, BCE_PCI_SWAP_DIAG0);
3576         if (val != 0x01020304) {
3577                 if_printf(&sc->arpcom.ac_if, "Byte swap is incorrect!\n");
3578                 return ENODEV;
3579         }
3580
3581         /* Just completed a reset, assume that firmware is running again. */
3582         sc->bce_fw_timed_out = 0;
3583         sc->bce_drv_cardiac_arrest = 0;
3584
3585         /* Wait for the firmware to finish its initialization. */
3586         rc = bce_fw_sync(sc, BCE_DRV_MSG_DATA_WAIT1 | reset_code);
3587         if (rc) {
3588                 if_printf(&sc->arpcom.ac_if,
3589                           "Firmware did not complete initialization!\n");
3590         }
3591         return rc;
3592 }
3593
3594
3595 static int
3596 bce_chipinit(struct bce_softc *sc)
3597 {
3598         uint32_t val;
3599         int rc = 0;
3600
3601         /* Make sure the interrupt is not active. */
3602         REG_WR(sc, BCE_PCICFG_INT_ACK_CMD, BCE_PCICFG_INT_ACK_CMD_MASK_INT);
3603         REG_RD(sc, BCE_PCICFG_INT_ACK_CMD);
3604
3605         /*
3606          * Initialize DMA byte/word swapping, configure the number of DMA
3607          * channels and PCI clock compensation delay.
3608          */
3609         val = BCE_DMA_CONFIG_DATA_BYTE_SWAP |
3610               BCE_DMA_CONFIG_DATA_WORD_SWAP |
3611 #if BYTE_ORDER == BIG_ENDIAN
3612               BCE_DMA_CONFIG_CNTL_BYTE_SWAP |
3613 #endif
3614               BCE_DMA_CONFIG_CNTL_WORD_SWAP |
3615               DMA_READ_CHANS << 12 |
3616               DMA_WRITE_CHANS << 16;
3617
3618         val |= (0x2 << 20) | BCE_DMA_CONFIG_CNTL_PCI_COMP_DLY;
3619
3620         if ((sc->bce_flags & BCE_PCIX_FLAG) && sc->bus_speed_mhz == 133)
3621                 val |= BCE_DMA_CONFIG_PCI_FAST_CLK_CMP;
3622
3623         /*
3624          * This setting resolves a problem observed on certain Intel PCI
3625          * chipsets that cannot handle multiple outstanding DMA operations.
3626          * See errata E9_5706A1_65.
3627          */
3628         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5706 &&
3629             BCE_CHIP_ID(sc) != BCE_CHIP_ID_5706_A0 &&
3630             !(sc->bce_flags & BCE_PCIX_FLAG))
3631                 val |= BCE_DMA_CONFIG_CNTL_PING_PONG_DMA;
3632
3633         REG_WR(sc, BCE_DMA_CONFIG, val);
3634
3635         /* Enable the RX_V2P and Context state machines before access. */
3636         REG_WR(sc, BCE_MISC_ENABLE_SET_BITS,
3637                BCE_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE |
3638                BCE_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE |
3639                BCE_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE);
3640
3641         /* Initialize context mapping and zero out the quick contexts. */
3642         rc = bce_init_ctx(sc);
3643         if (rc != 0)
3644                 return rc;
3645
3646         /* Initialize the on-boards CPUs */
3647         bce_init_cpus(sc);
3648
3649         /* Enable management frames (NC-SI) to flow to the MCP. */
3650         if (sc->bce_flags & BCE_MFW_ENABLE_FLAG) {
3651                 val = REG_RD(sc, BCE_RPM_MGMT_PKT_CTRL) |
3652                     BCE_RPM_MGMT_PKT_CTRL_MGMT_EN;
3653                 REG_WR(sc, BCE_RPM_MGMT_PKT_CTRL, val);
3654         }
3655
3656         /* Prepare NVRAM for access. */
3657         rc = bce_init_nvram(sc);
3658         if (rc != 0)
3659                 return rc;
3660
3661         /* Set the kernel bypass block size */
3662         val = REG_RD(sc, BCE_MQ_CONFIG);
3663         val &= ~BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE;
3664         val |= BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE_256;
3665
3666         /* Enable bins used on the 5709/5716. */
3667         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3668             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3669                 val |= BCE_MQ_CONFIG_BIN_MQ_MODE;
3670                 if (BCE_CHIP_ID(sc) == BCE_CHIP_ID_5709_A1)
3671                         val |= BCE_MQ_CONFIG_HALT_DIS;
3672         }
3673
3674         REG_WR(sc, BCE_MQ_CONFIG, val);
3675
3676         val = 0x10000 + (MAX_CID_CNT * MB_KERNEL_CTX_SIZE);
3677         REG_WR(sc, BCE_MQ_KNL_BYP_WIND_START, val);
3678         REG_WR(sc, BCE_MQ_KNL_WIND_END, val);
3679
3680         /* Set the page size and clear the RV2P processor stall bits. */
3681         val = (BCM_PAGE_BITS - 8) << 24;
3682         REG_WR(sc, BCE_RV2P_CONFIG, val);
3683
3684         /* Configure page size. */
3685  &