eefdee481c762292e2bb6419741d3e4411f999d2
[dragonfly.git] / sys / dev / netif / bnx / if_bnx.c
1 /*
2  * Copyright (c) 2001 Wind River Systems
3  * Copyright (c) 1997, 1998, 1999, 2001
4  *      Bill Paul <wpaul@windriver.com>.  All rights reserved.
5  *
6  * Redistribution and use in source and binary forms, with or without
7  * modification, are permitted provided that the following conditions
8  * are met:
9  * 1. Redistributions of source code must retain the above copyright
10  *    notice, this list of conditions and the following disclaimer.
11  * 2. Redistributions in binary form must reproduce the above copyright
12  *    notice, this list of conditions and the following disclaimer in the
13  *    documentation and/or other materials provided with the distribution.
14  * 3. All advertising materials mentioning features or use of this software
15  *    must display the following acknowledgement:
16  *      This product includes software developed by Bill Paul.
17  * 4. Neither the name of the author nor the names of any co-contributors
18  *    may be used to endorse or promote products derived from this software
19  *    without specific prior written permission.
20  *
21  * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
22  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24  * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
25  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
31  * THE POSSIBILITY OF SUCH DAMAGE.
32  *
33  * $FreeBSD: src/sys/dev/bge/if_bge.c,v 1.3.2.39 2005/07/03 03:41:18 silby Exp $
34  */
35
36 #include "opt_bnx.h"
37 #include "opt_ifpoll.h"
38
39 #include <sys/param.h>
40 #include <sys/bus.h>
41 #include <sys/endian.h>
42 #include <sys/kernel.h>
43 #include <sys/interrupt.h>
44 #include <sys/mbuf.h>
45 #include <sys/malloc.h>
46 #include <sys/queue.h>
47 #include <sys/rman.h>
48 #include <sys/serialize.h>
49 #include <sys/socket.h>
50 #include <sys/sockio.h>
51 #include <sys/sysctl.h>
52
53 #include <netinet/ip.h>
54 #include <netinet/tcp.h>
55
56 #include <net/bpf.h>
57 #include <net/ethernet.h>
58 #include <net/if.h>
59 #include <net/if_arp.h>
60 #include <net/if_dl.h>
61 #include <net/if_media.h>
62 #include <net/if_poll.h>
63 #include <net/if_types.h>
64 #include <net/ifq_var.h>
65 #include <net/vlan/if_vlan_var.h>
66 #include <net/vlan/if_vlan_ether.h>
67
68 #include <dev/netif/mii_layer/mii.h>
69 #include <dev/netif/mii_layer/miivar.h>
70 #include <dev/netif/mii_layer/brgphyreg.h>
71
72 #include <bus/pci/pcidevs.h>
73 #include <bus/pci/pcireg.h>
74 #include <bus/pci/pcivar.h>
75
76 #include <dev/netif/bge/if_bgereg.h>
77 #include <dev/netif/bnx/if_bnxvar.h>
78
79 /* "device miibus" required.  See GENERIC if you get errors here. */
80 #include "miibus_if.h"
81
82 #define BNX_CSUM_FEATURES       (CSUM_IP | CSUM_TCP | CSUM_UDP)
83
84 #define BNX_INTR_CKINTVL        ((10 * hz) / 1000)      /* 10ms */
85
86 static const struct bnx_type {
87         uint16_t                bnx_vid;
88         uint16_t                bnx_did;
89         char                    *bnx_name;
90 } bnx_devs[] = {
91         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5717,
92                 "Broadcom BCM5717 Gigabit Ethernet" },
93         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5717C,
94                 "Broadcom BCM5717C Gigabit Ethernet" },
95         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5718,
96                 "Broadcom BCM5718 Gigabit Ethernet" },
97         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5719,
98                 "Broadcom BCM5719 Gigabit Ethernet" },
99         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5720_ALT,
100                 "Broadcom BCM5720 Gigabit Ethernet" },
101
102         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5725,
103                 "Broadcom BCM5725 Gigabit Ethernet" },
104         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5727,
105                 "Broadcom BCM5727 Gigabit Ethernet" },
106         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5762,
107                 "Broadcom BCM5762 Gigabit Ethernet" },
108
109         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57761,
110                 "Broadcom BCM57761 Gigabit Ethernet" },
111         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57762,
112                 "Broadcom BCM57762 Gigabit Ethernet" },
113         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57765,
114                 "Broadcom BCM57765 Gigabit Ethernet" },
115         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57766,
116                 "Broadcom BCM57766 Gigabit Ethernet" },
117         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57781,
118                 "Broadcom BCM57781 Gigabit Ethernet" },
119         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57782,
120                 "Broadcom BCM57782 Gigabit Ethernet" },
121         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57785,
122                 "Broadcom BCM57785 Gigabit Ethernet" },
123         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57786,
124                 "Broadcom BCM57786 Gigabit Ethernet" },
125         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57791,
126                 "Broadcom BCM57791 Fast Ethernet" },
127         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57795,
128                 "Broadcom BCM57795 Fast Ethernet" },
129
130         { 0, 0, NULL }
131 };
132
133 #define BNX_IS_JUMBO_CAPABLE(sc)        ((sc)->bnx_flags & BNX_FLAG_JUMBO)
134 #define BNX_IS_5717_PLUS(sc)            ((sc)->bnx_flags & BNX_FLAG_5717_PLUS)
135 #define BNX_IS_57765_PLUS(sc)           ((sc)->bnx_flags & BNX_FLAG_57765_PLUS)
136 #define BNX_IS_57765_FAMILY(sc)  \
137         ((sc)->bnx_flags & BNX_FLAG_57765_FAMILY)
138
139 typedef int     (*bnx_eaddr_fcn_t)(struct bnx_softc *, uint8_t[]);
140
141 static int      bnx_probe(device_t);
142 static int      bnx_attach(device_t);
143 static int      bnx_detach(device_t);
144 static void     bnx_shutdown(device_t);
145 static int      bnx_suspend(device_t);
146 static int      bnx_resume(device_t);
147 static int      bnx_miibus_readreg(device_t, int, int);
148 static int      bnx_miibus_writereg(device_t, int, int, int);
149 static void     bnx_miibus_statchg(device_t);
150
151 #ifdef IFPOLL_ENABLE
152 static void     bnx_npoll(struct ifnet *, struct ifpoll_info *);
153 static void     bnx_npoll_compat(struct ifnet *, void *, int);
154 #endif
155 static void     bnx_intr_legacy(void *);
156 static void     bnx_msi(void *);
157 static void     bnx_msi_oneshot(void *);
158 static void     bnx_intr(struct bnx_softc *);
159 static void     bnx_enable_intr(struct bnx_softc *);
160 static void     bnx_disable_intr(struct bnx_softc *);
161 static void     bnx_txeof(struct bnx_tx_ring *, uint16_t);
162 static void     bnx_rxeof(struct bnx_softc *, uint16_t, int);
163
164 static void     bnx_start(struct ifnet *, struct ifaltq_subque *);
165 static int      bnx_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
166 static void     bnx_init(void *);
167 static void     bnx_stop(struct bnx_softc *);
168 static void     bnx_watchdog(struct ifnet *);
169 static int      bnx_ifmedia_upd(struct ifnet *);
170 static void     bnx_ifmedia_sts(struct ifnet *, struct ifmediareq *);
171 static void     bnx_tick(void *);
172
173 static int      bnx_alloc_jumbo_mem(struct bnx_softc *);
174 static void     bnx_free_jumbo_mem(struct bnx_softc *);
175 static struct bnx_jslot
176                 *bnx_jalloc(struct bnx_softc *);
177 static void     bnx_jfree(void *);
178 static void     bnx_jref(void *);
179 static int      bnx_newbuf_std(struct bnx_softc *, int, int);
180 static int      bnx_newbuf_jumbo(struct bnx_softc *, int, int);
181 static void     bnx_setup_rxdesc_std(struct bnx_softc *, int);
182 static void     bnx_setup_rxdesc_jumbo(struct bnx_softc *, int);
183 static int      bnx_init_rx_ring_std(struct bnx_softc *);
184 static void     bnx_free_rx_ring_std(struct bnx_softc *);
185 static int      bnx_init_rx_ring_jumbo(struct bnx_softc *);
186 static void     bnx_free_rx_ring_jumbo(struct bnx_softc *);
187 static void     bnx_free_tx_ring(struct bnx_tx_ring *);
188 static int      bnx_init_tx_ring(struct bnx_tx_ring *);
189 static int      bnx_create_tx_ring(struct bnx_tx_ring *);
190 static void     bnx_destroy_tx_ring(struct bnx_tx_ring *);
191 static int      bnx_dma_alloc(struct bnx_softc *);
192 static void     bnx_dma_free(struct bnx_softc *);
193 static int      bnx_dma_block_alloc(struct bnx_softc *, bus_size_t,
194                     bus_dma_tag_t *, bus_dmamap_t *, void **, bus_addr_t *);
195 static void     bnx_dma_block_free(bus_dma_tag_t, bus_dmamap_t, void *);
196 static struct mbuf *
197                 bnx_defrag_shortdma(struct mbuf *);
198 static int      bnx_encap(struct bnx_tx_ring *, struct mbuf **,
199                     uint32_t *, int *);
200 static int      bnx_setup_tso(struct bnx_tx_ring *, struct mbuf **,
201                     uint16_t *, uint16_t *);
202
203 static void     bnx_reset(struct bnx_softc *);
204 static int      bnx_chipinit(struct bnx_softc *);
205 static int      bnx_blockinit(struct bnx_softc *);
206 static void     bnx_stop_block(struct bnx_softc *, bus_size_t, uint32_t);
207 static void     bnx_enable_msi(struct bnx_softc *sc);
208 static void     bnx_setmulti(struct bnx_softc *);
209 static void     bnx_setpromisc(struct bnx_softc *);
210 static void     bnx_stats_update_regs(struct bnx_softc *);
211 static uint32_t bnx_dma_swap_options(struct bnx_softc *);
212
213 static uint32_t bnx_readmem_ind(struct bnx_softc *, uint32_t);
214 static void     bnx_writemem_ind(struct bnx_softc *, uint32_t, uint32_t);
215 #ifdef notdef
216 static uint32_t bnx_readreg_ind(struct bnx_softc *, uint32_t);
217 #endif
218 static void     bnx_writemem_direct(struct bnx_softc *, uint32_t, uint32_t);
219 static void     bnx_writembx(struct bnx_softc *, int, int);
220 static int      bnx_read_nvram(struct bnx_softc *, caddr_t, int, int);
221 static uint8_t  bnx_eeprom_getbyte(struct bnx_softc *, uint32_t, uint8_t *);
222 static int      bnx_read_eeprom(struct bnx_softc *, caddr_t, uint32_t, size_t);
223
224 static void     bnx_tbi_link_upd(struct bnx_softc *, uint32_t);
225 static void     bnx_copper_link_upd(struct bnx_softc *, uint32_t);
226 static void     bnx_autopoll_link_upd(struct bnx_softc *, uint32_t);
227 static void     bnx_link_poll(struct bnx_softc *);
228
229 static int      bnx_get_eaddr_mem(struct bnx_softc *, uint8_t[]);
230 static int      bnx_get_eaddr_nvram(struct bnx_softc *, uint8_t[]);
231 static int      bnx_get_eaddr_eeprom(struct bnx_softc *, uint8_t[]);
232 static int      bnx_get_eaddr(struct bnx_softc *, uint8_t[]);
233
234 static void     bnx_coal_change(struct bnx_softc *);
235 static int      bnx_sysctl_rx_coal_ticks(SYSCTL_HANDLER_ARGS);
236 static int      bnx_sysctl_tx_coal_ticks(SYSCTL_HANDLER_ARGS);
237 static int      bnx_sysctl_rx_coal_bds(SYSCTL_HANDLER_ARGS);
238 static int      bnx_sysctl_tx_coal_bds(SYSCTL_HANDLER_ARGS);
239 static int      bnx_sysctl_rx_coal_bds_int(SYSCTL_HANDLER_ARGS);
240 static int      bnx_sysctl_tx_coal_bds_int(SYSCTL_HANDLER_ARGS);
241 static int      bnx_sysctl_coal_chg(SYSCTL_HANDLER_ARGS, uint32_t *,
242                     int, int, uint32_t);
243
244 static int      bnx_msi_enable = 1;
245 TUNABLE_INT("hw.bnx.msi.enable", &bnx_msi_enable);
246
247 static device_method_t bnx_methods[] = {
248         /* Device interface */
249         DEVMETHOD(device_probe,         bnx_probe),
250         DEVMETHOD(device_attach,        bnx_attach),
251         DEVMETHOD(device_detach,        bnx_detach),
252         DEVMETHOD(device_shutdown,      bnx_shutdown),
253         DEVMETHOD(device_suspend,       bnx_suspend),
254         DEVMETHOD(device_resume,        bnx_resume),
255
256         /* bus interface */
257         DEVMETHOD(bus_print_child,      bus_generic_print_child),
258         DEVMETHOD(bus_driver_added,     bus_generic_driver_added),
259
260         /* MII interface */
261         DEVMETHOD(miibus_readreg,       bnx_miibus_readreg),
262         DEVMETHOD(miibus_writereg,      bnx_miibus_writereg),
263         DEVMETHOD(miibus_statchg,       bnx_miibus_statchg),
264
265         DEVMETHOD_END
266 };
267
268 static DEFINE_CLASS_0(bnx, bnx_driver, bnx_methods, sizeof(struct bnx_softc));
269 static devclass_t bnx_devclass;
270
271 DECLARE_DUMMY_MODULE(if_bnx);
272 DRIVER_MODULE(if_bnx, pci, bnx_driver, bnx_devclass, NULL, NULL);
273 DRIVER_MODULE(miibus, bnx, miibus_driver, miibus_devclass, NULL, NULL);
274
275 static uint32_t
276 bnx_readmem_ind(struct bnx_softc *sc, uint32_t off)
277 {
278         device_t dev = sc->bnx_dev;
279         uint32_t val;
280
281         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
282         val = pci_read_config(dev, BGE_PCI_MEMWIN_DATA, 4);
283         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4);
284         return (val);
285 }
286
287 static void
288 bnx_writemem_ind(struct bnx_softc *sc, uint32_t off, uint32_t val)
289 {
290         device_t dev = sc->bnx_dev;
291
292         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
293         pci_write_config(dev, BGE_PCI_MEMWIN_DATA, val, 4);
294         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4);
295 }
296
297 static void
298 bnx_writemem_direct(struct bnx_softc *sc, uint32_t off, uint32_t val)
299 {
300         CSR_WRITE_4(sc, off, val);
301 }
302
303 static void
304 bnx_writembx(struct bnx_softc *sc, int off, int val)
305 {
306         CSR_WRITE_4(sc, off, val);
307 }
308
309 /*
310  * Read a sequence of bytes from NVRAM.
311  */
312 static int
313 bnx_read_nvram(struct bnx_softc *sc, caddr_t dest, int off, int cnt)
314 {
315         return (1);
316 }
317
318 /*
319  * Read a byte of data stored in the EEPROM at address 'addr.' The
320  * BCM570x supports both the traditional bitbang interface and an
321  * auto access interface for reading the EEPROM. We use the auto
322  * access method.
323  */
324 static uint8_t
325 bnx_eeprom_getbyte(struct bnx_softc *sc, uint32_t addr, uint8_t *dest)
326 {
327         int i;
328         uint32_t byte = 0;
329
330         /*
331          * Enable use of auto EEPROM access so we can avoid
332          * having to use the bitbang method.
333          */
334         BNX_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM);
335
336         /* Reset the EEPROM, load the clock period. */
337         CSR_WRITE_4(sc, BGE_EE_ADDR,
338             BGE_EEADDR_RESET|BGE_EEHALFCLK(BGE_HALFCLK_384SCL));
339         DELAY(20);
340
341         /* Issue the read EEPROM command. */
342         CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr);
343
344         /* Wait for completion */
345         for(i = 0; i < BNX_TIMEOUT * 10; i++) {
346                 DELAY(10);
347                 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE)
348                         break;
349         }
350
351         if (i == BNX_TIMEOUT) {
352                 if_printf(&sc->arpcom.ac_if, "eeprom read timed out\n");
353                 return(1);
354         }
355
356         /* Get result. */
357         byte = CSR_READ_4(sc, BGE_EE_DATA);
358
359         *dest = (byte >> ((addr % 4) * 8)) & 0xFF;
360
361         return(0);
362 }
363
364 /*
365  * Read a sequence of bytes from the EEPROM.
366  */
367 static int
368 bnx_read_eeprom(struct bnx_softc *sc, caddr_t dest, uint32_t off, size_t len)
369 {
370         size_t i;
371         int err;
372         uint8_t byte;
373
374         for (byte = 0, err = 0, i = 0; i < len; i++) {
375                 err = bnx_eeprom_getbyte(sc, off + i, &byte);
376                 if (err)
377                         break;
378                 *(dest + i) = byte;
379         }
380
381         return(err ? 1 : 0);
382 }
383
384 static int
385 bnx_miibus_readreg(device_t dev, int phy, int reg)
386 {
387         struct bnx_softc *sc = device_get_softc(dev);
388         uint32_t val;
389         int i;
390
391         KASSERT(phy == sc->bnx_phyno,
392             ("invalid phyno %d, should be %d", phy, sc->bnx_phyno));
393
394         /* Clear the autopoll bit if set, otherwise may trigger PCI errors. */
395         if (sc->bnx_mi_mode & BGE_MIMODE_AUTOPOLL) {
396                 CSR_WRITE_4(sc, BGE_MI_MODE,
397                     sc->bnx_mi_mode & ~BGE_MIMODE_AUTOPOLL);
398                 DELAY(80);
399         }
400
401         CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ | BGE_MICOMM_BUSY |
402             BGE_MIPHY(phy) | BGE_MIREG(reg));
403
404         /* Poll for the PHY register access to complete. */
405         for (i = 0; i < BNX_TIMEOUT; i++) {
406                 DELAY(10);
407                 val = CSR_READ_4(sc, BGE_MI_COMM);
408                 if ((val & BGE_MICOMM_BUSY) == 0) {
409                         DELAY(5);
410                         val = CSR_READ_4(sc, BGE_MI_COMM);
411                         break;
412                 }
413         }
414         if (i == BNX_TIMEOUT) {
415                 if_printf(&sc->arpcom.ac_if, "PHY read timed out "
416                     "(phy %d, reg %d, val 0x%08x)\n", phy, reg, val);
417                 val = 0;
418         }
419
420         /* Restore the autopoll bit if necessary. */
421         if (sc->bnx_mi_mode & BGE_MIMODE_AUTOPOLL) {
422                 CSR_WRITE_4(sc, BGE_MI_MODE, sc->bnx_mi_mode);
423                 DELAY(80);
424         }
425
426         if (val & BGE_MICOMM_READFAIL)
427                 return 0;
428
429         return (val & 0xFFFF);
430 }
431
432 static int
433 bnx_miibus_writereg(device_t dev, int phy, int reg, int val)
434 {
435         struct bnx_softc *sc = device_get_softc(dev);
436         int i;
437
438         KASSERT(phy == sc->bnx_phyno,
439             ("invalid phyno %d, should be %d", phy, sc->bnx_phyno));
440
441         /* Clear the autopoll bit if set, otherwise may trigger PCI errors. */
442         if (sc->bnx_mi_mode & BGE_MIMODE_AUTOPOLL) {
443                 CSR_WRITE_4(sc, BGE_MI_MODE,
444                     sc->bnx_mi_mode & ~BGE_MIMODE_AUTOPOLL);
445                 DELAY(80);
446         }
447
448         CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE | BGE_MICOMM_BUSY |
449             BGE_MIPHY(phy) | BGE_MIREG(reg) | val);
450
451         for (i = 0; i < BNX_TIMEOUT; i++) {
452                 DELAY(10);
453                 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY)) {
454                         DELAY(5);
455                         CSR_READ_4(sc, BGE_MI_COMM); /* dummy read */
456                         break;
457                 }
458         }
459         if (i == BNX_TIMEOUT) {
460                 if_printf(&sc->arpcom.ac_if, "PHY write timed out "
461                     "(phy %d, reg %d, val %d)\n", phy, reg, val);
462         }
463
464         /* Restore the autopoll bit if necessary. */
465         if (sc->bnx_mi_mode & BGE_MIMODE_AUTOPOLL) {
466                 CSR_WRITE_4(sc, BGE_MI_MODE, sc->bnx_mi_mode);
467                 DELAY(80);
468         }
469
470         return 0;
471 }
472
473 static void
474 bnx_miibus_statchg(device_t dev)
475 {
476         struct bnx_softc *sc;
477         struct mii_data *mii;
478
479         sc = device_get_softc(dev);
480         mii = device_get_softc(sc->bnx_miibus);
481
482         if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
483             (IFM_ACTIVE | IFM_AVALID)) {
484                 switch (IFM_SUBTYPE(mii->mii_media_active)) {
485                 case IFM_10_T:
486                 case IFM_100_TX:
487                         sc->bnx_link = 1;
488                         break;
489                 case IFM_1000_T:
490                 case IFM_1000_SX:
491                 case IFM_2500_SX:
492                         sc->bnx_link = 1;
493                         break;
494                 default:
495                         sc->bnx_link = 0;
496                         break;
497                 }
498         } else {
499                 sc->bnx_link = 0;
500         }
501         if (sc->bnx_link == 0)
502                 return;
503
504         BNX_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_PORTMODE);
505         if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T ||
506             IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) {
507                 BNX_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_GMII);
508         } else {
509                 BNX_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_MII);
510         }
511
512         if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
513                 BNX_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX);
514         } else {
515                 BNX_SETBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX);
516         }
517 }
518
519 /*
520  * Memory management for jumbo frames.
521  */
522 static int
523 bnx_alloc_jumbo_mem(struct bnx_softc *sc)
524 {
525         struct ifnet *ifp = &sc->arpcom.ac_if;
526         struct bnx_jslot *entry;
527         uint8_t *ptr;
528         bus_addr_t paddr;
529         int i, error;
530
531         /*
532          * Create tag for jumbo mbufs.
533          * This is really a bit of a kludge. We allocate a special
534          * jumbo buffer pool which (thanks to the way our DMA
535          * memory allocation works) will consist of contiguous
536          * pages. This means that even though a jumbo buffer might
537          * be larger than a page size, we don't really need to
538          * map it into more than one DMA segment. However, the
539          * default mbuf tag will result in multi-segment mappings,
540          * so we have to create a special jumbo mbuf tag that
541          * lets us get away with mapping the jumbo buffers as
542          * a single segment. I think eventually the driver should
543          * be changed so that it uses ordinary mbufs and cluster
544          * buffers, i.e. jumbo frames can span multiple DMA
545          * descriptors. But that's a project for another day.
546          */
547
548         /*
549          * Create DMA stuffs for jumbo RX ring.
550          */
551         error = bnx_dma_block_alloc(sc, BGE_JUMBO_RX_RING_SZ,
552                                     &sc->bnx_cdata.bnx_rx_jumbo_ring_tag,
553                                     &sc->bnx_cdata.bnx_rx_jumbo_ring_map,
554                                     (void *)&sc->bnx_ldata.bnx_rx_jumbo_ring,
555                                     &sc->bnx_ldata.bnx_rx_jumbo_ring_paddr);
556         if (error) {
557                 if_printf(ifp, "could not create jumbo RX ring\n");
558                 return error;
559         }
560
561         /*
562          * Create DMA stuffs for jumbo buffer block.
563          */
564         error = bnx_dma_block_alloc(sc, BNX_JMEM,
565                                     &sc->bnx_cdata.bnx_jumbo_tag,
566                                     &sc->bnx_cdata.bnx_jumbo_map,
567                                     (void **)&sc->bnx_ldata.bnx_jumbo_buf,
568                                     &paddr);
569         if (error) {
570                 if_printf(ifp, "could not create jumbo buffer\n");
571                 return error;
572         }
573
574         SLIST_INIT(&sc->bnx_jfree_listhead);
575
576         /*
577          * Now divide it up into 9K pieces and save the addresses
578          * in an array. Note that we play an evil trick here by using
579          * the first few bytes in the buffer to hold the the address
580          * of the softc structure for this interface. This is because
581          * bnx_jfree() needs it, but it is called by the mbuf management
582          * code which will not pass it to us explicitly.
583          */
584         for (i = 0, ptr = sc->bnx_ldata.bnx_jumbo_buf; i < BNX_JSLOTS; i++) {
585                 entry = &sc->bnx_cdata.bnx_jslots[i];
586                 entry->bnx_sc = sc;
587                 entry->bnx_buf = ptr;
588                 entry->bnx_paddr = paddr;
589                 entry->bnx_inuse = 0;
590                 entry->bnx_slot = i;
591                 SLIST_INSERT_HEAD(&sc->bnx_jfree_listhead, entry, jslot_link);
592
593                 ptr += BNX_JLEN;
594                 paddr += BNX_JLEN;
595         }
596         return 0;
597 }
598
599 static void
600 bnx_free_jumbo_mem(struct bnx_softc *sc)
601 {
602         /* Destroy jumbo RX ring. */
603         bnx_dma_block_free(sc->bnx_cdata.bnx_rx_jumbo_ring_tag,
604                            sc->bnx_cdata.bnx_rx_jumbo_ring_map,
605                            sc->bnx_ldata.bnx_rx_jumbo_ring);
606
607         /* Destroy jumbo buffer block. */
608         bnx_dma_block_free(sc->bnx_cdata.bnx_jumbo_tag,
609                            sc->bnx_cdata.bnx_jumbo_map,
610                            sc->bnx_ldata.bnx_jumbo_buf);
611 }
612
613 /*
614  * Allocate a jumbo buffer.
615  */
616 static struct bnx_jslot *
617 bnx_jalloc(struct bnx_softc *sc)
618 {
619         struct bnx_jslot *entry;
620
621         lwkt_serialize_enter(&sc->bnx_jslot_serializer);
622         entry = SLIST_FIRST(&sc->bnx_jfree_listhead);
623         if (entry) {
624                 SLIST_REMOVE_HEAD(&sc->bnx_jfree_listhead, jslot_link);
625                 entry->bnx_inuse = 1;
626         } else {
627                 if_printf(&sc->arpcom.ac_if, "no free jumbo buffers\n");
628         }
629         lwkt_serialize_exit(&sc->bnx_jslot_serializer);
630         return(entry);
631 }
632
633 /*
634  * Adjust usage count on a jumbo buffer.
635  */
636 static void
637 bnx_jref(void *arg)
638 {
639         struct bnx_jslot *entry = (struct bnx_jslot *)arg;
640         struct bnx_softc *sc = entry->bnx_sc;
641
642         if (sc == NULL)
643                 panic("bnx_jref: can't find softc pointer!");
644
645         if (&sc->bnx_cdata.bnx_jslots[entry->bnx_slot] != entry) {
646                 panic("bnx_jref: asked to reference buffer "
647                     "that we don't manage!");
648         } else if (entry->bnx_inuse == 0) {
649                 panic("bnx_jref: buffer already free!");
650         } else {
651                 atomic_add_int(&entry->bnx_inuse, 1);
652         }
653 }
654
655 /*
656  * Release a jumbo buffer.
657  */
658 static void
659 bnx_jfree(void *arg)
660 {
661         struct bnx_jslot *entry = (struct bnx_jslot *)arg;
662         struct bnx_softc *sc = entry->bnx_sc;
663
664         if (sc == NULL)
665                 panic("bnx_jfree: can't find softc pointer!");
666
667         if (&sc->bnx_cdata.bnx_jslots[entry->bnx_slot] != entry) {
668                 panic("bnx_jfree: asked to free buffer that we don't manage!");
669         } else if (entry->bnx_inuse == 0) {
670                 panic("bnx_jfree: buffer already free!");
671         } else {
672                 /*
673                  * Possible MP race to 0, use the serializer.  The atomic insn
674                  * is still needed for races against bnx_jref().
675                  */
676                 lwkt_serialize_enter(&sc->bnx_jslot_serializer);
677                 atomic_subtract_int(&entry->bnx_inuse, 1);
678                 if (entry->bnx_inuse == 0) {
679                         SLIST_INSERT_HEAD(&sc->bnx_jfree_listhead, 
680                                           entry, jslot_link);
681                 }
682                 lwkt_serialize_exit(&sc->bnx_jslot_serializer);
683         }
684 }
685
686
687 /*
688  * Intialize a standard receive ring descriptor.
689  */
690 static int
691 bnx_newbuf_std(struct bnx_softc *sc, int i, int init)
692 {
693         struct mbuf *m_new = NULL;
694         bus_dma_segment_t seg;
695         bus_dmamap_t map;
696         int error, nsegs;
697
698         m_new = m_getcl(init ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR);
699         if (m_new == NULL)
700                 return ENOBUFS;
701         m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
702         m_adj(m_new, ETHER_ALIGN);
703
704         error = bus_dmamap_load_mbuf_segment(sc->bnx_cdata.bnx_rx_mtag,
705                         sc->bnx_cdata.bnx_rx_tmpmap, m_new,
706                         &seg, 1, &nsegs, BUS_DMA_NOWAIT);
707         if (error) {
708                 m_freem(m_new);
709                 return error;
710         }
711
712         if (!init) {
713                 bus_dmamap_sync(sc->bnx_cdata.bnx_rx_mtag,
714                                 sc->bnx_cdata.bnx_rx_std_dmamap[i],
715                                 BUS_DMASYNC_POSTREAD);
716                 bus_dmamap_unload(sc->bnx_cdata.bnx_rx_mtag,
717                         sc->bnx_cdata.bnx_rx_std_dmamap[i]);
718         }
719
720         map = sc->bnx_cdata.bnx_rx_tmpmap;
721         sc->bnx_cdata.bnx_rx_tmpmap = sc->bnx_cdata.bnx_rx_std_dmamap[i];
722         sc->bnx_cdata.bnx_rx_std_dmamap[i] = map;
723
724         sc->bnx_cdata.bnx_rx_std_chain[i].bnx_mbuf = m_new;
725         sc->bnx_cdata.bnx_rx_std_chain[i].bnx_paddr = seg.ds_addr;
726
727         bnx_setup_rxdesc_std(sc, i);
728         return 0;
729 }
730
731 static void
732 bnx_setup_rxdesc_std(struct bnx_softc *sc, int i)
733 {
734         struct bnx_rxchain *rc;
735         struct bge_rx_bd *r;
736
737         rc = &sc->bnx_cdata.bnx_rx_std_chain[i];
738         r = &sc->bnx_ldata.bnx_rx_std_ring[i];
739
740         r->bge_addr.bge_addr_lo = BGE_ADDR_LO(rc->bnx_paddr);
741         r->bge_addr.bge_addr_hi = BGE_ADDR_HI(rc->bnx_paddr);
742         r->bge_len = rc->bnx_mbuf->m_len;
743         r->bge_idx = i;
744         r->bge_flags = BGE_RXBDFLAG_END;
745 }
746
747 /*
748  * Initialize a jumbo receive ring descriptor. This allocates
749  * a jumbo buffer from the pool managed internally by the driver.
750  */
751 static int
752 bnx_newbuf_jumbo(struct bnx_softc *sc, int i, int init)
753 {
754         struct mbuf *m_new = NULL;
755         struct bnx_jslot *buf;
756         bus_addr_t paddr;
757
758         /* Allocate the mbuf. */
759         MGETHDR(m_new, init ? MB_WAIT : MB_DONTWAIT, MT_DATA);
760         if (m_new == NULL)
761                 return ENOBUFS;
762
763         /* Allocate the jumbo buffer */
764         buf = bnx_jalloc(sc);
765         if (buf == NULL) {
766                 m_freem(m_new);
767                 return ENOBUFS;
768         }
769
770         /* Attach the buffer to the mbuf. */
771         m_new->m_ext.ext_arg = buf;
772         m_new->m_ext.ext_buf = buf->bnx_buf;
773         m_new->m_ext.ext_free = bnx_jfree;
774         m_new->m_ext.ext_ref = bnx_jref;
775         m_new->m_ext.ext_size = BNX_JUMBO_FRAMELEN;
776
777         m_new->m_flags |= M_EXT;
778
779         m_new->m_data = m_new->m_ext.ext_buf;
780         m_new->m_len = m_new->m_pkthdr.len = m_new->m_ext.ext_size;
781
782         paddr = buf->bnx_paddr;
783         m_adj(m_new, ETHER_ALIGN);
784         paddr += ETHER_ALIGN;
785
786         /* Save necessary information */
787         sc->bnx_cdata.bnx_rx_jumbo_chain[i].bnx_mbuf = m_new;
788         sc->bnx_cdata.bnx_rx_jumbo_chain[i].bnx_paddr = paddr;
789
790         /* Set up the descriptor. */
791         bnx_setup_rxdesc_jumbo(sc, i);
792         return 0;
793 }
794
795 static void
796 bnx_setup_rxdesc_jumbo(struct bnx_softc *sc, int i)
797 {
798         struct bge_rx_bd *r;
799         struct bnx_rxchain *rc;
800
801         r = &sc->bnx_ldata.bnx_rx_jumbo_ring[i];
802         rc = &sc->bnx_cdata.bnx_rx_jumbo_chain[i];
803
804         r->bge_addr.bge_addr_lo = BGE_ADDR_LO(rc->bnx_paddr);
805         r->bge_addr.bge_addr_hi = BGE_ADDR_HI(rc->bnx_paddr);
806         r->bge_len = rc->bnx_mbuf->m_len;
807         r->bge_idx = i;
808         r->bge_flags = BGE_RXBDFLAG_END|BGE_RXBDFLAG_JUMBO_RING;
809 }
810
811 static int
812 bnx_init_rx_ring_std(struct bnx_softc *sc)
813 {
814         int i, error;
815
816         for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
817                 error = bnx_newbuf_std(sc, i, 1);
818                 if (error)
819                         return error;
820         }
821
822         sc->bnx_std = BGE_STD_RX_RING_CNT - 1;
823         bnx_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bnx_std);
824
825         return(0);
826 }
827
828 static void
829 bnx_free_rx_ring_std(struct bnx_softc *sc)
830 {
831         int i;
832
833         for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
834                 struct bnx_rxchain *rc = &sc->bnx_cdata.bnx_rx_std_chain[i];
835
836                 if (rc->bnx_mbuf != NULL) {
837                         bus_dmamap_unload(sc->bnx_cdata.bnx_rx_mtag,
838                                           sc->bnx_cdata.bnx_rx_std_dmamap[i]);
839                         m_freem(rc->bnx_mbuf);
840                         rc->bnx_mbuf = NULL;
841                 }
842                 bzero(&sc->bnx_ldata.bnx_rx_std_ring[i],
843                     sizeof(struct bge_rx_bd));
844         }
845 }
846
847 static int
848 bnx_init_rx_ring_jumbo(struct bnx_softc *sc)
849 {
850         struct bge_rcb *rcb;
851         int i, error;
852
853         for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
854                 error = bnx_newbuf_jumbo(sc, i, 1);
855                 if (error)
856                         return error;
857         }
858
859         sc->bnx_jumbo = BGE_JUMBO_RX_RING_CNT - 1;
860
861         rcb = &sc->bnx_ldata.bnx_info.bnx_jumbo_rx_rcb;
862         rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0, 0);
863         CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
864
865         bnx_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bnx_jumbo);
866
867         return(0);
868 }
869
870 static void
871 bnx_free_rx_ring_jumbo(struct bnx_softc *sc)
872 {
873         int i;
874
875         for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
876                 struct bnx_rxchain *rc = &sc->bnx_cdata.bnx_rx_jumbo_chain[i];
877
878                 if (rc->bnx_mbuf != NULL) {
879                         m_freem(rc->bnx_mbuf);
880                         rc->bnx_mbuf = NULL;
881                 }
882                 bzero(&sc->bnx_ldata.bnx_rx_jumbo_ring[i],
883                     sizeof(struct bge_rx_bd));
884         }
885 }
886
887 static void
888 bnx_free_tx_ring(struct bnx_tx_ring *txr)
889 {
890         int i;
891
892         for (i = 0; i < BGE_TX_RING_CNT; i++) {
893                 if (txr->bnx_tx_chain[i] != NULL) {
894                         bus_dmamap_unload(txr->bnx_tx_mtag,
895                             txr->bnx_tx_dmamap[i]);
896                         m_freem(txr->bnx_tx_chain[i]);
897                         txr->bnx_tx_chain[i] = NULL;
898                 }
899                 bzero(&txr->bnx_tx_ring[i], sizeof(struct bge_tx_bd));
900         }
901         txr->bnx_tx_saved_considx = BNX_TXCONS_UNSET;
902 }
903
904 static int
905 bnx_init_tx_ring(struct bnx_tx_ring *txr)
906 {
907         txr->bnx_txcnt = 0;
908         txr->bnx_tx_saved_considx = 0;
909         txr->bnx_tx_prodidx = 0;
910
911         /* Initialize transmit producer index for host-memory send ring. */
912         bnx_writembx(txr->bnx_sc, BGE_MBX_TX_HOST_PROD0_LO,
913             txr->bnx_tx_prodidx);
914
915         return(0);
916 }
917
918 static void
919 bnx_setmulti(struct bnx_softc *sc)
920 {
921         struct ifnet *ifp;
922         struct ifmultiaddr *ifma;
923         uint32_t hashes[4] = { 0, 0, 0, 0 };
924         int h, i;
925
926         ifp = &sc->arpcom.ac_if;
927
928         if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
929                 for (i = 0; i < 4; i++)
930                         CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0xFFFFFFFF);
931                 return;
932         }
933
934         /* First, zot all the existing filters. */
935         for (i = 0; i < 4; i++)
936                 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0);
937
938         /* Now program new ones. */
939         TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
940                 if (ifma->ifma_addr->sa_family != AF_LINK)
941                         continue;
942                 h = ether_crc32_le(
943                     LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
944                     ETHER_ADDR_LEN) & 0x7f;
945                 hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F);
946         }
947
948         for (i = 0; i < 4; i++)
949                 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]);
950 }
951
952 /*
953  * Do endian, PCI and DMA initialization. Also check the on-board ROM
954  * self-test results.
955  */
956 static int
957 bnx_chipinit(struct bnx_softc *sc)
958 {
959         uint32_t dma_rw_ctl, mode_ctl;
960         int i;
961
962         /* Set endian type before we access any non-PCI registers. */
963         pci_write_config(sc->bnx_dev, BGE_PCI_MISC_CTL,
964             BGE_INIT | BGE_PCIMISCCTL_TAGGED_STATUS, 4);
965
966         /* Clear the MAC control register */
967         CSR_WRITE_4(sc, BGE_MAC_MODE, 0);
968
969         /*
970          * Clear the MAC statistics block in the NIC's
971          * internal memory.
972          */
973         for (i = BGE_STATS_BLOCK;
974             i < BGE_STATS_BLOCK_END + 1; i += sizeof(uint32_t))
975                 BNX_MEMWIN_WRITE(sc, i, 0);
976
977         for (i = BGE_STATUS_BLOCK;
978             i < BGE_STATUS_BLOCK_END + 1; i += sizeof(uint32_t))
979                 BNX_MEMWIN_WRITE(sc, i, 0);
980
981         if (BNX_IS_57765_FAMILY(sc)) {
982                 uint32_t val;
983
984                 if (sc->bnx_chipid == BGE_CHIPID_BCM57765_A0) {
985                         mode_ctl = CSR_READ_4(sc, BGE_MODE_CTL);
986                         val = mode_ctl & ~BGE_MODECTL_PCIE_PORTS;
987
988                         /* Access the lower 1K of PL PCI-E block registers. */
989                         CSR_WRITE_4(sc, BGE_MODE_CTL,
990                             val | BGE_MODECTL_PCIE_PL_SEL);
991
992                         val = CSR_READ_4(sc, BGE_PCIE_PL_LO_PHYCTL5);
993                         val |= BGE_PCIE_PL_LO_PHYCTL5_DIS_L2CLKREQ;
994                         CSR_WRITE_4(sc, BGE_PCIE_PL_LO_PHYCTL5, val);
995
996                         CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl);
997                 }
998                 if (sc->bnx_chiprev != BGE_CHIPREV_57765_AX) {
999                         /* Fix transmit hangs */
1000                         val = CSR_READ_4(sc, BGE_CPMU_PADRNG_CTL);
1001                         val |= BGE_CPMU_PADRNG_CTL_RDIV2;
1002                         CSR_WRITE_4(sc, BGE_CPMU_PADRNG_CTL, val);
1003
1004                         mode_ctl = CSR_READ_4(sc, BGE_MODE_CTL);
1005                         val = mode_ctl & ~BGE_MODECTL_PCIE_PORTS;
1006
1007                         /* Access the lower 1K of DL PCI-E block registers. */
1008                         CSR_WRITE_4(sc, BGE_MODE_CTL,
1009                             val | BGE_MODECTL_PCIE_DL_SEL);
1010
1011                         val = CSR_READ_4(sc, BGE_PCIE_DL_LO_FTSMAX);
1012                         val &= ~BGE_PCIE_DL_LO_FTSMAX_MASK;
1013                         val |= BGE_PCIE_DL_LO_FTSMAX_VAL;
1014                         CSR_WRITE_4(sc, BGE_PCIE_DL_LO_FTSMAX, val);
1015
1016                         CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl);
1017                 }
1018
1019                 val = CSR_READ_4(sc, BGE_CPMU_LSPD_10MB_CLK);
1020                 val &= ~BGE_CPMU_LSPD_10MB_MACCLK_MASK;
1021                 val |= BGE_CPMU_LSPD_10MB_MACCLK_6_25;
1022                 CSR_WRITE_4(sc, BGE_CPMU_LSPD_10MB_CLK, val);
1023         }
1024
1025         /*
1026          * Set up the PCI DMA control register.
1027          */
1028         dma_rw_ctl = pci_read_config(sc->bnx_dev, BGE_PCI_DMA_RW_CTL, 4);
1029         /*
1030          * Disable 32bytes cache alignment for DMA write to host memory
1031          *
1032          * NOTE:
1033          * 64bytes cache alignment for DMA write to host memory is still
1034          * enabled.
1035          */
1036         dma_rw_ctl |= BGE_PCIDMARWCTL_DIS_CACHE_ALIGNMENT;
1037         if (sc->bnx_chipid == BGE_CHIPID_BCM57765_A0)
1038                 dma_rw_ctl &= ~BGE_PCIDMARWCTL_CRDRDR_RDMA_MRRS_MSK;
1039         /*
1040          * Enable HW workaround for controllers that misinterpret
1041          * a status tag update and leave interrupts permanently
1042          * disabled.
1043          */
1044         if (sc->bnx_asicrev != BGE_ASICREV_BCM5717 &&
1045             sc->bnx_asicrev != BGE_ASICREV_BCM5762 &&
1046             !BNX_IS_57765_FAMILY(sc))
1047                 dma_rw_ctl |= BGE_PCIDMARWCTL_TAGGED_STATUS_WA;
1048         if (bootverbose) {
1049                 if_printf(&sc->arpcom.ac_if, "DMA read/write %#x\n",
1050                     dma_rw_ctl);
1051         }
1052         pci_write_config(sc->bnx_dev, BGE_PCI_DMA_RW_CTL, dma_rw_ctl, 4);
1053
1054         /*
1055          * Set up general mode register.
1056          */
1057         mode_ctl = bnx_dma_swap_options(sc) | BGE_MODECTL_MAC_ATTN_INTR |
1058             BGE_MODECTL_HOST_SEND_BDS | BGE_MODECTL_TX_NO_PHDR_CSUM;
1059         CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl);
1060
1061         /*
1062          * Disable memory write invalidate.  Apparently it is not supported
1063          * properly by these devices.  Also ensure that INTx isn't disabled,
1064          * as these chips need it even when using MSI.
1065          */
1066         PCI_CLRBIT(sc->bnx_dev, BGE_PCI_CMD,
1067             (PCIM_CMD_MWRICEN | PCIM_CMD_INTxDIS), 4);
1068
1069         /* Set the timer prescaler (always 66Mhz) */
1070         CSR_WRITE_4(sc, BGE_MISC_CFG, 65 << 1/*BGE_32BITTIME_66MHZ*/);
1071
1072         return(0);
1073 }
1074
1075 static int
1076 bnx_blockinit(struct bnx_softc *sc)
1077 {
1078         struct bnx_tx_ring *txr = &sc->bnx_tx_ring[0];
1079         struct bge_rcb *rcb;
1080         bus_size_t vrcb;
1081         bge_hostaddr taddr;
1082         uint32_t val;
1083         int i, limit;
1084
1085         /*
1086          * Initialize the memory window pointer register so that
1087          * we can access the first 32K of internal NIC RAM. This will
1088          * allow us to set up the TX send ring RCBs and the RX return
1089          * ring RCBs, plus other things which live in NIC memory.
1090          */
1091         CSR_WRITE_4(sc, BGE_PCI_MEMWIN_BASEADDR, 0);
1092
1093         /* Configure mbuf pool watermarks */
1094         if (BNX_IS_57765_PLUS(sc)) {
1095                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
1096                 if (sc->arpcom.ac_if.if_mtu > ETHERMTU) {
1097                         CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x7e);
1098                         CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0xea);
1099                 } else {
1100                         CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x2a);
1101                         CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0xa0);
1102                 }
1103         } else {
1104                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
1105                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10);
1106                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60);
1107         }
1108
1109         /* Configure DMA resource watermarks */
1110         CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5);
1111         CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10);
1112
1113         /* Enable buffer manager */
1114         val = BGE_BMANMODE_ENABLE | BGE_BMANMODE_LOMBUF_ATTN;
1115         /*
1116          * Change the arbitration algorithm of TXMBUF read request to
1117          * round-robin instead of priority based for BCM5719.  When
1118          * TXFIFO is almost empty, RDMA will hold its request until
1119          * TXFIFO is not almost empty.
1120          */
1121         if (sc->bnx_asicrev == BGE_ASICREV_BCM5719)
1122                 val |= BGE_BMANMODE_NO_TX_UNDERRUN;
1123         if (sc->bnx_asicrev == BGE_ASICREV_BCM5717 ||
1124             sc->bnx_chipid == BGE_CHIPID_BCM5719_A0 ||
1125             sc->bnx_chipid == BGE_CHIPID_BCM5720_A0)
1126                 val |= BGE_BMANMODE_LOMBUF_ATTN;
1127         CSR_WRITE_4(sc, BGE_BMAN_MODE, val);
1128
1129         /* Poll for buffer manager start indication */
1130         for (i = 0; i < BNX_TIMEOUT; i++) {
1131                 if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE)
1132                         break;
1133                 DELAY(10);
1134         }
1135
1136         if (i == BNX_TIMEOUT) {
1137                 if_printf(&sc->arpcom.ac_if,
1138                           "buffer manager failed to start\n");
1139                 return(ENXIO);
1140         }
1141
1142         /* Enable flow-through queues */
1143         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
1144         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
1145
1146         /* Wait until queue initialization is complete */
1147         for (i = 0; i < BNX_TIMEOUT; i++) {
1148                 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0)
1149                         break;
1150                 DELAY(10);
1151         }
1152
1153         if (i == BNX_TIMEOUT) {
1154                 if_printf(&sc->arpcom.ac_if,
1155                           "flow-through queue init failed\n");
1156                 return(ENXIO);
1157         }
1158
1159         /*
1160          * Summary of rings supported by the controller:
1161          *
1162          * Standard Receive Producer Ring
1163          * - This ring is used to feed receive buffers for "standard"
1164          *   sized frames (typically 1536 bytes) to the controller.
1165          *
1166          * Jumbo Receive Producer Ring
1167          * - This ring is used to feed receive buffers for jumbo sized
1168          *   frames (i.e. anything bigger than the "standard" frames)
1169          *   to the controller.
1170          *
1171          * Mini Receive Producer Ring
1172          * - This ring is used to feed receive buffers for "mini"
1173          *   sized frames to the controller.
1174          * - This feature required external memory for the controller
1175          *   but was never used in a production system.  Should always
1176          *   be disabled.
1177          *
1178          * Receive Return Ring
1179          * - After the controller has placed an incoming frame into a
1180          *   receive buffer that buffer is moved into a receive return
1181          *   ring.  The driver is then responsible to passing the
1182          *   buffer up to the stack.  Many versions of the controller
1183          *   support multiple RR rings.
1184          *
1185          * Send Ring
1186          * - This ring is used for outgoing frames.  Many versions of
1187          *   the controller support multiple send rings.
1188          */
1189
1190         /* Initialize the standard receive producer ring control block. */
1191         rcb = &sc->bnx_ldata.bnx_info.bnx_std_rx_rcb;
1192         rcb->bge_hostaddr.bge_addr_lo =
1193             BGE_ADDR_LO(sc->bnx_ldata.bnx_rx_std_ring_paddr);
1194         rcb->bge_hostaddr.bge_addr_hi =
1195             BGE_ADDR_HI(sc->bnx_ldata.bnx_rx_std_ring_paddr);
1196         if (BNX_IS_57765_PLUS(sc)) {
1197                 /*
1198                  * Bits 31-16: Programmable ring size (2048, 1024, 512, .., 32)
1199                  * Bits 15-2 : Maximum RX frame size
1200                  * Bit 1     : 1 = Ring Disabled, 0 = Ring ENabled
1201                  * Bit 0     : Reserved
1202                  */
1203                 rcb->bge_maxlen_flags =
1204                     BGE_RCB_MAXLEN_FLAGS(512, BNX_MAX_FRAMELEN << 2);
1205         } else {
1206                 /*
1207                  * Bits 31-16: Programmable ring size (512, 256, 128, 64, 32)
1208                  * Bits 15-2 : Reserved (should be 0)
1209                  * Bit 1     : 1 = Ring Disabled, 0 = Ring Enabled
1210                  * Bit 0     : Reserved
1211                  */
1212                 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0);
1213         }
1214         if (BNX_IS_5717_PLUS(sc))
1215                 rcb->bge_nicaddr = BGE_STD_RX_RINGS_5717;
1216         else
1217                 rcb->bge_nicaddr = BGE_STD_RX_RINGS;
1218         /* Write the standard receive producer ring control block. */
1219         CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi);
1220         CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo);
1221         CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
1222         CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr);
1223         /* Reset the standard receive producer ring producer index. */
1224         bnx_writembx(sc, BGE_MBX_RX_STD_PROD_LO, 0);
1225
1226         /*
1227          * Initialize the jumbo RX producer ring control
1228          * block.  We set the 'ring disabled' bit in the
1229          * flags field until we're actually ready to start
1230          * using this ring (i.e. once we set the MTU
1231          * high enough to require it).
1232          */
1233         if (BNX_IS_JUMBO_CAPABLE(sc)) {
1234                 rcb = &sc->bnx_ldata.bnx_info.bnx_jumbo_rx_rcb;
1235                 /* Get the jumbo receive producer ring RCB parameters. */
1236                 rcb->bge_hostaddr.bge_addr_lo =
1237                     BGE_ADDR_LO(sc->bnx_ldata.bnx_rx_jumbo_ring_paddr);
1238                 rcb->bge_hostaddr.bge_addr_hi =
1239                     BGE_ADDR_HI(sc->bnx_ldata.bnx_rx_jumbo_ring_paddr);
1240                 rcb->bge_maxlen_flags =
1241                     BGE_RCB_MAXLEN_FLAGS(BNX_MAX_FRAMELEN,
1242                     BGE_RCB_FLAG_RING_DISABLED);
1243                 if (BNX_IS_5717_PLUS(sc))
1244                         rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS_5717;
1245                 else
1246                         rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS;
1247                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI,
1248                     rcb->bge_hostaddr.bge_addr_hi);
1249                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO,
1250                     rcb->bge_hostaddr.bge_addr_lo);
1251                 /* Program the jumbo receive producer ring RCB parameters. */
1252                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS,
1253                     rcb->bge_maxlen_flags);
1254                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr);
1255                 /* Reset the jumbo receive producer ring producer index. */
1256                 bnx_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0);
1257         }
1258
1259         /*
1260          * The BD ring replenish thresholds control how often the
1261          * hardware fetches new BD's from the producer rings in host
1262          * memory.  Setting the value too low on a busy system can
1263          * starve the hardware and recue the throughpout.
1264          *
1265          * Set the BD ring replentish thresholds. The recommended
1266          * values are 1/8th the number of descriptors allocated to
1267          * each ring.
1268          */
1269         val = 8;
1270         CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, val);
1271         if (BNX_IS_JUMBO_CAPABLE(sc)) {
1272                 CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH,
1273                     BGE_JUMBO_RX_RING_CNT/8);
1274         }
1275         if (BNX_IS_57765_PLUS(sc)) {
1276                 CSR_WRITE_4(sc, BGE_STD_REPLENISH_LWM, 32);
1277                 CSR_WRITE_4(sc, BGE_JMB_REPLENISH_LWM, 16);
1278         }
1279
1280         /*
1281          * Disable all send rings by setting the 'ring disabled' bit
1282          * in the flags field of all the TX send ring control blocks,
1283          * located in NIC memory.
1284          */
1285         if (BNX_IS_5717_PLUS(sc))
1286                 limit = 4;
1287         else if (BNX_IS_57765_FAMILY(sc) ||
1288             sc->bnx_asicrev == BGE_ASICREV_BCM5762)
1289                 limit = 2;
1290         else
1291                 limit = 1;
1292         vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB;
1293         for (i = 0; i < limit; i++) {
1294                 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1295                     BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED));
1296                 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
1297                 vrcb += sizeof(struct bge_rcb);
1298         }
1299
1300         /* Configure send ring RCB 0 (we use only the first ring) */
1301         vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB;
1302         BGE_HOSTADDR(taddr, txr->bnx_tx_ring_paddr);
1303         RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi);
1304         RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo);
1305         if (BNX_IS_5717_PLUS(sc)) {
1306                 RCB_WRITE_4(sc, vrcb, bge_nicaddr, BGE_SEND_RING_5717);
1307         } else {
1308                 RCB_WRITE_4(sc, vrcb, bge_nicaddr,
1309                     BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT));
1310         }
1311         RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1312             BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0));
1313
1314         /*
1315          * Disable all receive return rings by setting the
1316          * 'ring disabled' bit in the flags field of all the receive
1317          * return ring control blocks, located in NIC memory.
1318          */
1319         if (BNX_IS_5717_PLUS(sc)) {
1320                 /* Should be 17, use 16 until we get an SRAM map. */
1321                 limit = 16;
1322         } else if (BNX_IS_57765_FAMILY(sc) ||
1323             sc->bnx_asicrev == BGE_ASICREV_BCM5762) {
1324                 limit = 4;
1325         } else {
1326                 limit = 1;
1327         }
1328         /* Disable all receive return rings. */
1329         vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB;
1330         for (i = 0; i < limit; i++) {
1331                 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, 0);
1332                 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, 0);
1333                 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1334                     BGE_RCB_FLAG_RING_DISABLED);
1335                 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
1336                 bnx_writembx(sc, BGE_MBX_RX_CONS0_LO +
1337                     (i * (sizeof(uint64_t))), 0);
1338                 vrcb += sizeof(struct bge_rcb);
1339         }
1340
1341         /*
1342          * Set up receive return ring 0.  Note that the NIC address
1343          * for RX return rings is 0x0.  The return rings live entirely
1344          * within the host, so the nicaddr field in the RCB isn't used.
1345          */
1346         vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB;
1347         BGE_HOSTADDR(taddr, sc->bnx_ldata.bnx_rx_return_ring_paddr);
1348         RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi);
1349         RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo);
1350         RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
1351         RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1352             BGE_RCB_MAXLEN_FLAGS(BNX_RETURN_RING_CNT, 0));
1353
1354         /* Set random backoff seed for TX */
1355         CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF,
1356             sc->arpcom.ac_enaddr[0] + sc->arpcom.ac_enaddr[1] +
1357             sc->arpcom.ac_enaddr[2] + sc->arpcom.ac_enaddr[3] +
1358             sc->arpcom.ac_enaddr[4] + sc->arpcom.ac_enaddr[5] +
1359             BGE_TX_BACKOFF_SEED_MASK);
1360
1361         /* Set inter-packet gap */
1362         val = 0x2620;
1363         if (sc->bnx_asicrev == BGE_ASICREV_BCM5720 ||
1364             sc->bnx_asicrev == BGE_ASICREV_BCM5762) {
1365                 val |= CSR_READ_4(sc, BGE_TX_LENGTHS) &
1366                     (BGE_TXLEN_JMB_FRM_LEN_MSK | BGE_TXLEN_CNT_DN_VAL_MSK);
1367         }
1368         CSR_WRITE_4(sc, BGE_TX_LENGTHS, val);
1369
1370         /*
1371          * Specify which ring to use for packets that don't match
1372          * any RX rules.
1373          */
1374         CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08);
1375
1376         /*
1377          * Configure number of RX lists. One interrupt distribution
1378          * list, sixteen active lists, one bad frames class.
1379          */
1380         CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181);
1381
1382         /* Inialize RX list placement stats mask. */
1383         CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF);
1384         CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1);
1385
1386         /* Disable host coalescing until we get it set up */
1387         CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000);
1388
1389         /* Poll to make sure it's shut down. */
1390         for (i = 0; i < BNX_TIMEOUT; i++) {
1391                 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE))
1392                         break;
1393                 DELAY(10);
1394         }
1395
1396         if (i == BNX_TIMEOUT) {
1397                 if_printf(&sc->arpcom.ac_if,
1398                           "host coalescing engine failed to idle\n");
1399                 return(ENXIO);
1400         }
1401
1402         /* Set up host coalescing defaults */
1403         CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bnx_rx_coal_ticks);
1404         CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bnx_tx_coal_ticks);
1405         CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bnx_rx_coal_bds);
1406         CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bnx_tx_coal_bds);
1407         CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, sc->bnx_rx_coal_bds_int);
1408         CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, sc->bnx_tx_coal_bds_int);
1409
1410         /* Set up address of status block */
1411         bzero(sc->bnx_ldata.bnx_status_block, BGE_STATUS_BLK_SZ);
1412         CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI,
1413             BGE_ADDR_HI(sc->bnx_ldata.bnx_status_block_paddr));
1414         CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO,
1415             BGE_ADDR_LO(sc->bnx_ldata.bnx_status_block_paddr));
1416
1417         /* Set up status block partail update size. */
1418         val = BGE_STATBLKSZ_32BYTE;
1419 #if 0
1420         /*
1421          * Does not seem to have visible effect in both
1422          * bulk data (1472B UDP datagram) and tiny data
1423          * (18B UDP datagram) TX tests.
1424          */
1425         val |= BGE_HCCMODE_CLRTICK_TX;
1426 #endif
1427         /* Turn on host coalescing state machine */
1428         CSR_WRITE_4(sc, BGE_HCC_MODE, val | BGE_HCCMODE_ENABLE);
1429
1430         /* Turn on RX BD completion state machine and enable attentions */
1431         CSR_WRITE_4(sc, BGE_RBDC_MODE,
1432             BGE_RBDCMODE_ENABLE|BGE_RBDCMODE_ATTN);
1433
1434         /* Turn on RX list placement state machine */
1435         CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
1436
1437         val = BGE_MACMODE_TXDMA_ENB | BGE_MACMODE_RXDMA_ENB |
1438             BGE_MACMODE_RX_STATS_CLEAR | BGE_MACMODE_TX_STATS_CLEAR |
1439             BGE_MACMODE_RX_STATS_ENB | BGE_MACMODE_TX_STATS_ENB |
1440             BGE_MACMODE_FRMHDR_DMA_ENB;
1441
1442         if (sc->bnx_flags & BNX_FLAG_TBI)
1443                 val |= BGE_PORTMODE_TBI;
1444         else if (sc->bnx_flags & BNX_FLAG_MII_SERDES)
1445                 val |= BGE_PORTMODE_GMII;
1446         else
1447                 val |= BGE_PORTMODE_MII;
1448
1449         /* Turn on DMA, clear stats */
1450         CSR_WRITE_4(sc, BGE_MAC_MODE, val);
1451
1452         /* Set misc. local control, enable interrupts on attentions */
1453         CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN);
1454
1455 #ifdef notdef
1456         /* Assert GPIO pins for PHY reset */
1457         BNX_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0|
1458             BGE_MLC_MISCIO_OUT1|BGE_MLC_MISCIO_OUT2);
1459         BNX_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0|
1460             BGE_MLC_MISCIO_OUTEN1|BGE_MLC_MISCIO_OUTEN2);
1461 #endif
1462
1463         /* Turn on write DMA state machine */
1464         val = BGE_WDMAMODE_ENABLE|BGE_WDMAMODE_ALL_ATTNS;
1465         /* Enable host coalescing bug fix. */
1466         val |= BGE_WDMAMODE_STATUS_TAG_FIX;
1467         if (sc->bnx_asicrev == BGE_ASICREV_BCM5785) {
1468                 /* Request larger DMA burst size to get better performance. */
1469                 val |= BGE_WDMAMODE_BURST_ALL_DATA;
1470         }
1471         CSR_WRITE_4(sc, BGE_WDMA_MODE, val);
1472         DELAY(40);
1473
1474         if (BNX_IS_57765_PLUS(sc)) {
1475                 uint32_t dmactl, dmactl_reg;
1476
1477                 if (sc->bnx_asicrev == BGE_ASICREV_BCM5762)
1478                         dmactl_reg = BGE_RDMA_RSRVCTRL2;
1479                 else
1480                         dmactl_reg = BGE_RDMA_RSRVCTRL;
1481
1482                 dmactl = CSR_READ_4(sc, dmactl_reg);
1483                 /*
1484                  * Adjust tx margin to prevent TX data corruption and
1485                  * fix internal FIFO overflow.
1486                  */
1487                 if (sc->bnx_asicrev == BGE_ASICREV_BCM5719 ||
1488                     sc->bnx_asicrev == BGE_ASICREV_BCM5720 ||
1489                     sc->bnx_asicrev == BGE_ASICREV_BCM5762) {
1490                         dmactl &= ~(BGE_RDMA_RSRVCTRL_FIFO_LWM_MASK |
1491                             BGE_RDMA_RSRVCTRL_FIFO_HWM_MASK |
1492                             BGE_RDMA_RSRVCTRL_TXMRGN_MASK);
1493                         dmactl |= BGE_RDMA_RSRVCTRL_FIFO_LWM_1_5K |
1494                             BGE_RDMA_RSRVCTRL_FIFO_HWM_1_5K |
1495                             BGE_RDMA_RSRVCTRL_TXMRGN_320B;
1496                 }
1497                 /*
1498                  * Enable fix for read DMA FIFO overruns.
1499                  * The fix is to limit the number of RX BDs
1500                  * the hardware would fetch at a fime.
1501                  */
1502                 CSR_WRITE_4(sc, dmactl_reg,
1503                     dmactl | BGE_RDMA_RSRVCTRL_FIFO_OFLW_FIX);
1504         }
1505
1506         if (sc->bnx_asicrev == BGE_ASICREV_BCM5719) {
1507                 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL,
1508                     CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL) |
1509                     BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_4K |
1510                     BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K);
1511         } else if (sc->bnx_asicrev == BGE_ASICREV_BCM5720 ||
1512             sc->bnx_asicrev == BGE_ASICREV_BCM5762) {
1513                 uint32_t ctrl_reg;
1514
1515                 if (sc->bnx_asicrev == BGE_ASICREV_BCM5762)
1516                         ctrl_reg = BGE_RDMA_LSO_CRPTEN_CTRL2;
1517                 else
1518                         ctrl_reg = BGE_RDMA_LSO_CRPTEN_CTRL;
1519
1520                 /*
1521                  * Allow 4KB burst length reads for non-LSO frames.
1522                  * Enable 512B burst length reads for buffer descriptors.
1523                  */
1524                 CSR_WRITE_4(sc, ctrl_reg,
1525                     CSR_READ_4(sc, ctrl_reg) |
1526                     BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_512 |
1527                     BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K);
1528         }
1529
1530         /* Turn on read DMA state machine */
1531         val = BGE_RDMAMODE_ENABLE | BGE_RDMAMODE_ALL_ATTNS;
1532         if (sc->bnx_asicrev == BGE_ASICREV_BCM5717)
1533                 val |= BGE_RDMAMODE_MULT_DMA_RD_DIS;
1534         if (sc->bnx_asicrev == BGE_ASICREV_BCM5784 ||
1535             sc->bnx_asicrev == BGE_ASICREV_BCM5785 ||
1536             sc->bnx_asicrev == BGE_ASICREV_BCM57780) {
1537                 val |= BGE_RDMAMODE_BD_SBD_CRPT_ATTN |
1538                     BGE_RDMAMODE_MBUF_RBD_CRPT_ATTN |
1539                     BGE_RDMAMODE_MBUF_SBD_CRPT_ATTN;
1540         }
1541         if (sc->bnx_asicrev == BGE_ASICREV_BCM5720 ||
1542             sc->bnx_asicrev == BGE_ASICREV_BCM5762) {
1543                 val |= CSR_READ_4(sc, BGE_RDMA_MODE) &
1544                     BGE_RDMAMODE_H2BNC_VLAN_DET;
1545                 /*
1546                  * Allow multiple outstanding read requests from
1547                  * non-LSO read DMA engine.
1548                  */
1549                 val &= ~BGE_RDMAMODE_MULT_DMA_RD_DIS;
1550         }
1551         if (sc->bnx_asicrev == BGE_ASICREV_BCM57766)
1552                 val |= BGE_RDMAMODE_JMB_2K_MMRR;
1553         if (sc->bnx_flags & BNX_FLAG_TSO)
1554                 val |= BGE_RDMAMODE_TSO4_ENABLE;
1555         val |= BGE_RDMAMODE_FIFO_LONG_BURST;
1556         CSR_WRITE_4(sc, BGE_RDMA_MODE, val);
1557         DELAY(40);
1558
1559         /* Turn on RX data completion state machine */
1560         CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
1561
1562         /* Turn on RX BD initiator state machine */
1563         CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
1564
1565         /* Turn on RX data and RX BD initiator state machine */
1566         CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE);
1567
1568         /* Turn on send BD completion state machine */
1569         CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
1570
1571         /* Turn on send data completion state machine */
1572         val = BGE_SDCMODE_ENABLE;
1573         if (sc->bnx_asicrev == BGE_ASICREV_BCM5761)
1574                 val |= BGE_SDCMODE_CDELAY; 
1575         CSR_WRITE_4(sc, BGE_SDC_MODE, val);
1576
1577         /* Turn on send data initiator state machine */
1578         if (sc->bnx_flags & BNX_FLAG_TSO) {
1579                 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE |
1580                     BGE_SDIMODE_HW_LSO_PRE_DMA);
1581         } else {
1582                 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
1583         }
1584
1585         /* Turn on send BD initiator state machine */
1586         CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
1587
1588         /* Turn on send BD selector state machine */
1589         CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
1590
1591         CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF);
1592         CSR_WRITE_4(sc, BGE_SDI_STATS_CTL,
1593             BGE_SDISTATSCTL_ENABLE|BGE_SDISTATSCTL_FASTER);
1594
1595         /* ack/clear link change events */
1596         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED|
1597             BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE|
1598             BGE_MACSTAT_LINK_CHANGED);
1599         CSR_WRITE_4(sc, BGE_MI_STS, 0);
1600
1601         /*
1602          * Enable attention when the link has changed state for
1603          * devices that use auto polling.
1604          */
1605         if (sc->bnx_flags & BNX_FLAG_TBI) {
1606                 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK);
1607         } else {
1608                 if (sc->bnx_mi_mode & BGE_MIMODE_AUTOPOLL) {
1609                         CSR_WRITE_4(sc, BGE_MI_MODE, sc->bnx_mi_mode);
1610                         DELAY(80);
1611                 }
1612         }
1613
1614         /*
1615          * Clear any pending link state attention.
1616          * Otherwise some link state change events may be lost until attention
1617          * is cleared by bnx_intr() -> bnx_softc.bnx_link_upd() sequence.
1618          * It's not necessary on newer BCM chips - perhaps enabling link
1619          * state change attentions implies clearing pending attention.
1620          */
1621         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED|
1622             BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE|
1623             BGE_MACSTAT_LINK_CHANGED);
1624
1625         /* Enable link state change attentions. */
1626         BNX_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED);
1627
1628         return(0);
1629 }
1630
1631 /*
1632  * Probe for a Broadcom chip. Check the PCI vendor and device IDs
1633  * against our list and return its name if we find a match. Note
1634  * that since the Broadcom controller contains VPD support, we
1635  * can get the device name string from the controller itself instead
1636  * of the compiled-in string. This is a little slow, but it guarantees
1637  * we'll always announce the right product name.
1638  */
1639 static int
1640 bnx_probe(device_t dev)
1641 {
1642         const struct bnx_type *t;
1643         uint16_t product, vendor;
1644
1645         if (!pci_is_pcie(dev))
1646                 return ENXIO;
1647
1648         product = pci_get_device(dev);
1649         vendor = pci_get_vendor(dev);
1650
1651         for (t = bnx_devs; t->bnx_name != NULL; t++) {
1652                 if (vendor == t->bnx_vid && product == t->bnx_did)
1653                         break;
1654         }
1655         if (t->bnx_name == NULL)
1656                 return ENXIO;
1657
1658         device_set_desc(dev, t->bnx_name);
1659         return 0;
1660 }
1661
1662 static int
1663 bnx_attach(device_t dev)
1664 {
1665         struct ifnet *ifp;
1666         struct bnx_softc *sc;
1667         uint32_t hwcfg = 0;
1668         int error = 0, rid, capmask;
1669         uint8_t ether_addr[ETHER_ADDR_LEN];
1670         uint16_t product;
1671         driver_intr_t *intr_func;
1672         uintptr_t mii_priv = 0;
1673         u_int intr_flags;
1674 #ifdef BNX_TSO_DEBUG
1675         char desc[32];
1676         int i;
1677 #endif
1678
1679         sc = device_get_softc(dev);
1680         sc->bnx_dev = dev;
1681         callout_init_mp(&sc->bnx_stat_timer);
1682         callout_init_mp(&sc->bnx_intr_timer);
1683         lwkt_serialize_init(&sc->bnx_jslot_serializer);
1684
1685         product = pci_get_device(dev);
1686
1687 #ifndef BURN_BRIDGES
1688         if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
1689                 uint32_t irq, mem;
1690
1691                 irq = pci_read_config(dev, PCIR_INTLINE, 4);
1692                 mem = pci_read_config(dev, BGE_PCI_BAR0, 4);
1693
1694                 device_printf(dev, "chip is in D%d power mode "
1695                     "-- setting to D0\n", pci_get_powerstate(dev));
1696
1697                 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
1698
1699                 pci_write_config(dev, PCIR_INTLINE, irq, 4);
1700                 pci_write_config(dev, BGE_PCI_BAR0, mem, 4);
1701         }
1702 #endif  /* !BURN_BRIDGE */
1703
1704         /*
1705          * Map control/status registers.
1706          */
1707         pci_enable_busmaster(dev);
1708
1709         rid = BGE_PCI_BAR0;
1710         sc->bnx_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
1711             RF_ACTIVE);
1712
1713         if (sc->bnx_res == NULL) {
1714                 device_printf(dev, "couldn't map memory\n");
1715                 return ENXIO;
1716         }
1717
1718         sc->bnx_btag = rman_get_bustag(sc->bnx_res);
1719         sc->bnx_bhandle = rman_get_bushandle(sc->bnx_res);
1720
1721         /* Save various chip information */
1722         sc->bnx_chipid =
1723             pci_read_config(dev, BGE_PCI_MISC_CTL, 4) >>
1724             BGE_PCIMISCCTL_ASICREV_SHIFT;
1725         if (BGE_ASICREV(sc->bnx_chipid) == BGE_ASICREV_USE_PRODID_REG) {
1726                 /* All chips having dedicated ASICREV register have CPMU */
1727                 sc->bnx_flags |= BNX_FLAG_CPMU;
1728
1729                 switch (product) {
1730                 case PCI_PRODUCT_BROADCOM_BCM5717:
1731                 case PCI_PRODUCT_BROADCOM_BCM5717C:
1732                 case PCI_PRODUCT_BROADCOM_BCM5718:
1733                 case PCI_PRODUCT_BROADCOM_BCM5719:
1734                 case PCI_PRODUCT_BROADCOM_BCM5720_ALT:
1735                 case PCI_PRODUCT_BROADCOM_BCM5725:
1736                 case PCI_PRODUCT_BROADCOM_BCM5727:
1737                 case PCI_PRODUCT_BROADCOM_BCM5762:
1738                         sc->bnx_chipid = pci_read_config(dev,
1739                             BGE_PCI_GEN2_PRODID_ASICREV, 4);
1740                         break;
1741
1742                 case PCI_PRODUCT_BROADCOM_BCM57761:
1743                 case PCI_PRODUCT_BROADCOM_BCM57762:
1744                 case PCI_PRODUCT_BROADCOM_BCM57765:
1745                 case PCI_PRODUCT_BROADCOM_BCM57766:
1746                 case PCI_PRODUCT_BROADCOM_BCM57781:
1747                 case PCI_PRODUCT_BROADCOM_BCM57782:
1748                 case PCI_PRODUCT_BROADCOM_BCM57785:
1749                 case PCI_PRODUCT_BROADCOM_BCM57786:
1750                 case PCI_PRODUCT_BROADCOM_BCM57791:
1751                 case PCI_PRODUCT_BROADCOM_BCM57795:
1752                         sc->bnx_chipid = pci_read_config(dev,
1753                             BGE_PCI_GEN15_PRODID_ASICREV, 4);
1754                         break;
1755
1756                 default:
1757                         sc->bnx_chipid = pci_read_config(dev,
1758                             BGE_PCI_PRODID_ASICREV, 4);
1759                         break;
1760                 }
1761         }
1762         if (sc->bnx_chipid == BGE_CHIPID_BCM5717_C0)
1763                 sc->bnx_chipid = BGE_CHIPID_BCM5720_A0;
1764
1765         sc->bnx_asicrev = BGE_ASICREV(sc->bnx_chipid);
1766         sc->bnx_chiprev = BGE_CHIPREV(sc->bnx_chipid);
1767
1768         switch (sc->bnx_asicrev) {
1769         case BGE_ASICREV_BCM5717:
1770         case BGE_ASICREV_BCM5719:
1771         case BGE_ASICREV_BCM5720:
1772                 sc->bnx_flags |= BNX_FLAG_5717_PLUS | BNX_FLAG_57765_PLUS;
1773                 break;
1774
1775         case BGE_ASICREV_BCM5762:
1776                 sc->bnx_flags |= BNX_FLAG_57765_PLUS;
1777                 break;
1778
1779         case BGE_ASICREV_BCM57765:
1780         case BGE_ASICREV_BCM57766:
1781                 sc->bnx_flags |= BNX_FLAG_57765_FAMILY | BNX_FLAG_57765_PLUS;
1782                 break;
1783         }
1784
1785         sc->bnx_flags |= BNX_FLAG_TSO;
1786         if (sc->bnx_asicrev == BGE_ASICREV_BCM5719 &&
1787             sc->bnx_chipid == BGE_CHIPID_BCM5719_A0)
1788                 sc->bnx_flags &= ~BNX_FLAG_TSO;
1789
1790         if (sc->bnx_asicrev == BGE_ASICREV_BCM5717 ||
1791             BNX_IS_57765_FAMILY(sc)) {
1792                 /*
1793                  * All BCM57785 and BCM5718 families chips have a bug that
1794                  * under certain situation interrupt will not be enabled
1795                  * even if status tag is written to BGE_MBX_IRQ0_LO mailbox.
1796                  *
1797                  * While BCM5719 and BCM5720 have a hardware workaround
1798                  * which could fix the above bug.
1799                  * See the comment near BGE_PCIDMARWCTL_TAGGED_STATUS_WA in
1800                  * bnx_chipinit().
1801                  *
1802                  * For the rest of the chips in these two families, we will
1803                  * have to poll the status block at high rate (10ms currently)
1804                  * to check whether the interrupt is hosed or not.
1805                  * See bnx_intr_check() for details.
1806                  */
1807                 sc->bnx_flags |= BNX_FLAG_STATUSTAG_BUG;
1808         }
1809
1810         sc->bnx_pciecap = pci_get_pciecap_ptr(sc->bnx_dev);
1811         if (sc->bnx_asicrev == BGE_ASICREV_BCM5719 ||
1812             sc->bnx_asicrev == BGE_ASICREV_BCM5720)
1813                 pcie_set_max_readrq(dev, PCIEM_DEVCTL_MAX_READRQ_2048);
1814         else
1815                 pcie_set_max_readrq(dev, PCIEM_DEVCTL_MAX_READRQ_4096);
1816         device_printf(dev, "CHIP ID 0x%08x; "
1817                       "ASIC REV 0x%02x; CHIP REV 0x%02x\n",
1818                       sc->bnx_chipid, sc->bnx_asicrev, sc->bnx_chiprev);
1819
1820         /*
1821          * Set various PHY quirk flags.
1822          */
1823
1824         capmask = MII_CAPMASK_DEFAULT;
1825         if (product == PCI_PRODUCT_BROADCOM_BCM57791 ||
1826             product == PCI_PRODUCT_BROADCOM_BCM57795) {
1827                 /* 10/100 only */
1828                 capmask &= ~BMSR_EXTSTAT;
1829         }
1830
1831         mii_priv |= BRGPHY_FLAG_WIRESPEED;
1832         if (sc->bnx_chipid == BGE_CHIPID_BCM5762_A0)
1833                 mii_priv |= BRGPHY_FLAG_5762_A0;
1834
1835         /* Initialize if_name earlier, so if_printf could be used */
1836         ifp = &sc->arpcom.ac_if;
1837         if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1838
1839         /* Try to reset the chip. */
1840         bnx_reset(sc);
1841
1842         if (bnx_chipinit(sc)) {
1843                 device_printf(dev, "chip initialization failed\n");
1844                 error = ENXIO;
1845                 goto fail;
1846         }
1847
1848         /*
1849          * Get station address
1850          */
1851         error = bnx_get_eaddr(sc, ether_addr);
1852         if (error) {
1853                 device_printf(dev, "failed to read station address\n");
1854                 goto fail;
1855         }
1856
1857         /* XXX */
1858         sc->bnx_tx_ringcnt = 1;
1859
1860         error = bnx_dma_alloc(sc);
1861         if (error)
1862                 goto fail;
1863
1864         /*
1865          * Allocate interrupt
1866          */
1867         sc->bnx_irq_type = pci_alloc_1intr(dev, bnx_msi_enable, &sc->bnx_irq_rid,
1868             &intr_flags);
1869
1870         sc->bnx_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->bnx_irq_rid,
1871             intr_flags);
1872         if (sc->bnx_irq == NULL) {
1873                 device_printf(dev, "couldn't map interrupt\n");
1874                 error = ENXIO;
1875                 goto fail;
1876         }
1877
1878         if (sc->bnx_irq_type == PCI_INTR_TYPE_MSI) {
1879                 sc->bnx_flags |= BNX_FLAG_ONESHOT_MSI;
1880                 bnx_enable_msi(sc);
1881         }
1882
1883         /* Set default tuneable values. */
1884         sc->bnx_rx_coal_ticks = BNX_RX_COAL_TICKS_DEF;
1885         sc->bnx_tx_coal_ticks = BNX_TX_COAL_TICKS_DEF;
1886         sc->bnx_rx_coal_bds = BNX_RX_COAL_BDS_DEF;
1887         sc->bnx_tx_coal_bds = BNX_TX_COAL_BDS_DEF;
1888         sc->bnx_rx_coal_bds_int = BNX_RX_COAL_BDS_INT_DEF;
1889         sc->bnx_tx_coal_bds_int = BNX_TX_COAL_BDS_INT_DEF;
1890
1891         /* Set up ifnet structure */
1892         ifp->if_softc = sc;
1893         ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1894         ifp->if_ioctl = bnx_ioctl;
1895         ifp->if_start = bnx_start;
1896 #ifdef IFPOLL_ENABLE
1897         ifp->if_npoll = bnx_npoll;
1898 #endif
1899         ifp->if_watchdog = bnx_watchdog;
1900         ifp->if_init = bnx_init;
1901         ifp->if_mtu = ETHERMTU;
1902         ifp->if_capabilities = IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU;
1903         ifq_set_maxlen(&ifp->if_snd, BGE_TX_RING_CNT - 1);
1904         ifq_set_ready(&ifp->if_snd);
1905
1906         ifp->if_capabilities |= IFCAP_HWCSUM;
1907         ifp->if_hwassist = BNX_CSUM_FEATURES;
1908         if (sc->bnx_flags & BNX_FLAG_TSO) {
1909                 ifp->if_capabilities |= IFCAP_TSO;
1910                 ifp->if_hwassist |= CSUM_TSO;
1911         }
1912         ifp->if_capenable = ifp->if_capabilities;
1913
1914         /*
1915          * Figure out what sort of media we have by checking the
1916          * hardware config word in the first 32k of NIC internal memory,
1917          * or fall back to examining the EEPROM if necessary.
1918          * Note: on some BCM5700 cards, this value appears to be unset.
1919          * If that's the case, we have to rely on identifying the NIC
1920          * by its PCI subsystem ID, as we do below for the SysKonnect
1921          * SK-9D41.
1922          */
1923         if (bnx_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_SIG) == BGE_MAGIC_NUMBER) {
1924                 hwcfg = bnx_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_NICCFG);
1925         } else {
1926                 if (bnx_read_eeprom(sc, (caddr_t)&hwcfg, BGE_EE_HWCFG_OFFSET,
1927                                     sizeof(hwcfg))) {
1928                         device_printf(dev, "failed to read EEPROM\n");
1929                         error = ENXIO;
1930                         goto fail;
1931                 }
1932                 hwcfg = ntohl(hwcfg);
1933         }
1934
1935         /* The SysKonnect SK-9D41 is a 1000baseSX card. */
1936         if (pci_get_subvendor(dev) == PCI_PRODUCT_SCHNEIDERKOCH_SK_9D41 ||
1937             (hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER)
1938                 sc->bnx_flags |= BNX_FLAG_TBI;
1939
1940         /* Setup MI MODE */
1941         if (sc->bnx_flags & BNX_FLAG_CPMU)
1942                 sc->bnx_mi_mode = BGE_MIMODE_500KHZ_CONST;
1943         else
1944                 sc->bnx_mi_mode = BGE_MIMODE_BASE;
1945
1946         /* Setup link status update stuffs */
1947         if (sc->bnx_flags & BNX_FLAG_TBI) {
1948                 sc->bnx_link_upd = bnx_tbi_link_upd;
1949                 sc->bnx_link_chg = BGE_MACSTAT_LINK_CHANGED;
1950         } else if (sc->bnx_mi_mode & BGE_MIMODE_AUTOPOLL) {
1951                 sc->bnx_link_upd = bnx_autopoll_link_upd;
1952                 sc->bnx_link_chg = BGE_MACSTAT_LINK_CHANGED;
1953         } else {
1954                 sc->bnx_link_upd = bnx_copper_link_upd;
1955                 sc->bnx_link_chg = BGE_MACSTAT_LINK_CHANGED;
1956         }
1957
1958         /* Set default PHY address */
1959         sc->bnx_phyno = 1;
1960
1961         /*
1962          * PHY address mapping for various devices.
1963          *
1964          *          | F0 Cu | F0 Sr | F1 Cu | F1 Sr |
1965          * ---------+-------+-------+-------+-------+
1966          * BCM57XX  |   1   |   X   |   X   |   X   |
1967          * BCM5704  |   1   |   X   |   1   |   X   |
1968          * BCM5717  |   1   |   8   |   2   |   9   |
1969          * BCM5719  |   1   |   8   |   2   |   9   |
1970          * BCM5720  |   1   |   8   |   2   |   9   |
1971          *
1972          * Other addresses may respond but they are not
1973          * IEEE compliant PHYs and should be ignored.
1974          */
1975         if (BNX_IS_5717_PLUS(sc)) {
1976                 int f;
1977
1978                 f = pci_get_function(dev);
1979                 if (sc->bnx_chipid == BGE_CHIPID_BCM5717_A0) {
1980                         if (CSR_READ_4(sc, BGE_SGDIG_STS) &
1981                             BGE_SGDIGSTS_IS_SERDES)
1982                                 sc->bnx_phyno = f + 8;
1983                         else
1984                                 sc->bnx_phyno = f + 1;
1985                 } else {
1986                         if (CSR_READ_4(sc, BGE_CPMU_PHY_STRAP) &
1987                             BGE_CPMU_PHY_STRAP_IS_SERDES)
1988                                 sc->bnx_phyno = f + 8;
1989                         else
1990                                 sc->bnx_phyno = f + 1;
1991                 }
1992         }
1993
1994         if (sc->bnx_flags & BNX_FLAG_TBI) {
1995                 ifmedia_init(&sc->bnx_ifmedia, IFM_IMASK,
1996                     bnx_ifmedia_upd, bnx_ifmedia_sts);
1997                 ifmedia_add(&sc->bnx_ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL);
1998                 ifmedia_add(&sc->bnx_ifmedia,
1999                     IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL);
2000                 ifmedia_add(&sc->bnx_ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL);
2001                 ifmedia_set(&sc->bnx_ifmedia, IFM_ETHER|IFM_AUTO);
2002                 sc->bnx_ifmedia.ifm_media = sc->bnx_ifmedia.ifm_cur->ifm_media;
2003         } else {
2004                 struct mii_probe_args mii_args;
2005
2006                 mii_probe_args_init(&mii_args, bnx_ifmedia_upd, bnx_ifmedia_sts);
2007                 mii_args.mii_probemask = 1 << sc->bnx_phyno;
2008                 mii_args.mii_capmask = capmask;
2009                 mii_args.mii_privtag = MII_PRIVTAG_BRGPHY;
2010                 mii_args.mii_priv = mii_priv;
2011
2012                 error = mii_probe(dev, &sc->bnx_miibus, &mii_args);
2013                 if (error) {
2014                         device_printf(dev, "MII without any PHY!\n");
2015                         goto fail;
2016                 }
2017         }
2018
2019         /*
2020          * Create sysctl nodes.
2021          */
2022         sysctl_ctx_init(&sc->bnx_sysctl_ctx);
2023         sc->bnx_sysctl_tree = SYSCTL_ADD_NODE(&sc->bnx_sysctl_ctx,
2024                                               SYSCTL_STATIC_CHILDREN(_hw),
2025                                               OID_AUTO,
2026                                               device_get_nameunit(dev),
2027                                               CTLFLAG_RD, 0, "");
2028         if (sc->bnx_sysctl_tree == NULL) {
2029                 device_printf(dev, "can't add sysctl node\n");
2030                 error = ENXIO;
2031                 goto fail;
2032         }
2033
2034         SYSCTL_ADD_PROC(&sc->bnx_sysctl_ctx,
2035                         SYSCTL_CHILDREN(sc->bnx_sysctl_tree),
2036                         OID_AUTO, "rx_coal_ticks",
2037                         CTLTYPE_INT | CTLFLAG_RW,
2038                         sc, 0, bnx_sysctl_rx_coal_ticks, "I",
2039                         "Receive coalescing ticks (usec).");
2040         SYSCTL_ADD_PROC(&sc->bnx_sysctl_ctx,
2041                         SYSCTL_CHILDREN(sc->bnx_sysctl_tree),
2042                         OID_AUTO, "tx_coal_ticks",
2043                         CTLTYPE_INT | CTLFLAG_RW,
2044                         sc, 0, bnx_sysctl_tx_coal_ticks, "I",
2045                         "Transmit coalescing ticks (usec).");
2046         SYSCTL_ADD_PROC(&sc->bnx_sysctl_ctx,
2047                         SYSCTL_CHILDREN(sc->bnx_sysctl_tree),
2048                         OID_AUTO, "rx_coal_bds",
2049                         CTLTYPE_INT | CTLFLAG_RW,
2050                         sc, 0, bnx_sysctl_rx_coal_bds, "I",
2051                         "Receive max coalesced BD count.");
2052         SYSCTL_ADD_PROC(&sc->bnx_sysctl_ctx,
2053                         SYSCTL_CHILDREN(sc->bnx_sysctl_tree),
2054                         OID_AUTO, "tx_coal_bds",
2055                         CTLTYPE_INT | CTLFLAG_RW,
2056                         sc, 0, bnx_sysctl_tx_coal_bds, "I",
2057                         "Transmit max coalesced BD count.");
2058         /*
2059          * A common design characteristic for many Broadcom
2060          * client controllers is that they only support a
2061          * single outstanding DMA read operation on the PCIe
2062          * bus. This means that it will take twice as long to
2063          * fetch a TX frame that is split into header and
2064          * payload buffers as it does to fetch a single,
2065          * contiguous TX frame (2 reads vs. 1 read). For these
2066          * controllers, coalescing buffers to reduce the number
2067          * of memory reads is effective way to get maximum
2068          * performance(about 940Mbps).  Without collapsing TX
2069          * buffers the maximum TCP bulk transfer performance
2070          * is about 850Mbps. However forcing coalescing mbufs
2071          * consumes a lot of CPU cycles, so leave it off by
2072          * default.
2073          */
2074         SYSCTL_ADD_INT(&sc->bnx_sysctl_ctx,
2075             SYSCTL_CHILDREN(sc->bnx_sysctl_tree), OID_AUTO,
2076             "force_defrag", CTLFLAG_RW, &sc->bnx_force_defrag, 0,
2077             "Force defragment on TX path");
2078
2079         SYSCTL_ADD_INT(&sc->bnx_sysctl_ctx,
2080             SYSCTL_CHILDREN(sc->bnx_sysctl_tree), OID_AUTO,
2081             "tx_wreg", CTLFLAG_RW, &sc->bnx_tx_ring[0].bnx_tx_wreg, 0,
2082             "# of segments before writing to hardware register");
2083
2084         SYSCTL_ADD_PROC(&sc->bnx_sysctl_ctx,
2085             SYSCTL_CHILDREN(sc->bnx_sysctl_tree), OID_AUTO,
2086             "rx_coal_bds_int", CTLTYPE_INT | CTLFLAG_RW,
2087             sc, 0, bnx_sysctl_rx_coal_bds_int, "I",
2088             "Receive max coalesced BD count during interrupt.");
2089         SYSCTL_ADD_PROC(&sc->bnx_sysctl_ctx,
2090             SYSCTL_CHILDREN(sc->bnx_sysctl_tree), OID_AUTO,
2091             "tx_coal_bds_int", CTLTYPE_INT | CTLFLAG_RW,
2092             sc, 0, bnx_sysctl_tx_coal_bds_int, "I",
2093             "Transmit max coalesced BD count during interrupt.");
2094
2095 #ifdef BNX_TSO_DEBUG
2096         for (i = 0; i < BNX_TSO_NSTATS; ++i) {
2097                 ksnprintf(desc, sizeof(desc), "tso%d", i + 1);
2098                 SYSCTL_ADD_ULONG(&sc->bnx_sysctl_ctx,
2099                     SYSCTL_CHILDREN(sc->bnx_sysctl_tree), OID_AUTO,
2100                     desc, CTLFLAG_RW, &sc->bnx_tsosegs[i], "");
2101         }
2102 #endif
2103
2104         /*
2105          * Call MI attach routine.
2106          */
2107         ether_ifattach(ifp, ether_addr, NULL);
2108
2109         ifq_set_cpuid(&ifp->if_snd, sc->bnx_intr_cpuid);
2110
2111 #ifdef IFPOLL_ENABLE
2112         ifpoll_compat_setup(&sc->bnx_npoll,
2113             &sc->bnx_sysctl_ctx, sc->bnx_sysctl_tree,
2114             device_get_unit(dev), ifp->if_serializer);
2115 #endif
2116
2117         if (sc->bnx_irq_type == PCI_INTR_TYPE_MSI) {
2118                 if (sc->bnx_flags & BNX_FLAG_ONESHOT_MSI) {
2119                         intr_func = bnx_msi_oneshot;
2120                         if (bootverbose)
2121                                 device_printf(dev, "oneshot MSI\n");
2122                 } else {
2123                         intr_func = bnx_msi;
2124                 }
2125         } else {
2126                 intr_func = bnx_intr_legacy;
2127         }
2128         error = bus_setup_intr(dev, sc->bnx_irq, INTR_MPSAFE, intr_func, sc,
2129             &sc->bnx_intrhand, ifp->if_serializer);
2130         if (error) {
2131                 ether_ifdetach(ifp);
2132                 device_printf(dev, "couldn't set up irq\n");
2133                 goto fail;
2134         }
2135
2136         sc->bnx_intr_cpuid = rman_get_cpuid(sc->bnx_irq);
2137         sc->bnx_stat_cpuid = sc->bnx_intr_cpuid;
2138
2139         return(0);
2140 fail:
2141         bnx_detach(dev);
2142         return(error);
2143 }
2144
2145 static int
2146 bnx_detach(device_t dev)
2147 {
2148         struct bnx_softc *sc = device_get_softc(dev);
2149
2150         if (device_is_attached(dev)) {
2151                 struct ifnet *ifp = &sc->arpcom.ac_if;
2152
2153                 lwkt_serialize_enter(ifp->if_serializer);
2154                 bnx_stop(sc);
2155                 bnx_reset(sc);
2156                 bus_teardown_intr(dev, sc->bnx_irq, sc->bnx_intrhand);
2157                 lwkt_serialize_exit(ifp->if_serializer);
2158
2159                 ether_ifdetach(ifp);
2160         }
2161
2162         if (sc->bnx_flags & BNX_FLAG_TBI)
2163                 ifmedia_removeall(&sc->bnx_ifmedia);
2164         if (sc->bnx_miibus)
2165                 device_delete_child(dev, sc->bnx_miibus);
2166         bus_generic_detach(dev);
2167
2168         if (sc->bnx_irq != NULL) {
2169                 bus_release_resource(dev, SYS_RES_IRQ, sc->bnx_irq_rid,
2170                     sc->bnx_irq);
2171         }
2172         if (sc->bnx_irq_type == PCI_INTR_TYPE_MSI)
2173                 pci_release_msi(dev);
2174
2175         if (sc->bnx_res != NULL) {
2176                 bus_release_resource(dev, SYS_RES_MEMORY,
2177                     BGE_PCI_BAR0, sc->bnx_res);
2178         }
2179
2180         if (sc->bnx_sysctl_tree != NULL)
2181                 sysctl_ctx_free(&sc->bnx_sysctl_ctx);
2182
2183         bnx_dma_free(sc);
2184
2185         return 0;
2186 }
2187
2188 static void
2189 bnx_reset(struct bnx_softc *sc)
2190 {
2191         device_t dev;
2192         uint32_t cachesize, command, pcistate, reset;
2193         void (*write_op)(struct bnx_softc *, uint32_t, uint32_t);
2194         int i, val = 0;
2195         uint16_t devctl;
2196
2197         dev = sc->bnx_dev;
2198
2199         write_op = bnx_writemem_direct;
2200
2201         /* Save some important PCI state. */
2202         cachesize = pci_read_config(dev, BGE_PCI_CACHESZ, 4);
2203         command = pci_read_config(dev, BGE_PCI_CMD, 4);
2204         pcistate = pci_read_config(dev, BGE_PCI_PCISTATE, 4);
2205
2206         pci_write_config(dev, BGE_PCI_MISC_CTL,
2207             BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR|
2208             BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_PCISTATE_RW|
2209             BGE_PCIMISCCTL_TAGGED_STATUS, 4);
2210
2211         /* Disable fastboot on controllers that support it. */
2212         if (bootverbose)
2213                 if_printf(&sc->arpcom.ac_if, "Disabling fastboot\n");
2214         CSR_WRITE_4(sc, BGE_FASTBOOT_PC, 0x0);
2215
2216         /*
2217          * Write the magic number to SRAM at offset 0xB50.
2218          * When firmware finishes its initialization it will
2219          * write ~BGE_MAGIC_NUMBER to the same location.
2220          */
2221         bnx_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER);
2222
2223         reset = BGE_MISCCFG_RESET_CORE_CLOCKS|(65<<1);
2224
2225         /* XXX: Broadcom Linux driver. */
2226         /* Force PCI-E 1.0a mode */
2227         if (!BNX_IS_57765_PLUS(sc) &&
2228             CSR_READ_4(sc, BGE_PCIE_PHY_TSTCTL) ==
2229             (BGE_PCIE_PHY_TSTCTL_PSCRAM |
2230              BGE_PCIE_PHY_TSTCTL_PCIE10)) {
2231                 CSR_WRITE_4(sc, BGE_PCIE_PHY_TSTCTL,
2232                     BGE_PCIE_PHY_TSTCTL_PSCRAM);
2233         }
2234         if (sc->bnx_chipid != BGE_CHIPID_BCM5750_A0) {
2235                 /* Prevent PCIE link training during global reset */
2236                 CSR_WRITE_4(sc, BGE_MISC_CFG, (1<<29));
2237                 reset |= (1<<29);
2238         }
2239
2240         /* 
2241          * Set GPHY Power Down Override to leave GPHY
2242          * powered up in D0 uninitialized.
2243          */
2244         if ((sc->bnx_flags & BNX_FLAG_CPMU) == 0)
2245                 reset |= BGE_MISCCFG_GPHY_PD_OVERRIDE;
2246
2247         /* Issue global reset */
2248         write_op(sc, BGE_MISC_CFG, reset);
2249
2250         DELAY(1000);
2251
2252         /* XXX: Broadcom Linux driver. */
2253         if (sc->bnx_chipid == BGE_CHIPID_BCM5750_A0) {
2254                 uint32_t v;
2255
2256                 DELAY(500000); /* wait for link training to complete */
2257                 v = pci_read_config(dev, 0xc4, 4);
2258                 pci_write_config(dev, 0xc4, v | (1<<15), 4);
2259         }
2260
2261         devctl = pci_read_config(dev, sc->bnx_pciecap + PCIER_DEVCTRL, 2);
2262
2263         /* Disable no snoop and disable relaxed ordering. */
2264         devctl &= ~(PCIEM_DEVCTL_RELAX_ORDER | PCIEM_DEVCTL_NOSNOOP);
2265
2266         /* Old PCI-E chips only support 128 bytes Max PayLoad Size. */
2267         if ((sc->bnx_flags & BNX_FLAG_CPMU) == 0) {
2268                 devctl &= ~PCIEM_DEVCTL_MAX_PAYLOAD_MASK;
2269                 devctl |= PCIEM_DEVCTL_MAX_PAYLOAD_128;
2270         }
2271
2272         pci_write_config(dev, sc->bnx_pciecap + PCIER_DEVCTRL,
2273             devctl, 2);
2274
2275         /* Clear error status. */
2276         pci_write_config(dev, sc->bnx_pciecap + PCIER_DEVSTS,
2277             PCIEM_DEVSTS_CORR_ERR |
2278             PCIEM_DEVSTS_NFATAL_ERR |
2279             PCIEM_DEVSTS_FATAL_ERR |
2280             PCIEM_DEVSTS_UNSUPP_REQ, 2);
2281
2282         /* Reset some of the PCI state that got zapped by reset */
2283         pci_write_config(dev, BGE_PCI_MISC_CTL,
2284             BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR|
2285             BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_PCISTATE_RW|
2286             BGE_PCIMISCCTL_TAGGED_STATUS, 4);
2287         pci_write_config(dev, BGE_PCI_CACHESZ, cachesize, 4);
2288         pci_write_config(dev, BGE_PCI_CMD, command, 4);
2289         write_op(sc, BGE_MISC_CFG, (65 << 1));
2290
2291         /* Enable memory arbiter */
2292         CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
2293
2294         /*
2295          * Poll until we see the 1's complement of the magic number.
2296          * This indicates that the firmware initialization is complete.
2297          */
2298         for (i = 0; i < BNX_FIRMWARE_TIMEOUT; i++) {
2299                 val = bnx_readmem_ind(sc, BGE_SOFTWARE_GENCOMM);
2300                 if (val == ~BGE_MAGIC_NUMBER)
2301                         break;
2302                 DELAY(10);
2303         }
2304         if (i == BNX_FIRMWARE_TIMEOUT) {
2305                 if_printf(&sc->arpcom.ac_if, "firmware handshake "
2306                           "timed out, found 0x%08x\n", val);
2307         }
2308
2309         /* BCM57765 A0 needs additional time before accessing. */
2310         if (sc->bnx_chipid == BGE_CHIPID_BCM57765_A0)
2311                 DELAY(10 * 1000);
2312
2313         /*
2314          * XXX Wait for the value of the PCISTATE register to
2315          * return to its original pre-reset state. This is a
2316          * fairly good indicator of reset completion. If we don't
2317          * wait for the reset to fully complete, trying to read
2318          * from the device's non-PCI registers may yield garbage
2319          * results.
2320          */
2321         for (i = 0; i < BNX_TIMEOUT; i++) {
2322                 if (pci_read_config(dev, BGE_PCI_PCISTATE, 4) == pcistate)
2323                         break;
2324                 DELAY(10);
2325         }
2326
2327         /* Fix up byte swapping */
2328         CSR_WRITE_4(sc, BGE_MODE_CTL, bnx_dma_swap_options(sc));
2329
2330         CSR_WRITE_4(sc, BGE_MAC_MODE, 0);
2331
2332         /*
2333          * The 5704 in TBI mode apparently needs some special
2334          * adjustment to insure the SERDES drive level is set
2335          * to 1.2V.
2336          */
2337         if (sc->bnx_asicrev == BGE_ASICREV_BCM5704 &&
2338             (sc->bnx_flags & BNX_FLAG_TBI)) {
2339                 uint32_t serdescfg;
2340
2341                 serdescfg = CSR_READ_4(sc, BGE_SERDES_CFG);
2342                 serdescfg = (serdescfg & ~0xFFF) | 0x880;
2343                 CSR_WRITE_4(sc, BGE_SERDES_CFG, serdescfg);
2344         }
2345
2346         CSR_WRITE_4(sc, BGE_MI_MODE,
2347             sc->bnx_mi_mode & ~BGE_MIMODE_AUTOPOLL);
2348         DELAY(80);
2349
2350         /* XXX: Broadcom Linux driver. */
2351         if (!BNX_IS_57765_PLUS(sc)) {
2352                 uint32_t v;
2353
2354                 /* Enable Data FIFO protection. */
2355                 v = CSR_READ_4(sc, BGE_PCIE_TLDLPL_PORT);
2356                 CSR_WRITE_4(sc, BGE_PCIE_TLDLPL_PORT, v | (1 << 25));
2357         }
2358
2359         DELAY(10000);
2360
2361         if (sc->bnx_asicrev == BGE_ASICREV_BCM5720) {
2362                 BNX_CLRBIT(sc, BGE_CPMU_CLCK_ORIDE,
2363                     CPMU_CLCK_ORIDE_MAC_ORIDE_EN);
2364         }
2365 }
2366
2367 /*
2368  * Frame reception handling. This is called if there's a frame
2369  * on the receive return list.
2370  *
2371  * Note: we have to be able to handle two possibilities here:
2372  * 1) the frame is from the jumbo recieve ring
2373  * 2) the frame is from the standard receive ring
2374  */
2375
2376 static void
2377 bnx_rxeof(struct bnx_softc *sc, uint16_t rx_prod, int count)
2378 {
2379         struct ifnet *ifp;
2380         int stdcnt = 0, jumbocnt = 0;
2381
2382         ifp = &sc->arpcom.ac_if;
2383
2384         while (sc->bnx_rx_saved_considx != rx_prod && count != 0) {
2385                 struct bge_rx_bd        *cur_rx;
2386                 uint32_t                rxidx;
2387                 struct mbuf             *m = NULL;
2388                 uint16_t                vlan_tag = 0;
2389                 int                     have_tag = 0;
2390
2391                 --count;
2392
2393                 cur_rx =
2394             &sc->bnx_ldata.bnx_rx_return_ring[sc->bnx_rx_saved_considx];
2395
2396                 rxidx = cur_rx->bge_idx;
2397                 BNX_INC(sc->bnx_rx_saved_considx, BNX_RETURN_RING_CNT);
2398
2399                 if (cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) {
2400                         have_tag = 1;
2401                         vlan_tag = cur_rx->bge_vlan_tag;
2402                 }
2403
2404                 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) {
2405                         BNX_INC(sc->bnx_jumbo, BGE_JUMBO_RX_RING_CNT);
2406                         jumbocnt++;
2407
2408                         if (rxidx != sc->bnx_jumbo) {
2409                                 IFNET_STAT_INC(ifp, ierrors, 1);
2410                                 if_printf(ifp, "sw jumbo index(%d) "
2411                                     "and hw jumbo index(%d) mismatch, drop!\n",
2412                                     sc->bnx_jumbo, rxidx);
2413                                 bnx_setup_rxdesc_jumbo(sc, rxidx);
2414                                 continue;
2415                         }
2416
2417                         m = sc->bnx_cdata.bnx_rx_jumbo_chain[rxidx].bnx_mbuf;
2418                         if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
2419                                 IFNET_STAT_INC(ifp, ierrors, 1);
2420                                 bnx_setup_rxdesc_jumbo(sc, sc->bnx_jumbo);
2421                                 continue;
2422                         }
2423                         if (bnx_newbuf_jumbo(sc, sc->bnx_jumbo, 0)) {
2424                                 IFNET_STAT_INC(ifp, ierrors, 1);
2425                                 bnx_setup_rxdesc_jumbo(sc, sc->bnx_jumbo);
2426                                 continue;
2427                         }
2428                 } else {
2429                         BNX_INC(sc->bnx_std, BGE_STD_RX_RING_CNT);
2430                         stdcnt++;
2431
2432                         if (rxidx != sc->bnx_std) {
2433                                 IFNET_STAT_INC(ifp, ierrors, 1);
2434                                 if_printf(ifp, "sw std index(%d) "
2435                                     "and hw std index(%d) mismatch, drop!\n",
2436                                     sc->bnx_std, rxidx);
2437                                 bnx_setup_rxdesc_std(sc, rxidx);
2438                                 continue;
2439                         }
2440
2441                         m = sc->bnx_cdata.bnx_rx_std_chain[rxidx].bnx_mbuf;
2442                         if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
2443                                 IFNET_STAT_INC(ifp, ierrors, 1);
2444                                 bnx_setup_rxdesc_std(sc, sc->bnx_std);
2445                                 continue;
2446                         }
2447                         if (bnx_newbuf_std(sc, sc->bnx_std, 0)) {
2448                                 IFNET_STAT_INC(ifp, ierrors, 1);
2449                                 bnx_setup_rxdesc_std(sc, sc->bnx_std);
2450                                 continue;
2451                         }
2452                 }
2453
2454                 IFNET_STAT_INC(ifp, ipackets, 1);
2455                 m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN;
2456                 m->m_pkthdr.rcvif = ifp;
2457
2458                 if ((ifp->if_capenable & IFCAP_RXCSUM) &&
2459                     (cur_rx->bge_flags & BGE_RXBDFLAG_IPV6) == 0) {
2460                         if (cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) {
2461                                 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
2462                                 if ((cur_rx->bge_error_flag &
2463                                     BGE_RXERRFLAG_IP_CSUM_NOK) == 0)
2464                                         m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
2465                         }
2466                         if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM) {
2467                                 m->m_pkthdr.csum_data =
2468                                     cur_rx->bge_tcp_udp_csum;
2469                                 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID |
2470                                     CSUM_PSEUDO_HDR;
2471                         }
2472                 }
2473
2474                 /*
2475                  * If we received a packet with a vlan tag, pass it
2476                  * to vlan_input() instead of ether_input().
2477                  */
2478                 if (have_tag) {
2479                         m->m_flags |= M_VLANTAG;
2480                         m->m_pkthdr.ether_vlantag = vlan_tag;
2481                 }
2482                 ifp->if_input(ifp, m);
2483         }
2484
2485         bnx_writembx(sc, BGE_MBX_RX_CONS0_LO, sc->bnx_rx_saved_considx);
2486         if (stdcnt)
2487                 bnx_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bnx_std);
2488         if (jumbocnt)
2489                 bnx_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bnx_jumbo);
2490 }
2491
2492 static void
2493 bnx_txeof(struct bnx_tx_ring *txr, uint16_t tx_cons)
2494 {
2495         struct ifnet *ifp = &txr->bnx_sc->arpcom.ac_if;
2496
2497         /*
2498          * Go through our tx ring and free mbufs for those
2499          * frames that have been sent.
2500          */
2501         while (txr->bnx_tx_saved_considx != tx_cons) {
2502                 uint32_t idx = 0;
2503
2504                 idx = txr->bnx_tx_saved_considx;
2505                 if (txr->bnx_tx_chain[idx] != NULL) {
2506                         IFNET_STAT_INC(ifp, opackets, 1);
2507                         bus_dmamap_unload(txr->bnx_tx_mtag,
2508                             txr->bnx_tx_dmamap[idx]);
2509                         m_freem(txr->bnx_tx_chain[idx]);
2510                         txr->bnx_tx_chain[idx] = NULL;
2511                 }
2512                 txr->bnx_txcnt--;
2513                 BNX_INC(txr->bnx_tx_saved_considx, BGE_TX_RING_CNT);
2514         }
2515
2516         if ((BGE_TX_RING_CNT - txr->bnx_txcnt) >=
2517             (BNX_NSEG_RSVD + BNX_NSEG_SPARE))
2518                 ifq_clr_oactive(&ifp->if_snd);
2519
2520         if (txr->bnx_txcnt == 0)
2521                 ifp->if_timer = 0;
2522
2523         if (!ifq_is_empty(&ifp->if_snd))
2524                 if_devstart(ifp);
2525 }
2526
2527 #ifdef IFPOLL_ENABLE
2528
2529 static void
2530 bnx_npoll(struct ifnet *ifp, struct ifpoll_info *info)
2531 {
2532         struct bnx_softc *sc = ifp->if_softc;
2533
2534         ASSERT_SERIALIZED(ifp->if_serializer);
2535
2536         if (info != NULL) {
2537                 int cpuid = sc->bnx_npoll.ifpc_cpuid;
2538
2539                 info->ifpi_rx[cpuid].poll_func = bnx_npoll_compat;
2540                 info->ifpi_rx[cpuid].arg = NULL;
2541                 info->ifpi_rx[cpuid].serializer = ifp->if_serializer;
2542
2543                 if (ifp->if_flags & IFF_RUNNING)
2544                         bnx_disable_intr(sc);
2545                 ifq_set_cpuid(&ifp->if_snd, cpuid);
2546         } else {
2547                 if (ifp->if_flags & IFF_RUNNING)
2548                         bnx_enable_intr(sc);
2549                 ifq_set_cpuid(&ifp->if_snd, sc->bnx_intr_cpuid);
2550         }
2551 }
2552
2553 static void
2554 bnx_npoll_compat(struct ifnet *ifp, void *arg __unused, int cycle)
2555 {
2556         struct bnx_softc *sc = ifp->if_softc;
2557         struct bnx_tx_ring *txr = &sc->bnx_tx_ring[0]; /* XXX */
2558         struct bge_status_block *sblk = sc->bnx_ldata.bnx_status_block;
2559         uint16_t rx_prod, tx_cons;
2560
2561         ASSERT_SERIALIZED(ifp->if_serializer);
2562
2563         if (sc->bnx_npoll.ifpc_stcount-- == 0) {
2564                 sc->bnx_npoll.ifpc_stcount = sc->bnx_npoll.ifpc_stfrac;
2565                 /*
2566                  * Process link state changes.
2567                  */
2568                 bnx_link_poll(sc);
2569         }
2570
2571         sc->bnx_status_tag = sblk->bge_status_tag;
2572
2573         /*
2574          * Use a load fence to ensure that status_tag is saved
2575          * before rx_prod and tx_cons.
2576          */
2577         cpu_lfence();
2578
2579         rx_prod = sblk->bge_idx[0].bge_rx_prod_idx;
2580         tx_cons = sblk->bge_idx[0].bge_tx_cons_idx;
2581
2582         if (sc->bnx_rx_saved_considx != rx_prod)
2583                 bnx_rxeof(sc, rx_prod, cycle);
2584
2585         if (txr->bnx_tx_saved_considx != tx_cons)
2586                 bnx_txeof(txr, tx_cons);
2587
2588         if (sc->bnx_coal_chg)
2589                 bnx_coal_change(sc);
2590 }
2591
2592 #endif  /* IFPOLL_ENABLE */
2593
2594 static void
2595 bnx_intr_legacy(void *xsc)
2596 {
2597         struct bnx_softc *sc = xsc;
2598         struct bge_status_block *sblk = sc->bnx_ldata.bnx_status_block;
2599
2600         if (sc->bnx_status_tag == sblk->bge_status_tag) {
2601                 uint32_t val;
2602
2603                 val = pci_read_config(sc->bnx_dev, BGE_PCI_PCISTATE, 4);
2604                 if (val & BGE_PCISTAT_INTR_NOTACT)
2605                         return;
2606         }
2607
2608         /*
2609          * NOTE:
2610          * Interrupt will have to be disabled if tagged status
2611          * is used, else interrupt will always be asserted on
2612          * certain chips (at least on BCM5750 AX/BX).
2613          */
2614         bnx_writembx(sc, BGE_MBX_IRQ0_LO, 1);
2615
2616         bnx_intr(sc);
2617 }
2618
2619 static void
2620 bnx_msi(void *xsc)
2621 {
2622         struct bnx_softc *sc = xsc;
2623
2624         /* Disable interrupt first */
2625         bnx_writembx(sc, BGE_MBX_IRQ0_LO, 1);
2626         bnx_intr(sc);
2627 }
2628
2629 static void
2630 bnx_msi_oneshot(void *xsc)
2631 {
2632         bnx_intr(xsc);
2633 }
2634
2635 static void
2636 bnx_intr(struct bnx_softc *sc)
2637 {
2638         struct ifnet *ifp = &sc->arpcom.ac_if;
2639         struct bge_status_block *sblk = sc->bnx_ldata.bnx_status_block;
2640         uint16_t rx_prod, tx_cons;
2641         uint32_t status;
2642
2643         sc->bnx_status_tag = sblk->bge_status_tag;
2644         /*
2645          * Use a load fence to ensure that status_tag is saved 
2646          * before rx_prod, tx_cons and status.
2647          */
2648         cpu_lfence();
2649
2650         rx_prod = sblk->bge_idx[0].bge_rx_prod_idx;
2651         tx_cons = sblk->bge_idx[0].bge_tx_cons_idx;
2652         status = sblk->bge_status;
2653
2654         if ((status & BGE_STATFLAG_LINKSTATE_CHANGED) || sc->bnx_link_evt)
2655                 bnx_link_poll(sc);
2656
2657         if (ifp->if_flags & IFF_RUNNING) {
2658                 struct bnx_tx_ring *txr = &sc->bnx_tx_ring[0]; /* XXX */
2659
2660                 if (sc->bnx_rx_saved_considx != rx_prod)
2661                         bnx_rxeof(sc, rx_prod, -1);
2662
2663                 if (txr->bnx_tx_saved_considx != tx_cons)
2664                         bnx_txeof(txr, tx_cons);
2665         }
2666
2667         bnx_writembx(sc, BGE_MBX_IRQ0_LO, sc->bnx_status_tag << 24);
2668
2669         if (sc->bnx_coal_chg)
2670                 bnx_coal_change(sc);
2671 }
2672
2673 static void
2674 bnx_tick(void *xsc)
2675 {
2676         struct bnx_softc *sc = xsc;
2677         struct ifnet *ifp = &sc->arpcom.ac_if;
2678
2679         lwkt_serialize_enter(ifp->if_serializer);
2680
2681         KKASSERT(mycpuid == sc->bnx_stat_cpuid);
2682
2683         bnx_stats_update_regs(sc);
2684
2685         if (sc->bnx_flags & BNX_FLAG_TBI) {
2686                 /*
2687                  * Since in TBI mode auto-polling can't be used we should poll
2688                  * link status manually. Here we register pending link event
2689                  * and trigger interrupt.
2690                  */
2691                 sc->bnx_link_evt++;
2692                 BNX_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW);
2693         } else if (!sc->bnx_link) {
2694                 mii_tick(device_get_softc(sc->bnx_miibus));
2695         }
2696
2697         callout_reset(&sc->bnx_stat_timer, hz, bnx_tick, sc);
2698
2699         lwkt_serialize_exit(ifp->if_serializer);
2700 }
2701
2702 static void
2703 bnx_stats_update_regs(struct bnx_softc *sc)
2704 {
2705         struct ifnet *ifp = &sc->arpcom.ac_if;
2706         struct bge_mac_stats_regs stats;
2707         uint32_t *s;
2708         int i;
2709
2710         s = (uint32_t *)&stats;
2711         for (i = 0; i < sizeof(struct bge_mac_stats_regs); i += 4) {
2712                 *s = CSR_READ_4(sc, BGE_RX_STATS + i);
2713                 s++;
2714         }
2715
2716         IFNET_STAT_SET(ifp, collisions,
2717            (stats.dot3StatsSingleCollisionFrames +
2718            stats.dot3StatsMultipleCollisionFrames +
2719            stats.dot3StatsExcessiveCollisions +
2720            stats.dot3StatsLateCollisions));
2721 }
2722
2723 /*
2724  * Encapsulate an mbuf chain in the tx ring  by coupling the mbuf data
2725  * pointers to descriptors.
2726  */
2727 static int
2728 bnx_encap(struct bnx_tx_ring *txr, struct mbuf **m_head0, uint32_t *txidx,
2729     int *segs_used)
2730 {
2731         struct bge_tx_bd *d = NULL;
2732         uint16_t csum_flags = 0, vlan_tag = 0, mss = 0;
2733         bus_dma_segment_t segs[BNX_NSEG_NEW];
2734         bus_dmamap_t map;
2735         int error, maxsegs, nsegs, idx, i;
2736         struct mbuf *m_head = *m_head0, *m_new;
2737
2738         if (m_head->m_pkthdr.csum_flags & CSUM_TSO) {
2739 #ifdef BNX_TSO_DEBUG
2740                 int tso_nsegs;
2741 #endif
2742
2743                 error = bnx_setup_tso(txr, m_head0, &mss, &csum_flags);
2744                 if (error)
2745                         return error;
2746                 m_head = *m_head0;
2747
2748 #ifdef BNX_TSO_DEBUG
2749                 tso_nsegs = (m_head->m_pkthdr.len /
2750                     m_head->m_pkthdr.tso_segsz) - 1;
2751                 if (tso_nsegs > (BNX_TSO_NSTATS - 1))
2752                         tso_nsegs = BNX_TSO_NSTATS - 1;
2753                 else if (tso_nsegs < 0)
2754                         tso_nsegs = 0;
2755                 txr->sc->bnx_tsosegs[tso_nsegs]++;
2756 #endif
2757         } else if (m_head->m_pkthdr.csum_flags & BNX_CSUM_FEATURES) {
2758                 if (m_head->m_pkthdr.csum_flags & CSUM_IP)
2759                         csum_flags |= BGE_TXBDFLAG_IP_CSUM;
2760                 if (m_head->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP))
2761                         csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM;
2762                 if (m_head->m_flags & M_LASTFRAG)
2763                         csum_flags |= BGE_TXBDFLAG_IP_FRAG_END;
2764                 else if (m_head->m_flags & M_FRAG)
2765                         csum_flags |= BGE_TXBDFLAG_IP_FRAG;
2766         }
2767         if (m_head->m_flags & M_VLANTAG) {
2768                 csum_flags |= BGE_TXBDFLAG_VLAN_TAG;
2769                 vlan_tag = m_head->m_pkthdr.ether_vlantag;
2770         }
2771
2772         idx = *txidx;
2773         map = txr->bnx_tx_dmamap[idx];
2774
2775         maxsegs = (BGE_TX_RING_CNT - txr->bnx_txcnt) - BNX_NSEG_RSVD;
2776         KASSERT(maxsegs >= BNX_NSEG_SPARE,
2777                 ("not enough segments %d", maxsegs));
2778
2779         if (maxsegs > BNX_NSEG_NEW)
2780                 maxsegs = BNX_NSEG_NEW;
2781
2782         /*
2783          * Pad outbound frame to BGE_MIN_FRAMELEN for an unusual reason.
2784          * The bge hardware will pad out Tx runts to BGE_MIN_FRAMELEN,
2785          * but when such padded frames employ the bge IP/TCP checksum
2786          * offload, the hardware checksum assist gives incorrect results
2787          * (possibly from incorporating its own padding into the UDP/TCP
2788          * checksum; who knows).  If we pad such runts with zeros, the
2789          * onboard checksum comes out correct.
2790          */
2791         if ((csum_flags & BGE_TXBDFLAG_TCP_UDP_CSUM) &&
2792             m_head->m_pkthdr.len < BNX_MIN_FRAMELEN) {
2793                 error = m_devpad(m_head, BNX_MIN_FRAMELEN);
2794                 if (error)
2795                         goto back;
2796         }
2797
2798         if ((txr->bnx_tx_flags & BNX_TX_FLAG_SHORTDMA) &&
2799             m_head->m_next != NULL) {
2800                 m_new = bnx_defrag_shortdma(m_head);
2801                 if (m_new == NULL) {
2802                         error = ENOBUFS;
2803                         goto back;
2804                 }
2805                 *m_head0 = m_head = m_new;
2806         }
2807         if ((m_head->m_pkthdr.csum_flags & CSUM_TSO) == 0 &&
2808             txr->bnx_sc->bnx_force_defrag && m_head->m_next != NULL) {
2809                 /*
2810                  * Forcefully defragment mbuf chain to overcome hardware
2811                  * limitation which only support a single outstanding
2812                  * DMA read operation.  If it fails, keep moving on using
2813                  * the original mbuf chain.
2814                  */
2815                 m_new = m_defrag(m_head, MB_DONTWAIT);
2816                 if (m_new != NULL)
2817                         *m_head0 = m_head = m_new;
2818         }
2819
2820         error = bus_dmamap_load_mbuf_defrag(txr->bnx_tx_mtag, map,
2821             m_head0, segs, maxsegs, &nsegs, BUS_DMA_NOWAIT);
2822         if (error)
2823                 goto back;
2824         *segs_used += nsegs;
2825
2826         m_head = *m_head0;
2827         bus_dmamap_sync(txr->bnx_tx_mtag, map, BUS_DMASYNC_PREWRITE);
2828
2829         for (i = 0; ; i++) {
2830                 d = &txr->bnx_tx_ring[idx];
2831
2832                 d->bge_addr.bge_addr_lo = BGE_ADDR_LO(segs[i].ds_addr);
2833                 d->bge_addr.bge_addr_hi = BGE_ADDR_HI(segs[i].ds_addr);
2834                 d->bge_len = segs[i].ds_len;
2835                 d->bge_flags = csum_flags;
2836                 d->bge_vlan_tag = vlan_tag;
2837                 d->bge_mss = mss;
2838
2839                 if (i == nsegs - 1)
2840                         break;
2841                 BNX_INC(idx, BGE_TX_RING_CNT);
2842         }
2843         /* Mark the last segment as end of packet... */
2844         d->bge_flags |= BGE_TXBDFLAG_END;
2845
2846         /*
2847          * Insure that the map for this transmission is placed at
2848          * the array index of the last descriptor in this chain.
2849          */
2850         txr->bnx_tx_dmamap[*txidx] = txr->bnx_tx_dmamap[idx];
2851         txr->bnx_tx_dmamap[idx] = map;
2852         txr->bnx_tx_chain[idx] = m_head;
2853         txr->bnx_txcnt += nsegs;
2854
2855         BNX_INC(idx, BGE_TX_RING_CNT);
2856         *txidx = idx;
2857 back:
2858         if (error) {
2859                 m_freem(*m_head0);
2860                 *m_head0 = NULL;
2861         }
2862         return error;
2863 }
2864
2865 /*
2866  * Main transmit routine. To avoid having to do mbuf copies, we put pointers
2867  * to the mbuf data regions directly in the transmit descriptors.
2868  */
2869 static void
2870 bnx_start(struct ifnet *ifp, struct ifaltq_subque *ifsq)
2871 {
2872         struct bnx_softc *sc = ifp->if_softc;
2873         struct bnx_tx_ring *txr = &sc->bnx_tx_ring[0]; /* XXX */
2874         struct mbuf *m_head = NULL;
2875         uint32_t prodidx;
2876         int nsegs = 0;
2877
2878         ASSERT_ALTQ_SQ_DEFAULT(ifp, ifsq);
2879
2880         if ((ifp->if_flags & IFF_RUNNING) == 0 || ifq_is_oactive(&ifp->if_snd))
2881                 return;
2882
2883         prodidx = txr->bnx_tx_prodidx;
2884
2885         while (txr->bnx_tx_chain[prodidx] == NULL) {
2886                 /*
2887                  * Sanity check: avoid coming within BGE_NSEG_RSVD
2888                  * descriptors of the end of the ring.  Also make
2889                  * sure there are BGE_NSEG_SPARE descriptors for
2890                  * jumbo buffers' or TSO segments' defragmentation.
2891                  */
2892                 if ((BGE_TX_RING_CNT - txr->bnx_txcnt) <
2893                     (BNX_NSEG_RSVD + BNX_NSEG_SPARE)) {
2894                         ifq_set_oactive(&ifp->if_snd);
2895                         break;
2896                 }
2897
2898                 m_head = ifq_dequeue(&ifp->if_snd, NULL);
2899                 if (m_head == NULL)
2900                         break;
2901
2902                 /*
2903                  * Pack the data into the transmit ring. If we
2904                  * don't have room, set the OACTIVE flag and wait
2905                  * for the NIC to drain the ring.
2906                  */
2907                 if (bnx_encap(txr, &m_head, &prodidx, &nsegs)) {
2908                         ifq_set_oactive(&ifp->if_snd);
2909                         IFNET_STAT_INC(ifp, oerrors, 1);
2910                         break;
2911                 }
2912
2913                 if (nsegs >= txr->bnx_tx_wreg) {
2914                         /* Transmit */
2915                         bnx_writembx(txr->bnx_sc, BGE_MBX_TX_HOST_PROD0_LO,
2916                             prodidx);
2917                         nsegs = 0;
2918                 }
2919
2920                 ETHER_BPF_MTAP(ifp, m_head);
2921
2922                 /*
2923                  * Set a timeout in case the chip goes out to lunch.
2924                  */
2925                 ifp->if_timer = 5;
2926         }
2927
2928         if (nsegs > 0) {
2929                 /* Transmit */
2930                 bnx_writembx(txr->bnx_sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx);
2931         }
2932         txr->bnx_tx_prodidx = prodidx;
2933 }
2934
2935 static void
2936 bnx_init(void *xsc)
2937 {
2938         struct bnx_softc *sc = xsc;
2939         struct ifnet *ifp = &sc->arpcom.ac_if;
2940         uint16_t *m;
2941         uint32_t mode;
2942         int i;
2943
2944         ASSERT_SERIALIZED(ifp->if_serializer);
2945
2946         /* Cancel pending I/O and flush buffers. */
2947         bnx_stop(sc);
2948         bnx_reset(sc);
2949         bnx_chipinit(sc);
2950
2951         /*
2952          * Init the various state machines, ring
2953          * control blocks and firmware.
2954          */
2955         if (bnx_blockinit(sc)) {
2956                 if_printf(ifp, "initialization failure\n");
2957                 bnx_stop(sc);
2958                 return;
2959         }
2960
2961         /* Specify MTU. */
2962         CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu +
2963             ETHER_HDR_LEN + ETHER_CRC_LEN + EVL_ENCAPLEN);
2964
2965         /* Load our MAC address. */
2966         m = (uint16_t *)&sc->arpcom.ac_enaddr[0];
2967         CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0]));
2968         CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2]));
2969
2970         /* Enable or disable promiscuous mode as needed. */
2971         bnx_setpromisc(sc);
2972
2973         /* Program multicast filter. */
2974         bnx_setmulti(sc);
2975
2976         /* Init RX ring. */
2977         if (bnx_init_rx_ring_std(sc)) {
2978                 if_printf(ifp, "RX ring initialization failed\n");
2979                 bnx_stop(sc);
2980                 return;
2981         }
2982
2983         /* Init jumbo RX ring. */
2984         if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) {
2985                 if (bnx_init_rx_ring_jumbo(sc)) {
2986                         if_printf(ifp, "Jumbo RX ring initialization failed\n");
2987                         bnx_stop(sc);
2988                         return;
2989                 }
2990         }
2991
2992         /* Init our RX return ring index */
2993         sc->bnx_rx_saved_considx = 0;
2994
2995         /* Init TX ring. */
2996         for (i = 0; i < sc->bnx_tx_ringcnt; ++i)
2997                 bnx_init_tx_ring(&sc->bnx_tx_ring[i]);
2998
2999         /* Enable TX MAC state machine lockup fix. */
3000         mode = CSR_READ_4(sc, BGE_TX_MODE);
3001         mode |= BGE_TXMODE_MBUF_LOCKUP_FIX;
3002         if (sc->bnx_asicrev == BGE_ASICREV_BCM5720 ||
3003             sc->bnx_asicrev == BGE_ASICREV_BCM5762) {
3004                 mode &= ~(BGE_TXMODE_JMB_FRM_LEN | BGE_TXMODE_CNT_DN_MODE);
3005                 mode |= CSR_READ_4(sc, BGE_TX_MODE) &
3006                     (BGE_TXMODE_JMB_FRM_LEN | BGE_TXMODE_CNT_DN_MODE);
3007         }
3008         /* Turn on transmitter */
3009         CSR_WRITE_4(sc, BGE_TX_MODE, mode | BGE_TXMODE_ENABLE);
3010
3011         /* Turn on receiver */
3012         BNX_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);
3013
3014         /*
3015          * Set the number of good frames to receive after RX MBUF
3016          * Low Watermark has been reached.  After the RX MAC receives
3017          * this number of frames, it will drop subsequent incoming
3018          * frames until the MBUF High Watermark is reached.
3019          */
3020         if (BNX_IS_57765_FAMILY(sc))
3021                 CSR_WRITE_4(sc, BGE_MAX_RX_FRAME_LOWAT, 1);
3022         else
3023                 CSR_WRITE_4(sc, BGE_MAX_RX_FRAME_LOWAT, 2);
3024
3025         if (sc->bnx_irq_type == PCI_INTR_TYPE_MSI) {
3026                 if (bootverbose) {
3027                         if_printf(ifp, "MSI_MODE: %#x\n",
3028                             CSR_READ_4(sc, BGE_MSI_MODE));
3029                 }
3030         }
3031
3032         /* Tell firmware we're alive. */
3033         BNX_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
3034
3035         /* Enable host interrupts if polling(4) is not enabled. */
3036         PCI_SETBIT(sc->bnx_dev, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA, 4);
3037 #ifdef IFPOLL_ENABLE
3038         if (ifp->if_flags & IFF_NPOLLING)
3039                 bnx_disable_intr(sc);
3040         else
3041 #endif
3042         bnx_enable_intr(sc);
3043
3044         bnx_ifmedia_upd(ifp);
3045
3046         ifp->if_flags |= IFF_RUNNING;
3047         ifq_clr_oactive(&ifp->if_snd);
3048
3049         callout_reset_bycpu(&sc->bnx_stat_timer, hz, bnx_tick, sc,
3050             sc->bnx_stat_cpuid);
3051 }
3052
3053 /*
3054  * Set media options.
3055  */
3056 static int
3057 bnx_ifmedia_upd(struct ifnet *ifp)
3058 {
3059         struct bnx_softc *sc = ifp->if_softc;
3060
3061         /* If this is a 1000baseX NIC, enable the TBI port. */
3062         if (sc->bnx_flags & BNX_FLAG_TBI) {
3063                 struct ifmedia *ifm = &sc->bnx_ifmedia;
3064
3065                 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
3066                         return(EINVAL);
3067
3068                 switch(IFM_SUBTYPE(ifm->ifm_media)) {
3069                 case IFM_AUTO:
3070                         break;
3071
3072                 case IFM_1000_SX:
3073                         if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) {
3074                                 BNX_CLRBIT(sc, BGE_MAC_MODE,
3075                                     BGE_MACMODE_HALF_DUPLEX);
3076                         } else {
3077                                 BNX_SETBIT(sc, BGE_MAC_MODE,
3078                                     BGE_MACMODE_HALF_DUPLEX);
3079                         }
3080                         break;
3081                 default:
3082                         return(EINVAL);
3083                 }
3084         } else {
3085                 struct mii_data *mii = device_get_softc(sc->bnx_miibus);
3086
3087                 sc->bnx_link_evt++;
3088                 sc->bnx_link = 0;
3089                 if (mii->mii_instance) {
3090                         struct mii_softc *miisc;
3091
3092                         LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
3093                                 mii_phy_reset(miisc);
3094                 }
3095                 mii_mediachg(mii);
3096
3097                 /*
3098                  * Force an interrupt so that we will call bnx_link_upd
3099                  * if needed and clear any pending link state attention.
3100                  * Without this we are not getting any further interrupts
3101                  * for link state changes and thus will not UP the link and
3102                  * not be able to send in bnx_start.  The only way to get
3103                  * things working was to receive a packet and get an RX
3104                  * intr.
3105                  *
3106                  * bnx_tick should help for fiber cards and we might not
3107                  * need to do this here if BNX_FLAG_TBI is set but as
3108                  * we poll for fiber anyway it should not harm.
3109                  */
3110                 BNX_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW);
3111         }
3112         return(0);
3113 }
3114
3115 /*
3116  * Report current media status.
3117  */
3118 static void
3119 bnx_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
3120 {
3121         struct bnx_softc *sc = ifp->if_softc;
3122
3123         if (sc->bnx_flags & BNX_FLAG_TBI) {
3124                 ifmr->ifm_status = IFM_AVALID;
3125                 ifmr->ifm_active = IFM_ETHER;
3126                 if (CSR_READ_4(sc, BGE_MAC_STS) &
3127                     BGE_MACSTAT_TBI_PCS_SYNCHED) {
3128                         ifmr->ifm_status |= IFM_ACTIVE;
3129                 } else {
3130                         ifmr->ifm_active |= IFM_NONE;
3131                         return;
3132                 }
3133
3134                 ifmr->ifm_active |= IFM_1000_SX;
3135                 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX)
3136                         ifmr->ifm_active |= IFM_HDX;    
3137                 else
3138                         ifmr->ifm_active |= IFM_FDX;
3139         } else {
3140                 struct mii_data *mii = device_get_softc(sc->bnx_miibus);
3141
3142                 mii_pollstat(mii);
3143                 ifmr->ifm_active = mii->mii_media_active;
3144                 ifmr->ifm_status = mii->mii_media_status;
3145         }
3146 }
3147
3148 static int
3149 bnx_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
3150 {
3151         struct bnx_softc *sc = ifp->if_softc;
3152         struct ifreq *ifr = (struct ifreq *)data;
3153         int mask, error = 0;
3154
3155         ASSERT_SERIALIZED(ifp->if_serializer);
3156
3157         switch (command) {
3158         case SIOCSIFMTU:
3159                 if ((!BNX_IS_JUMBO_CAPABLE(sc) && ifr->ifr_mtu > ETHERMTU) ||
3160                     (BNX_IS_JUMBO_CAPABLE(sc) &&
3161                      ifr->ifr_mtu > BNX_JUMBO_MTU)) {
3162                         error = EINVAL;
3163                 } else if (ifp->if_mtu != ifr->ifr_mtu) {
3164                         ifp->if_mtu = ifr->ifr_mtu;
3165                         if (ifp->if_flags & IFF_RUNNING)
3166                                 bnx_init(sc);
3167                 }
3168                 break;
3169         case SIOCSIFFLAGS:
3170                 if (ifp->if_flags & IFF_UP) {
3171                         if (ifp->if_flags & IFF_RUNNING) {
3172                                 mask = ifp->if_flags ^ sc->bnx_if_flags;
3173
3174                                 /*
3175                                  * If only the state of the PROMISC flag
3176                                  * changed, then just use the 'set promisc
3177                                  * mode' command instead of reinitializing
3178                                  * the entire NIC. Doing a full re-init
3179                                  * means reloading the firmware and waiting
3180                                  * for it to start up, which may take a
3181                                  * second or two.  Similarly for ALLMULTI.
3182                                  */
3183                                 if (mask & IFF_PROMISC)
3184                                         bnx_setpromisc(sc);
3185                                 if (mask & IFF_ALLMULTI)
3186                                         bnx_setmulti(sc);
3187                         } else {
3188                                 bnx_init(sc);
3189                         }
3190                 } else if (ifp->if_flags & IFF_RUNNING) {
3191                         bnx_stop(sc);
3192                 }
3193                 sc->bnx_if_flags = ifp->if_flags;
3194                 break;
3195         case SIOCADDMULTI:
3196         case SIOCDELMULTI:
3197                 if (ifp->if_flags & IFF_RUNNING)
3198                         bnx_setmulti(sc);
3199                 break;
3200         case SIOCSIFMEDIA:
3201         case SIOCGIFMEDIA:
3202                 if (sc->bnx_flags & BNX_FLAG_TBI) {
3203                         error = ifmedia_ioctl(ifp, ifr,
3204                             &sc->bnx_ifmedia, command);
3205                 } else {
3206                         struct mii_data *mii;
3207
3208                         mii = device_get_softc(sc->bnx_miibus);
3209                         error = ifmedia_ioctl(ifp, ifr,
3210                                               &mii->mii_media, command);
3211                 }
3212                 break;
3213         case SIOCSIFCAP:
3214                 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
3215                 if (mask & IFCAP_HWCSUM) {
3216                         ifp->if_capenable ^= (mask & IFCAP_HWCSUM);
3217                         if (ifp->if_capenable & IFCAP_TXCSUM)
3218                                 ifp->if_hwassist |= BNX_CSUM_FEATURES;
3219                         else
3220                                 ifp->if_hwassist &= ~BNX_CSUM_FEATURES;
3221                 }
3222                 if (mask & IFCAP_TSO) {
3223                         ifp->if_capenable ^= (mask & IFCAP_TSO);
3224                         if (ifp->if_capenable & IFCAP_TSO)
3225                                 ifp->if_hwassist |= CSUM_TSO;
3226                         else
3227                                 ifp->if_hwassist &= ~CSUM_TSO;
3228                 }
3229                 break;
3230         default:
3231                 error = ether_ioctl(ifp, command, data);
3232                 break;
3233         }
3234         return error;
3235 }
3236
3237 static void
3238 bnx_watchdog(struct ifnet *ifp)
3239 {
3240         struct bnx_softc *sc = ifp->if_softc;
3241
3242         if_printf(ifp, "watchdog timeout -- resetting\n");
3243
3244         bnx_init(sc);
3245
3246         IFNET_STAT_INC(ifp, oerrors, 1);
3247
3248         if (!ifq_is_empty(&ifp->if_snd))
3249                 if_devstart(ifp);
3250 }
3251
3252 /*
3253  * Stop the adapter and free any mbufs allocated to the
3254  * RX and TX lists.
3255  */
3256 static void
3257 bnx_stop(struct bnx_softc *sc)
3258 {
3259         struct ifnet *ifp = &sc->arpcom.ac_if;
3260         int i;
3261
3262         ASSERT_SERIALIZED(ifp->if_serializer);
3263
3264         callout_stop(&sc->bnx_stat_timer);
3265
3266         /*
3267          * Disable all of the receiver blocks
3268          */
3269         bnx_stop_block(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);
3270         bnx_stop_block(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
3271         bnx_stop_block(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
3272         bnx_stop_block(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE);
3273         bnx_stop_block(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
3274         bnx_stop_block(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE);
3275
3276         /*
3277          * Disable all of the transmit blocks
3278          */
3279         bnx_stop_block(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
3280         bnx_stop_block(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
3281         bnx_stop_block(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
3282         bnx_stop_block(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE);
3283         bnx_stop_block(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE);
3284         bnx_stop_block(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
3285
3286         /*
3287          * Shut down all of the memory managers and related
3288          * state machines.
3289          */
3290         bnx_stop_block(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE);
3291         bnx_stop_block(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE);
3292         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
3293         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
3294
3295         /* Disable host interrupts. */
3296         bnx_disable_intr(sc);
3297
3298         /*
3299          * Tell firmware we're shutting down.
3300          */
3301         BNX_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
3302
3303         /* Free the RX lists. */
3304         bnx_free_rx_ring_std(sc);
3305
3306         /* Free jumbo RX list. */
3307         if (BNX_IS_JUMBO_CAPABLE(sc))
3308                 bnx_free_rx_ring_jumbo(sc);
3309
3310         /* Free TX buffers. */
3311         for (i = 0; i < sc->bnx_tx_ringcnt; ++i)
3312                 bnx_free_tx_ring(&sc->bnx_tx_ring[i]);
3313
3314         sc->bnx_status_tag = 0;
3315         sc->bnx_link = 0;
3316         sc->bnx_coal_chg = 0;
3317
3318         ifp->if_flags &= ~IFF_RUNNING;
3319         ifq_clr_oactive(&ifp->if_snd);
3320         ifp->if_timer = 0;
3321 }
3322
3323 /*
3324  * Stop all chip I/O so that the kernel's probe routines don't
3325  * get confused by errant DMAs when rebooting.
3326  */
3327 static void
3328 bnx_shutdown(device_t dev)
3329 {
3330         struct bnx_softc *sc = device_get_softc(dev);
3331         struct ifnet *ifp = &sc->arpcom.ac_if;
3332
3333         lwkt_serialize_enter(ifp->if_serializer);
3334         bnx_stop(sc);
3335         bnx_reset(sc);
3336         lwkt_serialize_exit(ifp->if_serializer);
3337 }
3338
3339 static int
3340 bnx_suspend(device_t dev)
3341 {
3342         struct bnx_softc *sc = device_get_softc(dev);
3343         struct ifnet *ifp = &sc->arpcom.ac_if;
3344
3345         lwkt_serialize_enter(ifp->if_serializer);
3346         bnx_stop(sc);
3347         lwkt_serialize_exit(ifp->if_serializer);
3348
3349         return 0;
3350 }
3351
3352 static int
3353 bnx_resume(device_t dev)
3354 {
3355         struct bnx_softc *sc = device_get_softc(dev);
3356         struct ifnet *ifp = &sc->arpcom.ac_if;
3357
3358         lwkt_serialize_enter(ifp->if_serializer);
3359
3360         if (ifp->if_flags & IFF_UP) {
3361                 bnx_init(sc);
3362
3363                 if (!ifq_is_empty(&ifp->if_snd))
3364                         if_devstart(ifp);
3365         }
3366
3367         lwkt_serialize_exit(ifp->if_serializer);
3368
3369         return 0;
3370 }
3371
3372 static void
3373 bnx_setpromisc(struct bnx_softc *sc)
3374 {
3375         struct ifnet *ifp = &sc->arpcom.ac_if;
3376
3377         if (ifp->if_flags & IFF_PROMISC)
3378                 BNX_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
3379         else
3380                 BNX_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
3381 }
3382
3383 static void
3384 bnx_dma_free(struct bnx_softc *sc)
3385 {
3386         int i;
3387
3388         /* Destroy RX mbuf DMA stuffs. */
3389         if (sc->bnx_cdata.bnx_rx_mtag != NULL) {
3390                 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
3391                         bus_dmamap_destroy(sc->bnx_cdata.bnx_rx_mtag,
3392                             sc->bnx_cdata.bnx_rx_std_dmamap[i]);
3393                 }
3394                 bus_dmamap_destroy(sc->bnx_cdata.bnx_rx_mtag,
3395                                    sc->bnx_cdata.bnx_rx_tmpmap);
3396                 bus_dma_tag_destroy(sc->bnx_cdata.bnx_rx_mtag);
3397         }
3398
3399         /* Destroy TX rings */
3400         if (sc->bnx_tx_ring != NULL) {
3401                 for (i = 0; i < sc->bnx_tx_ringcnt; ++i)
3402                         bnx_destroy_tx_ring(&sc->bnx_tx_ring[i]);
3403                 kfree(sc->bnx_tx_ring, M_DEVBUF);
3404         }
3405
3406         /* Destroy standard RX ring */
3407         bnx_dma_block_free(sc->bnx_cdata.bnx_rx_std_ring_tag,
3408                            sc->bnx_cdata.bnx_rx_std_ring_map,
3409                            sc->bnx_ldata.bnx_rx_std_ring);
3410
3411         if (BNX_IS_JUMBO_CAPABLE(sc))
3412                 bnx_free_jumbo_mem(sc);
3413
3414         /* Destroy RX return ring */
3415         bnx_dma_block_free(sc->bnx_cdata.bnx_rx_return_ring_tag,
3416                            sc->bnx_cdata.bnx_rx_return_ring_map,
3417                            sc->bnx_ldata.bnx_rx_return_ring);
3418
3419         /* Destroy status block */
3420         bnx_dma_block_free(sc->bnx_cdata.bnx_status_tag,
3421                            sc->bnx_cdata.bnx_status_map,
3422                            sc->bnx_ldata.bnx_status_block);
3423
3424         /* Destroy the parent tag */
3425         if (sc->bnx_cdata.bnx_parent_tag != NULL)
3426                 bus_dma_tag_destroy(sc->bnx_cdata.bnx_parent_tag);
3427 }
3428
3429 static int
3430 bnx_dma_alloc(struct bnx_softc *sc)
3431 {
3432         struct ifnet *ifp = &sc->arpcom.ac_if;
3433         int i, error;
3434
3435         /*
3436          * Allocate the parent bus DMA tag appropriate for PCI.
3437          *
3438          * All of the NetExtreme/NetLink controllers have 4GB boundary
3439          * DMA bug.
3440          * Whenever an address crosses a multiple of the 4GB boundary
3441          * (including 4GB, 8Gb, 12Gb, etc.) and makes the transition
3442          * from 0xX_FFFF_FFFF to 0x(X+1)_0000_0000 an internal DMA
3443          * state machine will lockup and cause the device to hang.
3444          */
3445         error = bus_dma_tag_create(NULL, 1, BGE_DMA_BOUNDARY_4G,
3446                                    BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
3447                                    NULL, NULL,
3448                                    BUS_SPACE_MAXSIZE_32BIT, 0,
3449                                    BUS_SPACE_MAXSIZE_32BIT,
3450                                    0, &sc->bnx_cdata.bnx_parent_tag);
3451         if (error) {
3452                 if_printf(ifp, "could not allocate parent dma tag\n");
3453                 return error;
3454         }
3455
3456         /*
3457          * Create DMA tag and maps for RX mbufs.
3458          */
3459         error = bus_dma_tag_create(sc->bnx_cdata.bnx_parent_tag, 1, 0,
3460                                    BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
3461                                    NULL, NULL, MCLBYTES, 1, MCLBYTES,
3462                                    BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK,
3463                                    &sc->bnx_cdata.bnx_rx_mtag);
3464         if (error) {
3465                 if_printf(ifp, "could not allocate RX mbuf dma tag\n");
3466                 return error;
3467         }
3468
3469         error = bus_dmamap_create(sc->bnx_cdata.bnx_rx_mtag,
3470                                   BUS_DMA_WAITOK, &sc->bnx_cdata.bnx_rx_tmpmap);
3471         if (error) {
3472                 bus_dma_tag_destroy(sc->bnx_cdata.bnx_rx_mtag);
3473                 sc->bnx_cdata.bnx_rx_mtag = NULL;
3474                 return error;
3475         }
3476
3477         for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
3478                 error = bus_dmamap_create(sc->bnx_cdata.bnx_rx_mtag,
3479                                           BUS_DMA_WAITOK,
3480                                           &sc->bnx_cdata.bnx_rx_std_dmamap[i]);
3481                 if (error) {
3482                         int j;
3483
3484                         for (j = 0; j < i; ++j) {
3485                                 bus_dmamap_destroy(sc->bnx_cdata.bnx_rx_mtag,
3486                                         sc->bnx_cdata.bnx_rx_std_dmamap[j]);
3487                         }
3488                         bus_dma_tag_destroy(sc->bnx_cdata.bnx_rx_mtag);
3489                         sc->bnx_cdata.bnx_rx_mtag = NULL;
3490
3491                         if_printf(ifp, "could not create DMA map for RX\n");
3492                         return error;
3493                 }
3494         }
3495
3496         /*
3497          * Create DMA stuffs for standard RX ring.
3498          */
3499         error = bnx_dma_block_alloc(sc, BGE_STD_RX_RING_SZ,
3500                                     &sc->bnx_cdata.bnx_rx_std_ring_tag,
3501                                     &sc->bnx_cdata.bnx_rx_std_ring_map,
3502                                     (void *)&sc->bnx_ldata.bnx_rx_std_ring,
3503                                     &sc->bnx_ldata.bnx_rx_std_ring_paddr);
3504         if (error) {
3505                 if_printf(ifp, "could not create std RX ring\n");
3506                 return error;
3507         }
3508
3509         /*
3510          * Create jumbo buffer pool.
3511          */
3512         if (BNX_IS_JUMBO_CAPABLE(sc)) {
3513                 error = bnx_alloc_jumbo_mem(sc);
3514                 if (error) {
3515                         if_printf(ifp, "could not create jumbo buffer pool\n");
3516                         return error;
3517                 }
3518         }
3519
3520         /*
3521          * Create DMA stuffs for RX return ring.
3522          */
3523         error = bnx_dma_block_alloc(sc,
3524             BGE_RX_RTN_RING_SZ(BNX_RETURN_RING_CNT),
3525             &sc->bnx_cdata.bnx_rx_return_ring_tag,
3526             &sc->bnx_cdata.bnx_rx_return_ring_map,
3527             (void *)&sc->bnx_ldata.bnx_rx_return_ring,
3528             &sc->bnx_ldata.bnx_rx_return_ring_paddr);
3529         if (error) {
3530                 if_printf(ifp, "could not create RX ret ring\n");
3531                 return error;
3532         }
3533
3534         /*
3535          * Create DMA stuffs for status block.
3536          */
3537         error = bnx_dma_block_alloc(sc, BGE_STATUS_BLK_SZ,
3538                                     &sc->bnx_cdata.bnx_status_tag,
3539                                     &sc->bnx_cdata.bnx_status_map,
3540                                     (void *)&sc->bnx_ldata.bnx_status_block,
3541                                     &sc->bnx_ldata.bnx_status_block_paddr);
3542         if (error) {
3543                 if_printf(ifp, "could not create status block\n");
3544                 return error;
3545         }
3546
3547         sc->bnx_tx_ring = kmalloc_cachealign(
3548             sizeof(struct bnx_tx_ring) * sc->bnx_tx_ringcnt, M_DEVBUF,
3549             M_WAITOK | M_ZERO);
3550         for (i = 0; i < sc->bnx_tx_ringcnt; ++i) {
3551                 struct bnx_tx_ring *txr = &sc->bnx_tx_ring[i];
3552
3553                 txr->bnx_sc = sc;
3554                 error = bnx_create_tx_ring(txr);
3555                 if (error) {
3556                         device_printf(sc->bnx_dev,
3557                             "can't create %dth tx ring\n", i);
3558                         return error;
3559                 }
3560         }
3561
3562         return 0;
3563 }
3564
3565 static int
3566 bnx_dma_block_alloc(struct bnx_softc *sc, bus_size_t size, bus_dma_tag_t *tag,
3567                     bus_dmamap_t *map, void **addr, bus_addr_t *paddr)
3568 {
3569         bus_dmamem_t dmem;
3570         int error;
3571
3572         error = bus_dmamem_coherent(sc->bnx_cdata.bnx_parent_tag, PAGE_SIZE, 0,
3573                                     BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
3574                                     size, BUS_DMA_WAITOK | BUS_DMA_ZERO, &dmem);
3575         if (error)
3576                 return error;
3577
3578         *tag = dmem.dmem_tag;
3579         *map = dmem.dmem_map;
3580         *addr = dmem.dmem_addr;
3581         *paddr = dmem.dmem_busaddr;
3582
3583         return 0;
3584 }
3585
3586 static void
3587 bnx_dma_block_free(bus_dma_tag_t tag, bus_dmamap_t map, void *addr)
3588 {
3589         if (tag != NULL) {
3590                 bus_dmamap_unload(tag, map);
3591                 bus_dmamem_free(tag, addr, map);
3592                 bus_dma_tag_destroy(tag);
3593         }
3594 }
3595
3596 static void
3597 bnx_tbi_link_upd(struct bnx_softc *sc, uint32_t status)
3598 {
3599         struct ifnet *ifp = &sc->arpcom.ac_if;
3600
3601 #define PCS_ENCODE_ERR  (BGE_MACSTAT_PORT_DECODE_ERROR|BGE_MACSTAT_MI_COMPLETE)
3602
3603         /*
3604          * Sometimes PCS encoding errors are detected in
3605          * TBI mode (on fiber NICs), and for some reason
3606          * the chip will signal them as link changes.
3607          * If we get a link change event, but the 'PCS
3608          * encoding error' bit in the MAC status register
3609          * is set, don't bother doing a link check.
3610          * This avoids spurious "gigabit link up" messages
3611          * that sometimes appear on fiber NICs during
3612          * periods of heavy traffic.
3613          */
3614         if (status & BGE_MACSTAT_TBI_PCS_SYNCHED) {
3615                 if (!sc->bnx_link) {
3616                         sc->bnx_link++;
3617                         if (sc->bnx_asicrev == BGE_ASICREV_BCM5704) {
3618                                 BNX_CLRBIT(sc, BGE_MAC_MODE,
3619                                     BGE_MACMODE_TBI_SEND_CFGS);
3620                         }
3621                         CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF);
3622
3623                         if (bootverbose)
3624                                 if_printf(ifp, "link UP\n");
3625
3626                         ifp->if_link_state = LINK_STATE_UP;
3627                         if_link_state_change(ifp);
3628                 }
3629         } else if ((status & PCS_ENCODE_ERR) != PCS_ENCODE_ERR) {
3630                 if (sc->bnx_link) {
3631                         sc->bnx_link = 0;
3632
3633                         if (bootverbose)
3634                                 if_printf(ifp, "link DOWN\n");
3635
3636                         ifp->if_link_state = LINK_STATE_DOWN;
3637                         if_link_state_change(ifp);
3638                 }
3639         }
3640
3641 #undef PCS_ENCODE_ERR
3642
3643         /* Clear the attention. */
3644         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
3645             BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
3646             BGE_MACSTAT_LINK_CHANGED);
3647 }
3648
3649 static void
3650 bnx_copper_link_upd(struct bnx_softc *sc, uint32_t status __unused)
3651 {
3652         struct ifnet *ifp = &sc->arpcom.ac_if;
3653         struct mii_data *mii = device_get_softc(sc->bnx_miibus);
3654
3655         mii_pollstat(mii);
3656         bnx_miibus_statchg(sc->bnx_dev);
3657
3658         if (bootverbose) {
3659                 if (sc->bnx_link)
3660                         if_printf(ifp, "link UP\n");
3661                 else
3662                         if_printf(ifp, "link DOWN\n");
3663         }
3664
3665         /* Clear the attention. */
3666         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
3667             BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
3668             BGE_MACSTAT_LINK_CHANGED);
3669 }
3670
3671 static void
3672 bnx_autopoll_link_upd(struct bnx_softc *sc, uint32_t status __unused)
3673 {
3674         struct ifnet *ifp = &sc->arpcom.ac_if;
3675         struct mii_data *mii = device_get_softc(sc->bnx_miibus);
3676
3677         mii_pollstat(mii);
3678
3679         if (!sc->bnx_link &&
3680             (mii->mii_media_status & IFM_ACTIVE) &&
3681             IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
3682                 sc->bnx_link++;
3683                 if (bootverbose)
3684                         if_printf(ifp, "link UP\n");
3685         } else if (sc->bnx_link &&
3686             (!(mii->mii_media_status & IFM_ACTIVE) ||
3687             IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) {
3688                 sc->bnx_link = 0;
3689                 if (bootverbose)
3690                         if_printf(ifp, "link DOWN\n");
3691         }
3692
3693         /* Clear the attention. */
3694         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
3695             BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
3696             BGE_MACSTAT_LINK_CHANGED);
3697 }
3698
3699 static int
3700 bnx_sysctl_rx_coal_ticks(SYSCTL_HANDLER_ARGS)
3701 {
3702         struct bnx_softc *sc = arg1;
3703
3704         return bnx_sysctl_coal_chg(oidp, arg1, arg2, req,
3705             &sc->bnx_rx_coal_ticks,
3706             BNX_RX_COAL_TICKS_MIN, BNX_RX_COAL_TICKS_MAX,
3707             BNX_RX_COAL_TICKS_CHG);
3708 }
3709
3710 static int
3711 bnx_sysctl_tx_coal_ticks(SYSCTL_HANDLER_ARGS)
3712 {
3713         struct bnx_softc *sc = arg1;
3714
3715         return bnx_sysctl_coal_chg(oidp, arg1, arg2, req,
3716             &sc->bnx_tx_coal_ticks,
3717             BNX_TX_COAL_TICKS_MIN, BNX_TX_COAL_TICKS_MAX,
3718             BNX_TX_COAL_TICKS_CHG);
3719 }
3720
3721 static int
3722 bnx_sysctl_rx_coal_bds(SYSCTL_HANDLER_ARGS)
3723 {
3724         struct bnx_softc *sc = arg1;
3725
3726         return bnx_sysctl_coal_chg(oidp, arg1, arg2, req,
3727             &sc->bnx_rx_coal_bds,
3728             BNX_RX_COAL_BDS_MIN, BNX_RX_COAL_BDS_MAX,
3729             BNX_RX_COAL_BDS_CHG);
3730 }
3731
3732 static int
3733 bnx_sysctl_tx_coal_bds(SYSCTL_HANDLER_ARGS)
3734 {
3735         struct bnx_softc *sc = arg1;
3736
3737         return bnx_sysctl_coal_chg(oidp, arg1, arg2, req,
3738             &sc->bnx_tx_coal_bds,
3739             BNX_TX_COAL_BDS_MIN, BNX_TX_COAL_BDS_MAX,
3740             BNX_TX_COAL_BDS_CHG);
3741 }
3742
3743 static int
3744 bnx_sysctl_rx_coal_bds_int(SYSCTL_HANDLER_ARGS)
3745 {
3746         struct bnx_softc *sc = arg1;
3747
3748         return bnx_sysctl_coal_chg(oidp, arg1, arg2, req,
3749             &sc->bnx_rx_coal_bds_int,
3750             BNX_RX_COAL_BDS_MIN, BNX_RX_COAL_BDS_MAX,
3751             BNX_RX_COAL_BDS_INT_CHG);
3752 }
3753
3754 static int
3755 bnx_sysctl_tx_coal_bds_int(SYSCTL_HANDLER_ARGS)
3756 {
3757         struct bnx_softc *sc = arg1;
3758
3759         return bnx_sysctl_coal_chg(oidp, arg1, arg2, req,
3760             &sc->bnx_tx_coal_bds_int,
3761             BNX_TX_COAL_BDS_MIN, BNX_TX_COAL_BDS_MAX,
3762             BNX_TX_COAL_BDS_INT_CHG);
3763 }
3764
3765 static int
3766 bnx_sysctl_coal_chg(SYSCTL_HANDLER_ARGS, uint32_t *coal,
3767     int coal_min, int coal_max, uint32_t coal_chg_mask)
3768 {
3769         struct bnx_softc *sc = arg1;
3770         struct ifnet *ifp = &sc->arpcom.ac_if;
3771         int error = 0, v;
3772
3773         lwkt_serialize_enter(ifp->if_serializer);
3774
3775         v = *coal;
3776         error = sysctl_handle_int(oidp, &v, 0, req);
3777         if (!error && req->newptr != NULL) {
3778                 if (v < coal_min || v > coal_max) {
3779                         error = EINVAL;
3780                 } else {
3781                         *coal = v;
3782                         sc->bnx_coal_chg |= coal_chg_mask;
3783                 }
3784         }
3785
3786         lwkt_serialize_exit(ifp->if_serializer);
3787         return error;
3788 }
3789
3790 static void
3791 bnx_coal_change(struct bnx_softc *sc)
3792 {
3793         struct ifnet *ifp = &sc->arpcom.ac_if;
3794
3795         ASSERT_SERIALIZED(ifp->if_serializer);
3796
3797         if (sc->bnx_coal_chg & BNX_RX_COAL_TICKS_CHG) {
3798                 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS,
3799                             sc->bnx_rx_coal_ticks);
3800                 DELAY(10);
3801                 CSR_READ_4(sc, BGE_HCC_RX_COAL_TICKS);
3802
3803                 if (bootverbose) {
3804                         if_printf(ifp, "rx_coal_ticks -> %u\n",
3805                                   sc->bnx_rx_coal_ticks);
3806                 }
3807         }
3808
3809         if (sc->bnx_coal_chg & BNX_TX_COAL_TICKS_CHG) {
3810                 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS,
3811                             sc->bnx_tx_coal_ticks);
3812                 DELAY(10);
3813                 CSR_READ_4(sc, BGE_HCC_TX_COAL_TICKS);
3814
3815                 if (bootverbose) {
3816                         if_printf(ifp, "tx_coal_ticks -> %u\n",
3817                                   sc->bnx_tx_coal_ticks);
3818                 }
3819         }
3820
3821         if (sc->bnx_coal_chg & BNX_RX_COAL_BDS_CHG) {
3822                 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS,
3823                             sc->bnx_rx_coal_bds);
3824                 DELAY(10);
3825                 CSR_READ_4(sc, BGE_HCC_RX_MAX_COAL_BDS);
3826
3827                 if (bootverbose) {
3828                         if_printf(ifp, "rx_coal_bds -> %u\n",
3829                                   sc->bnx_rx_coal_bds);
3830                 }
3831         }
3832
3833         if (sc->bnx_coal_chg & BNX_TX_COAL_BDS_CHG) {
3834                 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS,
3835                             sc->bnx_tx_coal_bds);
3836                 DELAY(10);
3837                 CSR_READ_4(sc, BGE_HCC_TX_MAX_COAL_BDS);
3838
3839                 if (bootverbose) {
3840                         if_printf(ifp, "tx_coal_bds -> %u\n",
3841                                   sc->bnx_tx_coal_bds);
3842                 }
3843         }
3844
3845         if (sc->bnx_coal_chg & BNX_RX_COAL_BDS_INT_CHG) {
3846                 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT,
3847                     sc->bnx_rx_coal_bds_int);
3848                 DELAY(10);
3849                 CSR_READ_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT);
3850
3851                 if (bootverbose) {
3852                         if_printf(ifp, "rx_coal_bds_int -> %u\n",
3853                             sc->bnx_rx_coal_bds_int);
3854                 }
3855         }
3856
3857         if (sc->bnx_coal_chg & BNX_TX_COAL_BDS_INT_CHG) {
3858                 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT,
3859                     sc->bnx_tx_coal_bds_int);
3860                 DELAY(10);
3861                 CSR_READ_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT);
3862
3863                 if (bootverbose) {
3864                         if_printf(ifp, "tx_coal_bds_int -> %u\n",
3865                             sc->bnx_tx_coal_bds_int);
3866                 }
3867         }
3868
3869         sc->bnx_coal_chg = 0;
3870 }
3871
3872 static void
3873 bnx_intr_check(void *xsc)
3874 {
3875         struct bnx_softc *sc = xsc;
3876         struct bnx_tx_ring *txr = &sc->bnx_tx_ring[0]; /* XXX */
3877         struct ifnet *ifp = &sc->arpcom.ac_if;
3878         struct bge_status_block *sblk = sc->bnx_ldata.bnx_status_block;
3879
3880         lwkt_serialize_enter(ifp->if_serializer);
3881
3882         KKASSERT(mycpuid == sc->bnx_intr_cpuid);
3883
3884         if ((ifp->if_flags & (IFF_RUNNING | IFF_NPOLLING)) != IFF_RUNNING) {
3885                 lwkt_serialize_exit(ifp->if_serializer);
3886                 return;
3887         }
3888
3889         if (sblk->bge_idx[0].bge_rx_prod_idx != sc->bnx_rx_saved_considx ||
3890             sblk->bge_idx[0].bge_tx_cons_idx != txr->bnx_tx_saved_considx) {
3891                 if (sc->bnx_rx_check_considx == sc->bnx_rx_saved_considx &&
3892                     sc->bnx_tx_check_considx == txr->bnx_tx_saved_considx) {
3893                         if (!sc->bnx_intr_maylose) {
3894                                 sc->bnx_intr_maylose = TRUE;
3895                                 goto done;
3896                         }
3897                         if (bootverbose)
3898                                 if_printf(ifp, "lost interrupt\n");
3899                         bnx_msi(sc);
3900                 }
3901         }
3902         sc->bnx_intr_maylose = FALSE;
3903         sc->bnx_rx_check_considx = sc->bnx_rx_saved_considx;
3904         sc->bnx_tx_check_considx = txr->bnx_tx_saved_considx;
3905
3906 done:
3907         callout_reset(&sc->bnx_intr_timer, BNX_INTR_CKINTVL,
3908             bnx_intr_check, sc);
3909         lwkt_serialize_exit(ifp->if_serializer);
3910 }
3911
3912 static void
3913 bnx_enable_intr(struct bnx_softc *sc)
3914 {
3915         struct ifnet *ifp = &sc->arpcom.ac_if;
3916
3917         lwkt_serialize_handler_enable(ifp->if_serializer);
3918
3919         /*
3920          * Enable interrupt.
3921          */
3922         bnx_writembx(sc, BGE_MBX_IRQ0_LO, sc->bnx_status_tag << 24);
3923         if (sc->bnx_flags & BNX_FLAG_ONESHOT_MSI) {
3924                 /* XXX Linux driver */
3925                 bnx_writembx(sc, BGE_MBX_IRQ0_LO, sc->bnx_status_tag << 24);
3926         }
3927
3928         /*
3929          * Unmask the interrupt when we stop polling.
3930          */
3931         PCI_CLRBIT(sc->bnx_dev, BGE_PCI_MISC_CTL,
3932             BGE_PCIMISCCTL_MASK_PCI_INTR, 4);
3933
3934         /*
3935          * Trigger another interrupt, since above writing
3936          * to interrupt mailbox0 may acknowledge pending
3937          * interrupt.
3938          */
3939         BNX_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET);
3940
3941         if (sc->bnx_flags & BNX_FLAG_STATUSTAG_BUG) {
3942                 sc->bnx_intr_maylose = FALSE;
3943                 sc->bnx_rx_check_considx = 0;
3944                 sc->bnx_tx_check_considx = 0;
3945
3946                 if (bootverbose)
3947                         if_printf(ifp, "status tag bug workaround\n");
3948
3949                 /* 10ms check interval */
3950                 callout_reset_bycpu(&sc->bnx_intr_timer, BNX_INTR_CKINTVL,
3951                     bnx_intr_check, sc, sc->bnx_intr_cpuid);
3952         }
3953 }
3954
3955 static void
3956 bnx_disable_intr(struct bnx_softc *sc)
3957 {
3958         struct ifnet *ifp = &sc->arpcom.ac_if;
3959
3960         /*
3961          * Mask the interrupt when we start polling.
3962          */
3963         PCI_SETBIT(sc->bnx_dev, BGE_PCI_MISC_CTL,
3964             BGE_PCIMISCCTL_MASK_PCI_INTR, 4);
3965
3966         /*
3967          * Acknowledge possible asserted interrupt.
3968          */
3969         bnx_writembx(sc, BGE_MBX_IRQ0_LO, 1);
3970
3971         callout_stop(&sc->bnx_intr_timer);
3972         sc->bnx_intr_maylose = FALSE;
3973         sc->bnx_rx_check_considx = 0;
3974         sc->bnx_tx_check_considx = 0;
3975
3976         sc->bnx_npoll.ifpc_stcount = 0;
3977
3978         lwkt_serialize_handler_disable(ifp->if_serializer);
3979 }
3980
3981 static int
3982 bnx_get_eaddr_mem(struct bnx_softc *sc, uint8_t ether_addr[])
3983 {
3984         uint32_t mac_addr;
3985         int ret = 1;
3986
3987         mac_addr = bnx_readmem_ind(sc, 0x0c14);
3988         if ((mac_addr >> 16) == 0x484b) {
3989                 ether_addr[0] = (uint8_t)(mac_addr >> 8);
3990                 ether_addr[1] = (uint8_t)mac_addr;
3991                 mac_addr = bnx_readmem_ind(sc, 0x0c18);
3992                 ether_addr[2] = (uint8_t)(mac_addr >> 24);
3993                 ether_addr[3] = (uint8_t)(mac_addr >> 16);
3994                 ether_addr[4] = (uint8_t)(mac_addr >> 8);
3995                 ether_addr[5] = (uint8_t)mac_addr;
3996                 ret = 0;
3997         }
3998         return ret;
3999 }
4000
4001 static int
4002 bnx_get_eaddr_nvram(struct bnx_softc *sc, uint8_t ether_addr[])
4003 {
4004         int mac_offset = BGE_EE_MAC_OFFSET;
4005
4006         if (BNX_IS_5717_PLUS(sc)) {
4007                 int f;
4008
4009                 f = pci_get_function(sc->bnx_dev);
4010                 if (f & 1)
4011