2 * Copyright (c) 1995 HD Associates, Inc.
7 * Pepperell, MA 01463-0276
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20 * This product includes software developed by HD Associates, Inc.
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41 * $FreeBSD: src/sys/i386/isa/labpc.c,v 1.35 1999/09/25 18:24:08 phk Exp $
42 * $DragonFly: src/sys/dev/misc/labpc/labpc.c,v 1.18 2006/09/05 00:55:38 dillon Exp $
46 #include "use_labpc.h"
47 #include "opt_debug_outb.h"
48 #include <sys/param.h>
50 #include <sys/systm.h>
52 #include <sys/kernel.h>
53 #include <sys/malloc.h>
55 #define bio_actf bio_act.tqe_next
56 #include <sys/dataacq.h>
58 #include <sys/thread2.h>
61 #include <machine/clock.h>
64 #include <bus/isa/i386/isa_device.h>
71 #define LABPC_MIN_TMO (hz)
74 #ifndef LABPC_DEFAULT_HERTZ
75 #define LABPC_DEFAULT_HERTZ 500
81 * S: SCAN bit for scan enable.
82 * I: INTERVAL for interval support
83 * D: 1: Digital I/O, 0: Analog I/O
86 * input: channel must be 0 to 7.
87 * output: channel must be 0 to 2
90 * 2: Alternate channel 0 then 1
93 * input: Channel must be 0 to 2.
94 * output: Channel must be 0 to 2.
100 #define UNIT(dev) (((minor(dev) & 0xB0) >> 6) & 0x3)
102 #define SCAN(dev) ((minor(dev) & 0x20) >> 5)
103 #define INTERVAL(dev) ((minor(dev) & 0x10) >> 4)
104 #define DIGITAL(dev) ((minor(dev) & 0x08) >> 3)
109 #define CHAN(dev) (minor(dev) & 0x7)
111 /* History: Derived from "dt2811.c" March 1995
117 #define DROPPED_INPUT 0x100
121 #define BUSY 0x00000001
127 struct bio start_queue; /* Start queue */
128 struct bio *last; /* End of start queue */
132 long tmo; /* Timeout in Hertz */
133 long min_tmo; /* Timeout in Hertz */
138 dev_t dev; /* Copy of device */
140 void (*starter)(struct ctlr *ctlr, long count);
141 void (*stop)(struct ctlr *ctlr);
142 void (*intr)(struct ctlr *ctlr);
144 /* Digital I/O support. Copy of Data Control Register for 8255:
146 u_char dcr_val, dcr_is;
149 * Handle for canceling our timeout.
153 /* Device configuration structure:
158 /* loutb is a slow outb for debugging. The overrun test may fail
159 * with this for some slower processors.
162 loutb(int port, u_char val)
168 #define loutb(port, val) outb(port, val)
171 static struct ctlr **labpcs; /* XXX: Should be dynamic */
173 /* CR_EXPR: A macro that sets the shadow register in addition to
174 * sending out the data.
176 #define CR_EXPR(LABPC, CR, EXPR) do { \
177 (LABPC)->cr_image[CR - 1] EXPR ; \
178 loutb(((LABPC)->base + ( (CR == 4) ? (0x0F) : (CR - 1))), ((LABPC)->cr_image[(CR - 1)])); \
181 #define CR_CLR(LABPC, CR) CR_EXPR(LABPC, CR, &=0)
182 #define CR_REFRESH(LABPC, CR) CR_EXPR(LABPC, CR, &=0xff)
183 #define CR_SET(LABPC, CR, EXPR) CR_EXPR(LABPC, CR, = EXPR)
185 /* Configuration and Status Register Group.
187 #define CR1(LABPC) ((LABPC)->base + 0x00) /* Page 4-5 */
189 #define GAINMASK 0x70
190 #define GAIN(LABPC, SEL) do { \
191 (LABPC)->cr_image[1 - 1] &= ~GAINMASK; \
192 (LABPC)->cr_image[1 - 1] |= (SEL << 4); \
193 loutb((LABPC)->base + (1 - 1), (LABPC)->cr_image[(1 - 1)]); \
198 #define MA(LABPC, SEL) do { \
199 (LABPC)->cr_image[1 - 1] &= ~MAMASK; \
200 (LABPC)->cr_image[1 - 1] |= SEL; \
201 loutb((LABPC)->base + (1 - 1), (LABPC)->cr_image[(1 - 1)]); \
204 #define STATUS(LABPC) ((LABPC)->base + 0x00) /* Page 4-7 */
205 #define LABPCPLUS 0x80
206 #define EXTGATA0 0x40
210 #define OVERFLOW 0x04
214 #define CR2(LABPC) ((LABPC)->base + 0x01) /* Page 4-9 */
223 #define SWTRIGGERRED(LABPC) ((LABPC->cr_image[1]) & SWTRIG)
225 #define CR3(LABPC) ((LABPC)->base + 0x02) /* Page 4-11 */
226 #define FIFOINTEN 0x20
227 #define ERRINTEN 0x10
228 #define CNTINTEN 0x08
230 #define DIOINTEN 0x02
233 #define ALLINTEN 0x3E
234 #define FIFOINTENABLED(LABPC) ((LABPC->cr_image[2]) & FIFOINTEN)
236 #define CR4(LABPC) ((LABPC)->base + 0x0F) /* Page 4-13 */
243 /* Analog Input Register Group
245 #define ADFIFO(LABPC) ((LABPC)->base + 0x0A) /* Page 4-16 */
246 #define ADCLEAR(LABPC) ((LABPC)->base + 0x08) /* Page 4-18 */
247 #define ADSTART(LABPC) ((LABPC)->base + 0x03) /* Page 4-19 */
248 #define DMATCICLR(LABPC) ((LABPC)->base + 0x0A) /* Page 4-20 */
250 /* Analog Output Register Group
252 #define DAC0L(LABPC) ((LABPC)->base + 0x04) /* Page 4-22 */
253 #define DAC0H(LABPC) ((LABPC)->base + 0x05) /* Page 4-22 */
254 #define DAC1L(LABPC) ((LABPC)->base + 0x06) /* Page 4-22 */
255 #define DAC1H(LABPC) ((LABPC)->base + 0x07) /* Page 4-22 */
259 #define A0DATA(LABPC) ((LABPC)->base + 0x14)
260 #define A1DATA(LABPC) ((LABPC)->base + 0x15)
261 #define A2DATA(LABPC) ((LABPC)->base + 0x16)
262 #define AMODE(LABPC) ((LABPC)->base + 0x17)
264 #define TICR(LABPC) ((LABPC)->base + 0x0c)
266 #define B0DATA(LABPC) ((LABPC)->base + 0x18)
267 #define B1DATA(LABPC) ((LABPC)->base + 0x19)
268 #define B2DATA(LABPC) ((LABPC)->base + 0x1A)
269 #define BMODE(LABPC) ((LABPC)->base + 0x1B)
274 #define PORTX(LABPC, X) ((LABPC)->base + 0x10 + X)
276 #define PORTA(LABPC) PORTX(LABPC, 0)
277 #define PORTB(LABPC) PORTX(LABPC, 1)
278 #define PORTC(LABPC) PORTX(LABPC, 2)
280 #define DCR(LABPC) ((LABPC)->base + 0x13)
282 static int labpcattach(struct isa_device *dev);
283 static int labpcprobe(struct isa_device *dev);
284 struct isa_driver labpcdriver =
285 { labpcprobe, labpcattach, "labpc", 0 };
287 static d_open_t labpcopen;
288 static d_close_t labpcclose;
289 static d_ioctl_t labpcioctl;
290 static d_strategy_t labpcstrategy;
292 #define CDEV_MAJOR 66
293 static struct dev_ops labpc_ops = {
294 { "labpc", CDEV_MAJOR, 0 },
296 .d_close = labpcclose,
298 .d_write = physwrite,
299 .d_ioctl = labpcioctl,
300 .d_strategy = labpcstrategy,
303 static void labpcintr(void *);
304 static void start(struct ctlr *ctlr);
307 bp_done(struct bio *bio, int err)
309 struct buf *bp = bio->bio_buf;
311 if (err || bp->b_resid)
312 bp->b_flags |= B_ERROR;
316 static void tmo_stop(void *p);
319 done_and_start_next(struct ctlr *ctlr, struct bio *bio, int err)
321 struct buf *bp = bio->bio_buf;
323 bp->b_resid = ctlr->data_end - ctlr->data;
327 ctlr->start_queue.bio_actf = bio->bio_actf;
330 callout_stop(&ctlr->ch);
336 ad_clear(struct ctlr *ctlr)
339 loutb(ADCLEAR(ctlr), 0);
340 for (i = 0; i < 10000 && (inb(STATUS(ctlr)) & GATA0); i++)
342 (void)inb(ADFIFO(ctlr));
343 (void)inb(ADFIFO(ctlr));
346 /* reset: Reset the board following the sequence on page 5-1
349 reset(struct ctlr *ctlr)
352 CR_CLR(ctlr, 3); /* Turn off interrupts first */
359 loutb(AMODE(ctlr), 0x34);
360 loutb(A0DATA(ctlr),0x0A);
361 loutb(A0DATA(ctlr),0x00);
363 loutb(DMATCICLR(ctlr), 0x00);
364 loutb(TICR(ctlr), 0x00);
368 loutb(DAC0L(ctlr), 0);
369 loutb(DAC0H(ctlr), 0);
370 loutb(DAC1L(ctlr), 0);
371 loutb(DAC1H(ctlr), 0);
376 /* overrun: slam the start convert register and OVERRUN should get set:
379 overrun(struct ctlr *ctlr)
383 u_char status = inb(STATUS(ctlr));
384 for (i = 0; ((status & OVERRUN) == 0) && i < 100; i++)
386 loutb(ADSTART(ctlr), 1);
387 status = inb(STATUS(ctlr));
396 if (NLABPC > MAX_UNITS)
399 labpcs = kmalloc(NLABPC * sizeof(struct ctlr *), M_DEVBUF,
402 * XXX this is really odd code, adding the device only if
403 * the allocation fails? it could be broken.
412 labpcprobe(struct isa_device *dev)
415 struct ctlr scratch, *ctlr, *l;
420 if (labpcinit() == 0)
422 printf("labpcprobe: init failed\n");
429 printf("Too many LAB-PCs. Reconfigure O/S.\n");
432 ctlr = &scratch; /* Need somebody with the right base for the macros */
433 ctlr->base = dev->id_iobase;
435 /* XXX: There really isn't a perfect way to probe this board.
436 * Here is my best attempt:
440 /* After reset none of these bits should be set:
442 status = inb(STATUS(ctlr));
443 if (status & (GATA0 | OVERFLOW | DAVAIL | OVERRUN))
446 /* Now try to overrun the board FIFO and get the overrun bit set:
448 status = overrun(ctlr);
450 if ((status & OVERRUN) == 0) /* No overrun bit set? */
453 /* Assume we have a board.
457 l = kmalloc(sizeof(struct ctlr), M_DEVBUF, M_WAITOK | M_ZERO);
458 l->base = ctlr->base;
461 dev->id_unit = l->unit;
467 /* attach: Set things in a normal state.
470 labpcattach(struct isa_device *dev)
472 struct ctlr *ctlr = labpcs[dev->id_unit];
474 dev->id_intr = (inthand2_t *)labpcintr;
475 callout_init(&ctlr->ch);
476 ctlr->sample_us = (1000000.0 / (double)LABPC_DEFAULT_HERTZ) + .50;
479 ctlr->min_tmo = LABPC_MIN_TMO;
481 ctlr->dcr_val = 0x80;
483 loutb(DCR(ctlr), ctlr->dcr_val);
485 dev_ops_add(&labpc_ops, -1, dev->id_unit);
486 make_dev(&labpc_ops, dev->id_unit, 0, 0, 0600,
487 "labpc%d", dev->id_unit);
493 static void null_intr (struct ctlr *ctlr) { }
494 static void null_start(struct ctlr *ctlr, long count) { }
495 static void null_stop (struct ctlr *ctlr) { }
498 trigger(struct ctlr *ctlr)
500 CR_EXPR(ctlr, 2, |= SWTRIG);
504 ad_start(struct ctlr *ctlr, long count)
506 if (!SWTRIGGERRED(ctlr)) {
507 int chan = CHAN(ctlr->dev);
508 CR_EXPR(ctlr, 1, &= ~SCANEN);
509 CR_EXPR(ctlr, 2, &= ~TBSEL);
512 GAIN(ctlr, ctlr->gains[chan]);
515 CR_EXPR(ctlr, 1, |= SCANEN);
517 loutb(AMODE(ctlr), 0x34);
518 loutb(A0DATA(ctlr), (u_char)((ctlr->sample_us & 0xff)));
519 loutb(A0DATA(ctlr), (u_char)((ctlr->sample_us >> 8)&0xff));
520 loutb(AMODE(ctlr), 0x70);
526 ctlr->tmo = ((count + 16) * (long)ctlr->sample_us * hz) / 1000000 +
531 ad_interval_start(struct ctlr *ctlr, long count)
533 int chan = CHAN(ctlr->dev);
534 int n_frames = count / (chan + 1);
536 if (!SWTRIGGERRED(ctlr)) {
537 CR_EXPR(ctlr, 1, &= ~SCANEN);
538 CR_EXPR(ctlr, 2, &= ~TBSEL);
541 GAIN(ctlr, ctlr->gains[chan]);
543 /* XXX: Is it really possible that you clear INTSCAN as
544 * the documentation says? That seems pretty unlikely.
546 CR_EXPR(ctlr, 4, &= ~INTSCAN); /* XXX: Is this possible? */
548 /* Program the sample interval counter to run as fast as
551 loutb(AMODE(ctlr), 0x34);
552 loutb(A0DATA(ctlr), (u_char)(0x02));
553 loutb(A0DATA(ctlr), (u_char)(0x00));
554 loutb(AMODE(ctlr), 0x70);
556 /* Program the interval scanning counter to run at the sample
559 loutb(BMODE(ctlr), 0x74);
560 loutb(B1DATA(ctlr), (u_char)((ctlr->sample_us & 0xff)));
561 loutb(B1DATA(ctlr), (u_char)((ctlr->sample_us >> 8)&0xff));
562 CR_EXPR(ctlr, 1, |= SCANEN);
568 /* Each frame time takes two microseconds per channel times
569 * the number of channels being sampled plus the sample period.
571 ctlr->tmo = ((n_frames + 16) *
572 ((long)ctlr->sample_us + (chan + 1 ) * 2 ) * hz) / 1000000 +
577 all_stop(struct ctlr *ctlr)
585 struct ctlr *ctlr = (struct ctlr *)p;
592 printf("labpc?: Null ctlr struct?\n");
597 printf("labpc%d: timeout", ctlr->unit);
601 bio = ctlr->start_queue.bio_actf;
604 printf(", Null bp.\n");
611 done_and_start_next(ctlr, bio, ETIMEDOUT);
616 static void ad_intr(struct ctlr *ctlr)
620 if (ctlr->cr_image[2] == 0)
622 if (ctlr->cleared_intr)
624 ctlr->cleared_intr = 0;
628 printf("ad_intr (should not happen) interrupt with interrupts off\n");
629 printf("status %x, cr3 %x\n", inb(STATUS(ctlr)), ctlr->cr_image[2]);
633 while ( (status = (inb(STATUS(ctlr)) & (DAVAIL|OVERRUN|OVERFLOW)) ) )
635 if ((status & (OVERRUN|OVERFLOW)))
637 struct bio *bio = ctlr->start_queue.bio_actf;
639 printf("ad_intr: error: bp %p, data %p, status %x",
640 bio->bio_buf, ctlr->data, status);
642 if (status & OVERRUN)
643 printf(" Conversion overrun (multiple A-D trigger)");
645 if (status & OVERFLOW)
646 printf(" FIFO overflow");
651 done_and_start_next(ctlr, bio, EIO);
654 printf("ad_intr: (should not happen) error between records\n");
655 ctlr->err = status; /* Set overrun condition */
659 else /* FIFO interrupt */
661 struct bio *bio = ctlr->start_queue.bio_actf;
664 *ctlr->data++ = inb(ADFIFO(ctlr));
665 if (ctlr->data == ctlr->data_end) {
666 /* Normal completion */
667 done_and_start_next(ctlr, bio, 0);
671 /* Interrupt with no where to put the data. */
672 printf("ad_intr: (should not happen) dropped input.\n");
673 (void)inb(ADFIFO(ctlr));
675 printf("bp %p, status %x, cr3 %x\n",
676 bio->bio_buf, status, ctlr->cr_image[2]);
677 ctlr->err = DROPPED_INPUT;
688 struct ctlr *ctlr = labpcs[unit];
692 /* lockout_multiple_opens: Return whether or not we can open again, or
693 * if the new mode is inconsistent with an already opened mode.
694 * We only permit multiple opens for digital I/O now.
698 lockout_multiple_open(dev_t current, dev_t next)
700 return ! (DIGITAL(current) && DIGITAL(next));
704 labpcopen(struct dev_open_args *ap)
706 dev_t dev = ap->a_head.a_dev;
707 u_short unit = UNIT(dev);
711 if (unit >= MAX_UNITS)
719 /* Don't allow another open if we have to change modes.
722 if ( (ctlr->flags & BUSY) == 0)
731 ctlr->intr = null_intr;
732 ctlr->starter = null_start;
733 ctlr->stop = null_stop;
735 else if (lockout_multiple_open(ctlr->dev, dev))
742 labpcclose(struct dev_close_args *ap)
744 dev_t dev = ap->a_head.a_dev;
745 struct ctlr *ctlr = labpcs[UNIT(dev)];
749 ctlr->flags &= ~BUSY;
755 * Start: Start a frame going in or out.
758 start(struct ctlr *ctlr)
763 if ((bio = ctlr->start_queue.bio_actf) == NULL) {
764 /* We must turn off FIFO interrupts when there is no
765 * place to put the data. We have to get back to
766 * reading before the FIFO overflows.
768 CR_EXPR(ctlr, 3, &= ~(FIFOINTEN|ERRINTEN));
769 ctlr->cleared_intr = 1;
775 ctlr->data = (u_char *)bp->b_data;
776 ctlr->data_end = ctlr->data + bp->b_bcount;
780 printf("labpc start: (should not happen) error between records.\n");
781 done_and_start_next(ctlr, bio, EIO);
787 printf("labpc start: (should not happen) NULL data pointer.\n");
788 done_and_start_next(ctlr, bio, EIO);
792 (*ctlr->starter)(ctlr, bp->b_bcount);
794 if (!FIFOINTENABLED(ctlr)) /* We can store the data again */
796 CR_EXPR(ctlr, 3, |= (FIFOINTEN|ERRINTEN));
798 /* Don't wait for the interrupts to fill things up.
803 callout_reset(&ctlr->ch, ctlr->tmo, tmo_stop, ctlr);
807 ad_strategy(struct bio *bio, struct ctlr *ctlr)
810 bio->bio_actf = NULL;
813 ctlr->last->bio_actf = bio;
817 ctlr->start_queue.bio_actf = bio;
824 /* da_strategy: Send data to the D-A. The CHAN field should be
827 * 2: Alternate port 0 then port 1
831 * 1. There is no state for CHAN field 2:
832 * the first sample in each buffer goes to channel 0.
834 * 2. No interrupt support yet.
837 da_strategy(struct bio *bio, struct ctlr *ctlr)
839 struct buf *bp = bio->bio_buf;
840 dev_t dev = bio->bio_driver_info;
856 case 2: /* Device 2 handles both ports interleaved. */
857 if (bp->b_bcount <= 2)
863 len = bp->b_bcount / 2;
864 data = (u_char *)bp->b_data;
866 for (i = 0; i < len; i++)
868 loutb(DAC0H(ctlr), *data++);
869 loutb(DAC0L(ctlr), *data++);
870 loutb(DAC1H(ctlr), *data++);
871 loutb(DAC1L(ctlr), *data++);
874 bp->b_resid = bp->b_bcount & 3;
883 /* Port 0 or 1 falls through to here.
885 if (bp->b_bcount & 1) /* Odd transfers are illegal */
889 data = (u_char *)bp->b_data;
891 for (i = 0; i < len; i++)
893 loutb(port + 1, *data++);
894 loutb(port, *data++);
902 /* Input masks for MODE 0 of the ports treating PC as a single
903 * 8 bit port. Set these bits to set the port to input.
905 /* A B lowc highc combined */
906 static u_char set_input[] = { 0x10, 0x02, 0x01, 0x08, 0x09 };
908 static void flush_dcr(struct ctlr *ctlr)
910 if (ctlr->dcr_is != ctlr->dcr_val)
912 loutb(DCR(ctlr), ctlr->dcr_val);
913 ctlr->dcr_is = ctlr->dcr_val;
917 /* do: Digital output
920 digital_out_strategy(struct bio *bio, struct ctlr *ctlr)
922 struct buf *bp = bio->bio_buf;
923 dev_t dev = bio->bio_driver_info;
928 int chan = CHAN(dev);
930 ctlr->dcr_val &= ~set_input[chan]; /* Digital out: Clear bit */
933 port = PORTX(ctlr, chan);
936 data = (u_char *)bp->b_data;
938 for (i = 0; i < len; i++)
940 loutb(port, *data++);
948 /* digital_in_strategy: Digital input
951 digital_in_strategy(struct bio *bio, struct ctlr *ctlr)
953 struct buf *bp = bio->bio_buf;
954 dev_t dev = bio->bio_driver_info;
959 int chan = CHAN(dev);
961 ctlr->dcr_val |= set_input[chan]; /* Digital in: Set bit */
963 port = PORTX(ctlr, chan);
966 data = (u_char *)bp->b_data;
968 for (i = 0; i < len; i++)
980 labpcstrategy(struct dev_strategy_args *ap)
982 dev_t dev = ap->a_head.a_dev;
983 struct bio *bio = ap->a_bio;
984 struct buf *bp = bio->bio_buf;
985 struct ctlr *ctlr = labpcs[UNIT(dev)];
987 bio->bio_driver_info = dev;
990 if (bp->b_cmd == BUF_CMD_READ) {
991 ctlr->starter = null_start;
992 ctlr->stop = all_stop;
993 ctlr->intr = null_intr;
994 digital_in_strategy(bio, ctlr);
998 ctlr->starter = null_start;
999 ctlr->stop = all_stop;
1000 ctlr->intr = null_intr;
1001 digital_out_strategy(bio, ctlr);
1005 if (bp->b_cmd == BUF_CMD_READ) {
1007 ctlr->starter = INTERVAL(ctlr->dev) ? ad_interval_start : ad_start;
1008 ctlr->stop = all_stop;
1009 ctlr->intr = ad_intr;
1010 ad_strategy(bio, ctlr);
1014 ctlr->starter = null_start;
1015 ctlr->stop = all_stop;
1016 ctlr->intr = null_intr;
1017 da_strategy(bio, ctlr);
1024 labpcioctl(struct dev_ioctl_args *ap)
1026 dev_t dev = ap->a_head.a_dev;
1027 caddr_t arg = ap->a_data;
1028 struct ctlr *ctlr = labpcs[UNIT(dev)];
1032 case AD_MICRO_PERIOD_SET:
1034 /* XXX I'm only supporting what I have to, which is
1035 * no slow periods. You can't get any slower than 15 Hz
1036 * with the current setup. To go slower you'll need to
1037 * support TCINTEN in CR3.
1040 long sample_us = *(long *)arg;
1042 if (sample_us > 65535)
1045 ctlr->sample_us = sample_us;
1049 case AD_MICRO_PERIOD_GET:
1050 *(long *)arg = ctlr->sample_us;
1061 case AD_SUPPORTED_GAINS:
1063 static double gains[] = {1., 1.25, 2., 5., 10., 20., 50., 100.};
1064 copyout(gains, *(caddr_t *)arg, sizeof(gains));
1071 copyin(*(caddr_t *)arg, ctlr->gains, sizeof(ctlr->gains));
1077 copyout(ctlr->gains, *(caddr_t *)arg, sizeof(ctlr->gains));