2 * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer,
10 * without modification.
11 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
12 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
13 * redistribution must be conditioned upon including a substantially
14 * similar Disclaimer requirement for further binary redistribution.
15 * 3. Neither the names of the above-listed copyright holders nor the names
16 * of any contributors may be used to endorse or promote products derived
17 * from this software without specific prior written permission.
19 * Alternatively, this software may be distributed under the terms of the
20 * GNU General Public License ("GPL") version 2 as published by the Free
21 * Software Foundation.
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
26 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
27 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
28 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
29 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
32 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
34 * THE POSSIBILITY OF SUCH DAMAGES.
36 * $FreeBSD: src/sys/dev/ath/if_ath.c,v 1.94.2.17 2006/04/19 16:14:47 sam Exp $
37 * $DragonFly: src/sys/dev/netif/ath/ath/if_ath.c,v 1.3 2006/09/05 00:55:39 dillon Exp $
41 * Driver for the Atheros Wireless LAN controller.
43 * This software is derived from work of Atsushi Onoe; his contribution
44 * is greatly appreciated.
49 #include <sys/param.h>
50 #include <sys/systm.h>
51 #include <sys/sysctl.h>
53 #include <sys/malloc.h>
54 #include <sys/kernel.h>
55 #include <sys/socket.h>
56 #include <sys/sockio.h>
57 #include <sys/errno.h>
58 #include <sys/callout.h>
60 #include <sys/endian.h>
61 #include <sys/kthread.h>
62 #include <sys/serialize.h>
64 #include <machine/bus.h>
65 #include <machine/resource.h>
70 #include <net/if_dl.h>
71 #include <net/if_media.h>
72 #include <net/if_types.h>
73 #include <net/if_arp.h>
74 #include <net/ethernet.h>
75 #include <net/if_llc.h>
76 #include <net/ifq_var.h>
78 #include <netproto/802_11/ieee80211_var.h>
84 #include <dev/netif/ath/ath/if_athvar.h>
85 #include <contrib/dev/ath/ah_desc.h>
86 #include <contrib/dev/ath/ah_devid.h> /* XXX for softled */
88 /* unaligned little endian access */
89 #define LE_READ_2(p) \
91 ((((uint8_t *)(p))[0] ) | (((uint8_t *)(p))[1] << 8)))
92 #define LE_READ_4(p) \
94 ((((uint8_t *)(p))[0] ) | (((uint8_t *)(p))[1] << 8) | \
95 (((uint8_t *)(p))[2] << 16) | (((uint8_t *)(p))[3] << 24)))
103 static void ath_init(void *);
104 static void ath_stop_no_pwchg(struct ifnet *);
105 static void ath_stop(struct ifnet *);
106 static void ath_start(struct ifnet *);
107 static int ath_reset(struct ifnet *);
108 static int ath_media_change(struct ifnet *);
109 static void ath_watchdog(struct ifnet *);
110 static int ath_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
111 static void ath_fatal_proc(struct ath_softc *);
112 static void ath_rxorn_proc(struct ath_softc *);
113 static void ath_bmiss_proc(struct ath_softc *);
114 static void ath_radar_proc(struct ath_softc *);
115 static int ath_key_alloc(struct ieee80211com *,
116 const struct ieee80211_key *,
117 ieee80211_keyix *, ieee80211_keyix *);
118 static int ath_key_delete(struct ieee80211com *,
119 const struct ieee80211_key *);
120 static int ath_key_set(struct ieee80211com *, const struct ieee80211_key *,
121 const uint8_t mac[IEEE80211_ADDR_LEN]);
122 static void ath_key_update_begin(struct ieee80211com *);
123 static void ath_key_update_end(struct ieee80211com *);
124 static void ath_mode_init(struct ath_softc *);
125 static void ath_setslottime(struct ath_softc *);
126 static void ath_updateslot(struct ifnet *);
127 static int ath_beaconq_setup(struct ath_hal *);
128 static int ath_beacon_alloc(struct ath_softc *, struct ieee80211_node *);
129 static void ath_beacon_setup(struct ath_softc *, struct ath_buf *);
130 static void ath_beacon_proc(struct ath_softc *);
131 static void ath_bstuck_proc(struct ath_softc *);
132 static void ath_beacon_free(struct ath_softc *);
133 static void ath_beacon_config(struct ath_softc *);
134 static void ath_descdma_cleanup(struct ath_softc *sc,
135 struct ath_descdma *, ath_bufhead *);
136 static int ath_desc_alloc(struct ath_softc *);
137 static void ath_desc_free(struct ath_softc *);
138 static struct ieee80211_node *ath_node_alloc(struct ieee80211_node_table *);
139 static void ath_node_free(struct ieee80211_node *);
140 static uint8_t ath_node_getrssi(const struct ieee80211_node *);
141 static int ath_rxbuf_init(struct ath_softc *, struct ath_buf *);
142 static void ath_recv_mgmt(struct ieee80211com *ic, struct mbuf *m,
143 struct ieee80211_node *ni,
144 int subtype, int rssi, uint32_t rstamp);
145 static void ath_setdefantenna(struct ath_softc *, u_int);
146 static void ath_rx_proc(struct ath_softc *);
147 static struct ath_txq *ath_txq_setup(struct ath_softc*, int qtype, int subtype);
148 static int ath_tx_setup(struct ath_softc *, int, int);
149 static int ath_wme_update(struct ieee80211com *);
150 static void ath_tx_cleanupq(struct ath_softc *, struct ath_txq *);
151 static void ath_tx_cleanup(struct ath_softc *);
152 static int ath_tx_start(struct ath_softc *, struct ieee80211_node *,
153 struct ath_buf *, struct mbuf *);
154 static void ath_tx_proc_q0(struct ath_softc *);
155 static void ath_tx_proc_q0123(struct ath_softc *);
156 static void ath_tx_proc(struct ath_softc *);
157 static int ath_chan_set(struct ath_softc *, struct ieee80211_channel *);
158 static void ath_draintxq(struct ath_softc *);
159 static void ath_stoprecv(struct ath_softc *);
160 static int ath_startrecv(struct ath_softc *);
161 static void ath_chan_change(struct ath_softc *, struct ieee80211_channel *);
162 static void ath_next_scan(void *);
163 static void ath_calibrate(void *);
164 static int ath_newstate(struct ieee80211com *, enum ieee80211_state, int);
165 static void ath_setup_stationkey(struct ieee80211_node *);
166 static void ath_newassoc(struct ieee80211_node *, int);
167 static int ath_getchannels(struct ath_softc *, u_int cc,
168 HAL_BOOL outdoor, HAL_BOOL xchanmode);
169 static void ath_led_event(struct ath_softc *, int);
170 static void ath_update_txpow(struct ath_softc *);
172 static int ath_rate_setup(struct ath_softc *, u_int mode);
173 static void ath_setcurmode(struct ath_softc *, enum ieee80211_phymode);
175 static void ath_sysctlattach(struct ath_softc *);
176 static void ath_bpfattach(struct ath_softc *);
177 static void ath_announce(struct ath_softc *);
179 static void ath_dma_map_mbuf(void *, bus_dma_segment_t *, int, bus_size_t,
182 SYSCTL_DECL(_hw_ath);
184 /* XXX validate sysctl values */
185 static int ath_dwelltime = 200; /* 5 channels/second */
186 SYSCTL_INT(_hw_ath, OID_AUTO, dwell, CTLFLAG_RW, &ath_dwelltime,
187 0, "channel dwell time (ms) for AP/station scanning");
188 static int ath_calinterval = 30; /* calibrate every 30 secs */
189 SYSCTL_INT(_hw_ath, OID_AUTO, calibrate, CTLFLAG_RW, &ath_calinterval,
190 0, "chip calibration interval (secs)");
191 static int ath_outdoor = AH_TRUE; /* outdoor operation */
192 SYSCTL_INT(_hw_ath, OID_AUTO, outdoor, CTLFLAG_RD, &ath_outdoor,
193 0, "outdoor operation");
194 TUNABLE_INT("hw.ath.outdoor", &ath_outdoor);
195 static int ath_xchanmode = AH_TRUE; /* extended channel use */
196 SYSCTL_INT(_hw_ath, OID_AUTO, xchanmode, CTLFLAG_RD, &ath_xchanmode,
197 0, "extended channel mode");
198 TUNABLE_INT("hw.ath.xchanmode", &ath_xchanmode);
199 static int ath_countrycode = CTRY_DEFAULT; /* country code */
200 SYSCTL_INT(_hw_ath, OID_AUTO, countrycode, CTLFLAG_RD, &ath_countrycode,
202 TUNABLE_INT("hw.ath.countrycode", &ath_countrycode);
203 static int ath_regdomain = 0; /* regulatory domain */
204 SYSCTL_INT(_hw_ath, OID_AUTO, regdomain, CTLFLAG_RD, &ath_regdomain,
205 0, "regulatory domain");
207 static int ath_rxbuf = ATH_RXBUF; /* # rx buffers to allocate */
208 SYSCTL_INT(_hw_ath, OID_AUTO, rxbuf, CTLFLAG_RD, &ath_rxbuf,
209 0, "rx buffers allocated");
210 TUNABLE_INT("hw.ath.rxbuf", &ath_rxbuf);
211 static int ath_txbuf = ATH_TXBUF; /* # tx buffers to allocate */
212 SYSCTL_INT(_hw_ath, OID_AUTO, txbuf, CTLFLAG_RD, &ath_txbuf,
213 0, "tx buffers allocated");
214 TUNABLE_INT("hw.ath.txbuf", &ath_txbuf);
217 static int ath_debug = 0;
218 SYSCTL_INT(_hw_ath, OID_AUTO, debug, CTLFLAG_RW, &ath_debug,
219 0, "control debugging printfs");
220 TUNABLE_INT("hw.ath.debug", &ath_debug);
222 ATH_DEBUG_XMIT = 0x00000001, /* basic xmit operation */
223 ATH_DEBUG_XMIT_DESC = 0x00000002, /* xmit descriptors */
224 ATH_DEBUG_RECV = 0x00000004, /* basic recv operation */
225 ATH_DEBUG_RECV_DESC = 0x00000008, /* recv descriptors */
226 ATH_DEBUG_RATE = 0x00000010, /* rate control */
227 ATH_DEBUG_RESET = 0x00000020, /* reset processing */
228 ATH_DEBUG_MODE = 0x00000040, /* mode init/setup */
229 ATH_DEBUG_BEACON = 0x00000080, /* beacon handling */
230 ATH_DEBUG_WATCHDOG = 0x00000100, /* watchdog timeout */
231 ATH_DEBUG_INTR = 0x00001000, /* ISR */
232 ATH_DEBUG_TX_PROC = 0x00002000, /* tx ISR proc */
233 ATH_DEBUG_RX_PROC = 0x00004000, /* rx ISR proc */
234 ATH_DEBUG_BEACON_PROC = 0x00008000, /* beacon ISR proc */
235 ATH_DEBUG_CALIBRATE = 0x00010000, /* periodic calibration */
236 ATH_DEBUG_KEYCACHE = 0x00020000, /* key cache management */
237 ATH_DEBUG_STATE = 0x00040000, /* 802.11 state transitions */
238 ATH_DEBUG_NODE = 0x00080000, /* node management */
239 ATH_DEBUG_LED = 0x00100000, /* led management */
240 ATH_DEBUG_FF = 0x00200000, /* fast frames */
241 ATH_DEBUG_DFS = 0x00400000, /* DFS processing */
242 ATH_DEBUG_FATAL = 0x80000000, /* fatal errors */
243 ATH_DEBUG_ANY = 0xffffffff
245 #define IFF_DUMPPKTS(sc, m) \
246 ((sc->sc_debug & (m)) || \
247 (sc->sc_ic.ic_if.if_flags & (IFF_DEBUG|IFF_LINK2)) == (IFF_DEBUG|IFF_LINK2))
248 #define DPRINTF(sc, m, fmt, ...) do { \
249 if (sc->sc_debug & (m)) \
250 printf(fmt, __VA_ARGS__); \
252 #define KEYPRINTF(sc, ix, hk, mac) do { \
253 if (sc->sc_debug & ATH_DEBUG_KEYCACHE) \
254 ath_keyprint(__func__, ix, hk, mac); \
256 static void ath_printrxbuf(struct ath_buf *bf, u_int ix, int);
257 static void ath_printtxbuf(struct ath_buf *bf, u_int qnum, u_int ix, int done);
259 #define IFF_DUMPPKTS(sc, m) \
260 ((sc->sc_ic.ic_if.if_flags & (IFF_DEBUG|IFF_LINK2)) == (IFF_DEBUG|IFF_LINK2))
261 #define DPRINTF(sc, m, fmt, ...) do { \
264 #define KEYPRINTF(sc, k, ix, mac) do { \
269 MALLOC_DEFINE(M_ATHDEV, "athdev", "ath driver dma buffers");
272 ath_attach(uint16_t devid, struct ath_softc *sc)
274 struct ieee80211com *ic = &sc->sc_ic;
275 struct ifnet *ifp = &ic->ic_if;
276 struct ath_hal *ah = NULL;
280 DPRINTF(sc, ATH_DEBUG_ANY, "%s: devid 0x%x\n", __func__, devid);
282 /* set these up early for if_printf use */
283 if_initname(ifp, device_get_name(sc->sc_dev),
284 device_get_unit(sc->sc_dev));
287 * Mark device invalid so any interrupts (shared or otherwise)
288 * that arrive before the HAL is setup are discarded.
293 * Arrange interrupt line.
296 sc->sc_irq = bus_alloc_resource_any(sc->sc_dev, SYS_RES_IRQ,
298 RF_SHAREABLE | RF_ACTIVE);
299 if (sc->sc_irq == NULL) {
300 if_printf(ifp, "could not map interrupt\n");
304 sysctl_ctx_init(&sc->sc_sysctl_ctx);
305 sc->sc_sysctl_tree = SYSCTL_ADD_NODE(&sc->sc_sysctl_ctx,
306 SYSCTL_STATIC_CHILDREN(_hw),
308 device_get_nameunit(sc->sc_dev),
310 if (sc->sc_sysctl_tree == NULL) {
311 if_printf(ifp, "could not add sysctl node\n");
316 ah = ath_hal_attach(devid, sc, sc->sc_st, sc->sc_sh, &status);
318 if_printf(ifp, "unable to attach hardware; HAL status %u\n",
325 if (ah->ah_abi != HAL_ABI_VERSION) {
326 if_printf(ifp, "HAL ABI mismatch detected "
327 "(HAL:0x%x != driver:0x%x)\n",
328 ah->ah_abi, HAL_ABI_VERSION);
332 sc->sc_invalid = 0; /* ready to go, enable interrupt handling */
335 * Check if the MAC has multi-rate retry support.
336 * We do this by trying to setup a fake extended
337 * descriptor. MAC's that don't have support will
338 * return false w/o doing anything. MAC's that do
339 * support it will return true w/o doing anything.
341 sc->sc_mrretry = ath_hal_setupxtxdesc(ah, NULL, 0,0, 0,0, 0,0);
344 * Check if the device has hardware counters for PHY
345 * errors. If so we need to enable the MIB interrupt
346 * so we can act on stat triggers.
348 if (ath_hal_hwphycounters(ah))
352 * Get the hardware key cache size.
354 sc->sc_keymax = ath_hal_keycachesize(ah);
355 if (sc->sc_keymax > ATH_KEYMAX) {
356 if_printf(ifp, "Warning, using only %u of %u key cache slots\n",
357 ATH_KEYMAX, sc->sc_keymax);
358 sc->sc_keymax = ATH_KEYMAX;
361 * Reset the key cache since some parts do not
362 * reset the contents on initial power up.
364 for (i = 0; i < sc->sc_keymax; i++)
365 ath_hal_keyreset(ah, i);
367 * Mark key cache slots associated with global keys
368 * as in use. If we knew TKIP was not to be used we
369 * could leave the +32, +64, and +32+64 slots free.
370 * XXX only for splitmic.
372 for (i = 0; i < IEEE80211_WEP_NKID; i++) {
373 setbit(sc->sc_keymap, i);
374 setbit(sc->sc_keymap, i+32);
375 setbit(sc->sc_keymap, i+64);
376 setbit(sc->sc_keymap, i+32+64);
380 * Collect the channel list using the default country
381 * code and including outdoor channels. The 802.11 layer
382 * is resposible for filtering this list based on settings
385 error = ath_getchannels(sc, ath_countrycode,
386 ath_outdoor, ath_xchanmode);
391 * Setup rate tables for all potential media types.
393 ath_rate_setup(sc, IEEE80211_MODE_11A);
394 ath_rate_setup(sc, IEEE80211_MODE_11B);
395 ath_rate_setup(sc, IEEE80211_MODE_11G);
396 ath_rate_setup(sc, IEEE80211_MODE_TURBO_A);
397 ath_rate_setup(sc, IEEE80211_MODE_TURBO_G);
399 /* NB: setup here so ath_rate_update is happy */
400 ath_setcurmode(sc, IEEE80211_MODE_11A);
403 * Allocate tx+rx descriptors and populate the lists.
405 error = ath_desc_alloc(sc);
407 if_printf(ifp, "failed to allocate descriptors: %d\n", error);
411 callout_init(&sc->sc_scan_ch);
412 callout_init(&sc->sc_cal_ch);
413 callout_init(&sc->sc_dfs_ch);
416 * Allocate hardware transmit queues: one queue for
417 * beacon frames and one data queue for each QoS
418 * priority. Note that the hal handles reseting
419 * these queues at the needed time.
423 sc->sc_bhalq = ath_beaconq_setup(ah);
424 if (sc->sc_bhalq == (u_int)-1) {
425 if_printf(ifp, "unable to setup a beacon xmit queue!\n");
430 sc->sc_cabq = ath_txq_setup(sc, HAL_TX_QUEUE_CAB, 0);
431 if (sc->sc_cabq == NULL) {
432 if_printf(ifp, "unable to setup CAB xmit queue!\n");
437 /* NB: insure BK queue is the lowest priority h/w queue */
438 if (!ath_tx_setup(sc, WME_AC_BK, HAL_WME_AC_BK)) {
439 if_printf(ifp, "unable to setup xmit queue for %s traffic!\n",
440 ieee80211_wme_acnames[WME_AC_BK]);
444 if (!ath_tx_setup(sc, WME_AC_BE, HAL_WME_AC_BE) ||
445 !ath_tx_setup(sc, WME_AC_VI, HAL_WME_AC_VI) ||
446 !ath_tx_setup(sc, WME_AC_VO, HAL_WME_AC_VO)) {
448 * Not enough hardware tx queues to properly do WME;
449 * just punt and assign them all to the same h/w queue.
450 * We could do a better job of this if, for example,
451 * we allocate queues when we switch from station to
454 if (sc->sc_ac2q[WME_AC_VI] != NULL)
455 ath_tx_cleanupq(sc, sc->sc_ac2q[WME_AC_VI]);
456 if (sc->sc_ac2q[WME_AC_BE] != NULL)
457 ath_tx_cleanupq(sc, sc->sc_ac2q[WME_AC_BE]);
458 sc->sc_ac2q[WME_AC_BE] = sc->sc_ac2q[WME_AC_BK];
459 sc->sc_ac2q[WME_AC_VI] = sc->sc_ac2q[WME_AC_BK];
460 sc->sc_ac2q[WME_AC_VO] = sc->sc_ac2q[WME_AC_BK];
464 * Special case certain configurations. Note the
465 * CAB queue is handled by these specially so don't
466 * include them when checking the txq setup mask.
468 switch (sc->sc_txqsetup &~ (1<<sc->sc_cabq->axq_qnum)) {
470 sc->sc_tx_proc = ath_tx_proc_q0;
471 if_printf(ifp, "tx_proc_q0\n");
474 sc->sc_tx_proc = ath_tx_proc_q0123;
475 if_printf(ifp, "tx_proc_q0123\n");
478 sc->sc_tx_proc = ath_tx_proc;
479 if_printf(ifp, "tx_proc\n");
484 * Setup rate control. Some rate control modules
485 * call back to change the anntena state so expose
486 * the necessary entry points.
487 * XXX maybe belongs in struct ath_ratectrl?
489 sc->sc_setdefantenna = ath_setdefantenna;
490 sc->sc_rc = ath_rate_attach(sc);
491 if (sc->sc_rc == NULL) {
498 sc->sc_ledon = 0; /* low true */
499 sc->sc_ledidle = (2700 * hz) / 1000; /* 2.7sec */
500 callout_init(&sc->sc_ledtimer);
503 * Auto-enable soft led processing for IBM cards and for
504 * 5211 minipci cards. Users can also manually enable/disable
505 * support with a sysctl.
507 sc->sc_softled = (devid == AR5212_DEVID_IBM || devid == AR5211_DEVID);
508 if (sc->sc_softled) {
509 ath_hal_gpioCfgOutput(ah, sc->sc_ledpin);
510 ath_hal_gpioset(ah, sc->sc_ledpin, !sc->sc_ledon);
514 ifp->if_flags = IFF_SIMPLEX | IFF_BROADCAST | IFF_MULTICAST;
515 ifp->if_start = ath_start;
516 ifp->if_watchdog = ath_watchdog;
517 ifp->if_ioctl = ath_ioctl;
518 ifp->if_init = ath_init;
519 ifq_set_maxlen(&ifp->if_snd, IFQ_MAXLEN);
520 ifq_set_ready(&ifp->if_snd);
522 ic->ic_reset = ath_reset;
523 ic->ic_newassoc = ath_newassoc;
524 ic->ic_updateslot = ath_updateslot;
525 ic->ic_wme.wme_update = ath_wme_update;
526 /* XXX not right but it's not used anywhere important */
527 ic->ic_phytype = IEEE80211_T_OFDM;
528 ic->ic_opmode = IEEE80211_M_STA;
530 IEEE80211_C_IBSS /* ibss, nee adhoc, mode */
531 | IEEE80211_C_HOSTAP /* hostap mode */
532 | IEEE80211_C_MONITOR /* monitor mode */
533 | IEEE80211_C_AHDEMO /* adhoc demo mode */
534 | IEEE80211_C_SHPREAMBLE /* short preamble supported */
535 | IEEE80211_C_SHSLOT /* short slot time supported */
536 | IEEE80211_C_WPA /* capable of WPA1+WPA2 */
539 * Query the hal to figure out h/w crypto support.
541 if (ath_hal_ciphersupported(ah, HAL_CIPHER_WEP))
542 ic->ic_caps |= IEEE80211_C_WEP;
543 if (ath_hal_ciphersupported(ah, HAL_CIPHER_AES_OCB))
544 ic->ic_caps |= IEEE80211_C_AES;
545 if (ath_hal_ciphersupported(ah, HAL_CIPHER_AES_CCM))
546 ic->ic_caps |= IEEE80211_C_AES_CCM;
547 if (ath_hal_ciphersupported(ah, HAL_CIPHER_CKIP))
548 ic->ic_caps |= IEEE80211_C_CKIP;
549 if (ath_hal_ciphersupported(ah, HAL_CIPHER_TKIP)) {
550 ic->ic_caps |= IEEE80211_C_TKIP;
552 * Check if h/w does the MIC and/or whether the
553 * separate key cache entries are required to
554 * handle both tx+rx MIC keys.
556 if (ath_hal_ciphersupported(ah, HAL_CIPHER_MIC))
557 ic->ic_caps |= IEEE80211_C_TKIPMIC;
558 if (ath_hal_tkipsplit(ah))
561 sc->sc_hasclrkey = ath_hal_ciphersupported(ah, HAL_CIPHER_CLR);
562 sc->sc_mcastkey = ath_hal_getmcastkeysearch(ah);
564 * TPC support can be done either with a global cap or
565 * per-packet support. The latter is not available on
566 * all parts. We're a bit pedantic here as all parts
567 * support a global cap.
569 if (ath_hal_hastpc(ah) || ath_hal_hastxpowlimit(ah))
570 ic->ic_caps |= IEEE80211_C_TXPMGT;
573 * Mark WME capability only if we have sufficient
574 * hardware queues to do proper priority scheduling.
576 if (sc->sc_ac2q[WME_AC_BE] != sc->sc_ac2q[WME_AC_BK])
577 ic->ic_caps |= IEEE80211_C_WME;
579 * Check for misc other capabilities.
581 if (ath_hal_hasbursting(ah))
582 ic->ic_caps |= IEEE80211_C_BURST;
585 * Indicate we need the 802.11 header padded to a
586 * 32-bit boundary for 4-address and QoS frames.
588 ic->ic_flags |= IEEE80211_F_DATAPAD;
591 * Query the hal about antenna support.
593 sc->sc_defant = ath_hal_getdefantenna(ah);
596 * Not all chips have the VEOL support we want to
597 * use with IBSS beacons; check here for it.
599 sc->sc_hasveol = ath_hal_hasveol(ah);
601 /* get mac address from hardware */
602 ath_hal_getmac(ah, ic->ic_myaddr);
604 /* call MI attach routine. */
605 ieee80211_ifattach(ic);
606 sc->sc_opmode = ic->ic_opmode;
607 /* override default methods */
608 ic->ic_node_alloc = ath_node_alloc;
609 sc->sc_node_free = ic->ic_node_free;
610 ic->ic_node_free = ath_node_free;
611 ic->ic_node_getrssi = ath_node_getrssi;
612 sc->sc_recv_mgmt = ic->ic_recv_mgmt;
613 ic->ic_recv_mgmt = ath_recv_mgmt;
614 sc->sc_newstate = ic->ic_newstate;
615 ic->ic_newstate = ath_newstate;
616 ic->ic_crypto.cs_max_keyix = sc->sc_keymax;
617 ic->ic_crypto.cs_key_alloc = ath_key_alloc;
618 ic->ic_crypto.cs_key_delete = ath_key_delete;
619 ic->ic_crypto.cs_key_set = ath_key_set;
620 ic->ic_crypto.cs_key_update_begin = ath_key_update_begin;
621 ic->ic_crypto.cs_key_update_end = ath_key_update_end;
622 /* complete initialization */
623 ieee80211_media_init(ic, ath_media_change, ieee80211_media_status);
627 * Setup dynamic sysctl's now that country code and
628 * regdomain are available from the hal.
630 ath_sysctlattach(sc);
632 error = bus_setup_intr(sc->sc_dev, sc->sc_irq, INTR_MPSAFE, ath_intr,
633 sc, &sc->sc_ih, ifp->if_serializer);
635 if_printf(ifp, "could not establish interrupt\n");
637 ieee80211_ifdetach(ic);
642 ieee80211_announce(ic);
652 ath_detach(struct ath_softc *sc)
654 struct ifnet *ifp = &sc->sc_ic.ic_if;
656 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags %x\n",
657 __func__, ifp->if_flags);
660 * NB: the order of these is important:
661 * o call the 802.11 layer before detaching the hal to
662 * insure callbacks into the driver to delete global
663 * key cache entries can be handled
664 * o reclaim the tx queue data structures after calling
665 * the 802.11 layer as we'll get called back to reclaim
666 * node state and potentially want to use them
667 * o to cleanup the tx queues the hal is called, so detach
669 * Other than that, it's straightforward...
672 if (device_is_attached(sc->sc_dev)) {
673 lwkt_serialize_enter(ifp->if_serializer);
675 ath_rate_stop(sc->sc_rc);
678 * It seems power changing in ath_stop() will freeze
679 * ath_hal_releasetxqueue(), which is called by
680 * ath_tx_cleanup() below.
683 ath_stop_no_pwchg(ifp);
687 bus_teardown_intr(sc->sc_dev, sc->sc_irq, sc->sc_ih);
689 lwkt_serialize_exit(ifp->if_serializer);
692 ieee80211_ifdetach(&sc->sc_ic);
695 if (sc->sc_rc != NULL)
696 ath_rate_detach(sc->sc_rc);
703 ath_hal_detach(sc->sc_ah);
705 if (sc->sc_irq != NULL) {
706 bus_release_resource(sc->sc_dev, SYS_RES_IRQ, sc->sc_irq_rid,
710 if (sc->sc_sysctl_tree != NULL)
711 sysctl_ctx_free(&sc->sc_sysctl_ctx);
717 ath_suspend(struct ath_softc *sc)
719 struct ifnet *ifp = &sc->sc_ic.ic_if;
721 lwkt_serialize_enter(ifp->if_serializer);
723 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags %x\n",
724 __func__, ifp->if_flags);
727 lwkt_serialize_exit(ifp->if_serializer);
731 ath_resume(struct ath_softc *sc)
733 struct ifnet *ifp = &sc->sc_ic.ic_if;
735 lwkt_serialize_enter(ifp->if_serializer);
737 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags %x\n",
738 __func__, ifp->if_flags);
740 if (ifp->if_flags & IFF_UP) {
742 if (ifp->if_flags & IFF_RUNNING)
745 if (sc->sc_softled) {
746 ath_hal_gpioCfgOutput(sc->sc_ah, sc->sc_ledpin);
747 ath_hal_gpioset(sc->sc_ah, sc->sc_ledpin, !sc->sc_ledon);
750 lwkt_serialize_exit(ifp->if_serializer);
754 ath_shutdown(struct ath_softc *sc)
756 struct ifnet *ifp = &sc->sc_ic.ic_if;
758 lwkt_serialize_enter(ifp->if_serializer);
760 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags %x\n",
761 __func__, ifp->if_flags);
764 lwkt_serialize_exit(ifp->if_serializer);
768 * Interrupt handler. Most of the actual processing is deferred.
773 struct ath_softc *sc = arg;
774 struct ifnet *ifp = &sc->sc_ic.ic_if;
775 struct ath_hal *ah = sc->sc_ah;
778 if (sc->sc_invalid) {
780 * The hardware is not ready/present, don't touch anything.
781 * Note this can happen early on if the IRQ is shared.
783 DPRINTF(sc, ATH_DEBUG_ANY, "%s: invalid; ignored\n", __func__);
786 if (!ath_hal_intrpend(ah)) /* shared irq, not for us */
788 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) !=
789 (IFF_UP | IFF_RUNNING)) {
790 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags 0x%x\n",
791 __func__, ifp->if_flags);
792 ath_hal_getisr(ah, &status); /* clear ISR */
793 ath_hal_intrset(ah, 0); /* disable further intr's */
797 * Figure out the reason(s) for the interrupt. Note
798 * that the hal returns a pseudo-ISR that may include
799 * bits we haven't explicitly enabled so we mask the
800 * value to insure we only process bits we requested.
802 ath_hal_getisr(ah, &status); /* NB: clears ISR too */
803 DPRINTF(sc, ATH_DEBUG_INTR, "%s: status 0x%x\n", __func__, status);
804 status &= sc->sc_imask; /* discard unasked for bits */
805 if (status & HAL_INT_FATAL) {
807 * Fatal errors are unrecoverable. Typically
808 * these are caused by DMA errors. Unfortunately
809 * the exact reason is not (presently) returned
812 sc->sc_stats.ast_hardware++;
813 ath_hal_intrset(ah, 0); /* disable intr's until reset */
815 } else if (status & HAL_INT_RXORN) {
816 sc->sc_stats.ast_rxorn++;
817 ath_hal_intrset(ah, 0); /* disable intr's until reset */
820 if (status & HAL_INT_SWBA) {
822 * Software beacon alert--time to send a beacon.
823 * Handle beacon transmission directly; deferring
824 * this is too slow to meet timing constraints
829 if (status & HAL_INT_RXEOL) {
831 * NB: the hardware should re-read the link when
832 * RXE bit is written, but it doesn't work at
833 * least on older hardware revs.
835 sc->sc_stats.ast_rxeol++;
836 sc->sc_rxlink = NULL;
838 if (status & HAL_INT_TXURN) {
839 sc->sc_stats.ast_txurn++;
840 /* bump tx trigger level */
841 ath_hal_updatetxtriglevel(ah, AH_TRUE);
843 if (status & HAL_INT_RX)
845 if (status & HAL_INT_TX)
847 if (status & HAL_INT_BMISS) {
848 sc->sc_stats.ast_bmiss++;
851 if (status & HAL_INT_MIB) {
852 sc->sc_stats.ast_mib++;
854 * Disable interrupts until we service the MIB
855 * interrupt; otherwise it will continue to fire.
857 ath_hal_intrset(ah, 0);
859 * Let the hal handle the event. We assume it will
860 * clear whatever condition caused the interrupt.
862 ath_hal_mibevent(ah, &sc->sc_halstats);
863 ath_hal_intrset(ah, sc->sc_imask);
869 ath_fatal_proc(struct ath_softc *sc)
871 struct ifnet *ifp = &sc->sc_ic.ic_if;
873 if_printf(ifp, "hardware error; resetting\n");
878 ath_rxorn_proc(struct ath_softc *sc)
880 struct ifnet *ifp = &sc->sc_ic.ic_if;
882 if_printf(ifp, "rx FIFO overrun; resetting\n");
887 ath_bmiss_proc(struct ath_softc *sc)
889 struct ieee80211com *ic = &sc->sc_ic;
891 DPRINTF(sc, ATH_DEBUG_ANY, "%s\n", __func__);
892 KASSERT(ic->ic_opmode == IEEE80211_M_STA,
893 ("unexpect operating mode %u", ic->ic_opmode));
894 if (ic->ic_state == IEEE80211_S_RUN) {
895 uint64_t lastrx = sc->sc_lastrx;
896 uint64_t tsf = ath_hal_gettsf64(sc->sc_ah);
898 ic->ic_bmissthreshold * ic->ic_bss->ni_intval * 1024;
900 DPRINTF(sc, ATH_DEBUG_BEACON,
901 "%s: tsf %llu lastrx %lld (%llu) bmiss %u\n",
902 __func__, (unsigned long long) tsf,
903 (unsigned long long)(tsf - lastrx),
904 (unsigned long long) lastrx, bmisstimeout);
906 * Workaround phantom bmiss interrupts by sanity-checking
907 * the time of our last rx'd frame. If it is within the
908 * beacon miss interval then ignore the interrupt. If it's
909 * truly a bmiss we'll get another interrupt soon and that'll
910 * be dispatched up for processing.
912 if (tsf - lastrx > bmisstimeout)
913 ieee80211_beacon_miss(ic);
915 sc->sc_stats.ast_bmiss_phantom++;
920 ath_radar_proc(struct ath_softc *sc)
922 struct ifnet *ifp = &sc->sc_ic.ic_if;
923 struct ath_hal *ah = sc->sc_ah;
926 if (ath_hal_procdfs(ah, &hchan)) {
927 if_printf(ifp, "radar detected on channel %u/0x%x/0x%x\n",
928 hchan.channel, hchan.channelFlags, hchan.privFlags);
930 * Initiate channel change.
937 ath_chan2flags(struct ieee80211com *ic, struct ieee80211_channel *chan)
939 #define N(a) (sizeof(a) / sizeof(a[0]))
940 static const u_int modeflags[] = {
941 0, /* IEEE80211_MODE_AUTO */
942 CHANNEL_A, /* IEEE80211_MODE_11A */
943 CHANNEL_B, /* IEEE80211_MODE_11B */
944 CHANNEL_PUREG, /* IEEE80211_MODE_11G */
945 0, /* IEEE80211_MODE_FH */
946 CHANNEL_ST, /* IEEE80211_MODE_TURBO_A */
947 CHANNEL_108G /* IEEE80211_MODE_TURBO_G */
949 enum ieee80211_phymode mode = ieee80211_chan2mode(ic, chan);
951 KASSERT(mode < N(modeflags), ("unexpected phy mode %u", mode));
952 KASSERT(modeflags[mode] != 0, ("mode %u undefined", mode));
953 return modeflags[mode];
957 /* XXX error cleanup */
961 struct ath_softc *sc = arg;
962 struct ieee80211com *ic = &sc->sc_ic;
963 struct ifnet *ifp = &ic->ic_if;
964 struct ath_hal *ah = sc->sc_ah;
967 ASSERT_SERIALIZED(ifp->if_serializer);
969 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags 0x%x\n",
970 __func__, ifp->if_flags);
973 * Stop anything previously setup. This is safe
974 * whether this is the first time through or not.
976 ath_stop_no_pwchg(ifp);
979 * The basic interface to setting the hardware in a good
980 * state is ``reset''. On return the hardware is known to
981 * be powered up and with interrupts disabled. This must
982 * be followed by initialization of the appropriate bits
983 * and then setup of the interrupt mask.
985 sc->sc_curchan.channel = ic->ic_curchan->ic_freq;
986 sc->sc_curchan.channelFlags = ath_chan2flags(ic, ic->ic_curchan);
987 if (!ath_hal_reset(ah, sc->sc_opmode, &sc->sc_curchan, AH_FALSE,
989 if_printf(ifp, "unable to reset hardware; hal status %u\n",
995 * This is needed only to setup initial state
996 * but it's best done after a reset.
998 ath_update_txpow(sc);
1000 * Likewise this is set during reset so update
1001 * state cached in the driver.
1003 sc->sc_diversity = ath_hal_getdiversity(ah);
1004 sc->sc_calinterval = 1;
1005 sc->sc_caltries = 0;
1008 * Setup the hardware after reset: the key cache
1009 * is filled as needed and the receive engine is
1010 * set going. Frame transmit is handled entirely
1011 * in the frame output path; there's nothing to do
1012 * here except setup the interrupt mask.
1014 if (ath_startrecv(sc) != 0) {
1015 if_printf(ifp, "unable to start recv logic\n");
1020 * Enable interrupts.
1022 sc->sc_imask = HAL_INT_RX | HAL_INT_TX
1023 | HAL_INT_RXEOL | HAL_INT_RXORN
1024 | HAL_INT_FATAL | HAL_INT_GLOBAL;
1026 * Enable MIB interrupts when there are hardware phy counters.
1027 * Note we only do this (at the moment) for station mode.
1029 if (sc->sc_needmib && ic->ic_opmode == IEEE80211_M_STA)
1030 sc->sc_imask |= HAL_INT_MIB;
1031 ath_hal_intrset(ah, sc->sc_imask);
1033 ifp->if_flags |= IFF_RUNNING;
1034 ic->ic_state = IEEE80211_S_INIT;
1037 * The hardware should be ready to go now so it's safe
1038 * to kick the 802.11 state machine as it's likely to
1039 * immediately call back to us to send mgmt frames.
1041 ath_chan_change(sc, ic->ic_curchan);
1042 if (ic->ic_opmode != IEEE80211_M_MONITOR) {
1043 if (ic->ic_roaming != IEEE80211_ROAMING_MANUAL)
1044 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1);
1046 ieee80211_new_state(ic, IEEE80211_S_RUN, -1);
1051 ath_stop_no_pwchg(struct ifnet *ifp)
1053 struct ath_softc *sc = ifp->if_softc;
1054 struct ieee80211com *ic = &sc->sc_ic;
1055 struct ath_hal *ah = sc->sc_ah;
1057 ASSERT_SERIALIZED(ifp->if_serializer);
1059 DPRINTF(sc, ATH_DEBUG_ANY, "%s: invalid %u if_flags 0x%x\n",
1060 __func__, sc->sc_invalid, ifp->if_flags);
1062 if (ifp->if_flags & IFF_RUNNING) {
1064 * Shutdown the hardware and driver:
1065 * reset 802.11 state machine
1067 * disable interrupts
1068 * turn off the radio
1069 * clear transmit machinery
1070 * clear receive machinery
1071 * drain and release tx queues
1072 * reclaim beacon resources
1073 * power down hardware
1075 * Note that some of this work is not possible if the
1076 * hardware is gone (invalid).
1078 ieee80211_new_state(ic, IEEE80211_S_INIT, -1);
1079 ifp->if_flags &= ~IFF_RUNNING;
1081 if (!sc->sc_invalid) {
1082 if (sc->sc_softled) {
1083 callout_stop(&sc->sc_ledtimer);
1084 ath_hal_gpioset(ah, sc->sc_ledpin,
1086 sc->sc_blinking = 0;
1088 ath_hal_intrset(ah, 0);
1091 if (!sc->sc_invalid) {
1093 ath_hal_phydisable(ah);
1095 sc->sc_rxlink = NULL;
1097 ifq_purge(&ifp->if_snd);
1099 ath_beacon_free(sc);
1104 ath_stop(struct ifnet *ifp)
1106 struct ath_softc *sc = ifp->if_softc;
1108 ASSERT_SERIALIZED(ifp->if_serializer);
1110 ath_stop_no_pwchg(ifp);
1111 if (!sc->sc_invalid) {
1113 * Set the chip in full sleep mode. Note that we are
1114 * careful to do this only when bringing the interface
1115 * completely to a stop. When the chip is in this state
1116 * it must be carefully woken up or references to
1117 * registers in the PCI clock domain may freeze the bus
1118 * (and system). This varies by chip and is mostly an
1119 * issue with newer parts that go to sleep more quickly.
1121 ath_hal_setpower(sc->sc_ah, HAL_PM_FULL_SLEEP);
1126 * Reset the hardware w/o losing operational state. This is
1127 * basically a more efficient way of doing ath_stop, ath_init,
1128 * followed by state transitions to the current 802.11
1129 * operational state. Used to recover from various errors and
1130 * to reset or reload hardware state.
1133 ath_reset(struct ifnet *ifp)
1135 struct ath_softc *sc = ifp->if_softc;
1136 struct ieee80211com *ic = &sc->sc_ic;
1137 struct ath_hal *ah = sc->sc_ah;
1138 struct ieee80211_channel *c;
1141 ASSERT_SERIALIZED(ifp->if_serializer);
1144 * Convert to a HAL channel description with the flags
1145 * constrained to reflect the current operating mode.
1148 sc->sc_curchan.channel = c->ic_freq;
1149 sc->sc_curchan.channelFlags = ath_chan2flags(ic, c);
1151 ath_hal_intrset(ah, 0); /* disable interrupts */
1152 ath_draintxq(sc); /* stop xmit side */
1153 ath_stoprecv(sc); /* stop recv side */
1154 /* NB: indicate channel change so we do a full reset */
1155 if (!ath_hal_reset(ah, sc->sc_opmode, &sc->sc_curchan, AH_TRUE,
1157 if_printf(ifp, "%s: unable to reset hardware; hal status %u\n",
1160 ath_update_txpow(sc); /* update tx power state */
1161 sc->sc_diversity = ath_hal_getdiversity(ah);
1162 sc->sc_calinterval = 1;
1163 sc->sc_caltries = 0;
1165 * We may be doing a reset in response to an ioctl
1166 * that changes the channel so update any state that
1167 * might change as a result.
1169 ath_chan_change(sc, c);
1170 if (ath_startrecv(sc) != 0) /* restart recv */
1171 if_printf(ifp, "%s: unable to start recv logic\n", __func__);
1172 if (ic->ic_state == IEEE80211_S_RUN)
1173 ath_beacon_config(sc); /* restart beacons */
1174 ath_hal_intrset(ah, sc->sc_imask);
1176 ath_start(ifp); /* restart xmit */
1181 ath_start(struct ifnet *ifp)
1183 struct ath_softc *sc = ifp->if_softc;
1184 struct ath_hal *ah = sc->sc_ah;
1185 struct ieee80211com *ic = &sc->sc_ic;
1186 struct ieee80211_node *ni;
1189 struct ieee80211_frame *wh;
1190 struct ether_header *eh;
1192 if ((ifp->if_flags & IFF_RUNNING) == 0 || sc->sc_invalid)
1197 * Grab a TX buffer and associated resources.
1199 bf = STAILQ_FIRST(&sc->sc_txbuf);
1201 STAILQ_REMOVE_HEAD(&sc->sc_txbuf, bf_list);
1203 DPRINTF(sc, ATH_DEBUG_XMIT, "%s: out of xmit buffers\n",
1205 sc->sc_stats.ast_tx_qstop++;
1206 ifp->if_flags |= IFF_OACTIVE;
1210 * Poll the management queue for frames; they
1211 * have priority over normal data frames.
1213 IF_DEQUEUE(&ic->ic_mgtq, m);
1216 * No data frames go out unless we're associated.
1218 if (ic->ic_state != IEEE80211_S_RUN) {
1219 DPRINTF(sc, ATH_DEBUG_XMIT,
1220 "%s: discard data packet, state %s\n",
1222 ieee80211_state_name[ic->ic_state]);
1223 sc->sc_stats.ast_tx_discard++;
1224 STAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list);
1227 m = ifq_dequeue(&ifp->if_snd, NULL);
1229 STAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list);
1233 * Find the node for the destination so we can do
1234 * things like power save and fast frames aggregation.
1236 if (m->m_len < sizeof(struct ether_header) &&
1237 (m = m_pullup(m, sizeof(struct ether_header))) == NULL) {
1238 ic->ic_stats.is_tx_nobuf++; /* XXX */
1242 eh = mtod(m, struct ether_header *);
1243 ni = ieee80211_find_txnode(ic, eh->ether_dhost);
1245 /* NB: ieee80211_find_txnode does stat+msg */
1249 if ((ni->ni_flags & IEEE80211_NODE_PWR_MGT) &&
1250 (m->m_flags & M_PWR_SAV) == 0) {
1252 * Station in power save mode; pass the frame
1253 * to the 802.11 layer and continue. We'll get
1254 * the frame back when the time is right.
1256 ieee80211_pwrsave(ic, ni, m);
1259 /* calculate priority so we can find the tx queue */
1260 if (ieee80211_classify(ic, m, ni)) {
1261 DPRINTF(sc, ATH_DEBUG_XMIT,
1262 "%s: discard, classification failure\n",
1270 * Encapsulate the packet in prep for transmission.
1272 m = ieee80211_encap(ic, m, ni);
1274 DPRINTF(sc, ATH_DEBUG_XMIT,
1275 "%s: encapsulation failure\n",
1277 sc->sc_stats.ast_tx_encap++;
1282 * Hack! The referenced node pointer is in the
1283 * rcvif field of the packet header. This is
1284 * placed there by ieee80211_mgmt_output because
1285 * we need to hold the reference with the frame
1286 * and there's no other way (other than packet
1287 * tags which we consider too expensive to use)
1290 ni = (struct ieee80211_node *) m->m_pkthdr.rcvif;
1291 m->m_pkthdr.rcvif = NULL;
1293 wh = mtod(m, struct ieee80211_frame *);
1294 if ((wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK) ==
1295 IEEE80211_FC0_SUBTYPE_PROBE_RESP) {
1296 /* fill time stamp */
1300 tsf = ath_hal_gettsf64(ah);
1301 /* XXX: adjust 100us delay to xmit */
1303 tstamp = (uint32_t *)&wh[1];
1304 tstamp[0] = htole32(tsf & 0xffffffff);
1305 tstamp[1] = htole32(tsf >> 32);
1307 sc->sc_stats.ast_tx_mgmt++;
1310 if (ath_tx_start(sc, ni, bf, m)) {
1314 STAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list);
1316 ieee80211_free_node(ni);
1320 sc->sc_tx_timer = 5;
1326 ath_media_change(struct ifnet *ifp)
1328 #define IS_UP(ifp) \
1329 ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == (IFF_RUNNING | IFF_UP))
1332 error = ieee80211_media_change(ifp);
1333 if (error == ENETRESET) {
1334 struct ath_softc *sc = ifp->if_softc;
1335 struct ieee80211com *ic = &sc->sc_ic;
1337 if (ic->ic_opmode == IEEE80211_M_AHDEMO) {
1339 * Adhoc demo mode is just ibss mode w/o beacons
1340 * (mostly). The hal knows nothing about it;
1341 * tell it we're operating in ibss mode.
1343 sc->sc_opmode = HAL_M_IBSS;
1345 sc->sc_opmode = ic->ic_opmode;
1347 ath_init(ifp->if_softc); /* XXX lose error */
1356 ath_keyprint(const char *tag, u_int ix,
1357 const HAL_KEYVAL *hk, const uint8_t mac[IEEE80211_ADDR_LEN])
1359 static const char *ciphers[] = {
1369 printf("%s: [%02u] %-7s ", tag, ix, ciphers[hk->kv_type]);
1370 for (i = 0, n = hk->kv_len; i < n; i++)
1371 printf("%02x", hk->kv_val[i]);
1372 printf(" mac %6D", mac, ":");
1373 if (hk->kv_type == HAL_CIPHER_TKIP) {
1375 for (i = 0; i < sizeof(hk->kv_mic); i++)
1376 printf("%02x", hk->kv_mic[i]);
1383 * Set a TKIP key into the hardware. This handles the
1384 * potential distribution of key state to multiple key
1385 * cache slots for TKIP.
1388 ath_keyset_tkip(struct ath_softc *sc, const struct ieee80211_key *k,
1389 HAL_KEYVAL *hk, const uint8_t mac[IEEE80211_ADDR_LEN])
1391 #define IEEE80211_KEY_XR (IEEE80211_KEY_XMIT | IEEE80211_KEY_RECV)
1392 static const uint8_t zerobssid[IEEE80211_ADDR_LEN];
1393 struct ath_hal *ah = sc->sc_ah;
1395 KASSERT(k->wk_cipher->ic_cipher == IEEE80211_CIPHER_TKIP,
1396 ("got a non-TKIP key, cipher %u", k->wk_cipher->ic_cipher));
1397 KASSERT(sc->sc_splitmic, ("key cache !split"));
1398 if ((k->wk_flags & IEEE80211_KEY_XR) == IEEE80211_KEY_XR) {
1400 * TX key goes at first index, RX key at the rx index.
1401 * The hal handles the MIC keys at index+64.
1403 memcpy(hk->kv_mic, k->wk_txmic, sizeof(hk->kv_mic));
1404 KEYPRINTF(sc, k->wk_keyix, hk, zerobssid);
1405 if (!ath_hal_keyset(ah, k->wk_keyix, hk, zerobssid))
1408 memcpy(hk->kv_mic, k->wk_rxmic, sizeof(hk->kv_mic));
1409 KEYPRINTF(sc, k->wk_keyix+32, hk, mac);
1410 /* XXX delete tx key on failure? */
1411 return ath_hal_keyset(ah, k->wk_keyix+32, hk, mac);
1412 } else if (k->wk_flags & IEEE80211_KEY_XR) {
1414 * TX/RX key goes at first index.
1415 * The hal handles the MIC keys are index+64.
1417 memcpy(hk->kv_mic, k->wk_flags & IEEE80211_KEY_XMIT ?
1418 k->wk_txmic : k->wk_rxmic, sizeof(hk->kv_mic));
1419 KEYPRINTF(sc, k->wk_keyix, hk, mac);
1420 return ath_hal_keyset(ah, k->wk_keyix, hk, mac);
1423 #undef IEEE80211_KEY_XR
1427 * Set a net80211 key into the hardware. This handles the
1428 * potential distribution of key state to multiple key
1429 * cache slots for TKIP with hardware MIC support.
1432 ath_keyset(struct ath_softc *sc, const struct ieee80211_key *k,
1433 const uint8_t mac0[IEEE80211_ADDR_LEN],
1434 struct ieee80211_node *bss)
1436 #define N(a) (sizeof(a)/sizeof(a[0]))
1437 static const uint8_t ciphermap[] = {
1438 HAL_CIPHER_WEP, /* IEEE80211_CIPHER_WEP */
1439 HAL_CIPHER_TKIP, /* IEEE80211_CIPHER_TKIP */
1440 HAL_CIPHER_AES_OCB, /* IEEE80211_CIPHER_AES_OCB */
1441 HAL_CIPHER_AES_CCM, /* IEEE80211_CIPHER_AES_CCM */
1442 (uint8_t) -1, /* 4 is not allocated */
1443 HAL_CIPHER_CKIP, /* IEEE80211_CIPHER_CKIP */
1444 HAL_CIPHER_CLR, /* IEEE80211_CIPHER_NONE */
1446 struct ath_hal *ah = sc->sc_ah;
1447 const struct ieee80211_cipher *cip = k->wk_cipher;
1448 uint8_t gmac[IEEE80211_ADDR_LEN];
1452 memset(&hk, 0, sizeof(hk));
1454 * Software crypto uses a "clear key" so non-crypto
1455 * state kept in the key cache are maintained and
1456 * so that rx frames have an entry to match.
1458 if ((k->wk_flags & IEEE80211_KEY_SWCRYPT) == 0) {
1459 KASSERT(cip->ic_cipher < N(ciphermap),
1460 ("invalid cipher type %u", cip->ic_cipher));
1461 hk.kv_type = ciphermap[cip->ic_cipher];
1462 hk.kv_len = k->wk_keylen;
1463 memcpy(hk.kv_val, k->wk_key, k->wk_keylen);
1465 hk.kv_type = HAL_CIPHER_CLR;
1467 if ((k->wk_flags & IEEE80211_KEY_GROUP) && sc->sc_mcastkey) {
1469 * Group keys on hardware that supports multicast frame
1470 * key search use a mac that is the sender's address with
1471 * the high bit set instead of the app-specified address.
1473 IEEE80211_ADDR_COPY(gmac, bss->ni_macaddr);
1479 if (hk.kv_type == HAL_CIPHER_TKIP &&
1480 (k->wk_flags & IEEE80211_KEY_SWMIC) == 0 &&
1482 return ath_keyset_tkip(sc, k, &hk, mac);
1484 KEYPRINTF(sc, k->wk_keyix, &hk, mac);
1485 return ath_hal_keyset(ah, k->wk_keyix, &hk, mac);
1491 * Allocate tx/rx key slots for TKIP. We allocate two slots for
1492 * each key, one for decrypt/encrypt and the other for the MIC.
1495 key_alloc_2pair(struct ath_softc *sc,
1496 ieee80211_keyix *txkeyix, ieee80211_keyix *rxkeyix)
1498 #define N(a) (sizeof(a)/sizeof(a[0]))
1501 KASSERT(sc->sc_splitmic, ("key cache !split"));
1502 /* XXX could optimize */
1503 for (i = 0; i < N(sc->sc_keymap)/4; i++) {
1504 uint8_t b = sc->sc_keymap[i];
1507 * One or more slots in this byte are free.
1515 /* XXX IEEE80211_KEY_XMIT | IEEE80211_KEY_RECV */
1516 if (isset(sc->sc_keymap, keyix+32) ||
1517 isset(sc->sc_keymap, keyix+64) ||
1518 isset(sc->sc_keymap, keyix+32+64)) {
1519 /* full pair unavailable */
1521 if (keyix == (i+1)*NBBY) {
1522 /* no slots were appropriate, advance */
1527 setbit(sc->sc_keymap, keyix);
1528 setbit(sc->sc_keymap, keyix+64);
1529 setbit(sc->sc_keymap, keyix+32);
1530 setbit(sc->sc_keymap, keyix+32+64);
1531 DPRINTF(sc, ATH_DEBUG_KEYCACHE,
1532 "%s: key pair %u,%u %u,%u\n",
1533 __func__, keyix, keyix+64,
1534 keyix+32, keyix+32+64);
1536 *rxkeyix = keyix+32;
1540 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s: out of pair space\n", __func__);
1546 * Allocate a single key cache slot.
1549 key_alloc_single(struct ath_softc *sc,
1550 ieee80211_keyix *txkeyix, ieee80211_keyix *rxkeyix)
1552 #define N(a) (sizeof(a)/sizeof(a[0]))
1555 /* XXX try i,i+32,i+64,i+32+64 to minimize key pair conflicts */
1556 for (i = 0; i < N(sc->sc_keymap); i++) {
1557 uint8_t b = sc->sc_keymap[i];
1560 * One or more slots are free.
1565 setbit(sc->sc_keymap, keyix);
1566 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s: key %u\n",
1568 *txkeyix = *rxkeyix = keyix;
1572 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s: out of space\n", __func__);
1578 * Allocate one or more key cache slots for a uniacst key. The
1579 * key itself is needed only to identify the cipher. For hardware
1580 * TKIP with split cipher+MIC keys we allocate two key cache slot
1581 * pairs so that we can setup separate TX and RX MIC keys. Note
1582 * that the MIC key for a TKIP key at slot i is assumed by the
1583 * hardware to be at slot i+64. This limits TKIP keys to the first
1587 ath_key_alloc(struct ieee80211com *ic, const struct ieee80211_key *k,
1588 ieee80211_keyix *keyix, ieee80211_keyix *rxkeyix)
1590 struct ath_softc *sc = ic->ic_ifp->if_softc;
1593 * Group key allocation must be handled specially for
1594 * parts that do not support multicast key cache search
1595 * functionality. For those parts the key id must match
1596 * the h/w key index so lookups find the right key. On
1597 * parts w/ the key search facility we install the sender's
1598 * mac address (with the high bit set) and let the hardware
1599 * find the key w/o using the key id. This is preferred as
1600 * it permits us to support multiple users for adhoc and/or
1601 * multi-station operation.
1603 if ((k->wk_flags & IEEE80211_KEY_GROUP) && !sc->sc_mcastkey) {
1604 if (!(&ic->ic_nw_keys[0] <= k &&
1605 k < &ic->ic_nw_keys[IEEE80211_WEP_NKID])) {
1606 /* should not happen */
1607 DPRINTF(sc, ATH_DEBUG_KEYCACHE,
1608 "%s: bogus group key\n", __func__);
1612 * XXX we pre-allocate the global keys so
1613 * have no way to check if they've already been allocated.
1615 *keyix = *rxkeyix = k - ic->ic_nw_keys;
1620 * We allocate two pair for TKIP when using the h/w to do
1621 * the MIC. For everything else, including software crypto,
1622 * we allocate a single entry. Note that s/w crypto requires
1623 * a pass-through slot on the 5211 and 5212. The 5210 does
1624 * not support pass-through cache entries and we map all
1625 * those requests to slot 0.
1627 if (k->wk_flags & IEEE80211_KEY_SWCRYPT) {
1628 return key_alloc_single(sc, keyix, rxkeyix);
1629 } else if (k->wk_cipher->ic_cipher == IEEE80211_CIPHER_TKIP &&
1630 (k->wk_flags & IEEE80211_KEY_SWMIC) == 0 && sc->sc_splitmic) {
1631 return key_alloc_2pair(sc, keyix, rxkeyix);
1633 return key_alloc_single(sc, keyix, rxkeyix);
1638 * Delete an entry in the key cache allocated by ath_key_alloc.
1641 ath_key_delete(struct ieee80211com *ic, const struct ieee80211_key *k)
1643 struct ath_softc *sc = ic->ic_ifp->if_softc;
1644 struct ath_hal *ah = sc->sc_ah;
1645 const struct ieee80211_cipher *cip = k->wk_cipher;
1646 u_int keyix = k->wk_keyix;
1648 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s: delete key %u\n", __func__, keyix);
1650 ath_hal_keyreset(ah, keyix);
1652 * Handle split tx/rx keying required for TKIP with h/w MIC.
1654 if (cip->ic_cipher == IEEE80211_CIPHER_TKIP &&
1655 (k->wk_flags & IEEE80211_KEY_SWMIC) == 0 && sc->sc_splitmic)
1656 ath_hal_keyreset(ah, keyix+32); /* RX key */
1657 if (keyix >= IEEE80211_WEP_NKID) {
1659 * Don't touch keymap entries for global keys so
1660 * they are never considered for dynamic allocation.
1662 clrbit(sc->sc_keymap, keyix);
1663 if (cip->ic_cipher == IEEE80211_CIPHER_TKIP &&
1664 (k->wk_flags & IEEE80211_KEY_SWMIC) == 0 &&
1666 clrbit(sc->sc_keymap, keyix+64); /* TX key MIC */
1667 clrbit(sc->sc_keymap, keyix+32); /* RX key */
1668 clrbit(sc->sc_keymap, keyix+32+64); /* RX key MIC */
1675 * Set the key cache contents for the specified key. Key cache
1676 * slot(s) must already have been allocated by ath_key_alloc.
1679 ath_key_set(struct ieee80211com *ic, const struct ieee80211_key *k,
1680 const uint8_t mac[IEEE80211_ADDR_LEN])
1682 struct ath_softc *sc = ic->ic_ifp->if_softc;
1684 return ath_keyset(sc, k, mac, ic->ic_bss);
1688 * Block/unblock tx+rx processing while a key change is done.
1689 * We assume the caller serializes key management operations
1690 * so we only need to worry about synchronization with other
1691 * uses that originate in the driver.
1694 ath_key_update_begin(struct ieee80211com *ic)
1696 struct ifnet *ifp = ic->ic_ifp;
1697 struct ath_softc *sc = ifp->if_softc;
1699 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s:\n", __func__);
1701 tasklet_disable(&sc->sc_rxtq);
1702 IF_LOCK(&ifp->if_snd); /* NB: doesn't block mgmt frames */
1707 ath_key_update_end(struct ieee80211com *ic)
1709 struct ifnet *ifp = ic->ic_ifp;
1710 struct ath_softc *sc = ifp->if_softc;
1712 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s:\n", __func__);
1714 IF_UNLOCK(&ifp->if_snd);
1715 tasklet_enable(&sc->sc_rxtq);
1720 * Calculate the receive filter according to the
1721 * operating mode and state:
1723 * o always accept unicast, broadcast, and multicast traffic
1724 * o maintain current state of phy error reception (the hal
1725 * may enable phy error frames for noise immunity work)
1726 * o probe request frames are accepted only when operating in
1727 * hostap, adhoc, or monitor modes
1728 * o enable promiscuous mode according to the interface state
1730 * - when operating in adhoc mode so the 802.11 layer creates
1731 * node table entries for peers,
1732 * - when operating in station mode for collecting rssi data when
1733 * the station is otherwise quiet, or
1737 ath_calcrxfilter(struct ath_softc *sc, enum ieee80211_state state)
1739 #define RX_FILTER_PRESERVE (HAL_RX_FILTER_PHYERR | HAL_RX_FILTER_PHYRADAR)
1740 struct ieee80211com *ic = &sc->sc_ic;
1741 struct ath_hal *ah = sc->sc_ah;
1742 struct ifnet *ifp = &ic->ic_if;
1745 rfilt = (ath_hal_getrxfilter(ah) & RX_FILTER_PRESERVE)
1746 | HAL_RX_FILTER_UCAST | HAL_RX_FILTER_BCAST | HAL_RX_FILTER_MCAST;
1747 if (ic->ic_opmode != IEEE80211_M_STA)
1748 rfilt |= HAL_RX_FILTER_PROBEREQ;
1749 if (ic->ic_opmode != IEEE80211_M_HOSTAP &&
1750 (ifp->if_flags & IFF_PROMISC))
1751 rfilt |= HAL_RX_FILTER_PROM;
1752 if (ic->ic_opmode == IEEE80211_M_STA ||
1753 ic->ic_opmode == IEEE80211_M_IBSS ||
1754 state == IEEE80211_S_SCAN)
1755 rfilt |= HAL_RX_FILTER_BEACON;
1757 #undef RX_FILTER_PRESERVE
1761 ath_mode_init(struct ath_softc *sc)
1763 struct ieee80211com *ic = &sc->sc_ic;
1764 struct ath_hal *ah = sc->sc_ah;
1765 struct ifnet *ifp = &ic->ic_if;
1766 uint32_t rfilt, mfilt[2], val;
1768 struct ifmultiaddr *ifma;
1770 /* configure rx filter */
1771 rfilt = ath_calcrxfilter(sc, ic->ic_state);
1772 ath_hal_setrxfilter(ah, rfilt);
1774 /* configure operational mode */
1775 ath_hal_setopmode(ah);
1778 * Handle any link-level address change. Note that we only
1779 * need to force ic_myaddr; any other addresses are handled
1780 * as a byproduct of the ifnet code marking the interface
1783 * XXX should get from lladdr instead of arpcom but that's more work
1785 IEEE80211_ADDR_COPY(ic->ic_myaddr, IF_LLADDR(ifp));
1786 ath_hal_setmac(ah, ic->ic_myaddr);
1788 /* calculate and install multicast filter */
1789 if ((ifp->if_flags & IFF_ALLMULTI) == 0) {
1790 mfilt[0] = mfilt[1] = 0;
1791 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1794 /* calculate XOR of eight 6bit values */
1795 dl = LLADDR((struct sockaddr_dl *)ifma->ifma_addr);
1796 val = LE_READ_4(dl + 0);
1797 pos = (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
1798 val = LE_READ_4(dl + 3);
1799 pos ^= (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
1801 mfilt[pos / 32] |= (1 << (pos % 32));
1804 mfilt[0] = mfilt[1] = ~0;
1806 ath_hal_setmcastfilter(ah, mfilt[0], mfilt[1]);
1807 DPRINTF(sc, ATH_DEBUG_MODE, "%s: RX filter 0x%x, MC filter %08x:%08x\n",
1808 __func__, rfilt, mfilt[0], mfilt[1]);
1812 * Set the slot time based on the current setting.
1815 ath_setslottime(struct ath_softc *sc)
1817 struct ieee80211com *ic = &sc->sc_ic;
1818 struct ath_hal *ah = sc->sc_ah;
1820 if (ic->ic_flags & IEEE80211_F_SHSLOT)
1821 ath_hal_setslottime(ah, HAL_SLOT_TIME_9);
1823 ath_hal_setslottime(ah, HAL_SLOT_TIME_20);
1824 sc->sc_updateslot = OK;
1828 * Callback from the 802.11 layer to update the
1829 * slot time based on the current setting.
1832 ath_updateslot(struct ifnet *ifp)
1834 struct ath_softc *sc = ifp->if_softc;
1835 struct ieee80211com *ic = &sc->sc_ic;
1838 * When not coordinating the BSS, change the hardware
1839 * immediately. For other operation we defer the change
1840 * until beacon updates have propagated to the stations.
1842 if (ic->ic_opmode == IEEE80211_M_HOSTAP)
1843 sc->sc_updateslot = UPDATE;
1845 ath_setslottime(sc);
1849 * Setup a h/w transmit queue for beacons.
1852 ath_beaconq_setup(struct ath_hal *ah)
1856 memset(&qi, 0, sizeof(qi));
1857 qi.tqi_aifs = HAL_TXQ_USEDEFAULT;
1858 qi.tqi_cwmin = HAL_TXQ_USEDEFAULT;
1859 qi.tqi_cwmax = HAL_TXQ_USEDEFAULT;
1860 /* NB: for dynamic turbo, don't enable any other interrupts */
1861 qi.tqi_qflags = HAL_TXQ_TXDESCINT_ENABLE;
1862 return ath_hal_setuptxqueue(ah, HAL_TX_QUEUE_BEACON, &qi);
1866 * Setup the transmit queue parameters for the beacon queue.
1869 ath_beaconq_config(struct ath_softc *sc)
1871 #define ATH_EXPONENT_TO_VALUE(v) ((1<<(v))-1)
1872 struct ieee80211com *ic = &sc->sc_ic;
1873 struct ath_hal *ah = sc->sc_ah;
1876 ath_hal_gettxqueueprops(ah, sc->sc_bhalq, &qi);
1877 if (ic->ic_opmode == IEEE80211_M_HOSTAP) {
1879 * Always burst out beacon and CAB traffic.
1881 qi.tqi_aifs = ATH_BEACON_AIFS_DEFAULT;
1882 qi.tqi_cwmin = ATH_BEACON_CWMIN_DEFAULT;
1883 qi.tqi_cwmax = ATH_BEACON_CWMAX_DEFAULT;
1885 struct wmeParams *wmep =
1886 &ic->ic_wme.wme_chanParams.cap_wmeParams[WME_AC_BE];
1888 * Adhoc mode; important thing is to use 2x cwmin.
1890 qi.tqi_aifs = wmep->wmep_aifsn;
1891 qi.tqi_cwmin = 2*ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmin);
1892 qi.tqi_cwmax = ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmax);
1895 if (!ath_hal_settxqueueprops(ah, sc->sc_bhalq, &qi)) {
1896 device_printf(sc->sc_dev, "unable to update parameters for "
1897 "beacon hardware queue!\n");
1900 ath_hal_resettxqueue(ah, sc->sc_bhalq); /* push to h/w */
1903 #undef ATH_EXPONENT_TO_VALUE
1907 * Allocate and setup an initial beacon frame.
1910 ath_beacon_alloc(struct ath_softc *sc, struct ieee80211_node *ni)
1912 struct ieee80211com *ic = ni->ni_ic;
1917 bf = STAILQ_FIRST(&sc->sc_bbuf);
1919 DPRINTF(sc, ATH_DEBUG_BEACON, "%s: no dma buffers\n", __func__);
1920 sc->sc_stats.ast_be_nombuf++; /* XXX */
1921 return ENOMEM; /* XXX */
1924 * NB: the beacon data buffer must be 32-bit aligned;
1925 * we assume the mbuf routines will return us something
1926 * with this alignment (perhaps should assert).
1928 m = ieee80211_beacon_alloc(ic, ni, &sc->sc_boff);
1930 DPRINTF(sc, ATH_DEBUG_BEACON, "%s: cannot get mbuf\n",
1932 sc->sc_stats.ast_be_nombuf++;
1936 error = bus_dmamap_load_mbuf(sc->sc_dmat, bf->bf_dmamap, m,
1937 ath_dma_map_mbuf, bf, BUS_DMA_NOWAIT);
1940 bf->bf_node = ieee80211_ref_node(ni);
1948 * Setup the beacon frame for transmit.
1951 ath_beacon_setup(struct ath_softc *sc, struct ath_buf *bf)
1953 #define USE_SHPREAMBLE(_ic) \
1954 (((_ic)->ic_flags & (IEEE80211_F_SHPREAMBLE | IEEE80211_F_USEBARKER))\
1955 == IEEE80211_F_SHPREAMBLE)
1956 struct ieee80211_node *ni = bf->bf_node;
1957 struct ieee80211com *ic = ni->ni_ic;
1958 struct mbuf *m = bf->bf_m;
1959 struct ath_hal *ah = sc->sc_ah;
1960 struct ath_desc *ds;
1962 const HAL_RATE_TABLE *rt;
1965 DPRINTF(sc, ATH_DEBUG_BEACON, "%s: m %p len %u\n",
1966 __func__, m, m->m_len);
1968 /* setup descriptors */
1971 flags = HAL_TXDESC_NOACK;
1972 if (ic->ic_opmode == IEEE80211_M_IBSS && sc->sc_hasveol) {
1973 ds->ds_link = bf->bf_daddr; /* self-linked */
1974 flags |= HAL_TXDESC_VEOL;
1976 * Let hardware handle antenna switching.
1978 antenna = sc->sc_txantenna;
1982 * Switch antenna every 4 beacons.
1983 * XXX assumes two antenna
1985 antenna = (sc->sc_stats.ast_be_xmit & 4 ? 2 : 1);
1988 KASSERT(bf->bf_nseg == 1,
1989 ("multi-segment beacon frame; nseg %u", bf->bf_nseg));
1990 ds->ds_data = bf->bf_segs[0].ds_addr;
1992 * Calculate rate code.
1993 * XXX everything at min xmit rate
1995 rix = sc->sc_minrateix;
1996 rt = sc->sc_currates;
1997 rate = rt->info[rix].rateCode;
1998 if (USE_SHPREAMBLE(ic))
1999 rate |= rt->info[rix].shortPreamble;
2000 ath_hal_setuptxdesc(ah, ds
2001 , m->m_len + IEEE80211_CRC_LEN /* frame length */
2002 , sizeof(struct ieee80211_frame)/* header length */
2003 , HAL_PKT_TYPE_BEACON /* Atheros packet type */
2004 , ni->ni_txpower /* txpower XXX */
2005 , rate, 1 /* series 0 rate/tries */
2006 , HAL_TXKEYIX_INVALID /* no encryption */
2007 , antenna /* antenna mode */
2008 , flags /* no ack, veol for beacons */
2009 , 0 /* rts/cts rate */
2010 , 0 /* rts/cts duration */
2012 /* NB: beacon's BufLen must be a multiple of 4 bytes */
2013 ath_hal_filltxdesc(ah, ds
2014 , roundup(m->m_len, 4) /* buffer length */
2015 , AH_TRUE /* first segment */
2016 , AH_TRUE /* last segment */
2017 , ds /* first descriptor */
2019 #undef USE_SHPREAMBLE
2023 * Transmit a beacon frame at SWBA. Dynamic updates to the
2024 * frame contents are done as needed and the slot time is
2025 * also adjusted based on current state.
2028 ath_beacon_proc(struct ath_softc *sc)
2030 struct ath_buf *bf = STAILQ_FIRST(&sc->sc_bbuf);
2031 struct ieee80211_node *ni = bf->bf_node;
2032 struct ieee80211com *ic = ni->ni_ic;
2033 struct ath_hal *ah = sc->sc_ah;
2035 int ncabq, error, otherant;
2037 if (ic->ic_opmode == IEEE80211_M_STA ||
2038 ic->ic_opmode == IEEE80211_M_MONITOR ||
2039 bf == NULL || bf->bf_m == NULL) {
2040 DPRINTF(sc, ATH_DEBUG_ANY, "%s: ic_flags=%x bf=%p bf_m=%p\n",
2041 __func__, ic->ic_flags, bf, bf ? bf->bf_m : NULL);
2045 * Check if the previous beacon has gone out. If
2046 * not don't don't try to post another, skip this
2047 * period and wait for the next. Missed beacons
2048 * indicate a problem and should not occur. If we
2049 * miss too many consecutive beacons reset the device.
2051 if (ath_hal_numtxpending(ah, sc->sc_bhalq) != 0) {
2052 sc->sc_bmisscount++;
2053 DPRINTF(sc, ATH_DEBUG_BEACON_PROC,
2054 "%s: missed %u consecutive beacons\n",
2055 __func__, sc->sc_bmisscount);
2056 if (sc->sc_bmisscount > 3) /* NB: 3 is a guess */
2057 ath_bstuck_proc(sc);
2060 if (sc->sc_bmisscount != 0) {
2061 DPRINTF(sc, ATH_DEBUG_BEACON,
2062 "%s: resume beacon xmit after %u misses\n",
2063 __func__, sc->sc_bmisscount);
2064 sc->sc_bmisscount = 0;
2068 * Update dynamic beacon contents. If this returns
2069 * non-zero then we need to remap the memory because
2070 * the beacon frame changed size (probably because
2071 * of the TIM bitmap).
2074 ncabq = sc->sc_cabq->axq_depth;
2075 if (ieee80211_beacon_update(ic, bf->bf_node, &sc->sc_boff, m, ncabq)) {
2076 /* XXX too conservative? */
2077 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap);
2078 error = bus_dmamap_load_mbuf(sc->sc_dmat, bf->bf_dmamap, m,
2079 ath_dma_map_mbuf, bf,
2082 if_printf(ic->ic_ifp,
2083 "%s: bus_dmamap_load_mbuf failed, error %u\n",
2090 * Handle slot time change when a non-ERP station joins/leaves
2091 * an 11g network. The 802.11 layer notifies us via callback,
2092 * we mark updateslot, then wait one beacon before effecting
2093 * the change. This gives associated stations at least one
2094 * beacon interval to note the state change.
2097 if (sc->sc_updateslot == UPDATE)
2098 sc->sc_updateslot = COMMIT; /* commit next beacon */
2099 else if (sc->sc_updateslot == COMMIT)
2100 ath_setslottime(sc); /* commit change to h/w */
2103 * Check recent per-antenna transmit statistics and flip
2104 * the default antenna if noticeably more frames went out
2105 * on the non-default antenna.
2106 * XXX assumes 2 anntenae
2108 otherant = sc->sc_defant & 1 ? 2 : 1;
2109 if (sc->sc_ant_tx[otherant] > sc->sc_ant_tx[sc->sc_defant] + 2)
2110 ath_setdefantenna(sc, otherant);
2111 sc->sc_ant_tx[1] = sc->sc_ant_tx[2] = 0;
2114 * Construct tx descriptor.
2116 ath_beacon_setup(sc, bf);
2119 * Stop any current dma and put the new frame on the queue.
2120 * This should never fail since we check above that no frames
2121 * are still pending on the queue.
2123 if (!ath_hal_stoptxdma(ah, sc->sc_bhalq)) {
2124 DPRINTF(sc, ATH_DEBUG_ANY,
2125 "%s: beacon queue %u did not stop?\n",
2126 __func__, sc->sc_bhalq);
2128 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, BUS_DMASYNC_PREWRITE);
2131 * Enable the CAB queue before the beacon queue to
2132 * insure cab frames are triggered by this beacon.
2134 if (sc->sc_boff.bo_tim[4] & 1) /* NB: only at DTIM */
2135 ath_hal_txstart(ah, sc->sc_cabq->axq_qnum);
2136 ath_hal_puttxbuf(ah, sc->sc_bhalq, bf->bf_daddr);
2137 ath_hal_txstart(ah, sc->sc_bhalq);
2138 DPRINTF(sc, ATH_DEBUG_BEACON_PROC,
2139 "%s: TXDP[%u] = %p (%p)\n", __func__,
2140 sc->sc_bhalq, (caddr_t)bf->bf_daddr, bf->bf_desc);
2142 sc->sc_stats.ast_be_xmit++;
2146 * Reset the hardware after detecting beacons have stopped.
2149 ath_bstuck_proc(struct ath_softc *sc)
2151 struct ifnet *ifp = &sc->sc_ic.ic_if;
2153 if_printf(ifp, "stuck beacon; resetting (bmiss count %u)\n",
2159 * Reclaim beacon resources.
2162 ath_beacon_free(struct ath_softc *sc)
2166 ASSERT_SERIALIZED(sc->sc_ic.ic_if.if_serializer);
2168 STAILQ_FOREACH(bf, &sc->sc_bbuf, bf_list) {
2169 if (bf->bf_m != NULL) {
2170 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap);
2174 if (bf->bf_node != NULL) {
2175 ieee80211_free_node(bf->bf_node);
2182 * Configure the beacon and sleep timers.
2184 * When operating as an AP this resets the TSF and sets
2185 * up the hardware to notify us when we need to issue beacons.
2187 * When operating in station mode this sets up the beacon
2188 * timers according to the timestamp of the last received
2189 * beacon and the current TSF, configures PCF and DTIM
2190 * handling, programs the sleep registers so the hardware
2191 * will wakeup in time to receive beacons, and configures
2192 * the beacon miss handling so we'll receive a BMISS
2193 * interrupt when we stop seeing beacons from the AP
2194 * we've associated with.
2197 ath_beacon_config(struct ath_softc *sc)
2199 #define TSF_TO_TU(_h,_l) \
2200 ((((uint32_t)(_h)) << 22) | (((uint32_t)(_l)) >> 10))
2202 struct ath_hal *ah = sc->sc_ah;
2203 struct ieee80211com *ic = &sc->sc_ic;
2204 struct ieee80211_node *ni = ic->ic_bss;
2205 uint32_t nexttbtt, intval, tsftu;
2208 /* extract tstamp from last beacon and convert to TU */
2209 nexttbtt = TSF_TO_TU(LE_READ_4(ni->ni_tstamp.data + 4),
2210 LE_READ_4(ni->ni_tstamp.data));
2211 /* NB: the beacon interval is kept internally in TU's */
2212 intval = ni->ni_intval & HAL_BEACON_PERIOD;
2213 if (nexttbtt == 0) /* e.g. for ap mode */
2215 else if (intval) /* NB: can be 0 for monitor mode */
2216 nexttbtt = roundup(nexttbtt, intval);
2217 DPRINTF(sc, ATH_DEBUG_BEACON, "%s: nexttbtt %u intval %u (%u)\n",
2218 __func__, nexttbtt, intval, ni->ni_intval);
2219 if (ic->ic_opmode == IEEE80211_M_STA) {
2220 HAL_BEACON_STATE bs;
2221 int dtimperiod, dtimcount;
2222 int cfpperiod, cfpcount;
2225 * Setup dtim and cfp parameters according to
2226 * last beacon we received (which may be none).
2228 dtimperiod = ni->ni_dtim_period;
2229 if (dtimperiod <= 0) /* NB: 0 if not known */
2231 dtimcount = ni->ni_dtim_count;
2232 if (dtimcount >= dtimperiod) /* NB: sanity check */
2233 dtimcount = 0; /* XXX? */
2234 cfpperiod = 1; /* NB: no PCF support yet */
2237 * Pull nexttbtt forward to reflect the current
2238 * TSF and calculate dtim+cfp state for the result.
2240 tsf = ath_hal_gettsf64(ah);
2241 tsftu = TSF_TO_TU(tsf>>32, tsf) + FUDGE;
2244 if (--dtimcount < 0) {
2245 dtimcount = dtimperiod - 1;
2247 cfpcount = cfpperiod - 1;
2249 } while (nexttbtt < tsftu);
2250 memset(&bs, 0, sizeof(bs));
2251 bs.bs_intval = intval;
2252 bs.bs_nexttbtt = nexttbtt;
2253 bs.bs_dtimperiod = dtimperiod*intval;
2254 bs.bs_nextdtim = bs.bs_nexttbtt + dtimcount*intval;
2255 bs.bs_cfpperiod = cfpperiod*bs.bs_dtimperiod;
2256 bs.bs_cfpnext = bs.bs_nextdtim + cfpcount*bs.bs_dtimperiod;
2257 bs.bs_cfpmaxduration = 0;
2260 * The 802.11 layer records the offset to the DTIM
2261 * bitmap while receiving beacons; use it here to
2262 * enable h/w detection of our AID being marked in
2263 * the bitmap vector (to indicate frames for us are
2264 * pending at the AP).
2265 * XXX do DTIM handling in s/w to WAR old h/w bugs
2266 * XXX enable based on h/w rev for newer chips
2268 bs.bs_timoffset = ni->ni_timoff;
2271 * Calculate the number of consecutive beacons to miss
2272 * before taking a BMISS interrupt. The configuration
2273 * is specified in ms, so we need to convert that to
2274 * TU's and then calculate based on the beacon interval.
2275 * Note that we clamp the result to at most 10 beacons.
2277 bs.bs_bmissthreshold = ic->ic_bmissthreshold;
2278 if (bs.bs_bmissthreshold > 10)
2279 bs.bs_bmissthreshold = 10;
2280 else if (bs.bs_bmissthreshold <= 0)
2281 bs.bs_bmissthreshold = 1;
2284 * Calculate sleep duration. The configuration is
2285 * given in ms. We insure a multiple of the beacon
2286 * period is used. Also, if the sleep duration is
2287 * greater than the DTIM period then it makes senses
2288 * to make it a multiple of that.
2290 * XXX fixed at 100ms
2292 bs.bs_sleepduration =
2293 roundup(IEEE80211_MS_TO_TU(100), bs.bs_intval);
2294 if (bs.bs_sleepduration > bs.bs_dtimperiod)
2295 bs.bs_sleepduration = roundup(bs.bs_sleepduration, bs.bs_dtimperiod);
2297 DPRINTF(sc, ATH_DEBUG_BEACON,
2298 "%s: tsf %ju tsf:tu %u intval %u nexttbtt %u dtim %u nextdtim %u bmiss %u sleep %u cfp:period %u maxdur %u next %u timoffset %u\n"
2305 , bs.bs_bmissthreshold
2306 , bs.bs_sleepduration
2308 , bs.bs_cfpmaxduration
2312 ath_hal_intrset(ah, 0);
2313 ath_hal_beacontimers(ah, &bs);
2314 sc->sc_imask |= HAL_INT_BMISS;
2315 ath_hal_intrset(ah, sc->sc_imask);
2317 ath_hal_intrset(ah, 0);
2318 if (nexttbtt == intval)
2319 intval |= HAL_BEACON_RESET_TSF;
2320 if (ic->ic_opmode == IEEE80211_M_IBSS) {
2322 * In IBSS mode enable the beacon timers but only
2323 * enable SWBA interrupts if we need to manually
2324 * prepare beacon frames. Otherwise we use a
2325 * self-linked tx descriptor and let the hardware
2328 intval |= HAL_BEACON_ENA;
2329 if (!sc->sc_hasveol)
2330 sc->sc_imask |= HAL_INT_SWBA;
2331 if ((intval & HAL_BEACON_RESET_TSF) == 0) {
2333 * Pull nexttbtt forward to reflect
2336 tsf = ath_hal_gettsf64(ah);
2337 tsftu = TSF_TO_TU(tsf>>32, tsf) + FUDGE;
2340 } while (nexttbtt < tsftu);
2342 ath_beaconq_config(sc);
2343 } else if (ic->ic_opmode == IEEE80211_M_HOSTAP) {
2345 * In AP mode we enable the beacon timers and
2346 * SWBA interrupts to prepare beacon frames.
2348 intval |= HAL_BEACON_ENA;
2349 sc->sc_imask |= HAL_INT_SWBA; /* beacon prepare */
2350 ath_beaconq_config(sc);
2352 ath_hal_beaconinit(ah, nexttbtt, intval);
2353 sc->sc_bmisscount = 0;
2354 ath_hal_intrset(ah, sc->sc_imask);
2356 * When using a self-linked beacon descriptor in
2357 * ibss mode load it once here.
2359 if (ic->ic_opmode == IEEE80211_M_IBSS && sc->sc_hasveol)
2360 ath_beacon_proc(sc);
2362 sc->sc_syncbeacon = 0;
2368 ath_load_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
2370 bus_addr_t *paddr = (bus_addr_t*) arg;
2371 KASSERT(error == 0, ("error %u on bus_dma callback", error));
2372 *paddr = segs->ds_addr;
2376 ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
2377 ath_bufhead *head, const char *name, int nbuf, int ndesc)
2379 #define DS2PHYS(_dd, _ds) \
2380 ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc))
2381 struct ifnet *ifp = &sc->sc_ic.ic_if;
2382 struct ath_desc *ds;
2384 int i, bsize, error;
2386 DPRINTF(sc, ATH_DEBUG_RESET, "%s: %s DMA: %u buffers %u desc/buf\n",
2387 __func__, name, nbuf, ndesc);
2390 dd->dd_desc_len = sizeof(struct ath_desc) * nbuf * ndesc;
2394 * Setup DMA descriptor area.
2396 error = bus_dma_tag_create(NULL, /* parent */
2397 PAGE_SIZE, 0, /* alignment, bounds */
2398 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
2399 BUS_SPACE_MAXADDR, /* highaddr */
2400 NULL, NULL, /* filter, filterarg */
2401 dd->dd_desc_len, /* maxsize */
2403 BUS_SPACE_MAXADDR, /* maxsegsize */
2404 BUS_DMA_ALLOCNOW, /* flags */
2407 if_printf(ifp, "cannot allocate %s DMA tag\n", dd->dd_name);
2411 /* allocate descriptors */
2412 error = bus_dmamap_create(dd->dd_dmat, BUS_DMA_WAITOK, &dd->dd_dmamap);
2414 if_printf(ifp, "unable to create dmamap for %s descriptors, "
2415 "error %u\n", dd->dd_name, error);
2419 error = bus_dmamem_alloc(dd->dd_dmat, (void **)&dd->dd_desc,
2420 BUS_DMA_WAITOK, &dd->dd_dmamap);
2422 if_printf(ifp, "unable to alloc memory for %u %s descriptors, "
2423 "error %u\n", nbuf * ndesc, dd->dd_name, error);
2427 error = bus_dmamap_load(dd->dd_dmat, dd->dd_dmamap,
2428 dd->dd_desc, dd->dd_desc_len,
2429 ath_load_cb, &dd->dd_desc_paddr,
2432 if_printf(ifp, "unable to map %s descriptors, error %u\n",
2433 dd->dd_name, error);
2435 bus_dmamem_free(dd->dd_dmat, dd->dd_desc, dd->dd_dmamap);
2441 DPRINTF(sc, ATH_DEBUG_RESET, "%s: %s DMA map: %p (%lu) -> %p (%lu)\n",
2442 __func__, dd->dd_name, ds, (u_long) dd->dd_desc_len,
2443 (caddr_t) dd->dd_desc_paddr, /*XXX*/ (u_long) dd->dd_desc_len);
2445 /* allocate rx buffers */
2446 bsize = sizeof(struct ath_buf) * nbuf;
2447 bf = kmalloc(bsize, M_ATHDEV, M_WAITOK | M_ZERO);
2450 for (i = 0; i < nbuf; i++, bf++, ds += ndesc) {
2452 bf->bf_daddr = DS2PHYS(dd, ds);
2453 error = bus_dmamap_create(sc->sc_dmat, BUS_DMA_WAITOK,
2456 if_printf(ifp, "unable to create dmamap for %s "
2457 "buffer %u, error %u\n", dd->dd_name, i, error);
2458 ath_descdma_cleanup(sc, dd, head);
2461 STAILQ_INSERT_TAIL(head, bf, bf_list);
2467 bus_dmamap_unload(dd->dd_dmat, dd->dd_dmamap);
2469 bus_dmamem_free(dd->dd_dmat, dd->dd_desc, dd->dd_dmamap);
2471 bus_dmamap_destroy(dd->dd_dmat, dd->dd_dmamap);
2473 bus_dma_tag_destroy(dd->dd_dmat);
2474 memset(dd, 0, sizeof(*dd));
2481 ath_descdma_cleanup(struct ath_softc *sc,
2482 struct ath_descdma *dd, ath_bufhead *head)
2485 struct ieee80211_node *ni;
2487 if (dd->dd_desc != NULL) {
2488 bus_dmamap_unload(dd->dd_dmat, dd->dd_dmamap);
2489 bus_dmamem_free(dd->dd_dmat, dd->dd_desc, dd->dd_dmamap);
2493 if (dd->dd_dmamap != NULL) {
2494 bus_dmamap_destroy(dd->dd_dmat, dd->dd_dmamap);
2495 dd->dd_dmamap = NULL;
2498 if (dd->dd_dmat != NULL) {
2499 bus_dma_tag_destroy(dd->dd_dmat);
2503 STAILQ_FOREACH(bf, head, bf_list) {
2508 if (bf->bf_dmamap != NULL) {
2509 bus_dmamap_destroy(sc->sc_dmat, bf->bf_dmamap);
2510 bf->bf_dmamap = NULL;
2516 * Reclaim node reference.
2518 ieee80211_free_node(ni);
2523 if (dd->dd_bufptr != NULL)
2524 kfree(dd->dd_bufptr, M_ATHDEV);
2525 memset(dd, 0, sizeof(*dd));
2529 ath_desc_alloc(struct ath_softc *sc)
2533 error = ath_descdma_setup(sc, &sc->sc_rxdma, &sc->sc_rxbuf,
2534 "rx", ath_rxbuf, 1);
2538 error = ath_descdma_setup(sc, &sc->sc_txdma, &sc->sc_txbuf,
2539 "tx", ath_txbuf, ATH_TXDESC);
2543 error = ath_descdma_setup(sc, &sc->sc_bdma, &sc->sc_bbuf,
2551 ath_desc_free(struct ath_softc *sc)
2554 if (sc->sc_bdma.dd_desc_len != 0) {
2555 ath_descdma_cleanup(sc, &sc->sc_bdma, &sc->sc_bbuf);
2556 sc->sc_bdma.dd_desc_len = 0;
2558 if (sc->sc_txdma.dd_desc_len != 0) {
2559 ath_descdma_cleanup(sc, &sc->sc_txdma, &sc->sc_txbuf);
2560 sc->sc_txdma.dd_desc_len = 0;
2562 if (sc->sc_rxdma.dd_desc_len != 0) {
2563 ath_descdma_cleanup(sc, &sc->sc_rxdma, &sc->sc_rxbuf);
2564 sc->sc_rxdma.dd_desc_len = 0;
2568 static struct ieee80211_node *
2569 ath_node_alloc(struct ieee80211_node_table *nt)
2571 struct ieee80211com *ic = nt->nt_ic;
2572 struct ath_softc *sc = ic->ic_ifp->if_softc;
2573 const size_t space = sizeof(struct ath_node) + sc->sc_rc->arc_space;
2574 struct ath_node *an;
2576 an = kmalloc(space, M_80211_NODE, M_NOWAIT|M_ZERO);
2581 an->an_avgrssi = ATH_RSSI_DUMMY_MARKER;
2582 ath_rate_node_init(sc, an);
2584 DPRINTF(sc, ATH_DEBUG_NODE, "%s: an %p\n", __func__, an);
2585 return &an->an_node;
2589 ath_node_free(struct ieee80211_node *ni)
2591 struct ieee80211com *ic = ni->ni_ic;
2592 struct ath_softc *sc = ic->ic_ifp->if_softc;
2594 DPRINTF(sc, ATH_DEBUG_NODE, "%s: ni %p\n", __func__, ni);
2596 ath_rate_node_cleanup(sc, ATH_NODE(ni));
2597 sc->sc_node_free(ni);
2601 ath_node_getrssi(const struct ieee80211_node *ni)
2603 #define HAL_EP_RND(x, mul) \
2604 ((((x)%(mul)) >= ((mul)/2)) ? ((x) + ((mul) - 1)) / (mul) : (x)/(mul))
2605 uint32_t avgrssi = ATH_NODE_CONST(ni)->an_avgrssi;
2609 * When only one frame is received there will be no state in
2610 * avgrssi so fallback on the value recorded by the 802.11 layer.
2612 if (avgrssi != ATH_RSSI_DUMMY_MARKER)
2613 rssi = HAL_EP_RND(avgrssi, HAL_RSSI_EP_MULTIPLIER);
2616 /* NB: theoretically we shouldn't need this, but be paranoid */
2617 return rssi < 0 ? 0 : rssi > 127 ? 127 : rssi;
2622 ath_rxbuf_init(struct ath_softc *sc, struct ath_buf *bf)
2624 struct ath_hal *ah = sc->sc_ah;
2627 struct ath_desc *ds;
2632 * NB: by assigning a page to the rx dma buffer we
2633 * implicitly satisfy the Atheros requirement that
2634 * this buffer be cache-line-aligned and sized to be
2635 * multiple of the cache line size. Not doing this
2636 * causes weird stuff to happen (for the 5210 at least).
2638 m = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR);
2640 DPRINTF(sc, ATH_DEBUG_ANY,
2641 "%s: no mbuf/cluster\n", __func__);
2642 sc->sc_stats.ast_rx_nombuf++;
2645 m->m_pkthdr.len = m->m_len = m->m_ext.ext_size;
2647 error = bus_dmamap_load_mbuf(sc->sc_dmat, bf->bf_dmamap, m,
2648 ath_dma_map_mbuf, bf,
2651 DPRINTF(sc, ATH_DEBUG_ANY,
2652 "%s: bus_dmamap_load_mbuf failed; error %d\n",
2654 sc->sc_stats.ast_rx_busdma++;
2658 KASSERT(bf->bf_nseg == 1,
2659 ("multi-segment packet; nseg %u", bf->bf_nseg));
2662 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, BUS_DMASYNC_PREREAD);
2665 * Setup descriptors. For receive we always terminate
2666 * the descriptor list with a self-linked entry so we'll
2667 * not get overrun under high load (as can happen with a
2668 * 5212 when ANI processing enables PHY error frames).
2670 * To insure the last descriptor is self-linked we create
2671 * each descriptor as self-linked and add it to the end. As
2672 * each additional descriptor is added the previous self-linked
2673 * entry is ``fixed'' naturally. This should be safe even
2674 * if DMA is happening. When processing RX interrupts we
2675 * never remove/process the last, self-linked, entry on the
2676 * descriptor list. This insures the hardware always has
2677 * someplace to write a new frame.
2680 ds->ds_link = bf->bf_daddr; /* link to self */
2681 ds->ds_data = bf->bf_segs[0].ds_addr;
2682 ds->ds_vdata = mtod(m, void *); /* for radar */
2683 ath_hal_setuprxdesc(ah, ds
2684 , m->m_len /* buffer size */
2688 if (sc->sc_rxlink != NULL)
2689 *sc->sc_rxlink = bf->bf_daddr;
2690 sc->sc_rxlink = &ds->ds_link;
2695 * Extend 15-bit time stamp from rx descriptor to
2696 * a full 64-bit TSF using the specified TSF.
2698 static __inline uint64_t
2699 ath_extend_tsf(uint32_t rstamp, uint64_t tsf)
2701 if ((tsf & 0x7fff) < rstamp)
2703 return ((tsf &~ 0x7fff) | rstamp);
2707 * Intercept management frames to collect beacon rssi data
2708 * and to do ibss merges.
2711 ath_recv_mgmt(struct ieee80211com *ic, struct mbuf *m,
2712 struct ieee80211_node *ni,
2713 int subtype, int rssi, uint32_t rstamp)
2715 struct ath_softc *sc = ic->ic_ifp->if_softc;
2718 * Call up first so subsequent work can use information
2719 * potentially stored in the node (e.g. for ibss merge).
2721 sc->sc_recv_mgmt(ic, m, ni, subtype, rssi, rstamp);
2723 case IEEE80211_FC0_SUBTYPE_BEACON:
2724 /* update rssi statistics for use by the hal */
2725 ATH_RSSI_LPF(sc->sc_halstats.ns_avgbrssi, rssi);
2726 if (sc->sc_syncbeacon &&
2727 ni == ic->ic_bss && ic->ic_state == IEEE80211_S_RUN) {
2729 * Resync beacon timers using the tsf of the beacon
2730 * frame we just received.
2732 ath_beacon_config(sc);
2735 case IEEE80211_FC0_SUBTYPE_PROBE_RESP:
2736 if (ic->ic_opmode == IEEE80211_M_IBSS &&
2737 ic->ic_state == IEEE80211_S_RUN) {
2738 uint64_t tsf = ath_extend_tsf(rstamp,
2739 ath_hal_gettsf64(sc->sc_ah));
2741 * Handle ibss merge as needed; check the tsf on the
2742 * frame before attempting the merge. The 802.11 spec
2743 * says the station should change it's bssid to match
2744 * the oldest station with the same ssid, where oldest
2745 * is determined by the tsf. Note that hardware
2746 * reconfiguration happens through callback to
2747 * ath_newstate as the state machine will go from
2748 * RUN -> RUN when this happens.
2750 if (le64toh(ni->ni_tstamp.tsf) >= tsf) {
2751 DPRINTF(sc, ATH_DEBUG_STATE,
2752 "ibss merge, rstamp %u tsf %ju "
2753 "tstamp %ju\n", rstamp, (uintmax_t)tsf,
2754 (uintmax_t)ni->ni_tstamp.tsf);
2755 ieee80211_ibss_merge(ni);
2763 * Set the default antenna.
2766 ath_setdefantenna(struct ath_softc *sc, u_int antenna)
2768 struct ath_hal *ah = sc->sc_ah;
2770 /* XXX block beacon interrupts */
2771 ath_hal_setdefantenna(ah, antenna);
2772 if (sc->sc_defant != antenna)
2773 sc->sc_stats.ast_ant_defswitch++;
2774 sc->sc_defant = antenna;
2775 sc->sc_rxotherant = 0;
2779 ath_rx_tap(struct ath_softc *sc, struct mbuf *m,
2780 const struct ath_desc *ds, uint64_t tsf, int16_t nf)
2784 KASSERT(sc->sc_drvbpf != NULL, ("no tap"));
2787 * Discard anything shorter than an ack or cts.
2789 if (m->m_pkthdr.len < IEEE80211_ACK_LEN) {
2790 DPRINTF(sc, ATH_DEBUG_RECV, "%s: runt packet %d\n",
2791 __func__, m->m_pkthdr.len);
2792 sc->sc_stats.ast_rx_tooshort++;
2795 sc->sc_rx_th.wr_tsf = htole64(
2796 ath_extend_tsf(ds->ds_rxstat.rs_tstamp, tsf));
2797 rix = ds->ds_rxstat.rs_rate;
2798 sc->sc_rx_th.wr_flags = sc->sc_hwmap[rix].rxflags;
2799 if (ds->ds_rxstat.rs_status & HAL_RXERR_CRC)
2800 sc->sc_rx_th.wr_flags |= IEEE80211_RADIOTAP_F_BADFCS;
2801 /* XXX propagate other error flags from descriptor */
2802 sc->sc_rx_th.wr_rate = sc->sc_hwmap[rix].ieeerate;
2803 sc->sc_rx_th.wr_antsignal = ds->ds_rxstat.rs_rssi + nf;
2804 sc->sc_rx_th.wr_antnoise = nf;
2805 sc->sc_rx_th.wr_antenna = ds->ds_rxstat.rs_antenna;
2807 bpf_ptap(sc->sc_drvbpf, m, &sc->sc_rx_th, sc->sc_rx_th_len);
2813 ath_rx_proc(struct ath_softc *sc)
2815 #define PA2DESC(_sc, _pa) \
2816 ((struct ath_desc *)((caddr_t)(_sc)->sc_rxdma.dd_desc + \
2817 ((_pa) - (_sc)->sc_rxdma.dd_desc_paddr)))
2819 struct ieee80211com *ic = &sc->sc_ic;
2820 struct ifnet *ifp = &ic->ic_if;
2821 struct ath_hal *ah = sc->sc_ah;
2822 struct ath_desc *ds;
2824 struct ieee80211_node *ni;
2825 struct ath_node *an;
2826 int len, type, ngood;
2833 nf = ath_hal_getchannoise(ah, &sc->sc_curchan);
2834 tsf = ath_hal_gettsf64(ah);
2836 bf = STAILQ_FIRST(&sc->sc_rxbuf);
2837 if (bf == NULL) { /* NB: shouldn't happen */
2838 if_printf(ifp, "%s: no buffer!\n", __func__);
2842 if (m == NULL) { /* NB: shouldn't happen */
2844 * If mbuf allocation failed previously there
2845 * will be no mbuf; try again to re-populate it.
2847 /* XXX make debug msg */
2848 if_printf(ifp, "%s: no mbuf!\n", __func__);
2849 STAILQ_REMOVE_HEAD(&sc->sc_rxbuf, bf_list);
2853 if (ds->ds_link == bf->bf_daddr) {
2854 /* NB: never process the self-linked entry at the end */
2857 /* XXX sync descriptor memory */
2859 * Must provide the virtual address of the current
2860 * descriptor, the physical address, and the virtual
2861 * address of the next descriptor in the h/w chain.
2862 * This allows the HAL to look ahead to see if the
2863 * hardware is done with a descriptor by checking the
2864 * done bit in the following descriptor and the address
2865 * of the current descriptor the DMA engine is working
2866 * on. All this is necessary because of our use of
2867 * a self-linked list to avoid rx overruns.
2869 status = ath_hal_rxprocdesc(ah, ds,
2870 bf->bf_daddr, PA2DESC(sc, ds->ds_link));
2872 if (sc->sc_debug & ATH_DEBUG_RECV_DESC)
2873 ath_printrxbuf(bf, 0, status == HAL_OK);
2875 if (status == HAL_EINPROGRESS)
2877 STAILQ_REMOVE_HEAD(&sc->sc_rxbuf, bf_list);
2878 if (ds->ds_rxstat.rs_more) {
2880 * Frame spans multiple descriptors; this
2881 * cannot happen yet as we don't support
2882 * jumbograms. If not in monitor mode,
2883 * discard the frame.
2885 if (ic->ic_opmode != IEEE80211_M_MONITOR) {
2886 sc->sc_stats.ast_rx_toobig++;
2889 /* fall thru for monitor mode handling... */
2890 } else if (ds->ds_rxstat.rs_status != 0) {
2891 if (ds->ds_rxstat.rs_status & HAL_RXERR_CRC)
2892 sc->sc_stats.ast_rx_crcerr++;
2893 if (ds->ds_rxstat.rs_status & HAL_RXERR_FIFO)
2894 sc->sc_stats.ast_rx_fifoerr++;
2895 if (ds->ds_rxstat.rs_status & HAL_RXERR_PHY) {
2896 sc->sc_stats.ast_rx_phyerr++;
2897 phyerr = ds->ds_rxstat.rs_phyerr & 0x1f;
2898 sc->sc_stats.ast_rx_phy[phyerr]++;
2901 if (ds->ds_rxstat.rs_status & HAL_RXERR_DECRYPT) {
2903 * Decrypt error. If the error occurred
2904 * because there was no hardware key, then
2905 * let the frame through so the upper layers
2906 * can process it. This is necessary for 5210
2907 * parts which have no way to setup a ``clear''
2910 * XXX do key cache faulting
2912 if (ds->ds_rxstat.rs_keyix == HAL_RXKEYIX_INVALID)
2914 sc->sc_stats.ast_rx_badcrypt++;
2916 if (ds->ds_rxstat.rs_status & HAL_RXERR_MIC) {
2917 sc->sc_stats.ast_rx_badmic++;
2919 * Do minimal work required to hand off
2920 * the 802.11 header for notifcation.
2922 /* XXX frag's and qos frames */
2923 len = ds->ds_rxstat.rs_datalen;
2924 if (len >= sizeof (struct ieee80211_frame)) {
2925 bus_dmamap_sync(sc->sc_dmat,
2927 BUS_DMASYNC_POSTREAD);
2928 ieee80211_notify_michael_failure(ic,
2929 mtod(m, struct ieee80211_frame *),
2931 ds->ds_rxstat.rs_keyix-32 :
2932 ds->ds_rxstat.rs_keyix
2938 * When a tap is present pass error frames
2939 * that have been requested. By default we
2940 * pass decrypt+mic errors but others may be
2941 * interesting (e.g. crc).
2943 if (sc->sc_drvbpf != NULL &&
2944 (ds->ds_rxstat.rs_status & sc->sc_monpass)) {
2945 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap,
2946 BUS_DMASYNC_POSTREAD);
2947 /* NB: bpf needs the mbuf length setup */
2948 len = ds->ds_rxstat.rs_datalen;
2949 m->m_pkthdr.len = m->m_len = len;
2950 ath_rx_tap(sc, m, ds, tsf, nf);
2952 /* XXX pass MIC errors up for s/w reclaculation */
2957 * Sync and unmap the frame. At this point we're
2958 * committed to passing the mbuf somewhere so clear
2959 * bf_m; this means a new sk_buff must be allocated
2960 * when the rx descriptor is setup again to receive
2963 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap,
2964 BUS_DMASYNC_POSTREAD);
2965 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap);
2968 m->m_pkthdr.rcvif = ifp;
2969 len = ds->ds_rxstat.rs_datalen;
2970 m->m_pkthdr.len = m->m_len = len;
2972 sc->sc_stats.ast_ant_rx[ds->ds_rxstat.rs_antenna]++;
2974 if (sc->sc_drvbpf != NULL && !ath_rx_tap(sc, m, ds, tsf, nf)) {
2975 m_freem(m); /* XXX reclaim */
2980 * From this point on we assume the frame is at least
2981 * as large as ieee80211_frame_min; verify that.
2983 if (len < IEEE80211_MIN_LEN) {
2984 DPRINTF(sc, ATH_DEBUG_RECV, "%s: short packet %d\n",
2986 sc->sc_stats.ast_rx_tooshort++;
2991 if (IFF_DUMPPKTS(sc, ATH_DEBUG_RECV)) {
2992 ieee80211_dump_pkt(mtod(m, caddr_t), len,
2993 sc->sc_hwmap[ds->ds_rxstat.rs_rate].ieeerate,
2994 ds->ds_rxstat.rs_rssi);
2997 m_adj(m, -IEEE80211_CRC_LEN);
3000 * Locate the node for sender, track state, and then
3001 * pass the (referenced) node up to the 802.11 layer
3004 ni = ieee80211_find_rxnode_withkey(ic,
3005 mtod(m, const struct ieee80211_frame_min *),
3006 ds->ds_rxstat.rs_keyix == HAL_RXKEYIX_INVALID ?
3007 IEEE80211_KEYIX_NONE : ds->ds_rxstat.rs_keyix);
3009 * Track rx rssi and do any rx antenna management.
3012 ATH_RSSI_LPF(an->an_avgrssi, ds->ds_rxstat.rs_rssi);
3013 ATH_RSSI_LPF(sc->sc_halstats.ns_avgrssi, ds->ds_rxstat.rs_rssi);
3015 * Send frame up for processing.
3017 type = ieee80211_input(ic, m, ni,
3018 ds->ds_rxstat.rs_rssi, ds->ds_rxstat.rs_tstamp);
3019 ieee80211_free_node(ni);
3020 if (sc->sc_diversity) {
3022 * When using fast diversity, change the default rx
3023 * antenna if diversity chooses the other antenna 3
3026 if (sc->sc_defant != ds->ds_rxstat.rs_antenna) {
3027 if (++sc->sc_rxotherant >= 3)
3028 ath_setdefantenna(sc,
3029 ds->ds_rxstat.rs_antenna);
3031 sc->sc_rxotherant = 0;
3033 if (sc->sc_softled) {
3035 * Blink for any data frame. Otherwise do a
3036 * heartbeat-style blink when idle. The latter
3037 * is mainly for station mode where we depend on
3038 * periodic beacon frames to trigger the poll event.
3040 if (type == IEEE80211_FC0_TYPE_DATA) {
3041 sc->sc_rxrate = ds->ds_rxstat.rs_rate;
3042 ath_led_event(sc, ATH_LED_RX);
3043 } else if (ticks - sc->sc_ledevent >= sc->sc_ledidle)
3044 ath_led_event(sc, ATH_LED_POLL);
3047 * Arrange to update the last rx timestamp only for
3048 * frames from our ap when operating in station mode.
3049 * This assumes the rx key is always setup when associated.
3051 if (ic->ic_opmode == IEEE80211_M_STA &&
3052 ds->ds_rxstat.rs_keyix != HAL_RXKEYIX_INVALID)
3055 STAILQ_INSERT_TAIL(&sc->sc_rxbuf, bf, bf_list);
3056 } while (ath_rxbuf_init(sc, bf) == 0);
3058 /* rx signal state monitoring */
3059 ath_hal_rxmonitor(ah, &sc->sc_halstats, &sc->sc_curchan);
3060 if (ath_hal_radar_event(ah))
3063 sc->sc_lastrx = tsf;
3068 * Setup a h/w transmit queue.
3070 static struct ath_txq *
3071 ath_txq_setup(struct ath_softc *sc, int qtype, int subtype)
3073 #define N(a) (sizeof(a)/sizeof(a[0]))
3074 struct ath_hal *ah = sc->sc_ah;
3078 memset(&qi, 0, sizeof(qi));
3079 qi.tqi_subtype = subtype;
3080 qi.tqi_aifs = HAL_TXQ_USEDEFAULT;
3081 qi.tqi_cwmin = HAL_TXQ_USEDEFAULT;
3082 qi.tqi_cwmax = HAL_TXQ_USEDEFAULT;
3084 * Enable interrupts only for EOL and DESC conditions.
3085 * We mark tx descriptors to receive a DESC interrupt
3086 * when a tx queue gets deep; otherwise waiting for the
3087 * EOL to reap descriptors. Note that this is done to
3088 * reduce interrupt load and this only defers reaping
3089 * descriptors, never transmitting frames. Aside from
3090 * reducing interrupts this also permits more concurrency.
3091 * The only potential downside is if the tx queue backs
3092 * up in which case the top half of the kernel may backup
3093 * due to a lack of tx descriptors.
3095 qi.tqi_qflags = HAL_TXQ_TXEOLINT_ENABLE | HAL_TXQ_TXDESCINT_ENABLE;
3096 qnum = ath_hal_setuptxqueue(ah, qtype, &qi);
3099 * NB: don't print a message, this happens
3100 * normally on parts with too few tx queues
3104 if (qnum >= N(sc->sc_txq)) {
3105 device_printf(sc->sc_dev,
3106 "hal qnum %u out of range, max %zu!\n",
3107 qnum, N(sc->sc_txq));
3108 ath_hal_releasetxqueue(ah, qnum);
3111 if (!IS_ATH_TXQ_SETUP(sc, qnum)) {
3112 struct ath_txq *txq = &sc->sc_txq[qnum];
3114 txq->axq_qnum = qnum;
3116 txq->axq_intrcnt = 0;
3117 txq->axq_link = NULL;
3118 STAILQ_INIT(&txq->axq_q);
3119 ATH_TXQ_SETUP(sc, qnum);
3121 return &sc->sc_txq[qnum];
3126 * Setup a hardware data transmit queue for the specified
3127 * access control. The hal may not support all requested
3128 * queues in which case it will return a reference to a
3129 * previously setup queue. We record the mapping from ac's
3130 * to h/w queues for use by ath_tx_start and also track
3131 * the set of h/w queues being used to optimize work in the
3132 * transmit interrupt handler and related routines.
3135 ath_tx_setup(struct ath_softc *sc, int ac, int haltype)
3137 #define N(a) (sizeof(a)/sizeof(a[0]))
3138 struct ath_txq *txq;
3140 if (ac >= N(sc->sc_ac2q)) {
3141 device_printf(sc->sc_dev, "AC %u out of range, max %zu!\n",
3142 ac, N(sc->sc_ac2q));
3145 txq = ath_txq_setup(sc, HAL_TX_QUEUE_DATA, haltype);
3147 sc->sc_ac2q[ac] = txq;
3156 * Update WME parameters for a transmit queue.
3159 ath_txq_update(struct ath_softc *sc, int ac)
3161 #define ATH_EXPONENT_TO_VALUE(v) ((1<<v)-1)
3162 #define ATH_TXOP_TO_US(v) (v<<5)
3163 struct ieee80211com *ic = &sc->sc_ic;
3164 struct ath_txq *txq = sc->sc_ac2q[ac];
3165 struct wmeParams *wmep = &ic->ic_wme.wme_chanParams.cap_wmeParams[ac];
3166 struct ath_hal *ah = sc->sc_ah;
3169 ath_hal_gettxqueueprops(ah, txq->axq_qnum, &qi);
3170 qi.tqi_aifs = wmep->wmep_aifsn;
3171 qi.tqi_cwmin = ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmin);
3172 qi.tqi_cwmax = ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmax);
3173 qi.tqi_burstTime = ATH_TXOP_TO_US(wmep->wmep_txopLimit);
3175 if (!ath_hal_settxqueueprops(ah, txq->axq_qnum, &qi)) {
3176 device_printf(sc->sc_dev, "unable to update hardware queue "
3177 "parameters for %s traffic!\n",
3178 ieee80211_wme_acnames[ac]);
3181 ath_hal_resettxqueue(ah, txq->axq_qnum); /* push to h/w */
3184 #undef ATH_TXOP_TO_US
3185 #undef ATH_EXPONENT_TO_VALUE
3189 * Callback from the 802.11 layer to update WME parameters.
3192 ath_wme_update(struct ieee80211com *ic)
3194 struct ath_softc *sc = ic->ic_ifp->if_softc;
3196 return !ath_txq_update(sc, WME_AC_BE) ||
3197 !ath_txq_update(sc, WME_AC_BK) ||
3198 !ath_txq_update(sc, WME_AC_VI) ||
3199 !ath_txq_update(sc, WME_AC_VO) ? EIO : 0;
3203 * Reclaim resources for a setup queue.
3206 ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq)
3208 ath_hal_releasetxqueue(sc->sc_ah, txq->axq_qnum);
3209 sc->sc_txqsetup &= ~(1<<txq->axq_qnum);
3213 * Reclaim all tx queue resources.
3216 ath_tx_cleanup(struct ath_softc *sc)
3220 for (i = 0; i < HAL_NUM_TX_QUEUES; i++)
3221 if (IS_ATH_TXQ_SETUP(sc, i))
3222 ath_tx_cleanupq(sc, &sc->sc_txq[i]);
3226 * Defragment an mbuf chain, returning at most maxfrags separate
3227 * mbufs+clusters. If this is not possible NULL is returned and
3228 * the original mbuf chain is left in it's present (potentially
3229 * modified) state. We use two techniques: collapsing consecutive
3230 * mbufs and replacing consecutive mbufs by a cluster.
3232 static struct mbuf *
3233 ath_defrag(struct mbuf *m0, int how, int maxfrags)
3235 struct mbuf *m, *n, *n2, **prev;
3239 * Calculate the current number of frags.
3242 for (m = m0; m != NULL; m = m->m_next)
3245 * First, try to collapse mbufs. Note that we always collapse
3246 * towards the front so we don't need to deal with moving the
3247 * pkthdr. This may be suboptimal if the first mbuf has much
3248 * less data than the following.
3256 if (n->m_len < M_TRAILINGSPACE(m)) {
3257 bcopy(mtod(n, void *), mtod(m, char *) + m->m_len,
3259 m->m_len += n->m_len;
3260 m->m_next = n->m_next;
3262 if (--curfrags <= maxfrags)
3267 KASSERT(maxfrags > 1,
3268 ("maxfrags %u, but normal collapse failed", maxfrags));
3270 * Collapse consecutive mbufs to a cluster.
3272 prev = &m0->m_next; /* NB: not the first mbuf */
3273 while ((n = *prev) != NULL) {
3274 if ((n2 = n->m_next) != NULL &&
3275 n->m_len + n2->m_len < MCLBYTES) {
3276 m = m_getcl(how, MT_DATA, 0);
3279 bcopy(mtod(n, void *), mtod(m, void *), n->m_len);
3280 bcopy(mtod(n2, void *), mtod(m, char *) + n->m_len,
3282 m->m_len = n->m_len + n2->m_len;
3283 m->m_next = n2->m_next;
3287 if (--curfrags <= maxfrags) /* +1 cl -2 mbufs */
3290 * Still not there, try the normal collapse
3291 * again before we allocate another cluster.
3298 * No place where we can collapse to a cluster; punt.
3299 * This can occur if, for example, you request 2 frags
3300 * but the packet requires that both be clusters (we
3301 * never reallocate the first mbuf to avoid moving the
3309 * Return h/w rate index for an IEEE rate (w/o basic rate bit).
3312 ath_tx_findrix(const HAL_RATE_TABLE *rt, int rate)
3316 for (i = 0; i < rt->rateCount; i++)
3317 if ((rt->info[i].dot11Rate & IEEE80211_RATE_VAL) == rate)
3319 return 0; /* NB: lowest rate */
3323 ath_tx_start(struct ath_softc *sc, struct ieee80211_node *ni,
3324 struct ath_buf *bf, struct mbuf *m0)
3326 struct ieee80211com *ic = &sc->sc_ic;
3327 struct ath_hal *ah = sc->sc_ah;
3328 struct ifnet *ifp = &ic->ic_if;
3329 const struct chanAccParams *cap = &ic->ic_wme.wme_chanParams;
3330 int i, error, iswep, ismcast, ismrr;
3331 int keyix, hdrlen, pktlen, try0;
3332 uint8_t rix, txrate, ctsrate;
3333 uint8_t cix = 0xff; /* NB: silence compiler */
3334 struct ath_desc *ds, *ds0;
3335 struct ath_txq *txq;
3336 struct ieee80211_frame *wh;
3337 u_int subtype, flags, ctsduration;
3339 const HAL_RATE_TABLE *rt;
3340 HAL_BOOL shortPreamble;
3341 struct ath_node *an;
3345 wh = mtod(m0, struct ieee80211_frame *);
3346 iswep = wh->i_fc[1] & IEEE80211_FC1_WEP;
3347 ismcast = IEEE80211_IS_MULTICAST(wh->i_addr1);
3348 hdrlen = ieee80211_anyhdrsize(wh);
3350 * Packet length must not include any
3351 * pad bytes; deduct them here.
3353 pktlen = m0->m_pkthdr.len - (hdrlen & 3);
3356 const struct ieee80211_cipher *cip;
3357 struct ieee80211_key *k;
3360 * Construct the 802.11 header+trailer for an encrypted
3361 * frame. The only reason this can fail is because of an
3362 * unknown or unsupported cipher/key type.
3364 k = ieee80211_crypto_encap(ic, ni, m0);
3367 * This can happen when the key is yanked after the
3368 * frame was queued. Just discard the frame; the
3369 * 802.11 layer counts failures and provides
3370 * debugging/diagnostics.
3376 * Adjust the packet + header lengths for the crypto
3377 * additions and calculate the h/w key index. When
3378 * a s/w mic is done the frame will have had any mic
3379 * added to it prior to entry so m0->m_pkthdr.len above will
3380 * account for it. Otherwise we need to add it to the
3384 hdrlen += cip->ic_header;
3385 pktlen += cip->ic_header + cip->ic_trailer;
3386 if ((k->wk_flags & IEEE80211_KEY_SWMIC) == 0)
3387 pktlen += cip->ic_miclen;
3388 keyix = k->wk_keyix;
3390 /* packet header may have moved, reset our local pointer */
3391 wh = mtod(m0, struct ieee80211_frame *);
3392 } else if (ni->ni_ucastkey.wk_cipher == &ieee80211_cipher_none) {
3394 * Use station key cache slot, if assigned.
3396 keyix = ni->ni_ucastkey.wk_keyix;
3397 if (keyix == IEEE80211_KEYIX_NONE)
3398 keyix = HAL_TXKEYIX_INVALID;
3400 keyix = HAL_TXKEYIX_INVALID;
3402 pktlen += IEEE80211_CRC_LEN;
3405 * Load the DMA map so any coalescing is done. This
3406 * also calculates the number of descriptors we need.
3408 error = bus_dmamap_load_mbuf(sc->sc_dmat, bf->bf_dmamap, m0,
3409 ath_dma_map_mbuf, bf, BUS_DMA_NOWAIT);
3410 if (error == EFBIG) {
3411 /* XXX packet requires too many descriptors */
3412 bf->bf_nseg = ATH_TXDESC+1;
3413 } else if (error != 0) {
3414 sc->sc_stats.ast_tx_busdma++;
3419 * Discard null packets and check for packets that
3420 * require too many TX descriptors. We try to convert
3421 * the latter to a cluster.
3423 if (bf->bf_nseg > ATH_TXDESC) { /* too many desc's, linearize */
3424 sc->sc_stats.ast_tx_linear++;
3425 m = ath_defrag(m0, MB_DONTWAIT, ATH_TXDESC);
3428 sc->sc_stats.ast_tx_nombuf++;
3432 error = bus_dmamap_load_mbuf(sc->sc_dmat, bf->bf_dmamap, m0,
3433 ath_dma_map_mbuf, bf,
3436 sc->sc_stats.ast_tx_busdma++;
3440 KASSERT(bf->bf_nseg <= ATH_TXDESC,
3441 ("too many segments after defrag; nseg %u", bf->bf_nseg));
3442 } else if (bf->bf_nseg == 0) { /* null packet, discard */
3443 sc->sc_stats.ast_tx_nodata++;
3447 DPRINTF(sc, ATH_DEBUG_XMIT, "%s: m %p len %u\n", __func__, m0, pktlen);
3448 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, BUS_DMASYNC_PREWRITE);
3450 bf->bf_node = ni; /* NB: held reference */
3452 /* setup descriptors */
3454 rt = sc->sc_currates;
3455 KASSERT(rt != NULL, ("no rate table, mode %u", sc->sc_curmode));
3458 * NB: the 802.11 layer marks whether or not we should
3459 * use short preamble based on the current mode and
3460 * negotiated parameters.
3462 if ((ic->ic_flags & IEEE80211_F_SHPREAMBLE) &&
3463 (ni->ni_capinfo & IEEE80211_CAPINFO_SHORT_PREAMBLE)) {
3464 shortPreamble = AH_TRUE;
3465 sc->sc_stats.ast_tx_shortpre++;
3467 shortPreamble = AH_FALSE;
3471 flags = HAL_TXDESC_CLRDMASK; /* XXX needed for crypto errs */
3472 ismrr = 0; /* default no multi-rate retry*/
3474 * Calculate Atheros packet type from IEEE80211 packet header,
3475 * setup for rate calculations, and select h/w transmit queue.
3477 switch (wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) {
3478 case IEEE80211_FC0_TYPE_MGT:
3479 subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK;
3480 if (subtype == IEEE80211_FC0_SUBTYPE_BEACON)
3481 atype = HAL_PKT_TYPE_BEACON;
3482 else if (subtype == IEEE80211_FC0_SUBTYPE_PROBE_RESP)
3483 atype = HAL_PKT_TYPE_PROBE_RESP;
3484 else if (subtype == IEEE80211_FC0_SUBTYPE_ATIM)
3485 atype = HAL_PKT_TYPE_ATIM;
3487 atype = HAL_PKT_TYPE_NORMAL; /* XXX */
3488 rix = sc->sc_minrateix;
3489 txrate = rt->info[rix].rateCode;
3491 txrate |= rt->info[rix].shortPreamble;
3492 try0 = ATH_TXMGTTRY;
3493 /* NB: force all management frames to highest queue */
3494 if (ni->ni_flags & IEEE80211_NODE_QOS) {
3495 /* NB: force all management frames to highest queue */
3499 flags |= HAL_TXDESC_INTREQ; /* force interrupt */
3501 case IEEE80211_FC0_TYPE_CTL:
3502 atype = HAL_PKT_TYPE_PSPOLL; /* stop setting of duration */
3503 rix = sc->sc_minrateix;
3504 txrate = rt->info[rix].rateCode;
3506 txrate |= rt->info[rix].shortPreamble;
3507 try0 = ATH_TXMGTTRY;
3508 /* NB: force all ctl frames to highest queue */
3509 if (ni->ni_flags & IEEE80211_NODE_QOS) {
3510 /* NB: force all ctl frames to highest queue */
3514 flags |= HAL_TXDESC_INTREQ; /* force interrupt */
3516 case IEEE80211_FC0_TYPE_DATA:
3517 atype = HAL_PKT_TYPE_NORMAL; /* default */
3519 * Data frames: multicast frames go out at a fixed rate,
3520 * otherwise consult the rate control module for the
3525 * Check mcast rate setting in case it's changed.
3526 * XXX move out of fastpath
3528 if (ic->ic_mcast_rate != sc->sc_mcastrate) {
3530 ath_tx_findrix(rt, ic->ic_mcast_rate);
3531 sc->sc_mcastrate = ic->ic_mcast_rate;
3533 rix = sc->sc_mcastrix;
3534 txrate = rt->info[rix].rateCode;
3536 txrate |= rt->info[rix].shortPreamble;
3539 ath_rate_findrate(sc, an, shortPreamble, pktlen,
3540 &rix, &try0, &txrate);
3541 sc->sc_txrate = txrate; /* for LED blinking */
3542 if (try0 != ATH_TXMAXTRY)
3545 pri = M_WME_GETAC(m0);
3546 if (cap->cap_wmeParams[pri].wmep_noackPolicy)
3547 flags |= HAL_TXDESC_NOACK;
3550 if_printf(ifp, "bogus frame type 0x%x (%s)\n",
3551 wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK, __func__);
3556 txq = sc->sc_ac2q[pri];
3559 * When servicing one or more stations in power-save mode
3560 * multicast frames must be buffered until after the beacon.
3561 * We use the CAB queue for that.
3563 if (ismcast && ic->ic_ps_sta) {
3565 /* XXX? more bit in 802.11 frame header */
3569 * Calculate miscellaneous flags.
3572 flags |= HAL_TXDESC_NOACK; /* no ack on broad/multicast */
3573 } else if (pktlen > ic->ic_rtsthreshold) {
3574 flags |= HAL_TXDESC_RTSENA; /* RTS based on frame length */
3575 cix = rt->info[rix].controlRate;
3576 sc->sc_stats.ast_tx_rts++;
3578 if (flags & HAL_TXDESC_NOACK) /* NB: avoid double counting */
3579 sc->sc_stats.ast_tx_noack++;
3582 * If 802.11g protection is enabled, determine whether
3583 * to use RTS/CTS or just CTS. Note that this is only
3584 * done for OFDM unicast frames.
3586 if ((ic->ic_flags & IEEE80211_F_USEPROT) &&
3587 rt->info[rix].phy == IEEE80211_T_OFDM &&
3588 (flags & HAL_TXDESC_NOACK) == 0) {
3589 /* XXX fragments must use CCK rates w/ protection */
3590 if (ic->ic_protmode == IEEE80211_PROT_RTSCTS)
3591 flags |= HAL_TXDESC_RTSENA;
3592 else if (ic->ic_protmode == IEEE80211_PROT_CTSONLY)
3593 flags |= HAL_TXDESC_CTSENA;
3594 cix = rt->info[sc->sc_protrix].controlRate;
3595 sc->sc_stats.ast_tx_protect++;
3599 * Calculate duration. This logically belongs in the 802.11
3600 * layer but it lacks sufficient information to calculate it.
3602 if ((flags & HAL_TXDESC_NOACK) == 0 &&
3603 (wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) != IEEE80211_FC0_TYPE_CTL) {
3606 * XXX not right with fragmentation.
3609 dur = rt->info[rix].spAckDuration;
3611 dur = rt->info[rix].lpAckDuration;
3612 *(uint16_t *)wh->i_dur = htole16(dur);
3616 * Calculate RTS/CTS rate and duration if needed.
3619 if (flags & (HAL_TXDESC_RTSENA|HAL_TXDESC_CTSENA)) {
3621 * CTS transmit rate is derived from the transmit rate
3622 * by looking in the h/w rate table. We must also factor
3623 * in whether or not a short preamble is to be used.
3625 /* NB: cix is set above where RTS/CTS is enabled */
3626 KASSERT(cix != 0xff, ("cix not setup"));
3627 ctsrate = rt->info[cix].rateCode;
3629 * Compute the transmit duration based on the frame
3630 * size and the size of an ACK frame. We call into the
3631 * HAL to do the computation since it depends on the
3632 * characteristics of the actual PHY being used.
3634 * NB: CTS is assumed the same size as an ACK so we can
3635 * use the precalculated ACK durations.
3637 if (shortPreamble) {
3638 ctsrate |= rt->info[cix].shortPreamble;
3639 if (flags & HAL_TXDESC_RTSENA) /* SIFS + CTS */
3640 ctsduration += rt->info[cix].spAckDuration;
3641 ctsduration += ath_hal_computetxtime(ah,
3642 rt, pktlen, rix, AH_TRUE);
3643 if ((flags & HAL_TXDESC_NOACK) == 0) /* SIFS + ACK */
3644 ctsduration += rt->info[rix].spAckDuration;
3646 if (flags & HAL_TXDESC_RTSENA) /* SIFS + CTS */
3647 ctsduration += rt->info[cix].lpAckDuration;
3648 ctsduration += ath_hal_computetxtime(ah,
3649 rt, pktlen, rix, AH_FALSE);
3650 if ((flags & HAL_TXDESC_NOACK) == 0) /* SIFS + ACK */
3651 ctsduration += rt->info[rix].lpAckDuration;
3654 * Must disable multi-rate retry when using RTS/CTS.
3657 try0 = ATH_TXMGTTRY; /* XXX */
3661 if (IFF_DUMPPKTS(sc, ATH_DEBUG_XMIT))
3662 ieee80211_dump_pkt(mtod(m0, caddr_t), m0->m_len,
3663 sc->sc_hwmap[txrate].ieeerate, -1);
3666 bpf_mtap(ic->ic_rawbpf, m0);
3667 if (sc->sc_drvbpf) {
3668 uint64_t tsf = ath_hal_gettsf64(ah);
3670 sc->sc_tx_th.wt_tsf = htole64(tsf);
3671 sc->sc_tx_th.wt_flags = sc->sc_hwmap[txrate].txflags;
3673 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_WEP;
3674 sc->sc_tx_th.wt_rate = sc->sc_hwmap[txrate].ieeerate;
3675 sc->sc_tx_th.wt_txpower = ni->ni_txpower;
3676 sc->sc_tx_th.wt_antenna = sc->sc_txantenna;
3678 bpf_ptap(sc->sc_drvbpf, m0, &sc->sc_tx_th, sc->sc_tx_th_len);
3682 * Determine if a tx interrupt should be generated for
3683 * this descriptor. We take a tx interrupt to reap
3684 * descriptors when the h/w hits an EOL condition or
3685 * when the descriptor is specifically marked to generate
3686 * an interrupt. We periodically mark descriptors in this
3687 * way to insure timely replenishing of the supply needed
3688 * for sending frames. Defering interrupts reduces system
3689 * load and potentially allows more concurrent work to be
3690 * done but if done to aggressively can cause senders to
3693 * NB: use >= to deal with sc_txintrperiod changing
3694 * dynamically through sysctl.
3696 if (flags & HAL_TXDESC_INTREQ) {
3697 txq->axq_intrcnt = 0;
3698 } else if (++txq->axq_intrcnt >= sc->sc_txintrperiod) {
3699 flags |= HAL_TXDESC_INTREQ;
3700 txq->axq_intrcnt = 0;
3704 * Formulate first tx descriptor with tx controls.
3706 /* XXX check return value? */
3707 ath_hal_setuptxdesc(ah, ds
3708 , pktlen /* packet length */
3709 , hdrlen /* header length */
3710 , atype /* Atheros packet type */
3711 , ni->ni_txpower /* txpower */
3712 , txrate, try0 /* series 0 rate/tries */
3713 , keyix /* key cache index */
3714 , sc->sc_txantenna /* antenna mode */
3716 , ctsrate /* rts/cts rate */
3717 , ctsduration /* rts/cts duration */
3719 bf->bf_flags = flags;
3721 * Setup the multi-rate retry state only when we're
3722 * going to use it. This assumes ath_hal_setuptxdesc
3723 * initializes the descriptors (so we don't have to)
3724 * when the hardware supports multi-rate retry and
3728 ath_rate_setupxtxdesc(sc, an, ds, shortPreamble, rix);
3731 * Fillin the remainder of the descriptor info.
3734 for (i = 0; i < bf->bf_nseg; i++, ds++) {
3735 ds->ds_data = bf->bf_segs[i].ds_addr;
3736 if (i == bf->bf_nseg - 1)
3739 ds->ds_link = bf->bf_daddr + sizeof(*ds) * (i + 1);
3740 ath_hal_filltxdesc(ah, ds
3741 , bf->bf_segs[i].ds_len /* segment length */
3742 , i == 0 /* first segment */
3743 , i == bf->bf_nseg - 1 /* last segment */
3744 , ds0 /* first descriptor */
3746 DPRINTF(sc, ATH_DEBUG_XMIT,
3747 "%s: %d: %08x %08x %08x %08x %08x %08x\n",
3748 __func__, i, ds->ds_link, ds->ds_data,
3749 ds->ds_ctl0, ds->ds_ctl1, ds->ds_hw[0], ds->ds_hw[1]);
3752 * Insert the frame on the outbound list and
3753 * pass it on to the hardware.
3755 ATH_TXQ_INSERT_TAIL(txq, bf, bf_list);
3756 if (txq->axq_link == NULL) {
3757 ath_hal_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr);
3758 DPRINTF(sc, ATH_DEBUG_XMIT,
3759 "%s: TXDP[%u] = %p (%p) depth %d\n", __func__,
3760 txq->axq_qnum, (caddr_t)bf->bf_daddr, bf->bf_desc,
3763 *txq->axq_link = bf->bf_daddr;
3764 DPRINTF(sc, ATH_DEBUG_XMIT,
3765 "%s: link[%u](%p)=%p (%p) depth %d\n", __func__,
3766 txq->axq_qnum, txq->axq_link,
3767 (caddr_t)bf->bf_daddr, bf->bf_desc, txq->axq_depth);
3769 txq->axq_link = &bf->bf_desc[bf->bf_nseg - 1].ds_link;
3771 * The CAB queue is started from the SWBA handler since
3772 * frames only go out on DTIM and to avoid possible races.
3774 if (txq != sc->sc_cabq)
3775 ath_hal_txstart(ah, txq->axq_qnum);
3781 * Process completed xmit descriptors from the specified queue.
3784 ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq)
3786 struct ath_hal *ah = sc->sc_ah;
3787 struct ieee80211com *ic = &sc->sc_ic;
3789 struct ath_desc *ds, *ds0;
3790 struct ieee80211_node *ni;
3791 struct ath_node *an;
3792 int sr, lr, pri, nacked;
3795 DPRINTF(sc, ATH_DEBUG_TX_PROC, "%s: tx queue %u head %p link %p\n",
3796 __func__, txq->axq_qnum,
3797 (caddr_t)(uintptr_t) ath_hal_gettxbuf(sc->sc_ah, txq->axq_qnum),
3801 txq->axq_intrcnt = 0; /* reset periodic desc intr count */
3802 bf = STAILQ_FIRST(&txq->axq_q);
3805 ds0 = &bf->bf_desc[0];
3806 ds = &bf->bf_desc[bf->bf_nseg - 1];
3807 status = ath_hal_txprocdesc(ah, ds);
3809 if (sc->sc_debug & ATH_DEBUG_XMIT_DESC)
3810 ath_printtxbuf(bf, txq->axq_qnum, 0, status == HAL_OK);
3812 if (status == HAL_EINPROGRESS)
3814 ATH_TXQ_REMOVE_HEAD(txq, bf_list);
3815 if (txq->axq_depth == 0)
3816 txq->axq_link = NULL;
3821 if (ds->ds_txstat.ts_status == 0) {
3822 uint8_t txant = ds->ds_txstat.ts_antenna;
3823 sc->sc_stats.ast_ant_tx[txant]++;
3824 sc->sc_ant_tx[txant]++;
3825 if (ds->ds_txstat.ts_rate & HAL_TXSTAT_ALTRATE)
3826 sc->sc_stats.ast_tx_altrate++;
3827 sc->sc_stats.ast_tx_rssi =
3828 ds->ds_txstat.ts_rssi;
3829 ATH_RSSI_LPF(sc->sc_halstats.ns_avgtxrssi,
3830 ds->ds_txstat.ts_rssi);
3831 pri = M_WME_GETAC(bf->bf_m);
3832 if (pri >= WME_AC_VO)
3833 ic->ic_wme.wme_hipri_traffic++;
3834 ni->ni_inact = ni->ni_inact_reload;
3836 if (ds->ds_txstat.ts_status & HAL_TXERR_XRETRY)
3837 sc->sc_stats.ast_tx_xretries++;
3838 if (ds->ds_txstat.ts_status & HAL_TXERR_FIFO)
3839 sc->sc_stats.ast_tx_fifoerr++;
3840 if (ds->ds_txstat.ts_status & HAL_TXERR_FILT)
3841 sc->sc_stats.ast_tx_filtered++;
3843 sr = ds->ds_txstat.ts_shortretry;
3844 lr = ds->ds_txstat.ts_longretry;
3845 sc->sc_stats.ast_tx_shortretry += sr;
3846 sc->sc_stats.ast_tx_longretry += lr;
3848 * Hand the descriptor to the rate control algorithm.
3850 if ((ds->ds_txstat.ts_status & HAL_TXERR_FILT) == 0 &&
3851 (bf->bf_flags & HAL_TXDESC_NOACK) == 0) {
3853 * If frame was ack'd update the last rx time
3854 * used to workaround phantom bmiss interrupts.
3856 if (ds->ds_txstat.ts_status == 0)
3858 ath_rate_tx_complete(sc, an, ds, ds0);
3861 * Reclaim reference to node.
3863 * NB: the node may be reclaimed here if, for example
3864 * this is a DEAUTH message that was sent and the
3865 * node was timed out due to inactivity.
3867 ieee80211_free_node(ni);
3869 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap,
3870 BUS_DMASYNC_POSTWRITE);
3871 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap);
3876 STAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list);
3882 txqactive(struct ath_hal *ah, int qnum)
3884 uint32_t txqs = 1<<qnum;
3885 ath_hal_gettxintrtxqs(ah, &txqs);
3886 return (txqs & (1<<qnum));
3890 * Deferred processing of transmit interrupt; special-cased
3891 * for a single hardware transmit queue (e.g. 5210 and 5211).
3894 ath_tx_proc_q0(struct ath_softc *sc)
3896 struct ifnet *ifp = &sc->sc_ic.ic_if;
3898 if (txqactive(sc->sc_ah, 0) && ath_tx_processq(sc, &sc->sc_txq[0]))
3899 sc->sc_lastrx = ath_hal_gettsf64(sc->sc_ah);
3900 if (txqactive(sc->sc_ah, sc->sc_cabq->axq_qnum))
3901 ath_tx_processq(sc, sc->sc_cabq);
3902 ifp->if_flags &= ~IFF_OACTIVE;
3903 sc->sc_tx_timer = 0;
3906 ath_led_event(sc, ATH_LED_TX);
3912 * Deferred processing of transmit interrupt; special-cased
3913 * for four hardware queues, 0-3 (e.g. 5212 w/ WME support).
3916 ath_tx_proc_q0123(struct ath_softc *sc)
3918 struct ifnet *ifp = &sc->sc_ic.ic_if;
3922 * Process each active queue.
3925 if (txqactive(sc->sc_ah, 0))
3926 nacked += ath_tx_processq(sc, &sc->sc_txq[0]);
3927 if (txqactive(sc->sc_ah, 1))
3928 nacked += ath_tx_processq(sc, &sc->sc_txq[1]);
3929 if (txqactive(sc->sc_ah, 2))
3930 nacked += ath_tx_processq(sc, &sc->sc_txq[2]);
3931 if (txqactive(sc->sc_ah, 3))
3932 nacked += ath_tx_processq(sc, &sc->sc_txq[3]);
3933 if (txqactive(sc->sc_ah, sc->sc_cabq->axq_qnum))
3934 ath_tx_processq(sc, sc->sc_cabq);
3936 sc->sc_lastrx = ath_hal_gettsf64(sc->sc_ah);
3938 ifp->if_flags &= ~IFF_OACTIVE;
3939 sc->sc_tx_timer = 0;
3942 ath_led_event(sc, ATH_LED_TX);
3948 * Deferred processing of transmit interrupt.
3951 ath_tx_proc(struct ath_softc *sc)
3953 struct ifnet *ifp = &sc->sc_ic.ic_if;
3957 * Process each active queue.
3960 for (i = 0; i < HAL_NUM_TX_QUEUES; i++)
3961 if (IS_ATH_TXQ_SETUP(sc, i) && txqactive(sc->sc_ah, i))
3962 nacked += ath_tx_processq(sc, &sc->sc_txq[i]);
3964 sc->sc_lastrx = ath_hal_gettsf64(sc->sc_ah);
3966 ifp->if_flags &= ~IFF_OACTIVE;
3967 sc->sc_tx_timer = 0;
3970 ath_led_event(sc, ATH_LED_TX);
3976 ath_tx_draintxq(struct ath_softc *sc, struct ath_txq *txq)
3979 struct ath_hal *ah = sc->sc_ah;
3981 struct ieee80211_node *ni;
3986 * NB: this assumes output has been stopped and
3987 * we do not need to block ath_tx_tasklet
3989 for (ix = 0;; ix++) {
3990 bf = STAILQ_FIRST(&txq->axq_q);
3992 txq->axq_link = NULL;
3995 ATH_TXQ_REMOVE_HEAD(txq, bf_list);
3997 if (sc->sc_debug & ATH_DEBUG_RESET)
3998 ath_printtxbuf(bf, txq->axq_qnum, ix,
3999 ath_hal_txprocdesc(ah, bf->bf_desc) == HAL_OK);
4000 #endif /* ATH_DEBUG */
4001 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap);
4008 * Reclaim node reference.
4010 ieee80211_free_node(ni);
4012 STAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list);
4017 ath_tx_stopdma(struct ath_softc *sc, struct ath_txq *txq)
4019 struct ath_hal *ah = sc->sc_ah;
4021 ath_hal_stoptxdma(ah, txq->axq_qnum);
4022 DPRINTF(sc, ATH_DEBUG_RESET, "%s: tx queue [%u] %p, link %p\n",
4023 __func__, txq->axq_qnum,
4024 (caddr_t)(uintptr_t)ath_hal_gettxbuf(ah, txq->axq_qnum),
4029 * Drain the transmit queues and reclaim resources.
4032 ath_draintxq(struct ath_softc *sc)
4034 struct ath_hal *ah = sc->sc_ah;
4035 struct ifnet *ifp = &sc->sc_ic.ic_if;
4038 ASSERT_SERIALIZED(ifp->if_serializer);
4040 /* XXX return value */
4041 if (!sc->sc_invalid) {
4042 /* don't touch the hardware if marked invalid */
4043 ath_hal_stoptxdma(ah, sc->sc_bhalq);
4044 DPRINTF(sc, ATH_DEBUG_RESET,
4045 "%s: beacon queue %p\n", __func__,
4046 (caddr_t)(uintptr_t) ath_hal_gettxbuf(ah, sc->sc_bhalq));
4047 for (i = 0; i < HAL_NUM_TX_QUEUES; i++)
4048 if (IS_ATH_TXQ_SETUP(sc, i))
4049 ath_tx_stopdma(sc, &sc->sc_txq[i]);
4051 for (i = 0; i < HAL_NUM_TX_QUEUES; i++)
4052 if (IS_ATH_TXQ_SETUP(sc, i))
4053 ath_tx_draintxq(sc, &sc->sc_txq[i]);
4054 ifp->if_flags &= ~IFF_OACTIVE;
4055 sc->sc_tx_timer = 0;
4059 * Disable the receive h/w in preparation for a reset.
4062 ath_stoprecv(struct ath_softc *sc)
4064 #define PA2DESC(_sc, _pa) \
4065 ((struct ath_desc *)((caddr_t)(_sc)->sc_rxdma.dd_desc + \
4066 ((_pa) - (_sc)->sc_rxdma.dd_desc_paddr)))
4067 struct ath_hal *ah = sc->sc_ah;
4069 ASSERT_SERIALIZED(sc->sc_ic.ic_if.if_serializer);
4071 ath_hal_stoppcurecv(ah); /* disable PCU */
4072 ath_hal_setrxfilter(ah, 0); /* clear recv filter */
4073 ath_hal_stopdmarecv(ah); /* disable DMA engine */
4074 DELAY(3000); /* 3ms is long enough for 1 frame */
4076 if (sc->sc_debug & (ATH_DEBUG_RESET | ATH_DEBUG_FATAL)) {
4080 printf("%s: rx queue %p, link %p\n", __func__,
4081 (caddr_t)(uintptr_t) ath_hal_getrxbuf(ah),
4084 STAILQ_FOREACH(bf, &sc->sc_rxbuf, bf_list) {
4085 struct ath_desc *ds = bf->bf_desc;
4088 status = ath_hal_rxprocdesc(ah, ds, bf->bf_daddr,
4089 PA2DESC(sc, ds->ds_link));
4090 if (status == HAL_OK ||
4091 (sc->sc_debug & ATH_DEBUG_FATAL))
4092 ath_printrxbuf(bf, ix, status == HAL_OK);
4097 sc->sc_rxlink = NULL; /* just in case */
4102 * Enable the receive h/w following a reset.
4105 ath_startrecv(struct ath_softc *sc)
4107 struct ath_hal *ah = sc->sc_ah;
4110 ASSERT_SERIALIZED(sc->sc_ic.ic_if.if_serializer);
4112 sc->sc_rxlink = NULL;
4113 STAILQ_FOREACH(bf, &sc->sc_rxbuf, bf_list) {
4114 int error = ath_rxbuf_init(sc, bf);
4116 DPRINTF(sc, ATH_DEBUG_RECV,
4117 "%s: ath_rxbuf_init failed %d\n",
4123 bf = STAILQ_FIRST(&sc->sc_rxbuf);
4124 ath_hal_putrxbuf(ah, bf->bf_daddr);
4125 ath_hal_rxena(ah); /* enable recv descriptors */
4126 ath_mode_init(sc); /* set filters, etc. */
4127 ath_hal_startpcurecv(ah); /* re-enable PCU/DMA engine */
4132 * Update internal state after a channel change.
4135 ath_chan_change(struct ath_softc *sc, struct ieee80211_channel *chan)
4137 struct ieee80211com *ic = &sc->sc_ic;
4138 enum ieee80211_phymode mode;
4142 * Change channels and update the h/w rate map
4143 * if we're switching; e.g. 11a to 11b/g.
4145 mode = ieee80211_chan2mode(ic, chan);
4146 if (mode != sc->sc_curmode)
4147 ath_setcurmode(sc, mode);
4149 * Update BPF state. NB: ethereal et. al. don't handle
4150 * merged flags well so pick a unique mode for their use.
4152 if (IEEE80211_IS_CHAN_A(chan))
4153 flags = IEEE80211_CHAN_A;
4154 /* XXX 11g schizophrenia */
4155 else if (IEEE80211_IS_CHAN_G(chan) ||
4156 IEEE80211_IS_CHAN_PUREG(chan))
4157 flags = IEEE80211_CHAN_G;
4159 flags = IEEE80211_CHAN_B;
4160 if (IEEE80211_IS_CHAN_T(chan))
4161 flags |= IEEE80211_CHAN_TURBO;
4162 sc->sc_tx_th.wt_chan_freq = sc->sc_rx_th.wr_chan_freq =
4163 htole16(chan->ic_freq);
4164 sc->sc_tx_th.wt_chan_flags = sc->sc_rx_th.wr_chan_flags =
4169 * Poll for a channel clear indication; this is required
4170 * for channels requiring DFS and not previously visited
4171 * and/or with a recent radar detection.
4174 ath_dfswait(void *arg)
4176 struct ath_softc *sc = arg;
4177 struct ath_hal *ah = sc->sc_ah;
4178 struct ifnet *ifp = &sc->sc_ic.ic_if;
4181 lwkt_serialize_enter(ifp->if_serializer);
4183 ath_hal_radar_wait(ah, &hchan);
4184 DPRINTF(sc, ATH_DEBUG_DFS, "%s: radar_wait %u/%x/%x\n",
4185 __func__, hchan.channel, hchan.channelFlags, hchan.privFlags);
4187 if (hchan.privFlags & CHANNEL_INTERFERENCE) {
4188 if_printf(ifp, "channel %u/0x%x/0x%x has interference\n",
4189 hchan.channel, hchan.channelFlags, hchan.privFlags);
4192 if ((hchan.privFlags & CHANNEL_DFS) == 0) {
4193 /* XXX should not happen */
4196 if (hchan.privFlags & CHANNEL_DFS_CLEAR) {
4197 sc->sc_curchan.privFlags |= CHANNEL_DFS_CLEAR;
4198 ifp->if_flags &= ~IFF_OACTIVE;
4199 if_printf(ifp, "channel %u/0x%x/0x%x marked clear\n",
4200 hchan.channel, hchan.channelFlags, hchan.privFlags);
4202 callout_reset(&sc->sc_dfs_ch, 2 * hz, ath_dfswait, sc);
4206 lwkt_serialize_exit(ifp->if_serializer);
4210 * Set/change channels. If the channel is really being changed,
4211 * it's done by reseting the chip. To accomplish this we must
4212 * first cleanup any pending DMA, then restart stuff after a la
4216 ath_chan_set(struct ath_softc *sc, struct ieee80211_channel *chan)
4218 struct ath_hal *ah = sc->sc_ah;
4219 struct ieee80211com *ic = &sc->sc_ic;
4220 struct ifnet *ifp = &ic->ic_if;
4224 * Convert to a HAL channel description with
4225 * the flags constrained to reflect the current
4228 hchan.channel = chan->ic_freq;
4229 hchan.channelFlags = ath_chan2flags(ic, chan);
4231 DPRINTF(sc, ATH_DEBUG_RESET,
4232 "%s: %u (%u MHz, hal flags 0x%x) -> %u (%u MHz, hal flags 0x%x)\n",
4234 ath_hal_mhz2ieee(ah, sc->sc_curchan.channel,
4235 sc->sc_curchan.channelFlags),
4236 sc->sc_curchan.channel, sc->sc_curchan.channelFlags,
4237 ath_hal_mhz2ieee(ah, hchan.channel, hchan.channelFlags),
4238 hchan.channel, hchan.channelFlags);
4239 if (hchan.channel != sc->sc_curchan.channel ||
4240 hchan.channelFlags != sc->sc_curchan.channelFlags) {
4244 * To switch channels clear any pending DMA operations;
4245 * wait long enough for the RX fifo to drain, reset the
4246 * hardware at the new frequency, and then re-enable
4247 * the relevant bits of the h/w.
4249 ath_hal_intrset(ah, 0); /* disable interrupts */
4250 ath_draintxq(sc); /* clear pending tx frames */
4251 ath_stoprecv(sc); /* turn off frame recv */
4252 if (!ath_hal_reset(ah, sc->sc_opmode, &hchan, AH_TRUE, &status)) {
4253 if_printf(ifp, "%s: unable to reset "
4254 "channel %u (%u Mhz, flags 0x%x hal flags 0x%x)\n",
4255 __func__, ieee80211_chan2ieee(ic, chan),
4256 chan->ic_freq, chan->ic_flags, hchan.channelFlags);
4259 sc->sc_curchan = hchan;
4260 ath_update_txpow(sc); /* update tx power state */
4261 sc->sc_diversity = ath_hal_getdiversity(ah);
4262 sc->sc_calinterval = 1;
4263 sc->sc_caltries = 0;
4266 * Re-enable rx framework.
4268 if (ath_startrecv(sc) != 0) {
4269 if_printf(ic->ic_ifp,
4270 "%s: unable to restart recv logic\n", __func__);
4275 * Change channels and update the h/w rate map
4276 * if we're switching; e.g. 11a to 11b/g.
4278 ic->ic_ibss_chan = chan;
4279 ath_chan_change(sc, chan);
4282 * Handle DFS required waiting period to determine
4283 * if channel is clear of radar traffic.
4285 if (ic->ic_opmode == IEEE80211_M_HOSTAP) {
4286 #define DFS_AND_NOT_CLEAR(_c) \
4287 (((_c)->privFlags & (CHANNEL_DFS | CHANNEL_DFS_CLEAR)) == CHANNEL_DFS)
4288 if (DFS_AND_NOT_CLEAR(&sc->sc_curchan)) {
4290 "wait for DFS clear channel signal\n");
4292 ifp->if_flags |= IFF_OACTIVE;
4293 callout_reset(&sc->sc_dfs_ch,
4294 2 * hz, ath_dfswait, sc);
4296 callout_stop(&sc->sc_dfs_ch);
4298 #undef DFS_NOT_CLEAR
4302 * Re-enable interrupts.
4304 ath_hal_intrset(ah, sc->sc_imask);
4310 ath_next_scan(void *arg)
4312 struct ath_softc *sc = arg;
4313 struct ieee80211com *ic = &sc->sc_ic;
4314 struct ifnet *ifp = &ic->ic_if;
4316 lwkt_serialize_enter(ifp->if_serializer);
4318 if (ic->ic_state == IEEE80211_S_SCAN)
4319 ieee80211_next_scan(ic);
4321 lwkt_serialize_exit(ifp->if_serializer);
4325 * Periodically recalibrate the PHY to account
4326 * for temperature/environment changes.
4329 ath_calibrate(void *arg)
4331 struct ath_softc *sc = arg;
4332 struct ath_hal *ah = sc->sc_ah;
4333 struct ifnet *ifp = &sc->sc_ic.ic_if;
4336 lwkt_serialize_enter(ifp->if_serializer);
4338 sc->sc_stats.ast_per_cal++;
4340 if (ath_hal_getrfgain(ah) == HAL_RFGAIN_NEED_CHANGE) {
4342 * Rfgain is out of bounds, reset the chip
4343 * to load new gain values.
4345 DPRINTF(sc, ATH_DEBUG_CALIBRATE,
4346 "%s: rfgain change\n", __func__);
4347 sc->sc_stats.ast_per_rfgain++;
4348 ath_reset(&sc->sc_ic.ic_if);
4350 if (!ath_hal_calibrate(ah, &sc->sc_curchan, &iqCalDone)) {
4351 DPRINTF(sc, ATH_DEBUG_ANY,
4352 "%s: calibration of channel %u failed\n",
4353 __func__, sc->sc_curchan.channel);
4354 sc->sc_stats.ast_per_calfail++;
4357 * Calibrate noise floor data again in case of change.
4359 ath_hal_process_noisefloor(ah);
4361 * Poll more frequently when the IQ calibration is in
4362 * progress to speedup loading the final settings.
4363 * We temper this aggressive polling with an exponential
4364 * back off after 4 tries up to ath_calinterval.
4366 if (iqCalDone || sc->sc_calinterval >= ath_calinterval) {
4367 sc->sc_caltries = 0;
4368 sc->sc_calinterval = ath_calinterval;
4369 } else if (sc->sc_caltries > 4) {
4370 sc->sc_caltries = 0;
4371 sc->sc_calinterval <<= 1;
4372 if (sc->sc_calinterval > ath_calinterval)
4373 sc->sc_calinterval = ath_calinterval;
4375 KASSERT(0 < sc->sc_calinterval && sc->sc_calinterval <= ath_calinterval,
4376 ("bad calibration interval %u", sc->sc_calinterval));
4378 DPRINTF(sc, ATH_DEBUG_CALIBRATE,
4379 "%s: next +%u (%siqCalDone tries %u)\n", __func__,
4380 sc->sc_calinterval, iqCalDone ? "" : "!", sc->sc_caltries);
4382 callout_reset(&sc->sc_cal_ch, sc->sc_calinterval * hz,
4385 lwkt_serialize_exit(ifp->if_serializer);
4389 ath_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg)
4391 struct ifnet *ifp = ic->ic_ifp;
4392 struct ath_softc *sc = ifp->if_softc;
4393 struct ath_hal *ah = sc->sc_ah;
4394 struct ieee80211_node *ni;
4396 const uint8_t *bssid;
4398 static const HAL_LED_STATE leds[] = {
4399 HAL_LED_INIT, /* IEEE80211_S_INIT */
4400 HAL_LED_SCAN, /* IEEE80211_S_SCAN */
4401 HAL_LED_AUTH, /* IEEE80211_S_AUTH */
4402 HAL_LED_ASSOC, /* IEEE80211_S_ASSOC */
4403 HAL_LED_RUN, /* IEEE80211_S_RUN */
4406 DPRINTF(sc, ATH_DEBUG_STATE, "%s: %s -> %s\n", __func__,
4407 ieee80211_state_name[ic->ic_state],
4408 ieee80211_state_name[nstate]);
4410 callout_stop(&sc->sc_scan_ch);
4411 callout_stop(&sc->sc_cal_ch);
4412 callout_stop(&sc->sc_dfs_ch);
4413 ath_hal_setledstate(ah, leds[nstate]); /* set LED */
4415 if (nstate == IEEE80211_S_INIT) {
4416 sc->sc_imask &= ~(HAL_INT_SWBA | HAL_INT_BMISS);
4418 * NB: disable interrupts so we don't rx frames.
4420 ath_hal_intrset(ah, sc->sc_imask &~ HAL_INT_GLOBAL);
4422 * Notify the rate control algorithm.
4424 ath_rate_newstate(sc, nstate);
4428 error = ath_chan_set(sc, ic->ic_curchan);
4431 rfilt = ath_calcrxfilter(sc, nstate);
4432 if (nstate == IEEE80211_S_SCAN)
4433 bssid = ifp->if_broadcastaddr;
4435 bssid = ni->ni_bssid;
4436 ath_hal_setrxfilter(ah, rfilt);
4437 DPRINTF(sc, ATH_DEBUG_STATE, "%s: RX filter 0x%x bssid %6D\n",
4438 __func__, rfilt, bssid, ":");
4440 if (nstate == IEEE80211_S_RUN && ic->ic_opmode == IEEE80211_M_STA)
4441 ath_hal_setassocid(ah, bssid, ni->ni_associd);
4443 ath_hal_setassocid(ah, bssid, 0);
4444 if (ic->ic_flags & IEEE80211_F_PRIVACY) {
4445 for (i = 0; i < IEEE80211_WEP_NKID; i++)
4446 if (ath_hal_keyisvalid(ah, i))
4447 ath_hal_keysetmac(ah, i, bssid);
4451 * Notify the rate control algorithm so rates
4452 * are setup should ath_beacon_alloc be called.
4454 ath_rate_newstate(sc, nstate);
4456 if (ic->ic_opmode == IEEE80211_M_MONITOR) {
4457 /* nothing to do */;
4458 } else if (nstate == IEEE80211_S_RUN) {
4459 DPRINTF(sc, ATH_DEBUG_STATE,
4460 "%s(RUN): ic_flags=0x%08x iv=%d bssid=%6D "
4461 "capinfo=0x%04x chan=%d\n"
4467 , ieee80211_chan2ieee(ic, ic->ic_curchan));
4469 switch (ic->ic_opmode) {
4470 case IEEE80211_M_HOSTAP:
4471 case IEEE80211_M_IBSS:
4473 * Allocate and setup the beacon frame.
4475 * Stop any previous beacon DMA. This may be
4476 * necessary, for example, when an ibss merge
4477 * causes reconfiguration; there will be a state
4478 * transition from RUN->RUN that means we may
4479 * be called with beacon transmission active.
4481 ath_hal_stoptxdma(ah, sc->sc_bhalq);
4482 ath_beacon_free(sc);
4483 error = ath_beacon_alloc(sc, ni);
4487 * If joining an adhoc network defer beacon timer
4488 * configuration to the next beacon frame so we
4489 * have a current TSF to use. Otherwise we're
4490 * starting an ibss/bss so there's no need to delay.
4492 if (ic->ic_opmode == IEEE80211_M_IBSS &&
4493 ic->ic_bss->ni_tstamp.tsf != 0)
4494 sc->sc_syncbeacon = 1;
4496 ath_beacon_config(sc);
4498 case IEEE80211_M_STA:
4500 * Allocate a key cache slot to the station.
4502 if ((ic->ic_flags & IEEE80211_F_PRIVACY) == 0 &&
4504 ni->ni_ucastkey.wk_keyix == IEEE80211_KEYIX_NONE)
4505 ath_setup_stationkey(ni);
4507 * Defer beacon timer configuration to the next
4508 * beacon frame so we have a current TSF to use
4509 * (any TSF collected when scanning is likely old).
4511 sc->sc_syncbeacon = 1;
4518 * Let the hal process statistics collected during a
4519 * scan so it can provide calibrated noise floor data.
4521 ath_hal_process_noisefloor(ah);
4523 * Reset rssi stats; maybe not the best place...
4525 sc->sc_halstats.ns_avgbrssi = ATH_RSSI_DUMMY_MARKER;
4526 sc->sc_halstats.ns_avgrssi = ATH_RSSI_DUMMY_MARKER;
4527 sc->sc_halstats.ns_avgtxrssi = ATH_RSSI_DUMMY_MARKER;
4530 sc->sc_imask &~ (HAL_INT_SWBA | HAL_INT_BMISS));
4531 sc->sc_imask &= ~(HAL_INT_SWBA | HAL_INT_BMISS);
4535 * Invoke the parent method to complete the work.
4537 error = sc->sc_newstate(ic, nstate, arg);
4539 * Finally, start any timers.
4541 if (nstate == IEEE80211_S_RUN) {
4542 /* start periodic recalibration timer */
4543 callout_reset(&sc->sc_cal_ch, sc->sc_calinterval * hz,
4545 } else if (nstate == IEEE80211_S_SCAN) {
4546 /* start ap/neighbor scan timer */
4547 callout_reset(&sc->sc_scan_ch, (ath_dwelltime * hz) / 1000,
4555 * Allocate a key cache slot to the station so we can
4556 * setup a mapping from key index to node. The key cache
4557 * slot is needed for managing antenna state and for
4558 * compression when stations do not use crypto. We do
4559 * it uniliaterally here; if crypto is employed this slot
4560 * will be reassigned.
4563 ath_setup_stationkey(struct ieee80211_node *ni)
4565 struct ieee80211com *ic = ni->ni_ic;
4566 struct ath_softc *sc = ic->ic_ifp->if_softc;
4567 ieee80211_keyix keyix, rxkeyix;
4569 if (!ath_key_alloc(ic, &ni->ni_ucastkey, &keyix, &rxkeyix)) {
4571 * Key cache is full; we'll fall back to doing
4572 * the more expensive lookup in software. Note
4573 * this also means no h/w compression.
4575 /* XXX msg+statistic */
4578 ni->ni_ucastkey.wk_keyix = keyix;
4579 ni->ni_ucastkey.wk_rxkeyix = rxkeyix;
4580 /* NB: this will create a pass-thru key entry */
4581 ath_keyset(sc, &ni->ni_ucastkey, ni->ni_macaddr, ic->ic_bss);
4586 * Setup driver-specific state for a newly associated node.
4587 * Note that we're called also on a re-associate, the isnew
4588 * param tells us if this is the first time or not.
4591 ath_newassoc(struct ieee80211_node *ni, int isnew)
4593 struct ieee80211com *ic = ni->ni_ic;
4594 struct ath_softc *sc = ic->ic_ifp->if_softc;
4596 ath_rate_newassoc(sc, ATH_NODE(ni), isnew);
4598 (ic->ic_flags & IEEE80211_F_PRIVACY) == 0 && sc->sc_hasclrkey) {
4599 KASSERT(ni->ni_ucastkey.wk_keyix == IEEE80211_KEYIX_NONE,
4600 ("new assoc with a unicast key already setup (keyix %u)",
4601 ni->ni_ucastkey.wk_keyix));
4602 ath_setup_stationkey(ni);
4607 ath_getchannels(struct ath_softc *sc, u_int cc,
4608 HAL_BOOL outdoor, HAL_BOOL xchanmode)
4610 #define COMPAT (CHANNEL_ALL_NOTURBO|CHANNEL_PASSIVE)
4611 struct ieee80211com *ic = &sc->sc_ic;
4612 struct ifnet *ifp = &ic->ic_if;
4613 struct ath_hal *ah = sc->sc_ah;
4617 chans = kmalloc(IEEE80211_CHAN_MAX * sizeof(HAL_CHANNEL), M_TEMP,
4620 if (!ath_hal_init_channels(ah, chans, IEEE80211_CHAN_MAX, &nchan,
4622 cc, HAL_MODE_ALL, outdoor, xchanmode)) {
4625 ath_hal_getregdomain(ah, &rd);
4626 if_printf(ifp, "unable to collect channel list from hal; "
4627 "regdomain likely %u country code %u\n", rd, cc);
4628 kfree(chans, M_TEMP);
4633 * Convert HAL channels to ieee80211 ones and insert
4634 * them in the table according to their channel number.
4636 for (i = 0; i < nchan; i++) {
4637 HAL_CHANNEL *c = &chans[i];
4640 ix = ath_hal_mhz2ieee(ah, c->channel, c->channelFlags);
4641 if (ix > IEEE80211_CHAN_MAX) {
4642 if_printf(ifp, "bad hal channel %d (%u/%x) ignored\n",
4643 ix, c->channel, c->channelFlags);
4647 /* XXX can't handle stuff <2400 right now */
4649 if_printf(ifp, "hal channel %d (%u/%x) "
4650 "cannot be handled; ignored\n",
4651 ix, c->channel, c->channelFlags);
4655 * Calculate net80211 flags; most are compatible
4656 * but some need massaging. Note the static turbo
4657 * conversion can be removed once net80211 is updated
4658 * to understand static vs. dynamic turbo.
4660 flags = c->channelFlags & COMPAT;
4661 if (c->channelFlags & CHANNEL_STURBO)
4662 flags |= IEEE80211_CHAN_TURBO;
4663 if (ic->ic_channels[ix].ic_freq == 0) {
4664 ic->ic_channels[ix].ic_freq = c->channel;
4665 ic->ic_channels[ix].ic_flags = flags;
4667 /* channels overlap; e.g. 11g and 11b */
4668 ic->ic_channels[ix].ic_flags |= flags;
4671 kfree(chans, M_TEMP);
4677 ath_led_done(void *arg)
4679 struct ath_softc *sc = arg;
4681 sc->sc_blinking = 0;
4685 * Turn the LED off: flip the pin and then set a timer so no
4686 * update will happen for the specified duration.
4689 ath_led_off(void *arg)
4691 struct ath_softc *sc = arg;
4693 ath_hal_gpioset(sc->sc_ah, sc->sc_ledpin, !sc->sc_ledon);
4694 callout_reset(&sc->sc_ledtimer, sc->sc_ledoff, ath_led_done, sc);
4698 * Blink the LED according to the specified on/off times.
4701 ath_led_blink(struct ath_softc *sc, int on, int off)
4703 DPRINTF(sc, ATH_DEBUG_LED, "%s: on %u off %u\n", __func__, on, off);
4704 ath_hal_gpioset(sc->sc_ah, sc->sc_ledpin, sc->sc_ledon);
4705 sc->sc_blinking = 1;
4706 sc->sc_ledoff = off;
4707 callout_reset(&sc->sc_ledtimer, on, ath_led_off, sc);
4711 ath_led_event(struct ath_softc *sc, int event)
4714 sc->sc_ledevent = ticks; /* time of last event */
4715 if (sc->sc_blinking) /* don't interrupt active blink */
4719 ath_led_blink(sc, sc->sc_hwmap[0].ledon,
4720 sc->sc_hwmap[0].ledoff);
4723 ath_led_blink(sc, sc->sc_hwmap[sc->sc_txrate].ledon,
4724 sc->sc_hwmap[sc->sc_txrate].ledoff);
4727 ath_led_blink(sc, sc->sc_hwmap[sc->sc_rxrate].ledon,
4728 sc->sc_hwmap[sc->sc_rxrate].ledoff);
4734 ath_update_txpow(struct ath_softc *sc)
4736 struct ieee80211com *ic = &sc->sc_ic;
4737 struct ath_hal *ah = sc->sc_ah;
4740 if (sc->sc_curtxpow != ic->ic_txpowlimit) {
4741 ath_hal_settxpowlimit(ah, ic->ic_txpowlimit);
4742 /* read back in case value is clamped */
4743 ath_hal_gettxpowlimit(ah, &txpow);
4744 ic->ic_txpowlimit = sc->sc_curtxpow = txpow;
4747 * Fetch max tx power level for status requests.
4749 ath_hal_getmaxtxpow(sc->sc_ah, &txpow);
4750 ic->ic_bss->ni_txpower = txpow;
4754 rate_setup(struct ath_softc *sc,
4755 const HAL_RATE_TABLE *rt, struct ieee80211_rateset *rs)
4759 if (rt->rateCount > IEEE80211_RATE_MAXSIZE) {
4760 DPRINTF(sc, ATH_DEBUG_ANY,
4761 "%s: rate table too small (%u > %u)\n",
4762 __func__, rt->rateCount, IEEE80211_RATE_MAXSIZE);
4763 maxrates = IEEE80211_RATE_MAXSIZE;
4765 maxrates = rt->rateCount;
4766 for (i = 0; i < maxrates; i++)
4767 rs->rs_rates[i] = rt->info[i].dot11Rate;
4768 rs->rs_nrates = maxrates;
4772 ath_rate_setup(struct ath_softc *sc, u_int mode)
4774 struct ath_hal *ah = sc->sc_ah;
4775 struct ieee80211com *ic = &sc->sc_ic;
4776 const HAL_RATE_TABLE *rt;
4779 case IEEE80211_MODE_11A:
4780 rt = ath_hal_getratetable(ah, HAL_MODE_11A);
4782 case IEEE80211_MODE_11B:
4783 rt = ath_hal_getratetable(ah, HAL_MODE_11B);
4785 case IEEE80211_MODE_11G:
4786 rt = ath_hal_getratetable(ah, HAL_MODE_11G);
4788 case IEEE80211_MODE_TURBO_A:
4789 /* XXX until static/dynamic turbo is fixed */
4790 rt = ath_hal_getratetable(ah, HAL_MODE_TURBO);
4792 case IEEE80211_MODE_TURBO_G:
4793 rt = ath_hal_getratetable(ah, HAL_MODE_108G);
4796 DPRINTF(sc, ATH_DEBUG_ANY, "%s: invalid mode %u\n",
4800 sc->sc_rates[mode] = rt;
4802 rate_setup(sc, rt, &ic->ic_sup_rates[mode]);
4809 ath_setcurmode(struct ath_softc *sc, enum ieee80211_phymode mode)
4811 #define N(a) (sizeof(a)/sizeof(a[0]))
4812 /* NB: on/off times from the Atheros NDIS driver, w/ permission */
4813 static const struct {
4814 u_int rate; /* tx/rx 802.11 rate */
4815 uint16_t timeOn; /* LED on time (ms) */
4816 uint16_t timeOff; /* LED off time (ms) */
4833 const HAL_RATE_TABLE *rt;
4836 memset(sc->sc_rixmap, 0xff, sizeof(sc->sc_rixmap));
4837 rt = sc->sc_rates[mode];
4838 KASSERT(rt != NULL, ("no h/w rate set for phy mode %u", mode));
4839 for (i = 0; i < rt->rateCount; i++)
4840 sc->sc_rixmap[rt->info[i].dot11Rate & IEEE80211_RATE_VAL] = i;
4841 memset(sc->sc_hwmap, 0, sizeof(sc->sc_hwmap));
4842 for (i = 0; i < 32; i++) {
4843 uint8_t ix = rt->rateCodeToIndex[i];
4845 sc->sc_hwmap[i].ledon = (500 * hz) / 1000;
4846 sc->sc_hwmap[i].ledoff = (130 * hz) / 1000;
4849 sc->sc_hwmap[i].ieeerate =
4850 rt->info[ix].dot11Rate & IEEE80211_RATE_VAL;
4851 sc->sc_hwmap[i].txflags = IEEE80211_RADIOTAP_F_DATAPAD;
4852 if (rt->info[ix].shortPreamble ||
4853 rt->info[ix].phy == IEEE80211_T_OFDM)
4854 sc->sc_hwmap[i].txflags |= IEEE80211_RADIOTAP_F_SHORTPRE;
4855 /* NB: receive frames include FCS */
4856 sc->sc_hwmap[i].rxflags = sc->sc_hwmap[i].txflags |
4857 IEEE80211_RADIOTAP_F_FCS;
4858 /* setup blink rate table to avoid per-packet lookup */
4859 for (j = 0; j < N(blinkrates)-1; j++)
4860 if (blinkrates[j].rate == sc->sc_hwmap[i].ieeerate)
4862 /* NB: this uses the last entry if the rate isn't found */
4863 /* XXX beware of overlow */
4864 sc->sc_hwmap[i].ledon = (blinkrates[j].timeOn * hz) / 1000;
4865 sc->sc_hwmap[i].ledoff = (blinkrates[j].timeOff * hz) / 1000;
4867 sc->sc_currates = rt;
4868 sc->sc_curmode = mode;
4870 * All protection frames are transmited at 2Mb/s for
4871 * 11g, otherwise at 1Mb/s.
4873 if (mode == IEEE80211_MODE_11G)
4874 sc->sc_protrix = ath_tx_findrix(rt, 2 * 2);
4876 sc->sc_protrix = ath_tx_findrix(rt, 2 * 1);
4877 /* rate index used to send management frames */
4878 sc->sc_minrateix = 0;
4880 * Setup multicast rate state.
4882 /* XXX layering violation */
4883 sc->sc_mcastrix = ath_tx_findrix(rt, sc->sc_ic.ic_mcast_rate);
4884 sc->sc_mcastrate = sc->sc_ic.ic_mcast_rate;
4885 /* NB: caller is responsible for reseting rate control state */
4891 ath_printrxbuf(struct ath_buf *bf, u_int ix, int done)
4893 struct ath_desc *ds;
4896 for (i = 0, ds = bf->bf_desc; i < bf->bf_nseg; i++, ds++) {
4897 printf("R[%2u] (DS.V:%p DS.P:%p) L:%08x D:%08x%s\n"
4898 " %08x %08x %08x %08x\n",
4899 ix, ds, (struct ath_desc *)bf->bf_daddr + i,
4900 ds->ds_link, ds->ds_data,
4901 !done ? "" : (ds->ds_rxstat.rs_status == 0) ? " *" : " !",
4902 ds->ds_ctl0, ds->ds_ctl1,
4903 ds->ds_hw[0], ds->ds_hw[1]);
4908 ath_printtxbuf(struct ath_buf *bf, u_int qnum, u_int ix, int done)
4910 struct ath_desc *ds;
4913 printf("Q%u[%3u]", qnum, ix);
4914 for (i = 0, ds = bf->bf_desc; i < bf->bf_nseg; i++, ds++) {
4915 printf(" (DS.V:%p DS.P:%p) L:%08x D:%08x F:04%x%s\n"
4916 " %08x %08x %08x %08x %08x %08x\n",
4917 ds, (struct ath_desc *)bf->bf_daddr + i,
4918 ds->ds_link, ds->ds_data, bf->bf_flags,
4919 !done ? "" : (ds->ds_txstat.ts_status == 0) ? " *" : " !",
4920 ds->ds_ctl0, ds->ds_ctl1,
4921 ds->ds_hw[0], ds->ds_hw[1], ds->ds_hw[2], ds->ds_hw[3]);
4924 #endif /* ATH_DEBUG */
4927 ath_watchdog(struct ifnet *ifp)
4929 struct ath_softc *sc = ifp->if_softc;
4930 struct ieee80211com *ic = &sc->sc_ic;
4933 if ((ifp->if_flags & IFF_RUNNING) == 0 || sc->sc_invalid)
4935 if (sc->sc_tx_timer) {
4936 if (--sc->sc_tx_timer == 0) {
4937 if_printf(ifp, "device timeout\n");
4940 sc->sc_stats.ast_watchdog++;
4944 ieee80211_watchdog(ic);
4949 * Diagnostic interface to the HAL. This is used by various
4950 * tools to do things like retrieve register contents for
4951 * debugging. The mechanism is intentionally opaque so that
4952 * it can change frequently w/o concern for compatiblity.
4955 ath_ioctl_diag(struct ath_softc *sc, struct ath_diag *ad)
4957 struct ath_hal *ah = sc->sc_ah;
4958 u_int id = ad->ad_id & ATH_DIAG_ID;
4959 void *indata = NULL;
4960 void *outdata = NULL;
4961 uint32_t insize = ad->ad_in_size;
4962 uint32_t outsize = ad->ad_out_size;
4965 if (ad->ad_id & ATH_DIAG_IN) {
4969 indata = kmalloc(insize, M_TEMP, M_NOWAIT);
4970 if (indata == NULL) {
4974 error = copyin(ad->ad_in_data, indata, insize);
4978 if (ad->ad_id & ATH_DIAG_DYN) {
4980 * Allocate a buffer for the results (otherwise the HAL
4981 * returns a pointer to a buffer where we can read the
4982 * results). Note that we depend on the HAL leaving this
4983 * pointer for us to use below in reclaiming the buffer;
4984 * may want to be more defensive.
4986 outdata = kmalloc(outsize, M_TEMP, M_NOWAIT);
4987 if (outdata == NULL) {
4992 if (ath_hal_getdiagstate(ah, id, indata, insize, &outdata, &outsize)) {
4993 if (outsize < ad->ad_out_size)
4994 ad->ad_out_size = outsize;
4995 if (outdata != NULL)
4996 error = copyout(outdata, ad->ad_out_data,
5002 if ((ad->ad_id & ATH_DIAG_IN) && indata != NULL)
5003 kfree(indata, M_TEMP);
5004 if ((ad->ad_id & ATH_DIAG_DYN) && outdata != NULL)
5005 kfree(outdata, M_TEMP);
5008 #endif /* ATH_DIAGAPI */
5011 ath_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data, struct ucred *cr)
5013 #define IS_RUNNING(ifp) \
5014 ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == (IFF_UP | IFF_RUNNING))
5015 struct ath_softc *sc = ifp->if_softc;
5016 struct ieee80211com *ic = &sc->sc_ic;
5017 struct ifreq *ifr = (struct ifreq *)data;
5020 ASSERT_SERIALIZED(ifp->if_serializer);
5024 if (IS_RUNNING(ifp)) {
5026 * To avoid rescanning another access point,
5027 * do not call ath_init() here. Instead,
5028 * only reflect promisc mode settings.
5031 } else if (ifp->if_flags & IFF_UP) {
5033 * Beware of being called during attach/detach
5034 * to reset promiscuous mode. In that case we
5035 * will still be marked UP but not RUNNING.
5036 * However trying to re-init the interface
5037 * is the wrong thing to do as we've already
5038 * torn down much of our state. There's
5039 * probably a better way to deal with this.
5041 if (!sc->sc_invalid && ic->ic_bss != NULL)
5042 ath_init(sc); /* XXX lose error */
5044 ath_stop_no_pwchg(ifp);
5049 * The upper layer has already installed/removed
5050 * the multicast address(es), just recalculate the
5051 * multicast filter for the card.
5053 if (ifp->if_flags & IFF_RUNNING)
5057 /* NB: embed these numbers to get a consistent view */
5058 sc->sc_stats.ast_tx_packets = ifp->if_opackets;
5059 sc->sc_stats.ast_rx_packets = ifp->if_ipackets;
5060 sc->sc_stats.ast_rx_rssi = ieee80211_getrssi(ic);
5062 * NB: Drop the softc lock in case of a page fault;
5063 * we'll accept any potential inconsisentcy in the
5064 * statistics. The alternative is to copy the data
5065 * to a local structure.
5067 return copyout(&sc->sc_stats,
5068 ifr->ifr_data, sizeof (sc->sc_stats));
5071 error = ath_ioctl_diag(sc, (struct ath_diag *)ifr);
5075 error = ieee80211_ioctl(ic, cmd, data, cr);
5076 if (error == ENETRESET) {
5077 if (IS_RUNNING(ifp) &&
5078 ic->ic_roaming != IEEE80211_ROAMING_MANUAL)
5079 ath_init(sc); /* XXX lose error */
5082 if (error == ERESTART)
5083 error = IS_RUNNING(ifp) ? ath_reset(ifp) : 0;
5091 ath_sysctl_slottime(SYSCTL_HANDLER_ARGS)
5093 struct ath_softc *sc = arg1;
5094 struct ifnet *ifp = &sc->sc_ic.ic_if;
5098 lwkt_serialize_enter(ifp->if_serializer);
5100 slottime = ath_hal_getslottime(sc->sc_ah);
5101 error = sysctl_handle_int(oidp, &slottime, 0, req);
5102 if (error || !req->newptr)
5104 error = !ath_hal_setslottime(sc->sc_ah, slottime) ? EINVAL : 0;
5106 lwkt_serialize_exit(ifp->if_serializer);
5111 ath_sysctl_acktimeout(SYSCTL_HANDLER_ARGS)
5113 struct ath_softc *sc = arg1;
5114 struct ifnet *ifp = &sc->sc_ic.ic_if;
5118 lwkt_serialize_enter(ifp->if_serializer);
5120 acktimeout = ath_hal_getacktimeout(sc->sc_ah);
5121 error = sysctl_handle_int(oidp, &acktimeout, 0, req);
5122 if (error || !req->newptr)
5124 error = !ath_hal_setacktimeout(sc->sc_ah, acktimeout) ? EINVAL : 0;
5126 lwkt_serialize_exit(ifp->if_serializer);
5131 ath_sysctl_ctstimeout(SYSCTL_HANDLER_ARGS)
5133 struct ath_softc *sc = arg1;
5134 struct ifnet *ifp = &sc->sc_ic.ic_if;
5138 lwkt_serialize_enter(ifp->if_serializer);
5140 ctstimeout = ath_hal_getctstimeout(sc->sc_ah);
5141 error = sysctl_handle_int(oidp, &ctstimeout, 0, req);
5142 if (error || !req->newptr)
5144 error = !ath_hal_setctstimeout(sc->sc_ah, ctstimeout) ? EINVAL : 0;
5146 lwkt_serialize_exit(ifp->if_serializer);
5151 ath_sysctl_softled(SYSCTL_HANDLER_ARGS)
5153 struct ath_softc *sc = arg1;
5154 struct ifnet *ifp = &sc->sc_ic.ic_if;
5158 lwkt_serialize_enter(ifp->if_serializer);
5160 softled = sc->sc_softled;
5161 error = sysctl_handle_int(oidp, &softled, 0, req);
5162 if (error || !req->newptr)
5164 softled = (softled != 0);
5165 if (softled != sc->sc_softled) {
5167 /* NB: handle any sc_ledpin change */
5168 ath_hal_gpioCfgOutput(sc->sc_ah, sc->sc_ledpin);
5169 ath_hal_gpioset(sc->sc_ah, sc->sc_ledpin,
5172 sc->sc_softled = softled;
5175 lwkt_serialize_exit(ifp->if_serializer);
5180 ath_sysctl_rxantenna(SYSCTL_HANDLER_ARGS)
5182 struct ath_softc *sc = arg1;
5183 struct ifnet *ifp = &sc->sc_ic.ic_if;
5187 lwkt_serialize_enter(ifp->if_serializer);
5189 defantenna = ath_hal_getdefantenna(sc->sc_ah);
5190 error = sysctl_handle_int(oidp, &defantenna, 0, req);
5191 if (!error && req->newptr)
5192 ath_hal_setdefantenna(sc->sc_ah, defantenna);
5194 lwkt_serialize_exit(ifp->if_serializer);
5199 ath_sysctl_diversity(SYSCTL_HANDLER_ARGS)
5201 struct ath_softc *sc = arg1;
5202 struct ifnet *ifp = &sc->sc_ic.ic_if;
5206 lwkt_serialize_enter(ifp->if_serializer);
5208 diversity = ath_hal_getdiversity(sc->sc_ah);
5209 error = sysctl_handle_int(oidp, &diversity, 0, req);
5210 if (error || !req->newptr)
5212 if (!ath_hal_setdiversity(sc->sc_ah, diversity)) {
5216 sc->sc_diversity = diversity;
5219 lwkt_serialize_exit(ifp->if_serializer);
5224 ath_sysctl_diag(SYSCTL_HANDLER_ARGS)
5226 struct ath_softc *sc = arg1;
5227 struct ifnet *ifp = &sc->sc_ic.ic_if;
5231 lwkt_serialize_enter(ifp->if_serializer);
5233 if (!ath_hal_getdiag(sc->sc_ah, &diag)) {
5237 error = sysctl_handle_int(oidp, &diag, 0, req);
5238 if (error || !req->newptr)
5240 error = !ath_hal_setdiag(sc->sc_ah, diag) ? EINVAL : 0;
5242 lwkt_serialize_exit(ifp->if_serializer);
5247 ath_sysctl_tpscale(SYSCTL_HANDLER_ARGS)
5249 struct ath_softc *sc = arg1;
5250 struct ifnet *ifp = &sc->sc_ic.ic_if;
5254 lwkt_serialize_enter(ifp->if_serializer);
5256 ath_hal_gettpscale(sc->sc_ah, &scale);
5257 error = sysctl_handle_int(oidp, &scale, 0, req);
5258 if (error || !req->newptr)
5260 error = !ath_hal_settpscale(sc->sc_ah, scale) ? EINVAL : ath_reset(ifp);
5262 lwkt_serialize_exit(ifp->if_serializer);
5267 ath_sysctl_tpc(SYSCTL_HANDLER_ARGS)
5269 struct ath_softc *sc = arg1;
5270 struct ifnet *ifp = &sc->sc_ic.ic_if;
5274 lwkt_serialize_enter(ifp->if_serializer);
5276 tpc = ath_hal_gettpc(sc->sc_ah);
5277 error = sysctl_handle_int(oidp, &tpc, 0, req);
5278 if (error || !req->newptr)
5280 error = !ath_hal_settpc(sc->sc_ah, tpc) ? EINVAL : 0;
5282 lwkt_serialize_exit(ifp->if_serializer);
5287 ath_sysctl_rfkill(SYSCTL_HANDLER_ARGS)
5289 struct ath_softc *sc = arg1;
5290 struct ifnet *ifp = &sc->sc_ic.ic_if;
5291 struct ath_hal *ah = sc->sc_ah;
5295 lwkt_serialize_enter(ifp->if_serializer);
5297 rfkill = ath_hal_getrfkill(ah);
5298 error = sysctl_handle_int(oidp, &rfkill, 0, req);
5299 if (error || !req->newptr)
5304 if (rfkill == ath_hal_getrfkill(ah)) /* unchanged */
5307 if (!ath_hal_setrfkill(ah, rfkill) || ath_reset(&sc->sc_ic.ic_if) != 0)
5310 lwkt_serialize_exit(ifp->if_serializer);
5315 ath_sysctl_rfsilent(SYSCTL_HANDLER_ARGS)
5317 struct ath_softc *sc = arg1;
5318 struct ifnet *ifp = &sc->sc_ic.ic_if;
5322 lwkt_serialize_enter(ifp->if_serializer);
5324 ath_hal_getrfsilent(sc->sc_ah, &rfsilent);
5325 error = sysctl_handle_int(oidp, &rfsilent, 0, req);
5326 if (error || !req->newptr)
5328 if (!ath_hal_setrfsilent(sc->sc_ah, rfsilent)) {
5332 sc->sc_rfsilentpin = rfsilent & 0x1c;
5333 sc->sc_rfsilentpol = (rfsilent & 0x2) != 0;
5336 lwkt_serialize_exit(ifp->if_serializer);
5341 ath_sysctl_regdomain(SYSCTL_HANDLER_ARGS)
5343 struct ath_softc *sc = arg1;
5344 struct ifnet *ifp = &sc->sc_ic.ic_if;
5348 lwkt_serialize_enter(ifp->if_serializer);
5350 if (!ath_hal_getregdomain(sc->sc_ah, &rd)) {
5354 error = sysctl_handle_int(oidp, &rd, 0, req);
5355 if (error || !req->newptr)
5357 error = !ath_hal_setregdomain(sc->sc_ah, rd) ? EINVAL : 0;
5359 lwkt_serialize_exit(ifp->if_serializer);
5364 ath_sysctl_tpack(SYSCTL_HANDLER_ARGS)
5366 struct ath_softc *sc = arg1;
5367 struct ifnet *ifp = &sc->sc_ic.ic_if;
5371 lwkt_serialize_enter(ifp->if_serializer);
5373 ath_hal_gettpack(sc->sc_ah, &tpack);
5374 error = sysctl_handle_int(oidp, &tpack, 0, req);
5375 if (error || !req->newptr)
5377 error = !ath_hal_settpack(sc->sc_ah, tpack) ? EINVAL : 0;
5379 lwkt_serialize_exit(ifp->if_serializer);
5384 ath_sysctl_tpcts(SYSCTL_HANDLER_ARGS)
5386 struct ath_softc *sc = arg1;
5387 struct ifnet *ifp = &sc->sc_ic.ic_if;
5391 lwkt_serialize_enter(ifp->if_serializer);
5393 ath_hal_gettpcts(sc->sc_ah, &tpcts);
5394 error = sysctl_handle_int(oidp, &tpcts, 0, req);
5395 if (error || !req->newptr)
5397 error = !ath_hal_settpcts(sc->sc_ah, tpcts) ? EINVAL : 0;
5399 lwkt_serialize_exit(ifp->if_serializer);
5404 ath_sysctlattach(struct ath_softc *sc)
5406 struct sysctl_ctx_list *ctx = &sc->sc_sysctl_ctx;
5407 struct sysctl_oid *tree = sc->sc_sysctl_tree;
5408 struct ath_hal *ah = sc->sc_ah;
5410 ath_hal_getcountrycode(sc->sc_ah, &sc->sc_countrycode);
5411 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
5412 "countrycode", CTLFLAG_RD, &sc->sc_countrycode, 0,
5413 "EEPROM country code");
5414 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
5415 "regdomain", CTLTYPE_INT | CTLFLAG_RW, sc, 0,
5416 ath_sysctl_regdomain, "I", "EEPROM regdomain code");
5418 sc->sc_debug = ath_debug;
5419 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
5420 "debug", CTLFLAG_RW, &sc->sc_debug, 0,
5421 "control debugging printfs");
5423 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
5424 "slottime", CTLTYPE_INT | CTLFLAG_RW, sc, 0,
5425 ath_sysctl_slottime, "I", "802.11 slot time (us)");
5426 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
5427 "acktimeout", CTLTYPE_INT | CTLFLAG_RW, sc, 0,
5428 ath_sysctl_acktimeout, "I", "802.11 ACK timeout (us)");
5429 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
5430 "ctstimeout", CTLTYPE_INT | CTLFLAG_RW, sc, 0,
5431 ath_sysctl_ctstimeout, "I", "802.11 CTS timeout (us)");
5432 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
5433 "softled", CTLTYPE_INT | CTLFLAG_RW, sc, 0,
5434 ath_sysctl_softled, "I", "enable/disable software LED support");
5435 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
5436 "ledpin", CTLFLAG_RW, &sc->sc_ledpin, 0,
5437 "GPIO pin connected to LED");
5438 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
5439 "ledon", CTLFLAG_RW, &sc->sc_ledon, 0,
5440 "setting to turn LED on");
5441 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
5442 "ledidle", CTLFLAG_RW, &sc->sc_ledidle, 0,
5443 "idle time for inactivity LED (ticks)");
5444 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
5445 "txantenna", CTLFLAG_RW, &sc->sc_txantenna, 0,
5446 "tx antenna (0=auto)");
5447 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
5448 "rxantenna", CTLTYPE_INT | CTLFLAG_RW, sc, 0,
5449 ath_sysctl_rxantenna, "I", "default/rx antenna");
5450 if (ath_hal_hasdiversity(ah))
5451 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
5452 "diversity", CTLTYPE_INT | CTLFLAG_RW, sc, 0,
5453 ath_sysctl_diversity, "I", "antenna diversity");
5454 sc->sc_txintrperiod = ATH_TXINTR_PERIOD;
5455 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
5456 "txintrperiod", CTLFLAG_RW, &sc->sc_txintrperiod, 0,
5457 "tx descriptor batching");
5458 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
5459 "diag", CTLTYPE_INT | CTLFLAG_RW, sc, 0,
5460 ath_sysctl_diag, "I", "h/w diagnostic control");
5461 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
5462 "tpscale", CTLTYPE_INT | CTLFLAG_RW, sc, 0,
5463 ath_sysctl_tpscale, "I", "tx power scaling");
5464 if (ath_hal_hastpc(ah)) {
5465 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
5466 "tpc", CTLTYPE_INT | CTLFLAG_RW, sc, 0,
5467 ath_sysctl_tpc, "I", "enable/disable per-packet TPC");
5468 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
5469 "tpack", CTLTYPE_INT | CTLFLAG_RW, sc, 0,
5470 ath_sysctl_tpack, "I", "tx power for ack frames");
5471 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
5472 "tpcts", CTLTYPE_INT | CTLFLAG_RW, sc, 0,
5473 ath_sysctl_tpcts, "I", "tx power for cts frames");
5475 if (ath_hal_hasrfsilent(ah)) {
5476 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
5477 "rfsilent", CTLTYPE_INT | CTLFLAG_RW, sc, 0,
5478 ath_sysctl_rfsilent, "I", "h/w RF silent config");
5479 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
5480 "rfkill", CTLTYPE_INT | CTLFLAG_RW, sc, 0,
5481 ath_sysctl_rfkill, "I", "enable/disable RF kill switch");
5483 sc->sc_monpass = HAL_RXERR_DECRYPT | HAL_RXERR_MIC;
5484 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
5485 "monpass", CTLFLAG_RW, &sc->sc_monpass, 0,
5486 "mask of error frames to pass when monitoring");
5490 ath_bpfattach(struct ath_softc *sc)
5492 struct ifnet *ifp = &sc->sc_ic.ic_if;
5494 bpfattach_dlt(ifp, DLT_IEEE802_11_RADIO,
5495 sizeof(struct ieee80211_frame) + sizeof(sc->sc_tx_th),
5498 * Initialize constant fields.
5499 * XXX make header lengths a multiple of 32-bits so subsequent
5500 * headers are properly aligned; this is a kludge to keep
5501 * certain applications happy.
5503 * NB: the channel is setup each time we transition to the
5504 * RUN state to avoid filling it in for each frame.
5506 sc->sc_tx_th_len = roundup(sizeof(sc->sc_tx_th), sizeof(uint32_t));
5507 sc->sc_tx_th.wt_ihdr.it_len = htole16(sc->sc_tx_th_len);
5508 sc->sc_tx_th.wt_ihdr.it_present = htole32(ATH_TX_RADIOTAP_PRESENT);
5510 sc->sc_rx_th_len = roundup(sizeof(sc->sc_rx_th), sizeof(uint32_t));
5511 sc->sc_rx_th.wr_ihdr.it_len = htole16(sc->sc_rx_th_len);
5512 sc->sc_rx_th.wr_ihdr.it_present = htole32(ATH_RX_RADIOTAP_PRESENT);
5516 * Announce various information on device/driver attach.
5519 ath_announce(struct ath_softc *sc)
5521 #define HAL_MODE_DUALBAND (HAL_MODE_11A|HAL_MODE_11B)
5522 struct ifnet *ifp = &sc->sc_ic.ic_if;
5523 struct ath_hal *ah = sc->sc_ah;
5526 if_printf(ifp, "mac %d.%d phy %d.%d",
5527 ah->ah_macVersion, ah->ah_macRev,
5528 ah->ah_phyRev >> 4, ah->ah_phyRev & 0xf);
5530 * Print radio revision(s). We check the wireless modes
5531 * to avoid falsely printing revs for inoperable parts.
5532 * Dual-band radio revs are returned in the 5Ghz rev number.
5534 ath_hal_getcountrycode(ah, &cc);
5535 modes = ath_hal_getwirelessmodes(ah, cc);
5536 if ((modes & HAL_MODE_DUALBAND) == HAL_MODE_DUALBAND) {
5537 if (ah->ah_analog5GhzRev && ah->ah_analog2GhzRev)
5538 printf(" 5ghz radio %d.%d 2ghz radio %d.%d",
5539 ah->ah_analog5GhzRev >> 4,
5540 ah->ah_analog5GhzRev & 0xf,
5541 ah->ah_analog2GhzRev >> 4,
5542 ah->ah_analog2GhzRev & 0xf);
5544 printf(" radio %d.%d", ah->ah_analog5GhzRev >> 4,
5545 ah->ah_analog5GhzRev & 0xf);
5547 printf(" radio %d.%d", ah->ah_analog5GhzRev >> 4,
5548 ah->ah_analog5GhzRev & 0xf);
5552 for (i = 0; i <= WME_AC_VO; i++) {
5553 struct ath_txq *txq = sc->sc_ac2q[i];
5554 if_printf(ifp, "Use hw queue %u for %s traffic\n",
5555 txq->axq_qnum, ieee80211_wme_acnames[i]);
5557 if_printf(ifp, "Use hw queue %u for CAB traffic\n",
5558 sc->sc_cabq->axq_qnum);
5559 if_printf(ifp, "Use hw queue %u for beacons\n", sc->sc_bhalq);
5561 if (ath_rxbuf != ATH_RXBUF)
5562 if_printf(ifp, "using %u rx buffers\n", ath_rxbuf);
5563 if (ath_txbuf != ATH_TXBUF)
5564 if_printf(ifp, "using %u tx buffers\n", ath_txbuf);
5565 #undef HAL_MODE_DUALBAND
5569 ath_dma_map_mbuf(void *arg, bus_dma_segment_t *segs, int nseg,
5570 bus_size_t mapsize, int error)
5572 struct ath_buf *bf = arg;
5577 KASSERT(nseg <= ATH_MAX_SCATTER, ("too many DMA segments"));
5578 bcopy(segs, bf->bf_segs, nseg * sizeof(bus_dma_segment_t));