3 * Joerg Sonnenberger <joerg@bec.de>. All rights reserved.
5 * Copyright (c) 1997, 1998-2003
6 * Bill Paul <wpaul@windriver.com>. All rights reserved.
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. All advertising materials mentioning features or use of this software
17 * must display the following acknowledgement:
18 * This product includes software developed by Bill Paul.
19 * 4. Neither the name of the author nor the names of any co-contributors
20 * may be used to endorse or promote products derived from this software
21 * without specific prior written permission.
23 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
26 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
33 * THE POSSIBILITY OF SUCH DAMAGE.
35 * $FreeBSD: src/sys/dev/re/if_re.c,v 1.25 2004/06/09 14:34:01 naddy Exp $
36 * $DragonFly: src/sys/dev/netif/re/if_re.c,v 1.23 2006/09/05 00:55:40 dillon Exp $
40 * RealTek 8139C+/8169/8169S/8110S PCI NIC driver
42 * Written by Bill Paul <wpaul@windriver.com>
43 * Senior Networking Software Engineer
48 * This driver is designed to support RealTek's next generation of
49 * 10/100 and 10/100/1000 PCI ethernet controllers. There are currently
50 * four devices in this family: the RTL8139C+, the RTL8169, the RTL8169S
53 * The 8139C+ is a 10/100 ethernet chip. It is backwards compatible
54 * with the older 8139 family, however it also supports a special
55 * C+ mode of operation that provides several new performance enhancing
56 * features. These include:
58 * o Descriptor based DMA mechanism. Each descriptor represents
59 * a single packet fragment. Data buffers may be aligned on
64 * o TCP/IP checksum offload for both RX and TX
66 * o High and normal priority transmit DMA rings
68 * o VLAN tag insertion and extraction
70 * o TCP large send (segmentation offload)
72 * Like the 8139, the 8139C+ also has a built-in 10/100 PHY. The C+
73 * programming API is fairly straightforward. The RX filtering, EEPROM
74 * access and PHY access is the same as it is on the older 8139 series
77 * The 8169 is a 64-bit 10/100/1000 gigabit ethernet MAC. It has almost the
78 * same programming API and feature set as the 8139C+ with the following
79 * differences and additions:
85 * o GMII and TBI ports/registers for interfacing with copper
88 * o RX and TX DMA rings can have up to 1024 descriptors
89 * (the 8139C+ allows a maximum of 64)
91 * o Slight differences in register layout from the 8139C+
93 * The TX start and timer interrupt registers are at different locations
94 * on the 8169 than they are on the 8139C+. Also, the status word in the
95 * RX descriptor has a slightly different bit layout. The 8169 does not
96 * have a built-in PHY. Most reference boards use a Marvell 88E1000 'Alaska'
99 * The 8169S/8110S 10/100/1000 devices have built-in copper gigE PHYs
100 * (the 'S' stands for 'single-chip'). These devices have the same
101 * programming API as the older 8169, but also have some vendor-specific
102 * registers for the on-board PHY. The 8110S is a LAN-on-motherboard
103 * part designed to be pin-compatible with the RealTek 8100 10/100 chip.
105 * This driver takes advantage of the RX and TX checksum offload and
106 * VLAN tag insertion/extraction features. It also implements TX
107 * interrupt moderation using the timer interrupt registers, which
108 * significantly reduces TX interrupt load. There is also support
109 * for jumbo frames, however the 8169/8169S/8110S can not transmit
110 * jumbo frames larger than 7440, so the max MTU possible with this
111 * driver is 7422 bytes.
114 #include "opt_polling.h"
116 #include <sys/param.h>
117 #include <sys/endian.h>
118 #include <sys/systm.h>
119 #include <sys/sockio.h>
120 #include <sys/mbuf.h>
121 #include <sys/malloc.h>
122 #include <sys/module.h>
123 #include <sys/kernel.h>
124 #include <sys/socket.h>
125 #include <sys/serialize.h>
126 #include <sys/thread2.h>
129 #include <net/ifq_var.h>
130 #include <net/if_arp.h>
131 #include <net/ethernet.h>
132 #include <net/if_dl.h>
133 #include <net/if_media.h>
134 #include <net/if_types.h>
135 #include <net/vlan/if_vlan_var.h>
139 #include <machine/bus_pio.h>
140 #include <machine/bus_memio.h>
141 #include <machine/bus.h>
142 #include <machine/resource.h>
144 #include <sys/rman.h>
146 #include <dev/netif/mii_layer/mii.h>
147 #include <dev/netif/mii_layer/miivar.h>
149 #include <bus/pci/pcidevs.h>
150 #include <bus/pci/pcireg.h>
151 #include <bus/pci/pcivar.h>
153 /* "controller miibus0" required. See GENERIC if you get errors here. */
154 #include "miibus_if.h"
156 #include <dev/netif/re/if_rereg.h>
159 * The hardware supports checksumming but, as usual, some chipsets screw it
160 * all up and produce bogus packets, so we disable it by default.
162 #define RE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
163 #define RE_DISABLE_HWCSUM
166 * Various supported device vendors/types and their names.
168 static struct re_type re_devs[] = {
169 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE528T, RE_HWREV_8169S,
170 "D-Link DGE-528(T) Gigabit Ethernet Adapter" },
171 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8139, RE_HWREV_8139CPLUS,
172 "RealTek 8139C+ 10/100BaseTX" },
173 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8169, RE_HWREV_8169,
174 "RealTek 8169 Gigabit Ethernet" },
175 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8169, RE_HWREV_8169S,
176 "RealTek 8169S Single-chip Gigabit Ethernet" },
177 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8169, RE_HWREV_8110S,
178 "RealTek 8110S Single-chip Gigabit Ethernet" },
182 static struct re_hwrev re_hwrevs[] = {
183 { RE_HWREV_8139CPLUS, RE_8139CPLUS, "C+"},
184 { RE_HWREV_8169, RE_8169, "8169"},
185 { RE_HWREV_8169S, RE_8169, "8169S"},
186 { RE_HWREV_8110S, RE_8169, "8110S"},
190 static int re_probe(device_t);
191 static int re_attach(device_t);
192 static int re_detach(device_t);
194 static int re_encap(struct re_softc *, struct mbuf **, int *, int *);
196 static void re_dma_map_addr(void *, bus_dma_segment_t *, int, int);
197 static void re_dma_map_desc(void *, bus_dma_segment_t *, int,
199 static int re_allocmem(device_t, struct re_softc *);
200 static int re_newbuf(struct re_softc *, int, struct mbuf *);
201 static int re_rx_list_init(struct re_softc *);
202 static int re_tx_list_init(struct re_softc *);
203 static void re_rxeof(struct re_softc *);
204 static void re_txeof(struct re_softc *);
205 static void re_intr(void *);
206 static void re_tick(void *);
207 static void re_tick_serialized(void *);
208 static void re_start(struct ifnet *);
209 static int re_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
210 static void re_init(void *);
211 static void re_stop(struct re_softc *);
212 static void re_watchdog(struct ifnet *);
213 static int re_suspend(device_t);
214 static int re_resume(device_t);
215 static void re_shutdown(device_t);
216 static int re_ifmedia_upd(struct ifnet *);
217 static void re_ifmedia_sts(struct ifnet *, struct ifmediareq *);
219 static void re_eeprom_putbyte(struct re_softc *, int);
220 static void re_eeprom_getword(struct re_softc *, int, u_int16_t *);
221 static void re_read_eeprom(struct re_softc *, caddr_t, int, int, int);
222 static int re_gmii_readreg(device_t, int, int);
223 static int re_gmii_writereg(device_t, int, int, int);
225 static int re_miibus_readreg(device_t, int, int);
226 static int re_miibus_writereg(device_t, int, int, int);
227 static void re_miibus_statchg(device_t);
229 static void re_setmulti(struct re_softc *);
230 static void re_reset(struct re_softc *);
232 static int re_diag(struct re_softc *);
233 #ifdef DEVICE_POLLING
234 static void re_poll(struct ifnet *ifp, enum poll_cmd cmd, int count);
237 static device_method_t re_methods[] = {
238 /* Device interface */
239 DEVMETHOD(device_probe, re_probe),
240 DEVMETHOD(device_attach, re_attach),
241 DEVMETHOD(device_detach, re_detach),
242 DEVMETHOD(device_suspend, re_suspend),
243 DEVMETHOD(device_resume, re_resume),
244 DEVMETHOD(device_shutdown, re_shutdown),
247 DEVMETHOD(bus_print_child, bus_generic_print_child),
248 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
251 DEVMETHOD(miibus_readreg, re_miibus_readreg),
252 DEVMETHOD(miibus_writereg, re_miibus_writereg),
253 DEVMETHOD(miibus_statchg, re_miibus_statchg),
258 static driver_t re_driver = {
261 sizeof(struct re_softc)
264 static devclass_t re_devclass;
266 DECLARE_DUMMY_MODULE(if_re);
267 DRIVER_MODULE(if_re, pci, re_driver, re_devclass, 0, 0);
268 DRIVER_MODULE(if_re, cardbus, re_driver, re_devclass, 0, 0);
269 DRIVER_MODULE(miibus, re, miibus_driver, miibus_devclass, 0, 0);
272 CSR_WRITE_1(sc, RE_EECMD, CSR_READ_1(sc, RE_EECMD) | (x))
275 CSR_WRITE_1(sc, RE_EECMD, CSR_READ_1(sc, RE_EECMD) & ~(x))
278 * Send a read command and address to the EEPROM, check for ACK.
281 re_eeprom_putbyte(struct re_softc *sc, int addr)
285 d = addr | sc->re_eecmd_read;
288 * Feed in each bit and strobe the clock.
290 for (i = 0x400; i != 0; i >>= 1) {
292 EE_SET(RE_EE_DATAIN);
294 EE_CLR(RE_EE_DATAIN);
304 * Read a word of data stored in the EEPROM at address 'addr.'
307 re_eeprom_getword(struct re_softc *sc, int addr, uint16_t *dest)
312 /* Enter EEPROM access mode. */
313 CSR_WRITE_1(sc, RE_EECMD, RE_EEMODE_PROGRAM|RE_EE_SEL);
316 * Send address of word we want to read.
318 re_eeprom_putbyte(sc, addr);
320 CSR_WRITE_1(sc, RE_EECMD, RE_EEMODE_PROGRAM|RE_EE_SEL);
323 * Start reading bits from EEPROM.
325 for (i = 0x8000; i != 0; i >>= 1) {
328 if (CSR_READ_1(sc, RE_EECMD) & RE_EE_DATAOUT)
334 /* Turn off EEPROM access mode. */
335 CSR_WRITE_1(sc, RE_EECMD, RE_EEMODE_OFF);
341 * Read a sequence of words from the EEPROM.
344 re_read_eeprom(struct re_softc *sc, caddr_t dest, int off, int cnt, int swap)
347 uint16_t word = 0, *ptr;
349 for (i = 0; i < cnt; i++) {
350 re_eeprom_getword(sc, off + i, &word);
351 ptr = (u_int16_t *)(dest + (i * 2));
353 *ptr = be16toh(word);
360 re_gmii_readreg(device_t dev, int phy, int reg)
362 struct re_softc *sc = device_get_softc(dev);
369 /* Let the rgephy driver read the GMEDIASTAT register */
371 if (reg == RE_GMEDIASTAT)
372 return(CSR_READ_1(sc, RE_GMEDIASTAT));
374 CSR_WRITE_4(sc, RE_PHYAR, reg << 16);
377 for (i = 0; i < RE_TIMEOUT; i++) {
378 rval = CSR_READ_4(sc, RE_PHYAR);
379 if (rval & RE_PHYAR_BUSY)
384 if (i == RE_TIMEOUT) {
385 device_printf(dev, "PHY read failed\n");
389 return(rval & RE_PHYAR_PHYDATA);
393 re_gmii_writereg(device_t dev, int phy, int reg, int data)
395 struct re_softc *sc = device_get_softc(dev);
399 CSR_WRITE_4(sc, RE_PHYAR,
400 (reg << 16) | (data & RE_PHYAR_PHYDATA) | RE_PHYAR_BUSY);
403 for (i = 0; i < RE_TIMEOUT; i++) {
404 rval = CSR_READ_4(sc, RE_PHYAR);
405 if ((rval & RE_PHYAR_BUSY) == 0)
411 device_printf(dev, "PHY write failed\n");
417 re_miibus_readreg(device_t dev, int phy, int reg)
419 struct re_softc *sc = device_get_softc(dev);
421 uint16_t re8139_reg = 0;
423 if (sc->re_type == RE_8169) {
424 rval = re_gmii_readreg(dev, phy, reg);
428 /* Pretend the internal PHY is only at address 0 */
434 re8139_reg = RE_BMCR;
437 re8139_reg = RE_BMSR;
440 re8139_reg = RE_ANAR;
443 re8139_reg = RE_ANER;
446 re8139_reg = RE_LPAR;
452 * Allow the rlphy driver to read the media status
453 * register. If we have a link partner which does not
454 * support NWAY, this is the register which will tell
455 * us the results of parallel detection.
458 return(CSR_READ_1(sc, RE_MEDIASTAT));
460 device_printf(dev, "bad phy register\n");
463 rval = CSR_READ_2(sc, re8139_reg);
468 re_miibus_writereg(device_t dev, int phy, int reg, int data)
470 struct re_softc *sc= device_get_softc(dev);
471 u_int16_t re8139_reg = 0;
473 if (sc->re_type == RE_8169)
474 return(re_gmii_writereg(dev, phy, reg, data));
476 /* Pretend the internal PHY is only at address 0 */
482 re8139_reg = RE_BMCR;
485 re8139_reg = RE_BMSR;
488 re8139_reg = RE_ANAR;
491 re8139_reg = RE_ANER;
494 re8139_reg = RE_LPAR;
500 device_printf(dev, "bad phy register\n");
503 CSR_WRITE_2(sc, re8139_reg, data);
508 re_miibus_statchg(device_t dev)
513 * Program the 64-bit multicast hash filter.
516 re_setmulti(struct re_softc *sc)
518 struct ifnet *ifp = &sc->arpcom.ac_if;
520 uint32_t hashes[2] = { 0, 0 };
521 struct ifmultiaddr *ifma;
525 rxfilt = CSR_READ_4(sc, RE_RXCFG);
527 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
528 rxfilt |= RE_RXCFG_RX_MULTI;
529 CSR_WRITE_4(sc, RE_RXCFG, rxfilt);
530 CSR_WRITE_4(sc, RE_MAR0, 0xFFFFFFFF);
531 CSR_WRITE_4(sc, RE_MAR4, 0xFFFFFFFF);
535 /* first, zot all the existing hash bits */
536 CSR_WRITE_4(sc, RE_MAR0, 0);
537 CSR_WRITE_4(sc, RE_MAR4, 0);
539 /* now program new ones */
540 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
541 if (ifma->ifma_addr->sa_family != AF_LINK)
543 h = ether_crc32_be(LLADDR((struct sockaddr_dl *)
544 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26;
546 hashes[0] |= (1 << h);
548 hashes[1] |= (1 << (h - 32));
553 rxfilt |= RE_RXCFG_RX_MULTI;
555 rxfilt &= ~RE_RXCFG_RX_MULTI;
557 CSR_WRITE_4(sc, RE_RXCFG, rxfilt);
558 CSR_WRITE_4(sc, RE_MAR0, hashes[0]);
559 CSR_WRITE_4(sc, RE_MAR4, hashes[1]);
563 re_reset(struct re_softc *sc)
567 CSR_WRITE_1(sc, RE_COMMAND, RE_CMD_RESET);
569 for (i = 0; i < RE_TIMEOUT; i++) {
571 if ((CSR_READ_1(sc, RE_COMMAND) & RE_CMD_RESET) == 0)
575 if_printf(&sc->arpcom.ac_if, "reset never completed!\n");
577 CSR_WRITE_1(sc, 0x82, 1);
581 * The following routine is designed to test for a defect on some
582 * 32-bit 8169 cards. Some of these NICs have the REQ64# and ACK64#
583 * lines connected to the bus, however for a 32-bit only card, they
584 * should be pulled high. The result of this defect is that the
585 * NIC will not work right if you plug it into a 64-bit slot: DMA
586 * operations will be done with 64-bit transfers, which will fail
587 * because the 64-bit data lines aren't connected.
589 * There's no way to work around this (short of talking a soldering
590 * iron to the board), however we can detect it. The method we use
591 * here is to put the NIC into digital loopback mode, set the receiver
592 * to promiscuous mode, and then try to send a frame. We then compare
593 * the frame data we sent to what was received. If the data matches,
594 * then the NIC is working correctly, otherwise we know the user has
595 * a defective NIC which has been mistakenly plugged into a 64-bit PCI
596 * slot. In the latter case, there's no way the NIC can work correctly,
597 * so we print out a message on the console and abort the device attach.
601 re_diag(struct re_softc *sc)
603 struct ifnet *ifp = &sc->arpcom.ac_if;
605 struct ether_header *eh;
606 struct re_desc *cur_rx;
609 int total_len, i, error = 0;
610 uint8_t dst[ETHER_ADDR_LEN] = { 0x00, 'h', 'e', 'l', 'l', 'o' };
611 uint8_t src[ETHER_ADDR_LEN] = { 0x00, 'w', 'o', 'r', 'l', 'd' };
613 /* Allocate a single mbuf */
615 MGETHDR(m0, MB_DONTWAIT, MT_DATA);
620 * Initialize the NIC in test mode. This sets the chip up
621 * so that it can send and receive frames, but performs the
622 * following special functions:
623 * - Puts receiver in promiscuous mode
624 * - Enables digital loopback mode
625 * - Leaves interrupts turned off
628 ifp->if_flags |= IFF_PROMISC;
635 /* Put some data in the mbuf */
637 eh = mtod(m0, struct ether_header *);
638 bcopy (dst, eh->ether_dhost, ETHER_ADDR_LEN);
639 bcopy (src, eh->ether_shost, ETHER_ADDR_LEN);
640 eh->ether_type = htons(ETHERTYPE_IP);
641 m0->m_pkthdr.len = m0->m_len = ETHER_MIN_LEN - ETHER_CRC_LEN;
644 * Queue the packet, start transmission.
645 * Note: ifq_handoff() ultimately calls re_start() for us.
648 CSR_WRITE_2(sc, RE_ISR, 0xFFFF);
649 error = ifq_handoff(ifp, m0, NULL);
656 /* Wait for it to propagate through the chip */
659 for (i = 0; i < RE_TIMEOUT; i++) {
660 status = CSR_READ_2(sc, RE_ISR);
661 if ((status & (RE_ISR_TIMEOUT_EXPIRED|RE_ISR_RX_OK)) ==
662 (RE_ISR_TIMEOUT_EXPIRED|RE_ISR_RX_OK))
667 if (i == RE_TIMEOUT) {
668 if_printf(ifp, "diagnostic failed to receive packet "
669 "in loopback mode\n");
675 * The packet should have been dumped into the first
676 * entry in the RX DMA ring. Grab it from there.
679 bus_dmamap_sync(sc->re_ldata.re_rx_list_tag,
680 sc->re_ldata.re_rx_list_map, BUS_DMASYNC_POSTREAD);
681 bus_dmamap_sync(sc->re_ldata.re_mtag, sc->re_ldata.re_rx_dmamap[0],
682 BUS_DMASYNC_POSTWRITE);
683 bus_dmamap_unload(sc->re_ldata.re_mtag, sc->re_ldata.re_rx_dmamap[0]);
685 m0 = sc->re_ldata.re_rx_mbuf[0];
686 sc->re_ldata.re_rx_mbuf[0] = NULL;
687 eh = mtod(m0, struct ether_header *);
689 cur_rx = &sc->re_ldata.re_rx_list[0];
690 total_len = RE_RXBYTES(cur_rx);
691 rxstat = le32toh(cur_rx->re_cmdstat);
693 if (total_len != ETHER_MIN_LEN) {
694 if_printf(ifp, "diagnostic failed, received short packet\n");
699 /* Test that the received packet data matches what we sent. */
701 if (bcmp(eh->ether_dhost, dst, ETHER_ADDR_LEN) ||
702 bcmp(eh->ether_shost, &src, ETHER_ADDR_LEN) ||
703 be16toh(eh->ether_type) != ETHERTYPE_IP) {
704 if_printf(ifp, "WARNING, DMA FAILURE!\n");
705 if_printf(ifp, "expected TX data: %6D/%6D/0x%x\n",
706 dst, ":", src, ":", ETHERTYPE_IP);
707 if_printf(ifp, "received RX data: %6D/%6D/0x%x\n",
708 eh->ether_dhost, ":", eh->ether_shost, ":",
709 ntohs(eh->ether_type));
710 if_printf(ifp, "You may have a defective 32-bit NIC plugged "
711 "into a 64-bit PCI slot.\n");
712 if_printf(ifp, "Please re-install the NIC in a 32-bit slot "
713 "for proper operation.\n");
714 if_printf(ifp, "Read the re(4) man page for more details.\n");
719 /* Turn interface off, release resources */
722 ifp->if_flags &= ~IFF_PROMISC;
731 * Probe for a RealTek 8139C+/8169/8110 chip. Check the PCI vendor and device
732 * IDs against our list and return a device name if we find a match.
735 re_probe(device_t dev)
741 uint16_t vendor, product;
745 vendor = pci_get_vendor(dev);
746 product = pci_get_device(dev);
748 for (t = re_devs; t->re_name != NULL; t++) {
749 if (product == t->re_did && vendor == t->re_vid)
754 * Check if we found a RealTek device.
756 if (t->re_name == NULL)
760 * Temporarily map the I/O space so we can read the chip ID register.
762 sc = kmalloc(sizeof(*sc), M_TEMP, M_WAITOK | M_ZERO);
764 sc->re_res = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &rid,
766 if (sc->re_res == NULL) {
767 device_printf(dev, "couldn't map ports/memory\n");
772 sc->re_btag = rman_get_bustag(sc->re_res);
773 sc->re_bhandle = rman_get_bushandle(sc->re_res);
775 hwrev = CSR_READ_4(sc, RE_TXCFG) & RE_TXCFG_HWREV;
776 bus_release_resource(dev, SYS_RES_IOPORT, RE_PCI_LOIO, sc->re_res);
780 * and continue matching for the specific chip...
782 for (; t->re_name != NULL; t++) {
783 if (product == t->re_did && vendor == t->re_vid &&
784 t->re_basetype == hwrev) {
785 device_set_desc(dev, t->re_name);
793 * This routine takes the segment list provided as the result of
794 * a bus_dma_map_load() operation and assigns the addresses/lengths
795 * to RealTek DMA descriptors. This can be called either by the RX
796 * code or the TX code. In the RX case, we'll probably wind up mapping
797 * at most one segment. For the TX case, there could be any number of
798 * segments since TX packets may span multiple mbufs. In either case,
799 * if the number of segments is larger than the re_maxsegs limit
800 * specified by the caller, we abort the mapping operation. Sadly,
801 * whoever designed the buffer mapping API did not provide a way to
802 * return an error from here, so we have to fake it a bit.
806 re_dma_map_desc(void *arg, bus_dma_segment_t *segs, int nseg,
807 bus_size_t mapsize, int error)
809 struct re_dmaload_arg *ctx;
810 struct re_desc *d = NULL;
819 /* Signal error to caller if there's too many segments */
820 if (nseg > ctx->re_maxsegs) {
826 * Map the segment array into descriptors. Note that we set the
827 * start-of-frame and end-of-frame markers for either TX or RX, but
828 * they really only have meaning in the TX case. (In the RX case,
829 * it's the chip that tells us where packets begin and end.)
830 * We also keep track of the end of the ring and set the
831 * end-of-ring bits as needed, and we set the ownership bits
832 * in all except the very first descriptor. (The caller will
833 * set this descriptor later when it start transmission or
838 d = &ctx->re_ring[idx];
839 if (le32toh(d->re_cmdstat) & RE_RDESC_STAT_OWN) {
843 cmdstat = segs[i].ds_len;
844 d->re_bufaddr_lo = htole32(RE_ADDR_LO(segs[i].ds_addr));
845 d->re_bufaddr_hi = htole32(RE_ADDR_HI(segs[i].ds_addr));
847 cmdstat |= RE_TDESC_CMD_SOF;
849 cmdstat |= RE_TDESC_CMD_OWN;
850 if (idx == (RE_RX_DESC_CNT - 1))
851 cmdstat |= RE_TDESC_CMD_EOR;
852 d->re_cmdstat = htole32(cmdstat | ctx->re_flags);
859 d->re_cmdstat |= htole32(RE_TDESC_CMD_EOF);
860 ctx->re_maxsegs = nseg;
865 * Map a single buffer address.
869 re_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
876 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg));
878 *addr = segs->ds_addr;
882 re_allocmem(device_t dev, struct re_softc *sc)
887 * Allocate map for RX mbufs.
890 error = bus_dma_tag_create(sc->re_parent_tag, ETHER_ALIGN, 0,
891 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL,
892 NULL, MCLBYTES * nseg, nseg, MCLBYTES, BUS_DMA_ALLOCNOW,
893 &sc->re_ldata.re_mtag);
895 device_printf(dev, "could not allocate dma tag\n");
900 * Allocate map for TX descriptor list.
902 error = bus_dma_tag_create(sc->re_parent_tag, RE_RING_ALIGN,
903 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL,
904 NULL, RE_TX_LIST_SZ, 1, RE_TX_LIST_SZ, BUS_DMA_ALLOCNOW,
905 &sc->re_ldata.re_tx_list_tag);
907 device_printf(dev, "could not allocate dma tag\n");
911 /* Allocate DMA'able memory for the TX ring */
913 error = bus_dmamem_alloc(sc->re_ldata.re_tx_list_tag,
914 (void **)&sc->re_ldata.re_tx_list, BUS_DMA_WAITOK | BUS_DMA_ZERO,
915 &sc->re_ldata.re_tx_list_map);
917 device_printf(dev, "could not allocate TX ring\n");
921 /* Load the map for the TX ring. */
923 error = bus_dmamap_load(sc->re_ldata.re_tx_list_tag,
924 sc->re_ldata.re_tx_list_map, sc->re_ldata.re_tx_list,
925 RE_TX_LIST_SZ, re_dma_map_addr,
926 &sc->re_ldata.re_tx_list_addr, BUS_DMA_NOWAIT);
928 device_printf(dev, "could not get addres of TX ring\n");
932 /* Create DMA maps for TX buffers */
934 for (i = 0; i < RE_TX_DESC_CNT; i++) {
935 error = bus_dmamap_create(sc->re_ldata.re_mtag, 0,
936 &sc->re_ldata.re_tx_dmamap[i]);
938 device_printf(dev, "can't create DMA map for TX\n");
944 * Allocate map for RX descriptor list.
946 error = bus_dma_tag_create(sc->re_parent_tag, RE_RING_ALIGN,
947 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL,
948 NULL, RE_TX_LIST_SZ, 1, RE_TX_LIST_SZ, BUS_DMA_ALLOCNOW,
949 &sc->re_ldata.re_rx_list_tag);
951 device_printf(dev, "could not allocate dma tag\n");
955 /* Allocate DMA'able memory for the RX ring */
957 error = bus_dmamem_alloc(sc->re_ldata.re_rx_list_tag,
958 (void **)&sc->re_ldata.re_rx_list, BUS_DMA_WAITOK | BUS_DMA_ZERO,
959 &sc->re_ldata.re_rx_list_map);
961 device_printf(dev, "could not allocate RX ring\n");
965 /* Load the map for the RX ring. */
967 error = bus_dmamap_load(sc->re_ldata.re_rx_list_tag,
968 sc->re_ldata.re_rx_list_map, sc->re_ldata.re_rx_list,
969 RE_TX_LIST_SZ, re_dma_map_addr,
970 &sc->re_ldata.re_rx_list_addr, BUS_DMA_NOWAIT);
972 device_printf(dev, "could not get address of RX ring\n");
976 /* Create DMA maps for RX buffers */
978 for (i = 0; i < RE_RX_DESC_CNT; i++) {
979 error = bus_dmamap_create(sc->re_ldata.re_mtag, 0,
980 &sc->re_ldata.re_rx_dmamap[i]);
982 device_printf(dev, "can't create DMA map for RX\n");
991 * Attach the interface. Allocate softc structures, do ifmedia
992 * setup and ethernet/BPF attach.
995 re_attach(device_t dev)
997 struct re_softc *sc = device_get_softc(dev);
999 struct re_hwrev *hw_rev;
1000 uint8_t eaddr[ETHER_ADDR_LEN];
1002 u_int16_t re_did = 0;
1003 int error = 0, rid, i;
1005 callout_init(&sc->re_timer);
1007 #ifndef BURN_BRIDGES
1009 * Handle power management nonsense.
1012 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
1013 uint32_t membase, irq;
1015 /* Save important PCI config data. */
1016 membase = pci_read_config(dev, RE_PCI_LOMEM, 4);
1017 irq = pci_read_config(dev, PCIR_INTLINE, 4);
1019 /* Reset the power state. */
1020 device_printf(dev, "chip is is in D%d power mode "
1021 "-- setting to D0\n", pci_get_powerstate(dev));
1023 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
1025 /* Restore PCI config data. */
1026 pci_write_config(dev, RE_PCI_LOMEM, membase, 4);
1027 pci_write_config(dev, PCIR_INTLINE, irq, 4);
1031 * Map control/status registers.
1033 pci_enable_busmaster(dev);
1036 sc->re_res = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &rid,
1039 if (sc->re_res == NULL) {
1040 device_printf(dev, "couldn't map ports/memory\n");
1045 sc->re_btag = rman_get_bustag(sc->re_res);
1046 sc->re_bhandle = rman_get_bushandle(sc->re_res);
1048 /* Allocate interrupt */
1050 sc->re_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
1051 RF_SHAREABLE | RF_ACTIVE);
1053 if (sc->re_irq == NULL) {
1054 device_printf(dev, "couldn't map interrupt\n");
1059 /* Reset the adapter. */
1062 hwrev = CSR_READ_4(sc, RE_TXCFG) & RE_TXCFG_HWREV;
1063 for (hw_rev = re_hwrevs; hw_rev->re_desc != NULL; hw_rev++) {
1064 if (hw_rev->re_rev == hwrev) {
1065 sc->re_type = hw_rev->re_type;
1070 if (sc->re_type == RE_8169) {
1071 /* Set RX length mask */
1072 sc->re_rxlenmask = RE_RDESC_STAT_GFRAGLEN;
1074 /* Force station address autoload from the EEPROM */
1075 CSR_WRITE_1(sc, RE_EECMD, RE_EEMODE_AUTOLOAD);
1076 for (i = 0; i < RE_TIMEOUT; i++) {
1077 if ((CSR_READ_1(sc, RE_EECMD) & RE_EEMODE_AUTOLOAD) == 0)
1081 if (i == RE_TIMEOUT)
1082 device_printf(dev, "eeprom autoload timed out\n");
1084 for (i = 0; i < ETHER_ADDR_LEN; i++)
1085 eaddr[i] = CSR_READ_1(sc, RE_IDR0 + i);
1089 /* Set RX length mask */
1090 sc->re_rxlenmask = RE_RDESC_STAT_FRAGLEN;
1092 sc->re_eecmd_read = RE_EECMD_READ_6BIT;
1093 re_read_eeprom(sc, (caddr_t)&re_did, 0, 1, 0);
1094 if (re_did != 0x8129)
1095 sc->re_eecmd_read = RE_EECMD_READ_8BIT;
1098 * Get station address from the EEPROM.
1100 re_read_eeprom(sc, (caddr_t)as, RE_EE_EADDR, 3, 0);
1101 for (i = 0; i < 3; i++) {
1102 eaddr[(i * 2) + 0] = as[i] & 0xff;
1103 eaddr[(i * 2) + 1] = as[i] >> 8;
1108 * Allocate the parent bus DMA tag appropriate for PCI.
1110 #define RE_NSEG_NEW 32
1111 error = bus_dma_tag_create(NULL, /* parent */
1112 1, 0, /* alignment, boundary */
1113 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */
1114 BUS_SPACE_MAXADDR, /* highaddr */
1115 NULL, NULL, /* filter, filterarg */
1116 MAXBSIZE, RE_NSEG_NEW, /* maxsize, nsegments */
1117 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */
1118 BUS_DMA_ALLOCNOW, /* flags */
1119 &sc->re_parent_tag);
1123 error = re_allocmem(dev, sc);
1129 if (mii_phy_probe(dev, &sc->re_miibus,
1130 re_ifmedia_upd, re_ifmedia_sts)) {
1131 device_printf(dev, "MII without any phy!\n");
1136 ifp = &sc->arpcom.ac_if;
1138 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1139 ifp->if_mtu = ETHERMTU;
1140 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1141 ifp->if_ioctl = re_ioctl;
1142 ifp->if_capabilities = IFCAP_VLAN_MTU;
1143 ifp->if_start = re_start;
1144 ifp->if_capabilities |= IFCAP_HWCSUM|IFCAP_VLAN_HWTAGGING;
1145 #ifdef DEVICE_POLLING
1146 ifp->if_poll = re_poll;
1148 ifp->if_watchdog = re_watchdog;
1149 ifp->if_init = re_init;
1150 if (sc->re_type == RE_8169)
1151 ifp->if_baudrate = 1000000000;
1153 ifp->if_baudrate = 100000000;
1154 ifq_set_maxlen(&ifp->if_snd, RE_IFQ_MAXLEN);
1155 ifq_set_ready(&ifp->if_snd);
1156 #ifdef RE_DISABLE_HWCSUM
1157 ifp->if_capenable = ifp->if_capabilities & ~IFCAP_HWCSUM;
1158 ifp->if_hwassist = 0;
1160 ifp->if_capenable = ifp->if_capabilities;
1161 ifp->if_hwassist = RE_CSUM_FEATURES;
1165 * Call MI attach routine.
1167 ether_ifattach(ifp, eaddr, NULL);
1169 lwkt_serialize_enter(ifp->if_serializer);
1170 /* Perform hardware diagnostic. */
1171 error = re_diag(sc);
1172 lwkt_serialize_exit(ifp->if_serializer);
1175 device_printf(dev, "hardware diagnostic failure\n");
1176 ether_ifdetach(ifp);
1180 /* Hook interrupt last to avoid having to lock softc */
1181 error = bus_setup_intr(dev, sc->re_irq, INTR_NETSAFE, re_intr, sc,
1182 &sc->re_intrhand, ifp->if_serializer);
1185 device_printf(dev, "couldn't set up irq\n");
1186 ether_ifdetach(ifp);
1198 * Shutdown hardware and free up resources. This can be called any
1199 * time after the mutex has been initialized. It is called in both
1200 * the error case in attach and the normal detach case so it needs
1201 * to be careful about only freeing resources that have actually been
1205 re_detach(device_t dev)
1207 struct re_softc *sc = device_get_softc(dev);
1208 struct ifnet *ifp = &sc->arpcom.ac_if;
1211 /* These should only be active if attach succeeded */
1212 if (device_is_attached(dev)) {
1213 lwkt_serialize_enter(ifp->if_serializer);
1215 bus_teardown_intr(dev, sc->re_irq, sc->re_intrhand);
1216 lwkt_serialize_exit(ifp->if_serializer);
1218 ether_ifdetach(ifp);
1221 device_delete_child(dev, sc->re_miibus);
1222 bus_generic_detach(dev);
1225 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->re_irq);
1227 bus_release_resource(dev, SYS_RES_IOPORT, RE_PCI_LOIO,
1231 /* Unload and free the RX DMA ring memory and map */
1233 if (sc->re_ldata.re_rx_list_tag) {
1234 bus_dmamap_unload(sc->re_ldata.re_rx_list_tag,
1235 sc->re_ldata.re_rx_list_map);
1236 bus_dmamem_free(sc->re_ldata.re_rx_list_tag,
1237 sc->re_ldata.re_rx_list,
1238 sc->re_ldata.re_rx_list_map);
1239 bus_dma_tag_destroy(sc->re_ldata.re_rx_list_tag);
1242 /* Unload and free the TX DMA ring memory and map */
1244 if (sc->re_ldata.re_tx_list_tag) {
1245 bus_dmamap_unload(sc->re_ldata.re_tx_list_tag,
1246 sc->re_ldata.re_tx_list_map);
1247 bus_dmamem_free(sc->re_ldata.re_tx_list_tag,
1248 sc->re_ldata.re_tx_list,
1249 sc->re_ldata.re_tx_list_map);
1250 bus_dma_tag_destroy(sc->re_ldata.re_tx_list_tag);
1253 /* Destroy all the RX and TX buffer maps */
1255 if (sc->re_ldata.re_mtag) {
1256 for (i = 0; i < RE_TX_DESC_CNT; i++)
1257 bus_dmamap_destroy(sc->re_ldata.re_mtag,
1258 sc->re_ldata.re_tx_dmamap[i]);
1259 for (i = 0; i < RE_RX_DESC_CNT; i++)
1260 bus_dmamap_destroy(sc->re_ldata.re_mtag,
1261 sc->re_ldata.re_rx_dmamap[i]);
1262 bus_dma_tag_destroy(sc->re_ldata.re_mtag);
1265 /* Unload and free the stats buffer and map */
1267 if (sc->re_ldata.re_stag) {
1268 bus_dmamap_unload(sc->re_ldata.re_stag,
1269 sc->re_ldata.re_rx_list_map);
1270 bus_dmamem_free(sc->re_ldata.re_stag,
1271 sc->re_ldata.re_stats,
1272 sc->re_ldata.re_smap);
1273 bus_dma_tag_destroy(sc->re_ldata.re_stag);
1276 if (sc->re_parent_tag)
1277 bus_dma_tag_destroy(sc->re_parent_tag);
1283 re_newbuf(struct re_softc *sc, int idx, struct mbuf *m)
1285 struct re_dmaload_arg arg;
1286 struct mbuf *n = NULL;
1290 n = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR);
1295 m->m_data = m->m_ext.ext_buf;
1298 * Initialize mbuf length fields and fixup
1299 * alignment so that the frame payload is
1302 m->m_len = m->m_pkthdr.len = MCLBYTES;
1303 m_adj(m, ETHER_ALIGN);
1309 arg.re_ring = sc->re_ldata.re_rx_list;
1311 error = bus_dmamap_load_mbuf(sc->re_ldata.re_mtag,
1312 sc->re_ldata.re_rx_dmamap[idx], m, re_dma_map_desc,
1313 &arg, BUS_DMA_NOWAIT);
1314 if (error || arg.re_maxsegs != 1) {
1320 sc->re_ldata.re_rx_list[idx].re_cmdstat |= htole32(RE_RDESC_CMD_OWN);
1321 sc->re_ldata.re_rx_mbuf[idx] = m;
1323 bus_dmamap_sync(sc->re_ldata.re_mtag, sc->re_ldata.re_rx_dmamap[idx],
1324 BUS_DMASYNC_PREREAD);
1330 re_tx_list_init(struct re_softc *sc)
1332 bzero(sc->re_ldata.re_tx_list, RE_TX_LIST_SZ);
1333 bzero(&sc->re_ldata.re_tx_mbuf, RE_TX_DESC_CNT * sizeof(struct mbuf *));
1335 bus_dmamap_sync(sc->re_ldata.re_tx_list_tag,
1336 sc->re_ldata.re_tx_list_map, BUS_DMASYNC_PREWRITE);
1337 sc->re_ldata.re_tx_prodidx = 0;
1338 sc->re_ldata.re_tx_considx = 0;
1339 sc->re_ldata.re_tx_free = RE_TX_DESC_CNT;
1345 re_rx_list_init(struct re_softc *sc)
1349 bzero(sc->re_ldata.re_rx_list, RE_RX_LIST_SZ);
1350 bzero(&sc->re_ldata.re_rx_mbuf, RE_RX_DESC_CNT * sizeof(struct mbuf *));
1352 for (i = 0; i < RE_RX_DESC_CNT; i++) {
1353 error = re_newbuf(sc, i, NULL);
1358 /* Flush the RX descriptors */
1360 bus_dmamap_sync(sc->re_ldata.re_rx_list_tag,
1361 sc->re_ldata.re_rx_list_map,
1362 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD);
1364 sc->re_ldata.re_rx_prodidx = 0;
1365 sc->re_head = sc->re_tail = NULL;
1371 * RX handler for C+ and 8169. For the gigE chips, we support
1372 * the reception of jumbo frames that have been fragmented
1373 * across multiple 2K mbuf cluster buffers.
1376 re_rxeof(struct re_softc *sc)
1378 struct ifnet *ifp = &sc->arpcom.ac_if;
1380 struct re_desc *cur_rx;
1381 uint32_t rxstat, rxvlan;
1384 /* Invalidate the descriptor memory */
1386 bus_dmamap_sync(sc->re_ldata.re_rx_list_tag,
1387 sc->re_ldata.re_rx_list_map, BUS_DMASYNC_POSTREAD);
1389 for (i = sc->re_ldata.re_rx_prodidx;
1390 RE_OWN(&sc->re_ldata.re_rx_list[i]) == 0 ; RE_DESC_INC(i)) {
1391 cur_rx = &sc->re_ldata.re_rx_list[i];
1392 m = sc->re_ldata.re_rx_mbuf[i];
1393 total_len = RE_RXBYTES(cur_rx);
1394 rxstat = le32toh(cur_rx->re_cmdstat);
1395 rxvlan = le32toh(cur_rx->re_vlanctl);
1397 /* Invalidate the RX mbuf and unload its map */
1399 bus_dmamap_sync(sc->re_ldata.re_mtag,
1400 sc->re_ldata.re_rx_dmamap[i],
1401 BUS_DMASYNC_POSTWRITE);
1402 bus_dmamap_unload(sc->re_ldata.re_mtag,
1403 sc->re_ldata.re_rx_dmamap[i]);
1405 if ((rxstat & RE_RDESC_STAT_EOF) == 0) {
1406 m->m_len = MCLBYTES - ETHER_ALIGN;
1407 if (sc->re_head == NULL) {
1408 sc->re_head = sc->re_tail = m;
1410 sc->re_tail->m_next = m;
1413 re_newbuf(sc, i, NULL);
1418 * NOTE: for the 8139C+, the frame length field
1419 * is always 12 bits in size, but for the gigE chips,
1420 * it is 13 bits (since the max RX frame length is 16K).
1421 * Unfortunately, all 32 bits in the status word
1422 * were already used, so to make room for the extra
1423 * length bit, RealTek took out the 'frame alignment
1424 * error' bit and shifted the other status bits
1425 * over one slot. The OWN, EOR, FS and LS bits are
1426 * still in the same places. We have already extracted
1427 * the frame length and checked the OWN bit, so rather
1428 * than using an alternate bit mapping, we shift the
1429 * status bits one space to the right so we can evaluate
1430 * them using the 8169 status as though it was in the
1431 * same format as that of the 8139C+.
1433 if (sc->re_type == RE_8169)
1436 if (rxstat & RE_RDESC_STAT_RXERRSUM) {
1439 * If this is part of a multi-fragment packet,
1440 * discard all the pieces.
1442 if (sc->re_head != NULL) {
1443 m_freem(sc->re_head);
1444 sc->re_head = sc->re_tail = NULL;
1446 re_newbuf(sc, i, m);
1451 * If allocating a replacement mbuf fails,
1452 * reload the current one.
1455 if (re_newbuf(sc, i, NULL)) {
1457 if (sc->re_head != NULL) {
1458 m_freem(sc->re_head);
1459 sc->re_head = sc->re_tail = NULL;
1461 re_newbuf(sc, i, m);
1465 if (sc->re_head != NULL) {
1466 m->m_len = total_len % (MCLBYTES - ETHER_ALIGN);
1468 * Special case: if there's 4 bytes or less
1469 * in this buffer, the mbuf can be discarded:
1470 * the last 4 bytes is the CRC, which we don't
1471 * care about anyway.
1473 if (m->m_len <= ETHER_CRC_LEN) {
1474 sc->re_tail->m_len -=
1475 (ETHER_CRC_LEN - m->m_len);
1478 m->m_len -= ETHER_CRC_LEN;
1479 sc->re_tail->m_next = m;
1482 sc->re_head = sc->re_tail = NULL;
1483 m->m_pkthdr.len = total_len - ETHER_CRC_LEN;
1485 m->m_pkthdr.len = m->m_len =
1486 (total_len - ETHER_CRC_LEN);
1489 m->m_pkthdr.rcvif = ifp;
1491 /* Do RX checksumming if enabled */
1493 if (ifp->if_capenable & IFCAP_RXCSUM) {
1495 /* Check IP header checksum */
1496 if (rxstat & RE_RDESC_STAT_PROTOID)
1497 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
1498 if ((rxstat & RE_RDESC_STAT_IPSUMBAD) == 0)
1499 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
1501 /* Check TCP/UDP checksum */
1502 if ((RE_TCPPKT(rxstat) &&
1503 (rxstat & RE_RDESC_STAT_TCPSUMBAD) == 0) ||
1504 (RE_UDPPKT(rxstat) &&
1505 (rxstat & RE_RDESC_STAT_UDPSUMBAD)) == 0) {
1506 m->m_pkthdr.csum_flags |=
1507 CSUM_DATA_VALID|CSUM_PSEUDO_HDR;
1508 m->m_pkthdr.csum_data = 0xffff;
1512 if (rxvlan & RE_RDESC_VLANCTL_TAG) {
1514 be16toh((rxvlan & RE_RDESC_VLANCTL_DATA)));
1516 ifp->if_input(ifp, m);
1520 /* Flush the RX DMA ring */
1522 bus_dmamap_sync(sc->re_ldata.re_rx_list_tag,
1523 sc->re_ldata.re_rx_list_map,
1524 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD);
1526 sc->re_ldata.re_rx_prodidx = i;
1530 re_txeof(struct re_softc *sc)
1532 struct ifnet *ifp = &sc->arpcom.ac_if;
1536 /* Invalidate the TX descriptor list */
1538 bus_dmamap_sync(sc->re_ldata.re_tx_list_tag,
1539 sc->re_ldata.re_tx_list_map,
1540 BUS_DMASYNC_POSTREAD);
1542 for (idx = sc->re_ldata.re_tx_considx;
1543 idx != sc->re_ldata.re_tx_prodidx; RE_DESC_INC(idx)) {
1544 txstat = le32toh(sc->re_ldata.re_tx_list[idx].re_cmdstat);
1545 if (txstat & RE_TDESC_CMD_OWN)
1549 * We only stash mbufs in the last descriptor
1550 * in a fragment chain, which also happens to
1551 * be the only place where the TX status bits
1554 if (txstat & RE_TDESC_CMD_EOF) {
1555 m_freem(sc->re_ldata.re_tx_mbuf[idx]);
1556 sc->re_ldata.re_tx_mbuf[idx] = NULL;
1557 bus_dmamap_unload(sc->re_ldata.re_mtag,
1558 sc->re_ldata.re_tx_dmamap[idx]);
1559 if (txstat & (RE_TDESC_STAT_EXCESSCOL|
1560 RE_TDESC_STAT_COLCNT))
1561 ifp->if_collisions++;
1562 if (txstat & RE_TDESC_STAT_TXERRSUM)
1567 sc->re_ldata.re_tx_free++;
1570 /* No changes made to the TX ring, so no flush needed */
1571 if (idx != sc->re_ldata.re_tx_considx) {
1572 sc->re_ldata.re_tx_considx = idx;
1573 ifp->if_flags &= ~IFF_OACTIVE;
1578 * If not all descriptors have been released reaped yet,
1579 * reload the timer so that we will eventually get another
1580 * interrupt that will cause us to re-enter this routine.
1581 * This is done in case the transmitter has gone idle.
1583 if (sc->re_ldata.re_tx_free != RE_TX_DESC_CNT)
1584 CSR_WRITE_4(sc, RE_TIMERCNT, 1);
1590 struct re_softc *sc = xsc;
1592 lwkt_serialize_enter(sc->arpcom.ac_if.if_serializer);
1593 re_tick_serialized(xsc);
1594 lwkt_serialize_exit(sc->arpcom.ac_if.if_serializer);
1598 re_tick_serialized(void *xsc)
1600 struct re_softc *sc = xsc;
1601 struct mii_data *mii;
1603 mii = device_get_softc(sc->re_miibus);
1606 callout_reset(&sc->re_timer, hz, re_tick, sc);
1609 #ifdef DEVICE_POLLING
1612 re_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
1614 struct re_softc *sc = ifp->if_softc;
1618 /* disable interrupts */
1619 CSR_WRITE_2(sc, RE_IMR, 0x0000);
1621 case POLL_DEREGISTER:
1622 /* enable interrupts */
1623 CSR_WRITE_2(sc, RE_IMR, RE_INTRS_CPLUS);
1626 sc->rxcycles = count;
1630 if (!ifq_is_empty(&ifp->if_snd))
1631 (*ifp->if_start)(ifp);
1633 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */
1636 status = CSR_READ_2(sc, RE_ISR);
1637 if (status == 0xffff)
1640 CSR_WRITE_2(sc, RE_ISR, status);
1643 * XXX check behaviour on receiver stalls.
1646 if (status & RE_ISR_SYSTEM_ERR) {
1654 #endif /* DEVICE_POLLING */
1659 struct re_softc *sc = arg;
1660 struct ifnet *ifp = &sc->arpcom.ac_if;
1663 if (sc->suspended || (ifp->if_flags & IFF_UP) == 0)
1667 status = CSR_READ_2(sc, RE_ISR);
1668 /* If the card has gone away the read returns 0xffff. */
1669 if (status == 0xffff)
1672 CSR_WRITE_2(sc, RE_ISR, status);
1674 if ((status & RE_INTRS_CPLUS) == 0)
1677 if (status & RE_ISR_RX_OK)
1680 if (status & RE_ISR_RX_ERR)
1683 if ((status & RE_ISR_TIMEOUT_EXPIRED) ||
1684 (status & RE_ISR_TX_ERR) ||
1685 (status & RE_ISR_TX_DESC_UNAVAIL))
1688 if (status & RE_ISR_SYSTEM_ERR) {
1693 if (status & RE_ISR_LINKCHG)
1694 re_tick_serialized(sc);
1697 if (!ifq_is_empty(&ifp->if_snd))
1698 (*ifp->if_start)(ifp);
1702 re_encap(struct re_softc *sc, struct mbuf **m_head, int *idx, int *called_defrag)
1704 struct ifnet *ifp = &sc->arpcom.ac_if;
1705 struct mbuf *m, *m_new = NULL;
1706 struct re_dmaload_arg arg;
1711 if (sc->re_ldata.re_tx_free <= 4)
1717 * Set up checksum offload. Note: checksum offload bits must
1718 * appear in all descriptors of a multi-descriptor transmit
1719 * attempt. (This is according to testing done with an 8169
1720 * chip. I'm not sure if this is a requirement or a bug.)
1725 if (m->m_pkthdr.csum_flags & CSUM_IP)
1726 arg.re_flags |= RE_TDESC_CMD_IPCSUM;
1727 if (m->m_pkthdr.csum_flags & CSUM_TCP)
1728 arg.re_flags |= RE_TDESC_CMD_TCPCSUM;
1729 if (m->m_pkthdr.csum_flags & CSUM_UDP)
1730 arg.re_flags |= RE_TDESC_CMD_UDPCSUM;
1734 arg.re_maxsegs = sc->re_ldata.re_tx_free;
1735 if (arg.re_maxsegs > 4)
1736 arg.re_maxsegs -= 4;
1737 arg.re_ring = sc->re_ldata.re_tx_list;
1739 map = sc->re_ldata.re_tx_dmamap[*idx];
1740 error = bus_dmamap_load_mbuf(sc->re_ldata.re_mtag, map,
1741 m, re_dma_map_desc, &arg, BUS_DMA_NOWAIT);
1743 if (error && error != EFBIG) {
1744 if_printf(ifp, "can't map mbuf (error %d)\n", error);
1748 /* Too many segments to map, coalesce into a single mbuf */
1750 if (error || arg.re_maxsegs == 0) {
1751 m_new = m_defrag_nofree(m, MB_DONTWAIT);
1762 arg.re_maxsegs = sc->re_ldata.re_tx_free;
1763 arg.re_ring = sc->re_ldata.re_tx_list;
1765 error = bus_dmamap_load_mbuf(sc->re_ldata.re_mtag, map,
1766 m, re_dma_map_desc, &arg, BUS_DMA_NOWAIT);
1769 if_printf(ifp, "can't map mbuf (error %d)\n", error);
1775 * Insure that the map for this transmission
1776 * is placed at the array index of the last descriptor
1779 sc->re_ldata.re_tx_dmamap[*idx] =
1780 sc->re_ldata.re_tx_dmamap[arg.re_idx];
1781 sc->re_ldata.re_tx_dmamap[arg.re_idx] = map;
1783 sc->re_ldata.re_tx_mbuf[arg.re_idx] = m;
1784 sc->re_ldata.re_tx_free -= arg.re_maxsegs;
1787 * Set up hardware VLAN tagging. Note: vlan tag info must
1788 * appear in the first descriptor of a multi-descriptor
1789 * transmission attempt.
1792 if ((m->m_flags & (M_PROTO1|M_PKTHDR)) == (M_PROTO1|M_PKTHDR) &&
1793 m->m_pkthdr.rcvif != NULL &&
1794 m->m_pkthdr.rcvif->if_type == IFT_L2VLAN) {
1796 ifv = m->m_pkthdr.rcvif->if_softc;
1798 sc->re_ldata.re_tx_list[*idx].re_vlanctl =
1799 htole32(htobe16(ifv->ifv_tag) | RE_TDESC_VLANCTL_TAG);
1802 /* Transfer ownership of packet to the chip. */
1804 sc->re_ldata.re_tx_list[arg.re_idx].re_cmdstat |=
1805 htole32(RE_TDESC_CMD_OWN);
1806 if (*idx != arg.re_idx)
1807 sc->re_ldata.re_tx_list[*idx].re_cmdstat |=
1808 htole32(RE_TDESC_CMD_OWN);
1810 RE_DESC_INC(arg.re_idx);
1817 * Main transmit routine for C+ and gigE NICs.
1821 re_start(struct ifnet *ifp)
1823 struct re_softc *sc = ifp->if_softc;
1824 struct mbuf *m_head;
1825 struct mbuf *m_head2;
1826 int called_defrag, idx, need_trans;
1828 idx = sc->re_ldata.re_tx_prodidx;
1831 while (sc->re_ldata.re_tx_mbuf[idx] == NULL) {
1832 m_head = ifq_poll(&ifp->if_snd);
1836 if (re_encap(sc, &m_head2, &idx, &called_defrag)) {
1838 * If we could not encapsulate the defragged packet,
1839 * the returned m_head2 is garbage and we must dequeue
1840 * and throw away the original packet.
1842 if (called_defrag) {
1843 ifq_dequeue(&ifp->if_snd, m_head);
1846 ifp->if_flags |= IFF_OACTIVE;
1851 * Clean out the packet we encapsulated. If we defragged
1852 * the packet the m_head2 is the one that got encapsulated
1853 * and the original must be thrown away. Otherwise m_head2
1854 * *IS* the original.
1856 ifq_dequeue(&ifp->if_snd, m_head);
1862 * If there's a BPF listener, bounce a copy of this frame
1865 BPF_MTAP(ifp, m_head2);
1872 /* Flush the TX descriptors */
1873 bus_dmamap_sync(sc->re_ldata.re_tx_list_tag,
1874 sc->re_ldata.re_tx_list_map,
1875 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD);
1877 sc->re_ldata.re_tx_prodidx = idx;
1880 * RealTek put the TX poll request register in a different
1881 * location on the 8169 gigE chip. I don't know why.
1883 if (sc->re_type == RE_8169)
1884 CSR_WRITE_2(sc, RE_GTXSTART, RE_TXSTART_START);
1886 CSR_WRITE_2(sc, RE_TXSTART, RE_TXSTART_START);
1889 * Use the countdown timer for interrupt moderation.
1890 * 'TX done' interrupts are disabled. Instead, we reset the
1891 * countdown timer, which will begin counting until it hits
1892 * the value in the TIMERINT register, and then trigger an
1893 * interrupt. Each time we write to the TIMERCNT register,
1894 * the timer count is reset to 0.
1896 CSR_WRITE_4(sc, RE_TIMERCNT, 1);
1899 * Set a timeout in case the chip goes out to lunch.
1907 struct re_softc *sc = xsc;
1908 struct ifnet *ifp = &sc->arpcom.ac_if;
1909 struct mii_data *mii;
1912 mii = device_get_softc(sc->re_miibus);
1915 * Cancel pending I/O and free all RX/TX buffers.
1920 * Enable C+ RX and TX mode, as well as VLAN stripping and
1921 * RX checksum offload. We must configure the C+ register
1922 * before all others.
1924 CSR_WRITE_2(sc, RE_CPLUS_CMD, RE_CPLUSCMD_RXENB | RE_CPLUSCMD_TXENB |
1925 RE_CPLUSCMD_PCI_MRW | RE_CPLUSCMD_VLANSTRIP |
1926 (ifp->if_capenable & IFCAP_RXCSUM ?
1927 RE_CPLUSCMD_RXCSUM_ENB : 0));
1930 * Init our MAC address. Even though the chipset
1931 * documentation doesn't mention it, we need to enter "Config
1932 * register write enable" mode to modify the ID registers.
1934 CSR_WRITE_1(sc, RE_EECMD, RE_EEMODE_WRITECFG);
1935 CSR_WRITE_STREAM_4(sc, RE_IDR0,
1936 *(u_int32_t *)(&sc->arpcom.ac_enaddr[0]));
1937 CSR_WRITE_STREAM_4(sc, RE_IDR4,
1938 *(u_int32_t *)(&sc->arpcom.ac_enaddr[4]));
1939 CSR_WRITE_1(sc, RE_EECMD, RE_EEMODE_OFF);
1942 * For C+ mode, initialize the RX descriptors and mbufs.
1944 re_rx_list_init(sc);
1945 re_tx_list_init(sc);
1948 * Enable transmit and receive.
1950 CSR_WRITE_1(sc, RE_COMMAND, RE_CMD_TX_ENB|RE_CMD_RX_ENB);
1953 * Set the initial TX and RX configuration.
1955 if (sc->re_testmode) {
1956 if (sc->re_type == RE_8169)
1957 CSR_WRITE_4(sc, RE_TXCFG,
1958 RE_TXCFG_CONFIG | RE_LOOPTEST_ON);
1960 CSR_WRITE_4(sc, RE_TXCFG,
1961 RE_TXCFG_CONFIG | RE_LOOPTEST_ON_CPLUS);
1963 CSR_WRITE_4(sc, RE_TXCFG, RE_TXCFG_CONFIG);
1964 CSR_WRITE_4(sc, RE_RXCFG, RE_RXCFG_CONFIG);
1966 /* Set the individual bit to receive frames for this host only. */
1967 rxcfg = CSR_READ_4(sc, RE_RXCFG);
1968 rxcfg |= RE_RXCFG_RX_INDIV;
1970 /* If we want promiscuous mode, set the allframes bit. */
1971 if (ifp->if_flags & IFF_PROMISC) {
1972 rxcfg |= RE_RXCFG_RX_ALLPHYS;
1973 CSR_WRITE_4(sc, RE_RXCFG, rxcfg);
1975 rxcfg &= ~RE_RXCFG_RX_ALLPHYS;
1976 CSR_WRITE_4(sc, RE_RXCFG, rxcfg);
1980 * Set capture broadcast bit to capture broadcast frames.
1982 if (ifp->if_flags & IFF_BROADCAST) {
1983 rxcfg |= RE_RXCFG_RX_BROAD;
1984 CSR_WRITE_4(sc, RE_RXCFG, rxcfg);
1986 rxcfg &= ~RE_RXCFG_RX_BROAD;
1987 CSR_WRITE_4(sc, RE_RXCFG, rxcfg);
1991 * Program the multicast filter, if necessary.
1995 #ifdef DEVICE_POLLING
1997 * Disable interrupts if we are polling.
1999 if (ifp->if_flags & IFF_POLLING)
2000 CSR_WRITE_2(sc, RE_IMR, 0);
2001 else /* otherwise ... */
2002 #endif /* DEVICE_POLLING */
2004 * Enable interrupts.
2006 if (sc->re_testmode)
2007 CSR_WRITE_2(sc, RE_IMR, 0);
2009 CSR_WRITE_2(sc, RE_IMR, RE_INTRS_CPLUS);
2011 /* Set initial TX threshold */
2012 sc->re_txthresh = RE_TX_THRESH_INIT;
2014 /* Start RX/TX process. */
2015 CSR_WRITE_4(sc, RE_MISSEDPKT, 0);
2017 /* Enable receiver and transmitter. */
2018 CSR_WRITE_1(sc, RE_COMMAND, RE_CMD_TX_ENB|RE_CMD_RX_ENB);
2021 * Load the addresses of the RX and TX lists into the chip.
2024 CSR_WRITE_4(sc, RE_RXLIST_ADDR_HI,
2025 RE_ADDR_HI(sc->re_ldata.re_rx_list_addr));
2026 CSR_WRITE_4(sc, RE_RXLIST_ADDR_LO,
2027 RE_ADDR_LO(sc->re_ldata.re_rx_list_addr));
2029 CSR_WRITE_4(sc, RE_TXLIST_ADDR_HI,
2030 RE_ADDR_HI(sc->re_ldata.re_tx_list_addr));
2031 CSR_WRITE_4(sc, RE_TXLIST_ADDR_LO,
2032 RE_ADDR_LO(sc->re_ldata.re_tx_list_addr));
2034 CSR_WRITE_1(sc, RE_EARLY_TX_THRESH, 16);
2037 * Initialize the timer interrupt register so that
2038 * a timer interrupt will be generated once the timer
2039 * reaches a certain number of ticks. The timer is
2040 * reloaded on each transmit. This gives us TX interrupt
2041 * moderation, which dramatically improves TX frame rate.
2044 if (sc->re_type == RE_8169)
2045 CSR_WRITE_4(sc, RE_TIMERINT_8169, 0x800);
2047 CSR_WRITE_4(sc, RE_TIMERINT, 0x400);
2050 * For 8169 gigE NICs, set the max allowed RX packet
2051 * size so we can receive jumbo frames.
2053 if (sc->re_type == RE_8169)
2054 CSR_WRITE_2(sc, RE_MAXRXPKTLEN, 16383);
2056 if (sc->re_testmode) {
2062 CSR_WRITE_1(sc, RE_CFG1, RE_CFG1_DRVLOAD|RE_CFG1_FULLDUPLEX);
2064 ifp->if_flags |= IFF_RUNNING;
2065 ifp->if_flags &= ~IFF_OACTIVE;
2067 callout_reset(&sc->re_timer, hz, re_tick, sc);
2071 * Set media options.
2074 re_ifmedia_upd(struct ifnet *ifp)
2076 struct re_softc *sc = ifp->if_softc;
2077 struct mii_data *mii;
2079 mii = device_get_softc(sc->re_miibus);
2086 * Report current media status.
2089 re_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
2091 struct re_softc *sc = ifp->if_softc;
2092 struct mii_data *mii;
2094 mii = device_get_softc(sc->re_miibus);
2097 ifmr->ifm_active = mii->mii_media_active;
2098 ifmr->ifm_status = mii->mii_media_status;
2102 re_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
2104 struct re_softc *sc = ifp->if_softc;
2105 struct ifreq *ifr = (struct ifreq *) data;
2106 struct mii_data *mii;
2111 if (ifr->ifr_mtu > RE_JUMBO_MTU)
2113 ifp->if_mtu = ifr->ifr_mtu;
2116 if (ifp->if_flags & IFF_UP)
2118 else if (ifp->if_flags & IFF_RUNNING)
2129 mii = device_get_softc(sc->re_miibus);
2130 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
2133 ifp->if_capenable &= ~(IFCAP_HWCSUM);
2134 ifp->if_capenable |=
2135 ifr->ifr_reqcap & (IFCAP_HWCSUM);
2136 if (ifp->if_capenable & IFCAP_TXCSUM)
2137 ifp->if_hwassist = RE_CSUM_FEATURES;
2139 ifp->if_hwassist = 0;
2140 if (ifp->if_flags & IFF_RUNNING)
2144 error = ether_ioctl(ifp, command, data);
2151 re_watchdog(struct ifnet *ifp)
2153 struct re_softc *sc = ifp->if_softc;
2155 if_printf(ifp, "watchdog timeout\n");
2164 if (!ifq_is_empty(&ifp->if_snd))
2169 * Stop the adapter and free any mbufs allocated to the
2173 re_stop(struct re_softc *sc)
2175 struct ifnet *ifp = &sc->arpcom.ac_if;
2179 callout_stop(&sc->re_timer);
2181 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
2183 CSR_WRITE_1(sc, RE_COMMAND, 0x00);
2184 CSR_WRITE_2(sc, RE_IMR, 0x0000);
2186 if (sc->re_head != NULL) {
2187 m_freem(sc->re_head);
2188 sc->re_head = sc->re_tail = NULL;
2191 /* Free the TX list buffers. */
2192 for (i = 0; i < RE_TX_DESC_CNT; i++) {
2193 if (sc->re_ldata.re_tx_mbuf[i] != NULL) {
2194 bus_dmamap_unload(sc->re_ldata.re_mtag,
2195 sc->re_ldata.re_tx_dmamap[i]);
2196 m_freem(sc->re_ldata.re_tx_mbuf[i]);
2197 sc->re_ldata.re_tx_mbuf[i] = NULL;
2201 /* Free the RX list buffers. */
2202 for (i = 0; i < RE_RX_DESC_CNT; i++) {
2203 if (sc->re_ldata.re_rx_mbuf[i] != NULL) {
2204 bus_dmamap_unload(sc->re_ldata.re_mtag,
2205 sc->re_ldata.re_rx_dmamap[i]);
2206 m_freem(sc->re_ldata.re_rx_mbuf[i]);
2207 sc->re_ldata.re_rx_mbuf[i] = NULL;
2213 * Device suspend routine. Stop the interface and save some PCI
2214 * settings in case the BIOS doesn't restore them properly on
2218 re_suspend(device_t dev)
2220 #ifndef BURN_BRIDGES
2223 struct re_softc *sc = device_get_softc(dev);
2227 #ifndef BURN_BRIDGES
2228 for (i = 0; i < 5; i++)
2229 sc->saved_maps[i] = pci_read_config(dev, PCIR_MAPS + i * 4, 4);
2230 sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4);
2231 sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1);
2232 sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1);
2233 sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1);
2242 * Device resume routine. Restore some PCI settings in case the BIOS
2243 * doesn't, re-enable busmastering, and restart the interface if
2247 re_resume(device_t dev)
2249 struct re_softc *sc = device_get_softc(dev);
2250 struct ifnet *ifp = &sc->arpcom.ac_if;
2251 #ifndef BURN_BRIDGES
2255 #ifndef BURN_BRIDGES
2256 /* better way to do this? */
2257 for (i = 0; i < 5; i++)
2258 pci_write_config(dev, PCIR_MAPS + i * 4, sc->saved_maps[i], 4);
2259 pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4);
2260 pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1);
2261 pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1);
2262 pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1);
2264 /* reenable busmastering */
2265 pci_enable_busmaster(dev);
2266 pci_enable_io(dev, SYS_RES_IOPORT);
2269 /* reinitialize interface if necessary */
2270 if (ifp->if_flags & IFF_UP)
2279 * Stop all chip I/O so that the kernel's probe routines don't
2280 * get confused by errant DMAs when rebooting.
2283 re_shutdown(device_t dev)
2285 struct re_softc *sc = device_get_softc(dev);