2 * Copyright (c) 1997, 1998, 1999
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
32 * $FreeBSD: src/sys/pci/if_sis.c,v 1.13.4.24 2003/03/05 18:42:33 njl Exp $
33 * $DragonFly: src/sys/dev/netif/sis/if_sis.c,v 1.35 2006/09/05 00:55:41 dillon Exp $
37 * SiS 900/SiS 7016 fast ethernet PCI NIC driver. Datasheets are
38 * available from http://www.sis.com.tw.
40 * This driver also supports the NatSemi DP83815. Datasheets are
41 * available from http://www.national.com.
43 * Written by Bill Paul <wpaul@ee.columbia.edu>
44 * Electrical Engineering Department
45 * Columbia University, New York City
49 * The SiS 900 is a fairly simple chip. It uses bus master DMA with
50 * simple TX and RX descriptors of 3 longwords in size. The receiver
51 * has a single perfect filter entry for the station address and a
52 * 128-bit multicast hash table. The SiS 900 has a built-in MII-based
53 * transceiver while the 7016 requires an external transceiver chip.
54 * Both chips offer the standard bit-bang MII interface as well as
55 * an enchanced PHY interface which simplifies accessing MII registers.
57 * The only downside to this chipset is that RX descriptors must be
61 #include "opt_polling.h"
63 #include <sys/param.h>
64 #include <sys/systm.h>
65 #include <sys/sockio.h>
67 #include <sys/malloc.h>
68 #include <sys/kernel.h>
69 #include <sys/socket.h>
70 #include <sys/sysctl.h>
71 #include <sys/serialize.h>
72 #include <sys/thread2.h>
75 #include <net/ifq_var.h>
76 #include <net/if_arp.h>
77 #include <net/ethernet.h>
78 #include <net/if_dl.h>
79 #include <net/if_media.h>
80 #include <net/if_types.h>
81 #include <net/vlan/if_vlan_var.h>
85 #include <machine/bus_pio.h>
86 #include <machine/bus_memio.h>
87 #include <machine/bus.h>
88 #include <machine/resource.h>
92 #include <dev/netif/mii_layer/mii.h>
93 #include <dev/netif/mii_layer/miivar.h>
95 #include <bus/pci/pcidevs.h>
96 #include <bus/pci/pcireg.h>
97 #include <bus/pci/pcivar.h>
99 #define SIS_USEIOSPACE
101 #include "if_sisreg.h"
103 /* "controller miibus0" required. See GENERIC if you get errors here. */
104 #include "miibus_if.h"
107 * Various supported device vendors/types and their names.
109 static struct sis_type sis_devs[] = {
110 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_900, "SiS 900 10/100BaseTX" },
111 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_7016, "SiS 7016 10/100BaseTX" },
112 { PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815, "NatSemi DP8381[56] 10/100BaseTX" },
116 static int sis_probe(device_t);
117 static int sis_attach(device_t);
118 static int sis_detach(device_t);
120 static int sis_newbuf(struct sis_softc *, struct sis_desc *,
122 static int sis_encap(struct sis_softc *, struct mbuf *, uint32_t *);
123 static void sis_rxeof(struct sis_softc *);
124 static void sis_rxeoc(struct sis_softc *);
125 static void sis_txeof(struct sis_softc *);
126 static void sis_intr(void *);
127 static void sis_tick(void *);
128 static void sis_start(struct ifnet *);
129 static int sis_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
130 static void sis_init(void *);
131 static void sis_stop(struct sis_softc *);
132 static void sis_watchdog(struct ifnet *);
133 static void sis_shutdown(device_t);
134 static int sis_ifmedia_upd(struct ifnet *);
135 static void sis_ifmedia_sts(struct ifnet *, struct ifmediareq *);
137 static uint16_t sis_reverse(uint16_t);
138 static void sis_delay(struct sis_softc *);
139 static void sis_eeprom_idle(struct sis_softc *);
140 static void sis_eeprom_putbyte(struct sis_softc *, int);
141 static void sis_eeprom_getword(struct sis_softc *, int, uint16_t *);
142 static void sis_read_eeprom(struct sis_softc *, caddr_t, int, int, int);
144 static void sis_read_cmos(struct sis_softc *, device_t, caddr_t, int, int);
145 static void sis_read_mac(struct sis_softc *, device_t, caddr_t);
146 static device_t sis_find_bridge(device_t);
149 static void sis_mii_sync(struct sis_softc *);
150 static void sis_mii_send(struct sis_softc *, uint32_t, int);
151 static int sis_mii_readreg(struct sis_softc *, struct sis_mii_frame *);
152 static int sis_mii_writereg(struct sis_softc *, struct sis_mii_frame *);
153 static int sis_miibus_readreg(device_t, int, int);
154 static int sis_miibus_writereg(device_t, int, int, int);
155 static void sis_miibus_statchg(device_t);
157 static void sis_setmulti_sis(struct sis_softc *);
158 static void sis_setmulti_ns(struct sis_softc *);
159 static uint32_t sis_mchash(struct sis_softc *, const uint8_t *);
160 static void sis_reset(struct sis_softc *);
161 static int sis_list_rx_init(struct sis_softc *);
162 static int sis_list_tx_init(struct sis_softc *);
164 static void sis_dma_map_desc_ptr(void *, bus_dma_segment_t *, int, int);
165 static void sis_dma_map_desc_next(void *, bus_dma_segment_t *, int, int);
166 static void sis_dma_map_ring(void *, bus_dma_segment_t *, int, int);
167 #ifdef DEVICE_POLLING
168 static poll_handler_t sis_poll;
170 #ifdef SIS_USEIOSPACE
171 #define SIS_RES SYS_RES_IOPORT
172 #define SIS_RID SIS_PCI_LOIO
174 #define SIS_RES SYS_RES_MEMORY
175 #define SIS_RID SIS_PCI_LOMEM
178 static device_method_t sis_methods[] = {
179 /* Device interface */
180 DEVMETHOD(device_probe, sis_probe),
181 DEVMETHOD(device_attach, sis_attach),
182 DEVMETHOD(device_detach, sis_detach),
183 DEVMETHOD(device_shutdown, sis_shutdown),
186 DEVMETHOD(bus_print_child, bus_generic_print_child),
187 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
190 DEVMETHOD(miibus_readreg, sis_miibus_readreg),
191 DEVMETHOD(miibus_writereg, sis_miibus_writereg),
192 DEVMETHOD(miibus_statchg, sis_miibus_statchg),
197 static driver_t sis_driver = {
200 sizeof(struct sis_softc)
203 static devclass_t sis_devclass;
205 DECLARE_DUMMY_MODULE(if_sis);
206 DRIVER_MODULE(if_sis, pci, sis_driver, sis_devclass, 0, 0);
207 DRIVER_MODULE(miibus, sis, miibus_driver, miibus_devclass, 0, 0);
209 #define SIS_SETBIT(sc, reg, x) \
210 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x))
212 #define SIS_CLRBIT(sc, reg, x) \
213 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x))
216 CSR_WRITE_4(sc, SIS_EECTL, CSR_READ_4(sc, SIS_EECTL) | x)
219 CSR_WRITE_4(sc, SIS_EECTL, CSR_READ_4(sc, SIS_EECTL) & ~x)
222 sis_dma_map_desc_next(void *arg, bus_dma_segment_t *segs, int nseg, int error)
227 r->sis_next = segs->ds_addr;
231 sis_dma_map_desc_ptr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
236 r->sis_ptr = segs->ds_addr;
240 sis_dma_map_ring(void *arg, bus_dma_segment_t *segs, int nseg, int error)
249 * Routine to reverse the bits in a word. Stolen almost
250 * verbatim from /usr/games/fortune.
253 sis_reverse(uint16_t n)
255 n = ((n >> 1) & 0x5555) | ((n << 1) & 0xaaaa);
256 n = ((n >> 2) & 0x3333) | ((n << 2) & 0xcccc);
257 n = ((n >> 4) & 0x0f0f) | ((n << 4) & 0xf0f0);
258 n = ((n >> 8) & 0x00ff) | ((n << 8) & 0xff00);
264 sis_delay(struct sis_softc *sc)
268 for (idx = (300 / 33) + 1; idx > 0; idx--)
269 CSR_READ_4(sc, SIS_CSR);
273 sis_eeprom_idle(struct sis_softc *sc)
277 SIO_SET(SIS_EECTL_CSEL);
279 SIO_SET(SIS_EECTL_CLK);
282 for (i = 0; i < 25; i++) {
283 SIO_CLR(SIS_EECTL_CLK);
285 SIO_SET(SIS_EECTL_CLK);
289 SIO_CLR(SIS_EECTL_CLK);
291 SIO_CLR(SIS_EECTL_CSEL);
293 CSR_WRITE_4(sc, SIS_EECTL, 0x00000000);
297 * Send a read command and address to the EEPROM, check for ACK.
300 sis_eeprom_putbyte(struct sis_softc *sc, int addr)
304 d = addr | SIS_EECMD_READ;
307 * Feed in each bit and stobe the clock.
309 for (i = 0x400; i; i >>= 1) {
311 SIO_SET(SIS_EECTL_DIN);
313 SIO_CLR(SIS_EECTL_DIN);
315 SIO_SET(SIS_EECTL_CLK);
317 SIO_CLR(SIS_EECTL_CLK);
323 * Read a word of data stored in the EEPROM at address 'addr.'
326 sis_eeprom_getword(struct sis_softc *sc, int addr, uint16_t *dest)
331 /* Force EEPROM to idle state. */
334 /* Enter EEPROM access mode. */
336 SIO_CLR(SIS_EECTL_CLK);
338 SIO_SET(SIS_EECTL_CSEL);
342 * Send address of word we want to read.
344 sis_eeprom_putbyte(sc, addr);
347 * Start reading bits from EEPROM.
349 for (i = 0x8000; i; i >>= 1) {
350 SIO_SET(SIS_EECTL_CLK);
352 if (CSR_READ_4(sc, SIS_EECTL) & SIS_EECTL_DOUT)
355 SIO_CLR(SIS_EECTL_CLK);
359 /* Turn off EEPROM access mode. */
366 * Read a sequence of words from the EEPROM.
369 sis_read_eeprom(struct sis_softc *sc, caddr_t dest, int off, int cnt, int swap)
372 uint16_t word = 0, *ptr;
374 for (i = 0; i < cnt; i++) {
375 sis_eeprom_getword(sc, off + i, &word);
376 ptr = (uint16_t *)(dest + (i * 2));
386 sis_find_bridge(device_t dev)
388 devclass_t pci_devclass;
389 device_t *pci_devices;
391 device_t *pci_children;
392 int pci_childcount = 0;
393 device_t *busp, *childp;
394 device_t child = NULL;
397 if ((pci_devclass = devclass_find("pci")) == NULL)
400 devclass_get_devices(pci_devclass, &pci_devices, &pci_count);
402 for (i = 0, busp = pci_devices; i < pci_count; i++, busp++) {
404 device_get_children(*busp, &pci_children, &pci_childcount);
405 for (j = 0, childp = pci_children; j < pci_childcount;
407 if (pci_get_vendor(*childp) == PCI_VENDOR_SIS &&
408 pci_get_device(*childp) == 0x0008) {
416 kfree(pci_devices, M_TEMP);
417 kfree(pci_children, M_TEMP);
422 sis_read_cmos(struct sis_softc *sc, device_t dev, caddr_t dest, int off,
428 bus_space_tag_t btag;
430 bridge = sis_find_bridge(dev);
433 reg = pci_read_config(bridge, 0x48, 1);
434 pci_write_config(bridge, 0x48, reg|0x40, 1);
437 btag = I386_BUS_SPACE_IO;
439 for (i = 0; i < cnt; i++) {
440 bus_space_write_1(btag, 0x0, 0x70, i + off);
441 *(dest + i) = bus_space_read_1(btag, 0x0, 0x71);
444 pci_write_config(bridge, 0x48, reg & ~0x40, 1);
448 sis_read_mac(struct sis_softc *sc, device_t dev, caddr_t dest)
450 uint32_t filtsave, csrsave;
452 filtsave = CSR_READ_4(sc, SIS_RXFILT_CTL);
453 csrsave = CSR_READ_4(sc, SIS_CSR);
455 CSR_WRITE_4(sc, SIS_CSR, SIS_CSR_RELOAD | filtsave);
456 CSR_WRITE_4(sc, SIS_CSR, 0);
458 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave & ~SIS_RXFILTCTL_ENABLE);
460 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR0);
461 ((uint16_t *)dest)[0] = CSR_READ_2(sc, SIS_RXFILT_DATA);
462 CSR_WRITE_4(sc, SIS_RXFILT_CTL,SIS_FILTADDR_PAR1);
463 ((uint16_t *)dest)[1] = CSR_READ_2(sc, SIS_RXFILT_DATA);
464 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR2);
465 ((uint16_t *)dest)[2] = CSR_READ_2(sc, SIS_RXFILT_DATA);
467 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave);
468 CSR_WRITE_4(sc, SIS_CSR, csrsave);
473 * Sync the PHYs by setting data bit and strobing the clock 32 times.
476 sis_mii_sync(struct sis_softc *sc)
480 SIO_SET(SIS_MII_DIR|SIS_MII_DATA);
482 for (i = 0; i < 32; i++) {
483 SIO_SET(SIS_MII_CLK);
485 SIO_CLR(SIS_MII_CLK);
491 * Clock a series of bits through the MII.
494 sis_mii_send(struct sis_softc *sc, uint32_t bits, int cnt)
498 SIO_CLR(SIS_MII_CLK);
500 for (i = (0x1 << (cnt - 1)); i; i >>= 1) {
502 SIO_SET(SIS_MII_DATA);
504 SIO_CLR(SIS_MII_DATA);
506 SIO_CLR(SIS_MII_CLK);
508 SIO_SET(SIS_MII_CLK);
513 * Read an PHY register through the MII.
516 sis_mii_readreg(struct sis_softc *sc, struct sis_mii_frame *frame)
521 * Set up frame for RX.
523 frame->mii_stdelim = SIS_MII_STARTDELIM;
524 frame->mii_opcode = SIS_MII_READOP;
525 frame->mii_turnaround = 0;
531 SIO_SET(SIS_MII_DIR);
536 * Send command/address info.
538 sis_mii_send(sc, frame->mii_stdelim, 2);
539 sis_mii_send(sc, frame->mii_opcode, 2);
540 sis_mii_send(sc, frame->mii_phyaddr, 5);
541 sis_mii_send(sc, frame->mii_regaddr, 5);
544 SIO_CLR((SIS_MII_CLK|SIS_MII_DATA));
546 SIO_SET(SIS_MII_CLK);
550 SIO_CLR(SIS_MII_DIR);
553 SIO_CLR(SIS_MII_CLK);
555 ack = CSR_READ_4(sc, SIS_EECTL) & SIS_MII_DATA;
556 SIO_SET(SIS_MII_CLK);
560 * Now try reading data bits. If the ack failed, we still
561 * need to clock through 16 cycles to keep the PHY(s) in sync.
564 for(i = 0; i < 16; i++) {
565 SIO_CLR(SIS_MII_CLK);
567 SIO_SET(SIS_MII_CLK);
573 for (i = 0x8000; i; i >>= 1) {
574 SIO_CLR(SIS_MII_CLK);
577 if (CSR_READ_4(sc, SIS_EECTL) & SIS_MII_DATA)
578 frame->mii_data |= i;
581 SIO_SET(SIS_MII_CLK);
587 SIO_CLR(SIS_MII_CLK);
589 SIO_SET(SIS_MII_CLK);
598 * Write to a PHY register through the MII.
601 sis_mii_writereg(struct sis_softc *sc, struct sis_mii_frame *frame)
604 * Set up frame for TX.
607 frame->mii_stdelim = SIS_MII_STARTDELIM;
608 frame->mii_opcode = SIS_MII_WRITEOP;
609 frame->mii_turnaround = SIS_MII_TURNAROUND;
612 * Turn on data output.
614 SIO_SET(SIS_MII_DIR);
618 sis_mii_send(sc, frame->mii_stdelim, 2);
619 sis_mii_send(sc, frame->mii_opcode, 2);
620 sis_mii_send(sc, frame->mii_phyaddr, 5);
621 sis_mii_send(sc, frame->mii_regaddr, 5);
622 sis_mii_send(sc, frame->mii_turnaround, 2);
623 sis_mii_send(sc, frame->mii_data, 16);
626 SIO_SET(SIS_MII_CLK);
628 SIO_CLR(SIS_MII_CLK);
634 SIO_CLR(SIS_MII_DIR);
640 sis_miibus_readreg(device_t dev, int phy, int reg)
642 struct sis_softc *sc;
643 struct sis_mii_frame frame;
645 sc = device_get_softc(dev);
647 if (sc->sis_type == SIS_TYPE_83815) {
651 * The NatSemi chip can take a while after
652 * a reset to come ready, during which the BMSR
653 * returns a value of 0. This is *never* supposed
654 * to happen: some of the BMSR bits are meant to
655 * be hardwired in the on position, and this can
656 * confuse the miibus code a bit during the probe
657 * and attach phase. So we make an effort to check
658 * for this condition and wait for it to clear.
660 if (!CSR_READ_4(sc, NS_BMSR))
662 return CSR_READ_4(sc, NS_BMCR + (reg * 4));
665 * Chipsets < SIS_635 seem not to be able to read/write
666 * through mdio. Use the enhanced PHY access register
669 if (sc->sis_type == SIS_TYPE_900 &&
670 sc->sis_rev < SIS_REV_635) {
676 CSR_WRITE_4(sc, SIS_PHYCTL,
677 (phy << 11) | (reg << 6) | SIS_PHYOP_READ);
678 SIS_SETBIT(sc, SIS_PHYCTL, SIS_PHYCTL_ACCESS);
680 for (i = 0; i < SIS_TIMEOUT; i++) {
681 if (!(CSR_READ_4(sc, SIS_PHYCTL) & SIS_PHYCTL_ACCESS))
685 if (i == SIS_TIMEOUT) {
686 device_printf(dev, "PHY failed to come ready\n");
690 val = (CSR_READ_4(sc, SIS_PHYCTL) >> 16) & 0xFFFF;
697 bzero((char *)&frame, sizeof(frame));
699 frame.mii_phyaddr = phy;
700 frame.mii_regaddr = reg;
701 sis_mii_readreg(sc, &frame);
703 return(frame.mii_data);
708 sis_miibus_writereg(device_t dev, int phy, int reg, int data)
710 struct sis_softc *sc;
711 struct sis_mii_frame frame;
713 sc = device_get_softc(dev);
715 if (sc->sis_type == SIS_TYPE_83815) {
718 CSR_WRITE_4(sc, NS_BMCR + (reg * 4), data);
722 if (sc->sis_type == SIS_TYPE_900 &&
723 sc->sis_rev < SIS_REV_635) {
729 CSR_WRITE_4(sc, SIS_PHYCTL, (data << 16) | (phy << 11) |
730 (reg << 6) | SIS_PHYOP_WRITE);
731 SIS_SETBIT(sc, SIS_PHYCTL, SIS_PHYCTL_ACCESS);
733 for (i = 0; i < SIS_TIMEOUT; i++) {
734 if (!(CSR_READ_4(sc, SIS_PHYCTL) & SIS_PHYCTL_ACCESS))
738 if (i == SIS_TIMEOUT)
739 device_printf(dev, "PHY failed to come ready\n");
741 bzero((char *)&frame, sizeof(frame));
743 frame.mii_phyaddr = phy;
744 frame.mii_regaddr = reg;
745 frame.mii_data = data;
746 sis_mii_writereg(sc, &frame);
752 sis_miibus_statchg(device_t dev)
754 struct sis_softc *sc;
756 sc = device_get_softc(dev);
761 sis_mchash(struct sis_softc *sc, const uint8_t *addr)
767 /* Compute CRC for the address value. */
768 crc = 0xFFFFFFFF; /* initial value */
770 for (i = 0; i < 6; i++) {
772 for (j = 0; j < 8; j++) {
773 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01);
777 crc = (crc ^ 0x04c11db6) | carry;
782 * return the filter bit position
784 * The NatSemi chip has a 512-bit filter, which is
785 * different than the SiS, so we special-case it.
787 if (sc->sis_type == SIS_TYPE_83815)
789 else if (sc->sis_rev >= SIS_REV_635 || sc->sis_rev == SIS_REV_900B)
796 sis_setmulti_ns(struct sis_softc *sc)
799 struct ifmultiaddr *ifma;
800 uint32_t h = 0, i, filtsave;
803 ifp = &sc->arpcom.ac_if;
805 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
806 SIS_CLRBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_MCHASH);
807 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLMULTI);
812 * We have to explicitly enable the multicast hash table
813 * on the NatSemi chip if we want to use it, which we do.
815 SIS_SETBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_MCHASH);
816 SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLMULTI);
818 filtsave = CSR_READ_4(sc, SIS_RXFILT_CTL);
820 /* first, zot all the existing hash bits */
821 for (i = 0; i < 32; i++) {
822 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_FMEM_LO + (i*2));
823 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 0);
826 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
827 if (ifma->ifma_addr->sa_family != AF_LINK)
830 LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
833 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_FMEM_LO + index);
836 SIS_SETBIT(sc, SIS_RXFILT_DATA, (1 << bit));
839 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave);
843 sis_setmulti_sis(struct sis_softc *sc)
846 struct ifmultiaddr *ifma;
847 uint32_t h, i, n, ctl;
850 ifp = &sc->arpcom.ac_if;
852 /* hash table size */
853 if (sc->sis_rev >= SIS_REV_635 || sc->sis_rev == SIS_REV_900B)
858 ctl = CSR_READ_4(sc, SIS_RXFILT_CTL) & SIS_RXFILTCTL_ENABLE;
860 if (ifp->if_flags & IFF_BROADCAST)
861 ctl |= SIS_RXFILTCTL_BROAD;
863 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
864 ctl |= SIS_RXFILTCTL_ALLMULTI;
865 if (ifp->if_flags & IFF_PROMISC)
866 ctl |= SIS_RXFILTCTL_BROAD|SIS_RXFILTCTL_ALLPHYS;
867 for (i = 0; i < n; i++)
870 for (i = 0; i < n; i++)
873 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
874 if (ifma->ifma_addr->sa_family != AF_LINK)
877 LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
878 hashes[h >> 4] |= 1 << (h & 0xf);
882 ctl |= SIS_RXFILTCTL_ALLMULTI;
883 for (i = 0; i < n; i++)
888 for (i = 0; i < n; i++) {
889 CSR_WRITE_4(sc, SIS_RXFILT_CTL, (4 + i) << 16);
890 CSR_WRITE_4(sc, SIS_RXFILT_DATA, hashes[i]);
893 CSR_WRITE_4(sc, SIS_RXFILT_CTL, ctl);
897 sis_reset(struct sis_softc *sc)
899 struct ifnet *ifp = &sc->arpcom.ac_if;
902 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RESET);
904 for (i = 0; i < SIS_TIMEOUT; i++) {
905 if (!(CSR_READ_4(sc, SIS_CSR) & SIS_CSR_RESET))
909 if (i == SIS_TIMEOUT)
910 if_printf(ifp, "reset never completed\n");
912 /* Wait a little while for the chip to get its brains in order. */
916 * If this is a NetSemi chip, make sure to clear
919 if (sc->sis_type == SIS_TYPE_83815) {
920 CSR_WRITE_4(sc, NS_CLKRUN, NS_CLKRUN_PMESTS);
921 CSR_WRITE_4(sc, NS_CLKRUN, 0);
926 * Probe for an SiS chip. Check the PCI vendor and device
927 * IDs against our list and return a device name if we find a match.
930 sis_probe(device_t dev)
936 while(t->sis_name != NULL) {
937 if ((pci_get_vendor(dev) == t->sis_vid) &&
938 (pci_get_device(dev) == t->sis_did)) {
939 device_set_desc(dev, t->sis_name);
949 * Attach the interface. Allocate softc structures, do ifmedia
950 * setup and ethernet/BPF attach.
953 sis_attach(device_t dev)
955 uint8_t eaddr[ETHER_ADDR_LEN];
957 struct sis_softc *sc;
959 int error, rid, waittime;
961 error = waittime = 0;
962 sc = device_get_softc(dev);
964 if (pci_get_device(dev) == PCI_PRODUCT_SIS_900)
965 sc->sis_type = SIS_TYPE_900;
966 if (pci_get_device(dev) == PCI_PRODUCT_SIS_7016)
967 sc->sis_type = SIS_TYPE_7016;
968 if (pci_get_vendor(dev) == PCI_VENDOR_NS)
969 sc->sis_type = SIS_TYPE_83815;
971 sc->sis_rev = pci_read_config(dev, PCIR_REVID, 1);
974 * Handle power management nonsense.
977 command = pci_read_config(dev, SIS_PCI_CAPID, 4) & 0x000000FF;
978 if (command == 0x01) {
980 command = pci_read_config(dev, SIS_PCI_PWRMGMTCTRL, 4);
981 if (command & SIS_PSTATE_MASK) {
982 uint32_t iobase, membase, irq;
984 /* Save important PCI config data. */
985 iobase = pci_read_config(dev, SIS_PCI_LOIO, 4);
986 membase = pci_read_config(dev, SIS_PCI_LOMEM, 4);
987 irq = pci_read_config(dev, SIS_PCI_INTLINE, 4);
989 /* Reset the power state. */
990 device_printf(dev, "chip is in D%d power mode "
991 "-- setting to D0\n", command & SIS_PSTATE_MASK);
992 command &= 0xFFFFFFFC;
993 pci_write_config(dev, SIS_PCI_PWRMGMTCTRL, command, 4);
995 /* Restore PCI config data. */
996 pci_write_config(dev, SIS_PCI_LOIO, iobase, 4);
997 pci_write_config(dev, SIS_PCI_LOMEM, membase, 4);
998 pci_write_config(dev, SIS_PCI_INTLINE, irq, 4);
1003 * Map control/status registers.
1005 command = pci_read_config(dev, PCIR_COMMAND, 4);
1006 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN);
1007 pci_write_config(dev, PCIR_COMMAND, command, 4);
1008 command = pci_read_config(dev, PCIR_COMMAND, 4);
1010 #ifdef SIS_USEIOSPACE
1011 if (!(command & PCIM_CMD_PORTEN)) {
1012 device_printf(dev, "failed to enable I/O ports!\n");
1017 if (!(command & PCIM_CMD_MEMEN)) {
1018 device_printf(dev, "failed to enable memory mapping!\n");
1025 sc->sis_res = bus_alloc_resource_any(dev, SIS_RES, &rid, RF_ACTIVE);
1027 if (sc->sis_res == NULL) {
1028 device_printf(dev, "couldn't map ports/memory\n");
1033 sc->sis_btag = rman_get_bustag(sc->sis_res);
1034 sc->sis_bhandle = rman_get_bushandle(sc->sis_res);
1036 /* Allocate interrupt */
1038 sc->sis_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
1039 RF_SHAREABLE | RF_ACTIVE);
1041 if (sc->sis_irq == NULL) {
1042 device_printf(dev, "couldn't map interrupt\n");
1047 /* Reset the adapter. */
1050 if (sc->sis_type == SIS_TYPE_900 &&
1051 (sc->sis_rev == SIS_REV_635 ||
1052 sc->sis_rev == SIS_REV_900B)) {
1053 SIO_SET(SIS_CFG_RND_CNT);
1054 SIO_SET(SIS_CFG_PERR_DETECT);
1058 * Get station address from the EEPROM.
1060 switch (pci_get_vendor(dev)) {
1063 * Reading the MAC address out of the EEPROM on
1064 * the NatSemi chip takes a bit more work than
1065 * you'd expect. The address spans 4 16-bit words,
1066 * with the first word containing only a single bit.
1067 * You have to shift everything over one bit to
1068 * get it aligned properly. Also, the bits are
1069 * stored backwards (the LSB is really the MSB,
1070 * and so on) so you have to reverse them in order
1071 * to get the MAC address into the form we want.
1072 * Why? Who the hell knows.
1077 sis_read_eeprom(sc, (caddr_t)&tmp,
1078 NS_EE_NODEADDR, 4, 0);
1080 /* Shift everything over one bit. */
1081 tmp[3] = tmp[3] >> 1;
1082 tmp[3] |= tmp[2] << 15;
1083 tmp[2] = tmp[2] >> 1;
1084 tmp[2] |= tmp[1] << 15;
1085 tmp[1] = tmp[1] >> 1;
1086 tmp[1] |= tmp[0] << 15;
1088 /* Now reverse all the bits. */
1089 tmp[3] = sis_reverse(tmp[3]);
1090 tmp[2] = sis_reverse(tmp[2]);
1091 tmp[1] = sis_reverse(tmp[1]);
1093 bcopy((char *)&tmp[1], eaddr, ETHER_ADDR_LEN);
1096 case PCI_VENDOR_SIS:
1100 * If this is a SiS 630E chipset with an embedded
1101 * SiS 900 controller, we have to read the MAC address
1102 * from the APC CMOS RAM. Our method for doing this
1103 * is very ugly since we have to reach out and grab
1104 * ahold of hardware for which we cannot properly
1105 * allocate resources. This code is only compiled on
1106 * the i386 architecture since the SiS 630E chipset
1107 * is for x86 motherboards only. Note that there are
1108 * a lot of magic numbers in this hack. These are
1109 * taken from SiS's Linux driver. I'd like to replace
1110 * them with proper symbolic definitions, but that
1111 * requires some datasheets that I don't have access
1114 if (sc->sis_rev == SIS_REV_630S ||
1115 sc->sis_rev == SIS_REV_630E ||
1116 sc->sis_rev == SIS_REV_630EA1)
1117 sis_read_cmos(sc, dev, (caddr_t)&eaddr, 0x9, 6);
1119 else if (sc->sis_rev == SIS_REV_635 ||
1120 sc->sis_rev == SIS_REV_630ET)
1121 sis_read_mac(sc, dev, (caddr_t)&eaddr);
1122 else if (sc->sis_rev == SIS_REV_96x) {
1124 * Allow to read EEPROM from LAN. It is shared
1125 * between a 1394 controller and the NIC and each
1126 * time we access it, we need to set SIS_EECMD_REQ.
1128 SIO_SET(SIS_EECMD_REQ);
1129 for (waittime = 0; waittime < SIS_TIMEOUT;
1131 /* Force EEPROM to idle state. */
1132 sis_eeprom_idle(sc);
1133 if (CSR_READ_4(sc, SIS_EECTL) & SIS_EECMD_GNT) {
1134 sis_read_eeprom(sc, (caddr_t)&eaddr,
1135 SIS_EE_NODEADDR, 3, 0);
1141 * Set SIS_EECTL_CLK to high, so a other master
1142 * can operate on the i2c bus.
1144 SIO_SET(SIS_EECTL_CLK);
1145 /* Refuse EEPROM access by LAN */
1146 SIO_SET(SIS_EECMD_DONE);
1149 sis_read_eeprom(sc, (caddr_t)&eaddr,
1150 SIS_EE_NODEADDR, 3, 0);
1154 callout_init(&sc->sis_timer);
1157 * Allocate the parent bus DMA tag appropriate for PCI.
1159 #define SIS_NSEG_NEW 32
1160 error = bus_dma_tag_create(NULL, /* parent */
1161 1, 0, /* alignment, boundary */
1162 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */
1163 BUS_SPACE_MAXADDR, /* highaddr */
1164 NULL, NULL, /* filter, filterarg */
1165 MAXBSIZE, SIS_NSEG_NEW, /* maxsize, nsegments */
1166 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */
1167 BUS_DMA_ALLOCNOW, /* flags */
1168 &sc->sis_parent_tag);
1173 * Now allocate a tag for the DMA descriptor lists and a chunk
1174 * of DMA-able memory based on the tag. Also obtain the physical
1175 * addresses of the RX and TX ring, which we'll need later.
1176 * All of our lists are allocated as a contiguous block of memory.
1178 error = bus_dma_tag_create(sc->sis_parent_tag, /* parent */
1179 1, 0, /* alignment, boundary */
1180 BUS_SPACE_MAXADDR, /* lowaddr */
1181 BUS_SPACE_MAXADDR, /* highaddr */
1182 NULL, NULL, /* filter, filterarg */
1183 SIS_RX_LIST_SZ, 1, /* maxsize, nsegments */
1184 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */
1186 &sc->sis_ldata.sis_rx_tag);
1190 error = bus_dmamem_alloc(sc->sis_ldata.sis_rx_tag,
1191 (void **)&sc->sis_ldata.sis_rx_list,
1192 BUS_DMA_WAITOK | BUS_DMA_ZERO,
1193 &sc->sis_ldata.sis_rx_dmamap);
1196 device_printf(dev, "no memory for rx list buffers!\n");
1197 bus_dma_tag_destroy(sc->sis_ldata.sis_rx_tag);
1198 sc->sis_ldata.sis_rx_tag = NULL;
1202 error = bus_dmamap_load(sc->sis_ldata.sis_rx_tag,
1203 sc->sis_ldata.sis_rx_dmamap,
1204 sc->sis_ldata.sis_rx_list,
1205 sizeof(struct sis_desc), sis_dma_map_ring,
1206 &sc->sis_cdata.sis_rx_paddr, 0);
1209 device_printf(dev, "cannot get address of the rx ring!\n");
1210 bus_dmamem_free(sc->sis_ldata.sis_rx_tag,
1211 sc->sis_ldata.sis_rx_list,
1212 sc->sis_ldata.sis_rx_dmamap);
1213 bus_dma_tag_destroy(sc->sis_ldata.sis_rx_tag);
1214 sc->sis_ldata.sis_rx_tag = NULL;
1218 error = bus_dma_tag_create(sc->sis_parent_tag, /* parent */
1219 1, 0, /* alignment, boundary */
1220 BUS_SPACE_MAXADDR, /* lowaddr */
1221 BUS_SPACE_MAXADDR, /* highaddr */
1222 NULL, NULL, /* filter, filterarg */
1223 SIS_TX_LIST_SZ, 1, /* maxsize, nsegments */
1224 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */
1226 &sc->sis_ldata.sis_tx_tag);
1230 error = bus_dmamem_alloc(sc->sis_ldata.sis_tx_tag,
1231 (void **)&sc->sis_ldata.sis_tx_list,
1232 BUS_DMA_WAITOK | BUS_DMA_ZERO,
1233 &sc->sis_ldata.sis_tx_dmamap);
1236 device_printf(dev, "no memory for tx list buffers!\n");
1237 bus_dma_tag_destroy(sc->sis_ldata.sis_tx_tag);
1238 sc->sis_ldata.sis_tx_tag = NULL;
1242 error = bus_dmamap_load(sc->sis_ldata.sis_tx_tag,
1243 sc->sis_ldata.sis_tx_dmamap,
1244 sc->sis_ldata.sis_tx_list,
1245 sizeof(struct sis_desc), sis_dma_map_ring,
1246 &sc->sis_cdata.sis_tx_paddr, 0);
1249 device_printf(dev, "cannot get address of the tx ring!\n");
1250 bus_dmamem_free(sc->sis_ldata.sis_tx_tag,
1251 sc->sis_ldata.sis_tx_list,
1252 sc->sis_ldata.sis_tx_dmamap);
1253 bus_dma_tag_destroy(sc->sis_ldata.sis_tx_tag);
1254 sc->sis_ldata.sis_tx_tag = NULL;
1258 error = bus_dma_tag_create(sc->sis_parent_tag, /* parent */
1259 1, 0, /* alignment, boundary */
1260 BUS_SPACE_MAXADDR, /* lowaddr */
1261 BUS_SPACE_MAXADDR, /* highaddr */
1262 NULL, NULL, /* filter, filterarg */
1263 MCLBYTES, 1, /* maxsize, nsegments */
1264 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */
1270 ifp = &sc->arpcom.ac_if;
1272 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1273 ifp->if_mtu = ETHERMTU;
1274 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1275 ifp->if_ioctl = sis_ioctl;
1276 ifp->if_start = sis_start;
1277 ifp->if_watchdog = sis_watchdog;
1278 ifp->if_init = sis_init;
1279 ifp->if_baudrate = 10000000;
1280 ifq_set_maxlen(&ifp->if_snd, SIS_TX_LIST_CNT - 1);
1281 ifq_set_ready(&ifp->if_snd);
1282 #ifdef DEVICE_POLLING
1283 ifp->if_poll = sis_poll;
1285 ifp->if_capenable = ifp->if_capabilities;
1290 if (mii_phy_probe(dev, &sc->sis_miibus,
1291 sis_ifmedia_upd, sis_ifmedia_sts)) {
1292 device_printf(dev, "MII without any PHY!\n");
1298 * Call MI attach routine.
1300 ether_ifattach(ifp, eaddr, NULL);
1303 * Tell the upper layer(s) we support long frames.
1305 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
1307 error = bus_setup_intr(dev, sc->sis_irq, INTR_NETSAFE,
1310 ifp->if_serializer);
1313 device_printf(dev, "couldn't set up irq\n");
1314 ether_ifdetach(ifp);
1326 * Shutdown hardware and free up resources. It is called in both the error case
1327 * and the normal detach case so it needs to be careful about only freeing
1328 * resources that have actually been allocated.
1331 sis_detach(device_t dev)
1333 struct sis_softc *sc = device_get_softc(dev);
1334 struct ifnet *ifp = &sc->arpcom.ac_if;
1337 if (device_is_attached(dev)) {
1338 lwkt_serialize_enter(ifp->if_serializer);
1341 bus_teardown_intr(dev, sc->sis_irq, sc->sis_intrhand);
1342 lwkt_serialize_exit(ifp->if_serializer);
1344 ether_ifdetach(ifp);
1347 device_delete_child(dev, sc->sis_miibus);
1348 bus_generic_detach(dev);
1351 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sis_irq);
1353 bus_release_resource(dev, SIS_RES, SIS_RID, sc->sis_res);
1355 if (sc->sis_ldata.sis_rx_tag) {
1356 bus_dmamap_unload(sc->sis_ldata.sis_rx_tag,
1357 sc->sis_ldata.sis_rx_dmamap);
1358 bus_dmamem_free(sc->sis_ldata.sis_rx_tag,
1359 sc->sis_ldata.sis_rx_list,
1360 sc->sis_ldata.sis_rx_dmamap);
1361 bus_dma_tag_destroy(sc->sis_ldata.sis_rx_tag);
1364 if (sc->sis_ldata.sis_tx_tag) {
1365 bus_dmamap_unload(sc->sis_ldata.sis_tx_tag,
1366 sc->sis_ldata.sis_tx_dmamap);
1367 bus_dmamem_free(sc->sis_ldata.sis_tx_tag,
1368 sc->sis_ldata.sis_tx_list,
1369 sc->sis_ldata.sis_tx_dmamap);
1370 bus_dma_tag_destroy(sc->sis_ldata.sis_tx_tag);
1373 bus_dma_tag_destroy(sc->sis_tag);
1374 if (sc->sis_parent_tag)
1375 bus_dma_tag_destroy(sc->sis_parent_tag);
1381 * Initialize the transmit descriptors.
1384 sis_list_tx_init(struct sis_softc *sc)
1386 struct sis_list_data *ld;
1387 struct sis_ring_data *cd;
1390 cd = &sc->sis_cdata;
1391 ld = &sc->sis_ldata;
1393 for (i = 0; i < SIS_TX_LIST_CNT; i++) {
1394 nexti = (i == (SIS_TX_LIST_CNT - 1)) ? 0 : i+1;
1395 ld->sis_tx_list[i].sis_nextdesc =
1396 &ld->sis_tx_list[nexti];
1397 bus_dmamap_load(sc->sis_ldata.sis_tx_tag,
1398 sc->sis_ldata.sis_tx_dmamap,
1399 &ld->sis_tx_list[nexti],
1400 sizeof(struct sis_desc), sis_dma_map_desc_next,
1401 &ld->sis_tx_list[i], 0);
1402 ld->sis_tx_list[i].sis_mbuf = NULL;
1403 ld->sis_tx_list[i].sis_ptr = 0;
1404 ld->sis_tx_list[i].sis_ctl = 0;
1407 cd->sis_tx_prod = cd->sis_tx_cons = cd->sis_tx_cnt = 0;
1409 bus_dmamap_sync(sc->sis_ldata.sis_tx_tag, sc->sis_ldata.sis_tx_dmamap,
1410 BUS_DMASYNC_PREWRITE);
1416 * Initialize the RX descriptors and allocate mbufs for them. Note that
1417 * we arrange the descriptors in a closed ring, so that the last descriptor
1418 * points back to the first.
1421 sis_list_rx_init(struct sis_softc *sc)
1423 struct sis_list_data *ld;
1424 struct sis_ring_data *cd;
1427 ld = &sc->sis_ldata;
1428 cd = &sc->sis_cdata;
1430 for (i = 0; i < SIS_RX_LIST_CNT; i++) {
1431 if (sis_newbuf(sc, &ld->sis_rx_list[i], NULL) == ENOBUFS)
1433 nexti = (i == (SIS_RX_LIST_CNT - 1)) ? 0 : i+1;
1434 ld->sis_rx_list[i].sis_nextdesc =
1435 &ld->sis_rx_list[nexti];
1436 bus_dmamap_load(sc->sis_ldata.sis_rx_tag,
1437 sc->sis_ldata.sis_rx_dmamap,
1438 &ld->sis_rx_list[nexti],
1439 sizeof(struct sis_desc), sis_dma_map_desc_next,
1440 &ld->sis_rx_list[i], 0);
1443 bus_dmamap_sync(sc->sis_ldata.sis_rx_tag, sc->sis_ldata.sis_rx_dmamap,
1444 BUS_DMASYNC_PREWRITE);
1446 cd->sis_rx_prod = 0;
1452 * Initialize an RX descriptor and attach an MBUF cluster.
1455 sis_newbuf(struct sis_softc *sc, struct sis_desc *c, struct mbuf *m)
1458 m = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR);
1462 m->m_data = m->m_ext.ext_buf;
1466 c->sis_ctl = SIS_RXLEN;
1468 bus_dmamap_create(sc->sis_tag, 0, &c->sis_map);
1469 bus_dmamap_load(sc->sis_tag, c->sis_map, mtod(m, void *), MCLBYTES,
1470 sis_dma_map_desc_ptr, c, 0);
1471 bus_dmamap_sync(sc->sis_tag, c->sis_map, BUS_DMASYNC_PREWRITE);
1477 * A frame has been uploaded: pass the resulting mbuf chain up to
1478 * the higher level protocols.
1481 sis_rxeof(struct sis_softc *sc)
1485 struct sis_desc *cur_rx;
1486 int i, total_len = 0;
1489 ifp = &sc->arpcom.ac_if;
1490 i = sc->sis_cdata.sis_rx_prod;
1492 while(SIS_OWNDESC(&sc->sis_ldata.sis_rx_list[i])) {
1494 #ifdef DEVICE_POLLING
1495 if (ifp->if_flags & IFF_POLLING) {
1496 if (sc->rxcycles <= 0)
1500 #endif /* DEVICE_POLLING */
1501 cur_rx = &sc->sis_ldata.sis_rx_list[i];
1502 rxstat = cur_rx->sis_rxstat;
1503 bus_dmamap_sync(sc->sis_tag, cur_rx->sis_map,
1504 BUS_DMASYNC_POSTWRITE);
1505 bus_dmamap_unload(sc->sis_tag, cur_rx->sis_map);
1506 bus_dmamap_destroy(sc->sis_tag, cur_rx->sis_map);
1507 m = cur_rx->sis_mbuf;
1508 cur_rx->sis_mbuf = NULL;
1509 total_len = SIS_RXBYTES(cur_rx);
1510 SIS_INC(i, SIS_RX_LIST_CNT);
1513 * If an error occurs, update stats, clear the
1514 * status word and leave the mbuf cluster in place:
1515 * it should simply get re-used next time this descriptor
1516 * comes up in the ring.
1518 if (!(rxstat & SIS_CMDSTS_PKT_OK)) {
1520 if (rxstat & SIS_RXSTAT_COLL)
1521 ifp->if_collisions++;
1522 sis_newbuf(sc, cur_rx, m);
1526 /* No errors; receive the packet. */
1529 * On the x86 we do not have alignment problems, so try to
1530 * allocate a new buffer for the receive ring, and pass up
1531 * the one where the packet is already, saving the expensive
1532 * copy done in m_devget().
1533 * If we are on an architecture with alignment problems, or
1534 * if the allocation fails, then use m_devget and leave the
1535 * existing buffer in the receive ring.
1537 if (sis_newbuf(sc, cur_rx, NULL) == 0)
1538 m->m_pkthdr.len = m->m_len = total_len;
1543 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN,
1544 total_len + ETHER_ALIGN, 0, ifp, NULL);
1545 sis_newbuf(sc, cur_rx, m);
1550 m_adj(m0, ETHER_ALIGN);
1555 ifp->if_input(ifp, m);
1558 sc->sis_cdata.sis_rx_prod = i;
1562 sis_rxeoc(struct sis_softc *sc)
1569 * A frame was downloaded to the chip. It's safe for us to clean up
1574 sis_txeof(struct sis_softc *sc)
1576 struct sis_desc *cur_tx;
1580 ifp = &sc->arpcom.ac_if;
1583 * Go through our tx list and free mbufs for those
1584 * frames that have been transmitted.
1586 for (idx = sc->sis_cdata.sis_tx_cons; sc->sis_cdata.sis_tx_cnt > 0;
1587 sc->sis_cdata.sis_tx_cnt--, SIS_INC(idx, SIS_TX_LIST_CNT) ) {
1588 cur_tx = &sc->sis_ldata.sis_tx_list[idx];
1590 if (SIS_OWNDESC(cur_tx))
1593 if (cur_tx->sis_ctl & SIS_CMDSTS_MORE)
1596 if (!(cur_tx->sis_ctl & SIS_CMDSTS_PKT_OK)) {
1598 if (cur_tx->sis_txstat & SIS_TXSTAT_EXCESSCOLLS)
1599 ifp->if_collisions++;
1600 if (cur_tx->sis_txstat & SIS_TXSTAT_OUTOFWINCOLL)
1601 ifp->if_collisions++;
1604 ifp->if_collisions +=
1605 (cur_tx->sis_txstat & SIS_TXSTAT_COLLCNT) >> 16;
1608 if (cur_tx->sis_mbuf != NULL) {
1609 m_freem(cur_tx->sis_mbuf);
1610 cur_tx->sis_mbuf = NULL;
1611 bus_dmamap_unload(sc->sis_tag, cur_tx->sis_map);
1612 bus_dmamap_destroy(sc->sis_tag, cur_tx->sis_map);
1616 if (idx != sc->sis_cdata.sis_tx_cons) {
1617 /* we freed up some buffers */
1618 sc->sis_cdata.sis_tx_cons = idx;
1619 ifp->if_flags &= ~IFF_OACTIVE;
1622 ifp->if_timer = (sc->sis_cdata.sis_tx_cnt == 0) ? 0 : 5;
1628 struct sis_softc *sc = xsc;
1629 struct mii_data *mii;
1630 struct ifnet *ifp = &sc->arpcom.ac_if;
1632 lwkt_serialize_enter(ifp->if_serializer);
1634 mii = device_get_softc(sc->sis_miibus);
1637 if (!sc->sis_link) {
1639 if (mii->mii_media_status & IFM_ACTIVE &&
1640 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE)
1642 if (!ifq_is_empty(&ifp->if_snd))
1646 callout_reset(&sc->sis_timer, hz, sis_tick, sc);
1647 lwkt_serialize_exit(ifp->if_serializer);
1650 #ifdef DEVICE_POLLING
1653 sis_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
1655 struct sis_softc *sc = ifp->if_softc;
1659 /* disable interrupts */
1660 CSR_WRITE_4(sc, SIS_IER, 0);
1662 case POLL_DEREGISTER:
1663 /* enable interrupts */
1664 CSR_WRITE_4(sc, SIS_IER, 1);
1668 * On the sis, reading the status register also clears it.
1669 * So before returning to intr mode we must make sure that all
1670 * possible pending sources of interrupts have been served.
1671 * In practice this means run to completion the *eof routines,
1672 * and then call the interrupt routine
1674 sc->rxcycles = count;
1677 if (!ifq_is_empty(&ifp->if_snd))
1680 if (sc->rxcycles > 0 || cmd == POLL_AND_CHECK_STATUS) {
1683 /* Reading the ISR register clears all interrupts. */
1684 status = CSR_READ_4(sc, SIS_ISR);
1686 if (status & (SIS_ISR_RX_ERR|SIS_ISR_RX_OFLOW))
1689 if (status & (SIS_ISR_RX_IDLE))
1690 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE);
1692 if (status & SIS_ISR_SYSERR) {
1700 #endif /* DEVICE_POLLING */
1705 struct sis_softc *sc;
1710 ifp = &sc->arpcom.ac_if;
1712 /* Supress unwanted interrupts */
1713 if (!(ifp->if_flags & IFF_UP)) {
1718 /* Disable interrupts. */
1719 CSR_WRITE_4(sc, SIS_IER, 0);
1722 /* Reading the ISR register clears all interrupts. */
1723 status = CSR_READ_4(sc, SIS_ISR);
1725 if ((status & SIS_INTRS) == 0)
1729 (SIS_ISR_TX_DESC_OK | SIS_ISR_TX_ERR | SIS_ISR_TX_OK |
1734 (SIS_ISR_RX_DESC_OK | SIS_ISR_RX_OK | SIS_ISR_RX_IDLE))
1737 if (status & (SIS_ISR_RX_ERR | SIS_ISR_RX_OFLOW))
1740 if (status & (SIS_ISR_RX_IDLE))
1741 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE);
1743 if (status & SIS_ISR_SYSERR) {
1749 /* Re-enable interrupts. */
1750 CSR_WRITE_4(sc, SIS_IER, 1);
1752 if (!ifq_is_empty(&ifp->if_snd))
1757 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
1758 * pointers to the fragment pointers.
1761 sis_encap(struct sis_softc *sc, struct mbuf *m_head, uint32_t *txidx)
1763 struct sis_desc *f = NULL;
1765 int frag, cur, cnt = 0;
1768 * If there's no way we can send any packets, return now.
1770 if (SIS_TX_LIST_CNT - sc->sis_cdata.sis_tx_cnt < 2)
1774 * Start packing the mbufs in this chain into
1775 * the fragment pointers. Stop when we run out
1776 * of fragments or hit the end of the mbuf chain.
1779 cur = frag = *txidx;
1781 for (m = m_head; m != NULL; m = m->m_next) {
1782 if (m->m_len != 0) {
1783 if ((SIS_TX_LIST_CNT -
1784 (sc->sis_cdata.sis_tx_cnt + cnt)) < 2)
1786 f = &sc->sis_ldata.sis_tx_list[frag];
1787 f->sis_ctl = SIS_CMDSTS_MORE | m->m_len;
1788 bus_dmamap_create(sc->sis_tag, 0, &f->sis_map);
1789 bus_dmamap_load(sc->sis_tag, f->sis_map,
1790 mtod(m, void *), m->m_len,
1791 sis_dma_map_desc_ptr, f, 0);
1792 bus_dmamap_sync(sc->sis_tag, f->sis_map,
1793 BUS_DMASYNC_PREREAD);
1795 f->sis_ctl |= SIS_CMDSTS_OWN;
1797 SIS_INC(frag, SIS_TX_LIST_CNT);
1805 sc->sis_ldata.sis_tx_list[cur].sis_mbuf = m_head;
1806 sc->sis_ldata.sis_tx_list[cur].sis_ctl &= ~SIS_CMDSTS_MORE;
1807 sc->sis_ldata.sis_tx_list[*txidx].sis_ctl |= SIS_CMDSTS_OWN;
1808 sc->sis_cdata.sis_tx_cnt += cnt;
1815 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
1816 * to the mbuf data regions directly in the transmit lists. We also save a
1817 * copy of the pointers since the transmit list fragment pointers are
1818 * physical addresses.
1822 sis_start(struct ifnet *ifp)
1824 struct sis_softc *sc;
1825 struct mbuf *m_head = NULL;
1834 idx = sc->sis_cdata.sis_tx_prod;
1836 if (ifp->if_flags & IFF_OACTIVE)
1840 while(sc->sis_ldata.sis_tx_list[idx].sis_mbuf == NULL) {
1841 m_head = ifq_poll(&ifp->if_snd);
1845 if (sis_encap(sc, m_head, &idx)) {
1846 ifp->if_flags |= IFF_OACTIVE;
1849 ifq_dequeue(&ifp->if_snd, m_head);
1853 * If there's a BPF listener, bounce a copy of this frame
1856 BPF_MTAP(ifp, m_head);
1863 sc->sis_cdata.sis_tx_prod = idx;
1864 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_TX_ENABLE);
1867 * Set a timeout in case the chip goes out to lunch.
1875 struct sis_softc *sc = xsc;
1876 struct ifnet *ifp = &sc->arpcom.ac_if;
1877 struct mii_data *mii;
1880 * Cancel pending I/O and free all RX/TX buffers.
1884 mii = device_get_softc(sc->sis_miibus);
1886 /* Set MAC address */
1887 if (sc->sis_type == SIS_TYPE_83815) {
1888 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR0);
1889 CSR_WRITE_4(sc, SIS_RXFILT_DATA,
1890 ((uint16_t *)sc->arpcom.ac_enaddr)[0]);
1891 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR1);
1892 CSR_WRITE_4(sc, SIS_RXFILT_DATA,
1893 ((uint16_t *)sc->arpcom.ac_enaddr)[1]);
1894 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR2);
1895 CSR_WRITE_4(sc, SIS_RXFILT_DATA,
1896 ((uint16_t *)sc->arpcom.ac_enaddr)[2]);
1898 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR0);
1899 CSR_WRITE_4(sc, SIS_RXFILT_DATA,
1900 ((uint16_t *)sc->arpcom.ac_enaddr)[0]);
1901 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR1);
1902 CSR_WRITE_4(sc, SIS_RXFILT_DATA,
1903 ((uint16_t *)sc->arpcom.ac_enaddr)[1]);
1904 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR2);
1905 CSR_WRITE_4(sc, SIS_RXFILT_DATA,
1906 ((uint16_t *)sc->arpcom.ac_enaddr)[2]);
1909 /* Init circular RX list. */
1910 if (sis_list_rx_init(sc) == ENOBUFS) {
1911 if_printf(ifp, "initialization failed: "
1912 "no memory for rx buffers\n");
1918 * Init tx descriptors.
1920 sis_list_tx_init(sc);
1923 * For the NatSemi chip, we have to explicitly enable the
1924 * reception of ARP frames, as well as turn on the 'perfect
1925 * match' filter where we store the station address, otherwise
1926 * we won't receive unicasts meant for this host.
1928 if (sc->sis_type == SIS_TYPE_83815) {
1929 SIS_SETBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_ARP);
1930 SIS_SETBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_PERFECT);
1933 /* If we want promiscuous mode, set the allframes bit. */
1934 if (ifp->if_flags & IFF_PROMISC)
1935 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLPHYS);
1937 SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLPHYS);
1940 * Set the capture broadcast bit to capture broadcast frames.
1942 if (ifp->if_flags & IFF_BROADCAST)
1943 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_BROAD);
1945 SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_BROAD);
1948 * Load the multicast filter.
1950 if (sc->sis_type == SIS_TYPE_83815)
1951 sis_setmulti_ns(sc);
1953 sis_setmulti_sis(sc);
1955 /* Turn the receive filter on */
1956 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ENABLE);
1959 * Load the address of the RX and TX lists.
1961 CSR_WRITE_4(sc, SIS_RX_LISTPTR, sc->sis_cdata.sis_rx_paddr);
1962 CSR_WRITE_4(sc, SIS_TX_LISTPTR, sc->sis_cdata.sis_tx_paddr);
1964 /* SIS_CFG_EDB_MASTER_EN indicates the EDB bus is used instead of
1965 * the PCI bus. When this bit is set, the Max DMA Burst Size
1966 * for TX/RX DMA should be no larger than 16 double words.
1968 if (CSR_READ_4(sc, SIS_CFG) & SIS_CFG_EDB_MASTER_EN)
1969 CSR_WRITE_4(sc, SIS_RX_CFG, SIS_RXCFG64);
1971 CSR_WRITE_4(sc, SIS_RX_CFG, SIS_RXCFG256);
1973 /* Accept Long Packets for VLAN support */
1974 SIS_SETBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_JABBER);
1976 /* Set TX configuration */
1977 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_10_T)
1978 CSR_WRITE_4(sc, SIS_TX_CFG, SIS_TXCFG_10);
1980 CSR_WRITE_4(sc, SIS_TX_CFG, SIS_TXCFG_100);
1982 /* Set full/half duplex mode. */
1983 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
1984 SIS_SETBIT(sc, SIS_TX_CFG,
1985 (SIS_TXCFG_IGN_HBEAT|SIS_TXCFG_IGN_CARR));
1986 SIS_SETBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_TXPKTS);
1988 SIS_CLRBIT(sc, SIS_TX_CFG,
1989 (SIS_TXCFG_IGN_HBEAT|SIS_TXCFG_IGN_CARR));
1990 SIS_CLRBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_TXPKTS);
1994 * Enable interrupts.
1996 CSR_WRITE_4(sc, SIS_IMR, SIS_INTRS);
1997 #ifdef DEVICE_POLLING
1999 * ... only enable interrupts if we are not polling, make sure
2000 * they are off otherwise.
2002 if (ifp->if_flags & IFF_POLLING)
2003 CSR_WRITE_4(sc, SIS_IER, 0);
2005 #endif /* DEVICE_POLLING */
2006 CSR_WRITE_4(sc, SIS_IER, 1);
2008 /* Enable receiver and transmitter. */
2009 SIS_CLRBIT(sc, SIS_CSR, SIS_CSR_TX_DISABLE|SIS_CSR_RX_DISABLE);
2010 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE);
2017 * Page 75 of the DP83815 manual recommends the
2018 * following register settings "for optimum
2019 * performance." Note however that at least three
2020 * of the registers are listed as "reserved" in
2021 * the register map, so who knows what they do.
2023 if (sc->sis_type == SIS_TYPE_83815) {
2024 CSR_WRITE_4(sc, NS_PHY_PAGE, 0x0001);
2025 CSR_WRITE_4(sc, NS_PHY_CR, 0x189C);
2026 CSR_WRITE_4(sc, NS_PHY_TDATA, 0x0000);
2027 CSR_WRITE_4(sc, NS_PHY_DSPCFG, 0x5040);
2028 CSR_WRITE_4(sc, NS_PHY_SDCFG, 0x008C);
2031 ifp->if_flags |= IFF_RUNNING;
2032 ifp->if_flags &= ~IFF_OACTIVE;
2034 callout_reset(&sc->sis_timer, hz, sis_tick, sc);
2038 * Set media options.
2041 sis_ifmedia_upd(struct ifnet *ifp)
2043 struct sis_softc *sc;
2044 struct mii_data *mii;
2048 mii = device_get_softc(sc->sis_miibus);
2050 if (mii->mii_instance) {
2051 struct mii_softc *miisc;
2052 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
2053 mii_phy_reset(miisc);
2061 * Report current media status.
2064 sis_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
2066 struct sis_softc *sc;
2067 struct mii_data *mii;
2071 mii = device_get_softc(sc->sis_miibus);
2073 ifmr->ifm_active = mii->mii_media_active;
2074 ifmr->ifm_status = mii->mii_media_status;
2078 sis_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
2080 struct sis_softc *sc = ifp->if_softc;
2081 struct ifreq *ifr = (struct ifreq *) data;
2082 struct mii_data *mii;
2087 if (ifp->if_flags & IFF_UP) {
2090 if (ifp->if_flags & IFF_RUNNING)
2097 if (sc->sis_type == SIS_TYPE_83815)
2098 sis_setmulti_ns(sc);
2100 sis_setmulti_sis(sc);
2105 mii = device_get_softc(sc->sis_miibus);
2106 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
2109 error = ether_ioctl(ifp, command, data);
2116 sis_watchdog(struct ifnet *ifp)
2118 struct sis_softc *sc;
2123 if_printf(ifp, "watchdog timeout\n");
2129 if (!ifq_is_empty(&ifp->if_snd))
2134 * Stop the adapter and free any mbufs allocated to the
2138 sis_stop(struct sis_softc *sc)
2143 ifp = &sc->arpcom.ac_if;
2146 callout_stop(&sc->sis_timer);
2148 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
2149 CSR_WRITE_4(sc, SIS_IER, 0);
2150 CSR_WRITE_4(sc, SIS_IMR, 0);
2151 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_TX_DISABLE|SIS_CSR_RX_DISABLE);
2153 CSR_WRITE_4(sc, SIS_TX_LISTPTR, 0);
2154 CSR_WRITE_4(sc, SIS_RX_LISTPTR, 0);
2159 * Free data in the RX lists.
2161 for (i = 0; i < SIS_RX_LIST_CNT; i++) {
2162 if (sc->sis_ldata.sis_rx_list[i].sis_mbuf != NULL) {
2163 bus_dmamap_unload(sc->sis_tag,
2164 sc->sis_ldata.sis_rx_list[i].sis_map);
2165 bus_dmamap_destroy(sc->sis_tag,
2166 sc->sis_ldata.sis_rx_list[i].sis_map);
2167 m_freem(sc->sis_ldata.sis_rx_list[i].sis_mbuf);
2168 sc->sis_ldata.sis_rx_list[i].sis_mbuf = NULL;
2171 bzero(sc->sis_ldata.sis_rx_list, sizeof(sc->sis_ldata.sis_rx_list));
2174 * Free the TX list buffers.
2176 for (i = 0; i < SIS_TX_LIST_CNT; i++) {
2177 if (sc->sis_ldata.sis_tx_list[i].sis_mbuf != NULL) {
2178 bus_dmamap_unload(sc->sis_tag,
2179 sc->sis_ldata.sis_tx_list[i].sis_map);
2180 bus_dmamap_destroy(sc->sis_tag,
2181 sc->sis_ldata.sis_tx_list[i].sis_map);
2182 m_freem(sc->sis_ldata.sis_tx_list[i].sis_mbuf);
2183 sc->sis_ldata.sis_tx_list[i].sis_mbuf = NULL;
2187 bzero(sc->sis_ldata.sis_tx_list, sizeof(sc->sis_ldata.sis_tx_list));
2191 * Stop all chip I/O so that the kernel's probe routines don't
2192 * get confused by errant DMAs when rebooting.
2195 sis_shutdown(device_t dev)
2197 struct sis_softc *sc;
2200 sc = device_get_softc(dev);
2201 ifp = &sc->arpcom.ac_if;
2202 lwkt_serialize_enter(ifp->if_serializer);
2205 lwkt_serialize_exit(ifp->if_serializer);