2 * Copyright (c) Comtrol Corporation <support@comtrol.com>
5 * PCI-specific part separated from:
6 * sys/i386/isa/rp.c,v 1.33 1999/09/28 11:45:27 phk Exp
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted prodived that the follwoing conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notive, this list of conditions and the following disclainer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials prodided with the distribution.
16 * 3. All advertising materials mentioning features or use of this software
17 * must display the following acknowledgement:
18 * This product includes software developed by Comtrol Corporation.
19 * 4. The name of Comtrol Corporation may not be used to endorse or
20 * promote products derived from this software without specific
21 * prior written permission.
23 * THIS SOFTWARE IS PROVIDED BY COMTROL CORPORATION ``AS IS'' AND ANY
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35 * $FreeBSD: src/sys/dev/rp/rp_pci.c,v 1.3.2.1 2002/06/18 03:11:46 obrien Exp $
36 * $DragonFly: src/sys/dev/serial/rp/rp_pci.c,v 1.6 2006/09/05 00:55:42 dillon Exp $
39 #include <sys/param.h>
40 #include <sys/systm.h>
41 #include <sys/fcntl.h>
42 #include <sys/malloc.h>
45 #include <sys/kernel.h>
46 #include <machine/resource.h>
47 #include <machine/bus.h>
55 #include <bus/pci/pcidevs.h>
56 #include <bus/pci/pcireg.h>
57 #include <bus/pci/pcivar.h>
59 /**************************************************************************
60 MUDBAC remapped for PCI
61 **************************************************************************/
63 #define _CFG_INT_PCI 0x40
64 #define _PCI_INT_FUNC 0x3A
66 #define PCI_STROB 0x2000
67 #define INTR_EN_PCI 0x0010
69 /***************************************************************************
70 Function: sPCIControllerEOI
71 Purpose: Strobe the MUDBAC's End Of Interrupt bit.
72 Call: sPCIControllerEOI(CtlP)
73 CONTROLLER_T *CtlP; Ptr to controller structure
75 #define sPCIControllerEOI(CtlP) rp_writeio2(CtlP, 0, _PCI_INT_FUNC, PCI_STROB)
77 /***************************************************************************
78 Function: sPCIGetControllerIntStatus
79 Purpose: Get the controller interrupt status
80 Call: sPCIGetControllerIntStatus(CtlP)
81 CONTROLLER_T *CtlP; Ptr to controller structure
82 Return: Byte_t: The controller interrupt status in the lower 4
83 bits. Bits 0 through 3 represent AIOP's 0
84 through 3 respectively. If a bit is set that
85 AIOP is interrupting. Bits 4 through 7 will
88 #define sPCIGetControllerIntStatus(CTLP) ((rp_readio2(CTLP, 0, _PCI_INT_FUNC) >> 8) & 0x1f)
90 static devclass_t rp_devclass;
92 static int rp_pciprobe(device_t dev);
93 static int rp_pciattach(device_t dev);
95 static int rp_pcidetach(device_t dev);
96 static int rp_pcishutdown(device_t dev);
98 static void rp_pcireleaseresource(CONTROLLER_t *ctlp);
99 static int sPCIInitController( CONTROLLER_t *CtlP,
105 static rp_aiop2rid_t rp_pci_aiop2rid;
106 static rp_aiop2off_t rp_pci_aiop2off;
107 static rp_ctlmask_t rp_pci_ctlmask;
110 * The following functions are the pci-specific part
115 rp_pciprobe(device_t dev)
120 if ((pci_get_devid(dev) & 0xffff) == PCI_VENDOR_COMTROL)
121 s = "RocketPort PCI";
124 device_set_desc(dev, s);
132 rp_pciattach(device_t dev)
134 int num_ports, num_aiops;
141 ctlp = device_get_softc(dev);
142 bzero(ctlp, sizeof(*ctlp));
144 unit = device_get_unit(dev);
145 ctlp->aiop2rid = rp_pci_aiop2rid;
146 ctlp->aiop2off = rp_pci_aiop2off;
147 ctlp->ctlmask = rp_pci_ctlmask;
149 /* Wake up the device. */
150 stcmd = pci_read_config(dev, PCIR_COMMAND, 4);
151 if ((stcmd & PCIM_CMD_PORTEN) == 0) {
152 stcmd |= (PCIM_CMD_PORTEN);
153 pci_write_config(dev, PCIR_COMMAND, 4, stcmd);
156 /* The IO ports of AIOPs for a PCI controller are continuous. */
158 ctlp->io_rid = malloc(sizeof(*(ctlp->io_rid)) * ctlp->io_num,
159 M_DEVBUF, M_WAITOK | M_ZERO);
160 ctlp->io = malloc(sizeof(*(ctlp->io)) * ctlp->io_num,
161 M_DEVBUF, M_WAITOK | M_ZERO);
163 ctlp->bus_ctlp = NULL;
165 ctlp->io_rid[0] = 0x10;
166 ctlp->io[0] = bus_alloc_resource(dev, SYS_RES_IOPORT, &ctlp->io_rid[0], 0, ~0, 1, RF_ACTIVE);
167 if(ctlp->io[0] == NULL) {
168 device_printf(dev, "ioaddr mapping failed for RocketPort(PCI).\n");
173 num_aiops = sPCIInitController(ctlp,
174 MAX_AIOPS_PER_BOARD, 0,
175 FREQ_DIS, 0, (pci_get_devid(dev) >> 16) & 0xffff);
178 for(aiop=0; aiop < num_aiops; aiop++) {
179 sResetAiopByNum(ctlp, aiop);
180 num_ports += sGetAiopNumChan(ctlp, aiop);
183 retval = rp_attachcommon(ctlp, num_aiops, num_ports);
190 rp_pcireleaseresource(ctlp);
197 rp_pcidetach(device_t dev)
201 if (device_get_state(dev) == DS_BUSY)
204 ctlp = device_get_softc(dev);
206 rp_pcireleaseresource(ctlp);
212 rp_pcishutdown(device_t dev)
216 if (device_get_state(dev) == DS_BUSY)
219 ctlp = device_get_softc(dev);
221 rp_pcireleaseresource(ctlp);
228 rp_pcireleaseresource(CONTROLLER_t *ctlp)
230 rp_releaseresource(ctlp);
232 if (ctlp->io != NULL) {
233 if (ctlp->io[0] != NULL)
234 bus_release_resource(ctlp->dev, SYS_RES_IOPORT, ctlp->io_rid[0], ctlp->io[0]);
235 kfree(ctlp->io, M_DEVBUF);
237 if (ctlp->io_rid != NULL)
238 kfree(ctlp->io_rid, M_DEVBUF);
242 sPCIInitController( CONTROLLER_t *CtlP,
251 CtlP->CtlID = CTLID_0001; /* controller release 1 */
253 sPCIControllerEOI(CtlP);
257 for(i=0; i < AiopNum; i++)
259 /*device_printf(CtlP->dev, "aiop %d.\n", i);*/
260 CtlP->AiopID[i] = sReadAiopID(CtlP, i); /* read AIOP ID */
261 /*device_printf(CtlP->dev, "ID = %d.\n", CtlP->AiopID[i]);*/
262 if(CtlP->AiopID[i] == AIOPID_NULL) /* if AIOP does not exist */
264 break; /* done looking for AIOPs */
267 switch( VendorDevice ) {
268 case PCI_PRODUCT_COMTROL_ROCKETPORT4QUAD:
269 case PCI_PRODUCT_COMTROL_ROCKETPORT4RJ:
270 case PCI_PRODUCT_COMTROL_ROCKETMODEM4:
271 CtlP->AiopNumChan[i] = 4;
273 case PCI_PRODUCT_COMTROL_ROCKETMODEM6:
274 CtlP->AiopNumChan[i] = 6;
276 case PCI_PRODUCT_COMTROL_ROCKETPORT8OCTA:
277 case PCI_PRODUCT_COMTROL_ROCKETPORT8RJ:
278 case PCI_PRODUCT_COMTROL_ROCKETPORT8EXT:
279 case PCI_PRODUCT_COMTROL_ROCKETPORT16EXT:
280 case PCI_PRODUCT_COMTROL_ROCKETPORT32EXT:
281 CtlP->AiopNumChan[i] = 8;
285 CtlP->AiopNumChan[i] = 8;
287 CtlP->AiopNumChan[i] = sReadAiopNumChan(CtlP, i);
291 /*device_printf(CtlP->dev, "%d channels.\n", CtlP->AiopNumChan[i]);*/
292 rp_writeaiop2(CtlP, i, _INDX_ADDR,_CLK_PRE); /* clock prescaler */
293 /*device_printf(CtlP->dev, "configuring clock prescaler.\n");*/
294 rp_writeaiop1(CtlP, i, _INDX_DATA,CLOCK_PRESC);
295 /*device_printf(CtlP->dev, "configured clock prescaler.\n");*/
296 CtlP->NumAiop++; /* bump count of AIOPs */
299 if(CtlP->NumAiop == 0)
302 return(CtlP->NumAiop);
307 * Maps (aiop, offset) to rid.
310 rp_pci_aiop2rid(int aiop, int offset)
312 /* Always return zero for a PCI controller. */
318 * Maps (aiop, offset) to the offset of resource.
321 rp_pci_aiop2off(int aiop, int offset)
323 /* Each AIOP reserves 0x40 bytes. */
324 return aiop * 0x40 + offset;
327 /* Read the int status for a PCI controller. */
329 rp_pci_ctlmask(CONTROLLER_t *ctlp)
331 return sPCIGetControllerIntStatus(ctlp);
334 static device_method_t rp_pcimethods[] = {
335 /* Device interface */
336 DEVMETHOD(device_probe, rp_pciprobe),
337 DEVMETHOD(device_attach, rp_pciattach),
339 DEVMETHOD(device_detach, rp_pcidetach),
340 DEVMETHOD(device_shutdown, rp_pcishutdown),
346 static driver_t rp_pcidriver = {
349 sizeof(CONTROLLER_t),
353 * rp can be attached to a pci bus.
355 DRIVER_MODULE(rp, pci, rp_pcidriver, rp_devclass, 0, 0);