2 * Copyright (c) 2004 Joerg Sonnenberger <joerg@bec.de>. All rights reserved.
4 * Copyright (c) 2001-2008, Intel Corporation
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:
10 * 1. Redistributions of source code must retain the above copyright notice,
11 * this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * 3. Neither the name of the Intel Corporation nor the names of its
18 * contributors may be used to endorse or promote products derived from
19 * this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
34 * Copyright (c) 2005 The DragonFly Project. All rights reserved.
36 * This code is derived from software contributed to The DragonFly Project
37 * by Matthew Dillon <dillon@backplane.com>
39 * Redistribution and use in source and binary forms, with or without
40 * modification, are permitted provided that the following conditions
43 * 1. Redistributions of source code must retain the above copyright
44 * notice, this list of conditions and the following disclaimer.
45 * 2. Redistributions in binary form must reproduce the above copyright
46 * notice, this list of conditions and the following disclaimer in
47 * the documentation and/or other materials provided with the
49 * 3. Neither the name of The DragonFly Project nor the names of its
50 * contributors may be used to endorse or promote products derived
51 * from this software without specific, prior written permission.
53 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
54 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
55 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
56 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
57 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
58 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
59 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
60 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
61 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
62 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
63 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
68 * SERIALIZATION API RULES:
70 * - If the driver uses the same serializer for the interrupt as for the
71 * ifnet, most of the serialization will be done automatically for the
74 * - ifmedia entry points will be serialized by the ifmedia code using the
77 * - if_* entry points except for if_input will be serialized by the IF
78 * and protocol layers.
80 * - The device driver must be sure to serialize access from timeout code
81 * installed by the device driver.
83 * - The device driver typically holds the serializer at the time it wishes
86 * - We must call lwkt_serialize_handler_enable() prior to enabling the
87 * hardware interrupt and lwkt_serialize_handler_disable() after disabling
88 * the hardware interrupt in order to avoid handler execution races from
89 * scheduled interrupt threads.
91 * NOTE! Since callers into the device driver hold the ifnet serializer,
92 * the device driver may be holding a serializer at the time it calls
93 * if_input even if it is not serializer-aware.
96 #include "opt_ifpoll.h"
98 #include <sys/param.h>
100 #include <sys/endian.h>
101 #include <sys/interrupt.h>
102 #include <sys/kernel.h>
104 #include <sys/malloc.h>
105 #include <sys/mbuf.h>
106 #include <sys/proc.h>
107 #include <sys/rman.h>
108 #include <sys/serialize.h>
109 #include <sys/socket.h>
110 #include <sys/sockio.h>
111 #include <sys/sysctl.h>
112 #include <sys/systm.h>
115 #include <net/ethernet.h>
117 #include <net/if_arp.h>
118 #include <net/if_dl.h>
119 #include <net/if_media.h>
120 #include <net/if_poll.h>
121 #include <net/ifq_var.h>
122 #include <net/vlan/if_vlan_var.h>
123 #include <net/vlan/if_vlan_ether.h>
125 #include <netinet/ip.h>
126 #include <netinet/tcp.h>
127 #include <netinet/udp.h>
129 #include <bus/pci/pcivar.h>
130 #include <bus/pci/pcireg.h>
132 #include <dev/netif/ig_hal/e1000_api.h>
133 #include <dev/netif/ig_hal/e1000_82571.h>
134 #include <dev/netif/em/if_em.h>
136 #define EM_NAME "Intel(R) PRO/1000 Network Connection "
137 #define EM_VER " 7.2.4"
139 #define _EM_DEVICE(id, ret) \
140 { EM_VENDOR_ID, E1000_DEV_ID_##id, ret, EM_NAME #id EM_VER }
141 #define EM_EMX_DEVICE(id) _EM_DEVICE(id, -100)
142 #define EM_DEVICE(id) _EM_DEVICE(id, 0)
143 #define EM_DEVICE_NULL { 0, 0, 0, NULL }
145 static const struct em_vendor_info em_vendor_info_array[] = {
147 EM_DEVICE(82540EM_LOM),
149 EM_DEVICE(82540EP_LOM),
150 EM_DEVICE(82540EP_LP),
154 EM_DEVICE(82541ER_LOM),
155 EM_DEVICE(82541EI_MOBILE),
157 EM_DEVICE(82541GI_LF),
158 EM_DEVICE(82541GI_MOBILE),
162 EM_DEVICE(82543GC_FIBER),
163 EM_DEVICE(82543GC_COPPER),
165 EM_DEVICE(82544EI_COPPER),
166 EM_DEVICE(82544EI_FIBER),
167 EM_DEVICE(82544GC_COPPER),
168 EM_DEVICE(82544GC_LOM),
170 EM_DEVICE(82545EM_COPPER),
171 EM_DEVICE(82545EM_FIBER),
172 EM_DEVICE(82545GM_COPPER),
173 EM_DEVICE(82545GM_FIBER),
174 EM_DEVICE(82545GM_SERDES),
176 EM_DEVICE(82546EB_COPPER),
177 EM_DEVICE(82546EB_FIBER),
178 EM_DEVICE(82546EB_QUAD_COPPER),
179 EM_DEVICE(82546GB_COPPER),
180 EM_DEVICE(82546GB_FIBER),
181 EM_DEVICE(82546GB_SERDES),
182 EM_DEVICE(82546GB_PCIE),
183 EM_DEVICE(82546GB_QUAD_COPPER),
184 EM_DEVICE(82546GB_QUAD_COPPER_KSP3),
187 EM_DEVICE(82547EI_MOBILE),
190 EM_EMX_DEVICE(82571EB_COPPER),
191 EM_EMX_DEVICE(82571EB_FIBER),
192 EM_EMX_DEVICE(82571EB_SERDES),
193 EM_EMX_DEVICE(82571EB_SERDES_DUAL),
194 EM_EMX_DEVICE(82571EB_SERDES_QUAD),
195 EM_EMX_DEVICE(82571EB_QUAD_COPPER),
196 EM_EMX_DEVICE(82571EB_QUAD_COPPER_BP),
197 EM_EMX_DEVICE(82571EB_QUAD_COPPER_LP),
198 EM_EMX_DEVICE(82571EB_QUAD_FIBER),
199 EM_EMX_DEVICE(82571PT_QUAD_COPPER),
201 EM_EMX_DEVICE(82572EI_COPPER),
202 EM_EMX_DEVICE(82572EI_FIBER),
203 EM_EMX_DEVICE(82572EI_SERDES),
204 EM_EMX_DEVICE(82572EI),
206 EM_EMX_DEVICE(82573E),
207 EM_EMX_DEVICE(82573E_IAMT),
208 EM_EMX_DEVICE(82573L),
212 EM_EMX_DEVICE(80003ES2LAN_COPPER_SPT),
213 EM_EMX_DEVICE(80003ES2LAN_SERDES_SPT),
214 EM_EMX_DEVICE(80003ES2LAN_COPPER_DPT),
215 EM_EMX_DEVICE(80003ES2LAN_SERDES_DPT),
217 EM_DEVICE(ICH8_IGP_M_AMT),
218 EM_DEVICE(ICH8_IGP_AMT),
219 EM_DEVICE(ICH8_IGP_C),
221 EM_DEVICE(ICH8_IFE_GT),
222 EM_DEVICE(ICH8_IFE_G),
223 EM_DEVICE(ICH8_IGP_M),
224 EM_DEVICE(ICH8_82567V_3),
226 EM_DEVICE(ICH9_IGP_M_AMT),
227 EM_DEVICE(ICH9_IGP_AMT),
228 EM_DEVICE(ICH9_IGP_C),
229 EM_DEVICE(ICH9_IGP_M),
230 EM_DEVICE(ICH9_IGP_M_V),
232 EM_DEVICE(ICH9_IFE_GT),
233 EM_DEVICE(ICH9_IFE_G),
236 EM_EMX_DEVICE(82574L),
237 EM_EMX_DEVICE(82574LA),
239 EM_DEVICE(ICH10_R_BM_LM),
240 EM_DEVICE(ICH10_R_BM_LF),
241 EM_DEVICE(ICH10_R_BM_V),
242 EM_DEVICE(ICH10_D_BM_LM),
243 EM_DEVICE(ICH10_D_BM_LF),
244 EM_DEVICE(ICH10_D_BM_V),
246 EM_DEVICE(PCH_M_HV_LM),
247 EM_DEVICE(PCH_M_HV_LC),
248 EM_DEVICE(PCH_D_HV_DM),
249 EM_DEVICE(PCH_D_HV_DC),
251 EM_DEVICE(PCH2_LV_LM),
252 EM_DEVICE(PCH2_LV_V),
254 /* required last entry */
258 static int em_probe(device_t);
259 static int em_attach(device_t);
260 static int em_detach(device_t);
261 static int em_shutdown(device_t);
262 static int em_suspend(device_t);
263 static int em_resume(device_t);
265 static void em_init(void *);
266 static void em_stop(struct adapter *);
267 static int em_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
268 static void em_start(struct ifnet *, struct ifaltq_subque *);
270 static void em_npoll(struct ifnet *, struct ifpoll_info *);
271 static void em_npoll_compat(struct ifnet *, void *, int);
273 static void em_watchdog(struct ifnet *);
274 static void em_media_status(struct ifnet *, struct ifmediareq *);
275 static int em_media_change(struct ifnet *);
276 static void em_timer(void *);
278 static void em_intr(void *);
279 static void em_intr_mask(void *);
280 static void em_intr_body(struct adapter *, boolean_t);
281 static void em_rxeof(struct adapter *, int);
282 static void em_txeof(struct adapter *);
283 static void em_tx_collect(struct adapter *);
284 static void em_tx_purge(struct adapter *);
285 static void em_enable_intr(struct adapter *);
286 static void em_disable_intr(struct adapter *);
288 static int em_dma_malloc(struct adapter *, bus_size_t,
289 struct em_dma_alloc *);
290 static void em_dma_free(struct adapter *, struct em_dma_alloc *);
291 static void em_init_tx_ring(struct adapter *);
292 static int em_init_rx_ring(struct adapter *);
293 static int em_create_tx_ring(struct adapter *);
294 static int em_create_rx_ring(struct adapter *);
295 static void em_destroy_tx_ring(struct adapter *, int);
296 static void em_destroy_rx_ring(struct adapter *, int);
297 static int em_newbuf(struct adapter *, int, int);
298 static int em_encap(struct adapter *, struct mbuf **, int *, int *);
299 static void em_rxcsum(struct adapter *, struct e1000_rx_desc *,
301 static int em_txcsum(struct adapter *, struct mbuf *,
302 uint32_t *, uint32_t *);
303 static int em_tso_pullup(struct adapter *, struct mbuf **);
304 static int em_tso_setup(struct adapter *, struct mbuf *,
305 uint32_t *, uint32_t *);
307 static int em_get_hw_info(struct adapter *);
308 static int em_is_valid_eaddr(const uint8_t *);
309 static int em_alloc_pci_res(struct adapter *);
310 static void em_free_pci_res(struct adapter *);
311 static int em_reset(struct adapter *);
312 static void em_setup_ifp(struct adapter *);
313 static void em_init_tx_unit(struct adapter *);
314 static void em_init_rx_unit(struct adapter *);
315 static void em_update_stats(struct adapter *);
316 static void em_set_promisc(struct adapter *);
317 static void em_disable_promisc(struct adapter *);
318 static void em_set_multi(struct adapter *);
319 static void em_update_link_status(struct adapter *);
320 static void em_smartspeed(struct adapter *);
321 static void em_set_itr(struct adapter *, uint32_t);
322 static void em_disable_aspm(struct adapter *);
324 /* Hardware workarounds */
325 static int em_82547_fifo_workaround(struct adapter *, int);
326 static void em_82547_update_fifo_head(struct adapter *, int);
327 static int em_82547_tx_fifo_reset(struct adapter *);
328 static void em_82547_move_tail(void *);
329 static void em_82547_move_tail_serialized(struct adapter *);
330 static uint32_t em_82544_fill_desc(bus_addr_t, uint32_t, PDESC_ARRAY);
332 static void em_print_debug_info(struct adapter *);
333 static void em_print_nvm_info(struct adapter *);
334 static void em_print_hw_stats(struct adapter *);
336 static int em_sysctl_stats(SYSCTL_HANDLER_ARGS);
337 static int em_sysctl_debug_info(SYSCTL_HANDLER_ARGS);
338 static int em_sysctl_int_throttle(SYSCTL_HANDLER_ARGS);
339 static int em_sysctl_int_tx_nsegs(SYSCTL_HANDLER_ARGS);
340 static void em_add_sysctl(struct adapter *adapter);
342 /* Management and WOL Support */
343 static void em_get_mgmt(struct adapter *);
344 static void em_rel_mgmt(struct adapter *);
345 static void em_get_hw_control(struct adapter *);
346 static void em_rel_hw_control(struct adapter *);
347 static void em_enable_wol(device_t);
349 static device_method_t em_methods[] = {
350 /* Device interface */
351 DEVMETHOD(device_probe, em_probe),
352 DEVMETHOD(device_attach, em_attach),
353 DEVMETHOD(device_detach, em_detach),
354 DEVMETHOD(device_shutdown, em_shutdown),
355 DEVMETHOD(device_suspend, em_suspend),
356 DEVMETHOD(device_resume, em_resume),
360 static driver_t em_driver = {
363 sizeof(struct adapter),
366 static devclass_t em_devclass;
368 DECLARE_DUMMY_MODULE(if_em);
369 MODULE_DEPEND(em, ig_hal, 1, 1, 1);
370 DRIVER_MODULE(if_em, pci, em_driver, em_devclass, NULL, NULL);
375 static int em_int_throttle_ceil = EM_DEFAULT_ITR;
376 static int em_rxd = EM_DEFAULT_RXD;
377 static int em_txd = EM_DEFAULT_TXD;
378 static int em_smart_pwr_down = 0;
380 /* Controls whether promiscuous also shows bad packets */
381 static int em_debug_sbp = FALSE;
383 static int em_82573_workaround = 1;
384 static int em_msi_enable = 1;
386 TUNABLE_INT("hw.em.int_throttle_ceil", &em_int_throttle_ceil);
387 TUNABLE_INT("hw.em.rxd", &em_rxd);
388 TUNABLE_INT("hw.em.txd", &em_txd);
389 TUNABLE_INT("hw.em.smart_pwr_down", &em_smart_pwr_down);
390 TUNABLE_INT("hw.em.sbp", &em_debug_sbp);
391 TUNABLE_INT("hw.em.82573_workaround", &em_82573_workaround);
392 TUNABLE_INT("hw.em.msi.enable", &em_msi_enable);
394 /* Global used in WOL setup with multiport cards */
395 static int em_global_quad_port_a = 0;
397 /* Set this to one to display debug statistics */
398 static int em_display_debug_stats = 0;
400 #if !defined(KTR_IF_EM)
401 #define KTR_IF_EM KTR_ALL
403 KTR_INFO_MASTER(if_em);
404 KTR_INFO(KTR_IF_EM, if_em, intr_beg, 0, "intr begin");
405 KTR_INFO(KTR_IF_EM, if_em, intr_end, 1, "intr end");
406 KTR_INFO(KTR_IF_EM, if_em, pkt_receive, 4, "rx packet");
407 KTR_INFO(KTR_IF_EM, if_em, pkt_txqueue, 5, "tx packet");
408 KTR_INFO(KTR_IF_EM, if_em, pkt_txclean, 6, "tx clean");
409 #define logif(name) KTR_LOG(if_em_ ## name)
412 em_probe(device_t dev)
414 const struct em_vendor_info *ent;
417 vid = pci_get_vendor(dev);
418 did = pci_get_device(dev);
420 for (ent = em_vendor_info_array; ent->desc != NULL; ++ent) {
421 if (vid == ent->vendor_id && did == ent->device_id) {
422 device_set_desc(dev, ent->desc);
423 device_set_async_attach(dev, TRUE);
431 em_attach(device_t dev)
433 struct adapter *adapter = device_get_softc(dev);
434 struct ifnet *ifp = &adapter->arpcom.ac_if;
437 uint16_t eeprom_data, device_id, apme_mask;
438 driver_intr_t *intr_func;
440 adapter->dev = adapter->osdep.dev = dev;
442 callout_init_mp(&adapter->timer);
443 callout_init_mp(&adapter->tx_fifo_timer);
445 /* Determine hardware and mac info */
446 error = em_get_hw_info(adapter);
448 device_printf(dev, "Identify hardware failed\n");
452 /* Setup PCI resources */
453 error = em_alloc_pci_res(adapter);
455 device_printf(dev, "Allocation of PCI resources failed\n");
460 * For ICH8 and family we need to map the flash memory,
461 * and this must happen after the MAC is identified.
463 if (adapter->hw.mac.type == e1000_ich8lan ||
464 adapter->hw.mac.type == e1000_ich9lan ||
465 adapter->hw.mac.type == e1000_ich10lan ||
466 adapter->hw.mac.type == e1000_pchlan ||
467 adapter->hw.mac.type == e1000_pch2lan) {
468 adapter->flash_rid = EM_BAR_FLASH;
470 adapter->flash = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
471 &adapter->flash_rid, RF_ACTIVE);
472 if (adapter->flash == NULL) {
473 device_printf(dev, "Mapping of Flash failed\n");
477 adapter->osdep.flash_bus_space_tag =
478 rman_get_bustag(adapter->flash);
479 adapter->osdep.flash_bus_space_handle =
480 rman_get_bushandle(adapter->flash);
483 * This is used in the shared code
484 * XXX this goof is actually not used.
486 adapter->hw.flash_address = (uint8_t *)adapter->flash;
489 switch (adapter->hw.mac.type) {
493 * Pullup extra 4bytes into the first data segment, see:
494 * 82571/82572 specification update errata #7
497 * 4bytes instead of 2bytes, which are mentioned in the
498 * errata, are pulled; mainly to keep rest of the data
501 adapter->flags |= EM_FLAG_TSO_PULLEX;
506 case e1000_80003es2lan:
507 adapter->flags |= EM_FLAG_TSO;
514 /* Do Shared Code initialization */
515 if (e1000_setup_init_funcs(&adapter->hw, TRUE)) {
516 device_printf(dev, "Setup of Shared code failed\n");
521 e1000_get_bus_info(&adapter->hw);
524 * Validate number of transmit and receive descriptors. It
525 * must not exceed hardware maximum, and must be multiple
526 * of E1000_DBA_ALIGN.
528 if ((em_txd * sizeof(struct e1000_tx_desc)) % EM_DBA_ALIGN != 0 ||
529 (adapter->hw.mac.type >= e1000_82544 && em_txd > EM_MAX_TXD) ||
530 (adapter->hw.mac.type < e1000_82544 && em_txd > EM_MAX_TXD_82543) ||
531 em_txd < EM_MIN_TXD) {
532 device_printf(dev, "Using %d TX descriptors instead of %d!\n",
533 EM_DEFAULT_TXD, em_txd);
534 adapter->num_tx_desc = EM_DEFAULT_TXD;
536 adapter->num_tx_desc = em_txd;
538 if ((em_rxd * sizeof(struct e1000_rx_desc)) % EM_DBA_ALIGN != 0 ||
539 (adapter->hw.mac.type >= e1000_82544 && em_rxd > EM_MAX_RXD) ||
540 (adapter->hw.mac.type < e1000_82544 && em_rxd > EM_MAX_RXD_82543) ||
541 em_rxd < EM_MIN_RXD) {
542 device_printf(dev, "Using %d RX descriptors instead of %d!\n",
543 EM_DEFAULT_RXD, em_rxd);
544 adapter->num_rx_desc = EM_DEFAULT_RXD;
546 adapter->num_rx_desc = em_rxd;
549 adapter->hw.mac.autoneg = DO_AUTO_NEG;
550 adapter->hw.phy.autoneg_wait_to_complete = FALSE;
551 adapter->hw.phy.autoneg_advertised = AUTONEG_ADV_DEFAULT;
552 adapter->rx_buffer_len = MCLBYTES;
555 * Interrupt throttle rate
557 if (em_int_throttle_ceil == 0) {
558 adapter->int_throttle_ceil = 0;
560 int throttle = em_int_throttle_ceil;
563 throttle = EM_DEFAULT_ITR;
565 /* Recalculate the tunable value to get the exact frequency. */
566 throttle = 1000000000 / 256 / throttle;
568 /* Upper 16bits of ITR is reserved and should be zero */
569 if (throttle & 0xffff0000)
570 throttle = 1000000000 / 256 / EM_DEFAULT_ITR;
572 adapter->int_throttle_ceil = 1000000000 / 256 / throttle;
575 e1000_init_script_state_82541(&adapter->hw, TRUE);
576 e1000_set_tbi_compatibility_82543(&adapter->hw, TRUE);
579 if (adapter->hw.phy.media_type == e1000_media_type_copper) {
580 adapter->hw.phy.mdix = AUTO_ALL_MODES;
581 adapter->hw.phy.disable_polarity_correction = FALSE;
582 adapter->hw.phy.ms_type = EM_MASTER_SLAVE;
585 /* Set the frame limits assuming standard ethernet sized frames. */
586 adapter->max_frame_size = ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN;
587 adapter->min_frame_size = ETH_ZLEN + ETHER_CRC_LEN;
589 /* This controls when hardware reports transmit completion status. */
590 adapter->hw.mac.report_tx_early = 1;
593 * Create top level busdma tag
595 error = bus_dma_tag_create(NULL, 1, 0,
596 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
598 BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT,
599 0, &adapter->parent_dtag);
601 device_printf(dev, "could not create top level DMA tag\n");
606 * Allocate Transmit Descriptor ring
608 tsize = roundup2(adapter->num_tx_desc * sizeof(struct e1000_tx_desc),
610 error = em_dma_malloc(adapter, tsize, &adapter->txdma);
612 device_printf(dev, "Unable to allocate tx_desc memory\n");
615 adapter->tx_desc_base = adapter->txdma.dma_vaddr;
618 * Allocate Receive Descriptor ring
620 rsize = roundup2(adapter->num_rx_desc * sizeof(struct e1000_rx_desc),
622 error = em_dma_malloc(adapter, rsize, &adapter->rxdma);
624 device_printf(dev, "Unable to allocate rx_desc memory\n");
627 adapter->rx_desc_base = adapter->rxdma.dma_vaddr;
629 /* Allocate multicast array memory. */
630 adapter->mta = kmalloc(ETH_ADDR_LEN * MAX_NUM_MULTICAST_ADDRESSES,
633 /* Indicate SOL/IDER usage */
634 if (e1000_check_reset_block(&adapter->hw)) {
636 "PHY reset is blocked due to SOL/IDER session.\n");
640 * Start from a known state, this is important in reading the
641 * nvm and mac from that.
643 e1000_reset_hw(&adapter->hw);
645 /* Make sure we have a good EEPROM before we read from it */
646 if (e1000_validate_nvm_checksum(&adapter->hw) < 0) {
648 * Some PCI-E parts fail the first check due to
649 * the link being in sleep state, call it again,
650 * if it fails a second time its a real issue.
652 if (e1000_validate_nvm_checksum(&adapter->hw) < 0) {
654 "The EEPROM Checksum Is Not Valid\n");
660 /* Copy the permanent MAC address out of the EEPROM */
661 if (e1000_read_mac_addr(&adapter->hw) < 0) {
662 device_printf(dev, "EEPROM read error while reading MAC"
667 if (!em_is_valid_eaddr(adapter->hw.mac.addr)) {
668 device_printf(dev, "Invalid MAC address\n");
673 /* Allocate transmit descriptors and buffers */
674 error = em_create_tx_ring(adapter);
676 device_printf(dev, "Could not setup transmit structures\n");
680 /* Allocate receive descriptors and buffers */
681 error = em_create_rx_ring(adapter);
683 device_printf(dev, "Could not setup receive structures\n");
687 /* Manually turn off all interrupts */
688 E1000_WRITE_REG(&adapter->hw, E1000_IMC, 0xffffffff);
690 /* Determine if we have to control management hardware */
691 if (e1000_enable_mng_pass_thru(&adapter->hw))
692 adapter->flags |= EM_FLAG_HAS_MGMT;
697 apme_mask = EM_EEPROM_APME;
699 switch (adapter->hw.mac.type) {
706 adapter->flags |= EM_FLAG_HAS_AMT;
710 case e1000_82546_rev_3:
713 case e1000_80003es2lan:
714 if (adapter->hw.bus.func == 1) {
715 e1000_read_nvm(&adapter->hw,
716 NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
718 e1000_read_nvm(&adapter->hw,
719 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
728 apme_mask = E1000_WUC_APME;
729 adapter->flags |= EM_FLAG_HAS_AMT;
730 eeprom_data = E1000_READ_REG(&adapter->hw, E1000_WUC);
734 e1000_read_nvm(&adapter->hw,
735 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
738 if (eeprom_data & apme_mask)
739 adapter->wol = E1000_WUFC_MAG | E1000_WUFC_MC;
742 * We have the eeprom settings, now apply the special cases
743 * where the eeprom may be wrong or the board won't support
744 * wake on lan on a particular port
746 device_id = pci_get_device(dev);
748 case E1000_DEV_ID_82546GB_PCIE:
752 case E1000_DEV_ID_82546EB_FIBER:
753 case E1000_DEV_ID_82546GB_FIBER:
754 case E1000_DEV_ID_82571EB_FIBER:
756 * Wake events only supported on port A for dual fiber
757 * regardless of eeprom setting
759 if (E1000_READ_REG(&adapter->hw, E1000_STATUS) &
764 case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3:
765 case E1000_DEV_ID_82571EB_QUAD_COPPER:
766 case E1000_DEV_ID_82571EB_QUAD_FIBER:
767 case E1000_DEV_ID_82571EB_QUAD_COPPER_LP:
768 /* if quad port adapter, disable WoL on all but port A */
769 if (em_global_quad_port_a != 0)
771 /* Reset for multiple quad port adapters */
772 if (++em_global_quad_port_a == 4)
773 em_global_quad_port_a = 0;
777 /* XXX disable wol */
780 /* Setup OS specific network interface */
781 em_setup_ifp(adapter);
783 /* Add sysctl tree, must after em_setup_ifp() */
784 em_add_sysctl(adapter);
788 ifpoll_compat_setup(&adapter->npoll,
789 &adapter->sysctl_ctx, adapter->sysctl_tree, device_get_unit(dev),
793 /* Reset the hardware */
794 error = em_reset(adapter);
796 device_printf(dev, "Unable to reset the hardware\n");
800 /* Initialize statistics */
801 em_update_stats(adapter);
803 adapter->hw.mac.get_link_status = 1;
804 em_update_link_status(adapter);
806 /* Do we need workaround for 82544 PCI-X adapter? */
807 if (adapter->hw.bus.type == e1000_bus_type_pcix &&
808 adapter->hw.mac.type == e1000_82544)
809 adapter->pcix_82544 = TRUE;
811 adapter->pcix_82544 = FALSE;
813 if (adapter->pcix_82544) {
815 * 82544 on PCI-X may split one TX segment
816 * into two TX descs, so we double its number
817 * of spare TX desc here.
819 adapter->spare_tx_desc = 2 * EM_TX_SPARE;
821 adapter->spare_tx_desc = EM_TX_SPARE;
823 if (adapter->flags & EM_FLAG_TSO)
824 adapter->spare_tx_desc = EM_TX_SPARE_TSO;
825 adapter->tx_wreg_nsegs = 8;
828 * Keep following relationship between spare_tx_desc, oact_tx_desc
830 * (spare_tx_desc + EM_TX_RESERVED) <=
831 * oact_tx_desc <= EM_TX_OACTIVE_MAX <= tx_int_nsegs
833 adapter->oact_tx_desc = adapter->num_tx_desc / 8;
834 if (adapter->oact_tx_desc > EM_TX_OACTIVE_MAX)
835 adapter->oact_tx_desc = EM_TX_OACTIVE_MAX;
836 if (adapter->oact_tx_desc < adapter->spare_tx_desc + EM_TX_RESERVED)
837 adapter->oact_tx_desc = adapter->spare_tx_desc + EM_TX_RESERVED;
839 adapter->tx_int_nsegs = adapter->num_tx_desc / 16;
840 if (adapter->tx_int_nsegs < adapter->oact_tx_desc)
841 adapter->tx_int_nsegs = adapter->oact_tx_desc;
843 /* Non-AMT based hardware can now take control from firmware */
844 if ((adapter->flags & (EM_FLAG_HAS_MGMT | EM_FLAG_HAS_AMT)) ==
845 EM_FLAG_HAS_MGMT && adapter->hw.mac.type >= e1000_82571)
846 em_get_hw_control(adapter);
849 * Missing Interrupt Following ICR read:
851 * 82571/82572 specification update errata #76
852 * 82573 specification update errata #31
853 * 82574 specification update errata #12
854 * 82583 specification update errata #4
857 if ((adapter->flags & EM_FLAG_SHARED_INTR) &&
858 (adapter->hw.mac.type == e1000_82571 ||
859 adapter->hw.mac.type == e1000_82572 ||
860 adapter->hw.mac.type == e1000_82573 ||
861 adapter->hw.mac.type == e1000_82574 ||
862 adapter->hw.mac.type == e1000_82583))
863 intr_func = em_intr_mask;
865 error = bus_setup_intr(dev, adapter->intr_res, INTR_MPSAFE,
866 intr_func, adapter, &adapter->intr_tag,
869 device_printf(dev, "Failed to register interrupt handler");
870 ether_ifdetach(&adapter->arpcom.ac_if);
874 ifq_set_cpuid(&ifp->if_snd, rman_get_cpuid(adapter->intr_res));
882 em_detach(device_t dev)
884 struct adapter *adapter = device_get_softc(dev);
886 if (device_is_attached(dev)) {
887 struct ifnet *ifp = &adapter->arpcom.ac_if;
889 lwkt_serialize_enter(ifp->if_serializer);
893 e1000_phy_hw_reset(&adapter->hw);
895 em_rel_mgmt(adapter);
896 em_rel_hw_control(adapter);
899 E1000_WRITE_REG(&adapter->hw, E1000_WUC,
901 E1000_WRITE_REG(&adapter->hw, E1000_WUFC, adapter->wol);
905 bus_teardown_intr(dev, adapter->intr_res, adapter->intr_tag);
907 lwkt_serialize_exit(ifp->if_serializer);
910 } else if (adapter->memory != NULL) {
911 em_rel_hw_control(adapter);
913 bus_generic_detach(dev);
915 em_free_pci_res(adapter);
917 em_destroy_tx_ring(adapter, adapter->num_tx_desc);
918 em_destroy_rx_ring(adapter, adapter->num_rx_desc);
920 /* Free Transmit Descriptor ring */
921 if (adapter->tx_desc_base)
922 em_dma_free(adapter, &adapter->txdma);
924 /* Free Receive Descriptor ring */
925 if (adapter->rx_desc_base)
926 em_dma_free(adapter, &adapter->rxdma);
928 /* Free top level busdma tag */
929 if (adapter->parent_dtag != NULL)
930 bus_dma_tag_destroy(adapter->parent_dtag);
932 /* Free sysctl tree */
933 if (adapter->sysctl_tree != NULL)
934 sysctl_ctx_free(&adapter->sysctl_ctx);
936 if (adapter->mta != NULL)
937 kfree(adapter->mta, M_DEVBUF);
943 em_shutdown(device_t dev)
945 return em_suspend(dev);
949 em_suspend(device_t dev)
951 struct adapter *adapter = device_get_softc(dev);
952 struct ifnet *ifp = &adapter->arpcom.ac_if;
954 lwkt_serialize_enter(ifp->if_serializer);
958 em_rel_mgmt(adapter);
959 em_rel_hw_control(adapter);
962 E1000_WRITE_REG(&adapter->hw, E1000_WUC, E1000_WUC_PME_EN);
963 E1000_WRITE_REG(&adapter->hw, E1000_WUFC, adapter->wol);
967 lwkt_serialize_exit(ifp->if_serializer);
969 return bus_generic_suspend(dev);
973 em_resume(device_t dev)
975 struct adapter *adapter = device_get_softc(dev);
976 struct ifnet *ifp = &adapter->arpcom.ac_if;
978 lwkt_serialize_enter(ifp->if_serializer);
981 em_get_mgmt(adapter);
984 lwkt_serialize_exit(ifp->if_serializer);
986 return bus_generic_resume(dev);
990 em_start(struct ifnet *ifp, struct ifaltq_subque *ifsq)
992 struct adapter *adapter = ifp->if_softc;
994 int idx = -1, nsegs = 0;
996 ASSERT_ALTQ_SQ_DEFAULT(ifp, ifsq);
997 ASSERT_SERIALIZED(ifp->if_serializer);
999 if ((ifp->if_flags & IFF_RUNNING) == 0 || ifq_is_oactive(&ifp->if_snd))
1002 if (!adapter->link_active) {
1003 ifq_purge(&ifp->if_snd);
1007 while (!ifq_is_empty(&ifp->if_snd)) {
1008 /* Now do we at least have a minimal? */
1009 if (EM_IS_OACTIVE(adapter)) {
1010 em_tx_collect(adapter);
1011 if (EM_IS_OACTIVE(adapter)) {
1012 ifq_set_oactive(&ifp->if_snd);
1013 adapter->no_tx_desc_avail1++;
1019 m_head = ifq_dequeue(&ifp->if_snd, NULL);
1023 if (em_encap(adapter, &m_head, &nsegs, &idx)) {
1025 em_tx_collect(adapter);
1029 if (nsegs >= adapter->tx_wreg_nsegs && idx >= 0) {
1030 E1000_WRITE_REG(&adapter->hw, E1000_TDT(0), idx);
1035 /* Send a copy of the frame to the BPF listener */
1036 ETHER_BPF_MTAP(ifp, m_head);
1038 /* Set timeout in case hardware has problems transmitting. */
1039 ifp->if_timer = EM_TX_TIMEOUT;
1042 E1000_WRITE_REG(&adapter->hw, E1000_TDT(0), idx);
1046 em_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
1048 struct adapter *adapter = ifp->if_softc;
1049 struct ifreq *ifr = (struct ifreq *)data;
1050 uint16_t eeprom_data = 0;
1051 int max_frame_size, mask, reinit;
1054 ASSERT_SERIALIZED(ifp->if_serializer);
1058 switch (adapter->hw.mac.type) {
1061 * 82573 only supports jumbo frames
1062 * if ASPM is disabled.
1064 e1000_read_nvm(&adapter->hw,
1065 NVM_INIT_3GIO_3, 1, &eeprom_data);
1066 if (eeprom_data & NVM_WORD1A_ASPM_MASK) {
1067 max_frame_size = ETHER_MAX_LEN;
1072 /* Limit Jumbo Frame size */
1076 case e1000_ich10lan:
1080 case e1000_80003es2lan:
1081 max_frame_size = 9234;
1085 max_frame_size = 4096;
1088 /* Adapters that do not support jumbo frames */
1091 max_frame_size = ETHER_MAX_LEN;
1095 max_frame_size = MAX_JUMBO_FRAME_SIZE;
1098 if (ifr->ifr_mtu > max_frame_size - ETHER_HDR_LEN -
1104 ifp->if_mtu = ifr->ifr_mtu;
1105 adapter->max_frame_size =
1106 ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
1108 if (ifp->if_flags & IFF_RUNNING)
1113 if (ifp->if_flags & IFF_UP) {
1114 if ((ifp->if_flags & IFF_RUNNING)) {
1115 if ((ifp->if_flags ^ adapter->if_flags) &
1116 (IFF_PROMISC | IFF_ALLMULTI)) {
1117 em_disable_promisc(adapter);
1118 em_set_promisc(adapter);
1123 } else if (ifp->if_flags & IFF_RUNNING) {
1126 adapter->if_flags = ifp->if_flags;
1131 if (ifp->if_flags & IFF_RUNNING) {
1132 em_disable_intr(adapter);
1133 em_set_multi(adapter);
1134 if (adapter->hw.mac.type == e1000_82542 &&
1135 adapter->hw.revision_id == E1000_REVISION_2)
1136 em_init_rx_unit(adapter);
1137 #ifdef IFPOLL_ENABLE
1138 if (!(ifp->if_flags & IFF_NPOLLING))
1140 em_enable_intr(adapter);
1145 /* Check SOL/IDER usage */
1146 if (e1000_check_reset_block(&adapter->hw)) {
1147 device_printf(adapter->dev, "Media change is"
1148 " blocked due to SOL/IDER session.\n");
1154 error = ifmedia_ioctl(ifp, ifr, &adapter->media, command);
1159 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
1160 if (mask & IFCAP_RXCSUM) {
1161 ifp->if_capenable ^= IFCAP_RXCSUM;
1164 if (mask & IFCAP_TXCSUM) {
1165 ifp->if_capenable ^= IFCAP_TXCSUM;
1166 if (ifp->if_capenable & IFCAP_TXCSUM)
1167 ifp->if_hwassist |= EM_CSUM_FEATURES;
1169 ifp->if_hwassist &= ~EM_CSUM_FEATURES;
1171 if (mask & IFCAP_TSO) {
1172 ifp->if_capenable ^= IFCAP_TSO;
1173 if (ifp->if_capenable & IFCAP_TSO)
1174 ifp->if_hwassist |= CSUM_TSO;
1176 ifp->if_hwassist &= ~CSUM_TSO;
1178 if (mask & IFCAP_VLAN_HWTAGGING) {
1179 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
1182 if (reinit && (ifp->if_flags & IFF_RUNNING))
1187 error = ether_ioctl(ifp, command, data);
1194 em_watchdog(struct ifnet *ifp)
1196 struct adapter *adapter = ifp->if_softc;
1198 ASSERT_SERIALIZED(ifp->if_serializer);
1201 * The timer is set to 5 every time start queues a packet.
1202 * Then txeof keeps resetting it as long as it cleans at
1203 * least one descriptor.
1204 * Finally, anytime all descriptors are clean the timer is
1208 if (E1000_READ_REG(&adapter->hw, E1000_TDT(0)) ==
1209 E1000_READ_REG(&adapter->hw, E1000_TDH(0))) {
1211 * If we reach here, all TX jobs are completed and
1212 * the TX engine should have been idled for some time.
1213 * We don't need to call if_devstart() here.
1215 ifq_clr_oactive(&ifp->if_snd);
1221 * If we are in this routine because of pause frames, then
1222 * don't reset the hardware.
1224 if (E1000_READ_REG(&adapter->hw, E1000_STATUS) &
1225 E1000_STATUS_TXOFF) {
1226 ifp->if_timer = EM_TX_TIMEOUT;
1230 if (e1000_check_for_link(&adapter->hw) == 0)
1231 if_printf(ifp, "watchdog timeout -- resetting\n");
1234 adapter->watchdog_events++;
1238 if (!ifq_is_empty(&ifp->if_snd))
1245 struct adapter *adapter = xsc;
1246 struct ifnet *ifp = &adapter->arpcom.ac_if;
1247 device_t dev = adapter->dev;
1250 ASSERT_SERIALIZED(ifp->if_serializer);
1255 * Packet Buffer Allocation (PBA)
1256 * Writing PBA sets the receive portion of the buffer
1257 * the remainder is used for the transmit buffer.
1259 * Devices before the 82547 had a Packet Buffer of 64K.
1260 * Default allocation: PBA=48K for Rx, leaving 16K for Tx.
1261 * After the 82547 the buffer was reduced to 40K.
1262 * Default allocation: PBA=30K for Rx, leaving 10K for Tx.
1263 * Note: default does not leave enough room for Jumbo Frame >10k.
1265 switch (adapter->hw.mac.type) {
1267 case e1000_82547_rev_2: /* 82547: Total Packet Buffer is 40K */
1268 if (adapter->max_frame_size > 8192)
1269 pba = E1000_PBA_22K; /* 22K for Rx, 18K for Tx */
1271 pba = E1000_PBA_30K; /* 30K for Rx, 10K for Tx */
1272 adapter->tx_fifo_head = 0;
1273 adapter->tx_head_addr = pba << EM_TX_HEAD_ADDR_SHIFT;
1274 adapter->tx_fifo_size =
1275 (E1000_PBA_40K - pba) << EM_PBA_BYTES_SHIFT;
1278 /* Total Packet Buffer on these is 48K */
1281 case e1000_80003es2lan:
1282 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
1285 case e1000_82573: /* 82573: Total Packet Buffer is 32K */
1286 pba = E1000_PBA_12K; /* 12K for Rx, 20K for Tx */
1291 pba = E1000_PBA_20K; /* 20K for Rx, 20K for Tx */
1299 case e1000_ich10lan:
1300 #define E1000_PBA_10K 0x000A
1301 pba = E1000_PBA_10K;
1306 pba = E1000_PBA_26K;
1310 /* Devices before 82547 had a Packet Buffer of 64K. */
1311 if (adapter->max_frame_size > 8192)
1312 pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */
1314 pba = E1000_PBA_48K; /* 48K for Rx, 16K for Tx */
1316 E1000_WRITE_REG(&adapter->hw, E1000_PBA, pba);
1318 /* Get the latest mac address, User can use a LAA */
1319 bcopy(IF_LLADDR(ifp), adapter->hw.mac.addr, ETHER_ADDR_LEN);
1321 /* Put the address into the Receive Address Array */
1322 e1000_rar_set(&adapter->hw, adapter->hw.mac.addr, 0);
1325 * With the 82571 adapter, RAR[0] may be overwritten
1326 * when the other port is reset, we make a duplicate
1327 * in RAR[14] for that eventuality, this assures
1328 * the interface continues to function.
1330 if (adapter->hw.mac.type == e1000_82571) {
1331 e1000_set_laa_state_82571(&adapter->hw, TRUE);
1332 e1000_rar_set(&adapter->hw, adapter->hw.mac.addr,
1333 E1000_RAR_ENTRIES - 1);
1336 /* Reset the hardware */
1337 if (em_reset(adapter)) {
1338 device_printf(dev, "Unable to reset the hardware\n");
1339 /* XXX em_stop()? */
1342 em_update_link_status(adapter);
1344 /* Setup VLAN support, basic and offload if available */
1345 E1000_WRITE_REG(&adapter->hw, E1000_VET, ETHERTYPE_VLAN);
1347 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) {
1350 ctrl = E1000_READ_REG(&adapter->hw, E1000_CTRL);
1351 ctrl |= E1000_CTRL_VME;
1352 E1000_WRITE_REG(&adapter->hw, E1000_CTRL, ctrl);
1355 /* Configure for OS presence */
1356 em_get_mgmt(adapter);
1358 /* Prepare transmit descriptors and buffers */
1359 em_init_tx_ring(adapter);
1360 em_init_tx_unit(adapter);
1362 /* Setup Multicast table */
1363 em_set_multi(adapter);
1365 /* Prepare receive descriptors and buffers */
1366 if (em_init_rx_ring(adapter)) {
1367 device_printf(dev, "Could not setup receive structures\n");
1371 em_init_rx_unit(adapter);
1373 /* Don't lose promiscuous settings */
1374 em_set_promisc(adapter);
1376 ifp->if_flags |= IFF_RUNNING;
1377 ifq_clr_oactive(&ifp->if_snd);
1379 callout_reset(&adapter->timer, hz, em_timer, adapter);
1380 e1000_clear_hw_cntrs_base_generic(&adapter->hw);
1382 /* MSI/X configuration for 82574 */
1383 if (adapter->hw.mac.type == e1000_82574) {
1386 tmp = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT);
1387 tmp |= E1000_CTRL_EXT_PBA_CLR;
1388 E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT, tmp);
1391 * Set the IVAR - interrupt vector routing.
1392 * Each nibble represents a vector, high bit
1393 * is enable, other 3 bits are the MSIX table
1394 * entry, we map RXQ0 to 0, TXQ0 to 1, and
1395 * Link (other) to 2, hence the magic number.
1397 E1000_WRITE_REG(&adapter->hw, E1000_IVAR, 0x800A0908);
1400 #ifdef IFPOLL_ENABLE
1402 * Only enable interrupts if we are not polling, make sure
1403 * they are off otherwise.
1405 if (ifp->if_flags & IFF_NPOLLING)
1406 em_disable_intr(adapter);
1408 #endif /* IFPOLL_ENABLE */
1409 em_enable_intr(adapter);
1411 /* AMT based hardware can now take control from firmware */
1412 if ((adapter->flags & (EM_FLAG_HAS_MGMT | EM_FLAG_HAS_AMT)) ==
1413 (EM_FLAG_HAS_MGMT | EM_FLAG_HAS_AMT) &&
1414 adapter->hw.mac.type >= e1000_82571)
1415 em_get_hw_control(adapter);
1417 /* Don't reset the phy next time init gets called */
1418 adapter->hw.phy.reset_disable = TRUE;
1421 #ifdef IFPOLL_ENABLE
1424 em_npoll_compat(struct ifnet *ifp, void *arg __unused, int count)
1426 struct adapter *adapter = ifp->if_softc;
1428 ASSERT_SERIALIZED(ifp->if_serializer);
1430 if (adapter->npoll.ifpc_stcount-- == 0) {
1433 adapter->npoll.ifpc_stcount = adapter->npoll.ifpc_stfrac;
1435 reg_icr = E1000_READ_REG(&adapter->hw, E1000_ICR);
1436 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
1437 callout_stop(&adapter->timer);
1438 adapter->hw.mac.get_link_status = 1;
1439 em_update_link_status(adapter);
1440 callout_reset(&adapter->timer, hz, em_timer, adapter);
1444 em_rxeof(adapter, count);
1447 if (!ifq_is_empty(&ifp->if_snd))
1452 em_npoll(struct ifnet *ifp, struct ifpoll_info *info)
1454 struct adapter *adapter = ifp->if_softc;
1456 ASSERT_SERIALIZED(ifp->if_serializer);
1459 int cpuid = adapter->npoll.ifpc_cpuid;
1461 info->ifpi_rx[cpuid].poll_func = em_npoll_compat;
1462 info->ifpi_rx[cpuid].arg = NULL;
1463 info->ifpi_rx[cpuid].serializer = ifp->if_serializer;
1465 if (ifp->if_flags & IFF_RUNNING)
1466 em_disable_intr(adapter);
1467 ifq_set_cpuid(&ifp->if_snd, cpuid);
1469 if (ifp->if_flags & IFF_RUNNING)
1470 em_enable_intr(adapter);
1471 ifq_set_cpuid(&ifp->if_snd, rman_get_cpuid(adapter->intr_res));
1475 #endif /* IFPOLL_ENABLE */
1480 em_intr_body(xsc, TRUE);
1484 em_intr_body(struct adapter *adapter, boolean_t chk_asserted)
1486 struct ifnet *ifp = &adapter->arpcom.ac_if;
1490 ASSERT_SERIALIZED(ifp->if_serializer);
1492 reg_icr = E1000_READ_REG(&adapter->hw, E1000_ICR);
1495 ((adapter->hw.mac.type >= e1000_82571 &&
1496 (reg_icr & E1000_ICR_INT_ASSERTED) == 0) ||
1503 * XXX: some laptops trigger several spurious interrupts
1504 * on em(4) when in the resume cycle. The ICR register
1505 * reports all-ones value in this case. Processing such
1506 * interrupts would lead to a freeze. I don't know why.
1508 if (reg_icr == 0xffffffff) {
1513 if (ifp->if_flags & IFF_RUNNING) {
1515 (E1000_ICR_RXT0 | E1000_ICR_RXDMT0 | E1000_ICR_RXO))
1516 em_rxeof(adapter, -1);
1517 if (reg_icr & E1000_ICR_TXDW) {
1519 if (!ifq_is_empty(&ifp->if_snd))
1524 /* Link status change */
1525 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
1526 callout_stop(&adapter->timer);
1527 adapter->hw.mac.get_link_status = 1;
1528 em_update_link_status(adapter);
1530 /* Deal with TX cruft when link lost */
1531 em_tx_purge(adapter);
1533 callout_reset(&adapter->timer, hz, em_timer, adapter);
1536 if (reg_icr & E1000_ICR_RXO)
1537 adapter->rx_overruns++;
1543 em_intr_mask(void *xsc)
1545 struct adapter *adapter = xsc;
1547 E1000_WRITE_REG(&adapter->hw, E1000_IMC, 0xffffffff);
1550 * ICR.INT_ASSERTED bit will never be set if IMS is 0,
1551 * so don't check it.
1553 em_intr_body(adapter, FALSE);
1554 E1000_WRITE_REG(&adapter->hw, E1000_IMS, IMS_ENABLE_MASK);
1558 em_media_status(struct ifnet *ifp, struct ifmediareq *ifmr)
1560 struct adapter *adapter = ifp->if_softc;
1561 u_char fiber_type = IFM_1000_SX;
1563 ASSERT_SERIALIZED(ifp->if_serializer);
1565 em_update_link_status(adapter);
1567 ifmr->ifm_status = IFM_AVALID;
1568 ifmr->ifm_active = IFM_ETHER;
1570 if (!adapter->link_active)
1573 ifmr->ifm_status |= IFM_ACTIVE;
1575 if (adapter->hw.phy.media_type == e1000_media_type_fiber ||
1576 adapter->hw.phy.media_type == e1000_media_type_internal_serdes) {
1577 if (adapter->hw.mac.type == e1000_82545)
1578 fiber_type = IFM_1000_LX;
1579 ifmr->ifm_active |= fiber_type | IFM_FDX;
1581 switch (adapter->link_speed) {
1583 ifmr->ifm_active |= IFM_10_T;
1586 ifmr->ifm_active |= IFM_100_TX;
1590 ifmr->ifm_active |= IFM_1000_T;
1593 if (adapter->link_duplex == FULL_DUPLEX)
1594 ifmr->ifm_active |= IFM_FDX;
1596 ifmr->ifm_active |= IFM_HDX;
1601 em_media_change(struct ifnet *ifp)
1603 struct adapter *adapter = ifp->if_softc;
1604 struct ifmedia *ifm = &adapter->media;
1606 ASSERT_SERIALIZED(ifp->if_serializer);
1608 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
1611 switch (IFM_SUBTYPE(ifm->ifm_media)) {
1613 adapter->hw.mac.autoneg = DO_AUTO_NEG;
1614 adapter->hw.phy.autoneg_advertised = AUTONEG_ADV_DEFAULT;
1620 adapter->hw.mac.autoneg = DO_AUTO_NEG;
1621 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
1625 adapter->hw.mac.autoneg = FALSE;
1626 adapter->hw.phy.autoneg_advertised = 0;
1627 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
1628 adapter->hw.mac.forced_speed_duplex = ADVERTISE_100_FULL;
1630 adapter->hw.mac.forced_speed_duplex = ADVERTISE_100_HALF;
1634 adapter->hw.mac.autoneg = FALSE;
1635 adapter->hw.phy.autoneg_advertised = 0;
1636 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
1637 adapter->hw.mac.forced_speed_duplex = ADVERTISE_10_FULL;
1639 adapter->hw.mac.forced_speed_duplex = ADVERTISE_10_HALF;
1643 if_printf(ifp, "Unsupported media type\n");
1648 * As the speed/duplex settings my have changed we need to
1651 adapter->hw.phy.reset_disable = FALSE;
1659 em_encap(struct adapter *adapter, struct mbuf **m_headp,
1660 int *segs_used, int *idx)
1662 bus_dma_segment_t segs[EM_MAX_SCATTER];
1664 struct em_buffer *tx_buffer, *tx_buffer_mapped;
1665 struct e1000_tx_desc *ctxd = NULL;
1666 struct mbuf *m_head = *m_headp;
1667 uint32_t txd_upper, txd_lower, txd_used, cmd = 0;
1668 int maxsegs, nsegs, i, j, first, last = 0, error;
1670 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) {
1671 error = em_tso_pullup(adapter, m_headp);
1677 txd_upper = txd_lower = 0;
1681 * Capture the first descriptor index, this descriptor
1682 * will have the index of the EOP which is the only one
1683 * that now gets a DONE bit writeback.
1685 first = adapter->next_avail_tx_desc;
1686 tx_buffer = &adapter->tx_buffer_area[first];
1687 tx_buffer_mapped = tx_buffer;
1688 map = tx_buffer->map;
1690 maxsegs = adapter->num_tx_desc_avail - EM_TX_RESERVED;
1691 KASSERT(maxsegs >= adapter->spare_tx_desc,
1692 ("not enough spare TX desc"));
1693 if (adapter->pcix_82544) {
1694 /* Half it; see the comment in em_attach() */
1697 if (maxsegs > EM_MAX_SCATTER)
1698 maxsegs = EM_MAX_SCATTER;
1700 error = bus_dmamap_load_mbuf_defrag(adapter->txtag, map, m_headp,
1701 segs, maxsegs, &nsegs, BUS_DMA_NOWAIT);
1703 if (error == ENOBUFS)
1704 adapter->mbuf_alloc_failed++;
1706 adapter->no_tx_dma_setup++;
1712 bus_dmamap_sync(adapter->txtag, map, BUS_DMASYNC_PREWRITE);
1715 adapter->tx_nsegs += nsegs;
1716 *segs_used += nsegs;
1718 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) {
1719 /* TSO will consume one TX desc */
1720 i = em_tso_setup(adapter, m_head, &txd_upper, &txd_lower);
1721 adapter->tx_nsegs += i;
1723 } else if (m_head->m_pkthdr.csum_flags & EM_CSUM_FEATURES) {
1724 /* TX csum offloading will consume one TX desc */
1725 i = em_txcsum(adapter, m_head, &txd_upper, &txd_lower);
1726 adapter->tx_nsegs += i;
1729 i = adapter->next_avail_tx_desc;
1731 /* Set up our transmit descriptors */
1732 for (j = 0; j < nsegs; j++) {
1733 /* If adapter is 82544 and on PCIX bus */
1734 if(adapter->pcix_82544) {
1735 DESC_ARRAY desc_array;
1736 uint32_t array_elements, counter;
1739 * Check the Address and Length combination and
1740 * split the data accordingly
1742 array_elements = em_82544_fill_desc(segs[j].ds_addr,
1743 segs[j].ds_len, &desc_array);
1744 for (counter = 0; counter < array_elements; counter++) {
1745 KKASSERT(txd_used < adapter->num_tx_desc_avail);
1747 tx_buffer = &adapter->tx_buffer_area[i];
1748 ctxd = &adapter->tx_desc_base[i];
1750 ctxd->buffer_addr = htole64(
1751 desc_array.descriptor[counter].address);
1752 ctxd->lower.data = htole32(
1753 E1000_TXD_CMD_IFCS | txd_lower |
1754 desc_array.descriptor[counter].length);
1755 ctxd->upper.data = htole32(txd_upper);
1758 if (++i == adapter->num_tx_desc)
1764 tx_buffer = &adapter->tx_buffer_area[i];
1765 ctxd = &adapter->tx_desc_base[i];
1767 ctxd->buffer_addr = htole64(segs[j].ds_addr);
1768 ctxd->lower.data = htole32(E1000_TXD_CMD_IFCS |
1769 txd_lower | segs[j].ds_len);
1770 ctxd->upper.data = htole32(txd_upper);
1773 if (++i == adapter->num_tx_desc)
1778 adapter->next_avail_tx_desc = i;
1779 if (adapter->pcix_82544) {
1780 KKASSERT(adapter->num_tx_desc_avail > txd_used);
1781 adapter->num_tx_desc_avail -= txd_used;
1783 KKASSERT(adapter->num_tx_desc_avail > nsegs);
1784 adapter->num_tx_desc_avail -= nsegs;
1787 /* Handle VLAN tag */
1788 if (m_head->m_flags & M_VLANTAG) {
1789 /* Set the vlan id. */
1790 ctxd->upper.fields.special =
1791 htole16(m_head->m_pkthdr.ether_vlantag);
1793 /* Tell hardware to add tag */
1794 ctxd->lower.data |= htole32(E1000_TXD_CMD_VLE);
1797 tx_buffer->m_head = m_head;
1798 tx_buffer_mapped->map = tx_buffer->map;
1799 tx_buffer->map = map;
1801 if (adapter->tx_nsegs >= adapter->tx_int_nsegs) {
1802 adapter->tx_nsegs = 0;
1805 * Report Status (RS) is turned on
1806 * every tx_int_nsegs descriptors.
1808 cmd = E1000_TXD_CMD_RS;
1811 * Keep track of the descriptor, which will
1812 * be written back by hardware.
1814 adapter->tx_dd[adapter->tx_dd_tail] = last;
1815 EM_INC_TXDD_IDX(adapter->tx_dd_tail);
1816 KKASSERT(adapter->tx_dd_tail != adapter->tx_dd_head);
1820 * Last Descriptor of Packet needs End Of Packet (EOP)
1822 ctxd->lower.data |= htole32(E1000_TXD_CMD_EOP | cmd);
1824 if (adapter->hw.mac.type == e1000_82547) {
1826 * Advance the Transmit Descriptor Tail (TDT), this tells the
1827 * E1000 that this frame is available to transmit.
1829 if (adapter->link_duplex == HALF_DUPLEX) {
1830 em_82547_move_tail_serialized(adapter);
1832 E1000_WRITE_REG(&adapter->hw, E1000_TDT(0), i);
1833 em_82547_update_fifo_head(adapter,
1834 m_head->m_pkthdr.len);
1838 * Defer TDT updating, until enough descriptors are setup
1846 * 82547 workaround to avoid controller hang in half-duplex environment.
1847 * The workaround is to avoid queuing a large packet that would span
1848 * the internal Tx FIFO ring boundary. We need to reset the FIFO pointers
1849 * in this case. We do that only when FIFO is quiescent.
1852 em_82547_move_tail_serialized(struct adapter *adapter)
1854 struct e1000_tx_desc *tx_desc;
1855 uint16_t hw_tdt, sw_tdt, length = 0;
1858 ASSERT_SERIALIZED(adapter->arpcom.ac_if.if_serializer);
1860 hw_tdt = E1000_READ_REG(&adapter->hw, E1000_TDT(0));
1861 sw_tdt = adapter->next_avail_tx_desc;
1863 while (hw_tdt != sw_tdt) {
1864 tx_desc = &adapter->tx_desc_base[hw_tdt];
1865 length += tx_desc->lower.flags.length;
1866 eop = tx_desc->lower.data & E1000_TXD_CMD_EOP;
1867 if (++hw_tdt == adapter->num_tx_desc)
1871 if (em_82547_fifo_workaround(adapter, length)) {
1872 adapter->tx_fifo_wrk_cnt++;
1873 callout_reset(&adapter->tx_fifo_timer, 1,
1874 em_82547_move_tail, adapter);
1877 E1000_WRITE_REG(&adapter->hw, E1000_TDT(0), hw_tdt);
1878 em_82547_update_fifo_head(adapter, length);
1885 em_82547_move_tail(void *xsc)
1887 struct adapter *adapter = xsc;
1888 struct ifnet *ifp = &adapter->arpcom.ac_if;
1890 lwkt_serialize_enter(ifp->if_serializer);
1891 em_82547_move_tail_serialized(adapter);
1892 lwkt_serialize_exit(ifp->if_serializer);
1896 em_82547_fifo_workaround(struct adapter *adapter, int len)
1898 int fifo_space, fifo_pkt_len;
1900 fifo_pkt_len = roundup2(len + EM_FIFO_HDR, EM_FIFO_HDR);
1902 if (adapter->link_duplex == HALF_DUPLEX) {
1903 fifo_space = adapter->tx_fifo_size - adapter->tx_fifo_head;
1905 if (fifo_pkt_len >= (EM_82547_PKT_THRESH + fifo_space)) {
1906 if (em_82547_tx_fifo_reset(adapter))
1916 em_82547_update_fifo_head(struct adapter *adapter, int len)
1918 int fifo_pkt_len = roundup2(len + EM_FIFO_HDR, EM_FIFO_HDR);
1920 /* tx_fifo_head is always 16 byte aligned */
1921 adapter->tx_fifo_head += fifo_pkt_len;
1922 if (adapter->tx_fifo_head >= adapter->tx_fifo_size)
1923 adapter->tx_fifo_head -= adapter->tx_fifo_size;
1927 em_82547_tx_fifo_reset(struct adapter *adapter)
1931 if ((E1000_READ_REG(&adapter->hw, E1000_TDT(0)) ==
1932 E1000_READ_REG(&adapter->hw, E1000_TDH(0))) &&
1933 (E1000_READ_REG(&adapter->hw, E1000_TDFT) ==
1934 E1000_READ_REG(&adapter->hw, E1000_TDFH)) &&
1935 (E1000_READ_REG(&adapter->hw, E1000_TDFTS) ==
1936 E1000_READ_REG(&adapter->hw, E1000_TDFHS)) &&
1937 (E1000_READ_REG(&adapter->hw, E1000_TDFPC) == 0)) {
1938 /* Disable TX unit */
1939 tctl = E1000_READ_REG(&adapter->hw, E1000_TCTL);
1940 E1000_WRITE_REG(&adapter->hw, E1000_TCTL,
1941 tctl & ~E1000_TCTL_EN);
1943 /* Reset FIFO pointers */
1944 E1000_WRITE_REG(&adapter->hw, E1000_TDFT,
1945 adapter->tx_head_addr);
1946 E1000_WRITE_REG(&adapter->hw, E1000_TDFH,
1947 adapter->tx_head_addr);
1948 E1000_WRITE_REG(&adapter->hw, E1000_TDFTS,
1949 adapter->tx_head_addr);
1950 E1000_WRITE_REG(&adapter->hw, E1000_TDFHS,
1951 adapter->tx_head_addr);
1953 /* Re-enable TX unit */
1954 E1000_WRITE_REG(&adapter->hw, E1000_TCTL, tctl);
1955 E1000_WRITE_FLUSH(&adapter->hw);
1957 adapter->tx_fifo_head = 0;
1958 adapter->tx_fifo_reset_cnt++;
1967 em_set_promisc(struct adapter *adapter)
1969 struct ifnet *ifp = &adapter->arpcom.ac_if;
1972 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL);
1974 if (ifp->if_flags & IFF_PROMISC) {
1975 reg_rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
1976 /* Turn this on if you want to see bad packets */
1978 reg_rctl |= E1000_RCTL_SBP;
1979 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl);
1980 } else if (ifp->if_flags & IFF_ALLMULTI) {
1981 reg_rctl |= E1000_RCTL_MPE;
1982 reg_rctl &= ~E1000_RCTL_UPE;
1983 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl);
1988 em_disable_promisc(struct adapter *adapter)
1992 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL);
1994 reg_rctl &= ~E1000_RCTL_UPE;
1995 reg_rctl &= ~E1000_RCTL_MPE;
1996 reg_rctl &= ~E1000_RCTL_SBP;
1997 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl);
2001 em_set_multi(struct adapter *adapter)
2003 struct ifnet *ifp = &adapter->arpcom.ac_if;
2004 struct ifmultiaddr *ifma;
2005 uint32_t reg_rctl = 0;
2010 bzero(mta, ETH_ADDR_LEN * MAX_NUM_MULTICAST_ADDRESSES);
2012 if (adapter->hw.mac.type == e1000_82542 &&
2013 adapter->hw.revision_id == E1000_REVISION_2) {
2014 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL);
2015 if (adapter->hw.bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE)
2016 e1000_pci_clear_mwi(&adapter->hw);
2017 reg_rctl |= E1000_RCTL_RST;
2018 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl);
2022 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
2023 if (ifma->ifma_addr->sa_family != AF_LINK)
2026 if (mcnt == MAX_NUM_MULTICAST_ADDRESSES)
2029 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
2030 &mta[mcnt * ETHER_ADDR_LEN], ETHER_ADDR_LEN);
2034 if (mcnt >= MAX_NUM_MULTICAST_ADDRESSES) {
2035 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL);
2036 reg_rctl |= E1000_RCTL_MPE;
2037 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl);
2039 e1000_update_mc_addr_list(&adapter->hw, mta, mcnt);
2042 if (adapter->hw.mac.type == e1000_82542 &&
2043 adapter->hw.revision_id == E1000_REVISION_2) {
2044 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL);
2045 reg_rctl &= ~E1000_RCTL_RST;
2046 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl);
2048 if (adapter->hw.bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE)
2049 e1000_pci_set_mwi(&adapter->hw);
2054 * This routine checks for link status and updates statistics.
2059 struct adapter *adapter = xsc;
2060 struct ifnet *ifp = &adapter->arpcom.ac_if;
2062 lwkt_serialize_enter(ifp->if_serializer);
2064 em_update_link_status(adapter);
2065 em_update_stats(adapter);
2067 /* Reset LAA into RAR[0] on 82571 */
2068 if (e1000_get_laa_state_82571(&adapter->hw) == TRUE)
2069 e1000_rar_set(&adapter->hw, adapter->hw.mac.addr, 0);
2071 if (em_display_debug_stats && (ifp->if_flags & IFF_RUNNING))
2072 em_print_hw_stats(adapter);
2074 em_smartspeed(adapter);
2076 callout_reset(&adapter->timer, hz, em_timer, adapter);
2078 lwkt_serialize_exit(ifp->if_serializer);
2082 em_update_link_status(struct adapter *adapter)
2084 struct e1000_hw *hw = &adapter->hw;
2085 struct ifnet *ifp = &adapter->arpcom.ac_if;
2086 device_t dev = adapter->dev;
2087 uint32_t link_check = 0;
2089 /* Get the cached link value or read phy for real */
2090 switch (hw->phy.media_type) {
2091 case e1000_media_type_copper:
2092 if (hw->mac.get_link_status) {
2093 /* Do the work to read phy */
2094 e1000_check_for_link(hw);
2095 link_check = !hw->mac.get_link_status;
2096 if (link_check) /* ESB2 fix */
2097 e1000_cfg_on_link_up(hw);
2103 case e1000_media_type_fiber:
2104 e1000_check_for_link(hw);
2106 E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU;
2109 case e1000_media_type_internal_serdes:
2110 e1000_check_for_link(hw);
2111 link_check = adapter->hw.mac.serdes_has_link;
2114 case e1000_media_type_unknown:
2119 /* Now check for a transition */
2120 if (link_check && adapter->link_active == 0) {
2121 e1000_get_speed_and_duplex(hw, &adapter->link_speed,
2122 &adapter->link_duplex);
2125 * Check if we should enable/disable SPEED_MODE bit on
2128 if (adapter->link_speed != SPEED_1000 &&
2129 (hw->mac.type == e1000_82571 ||
2130 hw->mac.type == e1000_82572)) {
2133 tarc0 = E1000_READ_REG(hw, E1000_TARC(0));
2134 tarc0 &= ~SPEED_MODE_BIT;
2135 E1000_WRITE_REG(hw, E1000_TARC(0), tarc0);
2138 device_printf(dev, "Link is up %d Mbps %s\n",
2139 adapter->link_speed,
2140 ((adapter->link_duplex == FULL_DUPLEX) ?
2141 "Full Duplex" : "Half Duplex"));
2143 adapter->link_active = 1;
2144 adapter->smartspeed = 0;
2145 ifp->if_baudrate = adapter->link_speed * 1000000;
2146 ifp->if_link_state = LINK_STATE_UP;
2147 if_link_state_change(ifp);
2148 } else if (!link_check && adapter->link_active == 1) {
2149 ifp->if_baudrate = adapter->link_speed = 0;
2150 adapter->link_duplex = 0;
2152 device_printf(dev, "Link is Down\n");
2153 adapter->link_active = 0;
2155 /* Link down, disable watchdog */
2158 ifp->if_link_state = LINK_STATE_DOWN;
2159 if_link_state_change(ifp);
2164 em_stop(struct adapter *adapter)
2166 struct ifnet *ifp = &adapter->arpcom.ac_if;
2169 ASSERT_SERIALIZED(ifp->if_serializer);
2171 em_disable_intr(adapter);
2173 callout_stop(&adapter->timer);
2174 callout_stop(&adapter->tx_fifo_timer);
2176 ifp->if_flags &= ~IFF_RUNNING;
2177 ifq_clr_oactive(&ifp->if_snd);
2180 e1000_reset_hw(&adapter->hw);
2181 if (adapter->hw.mac.type >= e1000_82544)
2182 E1000_WRITE_REG(&adapter->hw, E1000_WUC, 0);
2184 for (i = 0; i < adapter->num_tx_desc; i++) {
2185 struct em_buffer *tx_buffer = &adapter->tx_buffer_area[i];
2187 if (tx_buffer->m_head != NULL) {
2188 bus_dmamap_unload(adapter->txtag, tx_buffer->map);
2189 m_freem(tx_buffer->m_head);
2190 tx_buffer->m_head = NULL;
2194 for (i = 0; i < adapter->num_rx_desc; i++) {
2195 struct em_buffer *rx_buffer = &adapter->rx_buffer_area[i];
2197 if (rx_buffer->m_head != NULL) {
2198 bus_dmamap_unload(adapter->rxtag, rx_buffer->map);
2199 m_freem(rx_buffer->m_head);
2200 rx_buffer->m_head = NULL;
2204 if (adapter->fmp != NULL)
2205 m_freem(adapter->fmp);
2206 adapter->fmp = NULL;
2207 adapter->lmp = NULL;
2209 adapter->csum_flags = 0;
2210 adapter->csum_lhlen = 0;
2211 adapter->csum_iphlen = 0;
2212 adapter->csum_thlen = 0;
2213 adapter->csum_mss = 0;
2214 adapter->csum_pktlen = 0;
2216 adapter->tx_dd_head = 0;
2217 adapter->tx_dd_tail = 0;
2218 adapter->tx_nsegs = 0;
2222 em_get_hw_info(struct adapter *adapter)
2224 device_t dev = adapter->dev;
2226 /* Save off the information about this board */
2227 adapter->hw.vendor_id = pci_get_vendor(dev);
2228 adapter->hw.device_id = pci_get_device(dev);
2229 adapter->hw.revision_id = pci_get_revid(dev);
2230 adapter->hw.subsystem_vendor_id = pci_get_subvendor(dev);
2231 adapter->hw.subsystem_device_id = pci_get_subdevice(dev);
2233 /* Do Shared Code Init and Setup */
2234 if (e1000_set_mac_type(&adapter->hw))
2240 em_alloc_pci_res(struct adapter *adapter)
2242 device_t dev = adapter->dev;
2244 int val, rid, msi_enable;
2246 /* Enable bus mastering */
2247 pci_enable_busmaster(dev);
2249 adapter->memory_rid = EM_BAR_MEM;
2250 adapter->memory = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
2251 &adapter->memory_rid, RF_ACTIVE);
2252 if (adapter->memory == NULL) {
2253 device_printf(dev, "Unable to allocate bus resource: memory\n");
2256 adapter->osdep.mem_bus_space_tag =
2257 rman_get_bustag(adapter->memory);
2258 adapter->osdep.mem_bus_space_handle =
2259 rman_get_bushandle(adapter->memory);
2261 /* XXX This is quite goofy, it is not actually used */
2262 adapter->hw.hw_addr = (uint8_t *)&adapter->osdep.mem_bus_space_handle;
2264 /* Only older adapters use IO mapping */
2265 if (adapter->hw.mac.type > e1000_82543 &&
2266 adapter->hw.mac.type < e1000_82571) {
2267 /* Figure our where our IO BAR is ? */
2268 for (rid = PCIR_BAR(0); rid < PCIR_CARDBUSCIS;) {
2269 val = pci_read_config(dev, rid, 4);
2270 if (EM_BAR_TYPE(val) == EM_BAR_TYPE_IO) {
2271 adapter->io_rid = rid;
2275 /* check for 64bit BAR */
2276 if (EM_BAR_MEM_TYPE(val) == EM_BAR_MEM_TYPE_64BIT)
2279 if (rid >= PCIR_CARDBUSCIS) {
2280 device_printf(dev, "Unable to locate IO BAR\n");
2283 adapter->ioport = bus_alloc_resource_any(dev, SYS_RES_IOPORT,
2284 &adapter->io_rid, RF_ACTIVE);
2285 if (adapter->ioport == NULL) {
2286 device_printf(dev, "Unable to allocate bus resource: "
2290 adapter->hw.io_base = 0;
2291 adapter->osdep.io_bus_space_tag =
2292 rman_get_bustag(adapter->ioport);
2293 adapter->osdep.io_bus_space_handle =
2294 rman_get_bushandle(adapter->ioport);
2298 * Don't enable MSI-X on 82574, see:
2299 * 82574 specification update errata #15
2301 * Don't enable MSI on PCI/PCI-X chips, see:
2302 * 82540 specification update errata #6
2303 * 82545 specification update errata #4
2305 * Don't enable MSI on 82571/82572, see:
2306 * 82571/82572 specification update errata #63
2308 msi_enable = em_msi_enable;
2310 (!pci_is_pcie(dev) ||
2311 adapter->hw.mac.type == e1000_82571 ||
2312 adapter->hw.mac.type == e1000_82572))
2315 adapter->intr_type = pci_alloc_1intr(dev, msi_enable,
2316 &adapter->intr_rid, &intr_flags);
2318 if (adapter->intr_type == PCI_INTR_TYPE_LEGACY) {
2321 unshared = device_getenv_int(dev, "irq.unshared", 0);
2323 adapter->flags |= EM_FLAG_SHARED_INTR;
2325 device_printf(dev, "IRQ shared\n");
2327 intr_flags &= ~RF_SHAREABLE;
2329 device_printf(dev, "IRQ unshared\n");
2333 adapter->intr_res = bus_alloc_resource_any(dev, SYS_RES_IRQ,
2334 &adapter->intr_rid, intr_flags);
2335 if (adapter->intr_res == NULL) {
2336 device_printf(dev, "Unable to allocate bus resource: "
2341 adapter->hw.bus.pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2);
2342 adapter->hw.back = &adapter->osdep;
2347 em_free_pci_res(struct adapter *adapter)
2349 device_t dev = adapter->dev;
2351 if (adapter->intr_res != NULL) {
2352 bus_release_resource(dev, SYS_RES_IRQ,
2353 adapter->intr_rid, adapter->intr_res);
2356 if (adapter->intr_type == PCI_INTR_TYPE_MSI)
2357 pci_release_msi(dev);
2359 if (adapter->memory != NULL) {
2360 bus_release_resource(dev, SYS_RES_MEMORY,
2361 adapter->memory_rid, adapter->memory);
2364 if (adapter->flash != NULL) {
2365 bus_release_resource(dev, SYS_RES_MEMORY,
2366 adapter->flash_rid, adapter->flash);
2369 if (adapter->ioport != NULL) {
2370 bus_release_resource(dev, SYS_RES_IOPORT,
2371 adapter->io_rid, adapter->ioport);
2376 em_reset(struct adapter *adapter)
2378 device_t dev = adapter->dev;
2379 uint16_t rx_buffer_size;
2381 /* When hardware is reset, fifo_head is also reset */
2382 adapter->tx_fifo_head = 0;
2384 /* Set up smart power down as default off on newer adapters. */
2385 if (!em_smart_pwr_down &&
2386 (adapter->hw.mac.type == e1000_82571 ||
2387 adapter->hw.mac.type == e1000_82572)) {
2388 uint16_t phy_tmp = 0;
2390 /* Speed up time to link by disabling smart power down. */
2391 e1000_read_phy_reg(&adapter->hw,
2392 IGP02E1000_PHY_POWER_MGMT, &phy_tmp);
2393 phy_tmp &= ~IGP02E1000_PM_SPD;
2394 e1000_write_phy_reg(&adapter->hw,
2395 IGP02E1000_PHY_POWER_MGMT, phy_tmp);
2399 * These parameters control the automatic generation (Tx) and
2400 * response (Rx) to Ethernet PAUSE frames.
2401 * - High water mark should allow for at least two frames to be
2402 * received after sending an XOFF.
2403 * - Low water mark works best when it is very near the high water mark.
2404 * This allows the receiver to restart by sending XON when it has
2405 * drained a bit. Here we use an arbitary value of 1500 which will
2406 * restart after one full frame is pulled from the buffer. There
2407 * could be several smaller frames in the buffer and if so they will
2408 * not trigger the XON until their total number reduces the buffer
2410 * - The pause time is fairly large at 1000 x 512ns = 512 usec.
2413 (E1000_READ_REG(&adapter->hw, E1000_PBA) & 0xffff) << 10;
2415 adapter->hw.fc.high_water = rx_buffer_size -
2416 roundup2(adapter->max_frame_size, 1024);
2417 adapter->hw.fc.low_water = adapter->hw.fc.high_water - 1500;
2419 if (adapter->hw.mac.type == e1000_80003es2lan)
2420 adapter->hw.fc.pause_time = 0xFFFF;
2422 adapter->hw.fc.pause_time = EM_FC_PAUSE_TIME;
2424 adapter->hw.fc.send_xon = TRUE;
2426 adapter->hw.fc.requested_mode = e1000_fc_full;
2428 /* Workaround: no TX flow ctrl for PCH */
2429 if (adapter->hw.mac.type == e1000_pchlan)
2430 adapter->hw.fc.requested_mode = e1000_fc_rx_pause;
2432 /* Override - settings for PCH2LAN, ya its magic :) */
2433 if (adapter->hw.mac.type == e1000_pch2lan) {
2434 adapter->hw.fc.high_water = 0x5C20;
2435 adapter->hw.fc.low_water = 0x5048;
2436 adapter->hw.fc.pause_time = 0x0650;
2437 adapter->hw.fc.refresh_time = 0x0400;
2439 /* Jumbos need adjusted PBA */
2440 if (adapter->arpcom.ac_if.if_mtu > ETHERMTU)
2441 E1000_WRITE_REG(&adapter->hw, E1000_PBA, 12);
2443 E1000_WRITE_REG(&adapter->hw, E1000_PBA, 26);
2446 /* Issue a global reset */
2447 e1000_reset_hw(&adapter->hw);
2448 if (adapter->hw.mac.type >= e1000_82544)
2449 E1000_WRITE_REG(&adapter->hw, E1000_WUC, 0);
2450 em_disable_aspm(adapter);
2452 if (e1000_init_hw(&adapter->hw) < 0) {
2453 device_printf(dev, "Hardware Initialization Failed\n");
2457 E1000_WRITE_REG(&adapter->hw, E1000_VET, ETHERTYPE_VLAN);
2458 e1000_get_phy_info(&adapter->hw);
2459 e1000_check_for_link(&adapter->hw);
2465 em_setup_ifp(struct adapter *adapter)
2467 struct ifnet *ifp = &adapter->arpcom.ac_if;
2469 if_initname(ifp, device_get_name(adapter->dev),
2470 device_get_unit(adapter->dev));
2471 ifp->if_softc = adapter;
2472 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
2473 ifp->if_init = em_init;
2474 ifp->if_ioctl = em_ioctl;
2475 ifp->if_start = em_start;
2476 #ifdef IFPOLL_ENABLE
2477 ifp->if_npoll = em_npoll;
2479 ifp->if_watchdog = em_watchdog;
2480 ifq_set_maxlen(&ifp->if_snd, adapter->num_tx_desc - 1);
2481 ifq_set_ready(&ifp->if_snd);
2483 ether_ifattach(ifp, adapter->hw.mac.addr, NULL);
2485 ifp->if_capabilities = IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU;
2486 if (adapter->hw.mac.type >= e1000_82543)
2487 ifp->if_capabilities |= IFCAP_HWCSUM;
2488 if (adapter->flags & EM_FLAG_TSO)
2489 ifp->if_capabilities |= IFCAP_TSO;
2490 ifp->if_capenable = ifp->if_capabilities;
2492 if (ifp->if_capenable & IFCAP_TXCSUM)
2493 ifp->if_hwassist |= EM_CSUM_FEATURES;
2494 if (ifp->if_capenable & IFCAP_TSO)
2495 ifp->if_hwassist |= CSUM_TSO;
2498 * Tell the upper layer(s) we support long frames.
2500 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
2503 * Specify the media types supported by this adapter and register
2504 * callbacks to update media and link information
2506 ifmedia_init(&adapter->media, IFM_IMASK,
2507 em_media_change, em_media_status);
2508 if (adapter->hw.phy.media_type == e1000_media_type_fiber ||
2509 adapter->hw.phy.media_type == e1000_media_type_internal_serdes) {
2510 u_char fiber_type = IFM_1000_SX; /* default type */
2512 if (adapter->hw.mac.type == e1000_82545)
2513 fiber_type = IFM_1000_LX;
2514 ifmedia_add(&adapter->media, IFM_ETHER | fiber_type | IFM_FDX,
2516 ifmedia_add(&adapter->media, IFM_ETHER | fiber_type, 0, NULL);
2518 ifmedia_add(&adapter->media, IFM_ETHER | IFM_10_T, 0, NULL);
2519 ifmedia_add(&adapter->media, IFM_ETHER | IFM_10_T | IFM_FDX,
2521 ifmedia_add(&adapter->media, IFM_ETHER | IFM_100_TX,
2523 ifmedia_add(&adapter->media, IFM_ETHER | IFM_100_TX | IFM_FDX,
2525 if (adapter->hw.phy.type != e1000_phy_ife) {
2526 ifmedia_add(&adapter->media,
2527 IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL);
2528 ifmedia_add(&adapter->media,
2529 IFM_ETHER | IFM_1000_T, 0, NULL);
2532 ifmedia_add(&adapter->media, IFM_ETHER | IFM_AUTO, 0, NULL);
2533 ifmedia_set(&adapter->media, IFM_ETHER | IFM_AUTO);
2538 * Workaround for SmartSpeed on 82541 and 82547 controllers
2541 em_smartspeed(struct adapter *adapter)
2545 if (adapter->link_active || adapter->hw.phy.type != e1000_phy_igp ||
2546 adapter->hw.mac.autoneg == 0 ||
2547 (adapter->hw.phy.autoneg_advertised & ADVERTISE_1000_FULL) == 0)
2550 if (adapter->smartspeed == 0) {
2552 * If Master/Slave config fault is asserted twice,
2553 * we assume back-to-back
2555 e1000_read_phy_reg(&adapter->hw, PHY_1000T_STATUS, &phy_tmp);
2556 if (!(phy_tmp & SR_1000T_MS_CONFIG_FAULT))
2558 e1000_read_phy_reg(&adapter->hw, PHY_1000T_STATUS, &phy_tmp);
2559 if (phy_tmp & SR_1000T_MS_CONFIG_FAULT) {
2560 e1000_read_phy_reg(&adapter->hw,
2561 PHY_1000T_CTRL, &phy_tmp);
2562 if (phy_tmp & CR_1000T_MS_ENABLE) {
2563 phy_tmp &= ~CR_1000T_MS_ENABLE;
2564 e1000_write_phy_reg(&adapter->hw,
2565 PHY_1000T_CTRL, phy_tmp);
2566 adapter->smartspeed++;
2567 if (adapter->hw.mac.autoneg &&
2568 !e1000_phy_setup_autoneg(&adapter->hw) &&
2569 !e1000_read_phy_reg(&adapter->hw,
2570 PHY_CONTROL, &phy_tmp)) {
2571 phy_tmp |= MII_CR_AUTO_NEG_EN |
2572 MII_CR_RESTART_AUTO_NEG;
2573 e1000_write_phy_reg(&adapter->hw,
2574 PHY_CONTROL, phy_tmp);
2579 } else if (adapter->smartspeed == EM_SMARTSPEED_DOWNSHIFT) {
2580 /* If still no link, perhaps using 2/3 pair cable */
2581 e1000_read_phy_reg(&adapter->hw, PHY_1000T_CTRL, &phy_tmp);
2582 phy_tmp |= CR_1000T_MS_ENABLE;
2583 e1000_write_phy_reg(&adapter->hw, PHY_1000T_CTRL, phy_tmp);
2584 if (adapter->hw.mac.autoneg &&
2585 !e1000_phy_setup_autoneg(&adapter->hw) &&
2586 !e1000_read_phy_reg(&adapter->hw, PHY_CONTROL, &phy_tmp)) {
2587 phy_tmp |= MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG;
2588 e1000_write_phy_reg(&adapter->hw, PHY_CONTROL, phy_tmp);
2592 /* Restart process after EM_SMARTSPEED_MAX iterations */
2593 if (adapter->smartspeed++ == EM_SMARTSPEED_MAX)
2594 adapter->smartspeed = 0;
2598 em_dma_malloc(struct adapter *adapter, bus_size_t size,
2599 struct em_dma_alloc *dma)
2601 dma->dma_vaddr = bus_dmamem_coherent_any(adapter->parent_dtag,
2602 EM_DBA_ALIGN, size, BUS_DMA_WAITOK,
2603 &dma->dma_tag, &dma->dma_map,
2605 if (dma->dma_vaddr == NULL)
2612 em_dma_free(struct adapter *adapter, struct em_dma_alloc *dma)
2614 if (dma->dma_tag == NULL)
2616 bus_dmamap_unload(dma->dma_tag, dma->dma_map);
2617 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map);
2618 bus_dma_tag_destroy(dma->dma_tag);
2622 em_create_tx_ring(struct adapter *adapter)
2624 device_t dev = adapter->dev;
2625 struct em_buffer *tx_buffer;
2628 adapter->tx_buffer_area =
2629 kmalloc(sizeof(struct em_buffer) * adapter->num_tx_desc,
2630 M_DEVBUF, M_WAITOK | M_ZERO);
2633 * Create DMA tags for tx buffers
2635 error = bus_dma_tag_create(adapter->parent_dtag, /* parent */
2636 1, 0, /* alignment, bounds */
2637 BUS_SPACE_MAXADDR, /* lowaddr */
2638 BUS_SPACE_MAXADDR, /* highaddr */
2639 NULL, NULL, /* filter, filterarg */
2640 EM_TSO_SIZE, /* maxsize */
2641 EM_MAX_SCATTER, /* nsegments */
2642 PAGE_SIZE, /* maxsegsize */
2643 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW |
2644 BUS_DMA_ONEBPAGE, /* flags */
2647 device_printf(dev, "Unable to allocate TX DMA tag\n");
2648 kfree(adapter->tx_buffer_area, M_DEVBUF);
2649 adapter->tx_buffer_area = NULL;
2654 * Create DMA maps for tx buffers
2656 for (i = 0; i < adapter->num_tx_desc; i++) {
2657 tx_buffer = &adapter->tx_buffer_area[i];
2659 error = bus_dmamap_create(adapter->txtag,
2660 BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE,
2663 device_printf(dev, "Unable to create TX DMA map\n");
2664 em_destroy_tx_ring(adapter, i);
2672 em_init_tx_ring(struct adapter *adapter)
2674 /* Clear the old ring contents */
2675 bzero(adapter->tx_desc_base,
2676 (sizeof(struct e1000_tx_desc)) * adapter->num_tx_desc);
2679 adapter->next_avail_tx_desc = 0;
2680 adapter->next_tx_to_clean = 0;
2681 adapter->num_tx_desc_avail = adapter->num_tx_desc;
2685 em_init_tx_unit(struct adapter *adapter)
2687 uint32_t tctl, tarc, tipg = 0;
2690 /* Setup the Base and Length of the Tx Descriptor Ring */
2691 bus_addr = adapter->txdma.dma_paddr;
2692 E1000_WRITE_REG(&adapter->hw, E1000_TDLEN(0),
2693 adapter->num_tx_desc * sizeof(struct e1000_tx_desc));
2694 E1000_WRITE_REG(&adapter->hw, E1000_TDBAH(0),
2695 (uint32_t)(bus_addr >> 32));
2696 E1000_WRITE_REG(&adapter->hw, E1000_TDBAL(0),
2697 (uint32_t)bus_addr);
2698 /* Setup the HW Tx Head and Tail descriptor pointers */
2699 E1000_WRITE_REG(&adapter->hw, E1000_TDT(0), 0);
2700 E1000_WRITE_REG(&adapter->hw, E1000_TDH(0), 0);
2702 /* Set the default values for the Tx Inter Packet Gap timer */
2703 switch (adapter->hw.mac.type) {
2705 tipg = DEFAULT_82542_TIPG_IPGT;
2706 tipg |= DEFAULT_82542_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT;
2707 tipg |= DEFAULT_82542_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT;
2710 case e1000_80003es2lan:
2711 tipg = DEFAULT_82543_TIPG_IPGR1;
2712 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGR2 <<
2713 E1000_TIPG_IPGR2_SHIFT;
2717 if (adapter->hw.phy.media_type == e1000_media_type_fiber ||
2718 adapter->hw.phy.media_type ==
2719 e1000_media_type_internal_serdes)
2720 tipg = DEFAULT_82543_TIPG_IPGT_FIBER;
2722 tipg = DEFAULT_82543_TIPG_IPGT_COPPER;
2723 tipg |= DEFAULT_82543_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT;
2724 tipg |= DEFAULT_82543_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT;
2728 E1000_WRITE_REG(&adapter->hw, E1000_TIPG, tipg);
2730 /* NOTE: 0 is not allowed for TIDV */
2731 E1000_WRITE_REG(&adapter->hw, E1000_TIDV, 1);
2732 if(adapter->hw.mac.type >= e1000_82540)
2733 E1000_WRITE_REG(&adapter->hw, E1000_TADV, 0);
2735 if (adapter->hw.mac.type == e1000_82571 ||
2736 adapter->hw.mac.type == e1000_82572) {
2737 tarc = E1000_READ_REG(&adapter->hw, E1000_TARC(0));
2738 tarc |= SPEED_MODE_BIT;
2739 E1000_WRITE_REG(&adapter->hw, E1000_TARC(0), tarc);
2740 } else if (adapter->hw.mac.type == e1000_80003es2lan) {
2741 tarc = E1000_READ_REG(&adapter->hw, E1000_TARC(0));
2743 E1000_WRITE_REG(&adapter->hw, E1000_TARC(0), tarc);
2744 tarc = E1000_READ_REG(&adapter->hw, E1000_TARC(1));
2746 E1000_WRITE_REG(&adapter->hw, E1000_TARC(1), tarc);
2749 /* Program the Transmit Control Register */
2750 tctl = E1000_READ_REG(&adapter->hw, E1000_TCTL);
2751 tctl &= ~E1000_TCTL_CT;
2752 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC | E1000_TCTL_EN |
2753 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
2755 if (adapter->hw.mac.type >= e1000_82571)
2756 tctl |= E1000_TCTL_MULR;
2758 /* This write will effectively turn on the transmit unit. */
2759 E1000_WRITE_REG(&adapter->hw, E1000_TCTL, tctl);
2763 em_destroy_tx_ring(struct adapter *adapter, int ndesc)
2765 struct em_buffer *tx_buffer;
2768 if (adapter->tx_buffer_area == NULL)
2771 for (i = 0; i < ndesc; i++) {
2772 tx_buffer = &adapter->tx_buffer_area[i];
2774 KKASSERT(tx_buffer->m_head == NULL);
2775 bus_dmamap_destroy(adapter->txtag, tx_buffer->map);
2777 bus_dma_tag_destroy(adapter->txtag);
2779 kfree(adapter->tx_buffer_area, M_DEVBUF);
2780 adapter->tx_buffer_area = NULL;
2784 * The offload context needs to be set when we transfer the first
2785 * packet of a particular protocol (TCP/UDP). This routine has been
2786 * enhanced to deal with inserted VLAN headers.
2788 * If the new packet's ether header length, ip header length and
2789 * csum offloading type are same as the previous packet, we should
2790 * avoid allocating a new csum context descriptor; mainly to take
2791 * advantage of the pipeline effect of the TX data read request.
2793 * This function returns number of TX descrptors allocated for
2797 em_txcsum(struct adapter *adapter, struct mbuf *mp,
2798 uint32_t *txd_upper, uint32_t *txd_lower)
2800 struct e1000_context_desc *TXD;
2801 int curr_txd, ehdrlen, csum_flags;
2802 uint32_t cmd, hdr_len, ip_hlen;
2804 csum_flags = mp->m_pkthdr.csum_flags & EM_CSUM_FEATURES;
2805 ip_hlen = mp->m_pkthdr.csum_iphlen;
2806 ehdrlen = mp->m_pkthdr.csum_lhlen;
2808 if (adapter->csum_lhlen == ehdrlen &&
2809 adapter->csum_iphlen == ip_hlen &&
2810 adapter->csum_flags == csum_flags) {
2812 * Same csum offload context as the previous packets;
2815 *txd_upper = adapter->csum_txd_upper;
2816 *txd_lower = adapter->csum_txd_lower;
2821 * Setup a new csum offload context.
2824 curr_txd = adapter->next_avail_tx_desc;
2825 TXD = (struct e1000_context_desc *)&adapter->tx_desc_base[curr_txd];
2829 /* Setup of IP header checksum. */
2830 if (csum_flags & CSUM_IP) {
2832 * Start offset for header checksum calculation.
2833 * End offset for header checksum calculation.
2834 * Offset of place to put the checksum.
2836 TXD->lower_setup.ip_fields.ipcss = ehdrlen;
2837 TXD->lower_setup.ip_fields.ipcse =
2838 htole16(ehdrlen + ip_hlen - 1);
2839 TXD->lower_setup.ip_fields.ipcso =
2840 ehdrlen + offsetof(struct ip, ip_sum);
2841 cmd |= E1000_TXD_CMD_IP;
2842 *txd_upper |= E1000_TXD_POPTS_IXSM << 8;
2844 hdr_len = ehdrlen + ip_hlen;
2846 if (csum_flags & CSUM_TCP) {
2848 * Start offset for payload checksum calculation.
2849 * End offset for payload checksum calculation.
2850 * Offset of place to put the checksum.
2852 TXD->upper_setup.tcp_fields.tucss = hdr_len;
2853 TXD->upper_setup.tcp_fields.tucse = htole16(0);
2854 TXD->upper_setup.tcp_fields.tucso =
2855 hdr_len + offsetof(struct tcphdr, th_sum);
2856 cmd |= E1000_TXD_CMD_TCP;
2857 *txd_upper |= E1000_TXD_POPTS_TXSM << 8;
2858 } else if (csum_flags & CSUM_UDP) {
2860 * Start offset for header checksum calculation.
2861 * End offset for header checksum calculation.
2862 * Offset of place to put the checksum.
2864 TXD->upper_setup.tcp_fields.tucss = hdr_len;
2865 TXD->upper_setup.tcp_fields.tucse = htole16(0);
2866 TXD->upper_setup.tcp_fields.tucso =
2867 hdr_len + offsetof(struct udphdr, uh_sum);
2868 *txd_upper |= E1000_TXD_POPTS_TXSM << 8;
2871 *txd_lower = E1000_TXD_CMD_DEXT | /* Extended descr type */
2872 E1000_TXD_DTYP_D; /* Data descr */
2874 /* Save the information for this csum offloading context */
2875 adapter->csum_lhlen = ehdrlen;
2876 adapter->csum_iphlen = ip_hlen;
2877 adapter->csum_flags = csum_flags;
2878 adapter->csum_txd_upper = *txd_upper;
2879 adapter->csum_txd_lower = *txd_lower;
2881 TXD->tcp_seg_setup.data = htole32(0);
2882 TXD->cmd_and_length =
2883 htole32(E1000_TXD_CMD_IFCS | E1000_TXD_CMD_DEXT | cmd);
2885 if (++curr_txd == adapter->num_tx_desc)
2888 KKASSERT(adapter->num_tx_desc_avail > 0);
2889 adapter->num_tx_desc_avail--;
2891 adapter->next_avail_tx_desc = curr_txd;
2896 em_txeof(struct adapter *adapter)
2898 struct ifnet *ifp = &adapter->arpcom.ac_if;
2899 struct em_buffer *tx_buffer;
2900 int first, num_avail;
2902 if (adapter->tx_dd_head == adapter->tx_dd_tail)
2905 if (adapter->num_tx_desc_avail == adapter->num_tx_desc)
2908 num_avail = adapter->num_tx_desc_avail;
2909 first = adapter->next_tx_to_clean;
2911 while (adapter->tx_dd_head != adapter->tx_dd_tail) {
2912 struct e1000_tx_desc *tx_desc;
2913 int dd_idx = adapter->tx_dd[adapter->tx_dd_head];
2915 tx_desc = &adapter->tx_desc_base[dd_idx];
2916 if (tx_desc->upper.fields.status & E1000_TXD_STAT_DD) {
2917 EM_INC_TXDD_IDX(adapter->tx_dd_head);
2919 if (++dd_idx == adapter->num_tx_desc)
2922 while (first != dd_idx) {
2927 tx_buffer = &adapter->tx_buffer_area[first];
2928 if (tx_buffer->m_head) {
2930 bus_dmamap_unload(adapter->txtag,
2932 m_freem(tx_buffer->m_head);
2933 tx_buffer->m_head = NULL;
2936 if (++first == adapter->num_tx_desc)
2943 adapter->next_tx_to_clean = first;
2944 adapter->num_tx_desc_avail = num_avail;
2946 if (adapter->tx_dd_head == adapter->tx_dd_tail) {
2947 adapter->tx_dd_head = 0;
2948 adapter->tx_dd_tail = 0;
2951 if (!EM_IS_OACTIVE(adapter)) {
2952 ifq_clr_oactive(&ifp->if_snd);
2954 /* All clean, turn off the timer */
2955 if (adapter->num_tx_desc_avail == adapter->num_tx_desc)
2961 em_tx_collect(struct adapter *adapter)
2963 struct ifnet *ifp = &adapter->arpcom.ac_if;
2964 struct em_buffer *tx_buffer;
2965 int tdh, first, num_avail, dd_idx = -1;
2967 if (adapter->num_tx_desc_avail == adapter->num_tx_desc)
2970 tdh = E1000_READ_REG(&adapter->hw, E1000_TDH(0));
2971 if (tdh == adapter->next_tx_to_clean)
2974 if (adapter->tx_dd_head != adapter->tx_dd_tail)
2975 dd_idx = adapter->tx_dd[adapter->tx_dd_head];
2977 num_avail = adapter->num_tx_desc_avail;
2978 first = adapter->next_tx_to_clean;
2980 while (first != tdh) {
2985 tx_buffer = &adapter->tx_buffer_area[first];
2986 if (tx_buffer->m_head) {
2988 bus_dmamap_unload(adapter->txtag,
2990 m_freem(tx_buffer->m_head);
2991 tx_buffer->m_head = NULL;
2994 if (first == dd_idx) {
2995 EM_INC_TXDD_IDX(adapter->tx_dd_head);
2996 if (adapter->tx_dd_head == adapter->tx_dd_tail) {
2997 adapter->tx_dd_head = 0;
2998 adapter->tx_dd_tail = 0;
3001 dd_idx = adapter->tx_dd[adapter->tx_dd_head];
3005 if (++first == adapter->num_tx_desc)
3008 adapter->next_tx_to_clean = first;
3009 adapter->num_tx_desc_avail = num_avail;
3011 if (!EM_IS_OACTIVE(adapter)) {
3012 ifq_clr_oactive(&ifp->if_snd);
3014 /* All clean, turn off the timer */
3015 if (adapter->num_tx_desc_avail == adapter->num_tx_desc)
3021 * When Link is lost sometimes there is work still in the TX ring
3022 * which will result in a watchdog, rather than allow that do an
3023 * attempted cleanup and then reinit here. Note that this has been
3024 * seens mostly with fiber adapters.
3027 em_tx_purge(struct adapter *adapter)
3029 struct ifnet *ifp = &adapter->arpcom.ac_if;
3031 if (!adapter->link_active && ifp->if_timer) {
3032 em_tx_collect(adapter);
3033 if (ifp->if_timer) {
3034 if_printf(ifp, "Link lost, TX pending, reinit\n");
3042 em_newbuf(struct adapter *adapter, int i, int init)
3045 bus_dma_segment_t seg;
3047 struct em_buffer *rx_buffer;
3050 m = m_getcl(init ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR);
3052 adapter->mbuf_cluster_failed++;
3054 if_printf(&adapter->arpcom.ac_if,
3055 "Unable to allocate RX mbuf\n");
3059 m->m_len = m->m_pkthdr.len = MCLBYTES;
3061 if (adapter->max_frame_size <= MCLBYTES - ETHER_ALIGN)
3062 m_adj(m, ETHER_ALIGN);
3064 error = bus_dmamap_load_mbuf_segment(adapter->rxtag,
3065 adapter->rx_sparemap, m,
3066 &seg, 1, &nseg, BUS_DMA_NOWAIT);
3070 if_printf(&adapter->arpcom.ac_if,
3071 "Unable to load RX mbuf\n");
3076 rx_buffer = &adapter->rx_buffer_area[i];
3077 if (rx_buffer->m_head != NULL)
3078 bus_dmamap_unload(adapter->rxtag, rx_buffer->map);
3080 map = rx_buffer->map;
3081 rx_buffer->map = adapter->rx_sparemap;
3082 adapter->rx_sparemap = map;
3084 rx_buffer->m_head = m;
3086 adapter->rx_desc_base[i].buffer_addr = htole64(seg.ds_addr);
3091 em_create_rx_ring(struct adapter *adapter)
3093 device_t dev = adapter->dev;
3094 struct em_buffer *rx_buffer;
3097 adapter->rx_buffer_area =
3098 kmalloc(sizeof(struct em_buffer) * adapter->num_rx_desc,
3099 M_DEVBUF, M_WAITOK | M_ZERO);
3102 * Create DMA tag for rx buffers
3104 error = bus_dma_tag_create(adapter->parent_dtag, /* parent */
3105 1, 0, /* alignment, bounds */
3106 BUS_SPACE_MAXADDR, /* lowaddr */
3107 BUS_SPACE_MAXADDR, /* highaddr */
3108 NULL, NULL, /* filter, filterarg */
3109 MCLBYTES, /* maxsize */
3111 MCLBYTES, /* maxsegsize */
3112 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, /* flags */
3115 device_printf(dev, "Unable to allocate RX DMA tag\n");
3116 kfree(adapter->rx_buffer_area, M_DEVBUF);
3117 adapter->rx_buffer_area = NULL;
3122 * Create spare DMA map for rx buffers
3124 error = bus_dmamap_create(adapter->rxtag, BUS_DMA_WAITOK,
3125 &adapter->rx_sparemap);
3127 device_printf(dev, "Unable to create spare RX DMA map\n");
3128 bus_dma_tag_destroy(adapter->rxtag);
3129 kfree(adapter->rx_buffer_area, M_DEVBUF);
3130 adapter->rx_buffer_area = NULL;
3135 * Create DMA maps for rx buffers
3137 for (i = 0; i < adapter->num_rx_desc; i++) {
3138 rx_buffer = &adapter->rx_buffer_area[i];
3140 error = bus_dmamap_create(adapter->rxtag, BUS_DMA_WAITOK,
3143 device_printf(dev, "Unable to create RX DMA map\n");
3144 em_destroy_rx_ring(adapter, i);
3152 em_init_rx_ring(struct adapter *adapter)
3156 /* Reset descriptor ring */
3157 bzero(adapter->rx_desc_base,
3158 (sizeof(struct e1000_rx_desc)) * adapter->num_rx_desc);
3160 /* Allocate new ones. */
3161 for (i = 0; i < adapter->num_rx_desc; i++) {
3162 error = em_newbuf(adapter, i, 1);
3167 /* Setup our descriptor pointers */
3168 adapter->next_rx_desc_to_check = 0;
3174 em_init_rx_unit(struct adapter *adapter)
3176 struct ifnet *ifp = &adapter->arpcom.ac_if;
3181 * Make sure receives are disabled while setting
3182 * up the descriptor ring
3184 rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL);
3185 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, rctl & ~E1000_RCTL_EN);
3187 if (adapter->hw.mac.type >= e1000_82540) {
3191 * Set the interrupt throttling rate. Value is calculated
3192 * as ITR = 1 / (INT_THROTTLE_CEIL * 256ns)
3194 if (adapter->int_throttle_ceil)
3195 itr = 1000000000 / 256 / adapter->int_throttle_ceil;
3198 em_set_itr(adapter, itr);
3201 /* Disable accelerated ackknowledge */
3202 if (adapter->hw.mac.type == e1000_82574) {
3203 E1000_WRITE_REG(&adapter->hw,
3204 E1000_RFCTL, E1000_RFCTL_ACK_DIS);
3207 /* Receive Checksum Offload for TCP and UDP */
3208 if (ifp->if_capenable & IFCAP_RXCSUM) {
3211 rxcsum = E1000_READ_REG(&adapter->hw, E1000_RXCSUM);
3212 rxcsum |= (E1000_RXCSUM_IPOFL | E1000_RXCSUM_TUOFL);
3213 E1000_WRITE_REG(&adapter->hw, E1000_RXCSUM, rxcsum);
3217 * XXX TEMPORARY WORKAROUND: on some systems with 82573
3218 * long latencies are observed, like Lenovo X60. This
3219 * change eliminates the problem, but since having positive
3220 * values in RDTR is a known source of problems on other
3221 * platforms another solution is being sought.
3223 if (em_82573_workaround && adapter->hw.mac.type == e1000_82573) {
3224 E1000_WRITE_REG(&adapter->hw, E1000_RADV, EM_RADV_82573);
3225 E1000_WRITE_REG(&adapter->hw, E1000_RDTR, EM_RDTR_82573);
3229 * Setup the Base and Length of the Rx Descriptor Ring
3231 bus_addr = adapter->rxdma.dma_paddr;
3232 E1000_WRITE_REG(&adapter->hw, E1000_RDLEN(0),
3233 adapter->num_rx_desc * sizeof(struct e1000_rx_desc));
3234 E1000_WRITE_REG(&adapter->hw, E1000_RDBAH(0),
3235 (uint32_t)(bus_addr >> 32));
3236 E1000_WRITE_REG(&adapter->hw, E1000_RDBAL(0),
3237 (uint32_t)bus_addr);
3240 * Setup the HW Rx Head and Tail Descriptor Pointers
3242 E1000_WRITE_REG(&adapter->hw, E1000_RDH(0), 0);
3243 E1000_WRITE_REG(&adapter->hw, E1000_RDT(0), adapter->num_rx_desc - 1);
3245 /* Set early receive threshold on appropriate hw */
3246 if (((adapter->hw.mac.type == e1000_ich9lan) ||
3247 (adapter->hw.mac.type == e1000_pch2lan) ||
3248 (adapter->hw.mac.type == e1000_ich10lan)) &&
3249 (ifp->if_mtu > ETHERMTU)) {
3252 rxdctl = E1000_READ_REG(&adapter->hw, E1000_RXDCTL(0));
3253 E1000_WRITE_REG(&adapter->hw, E1000_RXDCTL(0), rxdctl | 3);
3254 E1000_WRITE_REG(&adapter->hw, E1000_ERT, 0x100 | (1 << 13));
3257 if (adapter->hw.mac.type == e1000_pch2lan) {
3258 if (ifp->if_mtu > ETHERMTU)
3259 e1000_lv_jumbo_workaround_ich8lan(&adapter->hw, TRUE);
3261 e1000_lv_jumbo_workaround_ich8lan(&adapter->hw, FALSE);
3264 /* Setup the Receive Control Register */
3265 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
3266 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_LBM_NO |
3267 E1000_RCTL_RDMTS_HALF |
3268 (adapter->hw.mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
3270 /* Make sure VLAN Filters are off */
3271 rctl &= ~E1000_RCTL_VFE;
3273 if (e1000_tbi_sbp_enabled_82543(&adapter->hw))
3274 rctl |= E1000_RCTL_SBP;
3276 rctl &= ~E1000_RCTL_SBP;
3278 switch (adapter->rx_buffer_len) {
3281 rctl |= E1000_RCTL_SZ_2048;
3285 rctl |= E1000_RCTL_SZ_4096 |
3286 E1000_RCTL_BSEX | E1000_RCTL_LPE;
3290 rctl |= E1000_RCTL_SZ_8192 |
3291 E1000_RCTL_BSEX | E1000_RCTL_LPE;
3295 rctl |= E1000_RCTL_SZ_16384 |
3296 E1000_RCTL_BSEX | E1000_RCTL_LPE;
3300 if (ifp->if_mtu > ETHERMTU)
3301 rctl |= E1000_RCTL_LPE;
3303 rctl &= ~E1000_RCTL_LPE;
3305 /* Enable Receives */
3306 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, rctl);
3310 em_destroy_rx_ring(struct adapter *adapter, int ndesc)
3312 struct em_buffer *rx_buffer;
3315 if (adapter->rx_buffer_area == NULL)
3318 for (i = 0; i < ndesc; i++) {
3319 rx_buffer = &adapter->rx_buffer_area[i];
3321 KKASSERT(rx_buffer->m_head == NULL);
3322 bus_dmamap_destroy(adapter->rxtag, rx_buffer->map);
3324 bus_dmamap_destroy(adapter->rxtag, adapter->rx_sparemap);
3325 bus_dma_tag_destroy(adapter->rxtag);
3327 kfree(adapter->rx_buffer_area, M_DEVBUF);
3328 adapter->rx_buffer_area = NULL;
3332 em_rxeof(struct adapter *adapter, int count)
3334 struct ifnet *ifp = &adapter->arpcom.ac_if;
3335 uint8_t status, accept_frame = 0, eop = 0;
3336 uint16_t len, desc_len, prev_len_adj;
3337 struct e1000_rx_desc *current_desc;
3341 i = adapter->next_rx_desc_to_check;
3342 current_desc = &adapter->rx_desc_base[i];
3344 if (!(current_desc->status & E1000_RXD_STAT_DD))
3347 while ((current_desc->status & E1000_RXD_STAT_DD) && count != 0) {
3348 struct mbuf *m = NULL;
3352 mp = adapter->rx_buffer_area[i].m_head;
3355 * Can't defer bus_dmamap_sync(9) because TBI_ACCEPT
3356 * needs to access the last received byte in the mbuf.
3358 bus_dmamap_sync(adapter->rxtag, adapter->rx_buffer_area[i].map,
3359 BUS_DMASYNC_POSTREAD);
3363 desc_len = le16toh(current_desc->length);
3364 status = current_desc->status;
3365 if (status & E1000_RXD_STAT_EOP) {
3368 if (desc_len < ETHER_CRC_LEN) {
3370 prev_len_adj = ETHER_CRC_LEN - desc_len;
3372 len = desc_len - ETHER_CRC_LEN;
3379 if (current_desc->errors & E1000_RXD_ERR_FRAME_ERR_MASK) {
3381 uint32_t pkt_len = desc_len;
3383 if (adapter->fmp != NULL)
3384 pkt_len += adapter->fmp->m_pkthdr.len;
3386 last_byte = *(mtod(mp, caddr_t) + desc_len - 1);
3387 if (TBI_ACCEPT(&adapter->hw, status,
3388 current_desc->errors, pkt_len, last_byte,
3389 adapter->min_frame_size, adapter->max_frame_size)) {
3390 e1000_tbi_adjust_stats_82543(&adapter->hw,
3391 &adapter->stats, pkt_len,
3392 adapter->hw.mac.addr,
3393 adapter->max_frame_size);
3402 if (em_newbuf(adapter, i, 0) != 0) {
3407 /* Assign correct length to the current fragment */
3410 if (adapter->fmp == NULL) {
3411 mp->m_pkthdr.len = len;
3412 adapter->fmp = mp; /* Store the first mbuf */
3416 * Chain mbuf's together
3420 * Adjust length of previous mbuf in chain if
3421 * we received less than 4 bytes in the last
3424 if (prev_len_adj > 0) {
3425 adapter->lmp->m_len -= prev_len_adj;
3426 adapter->fmp->m_pkthdr.len -=
3429 adapter->lmp->m_next = mp;
3430 adapter->lmp = adapter->lmp->m_next;
3431 adapter->fmp->m_pkthdr.len += len;
3435 adapter->fmp->m_pkthdr.rcvif = ifp;
3438 if (ifp->if_capenable & IFCAP_RXCSUM) {
3439 em_rxcsum(adapter, current_desc,
3443 if (status & E1000_RXD_STAT_VP) {
3444 adapter->fmp->m_pkthdr.ether_vlantag =
3445 (le16toh(current_desc->special) &
3446 E1000_RXD_SPC_VLAN_MASK);
3447 adapter->fmp->m_flags |= M_VLANTAG;
3450 adapter->fmp = NULL;
3451 adapter->lmp = NULL;
3457 /* Reuse loaded DMA map and just update mbuf chain */
3458 mp = adapter->rx_buffer_area[i].m_head;
3459 mp->m_len = mp->m_pkthdr.len = MCLBYTES;
3460 mp->m_data = mp->m_ext.ext_buf;
3462 if (adapter->max_frame_size <= (MCLBYTES - ETHER_ALIGN))
3463 m_adj(mp, ETHER_ALIGN);
3465 if (adapter->fmp != NULL) {
3466 m_freem(adapter->fmp);
3467 adapter->fmp = NULL;
3468 adapter->lmp = NULL;
3473 /* Zero out the receive descriptors status. */
3474 current_desc->status = 0;
3477 ifp->if_input(ifp, m);
3479 /* Advance our pointers to the next descriptor. */
3480 if (++i == adapter->num_rx_desc)
3482 current_desc = &adapter->rx_desc_base[i];
3484 adapter->next_rx_desc_to_check = i;
3486 /* Advance the E1000's Receive Queue #0 "Tail Pointer". */
3488 i = adapter->num_rx_desc - 1;
3489 E1000_WRITE_REG(&adapter->hw, E1000_RDT(0), i);
3493 em_rxcsum(struct adapter *adapter, struct e1000_rx_desc *rx_desc,
3496 /* 82543 or newer only */
3497 if (adapter->hw.mac.type < e1000_82543 ||
3498 /* Ignore Checksum bit is set */
3499 (rx_desc->status & E1000_RXD_STAT_IXSM))
3502 if ((rx_desc->status & E1000_RXD_STAT_IPCS) &&
3503 !(rx_desc->errors & E1000_RXD_ERR_IPE)) {
3504 /* IP Checksum Good */
3505 mp->m_pkthdr.csum_flags |= CSUM_IP_CHECKED | CSUM_IP_VALID;
3508 if ((rx_desc->status & E1000_RXD_STAT_TCPCS) &&
3509 !(rx_desc->errors & E1000_RXD_ERR_TCPE)) {
3510 mp->m_pkthdr.csum_flags |= CSUM_DATA_VALID |
3512 CSUM_FRAG_NOT_CHECKED;
3513 mp->m_pkthdr.csum_data = htons(0xffff);
3518 em_enable_intr(struct adapter *adapter)
3520 uint32_t ims_mask = IMS_ENABLE_MASK;
3522 lwkt_serialize_handler_enable(adapter->arpcom.ac_if.if_serializer);
3526 if (adapter->hw.mac.type == e1000_82574) {
3527 E1000_WRITE_REG(&adapter->hw, EM_EIAC, EM_MSIX_MASK);
3528 ims_mask |= EM_MSIX_MASK;
3531 E1000_WRITE_REG(&adapter->hw, E1000_IMS, ims_mask);
3535 em_disable_intr(struct adapter *adapter)
3537 uint32_t clear = 0xffffffff;
3540 * The first version of 82542 had an errata where when link was forced
3541 * it would stay up even up even if the cable was disconnected.
3542 * Sequence errors were used to detect the disconnect and then the
3543 * driver would unforce the link. This code in the in the ISR. For
3544 * this to work correctly the Sequence error interrupt had to be
3545 * enabled all the time.
3547 if (adapter->hw.mac.type == e1000_82542 &&
3548 adapter->hw.revision_id == E1000_REVISION_2)
3549 clear &= ~E1000_ICR_RXSEQ;
3550 else if (adapter->hw.mac.type == e1000_82574)
3551 E1000_WRITE_REG(&adapter->hw, EM_EIAC, 0);
3553 E1000_WRITE_REG(&adapter->hw, E1000_IMC, clear);
3555 adapter->npoll.ifpc_stcount = 0;
3557 lwkt_serialize_handler_disable(adapter->arpcom.ac_if.if_serializer);
3561 * Bit of a misnomer, what this really means is
3562 * to enable OS management of the system... aka
3563 * to disable special hardware management features
3566 em_get_mgmt(struct adapter *adapter)
3568 /* A shared code workaround */
3569 #define E1000_82542_MANC2H E1000_MANC2H
3570 if (adapter->flags & EM_FLAG_HAS_MGMT) {
3571 int manc2h = E1000_READ_REG(&adapter->hw, E1000_MANC2H);
3572 int manc = E1000_READ_REG(&adapter->hw, E1000_MANC);
3574 /* disable hardware interception of ARP */
3575 manc &= ~(E1000_MANC_ARP_EN);
3577 /* enable receiving management packets to the host */
3578 if (adapter->hw.mac.type >= e1000_82571) {
3579 manc |= E1000_MANC_EN_MNG2HOST;
3580 #define E1000_MNG2HOST_PORT_623 (1 << 5)
3581 #define E1000_MNG2HOST_PORT_664 (1 << 6)
3582 manc2h |= E1000_MNG2HOST_PORT_623;
3583 manc2h |= E1000_MNG2HOST_PORT_664;
3584 E1000_WRITE_REG(&adapter->hw, E1000_MANC2H, manc2h);
3587 E1000_WRITE_REG(&adapter->hw, E1000_MANC, manc);
3592 * Give control back to hardware management
3593 * controller if there is one.
3596 em_rel_mgmt(struct adapter *adapter)
3598 if (adapter->flags & EM_FLAG_HAS_MGMT) {
3599 int manc = E1000_READ_REG(&adapter->hw, E1000_MANC);
3601 /* re-enable hardware interception of ARP */
3602 manc |= E1000_MANC_ARP_EN;
3604 if (adapter->hw.mac.type >= e1000_82571)
3605 manc &= ~E1000_MANC_EN_MNG2HOST;
3607 E1000_WRITE_REG(&adapter->hw, E1000_MANC, manc);
3612 * em_get_hw_control() sets {CTRL_EXT|FWSM}:DRV_LOAD bit.
3613 * For ASF and Pass Through versions of f/w this means that
3614 * the driver is loaded. For AMT version (only with 82573)
3615 * of the f/w this means that the network i/f is open.
3618 em_get_hw_control(struct adapter *adapter)
3620 /* Let firmware know the driver has taken over */
3621 if (adapter->hw.mac.type == e1000_82573) {
3624 swsm = E1000_READ_REG(&adapter->hw, E1000_SWSM);
3625 E1000_WRITE_REG(&adapter->hw, E1000_SWSM,
3626 swsm | E1000_SWSM_DRV_LOAD);
3630 ctrl_ext = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT);
3631 E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT,
3632 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
3634 adapter->flags |= EM_FLAG_HW_CTRL;
3638 * em_rel_hw_control() resets {CTRL_EXT|FWSM}:DRV_LOAD bit.
3639 * For ASF and Pass Through versions of f/w this means that the
3640 * driver is no longer loaded. For AMT version (only with 82573)
3641 * of the f/w this means that the network i/f is closed.
3644 em_rel_hw_control(struct adapter *adapter)
3646 if ((adapter->flags & EM_FLAG_HW_CTRL) == 0)
3648 adapter->flags &= ~EM_FLAG_HW_CTRL;
3650 /* Let firmware taken over control of h/w */
3651 if (adapter->hw.mac.type == e1000_82573) {
3654 swsm = E1000_READ_REG(&adapter->hw, E1000_SWSM);
3655 E1000_WRITE_REG(&adapter->hw, E1000_SWSM,
3656 swsm & ~E1000_SWSM_DRV_LOAD);
3660 ctrl_ext = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT);
3661 E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT,
3662 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
3667 em_is_valid_eaddr(const uint8_t *addr)
3669 char zero_addr[ETHER_ADDR_LEN] = { 0, 0, 0, 0, 0, 0 };
3671 if ((addr[0] & 1) || !bcmp(addr, zero_addr, ETHER_ADDR_LEN))
3678 * Enable PCI Wake On Lan capability
3681 em_enable_wol(device_t dev)
3683 uint16_t cap, status;
3686 /* First find the capabilities pointer*/
3687 cap = pci_read_config(dev, PCIR_CAP_PTR, 2);
3689 /* Read the PM Capabilities */
3690 id = pci_read_config(dev, cap, 1);
3691 if (id != PCIY_PMG) /* Something wrong */
3695 * OK, we have the power capabilities,
3696 * so now get the status register
3698 cap += PCIR_POWER_STATUS;
3699 status = pci_read_config(dev, cap, 2);
3700 status |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
3701 pci_write_config(dev, cap, status, 2);
3706 * 82544 Coexistence issue workaround.
3707 * There are 2 issues.
3708 * 1. Transmit Hang issue.
3709 * To detect this issue, following equation can be used...
3710 * SIZE[3:0] + ADDR[2:0] = SUM[3:0].
3711 * If SUM[3:0] is in between 1 to 4, we will have this issue.
3714 * To detect this issue, following equation can be used...
3715 * SIZE[3:0] + ADDR[2:0] = SUM[3:0].
3716 * If SUM[3:0] is in between 9 to c, we will have this issue.
3719 * Make sure we do not have ending address
3720 * as 1,2,3,4(Hang) or 9,a,b,c (DAC)
3723 em_82544_fill_desc(bus_addr_t address, uint32_t length, PDESC_ARRAY desc_array)
3725 uint32_t safe_terminator;
3728 * Since issue is sensitive to length and address.
3729 * Let us first check the address...
3732 desc_array->descriptor[0].address = address;
3733 desc_array->descriptor[0].length = length;
3734 desc_array->elements = 1;
3735 return (desc_array->elements);
3739 (uint32_t)((((uint32_t)address & 0x7) + (length & 0xF)) & 0xF);
3741 /* If it does not fall between 0x1 to 0x4 and 0x9 to 0xC then return */
3742 if (safe_terminator == 0 ||
3743 (safe_terminator > 4 && safe_terminator < 9) ||
3744 (safe_terminator > 0xC && safe_terminator <= 0xF)) {
3745 desc_array->descriptor[0].address = address;
3746 desc_array->descriptor[0].length = length;
3747 desc_array->elements = 1;
3748 return (desc_array->elements);
3751 desc_array->descriptor[0].address = address;
3752 desc_array->descriptor[0].length = length - 4;
3753 desc_array->descriptor[1].address = address + (length - 4);
3754 desc_array->descriptor[1].length = 4;
3755 desc_array->elements = 2;
3756 return (desc_array->elements);
3760 em_update_stats(struct adapter *adapter)
3762 struct ifnet *ifp = &adapter->arpcom.ac_if;
3764 if (adapter->hw.phy.media_type == e1000_media_type_copper ||
3765 (E1000_READ_REG(&adapter->hw, E1000_STATUS) & E1000_STATUS_LU)) {
3766 adapter->stats.symerrs +=
3767 E1000_READ_REG(&adapter->hw, E1000_SYMERRS);
3768 adapter->stats.sec += E1000_READ_REG(&adapter->hw, E1000_SEC);
3770 adapter->stats.crcerrs += E1000_READ_REG(&adapter->hw, E1000_CRCERRS);
3771 adapter->stats.mpc += E1000_READ_REG(&adapter->hw, E1000_MPC);
3772 adapter->stats.scc += E1000_READ_REG(&adapter->hw, E1000_SCC);
3773 adapter->stats.ecol += E1000_READ_REG(&adapter->hw, E1000_ECOL);
3775 adapter->stats.mcc += E1000_READ_REG(&adapter->hw, E1000_MCC);
3776 adapter->stats.latecol += E1000_READ_REG(&adapter->hw, E1000_LATECOL);
3777 adapter->stats.colc += E1000_READ_REG(&adapter->hw, E1000_COLC);
3778 adapter->stats.dc += E1000_READ_REG(&adapter->hw, E1000_DC);
3779 adapter->stats.rlec += E1000_READ_REG(&adapter->hw, E1000_RLEC);
3780 adapter->stats.xonrxc += E1000_READ_REG(&adapter->hw, E1000_XONRXC);
3781 adapter->stats.xontxc += E1000_READ_REG(&adapter->hw, E1000_XONTXC);
3782 adapter->stats.xoffrxc += E1000_READ_REG(&adapter->hw, E1000_XOFFRXC);
3783 adapter->stats.xofftxc += E1000_READ_REG(&adapter->hw, E1000_XOFFTXC);
3784 adapter->stats.fcruc += E1000_READ_REG(&adapter->hw, E1000_FCRUC);
3785 adapter->stats.prc64 += E1000_READ_REG(&adapter->hw, E1000_PRC64);
3786 adapter->stats.prc127 += E1000_READ_REG(&adapter->hw, E1000_PRC127);
3787 adapter->stats.prc255 += E1000_READ_REG(&adapter->hw, E1000_PRC255);
3788 adapter->stats.prc511 += E1000_READ_REG(&adapter->hw, E1000_PRC511);
3789 adapter->stats.prc1023 += E1000_READ_REG(&adapter->hw, E1000_PRC1023);
3790 adapter->stats.prc1522 += E1000_READ_REG(&adapter->hw, E1000_PRC1522);
3791 adapter->stats.gprc += E1000_READ_REG(&adapter->hw, E1000_GPRC);
3792 adapter->stats.bprc += E1000_READ_REG(&adapter->hw, E1000_BPRC);
3793 adapter->stats.mprc += E1000_READ_REG(&adapter->hw, E1000_MPRC);
3794 adapter->stats.gptc += E1000_READ_REG(&adapter->hw, E1000_GPTC);
3796 /* For the 64-bit byte counters the low dword must be read first. */
3797 /* Both registers clear on the read of the high dword */
3799 adapter->stats.gorc += E1000_READ_REG(&adapter->hw, E1000_GORCH);
3800 adapter->stats.gotc += E1000_READ_REG(&adapter->hw, E1000_GOTCH);
3802 adapter->stats.rnbc += E1000_READ_REG(&adapter->hw, E1000_RNBC);
3803 adapter->stats.ruc += E1000_READ_REG(&adapter->hw, E1000_RUC);
3804 adapter->stats.rfc += E1000_READ_REG(&adapter->hw, E1000_RFC);
3805 adapter->stats.roc += E1000_READ_REG(&adapter->hw, E1000_ROC);
3806 adapter->stats.rjc += E1000_READ_REG(&adapter->hw, E1000_RJC);
3808 adapter->stats.tor += E1000_READ_REG(&adapter->hw, E1000_TORH);
3809 adapter->stats.tot += E1000_READ_REG(&adapter->hw, E1000_TOTH);
3811 adapter->stats.tpr += E1000_READ_REG(&adapter->hw, E1000_TPR);
3812 adapter->stats.tpt += E1000_READ_REG(&adapter->hw, E1000_TPT);
3813 adapter->stats.ptc64 += E1000_READ_REG(&adapter->hw, E1000_PTC64);
3814 adapter->stats.ptc127 += E1000_READ_REG(&adapter->hw, E1000_PTC127);
3815 adapter->stats.ptc255 += E1000_READ_REG(&adapter->hw, E1000_PTC255);
3816 adapter->stats.ptc511 += E1000_READ_REG(&adapter->hw, E1000_PTC511);
3817 adapter->stats.ptc1023 += E1000_READ_REG(&adapter->hw, E1000_PTC1023);
3818 adapter->stats.ptc1522 += E1000_READ_REG(&adapter->hw, E1000_PTC1522);
3819 adapter->stats.mptc += E1000_READ_REG(&adapter->hw, E1000_MPTC);
3820 adapter->stats.bptc += E1000_READ_REG(&adapter->hw, E1000_BPTC);
3822 if (adapter->hw.mac.type >= e1000_82543) {
3823 adapter->stats.algnerrc +=
3824 E1000_READ_REG(&adapter->hw, E1000_ALGNERRC);
3825 adapter->stats.rxerrc +=
3826 E1000_READ_REG(&adapter->hw, E1000_RXERRC);
3827 adapter->stats.tncrs +=
3828 E1000_READ_REG(&adapter->hw, E1000_TNCRS);
3829 adapter->stats.cexterr +=
3830 E1000_READ_REG(&adapter->hw, E1000_CEXTERR);
3831 adapter->stats.tsctc +=
3832 E1000_READ_REG(&adapter->hw, E1000_TSCTC);
3833 adapter->stats.tsctfc +=
3834 E1000_READ_REG(&adapter->hw, E1000_TSCTFC);
3837 ifp->if_collisions = adapter->stats.colc;
3841 adapter->dropped_pkts + adapter->stats.rxerrc +
3842 adapter->stats.crcerrs + adapter->stats.algnerrc +
3843 adapter->stats.ruc + adapter->stats.roc +
3844 adapter->stats.mpc + adapter->stats.cexterr;
3848 adapter->stats.ecol + adapter->stats.latecol +
3849 adapter->watchdog_events;
3853 em_print_debug_info(struct adapter *adapter)
3855 device_t dev = adapter->dev;
3856 uint8_t *hw_addr = adapter->hw.hw_addr;
3858 device_printf(dev, "Adapter hardware address = %p \n", hw_addr);
3859 device_printf(dev, "CTRL = 0x%x RCTL = 0x%x \n",
3860 E1000_READ_REG(&adapter->hw, E1000_CTRL),
3861 E1000_READ_REG(&adapter->hw, E1000_RCTL));
3862 device_printf(dev, "Packet buffer = Tx=%dk Rx=%dk \n",
3863 ((E1000_READ_REG(&adapter->hw, E1000_PBA) & 0xffff0000) >> 16),\
3864 (E1000_READ_REG(&adapter->hw, E1000_PBA) & 0xffff) );
3865 device_printf(dev, "Flow control watermarks high = %d low = %d\n",
3866 adapter->hw.fc.high_water,
3867 adapter->hw.fc.low_water);
3868 device_printf(dev, "tx_int_delay = %d, tx_abs_int_delay = %d\n",
3869 E1000_READ_REG(&adapter->hw, E1000_TIDV),
3870 E1000_READ_REG(&adapter->hw, E1000_TADV));
3871 device_printf(dev, "rx_int_delay = %d, rx_abs_int_delay = %d\n",
3872 E1000_READ_REG(&adapter->hw, E1000_RDTR),
3873 E1000_READ_REG(&adapter->hw, E1000_RADV));
3874 device_printf(dev, "fifo workaround = %lld, fifo_reset_count = %lld\n",
3875 (long long)adapter->tx_fifo_wrk_cnt,
3876 (long long)adapter->tx_fifo_reset_cnt);
3877 device_printf(dev, "hw tdh = %d, hw tdt = %d\n",
3878 E1000_READ_REG(&adapter->hw, E1000_TDH(0)),
3879 E1000_READ_REG(&adapter->hw, E1000_TDT(0)));
3880 device_printf(dev, "hw rdh = %d, hw rdt = %d\n",
3881 E1000_READ_REG(&adapter->hw, E1000_RDH(0)),
3882 E1000_READ_REG(&adapter->hw, E1000_RDT(0)));
3883 device_printf(dev, "Num Tx descriptors avail = %d\n",
3884 adapter->num_tx_desc_avail);
3885 device_printf(dev, "Tx Descriptors not avail1 = %ld\n",
3886 adapter->no_tx_desc_avail1);
3887 device_printf(dev, "Tx Descriptors not avail2 = %ld\n",
3888 adapter->no_tx_desc_avail2);
3889 device_printf(dev, "Std mbuf failed = %ld\n",
3890 adapter->mbuf_alloc_failed);
3891 device_printf(dev, "Std mbuf cluster failed = %ld\n",
3892 adapter->mbuf_cluster_failed);
3893 device_printf(dev, "Driver dropped packets = %ld\n",
3894 adapter->dropped_pkts);
3895 device_printf(dev, "Driver tx dma failure in encap = %ld\n",
3896 adapter->no_tx_dma_setup);
3900 em_print_hw_stats(struct adapter *adapter)
3902 device_t dev = adapter->dev;
3904 device_printf(dev, "Excessive collisions = %lld\n",
3905 (long long)adapter->stats.ecol);
3906 #if (DEBUG_HW > 0) /* Dont output these errors normally */
3907 device_printf(dev, "Symbol errors = %lld\n",
3908 (long long)adapter->stats.symerrs);
3910 device_printf(dev, "Sequence errors = %lld\n",
3911 (long long)adapter->stats.sec);
3912 device_printf(dev, "Defer count = %lld\n",
3913 (long long)adapter->stats.dc);
3914 device_printf(dev, "Missed Packets = %lld\n",
3915 (long long)adapter->stats.mpc);
3916 device_printf(dev, "Receive No Buffers = %lld\n",
3917 (long long)adapter->stats.rnbc);
3918 /* RLEC is inaccurate on some hardware, calculate our own. */
3919 device_printf(dev, "Receive Length Errors = %lld\n",
3920 ((long long)adapter->stats.roc + (long long)adapter->stats.ruc));
3921 device_printf(dev, "Receive errors = %lld\n",
3922 (long long)adapter->stats.rxerrc);
3923 device_printf(dev, "Crc errors = %lld\n",
3924 (long long)adapter->stats.crcerrs);
3925 device_printf(dev, "Alignment errors = %lld\n",
3926 (long long)adapter->stats.algnerrc);
3927 device_printf(dev, "Collision/Carrier extension errors = %lld\n",
3928 (long long)adapter->stats.cexterr);
3929 device_printf(dev, "RX overruns = %ld\n", adapter->rx_overruns);
3930 device_printf(dev, "watchdog timeouts = %ld\n",
3931 adapter->watchdog_events);
3932 device_printf(dev, "XON Rcvd = %lld\n",
3933 (long long)adapter->stats.xonrxc);
3934 device_printf(dev, "XON Xmtd = %lld\n",
3935 (long long)adapter->stats.xontxc);
3936 device_printf(dev, "XOFF Rcvd = %lld\n",
3937 (long long)adapter->stats.xoffrxc);
3938 device_printf(dev, "XOFF Xmtd = %lld\n",
3939 (long long)adapter->stats.xofftxc);
3940 device_printf(dev, "Good Packets Rcvd = %lld\n",
3941 (long long)adapter->stats.gprc);
3942 device_printf(dev, "Good Packets Xmtd = %lld\n",
3943 (long long)adapter->stats.gptc);
3947 em_print_nvm_info(struct adapter *adapter)
3949 uint16_t eeprom_data;
3952 /* Its a bit crude, but it gets the job done */
3953 kprintf("\nInterface EEPROM Dump:\n");
3954 kprintf("Offset\n0x0000 ");
3955 for (i = 0, j = 0; i < 32; i++, j++) {
3956 if (j == 8) { /* Make the offset block */
3958 kprintf("\n0x00%x0 ",row);
3960 e1000_read_nvm(&adapter->hw, i, 1, &eeprom_data);
3961 kprintf("%04x ", eeprom_data);
3967 em_sysctl_debug_info(SYSCTL_HANDLER_ARGS)
3969 struct adapter *adapter;
3974 error = sysctl_handle_int(oidp, &result, 0, req);
3975 if (error || !req->newptr)
3978 adapter = (struct adapter *)arg1;
3979 ifp = &adapter->arpcom.ac_if;
3981 lwkt_serialize_enter(ifp->if_serializer);
3984 em_print_debug_info(adapter);
3987 * This value will cause a hex dump of the
3988 * first 32 16-bit words of the EEPROM to
3992 em_print_nvm_info(adapter);
3994 lwkt_serialize_exit(ifp->if_serializer);
4000 em_sysctl_stats(SYSCTL_HANDLER_ARGS)
4005 error = sysctl_handle_int(oidp, &result, 0, req);
4006 if (error || !req->newptr)
4010 struct adapter *adapter = (struct adapter *)arg1;
4011 struct ifnet *ifp = &adapter->arpcom.ac_if;
4013 lwkt_serialize_enter(ifp->if_serializer);
4014 em_print_hw_stats(adapter);
4015 lwkt_serialize_exit(ifp->if_serializer);
4021 em_add_sysctl(struct adapter *adapter)
4023 sysctl_ctx_init(&adapter->sysctl_ctx);
4024 adapter->sysctl_tree = SYSCTL_ADD_NODE(&adapter->sysctl_ctx,
4025 SYSCTL_STATIC_CHILDREN(_hw), OID_AUTO,
4026 device_get_nameunit(adapter->dev),
4028 if (adapter->sysctl_tree == NULL) {
4029 device_printf(adapter->dev, "can't add sysctl node\n");
4031 SYSCTL_ADD_PROC(&adapter->sysctl_ctx,
4032 SYSCTL_CHILDREN(adapter->sysctl_tree),
4033 OID_AUTO, "debug", CTLTYPE_INT|CTLFLAG_RW, adapter, 0,
4034 em_sysctl_debug_info, "I", "Debug Information");
4036 SYSCTL_ADD_PROC(&adapter->sysctl_ctx,
4037 SYSCTL_CHILDREN(adapter->sysctl_tree),
4038 OID_AUTO, "stats", CTLTYPE_INT|CTLFLAG_RW, adapter, 0,
4039 em_sysctl_stats, "I", "Statistics");
4041 SYSCTL_ADD_INT(&adapter->sysctl_ctx,
4042 SYSCTL_CHILDREN(adapter->sysctl_tree),
4043 OID_AUTO, "rxd", CTLFLAG_RD,
4044 &adapter->num_rx_desc, 0, NULL);
4045 SYSCTL_ADD_INT(&adapter->sysctl_ctx,
4046 SYSCTL_CHILDREN(adapter->sysctl_tree),
4047 OID_AUTO, "txd", CTLFLAG_RD,
4048 &adapter->num_tx_desc, 0, NULL);
4050 if (adapter->hw.mac.type >= e1000_82540) {
4051 SYSCTL_ADD_PROC(&adapter->sysctl_ctx,
4052 SYSCTL_CHILDREN(adapter->sysctl_tree),
4053 OID_AUTO, "int_throttle_ceil",
4054 CTLTYPE_INT|CTLFLAG_RW, adapter, 0,
4055 em_sysctl_int_throttle, "I",
4056 "interrupt throttling rate");
4058 SYSCTL_ADD_PROC(&adapter->sysctl_ctx,
4059 SYSCTL_CHILDREN(adapter->sysctl_tree),
4060 OID_AUTO, "int_tx_nsegs",
4061 CTLTYPE_INT|CTLFLAG_RW, adapter, 0,
4062 em_sysctl_int_tx_nsegs, "I",
4063 "# segments per TX interrupt");
4064 SYSCTL_ADD_INT(&adapter->sysctl_ctx,
4065 SYSCTL_CHILDREN(adapter->sysctl_tree),
4066 OID_AUTO, "wreg_tx_nsegs", CTLFLAG_RW,
4067 &adapter->tx_wreg_nsegs, 0,
4068 "# segments before write to hardware register");
4073 em_sysctl_int_throttle(SYSCTL_HANDLER_ARGS)
4075 struct adapter *adapter = (void *)arg1;
4076 struct ifnet *ifp = &adapter->arpcom.ac_if;
4077 int error, throttle;
4079 throttle = adapter->int_throttle_ceil;
4080 error = sysctl_handle_int(oidp, &throttle, 0, req);
4081 if (error || req->newptr == NULL)
4083 if (throttle < 0 || throttle > 1000000000 / 256)
4088 * Set the interrupt throttling rate in 256ns increments,
4089 * recalculate sysctl value assignment to get exact frequency.
4091 throttle = 1000000000 / 256 / throttle;
4093 /* Upper 16bits of ITR is reserved and should be zero */
4094 if (throttle & 0xffff0000)
4098 lwkt_serialize_enter(ifp->if_serializer);
4101 adapter->int_throttle_ceil = 1000000000 / 256 / throttle;
4103 adapter->int_throttle_ceil = 0;
4105 if (ifp->if_flags & IFF_RUNNING)
4106 em_set_itr(adapter, throttle);
4108 lwkt_serialize_exit(ifp->if_serializer);
4111 if_printf(ifp, "Interrupt moderation set to %d/sec\n",
4112 adapter->int_throttle_ceil);
4118 em_sysctl_int_tx_nsegs(SYSCTL_HANDLER_ARGS)
4120 struct adapter *adapter = (void *)arg1;
4121 struct ifnet *ifp = &adapter->arpcom.ac_if;
4124 segs = adapter->tx_int_nsegs;
4125 error = sysctl_handle_int(oidp, &segs, 0, req);
4126 if (error || req->newptr == NULL)
4131 lwkt_serialize_enter(ifp->if_serializer);
4134 * Don't allow int_tx_nsegs to become:
4135 * o Less the oact_tx_desc
4136 * o Too large that no TX desc will cause TX interrupt to
4137 * be generated (OACTIVE will never recover)
4138 * o Too small that will cause tx_dd[] overflow
4140 if (segs < adapter->oact_tx_desc ||
4141 segs >= adapter->num_tx_desc - adapter->oact_tx_desc ||
4142 segs < adapter->num_tx_desc / EM_TXDD_SAFE) {
4146 adapter->tx_int_nsegs = segs;
4149 lwkt_serialize_exit(ifp->if_serializer);
4155 em_set_itr(struct adapter *adapter, uint32_t itr)
4157 E1000_WRITE_REG(&adapter->hw, E1000_ITR, itr);
4158 if (adapter->hw.mac.type == e1000_82574) {
4162 * When using MSIX interrupts we need to
4163 * throttle using the EITR register
4165 for (i = 0; i < 4; ++i) {
4166 E1000_WRITE_REG(&adapter->hw,
4167 E1000_EITR_82574(i), itr);
4173 em_disable_aspm(struct adapter *adapter)
4175 uint16_t link_cap, link_ctrl, disable;
4176 uint8_t pcie_ptr, reg;
4177 device_t dev = adapter->dev;
4179 switch (adapter->hw.mac.type) {
4184 * 82573 specification update
4185 * errata #8 disable L0s
4186 * errata #41 disable L1
4188 * 82571/82572 specification update
4189 # errata #13 disable L1
4190 * errata #68 disable L0s
4192 disable = PCIEM_LNKCTL_ASPM_L0S | PCIEM_LNKCTL_ASPM_L1;
4198 * 82574 specification update errata #20
4199 * 82583 specification update errata #9
4201 * There is no need to disable L1
4203 disable = PCIEM_LNKCTL_ASPM_L0S;
4210 pcie_ptr = pci_get_pciecap_ptr(dev);
4214 link_cap = pci_read_config(dev, pcie_ptr + PCIER_LINKCAP, 2);
4215 if ((link_cap & PCIEM_LNKCAP_ASPM_MASK) == 0)
4219 if_printf(&adapter->arpcom.ac_if,
4220 "disable ASPM %#02x\n", disable);
4223 reg = pcie_ptr + PCIER_LINKCTRL;
4224 link_ctrl = pci_read_config(dev, reg, 2);
4225 link_ctrl &= ~disable;
4226 pci_write_config(dev, reg, link_ctrl, 2);
4230 em_tso_pullup(struct adapter *adapter, struct mbuf **mp)
4232 int iphlen, hoff, thoff, ex = 0;
4237 KASSERT(M_WRITABLE(m), ("TSO mbuf not writable"));
4239 iphlen = m->m_pkthdr.csum_iphlen;
4240 thoff = m->m_pkthdr.csum_thlen;
4241 hoff = m->m_pkthdr.csum_lhlen;
4243 KASSERT(iphlen > 0, ("invalid ip hlen"));
4244 KASSERT(thoff > 0, ("invalid tcp hlen"));
4245 KASSERT(hoff > 0, ("invalid ether hlen"));
4247 if (adapter->flags & EM_FLAG_TSO_PULLEX)
4250 if (m->m_len < hoff + iphlen + thoff + ex) {
4251 m = m_pullup(m, hoff + iphlen + thoff + ex);
4258 ip = mtodoff(m, struct ip *, hoff);
4265 em_tso_setup(struct adapter *adapter, struct mbuf *mp,
4266 uint32_t *txd_upper, uint32_t *txd_lower)
4268 struct e1000_context_desc *TXD;
4269 int hoff, iphlen, thoff, hlen;
4270 int mss, pktlen, curr_txd;
4272 iphlen = mp->m_pkthdr.csum_iphlen;
4273 thoff = mp->m_pkthdr.csum_thlen;
4274 hoff = mp->m_pkthdr.csum_lhlen;
4275 mss = mp->m_pkthdr.tso_segsz;
4276 pktlen = mp->m_pkthdr.len;
4278 if (adapter->csum_flags == CSUM_TSO &&
4279 adapter->csum_iphlen == iphlen &&
4280 adapter->csum_lhlen == hoff &&
4281 adapter->csum_thlen == thoff &&
4282 adapter->csum_mss == mss &&
4283 adapter->csum_pktlen == pktlen) {
4284 *txd_upper = adapter->csum_txd_upper;
4285 *txd_lower = adapter->csum_txd_lower;
4288 hlen = hoff + iphlen + thoff;
4291 * Setup a new TSO context.
4294 curr_txd = adapter->next_avail_tx_desc;
4295 TXD = (struct e1000_context_desc *)&adapter->tx_desc_base[curr_txd];
4297 *txd_lower = E1000_TXD_CMD_DEXT | /* Extended descr type */
4298 E1000_TXD_DTYP_D | /* Data descr type */
4299 E1000_TXD_CMD_TSE; /* Do TSE on this packet */
4301 /* IP and/or TCP header checksum calculation and insertion. */
4302 *txd_upper = (E1000_TXD_POPTS_IXSM | E1000_TXD_POPTS_TXSM) << 8;
4305 * Start offset for header checksum calculation.
4306 * End offset for header checksum calculation.
4307 * Offset of place put the checksum.
4309 TXD->lower_setup.ip_fields.ipcss = hoff;
4310 TXD->lower_setup.ip_fields.ipcse = htole16(hoff + iphlen - 1);
4311 TXD->lower_setup.ip_fields.ipcso = hoff + offsetof(struct ip, ip_sum);
4314 * Start offset for payload checksum calculation.
4315 * End offset for payload checksum calculation.
4316 * Offset of place to put the checksum.
4318 TXD->upper_setup.tcp_fields.tucss = hoff + iphlen;
4319 TXD->upper_setup.tcp_fields.tucse = 0;
4320 TXD->upper_setup.tcp_fields.tucso =
4321 hoff + iphlen + offsetof(struct tcphdr, th_sum);
4324 * Payload size per packet w/o any headers.
4325 * Length of all headers up to payload.
4327 TXD->tcp_seg_setup.fields.mss = htole16(mss);
4328 TXD->tcp_seg_setup.fields.hdr_len = hlen;
4329 TXD->cmd_and_length = htole32(E1000_TXD_CMD_IFCS |
4330 E1000_TXD_CMD_DEXT | /* Extended descr */
4331 E1000_TXD_CMD_TSE | /* TSE context */
4332 E1000_TXD_CMD_IP | /* Do IP csum */
4333 E1000_TXD_CMD_TCP | /* Do TCP checksum */
4334 (pktlen - hlen)); /* Total len */
4336 /* Save the information for this TSO context */
4337 adapter->csum_flags = CSUM_TSO;
4338 adapter->csum_lhlen = hoff;
4339 adapter->csum_iphlen = iphlen;
4340 adapter->csum_thlen = thoff;
4341 adapter->csum_mss = mss;
4342 adapter->csum_pktlen = pktlen;
4343 adapter->csum_txd_upper = *txd_upper;
4344 adapter->csum_txd_lower = *txd_lower;
4346 if (++curr_txd == adapter->num_tx_desc)
4349 KKASSERT(adapter->num_tx_desc_avail > 0);
4350 adapter->num_tx_desc_avail--;
4352 adapter->next_avail_tx_desc = curr_txd;