1 /* $OpenBSD: if_txp.c,v 1.48 2001/06/27 06:34:50 kjc Exp $ */
2 /* $FreeBSD: src/sys/dev/txp/if_txp.c,v 1.4.2.4 2001/12/14 19:50:43 jlemon Exp $ */
6 * Jason L. Wright <jason@thought.net>, Theo de Raadt, and
7 * Aaron Campbell <aaron@monkey.org>. All rights reserved.
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 * 3. All advertising materials mentioning features or use of this software
18 * must display the following acknowledgement:
19 * This product includes software developed by Jason L. Wright,
20 * Theo de Raadt and Aaron Campbell.
21 * 4. Neither the name of the author nor the names of any co-contributors
22 * may be used to endorse or promote products derived from this software
23 * without specific prior written permission.
25 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY EXPRESS OR
26 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
27 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
28 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
35 * THE POSSIBILITY OF SUCH DAMAGE.
39 * Driver for 3c990 (Typhoon) Ethernet ASIC
42 #include <sys/param.h>
43 #include <sys/systm.h>
44 #include <sys/sockio.h>
46 #include <sys/malloc.h>
47 #include <sys/kernel.h>
48 #include <sys/socket.h>
49 #include <sys/serialize.h>
52 #include <sys/thread2.h>
53 #include <sys/interrupt.h>
56 #include <net/ifq_var.h>
57 #include <net/if_arp.h>
58 #include <net/ethernet.h>
59 #include <net/if_dl.h>
60 #include <net/if_types.h>
61 #include <net/vlan/if_vlan_var.h>
62 #include <net/vlan/if_vlan_ether.h>
64 #include <netinet/in.h>
65 #include <netinet/in_systm.h>
66 #include <netinet/in_var.h>
67 #include <netinet/ip.h>
68 #include <netinet/if_ether.h>
69 #include <sys/in_cksum.h>
71 #include <net/if_media.h>
75 #include <vm/vm.h> /* for vtophys */
76 #include <vm/pmap.h> /* for vtophys */
78 #include "../mii_layer/mii.h"
79 #include "../mii_layer/miivar.h"
81 #include <bus/pci/pcidevs.h>
82 #include <bus/pci/pcireg.h>
83 #include <bus/pci/pcivar.h>
85 #define TXP_USEIOSPACE
86 #define __STRICT_ALIGNMENT
88 #include "if_txpreg.h"
92 * Various supported device vendors/types and their names.
94 static struct txp_type txp_devs[] = {
95 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3CR990TX95,
96 "3Com 3cR990-TX-95 Etherlink with 3XP Processor" },
97 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3CR990TX97,
98 "3Com 3cR990-TX-97 Etherlink with 3XP Processor" },
99 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C990B,
100 "3Com 3cR990B-TXM Etherlink with 3XP Processor" },
101 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3CR990SVR95,
102 "3Com 3cR990-SRV-95 Etherlink Server with 3XP Processor" },
103 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3CR990SVR97,
104 "3Com 3cR990-SRV-97 Etherlink Server with 3XP Processor" },
105 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C990BSVR,
106 "3Com 3cR990B-SRV Etherlink Server with 3XP Processor" },
110 static int txp_probe (device_t);
111 static int txp_attach (device_t);
112 static int txp_detach (device_t);
113 static void txp_intr (void *);
114 static void txp_tick (void *);
115 static int txp_shutdown (device_t);
116 static int txp_ioctl (struct ifnet *, u_long, caddr_t, struct ucred *);
117 static void txp_start (struct ifnet *, struct ifaltq_subque *);
118 static void txp_stop (struct txp_softc *);
119 static void txp_init (void *);
120 static void txp_watchdog (struct ifnet *);
122 static void txp_release_resources (device_t);
123 static int txp_chip_init (struct txp_softc *);
124 static int txp_reset_adapter (struct txp_softc *);
125 static int txp_download_fw (struct txp_softc *);
126 static int txp_download_fw_wait (struct txp_softc *);
127 static int txp_download_fw_section (struct txp_softc *,
128 struct txp_fw_section_header *, int);
129 static int txp_alloc_rings (struct txp_softc *);
130 static int txp_rxring_fill (struct txp_softc *);
131 static void txp_rxring_empty (struct txp_softc *);
132 static void txp_set_filter (struct txp_softc *);
134 static int txp_cmd_desc_numfree (struct txp_softc *);
135 static int txp_command (struct txp_softc *, u_int16_t, u_int16_t, u_int32_t,
136 u_int32_t, u_int16_t *, u_int32_t *, u_int32_t *, int);
137 static int txp_command2 (struct txp_softc *, u_int16_t, u_int16_t,
138 u_int32_t, u_int32_t, struct txp_ext_desc *, u_int8_t,
139 struct txp_rsp_desc **, int);
140 static int txp_response (struct txp_softc *, u_int32_t, u_int16_t, u_int16_t,
141 struct txp_rsp_desc **);
142 static void txp_rsp_fixup (struct txp_softc *, struct txp_rsp_desc *,
143 struct txp_rsp_desc *);
144 static void txp_capabilities (struct txp_softc *);
146 static void txp_ifmedia_sts (struct ifnet *, struct ifmediareq *);
147 static int txp_ifmedia_upd (struct ifnet *);
149 static void txp_show_descriptor (void *);
151 static void txp_tx_reclaim (struct txp_softc *, struct txp_tx_ring *);
152 static void txp_rxbuf_reclaim (struct txp_softc *);
153 static void txp_rx_reclaim (struct txp_softc *, struct txp_rx_ring *);
155 #ifdef TXP_USEIOSPACE
156 #define TXP_RES SYS_RES_IOPORT
157 #define TXP_RID TXP_PCI_LOIO
159 #define TXP_RES SYS_RES_MEMORY
160 #define TXP_RID TXP_PCI_LOMEM
163 static device_method_t txp_methods[] = {
164 /* Device interface */
165 DEVMETHOD(device_probe, txp_probe),
166 DEVMETHOD(device_attach, txp_attach),
167 DEVMETHOD(device_detach, txp_detach),
168 DEVMETHOD(device_shutdown, txp_shutdown),
172 static driver_t txp_driver = {
175 sizeof(struct txp_softc)
178 static devclass_t txp_devclass;
180 DECLARE_DUMMY_MODULE(if_txp);
181 DRIVER_MODULE(if_txp, pci, txp_driver, txp_devclass, NULL, NULL);
184 txp_probe(device_t dev)
189 vid = pci_get_vendor(dev);
190 did = pci_get_device(dev);
192 for (t = txp_devs; t->txp_name != NULL; ++t) {
193 if ((vid == t->txp_vid) && (did == t->txp_did)) {
194 device_set_desc(dev, t->txp_name);
203 txp_attach(device_t dev)
205 struct txp_softc *sc;
209 uint8_t enaddr[ETHER_ADDR_LEN];
212 sc = device_get_softc(dev);
213 callout_init(&sc->txp_stat_timer);
215 ifp = &sc->sc_arpcom.ac_if;
216 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
218 pci_enable_busmaster(dev);
221 sc->sc_res = bus_alloc_resource_any(dev, TXP_RES, &rid, RF_ACTIVE);
223 if (sc->sc_res == NULL) {
224 device_printf(dev, "couldn't map ports/memory\n");
228 sc->sc_bt = rman_get_bustag(sc->sc_res);
229 sc->sc_bh = rman_get_bushandle(sc->sc_res);
231 /* Allocate interrupt */
233 sc->sc_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
234 RF_SHAREABLE | RF_ACTIVE);
236 if (sc->sc_irq == NULL) {
237 device_printf(dev, "couldn't map interrupt\n");
242 if (txp_chip_init(sc)) {
247 sc->sc_fwbuf = contigmalloc(32768, M_DEVBUF,
248 M_WAITOK, 0, 0xffffffff, PAGE_SIZE, 0);
249 error = txp_download_fw(sc);
250 contigfree(sc->sc_fwbuf, 32768, M_DEVBUF);
256 sc->sc_ldata = contigmalloc(sizeof(struct txp_ldata), M_DEVBUF,
257 M_WAITOK | M_ZERO, 0, 0xffffffff, PAGE_SIZE, 0);
259 if (txp_alloc_rings(sc)) {
264 if (txp_command(sc, TXP_CMD_MAX_PKT_SIZE_WRITE, TXP_MAX_PKTLEN, 0, 0,
265 NULL, NULL, NULL, 1)) {
270 if (txp_command(sc, TXP_CMD_STATION_ADDRESS_READ, 0, 0, 0,
271 &p1, &p2, NULL, 1)) {
278 enaddr[0] = ((uint8_t *)&p1)[1];
279 enaddr[1] = ((uint8_t *)&p1)[0];
280 enaddr[2] = ((uint8_t *)&p2)[3];
281 enaddr[3] = ((uint8_t *)&p2)[2];
282 enaddr[4] = ((uint8_t *)&p2)[1];
283 enaddr[5] = ((uint8_t *)&p2)[0];
285 ifmedia_init(&sc->sc_ifmedia, 0, txp_ifmedia_upd, txp_ifmedia_sts);
286 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_10_T, 0, NULL);
287 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_10_T|IFM_HDX, 0, NULL);
288 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL);
289 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_100_TX, 0, NULL);
290 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_100_TX|IFM_HDX, 0, NULL);
291 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_100_TX|IFM_FDX, 0, NULL);
292 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL);
294 sc->sc_xcvr = TXP_XCVR_AUTO;
295 txp_command(sc, TXP_CMD_XCVR_SELECT, TXP_XCVR_AUTO, 0, 0,
296 NULL, NULL, NULL, 0);
297 ifmedia_set(&sc->sc_ifmedia, IFM_ETHER|IFM_AUTO);
300 ifp->if_mtu = ETHERMTU;
301 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
302 ifp->if_ioctl = txp_ioctl;
303 ifp->if_start = txp_start;
304 ifp->if_watchdog = txp_watchdog;
305 ifp->if_init = txp_init;
306 ifp->if_baudrate = 100000000;
307 ifq_set_maxlen(&ifp->if_snd, TX_ENTRIES);
308 ifq_set_ready(&ifp->if_snd);
309 ifp->if_hwassist = 0;
310 txp_capabilities(sc);
312 ether_ifattach(ifp, enaddr, NULL);
314 error = bus_setup_intr(dev, sc->sc_irq, INTR_MPSAFE,
315 txp_intr, sc, &sc->sc_intrhand,
318 device_printf(dev, "couldn't set up irq\n");
323 ifq_set_cpuid(&ifp->if_snd, rman_get_cpuid(sc->sc_irq));
328 txp_release_resources(dev);
333 txp_detach(device_t dev)
335 struct txp_softc *sc = device_get_softc(dev);
336 struct ifnet *ifp = &sc->sc_arpcom.ac_if;
339 lwkt_serialize_enter(ifp->if_serializer);
343 bus_teardown_intr(dev, sc->sc_irq, sc->sc_intrhand);
345 lwkt_serialize_exit(ifp->if_serializer);
347 ifmedia_removeall(&sc->sc_ifmedia);
350 for (i = 0; i < RXBUF_ENTRIES; i++)
351 kfree(sc->sc_rxbufs[i].rb_sd, M_DEVBUF);
353 txp_release_resources(dev);
359 txp_release_resources(device_t dev)
361 struct txp_softc *sc;
363 sc = device_get_softc(dev);
365 if (sc->sc_irq != NULL)
366 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq);
368 if (sc->sc_res != NULL)
369 bus_release_resource(dev, TXP_RES, TXP_RID, sc->sc_res);
371 if (sc->sc_ldata != NULL)
372 contigfree(sc->sc_ldata, sizeof(struct txp_ldata), M_DEVBUF);
378 txp_chip_init(struct txp_softc *sc)
380 /* disable interrupts */
381 WRITE_REG(sc, TXP_IER, 0);
382 WRITE_REG(sc, TXP_IMR,
383 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT |
384 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 |
387 /* ack all interrupts */
388 WRITE_REG(sc, TXP_ISR, TXP_INT_RESERVED | TXP_INT_LATCH |
389 TXP_INT_A2H_7 | TXP_INT_A2H_6 | TXP_INT_A2H_5 | TXP_INT_A2H_4 |
390 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT |
391 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 |
392 TXP_INT_A2H_3 | TXP_INT_A2H_2 | TXP_INT_A2H_1 | TXP_INT_A2H_0);
394 if (txp_reset_adapter(sc))
397 /* disable interrupts */
398 WRITE_REG(sc, TXP_IER, 0);
399 WRITE_REG(sc, TXP_IMR,
400 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT |
401 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 |
404 /* ack all interrupts */
405 WRITE_REG(sc, TXP_ISR, TXP_INT_RESERVED | TXP_INT_LATCH |
406 TXP_INT_A2H_7 | TXP_INT_A2H_6 | TXP_INT_A2H_5 | TXP_INT_A2H_4 |
407 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT |
408 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 |
409 TXP_INT_A2H_3 | TXP_INT_A2H_2 | TXP_INT_A2H_1 | TXP_INT_A2H_0);
415 txp_reset_adapter(struct txp_softc *sc)
420 WRITE_REG(sc, TXP_SRR, TXP_SRR_ALL);
422 WRITE_REG(sc, TXP_SRR, 0);
424 /* Should wait max 6 seconds */
425 for (i = 0; i < 6000; i++) {
426 r = READ_REG(sc, TXP_A2H_0);
427 if (r == STAT_WAITING_FOR_HOST_REQUEST)
432 if (r != STAT_WAITING_FOR_HOST_REQUEST) {
433 if_printf(&sc->sc_arpcom.ac_if, "reset hung\n");
441 txp_download_fw(struct txp_softc *sc)
443 struct txp_fw_file_header *fileheader;
444 struct txp_fw_section_header *secthead;
446 u_int32_t r, i, ier, imr;
448 ier = READ_REG(sc, TXP_IER);
449 WRITE_REG(sc, TXP_IER, ier | TXP_INT_A2H_0);
451 imr = READ_REG(sc, TXP_IMR);
452 WRITE_REG(sc, TXP_IMR, imr | TXP_INT_A2H_0);
454 for (i = 0; i < 10000; i++) {
455 r = READ_REG(sc, TXP_A2H_0);
456 if (r == STAT_WAITING_FOR_HOST_REQUEST)
460 if (r != STAT_WAITING_FOR_HOST_REQUEST) {
461 if_printf(&sc->sc_arpcom.ac_if,
462 "not waiting for host request\n");
467 WRITE_REG(sc, TXP_ISR, TXP_INT_A2H_0);
469 fileheader = (struct txp_fw_file_header *)tc990image;
470 if (bcmp("TYPHOON", fileheader->magicid, sizeof(fileheader->magicid))) {
471 if_printf(&sc->sc_arpcom.ac_if, "fw invalid magic\n");
475 /* Tell boot firmware to get ready for image */
476 WRITE_REG(sc, TXP_H2A_1, fileheader->addr);
477 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_RUNTIME_IMAGE);
479 if (txp_download_fw_wait(sc)) {
480 if_printf(&sc->sc_arpcom.ac_if, "fw wait failed, initial\n");
484 secthead = (struct txp_fw_section_header *)(((u_int8_t *)tc990image) +
485 sizeof(struct txp_fw_file_header));
487 for (sect = 0; sect < fileheader->nsections; sect++) {
488 if (txp_download_fw_section(sc, secthead, sect))
490 secthead = (struct txp_fw_section_header *)
491 (((u_int8_t *)secthead) + secthead->nbytes +
495 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_DOWNLOAD_COMPLETE);
497 for (i = 0; i < 10000; i++) {
498 r = READ_REG(sc, TXP_A2H_0);
499 if (r == STAT_WAITING_FOR_BOOT)
503 if (r != STAT_WAITING_FOR_BOOT) {
504 if_printf(&sc->sc_arpcom.ac_if, "not waiting for boot\n");
508 WRITE_REG(sc, TXP_IER, ier);
509 WRITE_REG(sc, TXP_IMR, imr);
515 txp_download_fw_wait(struct txp_softc *sc)
519 for (i = 0; i < 10000; i++) {
520 r = READ_REG(sc, TXP_ISR);
521 if (r & TXP_INT_A2H_0)
526 if (!(r & TXP_INT_A2H_0)) {
527 if_printf(&sc->sc_arpcom.ac_if, "fw wait failed comm0\n");
531 WRITE_REG(sc, TXP_ISR, TXP_INT_A2H_0);
533 r = READ_REG(sc, TXP_A2H_0);
534 if (r != STAT_WAITING_FOR_SEGMENT) {
535 if_printf(&sc->sc_arpcom.ac_if, "fw not waiting for segment\n");
542 txp_download_fw_section(struct txp_softc *sc,
543 struct txp_fw_section_header *sect, int sectnum)
550 /* Skip zero length sections */
551 if (sect->nbytes == 0)
554 /* Make sure we aren't past the end of the image */
555 rseg = ((u_int8_t *)sect) - ((u_int8_t *)tc990image);
556 if (rseg >= sizeof(tc990image)) {
557 if_printf(&sc->sc_arpcom.ac_if, "fw invalid section address, "
558 "section %d\n", sectnum);
562 /* Make sure this section doesn't go past the end */
563 rseg += sect->nbytes;
564 if (rseg >= sizeof(tc990image)) {
565 if_printf(&sc->sc_arpcom.ac_if, "fw truncated section %d\n",
570 bcopy(((u_int8_t *)sect) + sizeof(*sect), sc->sc_fwbuf, sect->nbytes);
571 dma = vtophys(sc->sc_fwbuf);
574 * dummy up mbuf and verify section checksum
577 m.m_next = m.m_nextpkt = NULL;
578 m.m_len = sect->nbytes;
579 m.m_data = sc->sc_fwbuf;
581 csum = in_cksum(&m, sect->nbytes);
582 if (csum != sect->cksum) {
583 if_printf(&sc->sc_arpcom.ac_if, "fw section %d, bad "
584 "cksum (expected 0x%x got 0x%x)\n",
585 sectnum, sect->cksum, csum);
590 WRITE_REG(sc, TXP_H2A_1, sect->nbytes);
591 WRITE_REG(sc, TXP_H2A_2, sect->cksum);
592 WRITE_REG(sc, TXP_H2A_3, sect->addr);
593 WRITE_REG(sc, TXP_H2A_4, 0);
594 WRITE_REG(sc, TXP_H2A_5, dma & 0xffffffff);
595 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_SEGMENT_AVAILABLE);
597 if (txp_download_fw_wait(sc)) {
598 if_printf(&sc->sc_arpcom.ac_if, "fw wait failed, "
599 "section %d\n", sectnum);
610 struct txp_softc *sc = vsc;
611 struct txp_hostvar *hv = sc->sc_hostvar;
614 /* mask all interrupts */
615 WRITE_REG(sc, TXP_IMR, TXP_INT_RESERVED | TXP_INT_SELF |
616 TXP_INT_A2H_7 | TXP_INT_A2H_6 | TXP_INT_A2H_5 | TXP_INT_A2H_4 |
617 TXP_INT_A2H_2 | TXP_INT_A2H_1 | TXP_INT_A2H_0 |
618 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 |
619 TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | TXP_INT_LATCH);
621 isr = READ_REG(sc, TXP_ISR);
623 WRITE_REG(sc, TXP_ISR, isr);
625 if ((*sc->sc_rxhir.r_roff) != (*sc->sc_rxhir.r_woff))
626 txp_rx_reclaim(sc, &sc->sc_rxhir);
627 if ((*sc->sc_rxlor.r_roff) != (*sc->sc_rxlor.r_woff))
628 txp_rx_reclaim(sc, &sc->sc_rxlor);
630 if (hv->hv_rx_buf_write_idx == hv->hv_rx_buf_read_idx)
631 txp_rxbuf_reclaim(sc);
633 if (sc->sc_txhir.r_cnt && (sc->sc_txhir.r_cons !=
634 TXP_OFFSET2IDX(*(sc->sc_txhir.r_off))))
635 txp_tx_reclaim(sc, &sc->sc_txhir);
637 if (sc->sc_txlor.r_cnt && (sc->sc_txlor.r_cons !=
638 TXP_OFFSET2IDX(*(sc->sc_txlor.r_off))))
639 txp_tx_reclaim(sc, &sc->sc_txlor);
641 isr = READ_REG(sc, TXP_ISR);
644 /* unmask all interrupts */
645 WRITE_REG(sc, TXP_IMR, TXP_INT_A2H_3);
647 if_devstart(&sc->sc_arpcom.ac_if);
651 txp_rx_reclaim(struct txp_softc *sc, struct txp_rx_ring *r)
653 struct ifnet *ifp = &sc->sc_arpcom.ac_if;
654 struct txp_rx_desc *rxd;
656 struct txp_swdesc *sd = NULL;
657 u_int32_t roff, woff;
661 rxd = r->r_desc + (roff / sizeof(struct txp_rx_desc));
663 while (roff != woff) {
665 if (rxd->rx_flags & RX_FLAGS_ERROR) {
666 if_printf(ifp, "error 0x%x\n", rxd->rx_stat);
671 /* retrieve stashed pointer */
677 m->m_pkthdr.len = m->m_len = rxd->rx_len;
679 #ifdef __STRICT_ALIGNMENT
682 * XXX Nice chip, except it won't accept "off by 2"
683 * buffers, so we're force to copy. Supposedly
684 * this will be fixed in a newer firmware rev
685 * and this will be temporary.
689 MGETHDR(mnew, MB_DONTWAIT, MT_DATA);
694 if (m->m_len > (MHLEN - 2)) {
695 MCLGET(mnew, MB_DONTWAIT);
696 if (!(mnew->m_flags & M_EXT)) {
702 mnew->m_pkthdr.rcvif = ifp;
704 mnew->m_pkthdr.len = mnew->m_len = m->m_len;
705 m_copydata(m, 0, m->m_pkthdr.len, mtod(mnew, caddr_t));
711 if (rxd->rx_stat & RX_STAT_IPCKSUMBAD)
712 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
713 else if (rxd->rx_stat & RX_STAT_IPCKSUMGOOD)
714 m->m_pkthdr.csum_flags |=
715 CSUM_IP_CHECKED|CSUM_IP_VALID;
717 if ((rxd->rx_stat & RX_STAT_TCPCKSUMGOOD) ||
718 (rxd->rx_stat & RX_STAT_UDPCKSUMGOOD)) {
719 m->m_pkthdr.csum_flags |=
720 CSUM_DATA_VALID|CSUM_PSEUDO_HDR|
721 CSUM_FRAG_NOT_CHECKED;
722 m->m_pkthdr.csum_data = 0xffff;
725 if (rxd->rx_stat & RX_STAT_VLAN) {
726 m->m_flags |= M_VLANTAG;
727 m->m_pkthdr.ether_vlantag = htons(rxd->rx_vlan >> 16);
729 ifp->if_input(ifp, m);
733 roff += sizeof(struct txp_rx_desc);
734 if (roff == (RX_ENTRIES * sizeof(struct txp_rx_desc))) {
748 txp_rxbuf_reclaim(struct txp_softc *sc)
750 struct ifnet *ifp = &sc->sc_arpcom.ac_if;
751 struct txp_hostvar *hv = sc->sc_hostvar;
752 struct txp_rxbuf_desc *rbd;
753 struct txp_swdesc *sd;
756 if (!(ifp->if_flags & IFF_RUNNING))
759 i = sc->sc_rxbufprod;
760 rbd = sc->sc_rxbufs + i;
764 if (sd->sd_mbuf != NULL)
767 MGETHDR(sd->sd_mbuf, MB_DONTWAIT, MT_DATA);
768 if (sd->sd_mbuf == NULL)
771 MCLGET(sd->sd_mbuf, MB_DONTWAIT);
772 if ((sd->sd_mbuf->m_flags & M_EXT) == 0)
774 sd->sd_mbuf->m_pkthdr.rcvif = ifp;
775 sd->sd_mbuf->m_pkthdr.len = sd->sd_mbuf->m_len = MCLBYTES;
777 rbd->rb_paddrlo = vtophys(mtod(sd->sd_mbuf, vm_offset_t))
781 hv->hv_rx_buf_write_idx = TXP_IDX2OFFSET(i);
783 if (++i == RXBUF_ENTRIES) {
790 sc->sc_rxbufprod = i;
795 m_freem(sd->sd_mbuf);
801 * Reclaim mbufs and entries from a transmit ring.
804 txp_tx_reclaim(struct txp_softc *sc, struct txp_tx_ring *r)
806 struct ifnet *ifp = &sc->sc_arpcom.ac_if;
807 u_int32_t idx = TXP_OFFSET2IDX(*(r->r_off));
808 u_int32_t cons = r->r_cons, cnt = r->r_cnt;
809 struct txp_tx_desc *txd = r->r_desc + cons;
810 struct txp_swdesc *sd = sc->sc_txd + cons;
813 while (cons != idx) {
817 if ((txd->tx_flags & TX_FLAGS_TYPE_M) ==
818 TX_FLAGS_TYPE_DATA) {
827 ifq_clr_oactive(&ifp->if_snd);
829 if (++cons == TX_ENTRIES) {
848 txp_shutdown(device_t dev)
850 struct txp_softc *sc;
853 sc = device_get_softc(dev);
854 ifp = &sc->sc_arpcom.ac_if;
855 lwkt_serialize_enter(ifp->if_serializer);
857 /* mask all interrupts */
858 WRITE_REG(sc, TXP_IMR,
859 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT |
860 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 |
863 txp_command(sc, TXP_CMD_TX_DISABLE, 0, 0, 0, NULL, NULL, NULL, 0);
864 txp_command(sc, TXP_CMD_RX_DISABLE, 0, 0, 0, NULL, NULL, NULL, 0);
865 txp_command(sc, TXP_CMD_HALT, 0, 0, 0, NULL, NULL, NULL, 0);
867 lwkt_serialize_exit(ifp->if_serializer);
872 txp_alloc_rings(struct txp_softc *sc)
874 struct txp_boot_record *boot;
875 struct txp_ldata *ld;
880 boot = &ld->txp_boot;
886 bzero(&ld->txp_hostvar, sizeof(struct txp_hostvar));
887 boot->br_hostvar_lo = vtophys(&ld->txp_hostvar);
888 boot->br_hostvar_hi = 0;
889 sc->sc_hostvar = (struct txp_hostvar *)&ld->txp_hostvar;
891 /* hi priority tx ring */
892 boot->br_txhipri_lo = vtophys(&ld->txp_txhiring);
893 boot->br_txhipri_hi = 0;
894 boot->br_txhipri_siz = TX_ENTRIES * sizeof(struct txp_tx_desc);
895 sc->sc_txhir.r_reg = TXP_H2A_1;
896 sc->sc_txhir.r_desc = (struct txp_tx_desc *)&ld->txp_txhiring;
897 sc->sc_txhir.r_cons = sc->sc_txhir.r_prod = sc->sc_txhir.r_cnt = 0;
898 sc->sc_txhir.r_off = &sc->sc_hostvar->hv_tx_hi_desc_read_idx;
900 /* lo priority tx ring */
901 boot->br_txlopri_lo = vtophys(&ld->txp_txloring);
902 boot->br_txlopri_hi = 0;
903 boot->br_txlopri_siz = TX_ENTRIES * sizeof(struct txp_tx_desc);
904 sc->sc_txlor.r_reg = TXP_H2A_3;
905 sc->sc_txlor.r_desc = (struct txp_tx_desc *)&ld->txp_txloring;
906 sc->sc_txlor.r_cons = sc->sc_txlor.r_prod = sc->sc_txlor.r_cnt = 0;
907 sc->sc_txlor.r_off = &sc->sc_hostvar->hv_tx_lo_desc_read_idx;
909 /* high priority rx ring */
910 boot->br_rxhipri_lo = vtophys(&ld->txp_rxhiring);
911 boot->br_rxhipri_hi = 0;
912 boot->br_rxhipri_siz = RX_ENTRIES * sizeof(struct txp_rx_desc);
913 sc->sc_rxhir.r_desc = (struct txp_rx_desc *)&ld->txp_rxhiring;
914 sc->sc_rxhir.r_roff = &sc->sc_hostvar->hv_rx_hi_read_idx;
915 sc->sc_rxhir.r_woff = &sc->sc_hostvar->hv_rx_hi_write_idx;
917 /* low priority rx ring */
918 boot->br_rxlopri_lo = vtophys(&ld->txp_rxloring);
919 boot->br_rxlopri_hi = 0;
920 boot->br_rxlopri_siz = RX_ENTRIES * sizeof(struct txp_rx_desc);
921 sc->sc_rxlor.r_desc = (struct txp_rx_desc *)&ld->txp_rxloring;
922 sc->sc_rxlor.r_roff = &sc->sc_hostvar->hv_rx_lo_read_idx;
923 sc->sc_rxlor.r_woff = &sc->sc_hostvar->hv_rx_lo_write_idx;
926 bzero(&ld->txp_cmdring, sizeof(struct txp_cmd_desc) * CMD_ENTRIES);
927 boot->br_cmd_lo = vtophys(&ld->txp_cmdring);
929 boot->br_cmd_siz = CMD_ENTRIES * sizeof(struct txp_cmd_desc);
930 sc->sc_cmdring.base = (struct txp_cmd_desc *)&ld->txp_cmdring;
931 sc->sc_cmdring.size = CMD_ENTRIES * sizeof(struct txp_cmd_desc);
932 sc->sc_cmdring.lastwrite = 0;
935 bzero(&ld->txp_rspring, sizeof(struct txp_rsp_desc) * RSP_ENTRIES);
936 boot->br_resp_lo = vtophys(&ld->txp_rspring);
937 boot->br_resp_hi = 0;
938 boot->br_resp_siz = CMD_ENTRIES * sizeof(struct txp_rsp_desc);
939 sc->sc_rspring.base = (struct txp_rsp_desc *)&ld->txp_rspring;
940 sc->sc_rspring.size = RSP_ENTRIES * sizeof(struct txp_rsp_desc);
941 sc->sc_rspring.lastwrite = 0;
943 /* receive buffer ring */
944 boot->br_rxbuf_lo = vtophys(&ld->txp_rxbufs);
945 boot->br_rxbuf_hi = 0;
946 boot->br_rxbuf_siz = RXBUF_ENTRIES * sizeof(struct txp_rxbuf_desc);
947 sc->sc_rxbufs = (struct txp_rxbuf_desc *)&ld->txp_rxbufs;
949 for (i = 0; i < RXBUF_ENTRIES; i++) {
950 struct txp_swdesc *sd;
951 if (sc->sc_rxbufs[i].rb_sd != NULL)
953 sc->sc_rxbufs[i].rb_sd = kmalloc(sizeof(struct txp_swdesc),
955 sd = sc->sc_rxbufs[i].rb_sd;
958 sc->sc_rxbufprod = 0;
961 bzero(&ld->txp_zero, sizeof(u_int32_t));
962 boot->br_zero_lo = vtophys(&ld->txp_zero);
963 boot->br_zero_hi = 0;
965 /* See if it's waiting for boot, and try to boot it */
966 for (i = 0; i < 10000; i++) {
967 r = READ_REG(sc, TXP_A2H_0);
968 if (r == STAT_WAITING_FOR_BOOT)
973 if (r != STAT_WAITING_FOR_BOOT) {
974 if_printf(&sc->sc_arpcom.ac_if, "not waiting for boot\n");
978 WRITE_REG(sc, TXP_H2A_2, 0);
979 WRITE_REG(sc, TXP_H2A_1, vtophys(sc->sc_boot));
980 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_REGISTER_BOOT_RECORD);
982 /* See if it booted */
983 for (i = 0; i < 10000; i++) {
984 r = READ_REG(sc, TXP_A2H_0);
985 if (r == STAT_RUNNING)
989 if (r != STAT_RUNNING) {
990 if_printf(&sc->sc_arpcom.ac_if, "fw not running\n");
994 /* Clear TX and CMD ring write registers */
995 WRITE_REG(sc, TXP_H2A_1, TXP_BOOTCMD_NULL);
996 WRITE_REG(sc, TXP_H2A_2, TXP_BOOTCMD_NULL);
997 WRITE_REG(sc, TXP_H2A_3, TXP_BOOTCMD_NULL);
998 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_NULL);
1004 txp_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
1006 struct txp_softc *sc = ifp->if_softc;
1007 struct ifreq *ifr = (struct ifreq *)data;
1012 if (ifp->if_flags & IFF_UP) {
1015 if (ifp->if_flags & IFF_RUNNING)
1022 * Multicast list has changed; set the hardware
1023 * filter accordingly.
1030 error = ifmedia_ioctl(ifp, ifr, &sc->sc_ifmedia, command);
1033 error = ether_ioctl(ifp, command, data);
1040 txp_rxring_fill(struct txp_softc *sc)
1044 struct txp_swdesc *sd;
1046 ifp = &sc->sc_arpcom.ac_if;
1048 for (i = 0; i < RXBUF_ENTRIES; i++) {
1049 sd = sc->sc_rxbufs[i].rb_sd;
1050 MGETHDR(sd->sd_mbuf, MB_DONTWAIT, MT_DATA);
1051 if (sd->sd_mbuf == NULL)
1054 MCLGET(sd->sd_mbuf, MB_DONTWAIT);
1055 if ((sd->sd_mbuf->m_flags & M_EXT) == 0) {
1056 m_freem(sd->sd_mbuf);
1059 sd->sd_mbuf->m_pkthdr.len = sd->sd_mbuf->m_len = MCLBYTES;
1060 sd->sd_mbuf->m_pkthdr.rcvif = ifp;
1062 sc->sc_rxbufs[i].rb_paddrlo =
1063 vtophys(mtod(sd->sd_mbuf, vm_offset_t));
1064 sc->sc_rxbufs[i].rb_paddrhi = 0;
1067 sc->sc_hostvar->hv_rx_buf_write_idx = (RXBUF_ENTRIES - 1) *
1068 sizeof(struct txp_rxbuf_desc);
1074 txp_rxring_empty(struct txp_softc *sc)
1077 struct txp_swdesc *sd;
1079 if (sc->sc_rxbufs == NULL)
1082 for (i = 0; i < RXBUF_ENTRIES; i++) {
1083 if (&sc->sc_rxbufs[i] == NULL)
1085 sd = sc->sc_rxbufs[i].rb_sd;
1088 if (sd->sd_mbuf != NULL) {
1089 m_freem(sd->sd_mbuf);
1100 struct txp_softc *sc;
1106 ifp = &sc->sc_arpcom.ac_if;
1108 if (ifp->if_flags & IFF_RUNNING)
1113 txp_command(sc, TXP_CMD_MAX_PKT_SIZE_WRITE, TXP_MAX_PKTLEN, 0, 0,
1114 NULL, NULL, NULL, 1);
1116 /* Set station address. */
1117 ((u_int8_t *)&p1)[1] = sc->sc_arpcom.ac_enaddr[0];
1118 ((u_int8_t *)&p1)[0] = sc->sc_arpcom.ac_enaddr[1];
1119 ((u_int8_t *)&p2)[3] = sc->sc_arpcom.ac_enaddr[2];
1120 ((u_int8_t *)&p2)[2] = sc->sc_arpcom.ac_enaddr[3];
1121 ((u_int8_t *)&p2)[1] = sc->sc_arpcom.ac_enaddr[4];
1122 ((u_int8_t *)&p2)[0] = sc->sc_arpcom.ac_enaddr[5];
1123 txp_command(sc, TXP_CMD_STATION_ADDRESS_WRITE, p1, p2, 0,
1124 NULL, NULL, NULL, 1);
1128 txp_rxring_fill(sc);
1130 txp_command(sc, TXP_CMD_TX_ENABLE, 0, 0, 0, NULL, NULL, NULL, 1);
1131 txp_command(sc, TXP_CMD_RX_ENABLE, 0, 0, 0, NULL, NULL, NULL, 1);
1133 WRITE_REG(sc, TXP_IER, TXP_INT_RESERVED | TXP_INT_SELF |
1134 TXP_INT_A2H_7 | TXP_INT_A2H_6 | TXP_INT_A2H_5 | TXP_INT_A2H_4 |
1135 TXP_INT_A2H_2 | TXP_INT_A2H_1 | TXP_INT_A2H_0 |
1136 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 |
1137 TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | TXP_INT_LATCH);
1138 WRITE_REG(sc, TXP_IMR, TXP_INT_A2H_3);
1140 ifp->if_flags |= IFF_RUNNING;
1141 ifq_clr_oactive(&ifp->if_snd);
1144 callout_reset(&sc->txp_stat_timer, hz, txp_tick, sc);
1150 struct txp_softc *sc = vsc;
1151 struct ifnet *ifp = &sc->sc_arpcom.ac_if;
1152 struct txp_rsp_desc *rsp = NULL;
1153 struct txp_ext_desc *ext;
1155 lwkt_serialize_enter(ifp->if_serializer);
1156 txp_rxbuf_reclaim(sc);
1158 if (txp_command2(sc, TXP_CMD_READ_STATISTICS, 0, 0, 0, NULL, 0,
1161 if (rsp->rsp_numdesc != 6)
1163 if (txp_command(sc, TXP_CMD_CLEAR_STATISTICS, 0, 0, 0,
1164 NULL, NULL, NULL, 1))
1166 ext = (struct txp_ext_desc *)(rsp + 1);
1168 ifp->if_ierrors += ext[3].ext_2 + ext[3].ext_3 + ext[3].ext_4 +
1169 ext[4].ext_1 + ext[4].ext_4;
1170 ifp->if_oerrors += ext[0].ext_1 + ext[1].ext_1 + ext[1].ext_4 +
1172 ifp->if_collisions += ext[0].ext_2 + ext[0].ext_3 + ext[1].ext_2 +
1174 ifp->if_opackets += rsp->rsp_par2;
1175 ifp->if_ipackets += ext[2].ext_3;
1179 kfree(rsp, M_DEVBUF);
1181 callout_reset(&sc->txp_stat_timer, hz, txp_tick, sc);
1182 lwkt_serialize_exit(ifp->if_serializer);
1186 txp_start(struct ifnet *ifp, struct ifaltq_subque *ifsq)
1188 struct txp_softc *sc = ifp->if_softc;
1189 struct txp_tx_ring *r = &sc->sc_txhir;
1190 struct txp_tx_desc *txd;
1191 struct txp_frag_desc *fxd;
1192 struct mbuf *m, *m0, *m_defragged;
1193 struct txp_swdesc *sd;
1194 u_int32_t firstprod, firstcnt, prod, cnt;
1196 ASSERT_ALTQ_SQ_DEFAULT(ifp, ifsq);
1198 if ((ifp->if_flags & IFF_RUNNING) == 0 || ifq_is_oactive(&ifp->if_snd))
1210 if ((TX_ENTRIES - cnt) < 4)
1214 m = ifq_dequeue(&ifp->if_snd, NULL);
1218 frag = 1; /* Extra desc */
1219 for (m0 = m; m0 != NULL; m0 = m0->m_next)
1221 if ((cnt + frag) >= (TX_ENTRIES - 4)) {
1222 if (m_defragged != NULL) {
1224 * Even after defragmentation, there
1225 * are still too many fragments, so
1232 m_defragged = m_defrag(m, MB_DONTWAIT);
1233 if (m_defragged == NULL) {
1239 /* Recount # of fragments */
1243 sd = sc->sc_txd + prod;
1246 txd = r->r_desc + prod;
1247 txd->tx_flags = TX_FLAGS_TYPE_DATA;
1248 txd->tx_numdesc = 0;
1254 if (++prod == TX_ENTRIES)
1258 KASSERT(cnt < (TX_ENTRIES - 4), ("too many frag"));
1260 if (m->m_flags & M_VLANTAG) {
1261 txd->tx_pflags = TX_PFLAGS_VLAN |
1262 (htons(m->m_pkthdr.ether_vlantag) <<
1263 TX_PFLAGS_VLANTAG_S);
1266 if (m->m_pkthdr.csum_flags & CSUM_IP)
1267 txd->tx_pflags |= TX_PFLAGS_IPCKSUM;
1270 if (m->m_pkthdr.csum_flags & CSUM_TCP)
1271 txd->tx_pflags |= TX_PFLAGS_TCPCKSUM;
1272 if (m->m_pkthdr.csum_flags & CSUM_UDP)
1273 txd->tx_pflags |= TX_PFLAGS_UDPCKSUM;
1276 fxd = (struct txp_frag_desc *)(r->r_desc + prod);
1277 for (m0 = m; m0 != NULL; m0 = m0->m_next) {
1282 KASSERT(cnt < (TX_ENTRIES - 4), ("too many frag"));
1286 fxd->frag_flags = FRAG_FLAGS_TYPE_FRAG;
1287 fxd->frag_rsvd1 = 0;
1288 fxd->frag_len = m0->m_len;
1289 fxd->frag_addrlo = vtophys(mtod(m0, vm_offset_t));
1290 fxd->frag_addrhi = 0;
1291 fxd->frag_rsvd2 = 0;
1293 if (++prod == TX_ENTRIES) {
1294 fxd = (struct txp_frag_desc *)r->r_desc;
1302 ETHER_BPF_MTAP(ifp, m);
1303 WRITE_REG(sc, r->r_reg, TXP_IDX2OFFSET(prod));
1311 ifq_set_oactive(&ifp->if_snd);
1312 r->r_prod = firstprod;
1313 r->r_cnt = firstcnt;
1318 * Handle simple commands sent to the typhoon
1321 txp_command(struct txp_softc *sc, u_int16_t id, u_int16_t in1, u_int32_t in2,
1322 u_int32_t in3, u_int16_t *out1, u_int32_t *out2, u_int32_t *out3,
1325 struct txp_rsp_desc *rsp = NULL;
1327 if (txp_command2(sc, id, in1, in2, in3, NULL, 0, &rsp, wait))
1334 *out1 = rsp->rsp_par1;
1336 *out2 = rsp->rsp_par2;
1338 *out3 = rsp->rsp_par3;
1339 kfree(rsp, M_DEVBUF);
1344 txp_command2(struct txp_softc *sc, u_int16_t id, u_int16_t in1, u_int32_t in2,
1345 u_int32_t in3, struct txp_ext_desc *in_extp, u_int8_t in_extn,
1346 struct txp_rsp_desc **rspp, int wait)
1348 struct txp_hostvar *hv = sc->sc_hostvar;
1349 struct txp_cmd_desc *cmd;
1350 struct txp_ext_desc *ext;
1354 if (txp_cmd_desc_numfree(sc) < (in_extn + 1)) {
1355 if_printf(&sc->sc_arpcom.ac_if, "no free cmd descriptors\n");
1359 idx = sc->sc_cmdring.lastwrite;
1360 cmd = (struct txp_cmd_desc *)(((u_int8_t *)sc->sc_cmdring.base) + idx);
1361 bzero(cmd, sizeof(*cmd));
1363 cmd->cmd_numdesc = in_extn;
1364 cmd->cmd_seq = seq = sc->sc_seq++;
1366 cmd->cmd_par1 = in1;
1367 cmd->cmd_par2 = in2;
1368 cmd->cmd_par3 = in3;
1369 cmd->cmd_flags = CMD_FLAGS_TYPE_CMD |
1370 (wait ? CMD_FLAGS_RESP : 0) | CMD_FLAGS_VALID;
1372 idx += sizeof(struct txp_cmd_desc);
1373 if (idx == sc->sc_cmdring.size)
1376 for (i = 0; i < in_extn; i++) {
1377 ext = (struct txp_ext_desc *)(((u_int8_t *)sc->sc_cmdring.base) + idx);
1378 bcopy(in_extp, ext, sizeof(struct txp_ext_desc));
1380 idx += sizeof(struct txp_cmd_desc);
1381 if (idx == sc->sc_cmdring.size)
1385 sc->sc_cmdring.lastwrite = idx;
1387 WRITE_REG(sc, TXP_H2A_2, sc->sc_cmdring.lastwrite);
1392 for (i = 0; i < 10000; i++) {
1393 idx = hv->hv_resp_read_idx;
1394 if (idx != hv->hv_resp_write_idx) {
1396 if (txp_response(sc, idx, id, seq, rspp))
1403 if (i == 1000 || (*rspp) == NULL) {
1404 if_printf(&sc->sc_arpcom.ac_if, "0x%x command failed\n", id);
1412 txp_response(struct txp_softc *sc, u_int32_t ridx, u_int16_t id, u_int16_t seq,
1413 struct txp_rsp_desc **rspp)
1415 struct txp_hostvar *hv = sc->sc_hostvar;
1416 struct txp_rsp_desc *rsp;
1418 while (ridx != hv->hv_resp_write_idx) {
1419 rsp = (struct txp_rsp_desc *)(((u_int8_t *)sc->sc_rspring.base) + ridx);
1421 if (id == rsp->rsp_id && rsp->rsp_seq == seq) {
1422 *rspp = (struct txp_rsp_desc *)kmalloc(
1423 sizeof(struct txp_rsp_desc) * (rsp->rsp_numdesc + 1),
1424 M_DEVBUF, M_INTWAIT);
1425 if ((*rspp) == NULL)
1427 txp_rsp_fixup(sc, rsp, *rspp);
1431 if (rsp->rsp_flags & RSP_FLAGS_ERROR) {
1432 if_printf(&sc->sc_arpcom.ac_if, "response error!\n");
1433 txp_rsp_fixup(sc, rsp, NULL);
1434 ridx = hv->hv_resp_read_idx;
1438 switch (rsp->rsp_id) {
1439 case TXP_CMD_CYCLE_STATISTICS:
1440 case TXP_CMD_MEDIA_STATUS_READ:
1442 case TXP_CMD_HELLO_RESPONSE:
1443 if_printf(&sc->sc_arpcom.ac_if, "hello\n");
1446 if_printf(&sc->sc_arpcom.ac_if, "unknown id(0x%x)\n",
1450 txp_rsp_fixup(sc, rsp, NULL);
1451 ridx = hv->hv_resp_read_idx;
1452 hv->hv_resp_read_idx = ridx;
1459 txp_rsp_fixup(struct txp_softc *sc, struct txp_rsp_desc *rsp,
1460 struct txp_rsp_desc *dst)
1462 struct txp_rsp_desc *src = rsp;
1463 struct txp_hostvar *hv = sc->sc_hostvar;
1466 ridx = hv->hv_resp_read_idx;
1468 for (i = 0; i < rsp->rsp_numdesc + 1; i++) {
1470 bcopy(src, dst++, sizeof(struct txp_rsp_desc));
1471 ridx += sizeof(struct txp_rsp_desc);
1472 if (ridx == sc->sc_rspring.size) {
1473 src = sc->sc_rspring.base;
1477 sc->sc_rspring.lastwrite = hv->hv_resp_read_idx = ridx;
1480 hv->hv_resp_read_idx = ridx;
1484 txp_cmd_desc_numfree(struct txp_softc *sc)
1486 struct txp_hostvar *hv = sc->sc_hostvar;
1487 struct txp_boot_record *br = sc->sc_boot;
1488 u_int32_t widx, ridx, nfree;
1490 widx = sc->sc_cmdring.lastwrite;
1491 ridx = hv->hv_cmd_read_idx;
1494 /* Ring is completely free */
1495 nfree = br->br_cmd_siz - sizeof(struct txp_cmd_desc);
1498 nfree = br->br_cmd_siz -
1499 (widx - ridx + sizeof(struct txp_cmd_desc));
1501 nfree = ridx - widx - sizeof(struct txp_cmd_desc);
1504 return (nfree / sizeof(struct txp_cmd_desc));
1508 txp_stop(struct txp_softc *sc)
1512 ifp = &sc->sc_arpcom.ac_if;
1514 ifp->if_flags &= ~IFF_RUNNING;
1515 ifq_clr_oactive(&ifp->if_snd);
1517 callout_stop(&sc->txp_stat_timer);
1519 txp_command(sc, TXP_CMD_TX_DISABLE, 0, 0, 0, NULL, NULL, NULL, 1);
1520 txp_command(sc, TXP_CMD_RX_DISABLE, 0, 0, 0, NULL, NULL, NULL, 1);
1522 txp_rxring_empty(sc);
1528 txp_watchdog(struct ifnet *ifp)
1534 txp_ifmedia_upd(struct ifnet *ifp)
1536 struct txp_softc *sc = ifp->if_softc;
1537 struct ifmedia *ifm = &sc->sc_ifmedia;
1540 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
1543 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_10_T) {
1544 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
1545 new_xcvr = TXP_XCVR_10_FDX;
1547 new_xcvr = TXP_XCVR_10_HDX;
1548 } else if (IFM_SUBTYPE(ifm->ifm_media) == IFM_100_TX) {
1549 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
1550 new_xcvr = TXP_XCVR_100_FDX;
1552 new_xcvr = TXP_XCVR_100_HDX;
1553 } else if (IFM_SUBTYPE(ifm->ifm_media) == IFM_AUTO) {
1554 new_xcvr = TXP_XCVR_AUTO;
1559 if (sc->sc_xcvr == new_xcvr)
1562 txp_command(sc, TXP_CMD_XCVR_SELECT, new_xcvr, 0, 0,
1563 NULL, NULL, NULL, 0);
1564 sc->sc_xcvr = new_xcvr;
1570 txp_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
1572 struct txp_softc *sc = ifp->if_softc;
1573 struct ifmedia *ifm = &sc->sc_ifmedia;
1574 u_int16_t bmsr, bmcr, anlpar;
1576 ifmr->ifm_status = IFM_AVALID;
1577 ifmr->ifm_active = IFM_ETHER;
1579 if (txp_command(sc, TXP_CMD_PHY_MGMT_READ, 0, MII_BMSR, 0,
1580 &bmsr, NULL, NULL, 1))
1582 if (txp_command(sc, TXP_CMD_PHY_MGMT_READ, 0, MII_BMSR, 0,
1583 &bmsr, NULL, NULL, 1))
1586 if (txp_command(sc, TXP_CMD_PHY_MGMT_READ, 0, MII_BMCR, 0,
1587 &bmcr, NULL, NULL, 1))
1590 if (txp_command(sc, TXP_CMD_PHY_MGMT_READ, 0, MII_ANLPAR, 0,
1591 &anlpar, NULL, NULL, 1))
1594 if (bmsr & BMSR_LINK)
1595 ifmr->ifm_status |= IFM_ACTIVE;
1597 if (bmcr & BMCR_ISO) {
1598 ifmr->ifm_active |= IFM_NONE;
1599 ifmr->ifm_status = 0;
1603 if (bmcr & BMCR_LOOP)
1604 ifmr->ifm_active |= IFM_LOOP;
1606 if (bmcr & BMCR_AUTOEN) {
1607 if ((bmsr & BMSR_ACOMP) == 0) {
1608 ifmr->ifm_active |= IFM_NONE;
1612 if (anlpar & ANLPAR_T4)
1613 ifmr->ifm_active |= IFM_100_T4;
1614 else if (anlpar & ANLPAR_TX_FD)
1615 ifmr->ifm_active |= IFM_100_TX|IFM_FDX;
1616 else if (anlpar & ANLPAR_TX)
1617 ifmr->ifm_active |= IFM_100_TX;
1618 else if (anlpar & ANLPAR_10_FD)
1619 ifmr->ifm_active |= IFM_10_T|IFM_FDX;
1620 else if (anlpar & ANLPAR_10)
1621 ifmr->ifm_active |= IFM_10_T;
1623 ifmr->ifm_active |= IFM_NONE;
1625 ifmr->ifm_active = ifm->ifm_cur->ifm_media;
1629 ifmr->ifm_active |= IFM_NONE;
1630 ifmr->ifm_status &= ~IFM_AVALID;
1635 txp_show_descriptor(void *d)
1637 struct txp_cmd_desc *cmd = d;
1638 struct txp_rsp_desc *rsp = d;
1639 struct txp_tx_desc *txd = d;
1640 struct txp_frag_desc *frgd = d;
1642 switch (cmd->cmd_flags & CMD_FLAGS_TYPE_M) {
1643 case CMD_FLAGS_TYPE_CMD:
1644 /* command descriptor */
1645 kprintf("[cmd flags 0x%x num %d id %d seq %d par1 0x%x par2 0x%x par3 0x%x]\n",
1646 cmd->cmd_flags, cmd->cmd_numdesc, cmd->cmd_id, cmd->cmd_seq,
1647 cmd->cmd_par1, cmd->cmd_par2, cmd->cmd_par3);
1649 case CMD_FLAGS_TYPE_RESP:
1650 /* response descriptor */
1651 kprintf("[rsp flags 0x%x num %d id %d seq %d par1 0x%x par2 0x%x par3 0x%x]\n",
1652 rsp->rsp_flags, rsp->rsp_numdesc, rsp->rsp_id, rsp->rsp_seq,
1653 rsp->rsp_par1, rsp->rsp_par2, rsp->rsp_par3);
1655 case CMD_FLAGS_TYPE_DATA:
1656 /* data header (assuming tx for now) */
1657 kprintf("[data flags 0x%x num %d totlen %d addr 0x%x/0x%x pflags 0x%x]",
1658 txd->tx_flags, txd->tx_numdesc, txd->tx_totlen,
1659 txd->tx_addrlo, txd->tx_addrhi, txd->tx_pflags);
1661 case CMD_FLAGS_TYPE_FRAG:
1662 /* fragment descriptor */
1663 kprintf("[frag flags 0x%x rsvd1 0x%x len %d addr 0x%x/0x%x rsvd2 0x%x]",
1664 frgd->frag_flags, frgd->frag_rsvd1, frgd->frag_len,
1665 frgd->frag_addrlo, frgd->frag_addrhi, frgd->frag_rsvd2);
1668 kprintf("[unknown(%x) flags 0x%x num %d id %d seq %d par1 0x%x par2 0x%x par3 0x%x]\n",
1669 cmd->cmd_flags & CMD_FLAGS_TYPE_M,
1670 cmd->cmd_flags, cmd->cmd_numdesc, cmd->cmd_id, cmd->cmd_seq,
1671 cmd->cmd_par1, cmd->cmd_par2, cmd->cmd_par3);
1678 txp_set_filter(struct txp_softc *sc)
1680 struct ifnet *ifp = &sc->sc_arpcom.ac_if;
1682 struct ifmultiaddr *ifma;
1684 if (ifp->if_flags & IFF_PROMISC) {
1685 filter = TXP_RXFILT_PROMISC;
1689 filter = TXP_RXFILT_DIRECT;
1691 if (ifp->if_flags & IFF_BROADCAST)
1692 filter |= TXP_RXFILT_BROADCAST;
1694 if (ifp->if_flags & IFF_ALLMULTI) {
1695 filter |= TXP_RXFILT_ALLMULTI;
1697 uint32_t hashbit, hash[2];
1700 hash[0] = hash[1] = 0;
1702 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1703 if (ifma->ifma_addr->sa_family != AF_LINK)
1707 hashbit = (uint16_t)(ether_crc32_be(
1708 LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
1709 ETHER_ADDR_LEN) & (64 - 1));
1710 hash[hashbit / 32] |= (1 << hashbit % 32);
1714 filter |= TXP_RXFILT_HASHMULTI;
1715 txp_command(sc, TXP_CMD_MCAST_HASH_MASK_WRITE,
1716 2, hash[0], hash[1], NULL, NULL, NULL, 0);
1721 txp_command(sc, TXP_CMD_RX_FILTER_WRITE, filter, 0, 0,
1722 NULL, NULL, NULL, 1);
1726 txp_capabilities(struct txp_softc *sc)
1728 struct ifnet *ifp = &sc->sc_arpcom.ac_if;
1729 struct txp_rsp_desc *rsp = NULL;
1730 struct txp_ext_desc *ext;
1732 if (txp_command2(sc, TXP_CMD_OFFLOAD_READ, 0, 0, 0, NULL, 0, &rsp, 1))
1735 if (rsp->rsp_numdesc != 1)
1737 ext = (struct txp_ext_desc *)(rsp + 1);
1739 sc->sc_tx_capability = ext->ext_1 & OFFLOAD_MASK;
1740 sc->sc_rx_capability = ext->ext_2 & OFFLOAD_MASK;
1741 ifp->if_capabilities = 0;
1743 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_VLAN) {
1744 sc->sc_tx_capability |= OFFLOAD_VLAN;
1745 sc->sc_rx_capability |= OFFLOAD_VLAN;
1746 ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING;
1751 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_IPSEC) {
1752 sc->sc_tx_capability |= OFFLOAD_IPSEC;
1753 sc->sc_rx_capability |= OFFLOAD_IPSEC;
1754 ifp->if_capabilities |= IFCAP_IPSEC;
1758 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_IPCKSUM) {
1759 sc->sc_tx_capability |= OFFLOAD_IPCKSUM;
1760 sc->sc_rx_capability |= OFFLOAD_IPCKSUM;
1761 ifp->if_capabilities |= IFCAP_HWCSUM;
1762 ifp->if_hwassist |= CSUM_IP;
1765 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_TCPCKSUM) {
1767 sc->sc_tx_capability |= OFFLOAD_TCPCKSUM;
1769 sc->sc_rx_capability |= OFFLOAD_TCPCKSUM;
1770 ifp->if_capabilities |= IFCAP_HWCSUM;
1773 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_UDPCKSUM) {
1775 sc->sc_tx_capability |= OFFLOAD_UDPCKSUM;
1777 sc->sc_rx_capability |= OFFLOAD_UDPCKSUM;
1778 ifp->if_capabilities |= IFCAP_HWCSUM;
1780 ifp->if_capenable = ifp->if_capabilities;
1782 if (txp_command(sc, TXP_CMD_OFFLOAD_WRITE, 0,
1783 sc->sc_tx_capability, sc->sc_rx_capability, NULL, NULL, NULL, 1))
1788 kfree(rsp, M_DEVBUF);