2 * Copyright (c) 2008 The DragonFly Project. All rights reserved.
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5 * modification, are permitted provided that the following conditions
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18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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21 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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31 * from: vector.s, 386BSD 0.1 unknown origin
32 * $FreeBSD: src/sys/i386/isa/icu_vector.s,v 1.14.2.2 2000/07/18 21:12:42 dfr Exp $
35 * WARNING! SMP builds can use the ICU now so this code must be MP safe.
38 #include "opt_auto_eoi.h"
40 #include <machine/asmacros.h>
41 #include <machine/lock.h>
42 #include <machine/psl.h>
43 #include <machine/trap.h>
44 #include <machine/segments.h>
45 #include <machine_base/icu/icu.h>
46 #include <machine_base/icu/icu_ipl.h>
48 #include <bus/isa/isa.h>
52 #define ICU_EOI 0x20 /* XXX - define elsewhere */
54 #define IRQ_LBIT(irq_num) (1 << (irq_num))
55 #define IRQ_BIT(irq_num) (1 << ((irq_num) % 8))
56 #define IRQ_BYTE(irq_num) ((irq_num) >> 3)
59 #define ENABLE_ICU1 /* use auto-EOI to reduce i/o */
63 movb $ICU_EOI,%al ; /* as soon as possible send EOI ... */ \
64 OUTB_ICU1 ; /* ... to clear in service bit */ \
73 * The data sheet says no auto-EOI on slave, but it sometimes works.
75 #define ENABLE_ICU1_AND_2 ENABLE_ICU1
77 #define ENABLE_ICU1_AND_2 \
78 movb $ICU_EOI,%al ; /* as above */ \
79 outb %al,$IO_ICU2 ; /* but do second icu first ... */ \
80 OUTB_ICU1 ; /* ... then first icu (if !AUTO_EOI_1) */ \
87 #define ICU_PUSH_FRAME \
88 PUSH_FRAME ; /* 15 regs + space for 5 extras */ \
89 movl $0,TF_XFLAGS(%rsp) ; \
90 movl $0,TF_TRAPNO(%rsp) ; \
91 movl $0,TF_ADDR(%rsp) ; \
92 movl $0,TF_FLAGS(%rsp) ; \
93 movl $0,TF_ERR(%rsp) ; \
96 #define MASK_IRQ(icu, irq_num) \
98 movb icu_imen + IRQ_BYTE(irq_num),%al ; \
99 orb $IRQ_BIT(irq_num),%al ; \
100 movb %al,icu_imen + IRQ_BYTE(irq_num) ; \
101 outb %al,$icu+ICU_IMR_OFFSET ; \
104 #define UNMASK_IRQ(icu, irq_num) \
108 movb icu_imen + IRQ_BYTE(irq_num),%al ; \
109 andb $~IRQ_BIT(irq_num),%al ; \
110 movb %al,icu_imen + IRQ_BYTE(irq_num) ; \
111 outb %al,$icu+ICU_IMR_OFFSET ; \
116 * Interrupt call handlers run in the following sequence:
118 * - Push the trap frame required by doreti.
119 * - Mask the interrupt and reenable its source.
120 * - If we cannot take the interrupt set its ipending bit and
122 * - If we can take the interrupt clear its ipending bit,
123 * call the handler, then unmask the interrupt and doreti.
125 * YYY can cache gd base pointer instead of using hidden %fs
129 #define INTR_HANDLER(irq_num, icu, enable_icus) \
132 IDTVEC(icu_intr##irq_num) ; \
134 FAKE_MCOUNT(TF_RIP(%rsp)) ; \
135 MASK_IRQ(icu, irq_num) ; \
137 movq PCPU(curthread),%rbx ; \
138 testl $-1,TD_NEST_COUNT(%rbx) ; \
140 testl $-1,TD_CRITCOUNT(%rbx) ; \
143 /* set pending bit and return, leave interrupt masked */ \
145 orq $IRQ_LBIT(irq_num),PCPU_E8(ipending,%rdx) ; \
146 orl $RQF_INTPEND, PCPU(reqflags) ; \
149 /* clear pending bit, run handler */ \
151 andq $~IRQ_LBIT(irq_num),PCPU_E8(ipending,%rdx) ; \
153 movq %rsp,%rdi ; /* rdi = call argument */ \
154 incl TD_CRITCOUNT(%rbx) ; \
156 call ithread_fast_handler ; /* returns 0 to unmask int */ \
157 decl TD_CRITCOUNT(%rbx) ; \
158 addq $8,%rsp ; /* intr frame -> trap frame */ \
159 UNMASK_IRQ(icu, irq_num) ; \
165 INTR_HANDLER(0, IO_ICU1, ENABLE_ICU1)
166 INTR_HANDLER(1, IO_ICU1, ENABLE_ICU1)
167 INTR_HANDLER(2, IO_ICU1, ENABLE_ICU1)
168 INTR_HANDLER(3, IO_ICU1, ENABLE_ICU1)
169 INTR_HANDLER(4, IO_ICU1, ENABLE_ICU1)
170 INTR_HANDLER(5, IO_ICU1, ENABLE_ICU1)
171 INTR_HANDLER(6, IO_ICU1, ENABLE_ICU1)
172 INTR_HANDLER(7, IO_ICU1, ENABLE_ICU1)
173 INTR_HANDLER(8, IO_ICU2, ENABLE_ICU1_AND_2)
174 INTR_HANDLER(9, IO_ICU2, ENABLE_ICU1_AND_2)
175 INTR_HANDLER(10, IO_ICU2, ENABLE_ICU1_AND_2)
176 INTR_HANDLER(11, IO_ICU2, ENABLE_ICU1_AND_2)
177 INTR_HANDLER(12, IO_ICU2, ENABLE_ICU1_AND_2)
178 INTR_HANDLER(13, IO_ICU2, ENABLE_ICU1_AND_2)
179 INTR_HANDLER(14, IO_ICU2, ENABLE_ICU1_AND_2)
180 INTR_HANDLER(15, IO_ICU2, ENABLE_ICU1_AND_2)