igb: Remove unused code
[dragonfly.git] / sys / dev / netif / igb / if_igb.c
1 /*
2  * Copyright (c) 2001-2011, Intel Corporation 
3  * All rights reserved.
4  * 
5  * Redistribution and use in source and binary forms, with or without 
6  * modification, are permitted provided that the following conditions are met:
7  * 
8  *  1. Redistributions of source code must retain the above copyright notice, 
9  *     this list of conditions and the following disclaimer.
10  * 
11  *  2. Redistributions in binary form must reproduce the above copyright 
12  *     notice, this list of conditions and the following disclaimer in the 
13  *     documentation and/or other materials provided with the distribution.
14  * 
15  *  3. Neither the name of the Intel Corporation nor the names of its 
16  *     contributors may be used to endorse or promote products derived from 
17  *     this software without specific prior written permission.
18  * 
19  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 
21  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 
22  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 
23  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 
24  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 
25  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
26  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
27  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
28  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29  * POSSIBILITY OF SUCH DAMAGE.
30  */
31
32 #include "opt_ifpoll.h"
33 #include "opt_igb.h"
34
35 #include <sys/param.h>
36 #include <sys/bus.h>
37 #include <sys/endian.h>
38 #include <sys/interrupt.h>
39 #include <sys/kernel.h>
40 #include <sys/malloc.h>
41 #include <sys/mbuf.h>
42 #include <sys/proc.h>
43 #include <sys/rman.h>
44 #include <sys/serialize.h>
45 #include <sys/serialize2.h>
46 #include <sys/socket.h>
47 #include <sys/sockio.h>
48 #include <sys/sysctl.h>
49 #include <sys/systm.h>
50
51 #include <net/bpf.h>
52 #include <net/ethernet.h>
53 #include <net/if.h>
54 #include <net/if_arp.h>
55 #include <net/if_dl.h>
56 #include <net/if_media.h>
57 #include <net/ifq_var.h>
58 #include <net/toeplitz.h>
59 #include <net/toeplitz2.h>
60 #include <net/vlan/if_vlan_var.h>
61 #include <net/vlan/if_vlan_ether.h>
62 #include <net/if_poll.h>
63
64 #include <netinet/in_systm.h>
65 #include <netinet/in.h>
66 #include <netinet/ip.h>
67 #include <netinet/tcp.h>
68 #include <netinet/udp.h>
69
70 #include <bus/pci/pcivar.h>
71 #include <bus/pci/pcireg.h>
72
73 #include <dev/netif/ig_hal/e1000_api.h>
74 #include <dev/netif/ig_hal/e1000_82575.h>
75 #include <dev/netif/igb/if_igb.h>
76
77 #ifdef IGB_RSS_DEBUG
78 #define IGB_RSS_DPRINTF(sc, lvl, fmt, ...) \
79 do { \
80         if (sc->rss_debug >= lvl) \
81                 if_printf(&sc->arpcom.ac_if, fmt, __VA_ARGS__); \
82 } while (0)
83 #else   /* !IGB_RSS_DEBUG */
84 #define IGB_RSS_DPRINTF(sc, lvl, fmt, ...)      ((void)0)
85 #endif  /* IGB_RSS_DEBUG */
86
87 #define IGB_NAME        "Intel(R) PRO/1000 "
88 #define IGB_DEVICE(id)  \
89         { IGB_VENDOR_ID, E1000_DEV_ID_##id, IGB_NAME #id }
90 #define IGB_DEVICE_NULL { 0, 0, NULL }
91
92 static struct igb_device {
93         uint16_t        vid;
94         uint16_t        did;
95         const char      *desc;
96 } igb_devices[] = {
97         IGB_DEVICE(82575EB_COPPER),
98         IGB_DEVICE(82575EB_FIBER_SERDES),
99         IGB_DEVICE(82575GB_QUAD_COPPER),
100         IGB_DEVICE(82576),
101         IGB_DEVICE(82576_NS),
102         IGB_DEVICE(82576_NS_SERDES),
103         IGB_DEVICE(82576_FIBER),
104         IGB_DEVICE(82576_SERDES),
105         IGB_DEVICE(82576_SERDES_QUAD),
106         IGB_DEVICE(82576_QUAD_COPPER),
107         IGB_DEVICE(82576_QUAD_COPPER_ET2),
108         IGB_DEVICE(82576_VF),
109         IGB_DEVICE(82580_COPPER),
110         IGB_DEVICE(82580_FIBER),
111         IGB_DEVICE(82580_SERDES),
112         IGB_DEVICE(82580_SGMII),
113         IGB_DEVICE(82580_COPPER_DUAL),
114         IGB_DEVICE(82580_QUAD_FIBER),
115         IGB_DEVICE(DH89XXCC_SERDES),
116         IGB_DEVICE(DH89XXCC_SGMII),
117         IGB_DEVICE(DH89XXCC_SFP),
118         IGB_DEVICE(DH89XXCC_BACKPLANE),
119         IGB_DEVICE(I350_COPPER),
120         IGB_DEVICE(I350_FIBER),
121         IGB_DEVICE(I350_SERDES),
122         IGB_DEVICE(I350_SGMII),
123         IGB_DEVICE(I350_VF),
124
125         /* required last entry */
126         IGB_DEVICE_NULL
127 };
128
129 static int      igb_probe(device_t);
130 static int      igb_attach(device_t);
131 static int      igb_detach(device_t);
132 static int      igb_shutdown(device_t);
133 static int      igb_suspend(device_t);
134 static int      igb_resume(device_t);
135
136 static boolean_t igb_is_valid_ether_addr(const uint8_t *);
137 static void     igb_setup_ifp(struct igb_softc *);
138 static boolean_t igb_txcsum_ctx(struct igb_tx_ring *, struct mbuf *);
139 static int      igb_tso_pullup(struct igb_tx_ring *, struct mbuf **);
140 static void     igb_tso_ctx(struct igb_tx_ring *, struct mbuf *, uint32_t *);
141 static void     igb_add_sysctl(struct igb_softc *);
142 static int      igb_sysctl_intr_rate(SYSCTL_HANDLER_ARGS);
143 static int      igb_sysctl_msix_rate(SYSCTL_HANDLER_ARGS);
144 static int      igb_sysctl_tx_intr_nsegs(SYSCTL_HANDLER_ARGS);
145 static void     igb_set_ring_inuse(struct igb_softc *, boolean_t);
146 #ifdef IFPOLL_ENABLE
147 static int      igb_sysctl_npoll_rxoff(SYSCTL_HANDLER_ARGS);
148 static int      igb_sysctl_npoll_txoff(SYSCTL_HANDLER_ARGS);
149 #endif
150
151 static void     igb_vf_init_stats(struct igb_softc *);
152 static void     igb_reset(struct igb_softc *);
153 static void     igb_update_stats_counters(struct igb_softc *);
154 static void     igb_update_vf_stats_counters(struct igb_softc *);
155 static void     igb_update_link_status(struct igb_softc *);
156 static void     igb_init_tx_unit(struct igb_softc *);
157 static void     igb_init_rx_unit(struct igb_softc *);
158
159 static void     igb_set_vlan(struct igb_softc *);
160 static void     igb_set_multi(struct igb_softc *);
161 static void     igb_set_promisc(struct igb_softc *);
162 static void     igb_disable_promisc(struct igb_softc *);
163
164 static int      igb_alloc_rings(struct igb_softc *);
165 static void     igb_free_rings(struct igb_softc *);
166 static int      igb_create_tx_ring(struct igb_tx_ring *);
167 static int      igb_create_rx_ring(struct igb_rx_ring *);
168 static void     igb_free_tx_ring(struct igb_tx_ring *);
169 static void     igb_free_rx_ring(struct igb_rx_ring *);
170 static void     igb_destroy_tx_ring(struct igb_tx_ring *, int);
171 static void     igb_destroy_rx_ring(struct igb_rx_ring *, int);
172 static void     igb_init_tx_ring(struct igb_tx_ring *);
173 static int      igb_init_rx_ring(struct igb_rx_ring *);
174 static int      igb_newbuf(struct igb_rx_ring *, int, boolean_t);
175 static int      igb_encap(struct igb_tx_ring *, struct mbuf **);
176
177 static void     igb_stop(struct igb_softc *);
178 static void     igb_init(void *);
179 static int      igb_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
180 static void     igb_media_status(struct ifnet *, struct ifmediareq *);
181 static int      igb_media_change(struct ifnet *);
182 static void     igb_timer(void *);
183 static void     igb_watchdog(struct ifnet *);
184 static void     igb_start(struct ifnet *);
185 #ifdef IFPOLL_ENABLE
186 static void     igb_npoll(struct ifnet *, struct ifpoll_info *);
187 static void     igb_npoll_rx(struct ifnet *, void *, int);
188 static void     igb_npoll_tx(struct ifnet *, void *, int);
189 static void     igb_npoll_status(struct ifnet *, int);
190 #endif
191 static void     igb_serialize(struct ifnet *, enum ifnet_serialize);
192 static void     igb_deserialize(struct ifnet *, enum ifnet_serialize);
193 static int      igb_tryserialize(struct ifnet *, enum ifnet_serialize);
194 #ifdef INVARIANTS
195 static void     igb_serialize_assert(struct ifnet *, enum ifnet_serialize,
196                     boolean_t);
197 #endif
198
199 static void     igb_intr(void *);
200 static void     igb_intr_shared(void *);
201 static void     igb_rxeof(struct igb_rx_ring *, int);
202 static void     igb_txeof(struct igb_tx_ring *);
203 static void     igb_set_eitr(struct igb_softc *, int, int);
204 static void     igb_enable_intr(struct igb_softc *);
205 static void     igb_disable_intr(struct igb_softc *);
206 static void     igb_init_unshared_intr(struct igb_softc *);
207 static void     igb_init_intr(struct igb_softc *);
208 static int      igb_setup_intr(struct igb_softc *);
209 static void     igb_set_txintr_mask(struct igb_tx_ring *, int *, int);
210 static void     igb_set_rxintr_mask(struct igb_rx_ring *, int *, int);
211 static void     igb_set_intr_mask(struct igb_softc *);
212 static int      igb_alloc_intr(struct igb_softc *);
213 static void     igb_free_intr(struct igb_softc *);
214 static void     igb_teardown_intr(struct igb_softc *);
215 static void     igb_msix_try_alloc(struct igb_softc *);
216 static void     igb_msix_free(struct igb_softc *, boolean_t);
217 static int      igb_msix_setup(struct igb_softc *);
218 static void     igb_msix_teardown(struct igb_softc *, int);
219 static void     igb_msix_rx(void *);
220 static void     igb_msix_tx(void *);
221 static void     igb_msix_status(void *);
222
223 /* Management and WOL Support */
224 static void     igb_get_mgmt(struct igb_softc *);
225 static void     igb_rel_mgmt(struct igb_softc *);
226 static void     igb_get_hw_control(struct igb_softc *);
227 static void     igb_rel_hw_control(struct igb_softc *);
228 static void     igb_enable_wol(device_t);
229
230 static device_method_t igb_methods[] = {
231         /* Device interface */
232         DEVMETHOD(device_probe,         igb_probe),
233         DEVMETHOD(device_attach,        igb_attach),
234         DEVMETHOD(device_detach,        igb_detach),
235         DEVMETHOD(device_shutdown,      igb_shutdown),
236         DEVMETHOD(device_suspend,       igb_suspend),
237         DEVMETHOD(device_resume,        igb_resume),
238         { 0, 0 }
239 };
240
241 static driver_t igb_driver = {
242         "igb",
243         igb_methods,
244         sizeof(struct igb_softc),
245 };
246
247 static devclass_t igb_devclass;
248
249 DECLARE_DUMMY_MODULE(if_igb);
250 MODULE_DEPEND(igb, ig_hal, 1, 1, 1);
251 DRIVER_MODULE(if_igb, pci, igb_driver, igb_devclass, NULL, NULL);
252
253 static int      igb_rxd = IGB_DEFAULT_RXD;
254 static int      igb_txd = IGB_DEFAULT_TXD;
255 static int      igb_rxr = 0;
256 static int      igb_msi_enable = 1;
257 static int      igb_msix_enable = 1;
258 static int      igb_eee_disabled = 1;   /* Energy Efficient Ethernet */
259 static int      igb_fc_setting = e1000_fc_full;
260
261 /*
262  * DMA Coalescing, only for i350 - default to off,
263  * this feature is for power savings
264  */
265 static int      igb_dma_coalesce = 0;
266
267 TUNABLE_INT("hw.igb.rxd", &igb_rxd);
268 TUNABLE_INT("hw.igb.txd", &igb_txd);
269 TUNABLE_INT("hw.igb.rxr", &igb_rxr);
270 TUNABLE_INT("hw.igb.msi.enable", &igb_msi_enable);
271 TUNABLE_INT("hw.igb.msix.enable", &igb_msix_enable);
272 TUNABLE_INT("hw.igb.fc_setting", &igb_fc_setting);
273
274 /* i350 specific */
275 TUNABLE_INT("hw.igb.eee_disabled", &igb_eee_disabled);
276 TUNABLE_INT("hw.igb.dma_coalesce", &igb_dma_coalesce);
277
278 static __inline void
279 igb_rxcsum(uint32_t staterr, struct mbuf *mp)
280 {
281         /* Ignore Checksum bit is set */
282         if (staterr & E1000_RXD_STAT_IXSM)
283                 return;
284
285         if ((staterr & (E1000_RXD_STAT_IPCS | E1000_RXDEXT_STATERR_IPE)) ==
286             E1000_RXD_STAT_IPCS)
287                 mp->m_pkthdr.csum_flags |= CSUM_IP_CHECKED | CSUM_IP_VALID;
288
289         if (staterr & (E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS)) {
290                 if ((staterr & E1000_RXDEXT_STATERR_TCPE) == 0) {
291                         mp->m_pkthdr.csum_flags |= CSUM_DATA_VALID |
292                             CSUM_PSEUDO_HDR | CSUM_FRAG_NOT_CHECKED;
293                         mp->m_pkthdr.csum_data = htons(0xffff);
294                 }
295         }
296 }
297
298 static __inline struct pktinfo *
299 igb_rssinfo(struct mbuf *m, struct pktinfo *pi,
300     uint32_t hash, uint32_t hashtype, uint32_t staterr)
301 {
302         switch (hashtype) {
303         case E1000_RXDADV_RSSTYPE_IPV4_TCP:
304                 pi->pi_netisr = NETISR_IP;
305                 pi->pi_flags = 0;
306                 pi->pi_l3proto = IPPROTO_TCP;
307                 break;
308
309         case E1000_RXDADV_RSSTYPE_IPV4:
310                 if (staterr & E1000_RXD_STAT_IXSM)
311                         return NULL;
312
313                 if ((staterr &
314                      (E1000_RXD_STAT_TCPCS | E1000_RXDEXT_STATERR_TCPE)) ==
315                     E1000_RXD_STAT_TCPCS) {
316                         pi->pi_netisr = NETISR_IP;
317                         pi->pi_flags = 0;
318                         pi->pi_l3proto = IPPROTO_UDP;
319                         break;
320                 }
321                 /* FALL THROUGH */
322         default:
323                 return NULL;
324         }
325
326         m->m_flags |= M_HASH;
327         m->m_pkthdr.hash = toeplitz_hash(hash);
328         return pi;
329 }
330
331 static int
332 igb_probe(device_t dev)
333 {
334         const struct igb_device *d;
335         uint16_t vid, did;
336
337         vid = pci_get_vendor(dev);
338         did = pci_get_device(dev);
339
340         for (d = igb_devices; d->desc != NULL; ++d) {
341                 if (vid == d->vid && did == d->did) {
342                         device_set_desc(dev, d->desc);
343                         return 0;
344                 }
345         }
346         return ENXIO;
347 }
348
349 static int
350 igb_attach(device_t dev)
351 {
352         struct igb_softc *sc = device_get_softc(dev);
353         uint16_t eeprom_data;
354         int error = 0, i, j, ring_max;
355 #ifdef IFPOLL_ENABLE
356         int offset, offset_def;
357 #endif
358
359 #ifdef notyet
360         /* SYSCTL stuff */
361         SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
362             SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
363             OID_AUTO, "nvm", CTLTYPE_INT|CTLFLAG_RW, adapter, 0,
364             igb_sysctl_nvm_info, "I", "NVM Information");
365         SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
366             SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
367             OID_AUTO, "flow_control", CTLTYPE_INT|CTLFLAG_RW,
368             adapter, 0, igb_set_flowcntl, "I", "Flow Control");
369 #endif
370
371         callout_init_mp(&sc->timer);
372         lwkt_serialize_init(&sc->main_serialize);
373
374         if_initname(&sc->arpcom.ac_if, device_get_name(dev),
375             device_get_unit(dev));
376         sc->dev = sc->osdep.dev = dev;
377
378         /*
379          * Determine hardware and mac type
380          */
381         sc->hw.vendor_id = pci_get_vendor(dev);
382         sc->hw.device_id = pci_get_device(dev);
383         sc->hw.revision_id = pci_read_config(dev, PCIR_REVID, 1);
384         sc->hw.subsystem_vendor_id = pci_read_config(dev, PCIR_SUBVEND_0, 2);
385         sc->hw.subsystem_device_id = pci_read_config(dev, PCIR_SUBDEV_0, 2);
386
387         if (e1000_set_mac_type(&sc->hw))
388                 return ENXIO;
389
390         /* Are we a VF device? */
391         if (sc->hw.mac.type == e1000_vfadapt ||
392             sc->hw.mac.type == e1000_vfadapt_i350)
393                 sc->vf_ifp = 1;
394         else
395                 sc->vf_ifp = 0;
396
397         /*
398          * Configure total supported RX/TX ring count
399          */
400         switch (sc->hw.mac.type) {
401         case e1000_82575:
402                 ring_max = IGB_MAX_RING_82575;
403                 break;
404         case e1000_82580:
405                 ring_max = IGB_MAX_RING_82580;
406                 break;
407         case e1000_i350:
408                 ring_max = IGB_MAX_RING_I350;
409                 break;
410         case e1000_82576:
411                 ring_max = IGB_MAX_RING_82576;
412                 break;
413         default:
414                 ring_max = IGB_MIN_RING;
415                 break;
416         }
417         sc->rx_ring_cnt = device_getenv_int(dev, "rxr", igb_rxr);
418         sc->rx_ring_cnt = if_ring_count2(sc->rx_ring_cnt, ring_max);
419 #ifdef IGB_RSS_DEBUG
420         sc->rx_ring_cnt = device_getenv_int(dev, "rxr_debug", sc->rx_ring_cnt);
421 #endif
422         sc->rx_ring_inuse = sc->rx_ring_cnt;
423         sc->tx_ring_cnt = 1; /* XXX */
424
425         if (sc->hw.mac.type == e1000_82575)
426                 sc->flags |= IGB_FLAG_TSO_IPLEN0;
427
428         /* Enable bus mastering */
429         pci_enable_busmaster(dev);
430
431         /*
432          * Allocate IO memory
433          */
434         sc->mem_rid = PCIR_BAR(0);
435         sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->mem_rid,
436             RF_ACTIVE);
437         if (sc->mem_res == NULL) {
438                 device_printf(dev, "Unable to allocate bus resource: memory\n");
439                 error = ENXIO;
440                 goto failed;
441         }
442         sc->osdep.mem_bus_space_tag = rman_get_bustag(sc->mem_res);
443         sc->osdep.mem_bus_space_handle = rman_get_bushandle(sc->mem_res);
444
445         sc->hw.hw_addr = (uint8_t *)&sc->osdep.mem_bus_space_handle;
446
447         /* Save PCI command register for Shared Code */
448         sc->hw.bus.pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2);
449         sc->hw.back = &sc->osdep;
450
451         /* Do Shared Code initialization */
452         if (e1000_setup_init_funcs(&sc->hw, TRUE)) {
453                 device_printf(dev, "Setup of Shared code failed\n");
454                 error = ENXIO;
455                 goto failed;
456         }
457
458         e1000_get_bus_info(&sc->hw);
459
460         sc->hw.mac.autoneg = DO_AUTO_NEG;
461         sc->hw.phy.autoneg_wait_to_complete = FALSE;
462         sc->hw.phy.autoneg_advertised = AUTONEG_ADV_DEFAULT;
463
464         /* Copper options */
465         if (sc->hw.phy.media_type == e1000_media_type_copper) {
466                 sc->hw.phy.mdix = AUTO_ALL_MODES;
467                 sc->hw.phy.disable_polarity_correction = FALSE;
468                 sc->hw.phy.ms_type = IGB_MASTER_SLAVE;
469         }
470
471         /* Set the frame limits assuming  standard ethernet sized frames. */
472         sc->max_frame_size = ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN;
473
474         /* Allocate RX/TX rings */
475         error = igb_alloc_rings(sc);
476         if (error)
477                 goto failed;
478
479 #ifdef IFPOLL_ENABLE
480         /*
481          * NPOLLING RX CPU offset
482          */
483         if (sc->rx_ring_cnt == ncpus2) {
484                 offset = 0;
485         } else {
486                 offset_def = (sc->rx_ring_cnt * device_get_unit(dev)) % ncpus2;
487                 offset = device_getenv_int(dev, "npoll.rxoff", offset_def);
488                 if (offset >= ncpus2 ||
489                     offset % sc->rx_ring_cnt != 0) {
490                         device_printf(dev, "invalid npoll.rxoff %d, use %d\n",
491                             offset, offset_def);
492                         offset = offset_def;
493                 }
494         }
495         sc->rx_npoll_off = offset;
496
497         /*
498          * NPOLLING TX CPU offset
499          */
500         offset_def = sc->rx_npoll_off;
501         offset = device_getenv_int(dev, "npoll.txoff", offset_def);
502         if (offset >= ncpus2) {
503                 device_printf(dev, "invalid npoll.txoff %d, use %d\n",
504                     offset, offset_def);
505                 offset = offset_def;
506         }
507         sc->tx_npoll_off = offset;
508 #endif
509
510         /* Allocate interrupt */
511         error = igb_alloc_intr(sc);
512         if (error)
513                 goto failed;
514
515         /*
516          * Setup serializers
517          */
518         i = 0;
519         sc->serializes[i++] = &sc->main_serialize;
520
521         sc->tx_serialize = i;
522         for (j = 0; j < sc->tx_ring_cnt; ++j)
523                 sc->serializes[i++] = &sc->tx_rings[j].tx_serialize;
524
525         sc->rx_serialize = i;
526         for (j = 0; j < sc->rx_ring_cnt; ++j)
527                 sc->serializes[i++] = &sc->rx_rings[j].rx_serialize;
528
529         sc->serialize_cnt = i;
530         KKASSERT(sc->serialize_cnt <= IGB_NSERIALIZE);
531
532         /* Allocate the appropriate stats memory */
533         if (sc->vf_ifp) {
534                 sc->stats = kmalloc(sizeof(struct e1000_vf_stats), M_DEVBUF,
535                     M_WAITOK | M_ZERO);
536                 igb_vf_init_stats(sc);
537         } else {
538                 sc->stats = kmalloc(sizeof(struct e1000_hw_stats), M_DEVBUF,
539                     M_WAITOK | M_ZERO);
540         }
541
542         /* Allocate multicast array memory. */
543         sc->mta = kmalloc(ETHER_ADDR_LEN * MAX_NUM_MULTICAST_ADDRESSES,
544             M_DEVBUF, M_WAITOK);
545
546         /* Some adapter-specific advanced features */
547         if (sc->hw.mac.type >= e1000_i350) {
548 #ifdef notyet
549                 igb_set_sysctl_value(adapter, "dma_coalesce",
550                     "configure dma coalesce",
551                     &adapter->dma_coalesce, igb_dma_coalesce);
552                 igb_set_sysctl_value(adapter, "eee_disabled",
553                     "enable Energy Efficient Ethernet",
554                     &adapter->hw.dev_spec._82575.eee_disable,
555                     igb_eee_disabled);
556 #else
557                 sc->dma_coalesce = igb_dma_coalesce;
558                 sc->hw.dev_spec._82575.eee_disable = igb_eee_disabled;
559 #endif
560                 e1000_set_eee_i350(&sc->hw);
561         }
562
563         /*
564          * Start from a known state, this is important in reading the nvm and
565          * mac from that.
566          */
567         e1000_reset_hw(&sc->hw);
568
569         /* Make sure we have a good EEPROM before we read from it */
570         if (e1000_validate_nvm_checksum(&sc->hw) < 0) {
571                 /*
572                  * Some PCI-E parts fail the first check due to
573                  * the link being in sleep state, call it again,
574                  * if it fails a second time its a real issue.
575                  */
576                 if (e1000_validate_nvm_checksum(&sc->hw) < 0) {
577                         device_printf(dev,
578                             "The EEPROM Checksum Is Not Valid\n");
579                         error = EIO;
580                         goto failed;
581                 }
582         }
583
584         /* Copy the permanent MAC address out of the EEPROM */
585         if (e1000_read_mac_addr(&sc->hw) < 0) {
586                 device_printf(dev, "EEPROM read error while reading MAC"
587                     " address\n");
588                 error = EIO;
589                 goto failed;
590         }
591         if (!igb_is_valid_ether_addr(sc->hw.mac.addr)) {
592                 device_printf(dev, "Invalid MAC address\n");
593                 error = EIO;
594                 goto failed;
595         }
596
597         /* Setup OS specific network interface */
598         igb_setup_ifp(sc);
599
600         /* Add sysctl tree, must after igb_setup_ifp() */
601         igb_add_sysctl(sc);
602
603         /* Now get a good starting state */
604         igb_reset(sc);
605
606         /* Initialize statistics */
607         igb_update_stats_counters(sc);
608
609         sc->hw.mac.get_link_status = 1;
610         igb_update_link_status(sc);
611
612         /* Indicate SOL/IDER usage */
613         if (e1000_check_reset_block(&sc->hw)) {
614                 device_printf(dev,
615                     "PHY reset is blocked due to SOL/IDER session.\n");
616         }
617
618         /* Determine if we have to control management hardware */
619         if (e1000_enable_mng_pass_thru(&sc->hw))
620                 sc->flags |= IGB_FLAG_HAS_MGMT;
621
622         /*
623          * Setup Wake-on-Lan
624          */
625         /* APME bit in EEPROM is mapped to WUC.APME */
626         eeprom_data = E1000_READ_REG(&sc->hw, E1000_WUC) & E1000_WUC_APME;
627         if (eeprom_data)
628                 sc->wol = E1000_WUFC_MAG;
629         /* XXX disable WOL */
630         sc->wol = 0; 
631
632 #ifdef notyet
633         /* Register for VLAN events */
634         adapter->vlan_attach = EVENTHANDLER_REGISTER(vlan_config,
635              igb_register_vlan, adapter, EVENTHANDLER_PRI_FIRST);
636         adapter->vlan_detach = EVENTHANDLER_REGISTER(vlan_unconfig,
637              igb_unregister_vlan, adapter, EVENTHANDLER_PRI_FIRST);
638 #endif
639
640 #ifdef notyet
641         igb_add_hw_stats(adapter);
642 #endif
643
644         error = igb_setup_intr(sc);
645         if (error) {
646                 ether_ifdetach(&sc->arpcom.ac_if);
647                 goto failed;
648         }
649         return 0;
650
651 failed:
652         igb_detach(dev);
653         return error;
654 }
655
656 static int
657 igb_detach(device_t dev)
658 {
659         struct igb_softc *sc = device_get_softc(dev);
660
661         if (device_is_attached(dev)) {
662                 struct ifnet *ifp = &sc->arpcom.ac_if;
663
664                 ifnet_serialize_all(ifp);
665
666                 igb_stop(sc);
667
668                 e1000_phy_hw_reset(&sc->hw);
669
670                 /* Give control back to firmware */
671                 igb_rel_mgmt(sc);
672                 igb_rel_hw_control(sc);
673
674                 if (sc->wol) {
675                         E1000_WRITE_REG(&sc->hw, E1000_WUC, E1000_WUC_PME_EN);
676                         E1000_WRITE_REG(&sc->hw, E1000_WUFC, sc->wol);
677                         igb_enable_wol(dev);
678                 }
679
680                 igb_teardown_intr(sc);
681
682                 ifnet_deserialize_all(ifp);
683
684                 ether_ifdetach(ifp);
685         } else if (sc->mem_res != NULL) {
686                 igb_rel_hw_control(sc);
687         }
688         bus_generic_detach(dev);
689
690         if (sc->sysctl_tree != NULL)
691                 sysctl_ctx_free(&sc->sysctl_ctx);
692
693         igb_free_intr(sc);
694
695         if (sc->msix_mem_res != NULL) {
696                 bus_release_resource(dev, SYS_RES_MEMORY, sc->msix_mem_rid,
697                     sc->msix_mem_res);
698         }
699         if (sc->mem_res != NULL) {
700                 bus_release_resource(dev, SYS_RES_MEMORY, sc->mem_rid,
701                     sc->mem_res);
702         }
703
704         igb_free_rings(sc);
705
706         if (sc->mta != NULL)
707                 kfree(sc->mta, M_DEVBUF);
708         if (sc->stats != NULL)
709                 kfree(sc->stats, M_DEVBUF);
710
711         return 0;
712 }
713
714 static int
715 igb_shutdown(device_t dev)
716 {
717         return igb_suspend(dev);
718 }
719
720 static int
721 igb_suspend(device_t dev)
722 {
723         struct igb_softc *sc = device_get_softc(dev);
724         struct ifnet *ifp = &sc->arpcom.ac_if;
725
726         ifnet_serialize_all(ifp);
727
728         igb_stop(sc);
729
730         igb_rel_mgmt(sc);
731         igb_rel_hw_control(sc);
732
733         if (sc->wol) {
734                 E1000_WRITE_REG(&sc->hw, E1000_WUC, E1000_WUC_PME_EN);
735                 E1000_WRITE_REG(&sc->hw, E1000_WUFC, sc->wol);
736                 igb_enable_wol(dev);
737         }
738
739         ifnet_deserialize_all(ifp);
740
741         return bus_generic_suspend(dev);
742 }
743
744 static int
745 igb_resume(device_t dev)
746 {
747         struct igb_softc *sc = device_get_softc(dev);
748         struct ifnet *ifp = &sc->arpcom.ac_if;
749
750         ifnet_serialize_all(ifp);
751
752         igb_init(sc);
753         igb_get_mgmt(sc);
754
755         if_devstart(ifp);
756
757         ifnet_deserialize_all(ifp);
758
759         return bus_generic_resume(dev);
760 }
761
762 static int
763 igb_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
764 {
765         struct igb_softc *sc = ifp->if_softc;
766         struct ifreq *ifr = (struct ifreq *)data;
767         int max_frame_size, mask, reinit;
768         int error = 0;
769
770         ASSERT_IFNET_SERIALIZED_ALL(ifp);
771
772         switch (command) {
773         case SIOCSIFMTU:
774                 max_frame_size = 9234;
775                 if (ifr->ifr_mtu > max_frame_size - ETHER_HDR_LEN -
776                     ETHER_CRC_LEN) {
777                         error = EINVAL;
778                         break;
779                 }
780
781                 ifp->if_mtu = ifr->ifr_mtu;
782                 sc->max_frame_size = ifp->if_mtu + ETHER_HDR_LEN +
783                     ETHER_CRC_LEN;
784
785                 if (ifp->if_flags & IFF_RUNNING)
786                         igb_init(sc);
787                 break;
788
789         case SIOCSIFFLAGS:
790                 if (ifp->if_flags & IFF_UP) {
791                         if (ifp->if_flags & IFF_RUNNING) {
792                                 if ((ifp->if_flags ^ sc->if_flags) &
793                                     (IFF_PROMISC | IFF_ALLMULTI)) {
794                                         igb_disable_promisc(sc);
795                                         igb_set_promisc(sc);
796                                 }
797                         } else {
798                                 igb_init(sc);
799                         }
800                 } else if (ifp->if_flags & IFF_RUNNING) {
801                         igb_stop(sc);
802                 }
803                 sc->if_flags = ifp->if_flags;
804                 break;
805
806         case SIOCADDMULTI:
807         case SIOCDELMULTI:
808                 if (ifp->if_flags & IFF_RUNNING) {
809                         igb_disable_intr(sc);
810                         igb_set_multi(sc);
811 #ifdef IFPOLL_ENABLE
812                         if (!(ifp->if_flags & IFF_NPOLLING))
813 #endif
814                                 igb_enable_intr(sc);
815                 }
816                 break;
817
818         case SIOCSIFMEDIA:
819                 /*
820                  * As the speed/duplex settings are being
821                  * changed, we need toreset the PHY.
822                  */
823                 sc->hw.phy.reset_disable = FALSE;
824
825                 /* Check SOL/IDER usage */
826                 if (e1000_check_reset_block(&sc->hw)) {
827                         if_printf(ifp, "Media change is "
828                             "blocked due to SOL/IDER session.\n");
829                         break;
830                 }
831                 /* FALL THROUGH */
832
833         case SIOCGIFMEDIA:
834                 error = ifmedia_ioctl(ifp, ifr, &sc->media, command);
835                 break;
836
837         case SIOCSIFCAP:
838                 reinit = 0;
839                 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
840                 if (mask & IFCAP_RXCSUM) {
841                         ifp->if_capenable ^= IFCAP_RXCSUM;
842                         reinit = 1;
843                 }
844                 if (mask & IFCAP_VLAN_HWTAGGING) {
845                         ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
846                         reinit = 1;
847                 }
848                 if (mask & IFCAP_TXCSUM) {
849                         ifp->if_capenable ^= IFCAP_TXCSUM;
850                         if (ifp->if_capenable & IFCAP_TXCSUM)
851                                 ifp->if_hwassist |= IGB_CSUM_FEATURES;
852                         else
853                                 ifp->if_hwassist &= ~IGB_CSUM_FEATURES;
854                 }
855                 if (mask & IFCAP_TSO) {
856                         ifp->if_capenable ^= IFCAP_TSO;
857                         if (ifp->if_capenable & IFCAP_TSO)
858                                 ifp->if_hwassist |= CSUM_TSO;
859                         else
860                                 ifp->if_hwassist &= ~CSUM_TSO;
861                 }
862                 if (mask & IFCAP_RSS)
863                         ifp->if_capenable ^= IFCAP_RSS;
864                 if (reinit && (ifp->if_flags & IFF_RUNNING))
865                         igb_init(sc);
866                 break;
867
868         default:
869                 error = ether_ioctl(ifp, command, data);
870                 break;
871         }
872         return error;
873 }
874
875 static void
876 igb_init(void *xsc)
877 {
878         struct igb_softc *sc = xsc;
879         struct ifnet *ifp = &sc->arpcom.ac_if;
880         boolean_t polling;
881         int i;
882
883         ASSERT_IFNET_SERIALIZED_ALL(ifp);
884
885         igb_stop(sc);
886
887         /* Get the latest mac address, User can use a LAA */
888         bcopy(IF_LLADDR(ifp), sc->hw.mac.addr, ETHER_ADDR_LEN);
889
890         /* Put the address into the Receive Address Array */
891         e1000_rar_set(&sc->hw, sc->hw.mac.addr, 0);
892
893         igb_reset(sc);
894         igb_update_link_status(sc);
895
896         E1000_WRITE_REG(&sc->hw, E1000_VET, ETHERTYPE_VLAN);
897
898         /* Configure for OS presence */
899         igb_get_mgmt(sc);
900
901         polling = FALSE;
902 #ifdef IFPOLL_ENABLE
903         if (ifp->if_flags & IFF_NPOLLING)
904                 polling = TRUE;
905 #endif
906
907         /* Configured used RX/TX rings */
908         igb_set_ring_inuse(sc, polling);
909
910         /* Initialize interrupt */
911         igb_init_intr(sc);
912
913         /* Prepare transmit descriptors and buffers */
914         for (i = 0; i < sc->tx_ring_cnt; ++i)
915                 igb_init_tx_ring(&sc->tx_rings[i]);
916         igb_init_tx_unit(sc);
917
918         /* Setup Multicast table */
919         igb_set_multi(sc);
920
921 #if 0
922         /*
923          * Figure out the desired mbuf pool
924          * for doing jumbo/packetsplit
925          */
926         if (adapter->max_frame_size <= 2048)
927                 adapter->rx_mbuf_sz = MCLBYTES;
928         else if (adapter->max_frame_size <= 4096)
929                 adapter->rx_mbuf_sz = MJUMPAGESIZE;
930         else
931                 adapter->rx_mbuf_sz = MJUM9BYTES;
932 #endif
933
934         /* Prepare receive descriptors and buffers */
935         for (i = 0; i < sc->rx_ring_inuse; ++i) {
936                 int error;
937
938                 error = igb_init_rx_ring(&sc->rx_rings[i]);
939                 if (error) {
940                         if_printf(ifp, "Could not setup receive structures\n");
941                         igb_stop(sc);
942                         return;
943                 }
944         }
945         igb_init_rx_unit(sc);
946
947         /* Enable VLAN support */
948         if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING)
949                 igb_set_vlan(sc);
950
951         /* Don't lose promiscuous settings */
952         igb_set_promisc(sc);
953
954         ifp->if_flags |= IFF_RUNNING;
955         ifp->if_flags &= ~IFF_OACTIVE;
956
957         callout_reset(&sc->timer, hz, igb_timer, sc);
958         e1000_clear_hw_cntrs_base_generic(&sc->hw);
959
960         /* This clears any pending interrupts */
961         E1000_READ_REG(&sc->hw, E1000_ICR);
962
963         /*
964          * Only enable interrupts if we are not polling, make sure
965          * they are off otherwise.
966          */
967         if (polling) {
968                 igb_disable_intr(sc);
969         } else {
970                 igb_enable_intr(sc);
971                 E1000_WRITE_REG(&sc->hw, E1000_ICS, E1000_ICS_LSC);
972         }
973
974         /* Set Energy Efficient Ethernet */
975         e1000_set_eee_i350(&sc->hw);
976
977         /* Don't reset the phy next time init gets called */
978         sc->hw.phy.reset_disable = TRUE;
979 }
980
981 static void
982 igb_media_status(struct ifnet *ifp, struct ifmediareq *ifmr)
983 {
984         struct igb_softc *sc = ifp->if_softc;
985         u_char fiber_type = IFM_1000_SX;
986
987         ASSERT_IFNET_SERIALIZED_ALL(ifp);
988
989         igb_update_link_status(sc);
990
991         ifmr->ifm_status = IFM_AVALID;
992         ifmr->ifm_active = IFM_ETHER;
993
994         if (!sc->link_active)
995                 return;
996
997         ifmr->ifm_status |= IFM_ACTIVE;
998
999         if (sc->hw.phy.media_type == e1000_media_type_fiber ||
1000             sc->hw.phy.media_type == e1000_media_type_internal_serdes) {
1001                 ifmr->ifm_active |= fiber_type | IFM_FDX;
1002         } else {
1003                 switch (sc->link_speed) {
1004                 case 10:
1005                         ifmr->ifm_active |= IFM_10_T;
1006                         break;
1007
1008                 case 100:
1009                         ifmr->ifm_active |= IFM_100_TX;
1010                         break;
1011
1012                 case 1000:
1013                         ifmr->ifm_active |= IFM_1000_T;
1014                         break;
1015                 }
1016                 if (sc->link_duplex == FULL_DUPLEX)
1017                         ifmr->ifm_active |= IFM_FDX;
1018                 else
1019                         ifmr->ifm_active |= IFM_HDX;
1020         }
1021 }
1022
1023 static int
1024 igb_media_change(struct ifnet *ifp)
1025 {
1026         struct igb_softc *sc = ifp->if_softc;
1027         struct ifmedia *ifm = &sc->media;
1028
1029         ASSERT_IFNET_SERIALIZED_ALL(ifp);
1030
1031         if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
1032                 return EINVAL;
1033
1034         switch (IFM_SUBTYPE(ifm->ifm_media)) {
1035         case IFM_AUTO:
1036                 sc->hw.mac.autoneg = DO_AUTO_NEG;
1037                 sc->hw.phy.autoneg_advertised = AUTONEG_ADV_DEFAULT;
1038                 break;
1039
1040         case IFM_1000_LX:
1041         case IFM_1000_SX:
1042         case IFM_1000_T:
1043                 sc->hw.mac.autoneg = DO_AUTO_NEG;
1044                 sc->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
1045                 break;
1046
1047         case IFM_100_TX:
1048                 sc->hw.mac.autoneg = FALSE;
1049                 sc->hw.phy.autoneg_advertised = 0;
1050                 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
1051                         sc->hw.mac.forced_speed_duplex = ADVERTISE_100_FULL;
1052                 else
1053                         sc->hw.mac.forced_speed_duplex = ADVERTISE_100_HALF;
1054                 break;
1055
1056         case IFM_10_T:
1057                 sc->hw.mac.autoneg = FALSE;
1058                 sc->hw.phy.autoneg_advertised = 0;
1059                 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
1060                         sc->hw.mac.forced_speed_duplex = ADVERTISE_10_FULL;
1061                 else
1062                         sc->hw.mac.forced_speed_duplex = ADVERTISE_10_HALF;
1063                 break;
1064
1065         default:
1066                 if_printf(ifp, "Unsupported media type\n");
1067                 break;
1068         }
1069
1070         igb_init(sc);
1071
1072         return 0;
1073 }
1074
1075 static void
1076 igb_set_promisc(struct igb_softc *sc)
1077 {
1078         struct ifnet *ifp = &sc->arpcom.ac_if;
1079         struct e1000_hw *hw = &sc->hw;
1080         uint32_t reg;
1081
1082         if (sc->vf_ifp) {
1083                 e1000_promisc_set_vf(hw, e1000_promisc_enabled);
1084                 return;
1085         }
1086
1087         reg = E1000_READ_REG(hw, E1000_RCTL);
1088         if (ifp->if_flags & IFF_PROMISC) {
1089                 reg |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
1090                 E1000_WRITE_REG(hw, E1000_RCTL, reg);
1091         } else if (ifp->if_flags & IFF_ALLMULTI) {
1092                 reg |= E1000_RCTL_MPE;
1093                 reg &= ~E1000_RCTL_UPE;
1094                 E1000_WRITE_REG(hw, E1000_RCTL, reg);
1095         }
1096 }
1097
1098 static void
1099 igb_disable_promisc(struct igb_softc *sc)
1100 {
1101         struct e1000_hw *hw = &sc->hw;
1102         uint32_t reg;
1103
1104         if (sc->vf_ifp) {
1105                 e1000_promisc_set_vf(hw, e1000_promisc_disabled);
1106                 return;
1107         }
1108         reg = E1000_READ_REG(hw, E1000_RCTL);
1109         reg &= ~E1000_RCTL_UPE;
1110         reg &= ~E1000_RCTL_MPE;
1111         E1000_WRITE_REG(hw, E1000_RCTL, reg);
1112 }
1113
1114 static void
1115 igb_set_multi(struct igb_softc *sc)
1116 {
1117         struct ifnet *ifp = &sc->arpcom.ac_if;
1118         struct ifmultiaddr *ifma;
1119         uint32_t reg_rctl = 0;
1120         uint8_t *mta;
1121         int mcnt = 0;
1122
1123         mta = sc->mta;
1124         bzero(mta, ETH_ADDR_LEN * MAX_NUM_MULTICAST_ADDRESSES);
1125
1126         TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1127                 if (ifma->ifma_addr->sa_family != AF_LINK)
1128                         continue;
1129
1130                 if (mcnt == MAX_NUM_MULTICAST_ADDRESSES)
1131                         break;
1132
1133                 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
1134                     &mta[mcnt * ETH_ADDR_LEN], ETH_ADDR_LEN);
1135                 mcnt++;
1136         }
1137
1138         if (mcnt >= MAX_NUM_MULTICAST_ADDRESSES) {
1139                 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL);
1140                 reg_rctl |= E1000_RCTL_MPE;
1141                 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl);
1142         } else {
1143                 e1000_update_mc_addr_list(&sc->hw, mta, mcnt);
1144         }
1145 }
1146
1147 static void
1148 igb_timer(void *xsc)
1149 {
1150         struct igb_softc *sc = xsc;
1151
1152         lwkt_serialize_enter(&sc->main_serialize);
1153
1154         igb_update_link_status(sc);
1155         igb_update_stats_counters(sc);
1156
1157         callout_reset(&sc->timer, hz, igb_timer, sc);
1158
1159         lwkt_serialize_exit(&sc->main_serialize);
1160 }
1161
1162 static void
1163 igb_update_link_status(struct igb_softc *sc)
1164 {
1165         struct ifnet *ifp = &sc->arpcom.ac_if;
1166         struct e1000_hw *hw = &sc->hw;
1167         uint32_t link_check, thstat, ctrl;
1168
1169         link_check = thstat = ctrl = 0;
1170
1171         /* Get the cached link value or read for real */
1172         switch (hw->phy.media_type) {
1173         case e1000_media_type_copper:
1174                 if (hw->mac.get_link_status) {
1175                         /* Do the work to read phy */
1176                         e1000_check_for_link(hw);
1177                         link_check = !hw->mac.get_link_status;
1178                 } else {
1179                         link_check = TRUE;
1180                 }
1181                 break;
1182
1183         case e1000_media_type_fiber:
1184                 e1000_check_for_link(hw);
1185                 link_check = E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU;
1186                 break;
1187
1188         case e1000_media_type_internal_serdes:
1189                 e1000_check_for_link(hw);
1190                 link_check = hw->mac.serdes_has_link;
1191                 break;
1192
1193         /* VF device is type_unknown */
1194         case e1000_media_type_unknown:
1195                 e1000_check_for_link(hw);
1196                 link_check = !hw->mac.get_link_status;
1197                 /* Fall thru */
1198         default:
1199                 break;
1200         }
1201
1202         /* Check for thermal downshift or shutdown */
1203         if (hw->mac.type == e1000_i350) {
1204                 thstat = E1000_READ_REG(hw, E1000_THSTAT);
1205                 ctrl = E1000_READ_REG(hw, E1000_CTRL_EXT);
1206         }
1207
1208         /* Now we check if a transition has happened */
1209         if (link_check && sc->link_active == 0) {
1210                 e1000_get_speed_and_duplex(hw, 
1211                     &sc->link_speed, &sc->link_duplex);
1212                 if (bootverbose) {
1213                         if_printf(ifp, "Link is up %d Mbps %s\n",
1214                             sc->link_speed,
1215                             sc->link_duplex == FULL_DUPLEX ?
1216                             "Full Duplex" : "Half Duplex");
1217                 }
1218                 sc->link_active = 1;
1219
1220                 ifp->if_baudrate = sc->link_speed * 1000000;
1221                 if ((ctrl & E1000_CTRL_EXT_LINK_MODE_GMII) &&
1222                     (thstat & E1000_THSTAT_LINK_THROTTLE))
1223                         if_printf(ifp, "Link: thermal downshift\n");
1224                 /* This can sleep */
1225                 ifp->if_link_state = LINK_STATE_UP;
1226                 if_link_state_change(ifp);
1227         } else if (!link_check && sc->link_active == 1) {
1228                 ifp->if_baudrate = sc->link_speed = 0;
1229                 sc->link_duplex = 0;
1230                 if (bootverbose)
1231                         if_printf(ifp, "Link is Down\n");
1232                 if ((ctrl & E1000_CTRL_EXT_LINK_MODE_GMII) &&
1233                     (thstat & E1000_THSTAT_PWR_DOWN))
1234                         if_printf(ifp, "Link: thermal shutdown\n");
1235                 sc->link_active = 0;
1236                 /* This can sleep */
1237                 ifp->if_link_state = LINK_STATE_DOWN;
1238                 if_link_state_change(ifp);
1239         }
1240 }
1241
1242 static void
1243 igb_stop(struct igb_softc *sc)
1244 {
1245         struct ifnet *ifp = &sc->arpcom.ac_if;
1246         int i;
1247
1248         ASSERT_IFNET_SERIALIZED_ALL(ifp);
1249
1250         igb_disable_intr(sc);
1251
1252         callout_stop(&sc->timer);
1253
1254         ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1255         ifp->if_timer = 0;
1256
1257         e1000_reset_hw(&sc->hw);
1258         E1000_WRITE_REG(&sc->hw, E1000_WUC, 0);
1259
1260         e1000_led_off(&sc->hw);
1261         e1000_cleanup_led(&sc->hw);
1262
1263         for (i = 0; i < sc->tx_ring_cnt; ++i)
1264                 igb_free_tx_ring(&sc->tx_rings[i]);
1265         for (i = 0; i < sc->rx_ring_cnt; ++i)
1266                 igb_free_rx_ring(&sc->rx_rings[i]);
1267 }
1268
1269 static void
1270 igb_reset(struct igb_softc *sc)
1271 {
1272         struct ifnet *ifp = &sc->arpcom.ac_if;
1273         struct e1000_hw *hw = &sc->hw;
1274         struct e1000_fc_info *fc = &hw->fc;
1275         uint32_t pba = 0;
1276         uint16_t hwm;
1277
1278         /* Let the firmware know the OS is in control */
1279         igb_get_hw_control(sc);
1280
1281         /*
1282          * Packet Buffer Allocation (PBA)
1283          * Writing PBA sets the receive portion of the buffer
1284          * the remainder is used for the transmit buffer.
1285          */
1286         switch (hw->mac.type) {
1287         case e1000_82575:
1288                 pba = E1000_PBA_32K;
1289                 break;
1290
1291         case e1000_82576:
1292         case e1000_vfadapt:
1293                 pba = E1000_READ_REG(hw, E1000_RXPBS);
1294                 pba &= E1000_RXPBS_SIZE_MASK_82576;
1295                 break;
1296
1297         case e1000_82580:
1298         case e1000_i350:
1299         case e1000_vfadapt_i350:
1300                 pba = E1000_READ_REG(hw, E1000_RXPBS);
1301                 pba = e1000_rxpbs_adjust_82580(pba);
1302                 break;
1303                 /* XXX pba = E1000_PBA_35K; */
1304
1305         default:
1306                 break;
1307         }
1308
1309         /* Special needs in case of Jumbo frames */
1310         if (hw->mac.type == e1000_82575 && ifp->if_mtu > ETHERMTU) {
1311                 uint32_t tx_space, min_tx, min_rx;
1312
1313                 pba = E1000_READ_REG(hw, E1000_PBA);
1314                 tx_space = pba >> 16;
1315                 pba &= 0xffff;
1316
1317                 min_tx = (sc->max_frame_size +
1318                     sizeof(struct e1000_tx_desc) - ETHER_CRC_LEN) * 2;
1319                 min_tx = roundup2(min_tx, 1024);
1320                 min_tx >>= 10;
1321                 min_rx = sc->max_frame_size;
1322                 min_rx = roundup2(min_rx, 1024);
1323                 min_rx >>= 10;
1324                 if (tx_space < min_tx && (min_tx - tx_space) < pba) {
1325                         pba = pba - (min_tx - tx_space);
1326                         /*
1327                          * if short on rx space, rx wins
1328                          * and must trump tx adjustment
1329                          */
1330                         if (pba < min_rx)
1331                                 pba = min_rx;
1332                 }
1333                 E1000_WRITE_REG(hw, E1000_PBA, pba);
1334         }
1335
1336         /*
1337          * These parameters control the automatic generation (Tx) and
1338          * response (Rx) to Ethernet PAUSE frames.
1339          * - High water mark should allow for at least two frames to be
1340          *   received after sending an XOFF.
1341          * - Low water mark works best when it is very near the high water mark.
1342          *   This allows the receiver to restart by sending XON when it has
1343          *   drained a bit.
1344          */
1345         hwm = min(((pba << 10) * 9 / 10),
1346             ((pba << 10) - 2 * sc->max_frame_size));
1347
1348         if (hw->mac.type < e1000_82576) {
1349                 fc->high_water = hwm & 0xFFF8; /* 8-byte granularity */
1350                 fc->low_water = fc->high_water - 8;
1351         } else {
1352                 fc->high_water = hwm & 0xFFF0; /* 16-byte granularity */
1353                 fc->low_water = fc->high_water - 16;
1354         }
1355         fc->pause_time = IGB_FC_PAUSE_TIME;
1356         fc->send_xon = TRUE;
1357
1358         /* Issue a global reset */
1359         e1000_reset_hw(hw);
1360         E1000_WRITE_REG(hw, E1000_WUC, 0);
1361
1362         if (e1000_init_hw(hw) < 0)
1363                 if_printf(ifp, "Hardware Initialization Failed\n");
1364
1365         /* Setup DMA Coalescing */
1366         if (hw->mac.type == e1000_i350 && sc->dma_coalesce) {
1367                 uint32_t reg;
1368
1369                 hwm = (pba - 4) << 10;
1370                 reg = ((pba - 6) << E1000_DMACR_DMACTHR_SHIFT)
1371                     & E1000_DMACR_DMACTHR_MASK;
1372
1373                 /* transition to L0x or L1 if available..*/
1374                 reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK);
1375
1376                 /* timer = +-1000 usec in 32usec intervals */
1377                 reg |= (1000 >> 5);
1378                 E1000_WRITE_REG(hw, E1000_DMACR, reg);
1379
1380                 /* No lower threshold */
1381                 E1000_WRITE_REG(hw, E1000_DMCRTRH, 0);
1382
1383                 /* set hwm to PBA -  2 * max frame size */
1384                 E1000_WRITE_REG(hw, E1000_FCRTC, hwm);
1385
1386                 /* Set the interval before transition */
1387                 reg = E1000_READ_REG(hw, E1000_DMCTLX);
1388                 reg |= 0x800000FF; /* 255 usec */
1389                 E1000_WRITE_REG(hw, E1000_DMCTLX, reg);
1390
1391                 /* free space in tx packet buffer to wake from DMA coal */
1392                 E1000_WRITE_REG(hw, E1000_DMCTXTH,
1393                     (20480 - (2 * sc->max_frame_size)) >> 6);
1394
1395                 /* make low power state decision controlled by DMA coal */
1396                 reg = E1000_READ_REG(hw, E1000_PCIEMISC);
1397                 E1000_WRITE_REG(hw, E1000_PCIEMISC,
1398                     reg | E1000_PCIEMISC_LX_DECISION);
1399                 if_printf(ifp, "DMA Coalescing enabled\n");
1400         }
1401
1402         E1000_WRITE_REG(&sc->hw, E1000_VET, ETHERTYPE_VLAN);
1403         e1000_get_phy_info(hw);
1404         e1000_check_for_link(hw);
1405 }
1406
1407 static void
1408 igb_setup_ifp(struct igb_softc *sc)
1409 {
1410         struct ifnet *ifp = &sc->arpcom.ac_if;
1411
1412         ifp->if_softc = sc;
1413         ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1414         ifp->if_init = igb_init;
1415         ifp->if_ioctl = igb_ioctl;
1416         ifp->if_start = igb_start;
1417         ifp->if_serialize = igb_serialize;
1418         ifp->if_deserialize = igb_deserialize;
1419         ifp->if_tryserialize = igb_tryserialize;
1420 #ifdef INVARIANTS
1421         ifp->if_serialize_assert = igb_serialize_assert;
1422 #endif
1423 #ifdef IFPOLL_ENABLE
1424         ifp->if_npoll = igb_npoll;
1425 #endif
1426         ifp->if_watchdog = igb_watchdog;
1427
1428         ifq_set_maxlen(&ifp->if_snd, sc->tx_rings[0].num_tx_desc - 1);
1429         ifq_set_ready(&ifp->if_snd);
1430
1431         ether_ifattach(ifp, sc->hw.mac.addr, NULL);
1432
1433         ifp->if_capabilities =
1434             IFCAP_HWCSUM | IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU | IFCAP_TSO;
1435         if (IGB_ENABLE_HWRSS(sc))
1436                 ifp->if_capabilities |= IFCAP_RSS;
1437         ifp->if_capenable = ifp->if_capabilities;
1438         ifp->if_hwassist = IGB_CSUM_FEATURES | CSUM_TSO;
1439
1440         /*
1441          * Tell the upper layer(s) we support long frames
1442          */
1443         ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
1444
1445         /*
1446          * Specify the media types supported by this adapter and register
1447          * callbacks to update media and link information
1448          */
1449         ifmedia_init(&sc->media, IFM_IMASK, igb_media_change, igb_media_status);
1450         if (sc->hw.phy.media_type == e1000_media_type_fiber ||
1451             sc->hw.phy.media_type == e1000_media_type_internal_serdes) {
1452                 ifmedia_add(&sc->media, IFM_ETHER | IFM_1000_SX | IFM_FDX,
1453                     0, NULL);
1454                 ifmedia_add(&sc->media, IFM_ETHER | IFM_1000_SX, 0, NULL);
1455         } else {
1456                 ifmedia_add(&sc->media, IFM_ETHER | IFM_10_T, 0, NULL);
1457                 ifmedia_add(&sc->media, IFM_ETHER | IFM_10_T | IFM_FDX,
1458                     0, NULL);
1459                 ifmedia_add(&sc->media, IFM_ETHER | IFM_100_TX, 0, NULL);
1460                 ifmedia_add(&sc->media, IFM_ETHER | IFM_100_TX | IFM_FDX,
1461                     0, NULL);
1462                 if (sc->hw.phy.type != e1000_phy_ife) {
1463                         ifmedia_add(&sc->media,
1464                             IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL);
1465                         ifmedia_add(&sc->media,
1466                             IFM_ETHER | IFM_1000_T, 0, NULL);
1467                 }
1468         }
1469         ifmedia_add(&sc->media, IFM_ETHER | IFM_AUTO, 0, NULL);
1470         ifmedia_set(&sc->media, IFM_ETHER | IFM_AUTO);
1471 }
1472
1473 static void
1474 igb_add_sysctl(struct igb_softc *sc)
1475 {
1476         char node[32];
1477         int i;
1478
1479         sysctl_ctx_init(&sc->sysctl_ctx);
1480         sc->sysctl_tree = SYSCTL_ADD_NODE(&sc->sysctl_ctx,
1481             SYSCTL_STATIC_CHILDREN(_hw), OID_AUTO,
1482             device_get_nameunit(sc->dev), CTLFLAG_RD, 0, "");
1483         if (sc->sysctl_tree == NULL) {
1484                 device_printf(sc->dev, "can't add sysctl node\n");
1485                 return;
1486         }
1487
1488         SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1489             OID_AUTO, "rxr", CTLFLAG_RD, &sc->rx_ring_cnt, 0, "# of RX rings");
1490         SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1491             OID_AUTO, "rxr_inuse", CTLFLAG_RD, &sc->rx_ring_inuse, 0,
1492             "# of RX rings used");
1493         SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1494             OID_AUTO, "rxd", CTLFLAG_RD, &sc->rx_rings[0].num_rx_desc, 0,
1495             "# of RX descs");
1496         SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1497             OID_AUTO, "txd", CTLFLAG_RD, &sc->tx_rings[0].num_tx_desc, 0,
1498             "# of TX descs");
1499
1500         if (sc->intr_type != PCI_INTR_TYPE_MSIX) {
1501                 SYSCTL_ADD_PROC(&sc->sysctl_ctx,
1502                     SYSCTL_CHILDREN(sc->sysctl_tree),
1503                     OID_AUTO, "intr_rate", CTLTYPE_INT | CTLFLAG_RW,
1504                     sc, 0, igb_sysctl_intr_rate, "I", "interrupt rate");
1505         } else {
1506                 for (i = 0; i < sc->msix_cnt; ++i) {
1507                         struct igb_msix_data *msix = &sc->msix_data[i];
1508
1509                         ksnprintf(node, sizeof(node), "msix%d_rate", i);
1510                         SYSCTL_ADD_PROC(&sc->sysctl_ctx,
1511                             SYSCTL_CHILDREN(sc->sysctl_tree),
1512                             OID_AUTO, node, CTLTYPE_INT | CTLFLAG_RW,
1513                             msix, 0, igb_sysctl_msix_rate, "I",
1514                             msix->msix_rate_desc);
1515                 }
1516         }
1517
1518         SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1519             OID_AUTO, "tx_intr_nsegs", CTLTYPE_INT | CTLFLAG_RW,
1520             sc, 0, igb_sysctl_tx_intr_nsegs, "I",
1521             "# of segments per TX interrupt");
1522
1523 #ifdef IFPOLL_ENABLE
1524         SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1525             OID_AUTO, "npoll_rxoff", CTLTYPE_INT|CTLFLAG_RW,
1526             sc, 0, igb_sysctl_npoll_rxoff, "I", "NPOLLING RX cpu offset");
1527         SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1528             OID_AUTO, "npoll_txoff", CTLTYPE_INT|CTLFLAG_RW,
1529             sc, 0, igb_sysctl_npoll_txoff, "I", "NPOLLING TX cpu offset");
1530 #endif
1531
1532 #ifdef IGB_RSS_DEBUG
1533         SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1534             OID_AUTO, "rss_debug", CTLFLAG_RW, &sc->rss_debug, 0,
1535             "RSS debug level");
1536         for (i = 0; i < sc->rx_ring_cnt; ++i) {
1537                 ksnprintf(node, sizeof(node), "rx%d_pkt", i);
1538                 SYSCTL_ADD_ULONG(&sc->sysctl_ctx,
1539                     SYSCTL_CHILDREN(sc->sysctl_tree), OID_AUTO, node,
1540                     CTLFLAG_RW, &sc->rx_rings[i].rx_packets, "RXed packets");
1541         }
1542 #endif
1543 }
1544
1545 static int
1546 igb_alloc_rings(struct igb_softc *sc)
1547 {
1548         int error, i;
1549
1550         /*
1551          * Create top level busdma tag
1552          */
1553         error = bus_dma_tag_create(NULL, 1, 0,
1554             BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL,
1555             BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 0,
1556             &sc->parent_tag);
1557         if (error) {
1558                 device_printf(sc->dev, "could not create top level DMA tag\n");
1559                 return error;
1560         }
1561
1562         /*
1563          * Allocate TX descriptor rings and buffers
1564          */
1565         sc->tx_rings = kmalloc(sizeof(struct igb_tx_ring) * sc->tx_ring_cnt,
1566             M_DEVBUF, M_WAITOK | M_ZERO);
1567         for (i = 0; i < sc->tx_ring_cnt; ++i) {
1568                 struct igb_tx_ring *txr = &sc->tx_rings[i];
1569
1570                 /* Set up some basics */
1571                 txr->sc = sc;
1572                 txr->me = i;
1573                 lwkt_serialize_init(&txr->tx_serialize);
1574
1575                 error = igb_create_tx_ring(txr);
1576                 if (error)
1577                         return error;
1578         }
1579
1580         /*
1581          * Allocate RX descriptor rings and buffers
1582          */ 
1583         sc->rx_rings = kmalloc(sizeof(struct igb_rx_ring) * sc->rx_ring_cnt,
1584             M_DEVBUF, M_WAITOK | M_ZERO);
1585         for (i = 0; i < sc->rx_ring_cnt; ++i) {
1586                 struct igb_rx_ring *rxr = &sc->rx_rings[i];
1587
1588                 /* Set up some basics */
1589                 rxr->sc = sc;
1590                 rxr->me = i;
1591                 lwkt_serialize_init(&rxr->rx_serialize);
1592
1593                 error = igb_create_rx_ring(rxr);
1594                 if (error)
1595                         return error;
1596         }
1597
1598         return 0;
1599 }
1600
1601 static void
1602 igb_free_rings(struct igb_softc *sc)
1603 {
1604         int i;
1605
1606         if (sc->tx_rings != NULL) {
1607                 for (i = 0; i < sc->tx_ring_cnt; ++i) {
1608                         struct igb_tx_ring *txr = &sc->tx_rings[i];
1609
1610                         igb_destroy_tx_ring(txr, txr->num_tx_desc);
1611                 }
1612                 kfree(sc->tx_rings, M_DEVBUF);
1613         }
1614
1615         if (sc->rx_rings != NULL) {
1616                 for (i = 0; i < sc->rx_ring_cnt; ++i) {
1617                         struct igb_rx_ring *rxr = &sc->rx_rings[i];
1618
1619                         igb_destroy_rx_ring(rxr, rxr->num_rx_desc);
1620                 }
1621                 kfree(sc->rx_rings, M_DEVBUF);
1622         }
1623 }
1624
1625 static int
1626 igb_create_tx_ring(struct igb_tx_ring *txr)
1627 {
1628         int tsize, error, i;
1629
1630         /*
1631          * Validate number of transmit descriptors. It must not exceed
1632          * hardware maximum, and must be multiple of IGB_DBA_ALIGN.
1633          */
1634         if (((igb_txd * sizeof(struct e1000_tx_desc)) % IGB_DBA_ALIGN) != 0 ||
1635             (igb_txd > IGB_MAX_TXD) || (igb_txd < IGB_MIN_TXD)) {
1636                 device_printf(txr->sc->dev,
1637                     "Using %d TX descriptors instead of %d!\n",
1638                     IGB_DEFAULT_TXD, igb_txd);
1639                 txr->num_tx_desc = IGB_DEFAULT_TXD;
1640         } else {
1641                 txr->num_tx_desc = igb_txd;
1642         }
1643
1644         /*
1645          * Allocate TX descriptor ring
1646          */
1647         tsize = roundup2(txr->num_tx_desc * sizeof(union e1000_adv_tx_desc),
1648             IGB_DBA_ALIGN);
1649         txr->txdma.dma_vaddr = bus_dmamem_coherent_any(txr->sc->parent_tag,
1650             IGB_DBA_ALIGN, tsize, BUS_DMA_WAITOK,
1651             &txr->txdma.dma_tag, &txr->txdma.dma_map, &txr->txdma.dma_paddr);
1652         if (txr->txdma.dma_vaddr == NULL) {
1653                 device_printf(txr->sc->dev,
1654                     "Unable to allocate TX Descriptor memory\n");
1655                 return ENOMEM;
1656         }
1657         txr->tx_base = txr->txdma.dma_vaddr;
1658         bzero(txr->tx_base, tsize);
1659
1660         txr->tx_buf = kmalloc(sizeof(struct igb_tx_buf) * txr->num_tx_desc,
1661             M_DEVBUF, M_WAITOK | M_ZERO);
1662
1663         /*
1664          * Allocate TX head write-back buffer
1665          */
1666         txr->tx_hdr = bus_dmamem_coherent_any(txr->sc->parent_tag,
1667             __VM_CACHELINE_SIZE, __VM_CACHELINE_SIZE, BUS_DMA_WAITOK,
1668             &txr->tx_hdr_dtag, &txr->tx_hdr_dmap, &txr->tx_hdr_paddr);
1669         if (txr->tx_hdr == NULL) {
1670                 device_printf(txr->sc->dev,
1671                     "Unable to allocate TX head write-back buffer\n");
1672                 return ENOMEM;
1673         }
1674
1675         /*
1676          * Create DMA tag for TX buffers
1677          */
1678         error = bus_dma_tag_create(txr->sc->parent_tag,
1679             1, 0,               /* alignment, bounds */
1680             BUS_SPACE_MAXADDR,  /* lowaddr */
1681             BUS_SPACE_MAXADDR,  /* highaddr */
1682             NULL, NULL,         /* filter, filterarg */
1683             IGB_TSO_SIZE,       /* maxsize */
1684             IGB_MAX_SCATTER,    /* nsegments */
1685             PAGE_SIZE,          /* maxsegsize */
1686             BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW |
1687             BUS_DMA_ONEBPAGE,   /* flags */
1688             &txr->tx_tag);
1689         if (error) {
1690                 device_printf(txr->sc->dev, "Unable to allocate TX DMA tag\n");
1691                 kfree(txr->tx_buf, M_DEVBUF);
1692                 txr->tx_buf = NULL;
1693                 return error;
1694         }
1695
1696         /*
1697          * Create DMA maps for TX buffers
1698          */
1699         for (i = 0; i < txr->num_tx_desc; ++i) {
1700                 struct igb_tx_buf *txbuf = &txr->tx_buf[i];
1701
1702                 error = bus_dmamap_create(txr->tx_tag,
1703                     BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE, &txbuf->map);
1704                 if (error) {
1705                         device_printf(txr->sc->dev,
1706                             "Unable to create TX DMA map\n");
1707                         igb_destroy_tx_ring(txr, i);
1708                         return error;
1709                 }
1710         }
1711
1712         /*
1713          * Initialize various watermark
1714          */
1715         txr->spare_desc = IGB_TX_SPARE;
1716         txr->intr_nsegs = txr->num_tx_desc / 16;
1717         txr->oact_hi_desc = txr->num_tx_desc / 2;
1718         txr->oact_lo_desc = txr->num_tx_desc / 8;
1719         if (txr->oact_lo_desc > IGB_TX_OACTIVE_MAX)
1720                 txr->oact_lo_desc = IGB_TX_OACTIVE_MAX;
1721         if (txr->oact_lo_desc < txr->spare_desc + IGB_TX_RESERVED)
1722                 txr->oact_lo_desc = txr->spare_desc + IGB_TX_RESERVED;
1723
1724         return 0;
1725 }
1726
1727 static void
1728 igb_free_tx_ring(struct igb_tx_ring *txr)
1729 {
1730         int i;
1731
1732         for (i = 0; i < txr->num_tx_desc; ++i) {
1733                 struct igb_tx_buf *txbuf = &txr->tx_buf[i];
1734
1735                 if (txbuf->m_head != NULL) {
1736                         bus_dmamap_unload(txr->tx_tag, txbuf->map);
1737                         m_freem(txbuf->m_head);
1738                         txbuf->m_head = NULL;
1739                 }
1740         }
1741 }
1742
1743 static void
1744 igb_destroy_tx_ring(struct igb_tx_ring *txr, int ndesc)
1745 {
1746         int i;
1747
1748         if (txr->txdma.dma_vaddr != NULL) {
1749                 bus_dmamap_unload(txr->txdma.dma_tag, txr->txdma.dma_map);
1750                 bus_dmamem_free(txr->txdma.dma_tag, txr->txdma.dma_vaddr,
1751                     txr->txdma.dma_map);
1752                 bus_dma_tag_destroy(txr->txdma.dma_tag);
1753                 txr->txdma.dma_vaddr = NULL;
1754         }
1755
1756         if (txr->tx_hdr != NULL) {
1757                 bus_dmamap_unload(txr->tx_hdr_dtag, txr->tx_hdr_dmap);
1758                 bus_dmamem_free(txr->tx_hdr_dtag, txr->tx_hdr,
1759                     txr->tx_hdr_dmap);
1760                 bus_dma_tag_destroy(txr->tx_hdr_dtag);
1761                 txr->tx_hdr = NULL;
1762         }
1763
1764         if (txr->tx_buf == NULL)
1765                 return;
1766
1767         for (i = 0; i < ndesc; ++i) {
1768                 struct igb_tx_buf *txbuf = &txr->tx_buf[i];
1769
1770                 KKASSERT(txbuf->m_head == NULL);
1771                 bus_dmamap_destroy(txr->tx_tag, txbuf->map);
1772         }
1773         bus_dma_tag_destroy(txr->tx_tag);
1774
1775         kfree(txr->tx_buf, M_DEVBUF);
1776         txr->tx_buf = NULL;
1777 }
1778
1779 static void
1780 igb_init_tx_ring(struct igb_tx_ring *txr)
1781 {
1782         /* Clear the old descriptor contents */
1783         bzero(txr->tx_base,
1784             sizeof(union e1000_adv_tx_desc) * txr->num_tx_desc);
1785
1786         /* Clear TX head write-back buffer */
1787         *(txr->tx_hdr) = 0;
1788
1789         /* Reset indices */
1790         txr->next_avail_desc = 0;
1791         txr->next_to_clean = 0;
1792         txr->tx_nsegs = 0;
1793
1794         /* Set number of descriptors available */
1795         txr->tx_avail = txr->num_tx_desc;
1796 }
1797
1798 static void
1799 igb_init_tx_unit(struct igb_softc *sc)
1800 {
1801         struct e1000_hw *hw = &sc->hw;
1802         uint32_t tctl;
1803         int i;
1804
1805         /* Setup the Tx Descriptor Rings */
1806         for (i = 0; i < sc->tx_ring_cnt; ++i) {
1807                 struct igb_tx_ring *txr = &sc->tx_rings[i];
1808                 uint64_t bus_addr = txr->txdma.dma_paddr;
1809                 uint64_t hdr_paddr = txr->tx_hdr_paddr;
1810                 uint32_t txdctl = 0;
1811                 uint32_t dca_txctrl;
1812
1813                 E1000_WRITE_REG(hw, E1000_TDLEN(i),
1814                     txr->num_tx_desc * sizeof(struct e1000_tx_desc));
1815                 E1000_WRITE_REG(hw, E1000_TDBAH(i),
1816                     (uint32_t)(bus_addr >> 32));
1817                 E1000_WRITE_REG(hw, E1000_TDBAL(i),
1818                     (uint32_t)bus_addr);
1819
1820                 /* Setup the HW Tx Head and Tail descriptor pointers */
1821                 E1000_WRITE_REG(hw, E1000_TDT(i), 0);
1822                 E1000_WRITE_REG(hw, E1000_TDH(i), 0);
1823
1824                 /*
1825                  * WTHRESH is ignored by the hardware, since header
1826                  * write back mode is used.
1827                  */
1828                 txdctl |= IGB_TX_PTHRESH;
1829                 txdctl |= IGB_TX_HTHRESH << 8;
1830                 txdctl |= IGB_TX_WTHRESH << 16;
1831                 txdctl |= E1000_TXDCTL_QUEUE_ENABLE;
1832                 E1000_WRITE_REG(hw, E1000_TXDCTL(i), txdctl);
1833
1834                 dca_txctrl = E1000_READ_REG(hw, E1000_DCA_TXCTRL(i));
1835                 dca_txctrl &= ~E1000_DCA_TXCTRL_TX_WB_RO_EN;
1836                 E1000_WRITE_REG(hw, E1000_DCA_TXCTRL(i), dca_txctrl);
1837
1838                 /*
1839                  * Don't set WB_on_EITR:
1840                  * - 82575 does not have it
1841                  * - It almost has no effect on 82576, see:
1842                  *   82576 specification update errata #26
1843                  * - It causes unnecessary bus traffic
1844                  */
1845                 E1000_WRITE_REG(hw, E1000_TDWBAH(i),
1846                     (uint32_t)(hdr_paddr >> 32));
1847                 E1000_WRITE_REG(hw, E1000_TDWBAL(i),
1848                     ((uint32_t)hdr_paddr) | E1000_TX_HEAD_WB_ENABLE);
1849         }
1850
1851         if (sc->vf_ifp)
1852                 return;
1853
1854         e1000_config_collision_dist(hw);
1855
1856         /* Program the Transmit Control Register */
1857         tctl = E1000_READ_REG(hw, E1000_TCTL);
1858         tctl &= ~E1000_TCTL_CT;
1859         tctl |= (E1000_TCTL_PSP | E1000_TCTL_RTLC | E1000_TCTL_EN |
1860             (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT));
1861
1862         /* This write will effectively turn on the transmit unit. */
1863         E1000_WRITE_REG(hw, E1000_TCTL, tctl);
1864 }
1865
1866 static boolean_t
1867 igb_txcsum_ctx(struct igb_tx_ring *txr, struct mbuf *mp)
1868 {
1869         struct e1000_adv_tx_context_desc *TXD;
1870         uint32_t vlan_macip_lens, type_tucmd_mlhl, mss_l4len_idx;
1871         int ehdrlen, ctxd, ip_hlen = 0;
1872         boolean_t offload = TRUE;
1873
1874         if ((mp->m_pkthdr.csum_flags & IGB_CSUM_FEATURES) == 0)
1875                 offload = FALSE;
1876
1877         vlan_macip_lens = type_tucmd_mlhl = mss_l4len_idx = 0;
1878
1879         ctxd = txr->next_avail_desc;
1880         TXD = (struct e1000_adv_tx_context_desc *)&txr->tx_base[ctxd];
1881
1882         /*
1883          * In advanced descriptors the vlan tag must 
1884          * be placed into the context descriptor, thus
1885          * we need to be here just for that setup.
1886          */
1887         if (mp->m_flags & M_VLANTAG) {
1888                 uint16_t vlantag;
1889
1890                 vlantag = htole16(mp->m_pkthdr.ether_vlantag);
1891                 vlan_macip_lens |= (vlantag << E1000_ADVTXD_VLAN_SHIFT);
1892         } else if (!offload) {
1893                 return FALSE;
1894         }
1895
1896         ehdrlen = mp->m_pkthdr.csum_lhlen;
1897         KASSERT(ehdrlen > 0, ("invalid ether hlen"));
1898
1899         /* Set the ether header length */
1900         vlan_macip_lens |= ehdrlen << E1000_ADVTXD_MACLEN_SHIFT;
1901         if (mp->m_pkthdr.csum_flags & CSUM_IP) {
1902                 type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_IPV4;
1903                 ip_hlen = mp->m_pkthdr.csum_iphlen;
1904                 KASSERT(ip_hlen > 0, ("invalid ip hlen"));
1905         }
1906         vlan_macip_lens |= ip_hlen;
1907
1908         type_tucmd_mlhl |= E1000_ADVTXD_DCMD_DEXT | E1000_ADVTXD_DTYP_CTXT;
1909         if (mp->m_pkthdr.csum_flags & CSUM_TCP)
1910                 type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_L4T_TCP;
1911         else if (mp->m_pkthdr.csum_flags & CSUM_UDP)
1912                 type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_L4T_UDP;
1913
1914         /* 82575 needs the queue index added */
1915         if (txr->sc->hw.mac.type == e1000_82575)
1916                 mss_l4len_idx = txr->me << 4;
1917
1918         /* Now copy bits into descriptor */
1919         TXD->vlan_macip_lens = htole32(vlan_macip_lens);
1920         TXD->type_tucmd_mlhl = htole32(type_tucmd_mlhl);
1921         TXD->seqnum_seed = htole32(0);
1922         TXD->mss_l4len_idx = htole32(mss_l4len_idx);
1923
1924         /* We've consumed the first desc, adjust counters */
1925         if (++ctxd == txr->num_tx_desc)
1926                 ctxd = 0;
1927         txr->next_avail_desc = ctxd;
1928         --txr->tx_avail;
1929
1930         return offload;
1931 }
1932
1933 static void
1934 igb_txeof(struct igb_tx_ring *txr)
1935 {
1936         struct ifnet *ifp = &txr->sc->arpcom.ac_if;
1937         int first, hdr, avail;
1938
1939         if (txr->tx_avail == txr->num_tx_desc)
1940                 return;
1941
1942         first = txr->next_to_clean;
1943         hdr = *(txr->tx_hdr);
1944
1945         if (first == hdr)
1946                 return;
1947
1948         avail = txr->tx_avail;
1949         while (first != hdr) {
1950                 struct igb_tx_buf *txbuf = &txr->tx_buf[first];
1951
1952                 ++avail;
1953                 if (txbuf->m_head) {
1954                         bus_dmamap_unload(txr->tx_tag, txbuf->map);
1955                         m_freem(txbuf->m_head);
1956                         txbuf->m_head = NULL;
1957                         ++ifp->if_opackets;
1958                 }
1959                 if (++first == txr->num_tx_desc)
1960                         first = 0;
1961         }
1962         txr->next_to_clean = first;
1963         txr->tx_avail = avail;
1964
1965         /*
1966          * If we have a minimum free, clear IFF_OACTIVE
1967          * to tell the stack that it is OK to send packets.
1968          */
1969         if (IGB_IS_NOT_OACTIVE(txr)) {
1970                 ifp->if_flags &= ~IFF_OACTIVE;
1971
1972                 /*
1973                  * We have enough TX descriptors, turn off
1974                  * the watchdog.  We allow small amount of
1975                  * packets (roughly intr_nsegs) pending on
1976                  * the transmit ring.
1977                  */
1978                 ifp->if_timer = 0;
1979         }
1980 }
1981
1982 static int
1983 igb_create_rx_ring(struct igb_rx_ring *rxr)
1984 {
1985         int rsize, i, error;
1986
1987         /*
1988          * Validate number of receive descriptors. It must not exceed
1989          * hardware maximum, and must be multiple of IGB_DBA_ALIGN.
1990          */
1991         if (((igb_rxd * sizeof(struct e1000_rx_desc)) % IGB_DBA_ALIGN) != 0 ||
1992             (igb_rxd > IGB_MAX_RXD) || (igb_rxd < IGB_MIN_RXD)) {
1993                 device_printf(rxr->sc->dev,
1994                     "Using %d RX descriptors instead of %d!\n",
1995                     IGB_DEFAULT_RXD, igb_rxd);
1996                 rxr->num_rx_desc = IGB_DEFAULT_RXD;
1997         } else {
1998                 rxr->num_rx_desc = igb_rxd;
1999         }
2000
2001         /*
2002          * Allocate RX descriptor ring
2003          */
2004         rsize = roundup2(rxr->num_rx_desc * sizeof(union e1000_adv_rx_desc),
2005             IGB_DBA_ALIGN);
2006         rxr->rxdma.dma_vaddr = bus_dmamem_coherent_any(rxr->sc->parent_tag,
2007             IGB_DBA_ALIGN, rsize, BUS_DMA_WAITOK,
2008             &rxr->rxdma.dma_tag, &rxr->rxdma.dma_map,
2009             &rxr->rxdma.dma_paddr);
2010         if (rxr->rxdma.dma_vaddr == NULL) {
2011                 device_printf(rxr->sc->dev,
2012                     "Unable to allocate RxDescriptor memory\n");
2013                 return ENOMEM;
2014         }
2015         rxr->rx_base = rxr->rxdma.dma_vaddr;
2016         bzero(rxr->rx_base, rsize);
2017
2018         rxr->rx_buf = kmalloc(sizeof(struct igb_rx_buf) * rxr->num_rx_desc,
2019             M_DEVBUF, M_WAITOK | M_ZERO);
2020
2021         /*
2022          * Create DMA tag for RX buffers
2023          */
2024         error = bus_dma_tag_create(rxr->sc->parent_tag,
2025             1, 0,               /* alignment, bounds */
2026             BUS_SPACE_MAXADDR,  /* lowaddr */
2027             BUS_SPACE_MAXADDR,  /* highaddr */
2028             NULL, NULL,         /* filter, filterarg */
2029             MCLBYTES,           /* maxsize */
2030             1,                  /* nsegments */
2031             MCLBYTES,           /* maxsegsize */
2032             BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, /* flags */
2033             &rxr->rx_tag);
2034         if (error) {
2035                 device_printf(rxr->sc->dev,
2036                     "Unable to create RX payload DMA tag\n");
2037                 kfree(rxr->rx_buf, M_DEVBUF);
2038                 rxr->rx_buf = NULL;
2039                 return error;
2040         }
2041
2042         /*
2043          * Create spare DMA map for RX buffers
2044          */
2045         error = bus_dmamap_create(rxr->rx_tag, BUS_DMA_WAITOK,
2046             &rxr->rx_sparemap);
2047         if (error) {
2048                 device_printf(rxr->sc->dev,
2049                     "Unable to create spare RX DMA maps\n");
2050                 bus_dma_tag_destroy(rxr->rx_tag);
2051                 kfree(rxr->rx_buf, M_DEVBUF);
2052                 rxr->rx_buf = NULL;
2053                 return error;
2054         }
2055
2056         /*
2057          * Create DMA maps for RX buffers
2058          */
2059         for (i = 0; i < rxr->num_rx_desc; i++) {
2060                 struct igb_rx_buf *rxbuf = &rxr->rx_buf[i];
2061
2062                 error = bus_dmamap_create(rxr->rx_tag,
2063                     BUS_DMA_WAITOK, &rxbuf->map);
2064                 if (error) {
2065                         device_printf(rxr->sc->dev,
2066                             "Unable to create RX DMA maps\n");
2067                         igb_destroy_rx_ring(rxr, i);
2068                         return error;
2069                 }
2070         }
2071         return 0;
2072 }
2073
2074 static void
2075 igb_free_rx_ring(struct igb_rx_ring *rxr)
2076 {
2077         int i;
2078
2079         for (i = 0; i < rxr->num_rx_desc; ++i) {
2080                 struct igb_rx_buf *rxbuf = &rxr->rx_buf[i];
2081
2082                 if (rxbuf->m_head != NULL) {
2083                         bus_dmamap_unload(rxr->rx_tag, rxbuf->map);
2084                         m_freem(rxbuf->m_head);
2085                         rxbuf->m_head = NULL;
2086                 }
2087         }
2088
2089         if (rxr->fmp != NULL)
2090                 m_freem(rxr->fmp);
2091         rxr->fmp = NULL;
2092         rxr->lmp = NULL;
2093 }
2094
2095 static void
2096 igb_destroy_rx_ring(struct igb_rx_ring *rxr, int ndesc)
2097 {
2098         int i;
2099
2100         if (rxr->rxdma.dma_vaddr != NULL) {
2101                 bus_dmamap_unload(rxr->rxdma.dma_tag, rxr->rxdma.dma_map);
2102                 bus_dmamem_free(rxr->rxdma.dma_tag, rxr->rxdma.dma_vaddr,
2103                     rxr->rxdma.dma_map);
2104                 bus_dma_tag_destroy(rxr->rxdma.dma_tag);
2105                 rxr->rxdma.dma_vaddr = NULL;
2106         }
2107
2108         if (rxr->rx_buf == NULL)
2109                 return;
2110
2111         for (i = 0; i < ndesc; ++i) {
2112                 struct igb_rx_buf *rxbuf = &rxr->rx_buf[i];
2113
2114                 KKASSERT(rxbuf->m_head == NULL);
2115                 bus_dmamap_destroy(rxr->rx_tag, rxbuf->map);
2116         }
2117         bus_dmamap_destroy(rxr->rx_tag, rxr->rx_sparemap);
2118         bus_dma_tag_destroy(rxr->rx_tag);
2119
2120         kfree(rxr->rx_buf, M_DEVBUF);
2121         rxr->rx_buf = NULL;
2122 }
2123
2124 static void
2125 igb_setup_rxdesc(union e1000_adv_rx_desc *rxd, const struct igb_rx_buf *rxbuf)
2126 {
2127         rxd->read.pkt_addr = htole64(rxbuf->paddr);
2128         rxd->wb.upper.status_error = 0;
2129 }
2130
2131 static int
2132 igb_newbuf(struct igb_rx_ring *rxr, int i, boolean_t wait)
2133 {
2134         struct mbuf *m;
2135         bus_dma_segment_t seg;
2136         bus_dmamap_t map;
2137         struct igb_rx_buf *rxbuf;
2138         int error, nseg;
2139
2140         m = m_getcl(wait ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR);
2141         if (m == NULL) {
2142                 if (wait) {
2143                         if_printf(&rxr->sc->arpcom.ac_if,
2144                             "Unable to allocate RX mbuf\n");
2145                 }
2146                 return ENOBUFS;
2147         }
2148         m->m_len = m->m_pkthdr.len = MCLBYTES;
2149
2150         if (rxr->sc->max_frame_size <= MCLBYTES - ETHER_ALIGN)
2151                 m_adj(m, ETHER_ALIGN);
2152
2153         error = bus_dmamap_load_mbuf_segment(rxr->rx_tag,
2154             rxr->rx_sparemap, m, &seg, 1, &nseg, BUS_DMA_NOWAIT);
2155         if (error) {
2156                 m_freem(m);
2157                 if (wait) {
2158                         if_printf(&rxr->sc->arpcom.ac_if,
2159                             "Unable to load RX mbuf\n");
2160                 }
2161                 return error;
2162         }
2163
2164         rxbuf = &rxr->rx_buf[i];
2165         if (rxbuf->m_head != NULL)
2166                 bus_dmamap_unload(rxr->rx_tag, rxbuf->map);
2167
2168         map = rxbuf->map;
2169         rxbuf->map = rxr->rx_sparemap;
2170         rxr->rx_sparemap = map;
2171
2172         rxbuf->m_head = m;
2173         rxbuf->paddr = seg.ds_addr;
2174
2175         igb_setup_rxdesc(&rxr->rx_base[i], rxbuf);
2176         return 0;
2177 }
2178
2179 static int
2180 igb_init_rx_ring(struct igb_rx_ring *rxr)
2181 {
2182         int i;
2183
2184         /* Clear the ring contents */
2185         bzero(rxr->rx_base,
2186             rxr->num_rx_desc * sizeof(union e1000_adv_rx_desc));
2187
2188         /* Now replenish the ring mbufs */
2189         for (i = 0; i < rxr->num_rx_desc; ++i) {
2190                 int error;
2191
2192                 error = igb_newbuf(rxr, i, TRUE);
2193                 if (error)
2194                         return error;
2195         }
2196
2197         /* Setup our descriptor indices */
2198         rxr->next_to_check = 0;
2199
2200         rxr->fmp = NULL;
2201         rxr->lmp = NULL;
2202         rxr->discard = FALSE;
2203
2204         return 0;
2205 }
2206
2207 static void
2208 igb_init_rx_unit(struct igb_softc *sc)
2209 {
2210         struct ifnet *ifp = &sc->arpcom.ac_if;
2211         struct e1000_hw *hw = &sc->hw;
2212         uint32_t rctl, rxcsum, srrctl = 0;
2213         int i;
2214
2215         /*
2216          * Make sure receives are disabled while setting
2217          * up the descriptor ring
2218          */
2219         rctl = E1000_READ_REG(hw, E1000_RCTL);
2220         E1000_WRITE_REG(hw, E1000_RCTL, rctl & ~E1000_RCTL_EN);
2221
2222 #if 0
2223         /*
2224         ** Set up for header split
2225         */
2226         if (igb_header_split) {
2227                 /* Use a standard mbuf for the header */
2228                 srrctl |= IGB_HDR_BUF << E1000_SRRCTL_BSIZEHDRSIZE_SHIFT;
2229                 srrctl |= E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
2230         } else
2231 #endif
2232                 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
2233
2234         /*
2235         ** Set up for jumbo frames
2236         */
2237         if (ifp->if_mtu > ETHERMTU) {
2238                 rctl |= E1000_RCTL_LPE;
2239 #if 0
2240                 if (adapter->rx_mbuf_sz == MJUMPAGESIZE) {
2241                         srrctl |= 4096 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
2242                         rctl |= E1000_RCTL_SZ_4096 | E1000_RCTL_BSEX;
2243                 } else if (adapter->rx_mbuf_sz > MJUMPAGESIZE) {
2244                         srrctl |= 8192 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
2245                         rctl |= E1000_RCTL_SZ_8192 | E1000_RCTL_BSEX;
2246                 }
2247                 /* Set maximum packet len */
2248                 psize = adapter->max_frame_size;
2249                 /* are we on a vlan? */
2250                 if (adapter->ifp->if_vlantrunk != NULL)
2251                         psize += VLAN_TAG_SIZE;
2252                 E1000_WRITE_REG(&adapter->hw, E1000_RLPML, psize);
2253 #else
2254                 srrctl |= 2048 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
2255                 rctl |= E1000_RCTL_SZ_2048;
2256 #endif
2257         } else {
2258                 rctl &= ~E1000_RCTL_LPE;
2259                 srrctl |= 2048 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
2260                 rctl |= E1000_RCTL_SZ_2048;
2261         }
2262
2263         /* Setup the Base and Length of the Rx Descriptor Rings */
2264         for (i = 0; i < sc->rx_ring_inuse; ++i) {
2265                 struct igb_rx_ring *rxr = &sc->rx_rings[i];
2266                 uint64_t bus_addr = rxr->rxdma.dma_paddr;
2267                 uint32_t rxdctl;
2268
2269                 E1000_WRITE_REG(hw, E1000_RDLEN(i),
2270                     rxr->num_rx_desc * sizeof(struct e1000_rx_desc));
2271                 E1000_WRITE_REG(hw, E1000_RDBAH(i),
2272                     (uint32_t)(bus_addr >> 32));
2273                 E1000_WRITE_REG(hw, E1000_RDBAL(i),
2274                     (uint32_t)bus_addr);
2275                 E1000_WRITE_REG(hw, E1000_SRRCTL(i), srrctl);
2276                 /* Enable this Queue */
2277                 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(i));
2278                 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
2279                 rxdctl &= 0xFFF00000;
2280                 rxdctl |= IGB_RX_PTHRESH;
2281                 rxdctl |= IGB_RX_HTHRESH << 8;
2282                 /*
2283                  * Don't set WTHRESH to a value above 1 on 82576, see:
2284                  * 82576 specification update errata #26
2285                  */
2286                 rxdctl |= IGB_RX_WTHRESH << 16;
2287                 E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl);
2288         }
2289
2290         rxcsum = E1000_READ_REG(&sc->hw, E1000_RXCSUM);
2291         rxcsum &= ~(E1000_RXCSUM_PCSS_MASK | E1000_RXCSUM_IPPCSE);
2292
2293         /*
2294          * Receive Checksum Offload for TCP and UDP
2295          *
2296          * Checksum offloading is also enabled if multiple receive
2297          * queue is to be supported, since we need it to figure out
2298          * fragments.
2299          */
2300         if ((ifp->if_capenable & IFCAP_RXCSUM) || IGB_ENABLE_HWRSS(sc)) {
2301                 /*
2302                  * NOTE:
2303                  * PCSD must be enabled to enable multiple
2304                  * receive queues.
2305                  */
2306                 rxcsum |= E1000_RXCSUM_IPOFL | E1000_RXCSUM_TUOFL |
2307                     E1000_RXCSUM_PCSD;
2308         } else {
2309                 rxcsum &= ~(E1000_RXCSUM_IPOFL | E1000_RXCSUM_TUOFL |
2310                     E1000_RXCSUM_PCSD);
2311         }
2312         E1000_WRITE_REG(&sc->hw, E1000_RXCSUM, rxcsum);
2313
2314         if (IGB_ENABLE_HWRSS(sc)) {
2315                 uint8_t key[IGB_NRSSRK * IGB_RSSRK_SIZE];
2316                 uint32_t reta_shift;
2317                 int j, r;
2318
2319                 /*
2320                  * NOTE:
2321                  * When we reach here, RSS has already been disabled
2322                  * in igb_stop(), so we could safely configure RSS key
2323                  * and redirect table.
2324                  */
2325
2326                 /*
2327                  * Configure RSS key
2328                  */
2329                 toeplitz_get_key(key, sizeof(key));
2330                 for (i = 0; i < IGB_NRSSRK; ++i) {
2331                         uint32_t rssrk;
2332
2333                         rssrk = IGB_RSSRK_VAL(key, i);
2334                         IGB_RSS_DPRINTF(sc, 1, "rssrk%d 0x%08x\n", i, rssrk);
2335
2336                         E1000_WRITE_REG(hw, E1000_RSSRK(i), rssrk);
2337                 }
2338
2339                 /*
2340                  * Configure RSS redirect table in following fashion:
2341                  * (hash & ring_cnt_mask) == rdr_table[(hash & rdr_table_mask)]
2342                  */
2343                 reta_shift = IGB_RETA_SHIFT;
2344                 if (hw->mac.type == e1000_82575)
2345                         reta_shift = IGB_RETA_SHIFT_82575;
2346
2347                 r = 0;
2348                 for (j = 0; j < IGB_NRETA; ++j) {
2349                         uint32_t reta = 0;
2350
2351                         for (i = 0; i < IGB_RETA_SIZE; ++i) {
2352                                 uint32_t q;
2353
2354                                 q = (r % sc->rx_ring_inuse) << reta_shift;
2355                                 reta |= q << (8 * i);
2356                                 ++r;
2357                         }
2358                         IGB_RSS_DPRINTF(sc, 1, "reta 0x%08x\n", reta);
2359                         E1000_WRITE_REG(hw, E1000_RETA(j), reta);
2360                 }
2361
2362                 /*
2363                  * Enable multiple receive queues.
2364                  * Enable IPv4 RSS standard hash functions.
2365                  * Disable RSS interrupt on 82575
2366                  */
2367                 E1000_WRITE_REG(&sc->hw, E1000_MRQC,
2368                                 E1000_MRQC_ENABLE_RSS_4Q |
2369                                 E1000_MRQC_RSS_FIELD_IPV4_TCP |
2370                                 E1000_MRQC_RSS_FIELD_IPV4);
2371         }
2372
2373         /* Setup the Receive Control Register */
2374         rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
2375         rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_LBM_NO |
2376             E1000_RCTL_RDMTS_HALF |
2377             (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
2378         /* Strip CRC bytes. */
2379         rctl |= E1000_RCTL_SECRC;
2380         /* Make sure VLAN Filters are off */
2381         rctl &= ~E1000_RCTL_VFE;
2382         /* Don't store bad packets */
2383         rctl &= ~E1000_RCTL_SBP;
2384
2385         /* Enable Receives */
2386         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2387
2388         /*
2389          * Setup the HW Rx Head and Tail Descriptor Pointers
2390          *   - needs to be after enable
2391          */
2392         for (i = 0; i < sc->rx_ring_inuse; ++i) {
2393                 struct igb_rx_ring *rxr = &sc->rx_rings[i];
2394
2395                 E1000_WRITE_REG(hw, E1000_RDH(i), rxr->next_to_check);
2396                 E1000_WRITE_REG(hw, E1000_RDT(i), rxr->num_rx_desc - 1);
2397         }
2398 }
2399
2400 static void
2401 igb_rxeof(struct igb_rx_ring *rxr, int count)
2402 {
2403         struct ifnet *ifp = &rxr->sc->arpcom.ac_if;
2404         union e1000_adv_rx_desc *cur;
2405         uint32_t staterr;
2406         int i;
2407
2408         i = rxr->next_to_check;
2409         cur = &rxr->rx_base[i];
2410         staterr = le32toh(cur->wb.upper.status_error);
2411
2412         if ((staterr & E1000_RXD_STAT_DD) == 0)
2413                 return;
2414
2415         while ((staterr & E1000_RXD_STAT_DD) && count != 0) {
2416                 struct pktinfo *pi = NULL, pi0;
2417                 struct igb_rx_buf *rxbuf = &rxr->rx_buf[i];
2418                 struct mbuf *m = NULL;
2419                 boolean_t eop;
2420
2421                 eop = (staterr & E1000_RXD_STAT_EOP) ? TRUE : FALSE;
2422                 if (eop)
2423                         --count;
2424
2425                 if ((staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) == 0 &&
2426                     !rxr->discard) {
2427                         struct mbuf *mp = rxbuf->m_head;
2428                         uint32_t hash, hashtype;
2429                         uint16_t vlan;
2430                         int len;
2431
2432                         len = le16toh(cur->wb.upper.length);
2433                         if (rxr->sc->hw.mac.type == e1000_i350 &&
2434                             (staterr & E1000_RXDEXT_STATERR_LB))
2435                                 vlan = be16toh(cur->wb.upper.vlan);
2436                         else
2437                                 vlan = le16toh(cur->wb.upper.vlan);
2438
2439                         hash = le32toh(cur->wb.lower.hi_dword.rss);
2440                         hashtype = le32toh(cur->wb.lower.lo_dword.data) &
2441                             E1000_RXDADV_RSSTYPE_MASK;
2442
2443                         IGB_RSS_DPRINTF(rxr->sc, 10,
2444                             "ring%d, hash 0x%08x, hashtype %u\n",
2445                             rxr->me, hash, hashtype);
2446
2447                         bus_dmamap_sync(rxr->rx_tag, rxbuf->map,
2448                             BUS_DMASYNC_POSTREAD);
2449
2450                         if (igb_newbuf(rxr, i, FALSE) != 0) {
2451                                 ifp->if_iqdrops++;
2452                                 goto discard;
2453                         }
2454
2455                         mp->m_len = len;
2456                         if (rxr->fmp == NULL) {
2457                                 mp->m_pkthdr.len = len;
2458                                 rxr->fmp = mp;
2459                                 rxr->lmp = mp;
2460                         } else {
2461                                 rxr->lmp->m_next = mp;
2462                                 rxr->lmp = rxr->lmp->m_next;
2463                                 rxr->fmp->m_pkthdr.len += len;
2464                         }
2465
2466                         if (eop) {
2467                                 m = rxr->fmp;
2468                                 rxr->fmp = NULL;
2469                                 rxr->lmp = NULL;
2470
2471                                 m->m_pkthdr.rcvif = ifp;
2472                                 ifp->if_ipackets++;
2473
2474                                 if (ifp->if_capenable & IFCAP_RXCSUM)
2475                                         igb_rxcsum(staterr, m);
2476
2477                                 if (staterr & E1000_RXD_STAT_VP) {
2478                                         m->m_pkthdr.ether_vlantag = vlan;
2479                                         m->m_flags |= M_VLANTAG;
2480                                 }
2481
2482                                 if (ifp->if_capenable & IFCAP_RSS) {
2483                                         pi = igb_rssinfo(m, &pi0,
2484                                             hash, hashtype, staterr);
2485                                 }
2486 #ifdef IGB_RSS_DEBUG
2487                                 rxr->rx_packets++;
2488 #endif
2489                         }
2490                 } else {
2491                         ifp->if_ierrors++;
2492 discard:
2493                         igb_setup_rxdesc(cur, rxbuf);
2494                         if (!eop)
2495                                 rxr->discard = TRUE;
2496                         else
2497                                 rxr->discard = FALSE;
2498                         if (rxr->fmp != NULL) {
2499                                 m_freem(rxr->fmp);
2500                                 rxr->fmp = NULL;
2501                                 rxr->lmp = NULL;
2502                         }
2503                         m = NULL;
2504                 }
2505
2506                 if (m != NULL)
2507                         ether_input_pkt(ifp, m, pi);
2508
2509                 /* Advance our pointers to the next descriptor. */
2510                 if (++i == rxr->num_rx_desc)
2511                         i = 0;
2512
2513                 cur = &rxr->rx_base[i];
2514                 staterr = le32toh(cur->wb.upper.status_error);
2515         }
2516         rxr->next_to_check = i;
2517
2518         if (--i < 0)
2519                 i = rxr->num_rx_desc - 1;
2520         E1000_WRITE_REG(&rxr->sc->hw, E1000_RDT(rxr->me), i);
2521 }
2522
2523
2524 static void
2525 igb_set_vlan(struct igb_softc *sc)
2526 {
2527         struct e1000_hw *hw = &sc->hw;
2528         uint32_t reg;
2529 #if 0
2530         struct ifnet *ifp = sc->arpcom.ac_if;
2531 #endif
2532
2533         if (sc->vf_ifp) {
2534                 e1000_rlpml_set_vf(hw, sc->max_frame_size + VLAN_TAG_SIZE);
2535                 return;
2536         }
2537
2538         reg = E1000_READ_REG(hw, E1000_CTRL);
2539         reg |= E1000_CTRL_VME;
2540         E1000_WRITE_REG(hw, E1000_CTRL, reg);
2541
2542 #if 0
2543         /* Enable the Filter Table */
2544         if (ifp->if_capenable & IFCAP_VLAN_HWFILTER) {
2545                 reg = E1000_READ_REG(hw, E1000_RCTL);
2546                 reg &= ~E1000_RCTL_CFIEN;
2547                 reg |= E1000_RCTL_VFE;
2548                 E1000_WRITE_REG(hw, E1000_RCTL, reg);
2549         }
2550 #endif
2551
2552         /* Update the frame size */
2553         E1000_WRITE_REG(&sc->hw, E1000_RLPML,
2554             sc->max_frame_size + VLAN_TAG_SIZE);
2555
2556 #if 0
2557         /* Don't bother with table if no vlans */
2558         if ((adapter->num_vlans == 0) ||
2559             ((ifp->if_capenable & IFCAP_VLAN_HWFILTER) == 0))
2560                 return;
2561         /*
2562         ** A soft reset zero's out the VFTA, so
2563         ** we need to repopulate it now.
2564         */
2565         for (int i = 0; i < IGB_VFTA_SIZE; i++)
2566                 if (adapter->shadow_vfta[i] != 0) {
2567                         if (adapter->vf_ifp)
2568                                 e1000_vfta_set_vf(hw,
2569                                     adapter->shadow_vfta[i], TRUE);
2570                         else
2571                                 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA,
2572                                  i, adapter->shadow_vfta[i]);
2573                 }
2574 #endif
2575 }
2576
2577 static void
2578 igb_enable_intr(struct igb_softc *sc)
2579 {
2580         if (sc->intr_type != PCI_INTR_TYPE_MSIX) {
2581                 lwkt_serialize_handler_enable(&sc->main_serialize);
2582         } else {
2583                 int i;
2584
2585                 for (i = 0; i < sc->msix_cnt; ++i) {
2586                         lwkt_serialize_handler_enable(
2587                             sc->msix_data[i].msix_serialize);
2588                 }
2589         }
2590
2591         if ((sc->flags & IGB_FLAG_SHARED_INTR) == 0) {
2592                 if (sc->intr_type == PCI_INTR_TYPE_MSIX)
2593                         E1000_WRITE_REG(&sc->hw, E1000_EIAC, sc->intr_mask);
2594                 else
2595                         E1000_WRITE_REG(&sc->hw, E1000_EIAC, 0);
2596                 E1000_WRITE_REG(&sc->hw, E1000_EIAM, sc->intr_mask);
2597                 E1000_WRITE_REG(&sc->hw, E1000_EIMS, sc->intr_mask);
2598                 E1000_WRITE_REG(&sc->hw, E1000_IMS, E1000_IMS_LSC);
2599         } else {
2600                 E1000_WRITE_REG(&sc->hw, E1000_IMS, IMS_ENABLE_MASK);
2601         }
2602         E1000_WRITE_FLUSH(&sc->hw);
2603 }
2604
2605 static void
2606 igb_disable_intr(struct igb_softc *sc)
2607 {
2608         if ((sc->flags & IGB_FLAG_SHARED_INTR) == 0) {
2609                 E1000_WRITE_REG(&sc->hw, E1000_EIMC, 0xffffffff);
2610                 E1000_WRITE_REG(&sc->hw, E1000_EIAC, 0);
2611         }
2612         E1000_WRITE_REG(&sc->hw, E1000_IMC, 0xffffffff);
2613         E1000_WRITE_FLUSH(&sc->hw);
2614
2615         if (sc->intr_type != PCI_INTR_TYPE_MSIX) {
2616                 lwkt_serialize_handler_disable(&sc->main_serialize);
2617         } else {
2618                 int i;
2619
2620                 for (i = 0; i < sc->msix_cnt; ++i) {
2621                         lwkt_serialize_handler_disable(
2622                             sc->msix_data[i].msix_serialize);
2623                 }
2624         }
2625 }
2626
2627 /*
2628  * Bit of a misnomer, what this really means is
2629  * to enable OS management of the system... aka
2630  * to disable special hardware management features 
2631  */
2632 static void
2633 igb_get_mgmt(struct igb_softc *sc)
2634 {
2635         if (sc->flags & IGB_FLAG_HAS_MGMT) {
2636                 int manc2h = E1000_READ_REG(&sc->hw, E1000_MANC2H);
2637                 int manc = E1000_READ_REG(&sc->hw, E1000_MANC);
2638
2639                 /* disable hardware interception of ARP */
2640                 manc &= ~E1000_MANC_ARP_EN;
2641
2642                 /* enable receiving management packets to the host */
2643                 manc |= E1000_MANC_EN_MNG2HOST;
2644                 manc2h |= 1 << 5; /* Mng Port 623 */
2645                 manc2h |= 1 << 6; /* Mng Port 664 */
2646                 E1000_WRITE_REG(&sc->hw, E1000_MANC2H, manc2h);
2647                 E1000_WRITE_REG(&sc->hw, E1000_MANC, manc);
2648         }
2649 }
2650
2651 /*
2652  * Give control back to hardware management controller
2653  * if there is one.
2654  */
2655 static void
2656 igb_rel_mgmt(struct igb_softc *sc)
2657 {
2658         if (sc->flags & IGB_FLAG_HAS_MGMT) {
2659                 int manc = E1000_READ_REG(&sc->hw, E1000_MANC);
2660
2661                 /* Re-enable hardware interception of ARP */
2662                 manc |= E1000_MANC_ARP_EN;
2663                 manc &= ~E1000_MANC_EN_MNG2HOST;
2664
2665                 E1000_WRITE_REG(&sc->hw, E1000_MANC, manc);
2666         }
2667 }
2668
2669 /*
2670  * Sets CTRL_EXT:DRV_LOAD bit.
2671  *
2672  * For ASF and Pass Through versions of f/w this means that
2673  * the driver is loaded. 
2674  */
2675 static void
2676 igb_get_hw_control(struct igb_softc *sc)
2677 {
2678         uint32_t ctrl_ext;
2679
2680         if (sc->vf_ifp)
2681                 return;
2682
2683         /* Let firmware know the driver has taken over */
2684         ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT);
2685         E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT,
2686             ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
2687 }
2688
2689 /*
2690  * Resets CTRL_EXT:DRV_LOAD bit.
2691  *
2692  * For ASF and Pass Through versions of f/w this means that the
2693  * driver is no longer loaded.
2694  */
2695 static void
2696 igb_rel_hw_control(struct igb_softc *sc)
2697 {
2698         uint32_t ctrl_ext;
2699
2700         if (sc->vf_ifp)
2701                 return;
2702
2703         /* Let firmware taken over control of h/w */
2704         ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT);
2705         E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT,
2706             ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
2707 }
2708
2709 static int
2710 igb_is_valid_ether_addr(const uint8_t *addr)
2711 {
2712         uint8_t zero_addr[ETHER_ADDR_LEN] = { 0, 0, 0, 0, 0, 0 };
2713
2714         if ((addr[0] & 1) || !bcmp(addr, zero_addr, ETHER_ADDR_LEN))
2715                 return FALSE;
2716         return TRUE;
2717 }
2718
2719 /*
2720  * Enable PCI Wake On Lan capability
2721  */
2722 static void
2723 igb_enable_wol(device_t dev)
2724 {
2725         uint16_t cap, status;
2726         uint8_t id;
2727
2728         /* First find the capabilities pointer*/
2729         cap = pci_read_config(dev, PCIR_CAP_PTR, 2);
2730
2731         /* Read the PM Capabilities */
2732         id = pci_read_config(dev, cap, 1);
2733         if (id != PCIY_PMG)     /* Something wrong */
2734                 return;
2735
2736         /*
2737          * OK, we have the power capabilities,
2738          * so now get the status register
2739          */
2740         cap += PCIR_POWER_STATUS;
2741         status = pci_read_config(dev, cap, 2);
2742         status |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
2743         pci_write_config(dev, cap, status, 2);
2744 }
2745
2746 static void
2747 igb_update_stats_counters(struct igb_softc *sc)
2748 {
2749         struct e1000_hw *hw = &sc->hw;
2750         struct e1000_hw_stats *stats;
2751         struct ifnet *ifp = &sc->arpcom.ac_if;
2752
2753         /* 
2754          * The virtual function adapter has only a
2755          * small controlled set of stats, do only 
2756          * those and return.
2757          */
2758         if (sc->vf_ifp) {
2759                 igb_update_vf_stats_counters(sc);
2760                 return;
2761         }
2762         stats = sc->stats;
2763
2764         if (sc->hw.phy.media_type == e1000_media_type_copper ||
2765             (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
2766                 stats->symerrs +=
2767                     E1000_READ_REG(hw,E1000_SYMERRS);
2768                 stats->sec += E1000_READ_REG(hw, E1000_SEC);
2769         }
2770
2771         stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
2772         stats->mpc += E1000_READ_REG(hw, E1000_MPC);
2773         stats->scc += E1000_READ_REG(hw, E1000_SCC);
2774         stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
2775
2776         stats->mcc += E1000_READ_REG(hw, E1000_MCC);
2777         stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
2778         stats->colc += E1000_READ_REG(hw, E1000_COLC);
2779         stats->dc += E1000_READ_REG(hw, E1000_DC);
2780         stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
2781         stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
2782         stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
2783
2784         /*
2785          * For watchdog management we need to know if we have been
2786          * paused during the last interval, so capture that here.
2787          */ 
2788         sc->pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
2789         stats->xoffrxc += sc->pause_frames;
2790         stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
2791         stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
2792         stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
2793         stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
2794         stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
2795         stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
2796         stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
2797         stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
2798         stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
2799         stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
2800         stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
2801         stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
2802
2803         /* For the 64-bit byte counters the low dword must be read first. */
2804         /* Both registers clear on the read of the high dword */
2805
2806         stats->gorc += E1000_READ_REG(hw, E1000_GORCL) +
2807             ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
2808         stats->gotc += E1000_READ_REG(hw, E1000_GOTCL) +
2809             ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
2810
2811         stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
2812         stats->ruc += E1000_READ_REG(hw, E1000_RUC);
2813         stats->rfc += E1000_READ_REG(hw, E1000_RFC);
2814         stats->roc += E1000_READ_REG(hw, E1000_ROC);
2815         stats->rjc += E1000_READ_REG(hw, E1000_RJC);
2816
2817         stats->tor += E1000_READ_REG(hw, E1000_TORH);
2818         stats->tot += E1000_READ_REG(hw, E1000_TOTH);
2819
2820         stats->tpr += E1000_READ_REG(hw, E1000_TPR);
2821         stats->tpt += E1000_READ_REG(hw, E1000_TPT);
2822         stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
2823         stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
2824         stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
2825         stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
2826         stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
2827         stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
2828         stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
2829         stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
2830
2831         /* Interrupt Counts */
2832
2833         stats->iac += E1000_READ_REG(hw, E1000_IAC);
2834         stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
2835         stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
2836         stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
2837         stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
2838         stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
2839         stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
2840         stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
2841         stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
2842
2843         /* Host to Card Statistics */
2844
2845         stats->cbtmpc += E1000_READ_REG(hw, E1000_CBTMPC);
2846         stats->htdpmc += E1000_READ_REG(hw, E1000_HTDPMC);
2847         stats->cbrdpc += E1000_READ_REG(hw, E1000_CBRDPC);
2848         stats->cbrmpc += E1000_READ_REG(hw, E1000_CBRMPC);
2849         stats->rpthc += E1000_READ_REG(hw, E1000_RPTHC);
2850         stats->hgptc += E1000_READ_REG(hw, E1000_HGPTC);
2851         stats->htcbdpc += E1000_READ_REG(hw, E1000_HTCBDPC);
2852         stats->hgorc += (E1000_READ_REG(hw, E1000_HGORCL) +
2853             ((uint64_t)E1000_READ_REG(hw, E1000_HGORCH) << 32));
2854         stats->hgotc += (E1000_READ_REG(hw, E1000_HGOTCL) +
2855             ((uint64_t)E1000_READ_REG(hw, E1000_HGOTCH) << 32));
2856         stats->lenerrs += E1000_READ_REG(hw, E1000_LENERRS);
2857         stats->scvpc += E1000_READ_REG(hw, E1000_SCVPC);
2858         stats->hrmpc += E1000_READ_REG(hw, E1000_HRMPC);
2859
2860         stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
2861         stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
2862         stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
2863         stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
2864         stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
2865         stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
2866
2867         ifp->if_collisions = stats->colc;
2868
2869         /* Rx Errors */
2870         ifp->if_ierrors = stats->rxerrc + stats->crcerrs + stats->algnerrc +
2871             stats->ruc + stats->roc + stats->mpc + stats->cexterr;
2872
2873         /* Tx Errors */
2874         ifp->if_oerrors = stats->ecol + stats->latecol + sc->watchdog_events;
2875
2876         /* Driver specific counters */
2877         sc->device_control = E1000_READ_REG(hw, E1000_CTRL);
2878         sc->rx_control = E1000_READ_REG(hw, E1000_RCTL);
2879         sc->int_mask = E1000_READ_REG(hw, E1000_IMS);
2880         sc->eint_mask = E1000_READ_REG(hw, E1000_EIMS);
2881         sc->packet_buf_alloc_tx =
2882             ((E1000_READ_REG(hw, E1000_PBA) & 0xffff0000) >> 16);
2883         sc->packet_buf_alloc_rx =
2884             (E1000_READ_REG(hw, E1000_PBA) & 0xffff);
2885 }
2886
2887 static void
2888 igb_vf_init_stats(struct igb_softc *sc)
2889 {
2890         struct e1000_hw *hw = &sc->hw;
2891         struct e1000_vf_stats *stats;
2892
2893         stats = sc->stats;
2894         stats->last_gprc = E1000_READ_REG(hw, E1000_VFGPRC);
2895         stats->last_gorc = E1000_READ_REG(hw, E1000_VFGORC);
2896         stats->last_gptc = E1000_READ_REG(hw, E1000_VFGPTC);
2897         stats->last_gotc = E1000_READ_REG(hw, E1000_VFGOTC);
2898         stats->last_mprc = E1000_READ_REG(hw, E1000_VFMPRC);
2899 }
2900  
2901 static void
2902 igb_update_vf_stats_counters(struct igb_softc *sc)
2903 {
2904         struct e1000_hw *hw = &sc->hw;
2905         struct e1000_vf_stats *stats;
2906
2907         if (sc->link_speed == 0)
2908                 return;
2909
2910         stats = sc->stats;
2911         UPDATE_VF_REG(E1000_VFGPRC, stats->last_gprc, stats->gprc);
2912         UPDATE_VF_REG(E1000_VFGORC, stats->last_gorc, stats->gorc);
2913         UPDATE_VF_REG(E1000_VFGPTC, stats->last_gptc, stats->gptc);
2914         UPDATE_VF_REG(E1000_VFGOTC, stats->last_gotc, stats->gotc);
2915         UPDATE_VF_REG(E1000_VFMPRC, stats->last_mprc, stats->mprc);
2916 }
2917
2918 #ifdef IFPOLL_ENABLE
2919
2920 static void
2921 igb_npoll_status(struct ifnet *ifp, int pollhz __unused)
2922 {
2923         struct igb_softc *sc = ifp->if_softc;
2924         uint32_t reg_icr;
2925
2926         ASSERT_SERIALIZED(&sc->main_serialize);
2927
2928         reg_icr = E1000_READ_REG(&sc->hw, E1000_ICR);
2929         if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
2930                 sc->hw.mac.get_link_status = 1;
2931                 igb_update_link_status(sc);
2932         }
2933 }
2934
2935 static void
2936 igb_npoll_tx(struct ifnet *ifp, void *arg, int cycle __unused)
2937 {
2938         struct igb_tx_ring *txr = arg;
2939
2940         ASSERT_SERIALIZED(&txr->tx_serialize);
2941
2942         igb_txeof(txr);
2943         if (!ifq_is_empty(&ifp->if_snd))
2944                 if_devstart(ifp);
2945 }
2946
2947 static void
2948 igb_npoll_rx(struct ifnet *ifp __unused, void *arg, int cycle)
2949 {
2950         struct igb_rx_ring *rxr = arg;
2951
2952         ASSERT_SERIALIZED(&rxr->rx_serialize);
2953
2954         igb_rxeof(rxr, cycle);
2955 }
2956
2957 static void
2958 igb_npoll(struct ifnet *ifp, struct ifpoll_info *info)
2959 {
2960         struct igb_softc *sc = ifp->if_softc;
2961
2962         ASSERT_IFNET_SERIALIZED_ALL(ifp);
2963
2964         if (info) {
2965                 struct igb_tx_ring *txr;
2966                 int i, off;
2967
2968                 info->ifpi_status.status_func = igb_npoll_status;
2969                 info->ifpi_status.serializer = &sc->main_serialize;
2970
2971                 off = sc->tx_npoll_off;
2972                 KKASSERT(off < ncpus2);
2973                 txr = &sc->tx_rings[0];
2974                 info->ifpi_tx[off].poll_func = igb_npoll_tx;
2975                 info->ifpi_tx[off].arg = txr;
2976                 info->ifpi_tx[off].serializer = &txr->tx_serialize;
2977
2978                 off = sc->rx_npoll_off;
2979                 for (i = 0; i < sc->rx_ring_cnt; ++i) {
2980                         struct igb_rx_ring *rxr = &sc->rx_rings[i];
2981                         int idx = i + off;
2982
2983                         KKASSERT(idx < ncpus2);
2984                         info->ifpi_rx[idx].poll_func = igb_npoll_rx;
2985                         info->ifpi_rx[idx].arg = rxr;
2986                         info->ifpi_rx[idx].serializer = &rxr->rx_serialize;
2987                 }
2988
2989                 if (ifp->if_flags & IFF_RUNNING) {
2990                         if (sc->rx_ring_inuse == sc->rx_ring_cnt)
2991                                 igb_disable_intr(sc);
2992                         else
2993                                 igb_init(sc);
2994                 }
2995                 ifp->if_npoll_cpuid = sc->tx_npoll_off;
2996         } else {
2997                 if (ifp->if_flags & IFF_RUNNING) {
2998                         if (sc->rx_ring_inuse == sc->rx_ring_cnt)
2999                                 igb_enable_intr(sc);
3000                         else
3001                                 igb_init(sc);
3002                 }
3003                 ifp->if_npoll_cpuid = -1;
3004         }
3005 }
3006
3007 #endif /* IFPOLL_ENABLE */
3008
3009 static void
3010 igb_intr(void *xsc)
3011 {
3012         struct igb_softc *sc = xsc;
3013         struct ifnet *ifp = &sc->arpcom.ac_if;
3014         uint32_t eicr;
3015
3016         ASSERT_SERIALIZED(&sc->main_serialize);
3017
3018         eicr = E1000_READ_REG(&sc->hw, E1000_EICR);
3019
3020         if (eicr == 0)
3021                 return;
3022
3023         if (ifp->if_flags & IFF_RUNNING) {
3024                 struct igb_tx_ring *txr;
3025                 int i;
3026
3027                 for (i = 0; i < sc->rx_ring_inuse; ++i) {
3028                         struct igb_rx_ring *rxr = &sc->rx_rings[i];
3029
3030                         if (eicr & rxr->rx_intr_mask) {
3031                                 lwkt_serialize_enter(&rxr->rx_serialize);
3032                                 igb_rxeof(rxr, -1);
3033                                 lwkt_serialize_exit(&rxr->rx_serialize);
3034                         }
3035                 }
3036
3037                 txr = &sc->tx_rings[0];
3038                 if (eicr & txr->tx_intr_mask) {
3039                         lwkt_serialize_enter(&txr->tx_serialize);
3040                         igb_txeof(txr);
3041                         if (!ifq_is_empty(&ifp->if_snd))
3042                                 if_devstart(ifp);
3043                         lwkt_serialize_exit(&txr->tx_serialize);
3044                 }
3045         }
3046
3047         if (eicr & E1000_EICR_OTHER) {
3048                 uint32_t icr = E1000_READ_REG(&sc->hw, E1000_ICR);
3049
3050                 /* Link status change */
3051                 if (icr & E1000_ICR_LSC) {
3052                         sc->hw.mac.get_link_status = 1;
3053                         igb_update_link_status(sc);
3054                 }
3055         }
3056
3057         /*
3058          * Reading EICR has the side effect to clear interrupt mask,
3059          * so all interrupts need to be enabled here.
3060          */
3061         E1000_WRITE_REG(&sc->hw, E1000_EIMS, sc->intr_mask);
3062 }
3063
3064 static void
3065 igb_intr_shared(void *xsc)
3066 {
3067         struct igb_softc *sc = xsc;
3068         struct ifnet *ifp = &sc->arpcom.ac_if;
3069         uint32_t reg_icr;
3070
3071         ASSERT_SERIALIZED(&sc->main_serialize);
3072
3073         reg_icr = E1000_READ_REG(&sc->hw, E1000_ICR);
3074
3075         /* Hot eject?  */
3076         if (reg_icr == 0xffffffff)
3077                 return;
3078
3079         /* Definitely not our interrupt.  */
3080         if (reg_icr == 0x0)
3081                 return;
3082
3083         if ((reg_icr & E1000_ICR_INT_ASSERTED) == 0)
3084                 return;
3085
3086         if (ifp->if_flags & IFF_RUNNING) {
3087                 if (reg_icr &
3088                     (E1000_ICR_RXT0 | E1000_ICR_RXDMT0 | E1000_ICR_RXO)) {
3089                         int i;
3090
3091                         for (i = 0; i < sc->rx_ring_inuse; ++i) {
3092                                 struct igb_rx_ring *rxr = &sc->rx_rings[i];
3093
3094                                 lwkt_serialize_enter(&rxr->rx_serialize);
3095                                 igb_rxeof(rxr, -1);
3096                                 lwkt_serialize_exit(&rxr->rx_serialize);
3097                         }
3098                 }
3099
3100                 if (reg_icr & E1000_ICR_TXDW) {
3101                         struct igb_tx_ring *txr = &sc->tx_rings[0];
3102
3103                         lwkt_serialize_enter(&txr->tx_serialize);
3104                         igb_txeof(txr);
3105                         if (!ifq_is_empty(&ifp->if_snd))
3106                                 if_devstart(ifp);
3107                         lwkt_serialize_exit(&txr->tx_serialize);
3108                 }
3109         }
3110
3111         /* Link status change */
3112         if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
3113                 sc->hw.mac.get_link_status = 1;
3114                 igb_update_link_status(sc);
3115         }
3116
3117         if (reg_icr & E1000_ICR_RXO)
3118                 sc->rx_overruns++;
3119 }
3120
3121 static int
3122 igb_encap(struct igb_tx_ring *txr, struct mbuf **m_headp)
3123 {
3124         bus_dma_segment_t segs[IGB_MAX_SCATTER];
3125         bus_dmamap_t map;
3126         struct igb_tx_buf *tx_buf, *tx_buf_mapped;
3127         union e1000_adv_tx_desc *txd = NULL;
3128         struct mbuf *m_head = *m_headp;
3129         uint32_t olinfo_status = 0, cmd_type_len = 0, cmd_rs = 0;
3130         int maxsegs, nsegs, i, j, error, last = 0;
3131         uint32_t hdrlen = 0;
3132
3133         if (m_head->m_pkthdr.csum_flags & CSUM_TSO) {
3134                 error = igb_tso_pullup(txr, m_headp);
3135                 if (error)
3136                         return error;
3137                 m_head = *m_headp;
3138         }
3139
3140         /* Set basic descriptor constants */
3141         cmd_type_len |= E1000_ADVTXD_DTYP_DATA;
3142         cmd_type_len |= E1000_ADVTXD_DCMD_IFCS | E1000_ADVTXD_DCMD_DEXT;
3143         if (m_head->m_flags & M_VLANTAG)
3144                 cmd_type_len |= E1000_ADVTXD_DCMD_VLE;
3145
3146         /*
3147          * Map the packet for DMA.
3148          */
3149         tx_buf = &txr->tx_buf[txr->next_avail_desc];
3150         tx_buf_mapped = tx_buf;
3151         map = tx_buf->map;
3152
3153         maxsegs = txr->tx_avail - IGB_TX_RESERVED;
3154         KASSERT(maxsegs >= txr->spare_desc, ("not enough spare TX desc\n"));
3155         if (maxsegs > IGB_MAX_SCATTER)
3156                 maxsegs = IGB_MAX_SCATTER;
3157
3158         error = bus_dmamap_load_mbuf_defrag(txr->tx_tag, map, m_headp,
3159             segs, maxsegs, &nsegs, BUS_DMA_NOWAIT);
3160         if (error) {
3161                 if (error == ENOBUFS)
3162                         txr->sc->mbuf_defrag_failed++;
3163                 else
3164                         txr->sc->no_tx_dma_setup++;
3165
3166                 m_freem(*m_headp);
3167                 *m_headp = NULL;
3168                 return error;
3169         }
3170         bus_dmamap_sync(txr->tx_tag, map, BUS_DMASYNC_PREWRITE);
3171
3172         m_head = *m_headp;
3173
3174         /*
3175          * Set up the TX context descriptor, if any hardware offloading is
3176          * needed.  This includes CSUM, VLAN, and TSO.  It will consume one
3177          * TX descriptor.
3178          *
3179          * Unlike these chips' predecessors (em/emx), TX context descriptor
3180          * will _not_ interfere TX data fetching pipelining.
3181          */
3182         if (m_head->m_pkthdr.csum_flags & CSUM_TSO) {
3183                 igb_tso_ctx(txr, m_head, &hdrlen);
3184                 cmd_type_len |= E1000_ADVTXD_DCMD_TSE;
3185                 olinfo_status |= E1000_TXD_POPTS_IXSM << 8;
3186                 olinfo_status |= E1000_TXD_POPTS_TXSM << 8;
3187                 txr->tx_nsegs++;
3188         } else if (igb_txcsum_ctx(txr, m_head)) {
3189                 if (m_head->m_pkthdr.csum_flags & CSUM_IP)
3190                         olinfo_status |= (E1000_TXD_POPTS_IXSM << 8);
3191                 if (m_head->m_pkthdr.csum_flags & (CSUM_UDP | CSUM_TCP))
3192                         olinfo_status |= (E1000_TXD_POPTS_TXSM << 8);
3193                 txr->tx_nsegs++;
3194         }
3195
3196         txr->tx_nsegs += nsegs;
3197         if (txr->tx_nsegs >= txr->intr_nsegs) {
3198                 /*
3199                  * Report Status (RS) is turned on every intr_nsegs
3200                  * descriptors (roughly).
3201                  */
3202                 txr->tx_nsegs = 0;
3203                 cmd_rs = E1000_ADVTXD_DCMD_RS;
3204         }
3205
3206         /* Calculate payload length */
3207         olinfo_status |= ((m_head->m_pkthdr.len - hdrlen)
3208             << E1000_ADVTXD_PAYLEN_SHIFT);
3209
3210         /* 82575 needs the queue index added */
3211         if (txr->sc->hw.mac.type == e1000_82575)
3212                 olinfo_status |= txr->me << 4;
3213
3214         /* Set up our transmit descriptors */
3215         i = txr->next_avail_desc;
3216         for (j = 0; j < nsegs; j++) {
3217                 bus_size_t seg_len;
3218                 bus_addr_t seg_addr;
3219
3220                 tx_buf = &txr->tx_buf[i];
3221                 txd = (union e1000_adv_tx_desc *)&txr->tx_base[i];
3222                 seg_addr = segs[j].ds_addr;
3223                 seg_len = segs[j].ds_len;
3224
3225                 txd->read.buffer_addr = htole64(seg_addr);
3226                 txd->read.cmd_type_len = htole32(cmd_type_len | seg_len);
3227                 txd->read.olinfo_status = htole32(olinfo_status);
3228                 last = i;
3229                 if (++i == txr->num_tx_desc)
3230                         i = 0;
3231                 tx_buf->m_head = NULL;
3232         }
3233
3234         KASSERT(txr->tx_avail > nsegs, ("invalid avail TX desc\n"));
3235         txr->next_avail_desc = i;
3236         txr->tx_avail -= nsegs;
3237
3238         tx_buf->m_head = m_head;
3239         tx_buf_mapped->map = tx_buf->map;
3240         tx_buf->map = map;
3241
3242         /*
3243          * Last Descriptor of Packet needs End Of Packet (EOP)
3244          */
3245         txd->read.cmd_type_len |= htole32(E1000_ADVTXD_DCMD_EOP | cmd_rs);
3246
3247         /*
3248          * Advance the Transmit Descriptor Tail (TDT), this tells the E1000
3249          * that this frame is available to transmit.
3250          */
3251         E1000_WRITE_REG(&txr->sc->hw, E1000_TDT(txr->me), i);
3252         ++txr->tx_packets;
3253
3254         return 0;
3255 }
3256
3257 static void
3258 igb_start(struct ifnet *ifp)
3259 {
3260         struct igb_softc *sc = ifp->if_softc;
3261         struct igb_tx_ring *txr = &sc->tx_rings[0];
3262         struct mbuf *m_head;
3263
3264         ASSERT_SERIALIZED(&txr->tx_serialize);
3265
3266         if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING)
3267                 return;
3268
3269         if (!sc->link_active) {
3270                 ifq_purge(&ifp->if_snd);
3271                 return;
3272         }
3273
3274         if (!IGB_IS_NOT_OACTIVE(txr))
3275                 igb_txeof(txr);
3276
3277         while (!ifq_is_empty(&ifp->if_snd)) {
3278                 if (IGB_IS_OACTIVE(txr)) {
3279                         ifp->if_flags |= IFF_OACTIVE;
3280                         /* Set watchdog on */
3281                         ifp->if_timer = 5;
3282                         break;
3283                 }
3284
3285                 m_head = ifq_dequeue(&ifp->if_snd, NULL);
3286                 if (m_head == NULL)
3287                         break;
3288
3289                 if (igb_encap(txr, &m_head)) {
3290                         ifp->if_oerrors++;
3291                         continue;
3292                 }
3293
3294                 /* Send a copy of the frame to the BPF listener */
3295                 ETHER_BPF_MTAP(ifp, m_head);
3296         }
3297 }
3298
3299 static void
3300 igb_watchdog(struct ifnet *ifp)
3301 {
3302         struct igb_softc *sc = ifp->if_softc;
3303         struct igb_tx_ring *txr = &sc->tx_rings[0];
3304
3305         ASSERT_IFNET_SERIALIZED_ALL(ifp);
3306
3307         /* 
3308          * If flow control has paused us since last checking
3309          * it invalidates the watchdog timing, so dont run it.
3310          */
3311         if (sc->pause_frames) {
3312                 sc->pause_frames = 0;
3313                 ifp->if_timer = 5;
3314                 return;
3315         }
3316
3317         if_printf(ifp, "Watchdog timeout -- resetting\n");
3318         if_printf(ifp, "Queue(%d) tdh = %d, hw tdt = %d\n", txr->me,
3319             E1000_READ_REG(&sc->hw, E1000_TDH(txr->me)),
3320             E1000_READ_REG(&sc->hw, E1000_TDT(txr->me)));
3321         if_printf(ifp, "TX(%d) desc avail = %d, "
3322             "Next TX to Clean = %d\n",
3323             txr->me, txr->tx_avail, txr->next_to_clean);
3324
3325         ifp->if_oerrors++;
3326         sc->watchdog_events++;
3327
3328         igb_init(sc);
3329         if (!ifq_is_empty(&ifp->if_snd))
3330                 if_devstart(ifp);
3331 }
3332
3333 static void
3334 igb_set_eitr(struct igb_softc *sc, int idx, int rate)
3335 {
3336         uint32_t eitr = 0;
3337
3338         if (rate > 0) {
3339                 if (sc->hw.mac.type == e1000_82575) {
3340                         eitr = 1000000000 / 256 / rate;
3341                         /*
3342                          * NOTE:
3343                          * Document is wrong on the 2 bits left shift
3344                          */
3345                 } else {
3346                         eitr = 1000000 / rate;
3347                         eitr <<= IGB_EITR_INTVL_SHIFT;
3348                 }
3349
3350                 if (eitr == 0) {
3351                         /* Don't disable it */
3352                         eitr = 1 << IGB_EITR_INTVL_SHIFT;
3353                 } else if (eitr > IGB_EITR_INTVL_MASK) {
3354                         /* Don't allow it to be too large */
3355                         eitr = IGB_EITR_INTVL_MASK;
3356                 }
3357         }
3358         if (sc->hw.mac.type == e1000_82575)
3359                 eitr |= eitr << 16;
3360         else
3361                 eitr |= E1000_EITR_CNT_IGNR;
3362         E1000_WRITE_REG(&sc->hw, E1000_EITR(idx), eitr);
3363 }
3364
3365 static int
3366 igb_sysctl_intr_rate(SYSCTL_HANDLER_ARGS)
3367 {
3368         struct igb_softc *sc = (void *)arg1;
3369         struct ifnet *ifp = &sc->arpcom.ac_if;
3370         int error, intr_rate;
3371
3372         intr_rate = sc->intr_rate;
3373         error = sysctl_handle_int(oidp, &intr_rate, 0, req);
3374         if (error || req->newptr == NULL)
3375                 return error;
3376         if (intr_rate < 0)
3377                 return EINVAL;
3378
3379         ifnet_serialize_all(ifp);
3380
3381         sc->intr_rate = intr_rate;
3382         if (ifp->if_flags & IFF_RUNNING)
3383                 igb_set_eitr(sc, 0, sc->intr_rate);
3384
3385         if (bootverbose)
3386                 if_printf(ifp, "interrupt rate set to %d/sec\n", sc->intr_rate);
3387
3388         ifnet_deserialize_all(ifp);
3389
3390         return 0;
3391 }
3392
3393 static int
3394 igb_sysctl_msix_rate(SYSCTL_HANDLER_ARGS)
3395 {
3396         struct igb_msix_data *msix = (void *)arg1;
3397         struct igb_softc *sc = msix->msix_sc;
3398         struct ifnet *ifp = &sc->arpcom.ac_if;
3399         int error, msix_rate;
3400
3401         msix_rate = msix->msix_rate;
3402         error = sysctl_handle_int(oidp, &msix_rate, 0, req);
3403         if (error || req->newptr == NULL)
3404                 return error;
3405         if (msix_rate < 0)
3406                 return EINVAL;
3407
3408         lwkt_serialize_enter(msix->msix_serialize);
3409
3410         msix->msix_rate = msix_rate;
3411         if (ifp->if_flags & IFF_RUNNING)
3412                 igb_set_eitr(sc, msix->msix_vector, msix->msix_rate);
3413
3414         if (bootverbose) {
3415                 if_printf(ifp, "%s set to %d/sec\n", msix->msix_rate_desc,
3416                     msix->msix_rate);
3417         }
3418
3419         lwkt_serialize_exit(msix->msix_serialize);
3420
3421         return 0;
3422 }
3423
3424 static int
3425 igb_sysctl_tx_intr_nsegs(SYSCTL_HANDLER_ARGS)
3426 {
3427         struct igb_softc *sc = (void *)arg1;
3428         struct ifnet *ifp = &sc->arpcom.ac_if;
3429         struct igb_tx_ring *txr = &sc->tx_rings[0];
3430         int error, nsegs;
3431
3432         nsegs = txr->intr_nsegs;
3433         error = sysctl_handle_int(oidp, &nsegs, 0, req);
3434         if (error || req->newptr == NULL)
3435                 return error;
3436         if (nsegs <= 0)
3437                 return EINVAL;
3438
3439         ifnet_serialize_all(ifp);
3440
3441         if (nsegs >= txr->num_tx_desc - txr->oact_lo_desc ||
3442             nsegs >= txr->oact_hi_desc - IGB_MAX_SCATTER) {
3443                 error = EINVAL;
3444         } else {
3445                 error = 0;
3446                 txr->intr_nsegs = nsegs;
3447         }
3448
3449         ifnet_deserialize_all(ifp);
3450
3451         return error;
3452 }
3453
3454 #ifdef IFPOLL_ENABLE
3455
3456 static int
3457 igb_sysctl_npoll_rxoff(SYSCTL_HANDLER_ARGS)
3458 {
3459         struct igb_softc *sc = (void *)arg1;
3460         struct ifnet *ifp = &sc->arpcom.ac_if;
3461         int error, off;
3462
3463         off = sc->rx_npoll_off;
3464         error = sysctl_handle_int(oidp, &off, 0, req);
3465         if (error || req->newptr == NULL)
3466                 return error;
3467         if (off < 0)
3468                 return EINVAL;
3469
3470         ifnet_serialize_all(ifp);
3471         if (off >= ncpus2 || off % sc->rx_ring_cnt != 0) {
3472                 error = EINVAL;
3473         } else {
3474                 error = 0;
3475                 sc->rx_npoll_off = off;
3476         }
3477         ifnet_deserialize_all(ifp);
3478
3479         return error;
3480 }
3481
3482 static int
3483 igb_sysctl_npoll_txoff(SYSCTL_HANDLER_ARGS)
3484 {
3485         struct igb_softc *sc = (void *)arg1;
3486         struct ifnet *ifp = &sc->arpcom.ac_if;
3487         int error, off;
3488
3489         off = sc->tx_npoll_off;
3490         error = sysctl_handle_int(oidp, &off, 0, req);
3491         if (error || req->newptr == NULL)
3492                 return error;
3493         if (off < 0)
3494                 return EINVAL;
3495
3496         ifnet_serialize_all(ifp);
3497         if (off >= ncpus2) {
3498                 error = EINVAL;
3499         } else {
3500                 error = 0;
3501                 sc->tx_npoll_off = off;
3502         }
3503         ifnet_deserialize_all(ifp);
3504
3505         return error;
3506 }
3507
3508 #endif  /* IFPOLL_ENABLE */
3509
3510 static void
3511 igb_init_intr(struct igb_softc *sc)
3512 {
3513         igb_set_intr_mask(sc);
3514
3515         if ((sc->flags & IGB_FLAG_SHARED_INTR) == 0)
3516                 igb_init_unshared_intr(sc);
3517
3518         if (sc->intr_type != PCI_INTR_TYPE_MSIX) {
3519                 igb_set_eitr(sc, 0, sc->intr_rate);
3520         } else {
3521                 int i;
3522
3523                 for (i = 0; i < sc->msix_cnt; ++i)
3524                         igb_set_eitr(sc, i, sc->msix_data[i].msix_rate);
3525         }
3526 }
3527
3528 static void
3529 igb_init_unshared_intr(struct igb_softc *sc)
3530 {
3531         struct e1000_hw *hw = &sc->hw;
3532         const struct igb_rx_ring *rxr;
3533         const struct igb_tx_ring *txr;
3534         uint32_t ivar, index;
3535         int i;
3536
3537         /*
3538          * Enable extended mode
3539          */
3540         if (sc->hw.mac.type != e1000_82575) {
3541                 uint32_t gpie;
3542                 int ivar_max;
3543
3544                 gpie = E1000_GPIE_NSICR;
3545                 if (sc->intr_type == PCI_INTR_TYPE_MSIX) {
3546                         gpie |= E1000_GPIE_MSIX_MODE |
3547                             E1000_GPIE_EIAME |
3548                             E1000_GPIE_PBA;
3549                 }
3550                 E1000_WRITE_REG(hw, E1000_GPIE, gpie);
3551
3552                 /*
3553                  * Clear IVARs
3554                  */
3555                 switch (sc->hw.mac.type) {
3556                 case e1000_82580:
3557                         ivar_max = IGB_MAX_IVAR_82580;
3558                         break;
3559
3560                 case e1000_i350:
3561                         ivar_max = IGB_MAX_IVAR_I350;
3562                         break;
3563
3564                 case e1000_vfadapt:
3565                 case e1000_vfadapt_i350:
3566                         ivar_max = IGB_MAX_IVAR_VF;
3567                         break;
3568
3569                 case e1000_82576:
3570                         ivar_max = IGB_MAX_IVAR_82576;
3571                         break;
3572
3573                 default:
3574                         panic("unknown mac type %d\n", sc->hw.mac.type);
3575                 }
3576                 for (i = 0; i < ivar_max; ++i)
3577                         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, i, 0);
3578                 E1000_WRITE_REG(hw, E1000_IVAR_MISC, 0);
3579         } else {
3580                 uint32_t tmp;
3581
3582                 KASSERT(sc->intr_type != PCI_INTR_TYPE_MSIX,
3583                     ("82575 w/ MSI-X"));
3584                 tmp = E1000_READ_REG(hw, E1000_CTRL_EXT);
3585                 tmp |= E1000_CTRL_EXT_IRCA;
3586                 E1000_WRITE_REG(hw, E1000_CTRL_EXT, tmp);
3587         }
3588
3589         /*
3590          * Map TX/RX interrupts to EICR
3591          */
3592         switch (sc->hw.mac.type) {
3593         case e1000_82580:
3594         case e1000_i350:
3595         case e1000_vfadapt:
3596         case e1000_vfadapt_i350:
3597                 /* RX entries */
3598                 for (i = 0; i < sc->rx_ring_inuse; ++i) {
3599                         rxr = &sc->rx_rings[i];
3600
3601                         index = i >> 1;
3602                         ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
3603
3604                         if (i & 1) {
3605                                 ivar &= 0xff00ffff;
3606                                 ivar |=
3607                                 (rxr->rx_intr_bit | E1000_IVAR_VALID) << 16;
3608                         } else {
3609                                 ivar &= 0xffffff00;
3610                                 ivar |=
3611                                 (rxr->rx_intr_bit | E1000_IVAR_VALID);
3612                         }
3613                         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
3614                 }
3615                 /* TX entries */
3616                 for (i = 0; i < sc->tx_ring_cnt; ++i) {
3617                         txr = &sc->tx_rings[i];
3618
3619                         index = i >> 1;
3620                         ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
3621
3622                         if (i & 1) {
3623                                 ivar &= 0x00ffffff;
3624                                 ivar |=
3625                                 (txr->tx_intr_bit | E1000_IVAR_VALID) << 24;
3626                         } else {
3627                                 ivar &= 0xffff00ff;
3628                                 ivar |=
3629                                 (txr->tx_intr_bit | E1000_IVAR_VALID) << 8;
3630                         }
3631                         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
3632                 }
3633                 if (sc->intr_type == PCI_INTR_TYPE_MSIX) {
3634                         ivar = (sc->sts_intr_bit | E1000_IVAR_VALID) << 8;
3635                         E1000_WRITE_REG(hw, E1000_IVAR_MISC, ivar);
3636                 }
3637                 break;
3638
3639         case e1000_82576:
3640                 /* RX entries */
3641                 for (i = 0; i < sc->rx_ring_inuse; ++i) {
3642                         rxr = &sc->rx_rings[i];
3643
3644                         index = i & 0x7; /* Each IVAR has two entries */
3645                         ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
3646
3647                         if (i < 8) {
3648                                 ivar &= 0xffffff00;
3649                                 ivar |=
3650                                 (rxr->rx_intr_bit | E1000_IVAR_VALID);
3651                         } else {
3652                                 ivar &= 0xff00ffff;
3653                                 ivar |=
3654                                 (rxr->rx_intr_bit | E1000_IVAR_VALID) << 16;
3655                         }
3656                         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
3657                 }
3658                 /* TX entries */
3659                 for (i = 0; i < sc->tx_ring_cnt; ++i) {
3660                         txr = &sc->tx_rings[i];
3661
3662                         index = i & 0x7; /* Each IVAR has two entries */
3663                         ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
3664
3665                         if (i < 8) {
3666                                 ivar &= 0xffff00ff;
3667                                 ivar |=
3668                                 (txr->tx_intr_bit | E1000_IVAR_VALID) << 8;
3669                         } else {
3670                                 ivar &= 0x00ffffff;
3671                                 ivar |=
3672                                 (txr->tx_intr_bit | E1000_IVAR_VALID) << 24;
3673                         }
3674                         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
3675                 }
3676                 if (sc->intr_type == PCI_INTR_TYPE_MSIX) {
3677                         ivar = (sc->sts_intr_bit | E1000_IVAR_VALID) << 8;
3678                         E1000_WRITE_REG(hw, E1000_IVAR_MISC, ivar);
3679                 }
3680                 break;
3681
3682         case e1000_82575:
3683                 /*
3684                  * Enable necessary interrupt bits.
3685                  *
3686                  * The name of the register is confusing; in addition to
3687                  * configuring the first vector of MSI-X, it also configures
3688                  * which bits of EICR could be set by the hardware even when
3689                  * MSI or line interrupt is used; it thus controls interrupt
3690                  * generation.  It MUST be configured explicitly; the default
3691                  * value mentioned in the datasheet is wrong: RX queue0 and
3692                  * TX queue0 are NOT enabled by default.
3693                  */
3694                 E1000_WRITE_REG(&sc->hw, E1000_MSIXBM(0), sc->intr_mask);
3695                 break;
3696
3697         default:
3698                 panic("unknown mac type %d\n", sc->hw.mac.type);
3699         }
3700 }
3701
3702 static int
3703 igb_setup_intr(struct igb_softc *sc)
3704 {
3705         struct ifnet *ifp = &sc->arpcom.ac_if;
3706         int error;
3707
3708         if (sc->intr_type == PCI_INTR_TYPE_MSIX)
3709                 return igb_msix_setup(sc);
3710
3711         error = bus_setup_intr(sc->dev, sc->intr_res, INTR_MPSAFE,
3712             (sc->flags & IGB_FLAG_SHARED_INTR) ? igb_intr_shared : igb_intr,
3713             sc, &sc->intr_tag, &sc->main_serialize);
3714         if (error) {
3715                 device_printf(sc->dev, "Failed to register interrupt handler");
3716                 return error;
3717         }
3718
3719         ifp->if_cpuid = rman_get_cpuid(sc->intr_res);
3720         KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus);
3721
3722         return 0;
3723 }
3724
3725 static void
3726 igb_set_txintr_mask(struct igb_tx_ring *txr, int *intr_bit0, int intr_bitmax)
3727 {
3728         if (txr->sc->hw.mac.type == e1000_82575) {
3729                 txr->tx_intr_bit = 0;   /* unused */
3730                 switch (txr->me) {
3731                 case 0:
3732                         txr->tx_intr_mask = E1000_EICR_TX_QUEUE0;
3733                         break;
3734                 case 1:
3735                         txr->tx_intr_mask = E1000_EICR_TX_QUEUE1;
3736                         break;
3737                 case 2:
3738                         txr->tx_intr_mask = E1000_EICR_TX_QUEUE2;
3739                         break;
3740                 case 3:
3741                         txr->tx_intr_mask = E1000_EICR_TX_QUEUE3;
3742                         break;
3743                 default:
3744                         panic("unsupported # of TX ring, %d\n", txr->me);
3745                 }
3746         } else {
3747                 int intr_bit = *intr_bit0;
3748
3749                 txr->tx_intr_bit = intr_bit % intr_bitmax;
3750                 txr->tx_intr_mask = 1 << txr->tx_intr_bit;
3751
3752                 *intr_bit0 = intr_bit + 1;
3753         }
3754 }
3755
3756 static void
3757 igb_set_rxintr_mask(struct igb_rx_ring *rxr, int *intr_bit0, int intr_bitmax)
3758 {
3759         if (rxr->sc->hw.mac.type == e1000_82575) {
3760                 rxr->rx_intr_bit = 0;   /* unused */
3761                 switch (rxr->me) {
3762                 case 0:
3763                         rxr->rx_intr_mask = E1000_EICR_RX_QUEUE0;
3764                         break;
3765                 case 1:
3766                         rxr->rx_intr_mask = E1000_EICR_RX_QUEUE1;
3767                         break;
3768                 case 2:
3769                         rxr->rx_intr_mask = E1000_EICR_RX_QUEUE2;
3770                         break;
3771                 case 3:
3772                         rxr->rx_intr_mask = E1000_EICR_RX_QUEUE3;
3773                         break;
3774                 default:
3775                         panic("unsupported # of RX ring, %d\n", rxr->me);
3776                 }
3777         } else {
3778                 int intr_bit = *intr_bit0;
3779
3780                 rxr->rx_intr_bit = intr_bit % intr_bitmax;
3781                 rxr->rx_intr_mask = 1 << rxr->rx_intr_bit;
3782
3783                 *intr_bit0 = intr_bit + 1;
3784         }
3785 }
3786
3787 static void
3788 igb_serialize(struct ifnet *ifp, enum ifnet_serialize slz)
3789 {
3790         struct igb_softc *sc = ifp->if_softc;
3791
3792         ifnet_serialize_array_enter(sc->serializes, sc->serialize_cnt,
3793             sc->tx_serialize, sc->rx_serialize, slz);
3794 }
3795
3796 static void
3797 igb_deserialize(struct ifnet *ifp, enum ifnet_serialize slz)
3798 {
3799         struct igb_softc *sc = ifp->if_softc;
3800
3801         ifnet_serialize_array_exit(sc->serializes, sc->serialize_cnt,
3802             sc->tx_serialize, sc->rx_serialize, slz);
3803 }
3804
3805 static int
3806 igb_tryserialize(struct ifnet *ifp, enum ifnet_serialize slz)
3807 {
3808         struct igb_softc *sc = ifp->if_softc;
3809
3810         return ifnet_serialize_array_try(sc->serializes, sc->serialize_cnt,
3811             sc->tx_serialize, sc->rx_serialize, slz);
3812 }
3813
3814 #ifdef INVARIANTS
3815
3816 static void
3817 igb_serialize_assert(struct ifnet *ifp, enum ifnet_serialize slz,
3818     boolean_t serialized)
3819 {
3820         struct igb_softc *sc = ifp->if_softc;
3821
3822         ifnet_serialize_array_assert(sc->serializes, sc->serialize_cnt,
3823             sc->tx_serialize, sc->rx_serialize, slz, serialized);
3824 }
3825
3826 #endif  /* INVARIANTS */
3827
3828 static void
3829 igb_set_intr_mask(struct igb_softc *sc)
3830 {
3831         int i;
3832
3833         sc->intr_mask = sc->sts_intr_mask;
3834         for (i = 0; i < sc->rx_ring_inuse; ++i)
3835                 sc->intr_mask |= sc->rx_rings[i].rx_intr_mask;
3836         for (i = 0; i < sc->tx_ring_cnt; ++i)
3837                 sc->intr_mask |= sc->tx_rings[i].tx_intr_mask;
3838         if (bootverbose) {
3839                 if_printf(&sc->arpcom.ac_if, "intr mask 0x%08x\n",
3840                     sc->intr_mask);
3841         }
3842 }
3843
3844 static int
3845 igb_alloc_intr(struct igb_softc *sc)
3846 {
3847         int i, intr_bit, intr_bitmax;
3848         u_int intr_flags;
3849
3850         igb_msix_try_alloc(sc);
3851         if (sc->intr_type == PCI_INTR_TYPE_MSIX)
3852                 goto done;
3853
3854         /*
3855          * Allocate MSI/legacy interrupt resource
3856          */
3857         sc->intr_type = pci_alloc_1intr(sc->dev, igb_msi_enable,
3858             &sc->intr_rid, &intr_flags);
3859
3860         if (sc->intr_type == PCI_INTR_TYPE_LEGACY) {
3861                 int unshared;
3862
3863                 unshared = device_getenv_int(sc->dev, "irq.unshared", 0);
3864                 if (!unshared) {
3865                         sc->flags |= IGB_FLAG_SHARED_INTR;
3866                         if (bootverbose)
3867                                 device_printf(sc->dev, "IRQ shared\n");
3868                 } else {
3869                         intr_flags &= ~RF_SHAREABLE;
3870                         if (bootverbose)
3871                                 device_printf(sc->dev, "IRQ unshared\n");
3872                 }
3873         }
3874
3875         sc->intr_res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ,
3876             &sc->intr_rid, intr_flags);
3877         if (sc->intr_res == NULL) {
3878                 device_printf(sc->dev, "Unable to allocate bus resource: "
3879                     "interrupt\n");
3880                 return ENXIO;
3881         }
3882
3883         /*
3884          * Setup MSI/legacy interrupt mask
3885          */
3886         switch (sc->hw.mac.type) {
3887         case e1000_82575:
3888                 intr_bitmax = IGB_MAX_TXRXINT_82575;
3889                 break;
3890         case e1000_82580:
3891                 intr_bitmax = IGB_MAX_TXRXINT_82580;
3892                 break;
3893         case e1000_i350:
3894                 intr_bitmax = IGB_MAX_TXRXINT_I350;
3895                 break;
3896         case e1000_82576:
3897                 intr_bitmax = IGB_MAX_TXRXINT_82576;
3898                 break;
3899         default:
3900                 intr_bitmax = IGB_MIN_TXRXINT;
3901                 break;
3902         }
3903         intr_bit = 0;
3904         for (i = 0; i < sc->tx_ring_cnt; ++i)
3905                 igb_set_txintr_mask(&sc->tx_rings[i], &intr_bit, intr_bitmax);
3906         for (i = 0; i < sc->rx_ring_cnt; ++i)
3907                 igb_set_rxintr_mask(&sc->rx_rings[i], &intr_bit, intr_bitmax);
3908         sc->sts_intr_bit = 0;
3909         sc->sts_intr_mask = E1000_EICR_OTHER;
3910
3911         /* Initialize interrupt rate */
3912         sc->intr_rate = IGB_INTR_RATE;
3913 done:
3914         igb_set_ring_inuse(sc, FALSE);
3915         igb_set_intr_mask(sc);
3916         return 0;
3917 }
3918
3919 static void
3920 igb_free_intr(struct igb_softc *sc)
3921 {
3922         if (sc->intr_type != PCI_INTR_TYPE_MSIX) {
3923                 if (sc->intr_res != NULL) {
3924                         bus_release_resource(sc->dev, SYS_RES_IRQ, sc->intr_rid,
3925                             sc->intr_res);
3926                 }
3927                 if (sc->intr_type == PCI_INTR_TYPE_MSI)
3928                         pci_release_msi(sc->dev);
3929         } else {
3930                 igb_msix_free(sc, TRUE);
3931         }
3932 }
3933
3934 static void
3935 igb_teardown_intr(struct igb_softc *sc)
3936 {
3937         if (sc->intr_type != PCI_INTR_TYPE_MSIX)
3938                 bus_teardown_intr(sc->dev, sc->intr_res, sc->intr_tag);
3939         else
3940                 igb_msix_teardown(sc, sc->msix_cnt);
3941 }
3942
3943 static void
3944 igb_msix_try_alloc(struct igb_softc *sc)
3945 {
3946         int msix_enable, msix_cnt, msix_cnt2, alloc_cnt;
3947         int i, x, error;
3948         struct igb_msix_data *msix;
3949         boolean_t aggregate, setup = FALSE;
3950
3951         /*
3952          * Don't enable MSI-X on 82575, see:
3953          * 82575 specification update errata #25
3954          */
3955         if (sc->hw.mac.type == e1000_82575)
3956                 return;
3957
3958         /* Don't enable MSI-X on VF */
3959         if (sc->vf_ifp)
3960                 return;
3961
3962         msix_enable = device_getenv_int(sc->dev, "msix.enable",
3963             igb_msix_enable);
3964         if (!msix_enable)
3965                 return;
3966
3967         msix_cnt = pci_msix_count(sc->dev);
3968 #ifdef IGB_MSIX_DEBUG
3969         msix_cnt = device_getenv_int(sc->dev, "msix.count", msix_cnt);
3970 #endif
3971         if (msix_cnt <= 1) {
3972                 /* One MSI-X model does not make sense */
3973                 return;
3974         }
3975
3976         i = 0;
3977         while ((1 << (i + 1)) <= msix_cnt)
3978                 ++i;
3979         msix_cnt2 = 1 << i;
3980
3981         if (bootverbose) {
3982                 device_printf(sc->dev, "MSI-X count %d/%d\n",
3983                     msix_cnt2, msix_cnt);
3984         }
3985
3986         KKASSERT(msix_cnt2 <= msix_cnt);
3987         if (msix_cnt == msix_cnt2) {
3988                 /* We need at least one MSI-X for link status */
3989                 msix_cnt2 >>= 1;
3990                 if (msix_cnt2 <= 1) {
3991                         /* One MSI-X for RX/TX does not make sense */
3992                         device_printf(sc->dev, "not enough MSI-X for TX/RX, "
3993                             "MSI-X count %d/%d\n", msix_cnt2, msix_cnt);
3994                         return;
3995                 }
3996                 KKASSERT(msix_cnt > msix_cnt2);
3997
3998                 if (bootverbose) {
3999                         device_printf(sc->dev, "MSI-X count fixup %d/%d\n",
4000                             msix_cnt2, msix_cnt);
4001                 }
4002         }
4003
4004         sc->rx_ring_msix = sc->rx_ring_cnt;
4005         if (sc->rx_ring_msix > msix_cnt2)
4006                 sc->rx_ring_msix = msix_cnt2;
4007
4008         if (msix_cnt >= sc->tx_ring_cnt + sc->rx_ring_msix + 1) {
4009                 /*
4010                  * Independent TX/RX MSI-X
4011                  */
4012                 aggregate = FALSE;
4013                 if (bootverbose)
4014                         device_printf(sc->dev, "independent TX/RX MSI-X\n");
4015                 alloc_cnt = sc->tx_ring_cnt + sc->rx_ring_msix;
4016         } else {
4017                 /*
4018                  * Aggregate TX/RX MSI-X
4019                  */
4020                 aggregate = TRUE;
4021                 if (bootverbose)
4022                         device_printf(sc->dev, "aggregate TX/RX MSI-X\n");
4023                 alloc_cnt = msix_cnt2;
4024                 if (alloc_cnt > ncpus2)
4025                         alloc_cnt = ncpus2;
4026                 if (sc->rx_ring_msix > alloc_cnt)
4027                         sc->rx_ring_msix = alloc_cnt;
4028         }
4029         ++alloc_cnt;    /* For link status */
4030
4031         if (bootverbose) {
4032                 device_printf(sc->dev, "MSI-X alloc %d, RX ring %d\n",
4033                     alloc_cnt, sc->rx_ring_msix);
4034         }
4035
4036         sc->msix_mem_rid = PCIR_BAR(IGB_MSIX_BAR);
4037         sc->msix_mem_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY,
4038             &sc->msix_mem_rid, RF_ACTIVE);
4039         if (sc->msix_mem_res == NULL) {
4040                 device_printf(sc->dev, "Unable to map MSI-X table\n");
4041                 return;
4042         }
4043
4044         sc->msix_cnt = alloc_cnt;
4045         sc->msix_data = kmalloc(sizeof(struct igb_msix_data) * sc->msix_cnt,
4046             M_DEVBUF, M_WAITOK | M_ZERO);
4047         for (x = 0; x < sc->msix_cnt; ++x) {
4048                 msix = &sc->msix_data[x];
4049
4050                 lwkt_serialize_init(&msix->msix_serialize0);
4051                 msix->msix_sc = sc;
4052                 msix->msix_rid = -1;
4053                 msix->msix_vector = x;
4054                 msix->msix_mask = 1 << msix->msix_vector;
4055                 msix->msix_rate = IGB_INTR_RATE;
4056         }
4057
4058         x = 0;
4059         if (!aggregate) {
4060                 int offset, offset_def;
4061
4062                 if (sc->rx_ring_msix == ncpus2) {
4063                         offset = 0;
4064                 } else {
4065                         offset_def = (sc->rx_ring_msix *
4066                             device_get_unit(sc->dev)) % ncpus2;
4067
4068                         offset = device_getenv_int(sc->dev,
4069                             "msix.rxoff", offset_def);
4070                         if (offset >= ncpus2 ||
4071                             offset % sc->rx_ring_msix != 0) {
4072                                 device_printf(sc->dev,
4073                     &n