2 * Copyright (c) 1997, 1998, 1999
3 * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
32 * $FreeBSD: src/sys/pci/if_dc.c,v 1.9.2.45 2003/06/08 14:31:53 mux Exp $
36 * DEC "tulip" clone ethernet driver. Supports the DEC/Intel 21143
37 * series chips and several workalikes including the following:
39 * Macronix 98713/98715/98725/98727/98732 PMAC (www.macronix.com)
40 * Macronix/Lite-On 82c115 PNIC II (www.macronix.com)
41 * Lite-On 82c168/82c169 PNIC (www.litecom.com)
42 * ASIX Electronics AX88140A (www.asix.com.tw)
43 * ASIX Electronics AX88141 (www.asix.com.tw)
44 * ADMtek AL981 (www.admtek.com.tw)
45 * ADMtek AN985 (www.admtek.com.tw)
46 * Netgear FA511 (www.netgear.com) Appears to be rebadged ADMTek AN985
47 * Davicom DM9100, DM9102, DM9102A (www.davicom8.com)
48 * Accton EN1217 (www.accton.com)
49 * Xircom X3201 (www.xircom.com)
51 * Conexant LANfinity (www.conexant.com)
53 * Datasheets for the 21143 are available at developer.intel.com.
54 * Datasheets for the clone parts can be found at their respective sites.
55 * (Except for the PNIC; see www.freebsd.org/~wpaul/PNIC/pnic.ps.gz.)
56 * The PNIC II is essentially a Macronix 98715A chip; the only difference
57 * worth noting is that its multicast hash table is only 128 bits wide
60 * Written by Bill Paul <wpaul@ee.columbia.edu>
61 * Electrical Engineering Department
62 * Columbia University, New York City
66 * The Intel 21143 is the successor to the DEC 21140. It is basically
67 * the same as the 21140 but with a few new features. The 21143 supports
68 * three kinds of media attachments:
70 * o MII port, for 10Mbps and 100Mbps support and NWAY
71 * autonegotiation provided by an external PHY.
72 * o SYM port, for symbol mode 100Mbps support.
76 * The 100Mbps SYM port and 10baseT port can be used together in
77 * combination with the internal NWAY support to create a 10/100
78 * autosensing configuration.
80 * Note that not all tulip workalikes are handled in this driver: we only
81 * deal with those which are relatively well behaved. The Winbond is
82 * handled separately due to its different register offsets and the
83 * special handling needed for its various bugs. The PNIC is handled
84 * here, but I'm not thrilled about it.
86 * All of the workalike chips use some form of MII transceiver support
87 * with the exception of the Macronix chips, which also have a SYM port.
88 * The ASIX AX88140A is also documented to have a SYM port, but all
89 * the cards I've seen use an MII transceiver, probably because the
90 * AX88140A doesn't support internal NWAY.
93 #include "opt_ifpoll.h"
95 #include <sys/param.h>
96 #include <sys/systm.h>
97 #include <sys/sockio.h>
99 #include <sys/malloc.h>
100 #include <sys/kernel.h>
101 #include <sys/interrupt.h>
102 #include <sys/socket.h>
103 #include <sys/sysctl.h>
105 #include <sys/rman.h>
106 #include <sys/thread2.h>
109 #include <net/ifq_var.h>
110 #include <net/if_arp.h>
111 #include <net/ethernet.h>
112 #include <net/if_dl.h>
113 #include <net/if_media.h>
114 #include <net/if_poll.h>
115 #include <net/if_types.h>
116 #include <net/vlan/if_vlan_var.h>
120 #include <vm/vm.h> /* for vtophys */
121 #include <vm/pmap.h> /* for vtophys */
123 #include "../mii_layer/mii.h"
124 #include "../mii_layer/miivar.h"
126 #include <bus/pci/pcireg.h>
127 #include <bus/pci/pcivar.h>
129 #define DC_USEIOSPACE
131 #include "if_dcreg.h"
133 /* "controller miibus0" required. See GENERIC if you get errors here. */
134 #include "miibus_if.h"
137 * Various supported device vendors/types and their names.
139 static const struct dc_type dc_devs[] = {
140 { DC_VENDORID_DEC, DC_DEVICEID_21143,
141 "Intel 21143 10/100BaseTX" },
142 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9009,
143 "Davicom DM9009 10/100BaseTX" },
144 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9100,
145 "Davicom DM9100 10/100BaseTX" },
146 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102,
147 "Davicom DM9102 10/100BaseTX" },
148 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102,
149 "Davicom DM9102A 10/100BaseTX" },
150 { DC_VENDORID_ADMTEK, DC_DEVICEID_AL981,
151 "ADMtek AL981 10/100BaseTX" },
152 { DC_VENDORID_ADMTEK, DC_DEVICEID_AN985,
153 "ADMtek AN985 10/100BaseTX" },
154 { DC_VENDORID_ADMTEK, DC_DEVICEID_FA511,
155 "Netgear FA511 10/100BaseTX" },
156 { DC_VENDORID_ADMTEK, DC_DEVICEID_ADM9511,
157 "ADMtek ADM9511 10/100BaseTX" },
158 { DC_VENDORID_ADMTEK, DC_DEVICEID_ADM9513,
159 "ADMtek ADM9513 10/100BaseTX" },
160 { DC_VENDORID_ASIX, DC_DEVICEID_AX88140A,
161 "ASIX AX88140A 10/100BaseTX" },
162 { DC_VENDORID_ASIX, DC_DEVICEID_AX88140A,
163 "ASIX AX88141 10/100BaseTX" },
164 { DC_VENDORID_MX, DC_DEVICEID_98713,
165 "Macronix 98713 10/100BaseTX" },
166 { DC_VENDORID_MX, DC_DEVICEID_98713,
167 "Macronix 98713A 10/100BaseTX" },
168 { DC_VENDORID_CP, DC_DEVICEID_98713_CP,
169 "Compex RL100-TX 10/100BaseTX" },
170 { DC_VENDORID_CP, DC_DEVICEID_98713_CP,
171 "Compex RL100-TX 10/100BaseTX" },
172 { DC_VENDORID_MX, DC_DEVICEID_987x5,
173 "Macronix 98715/98715A 10/100BaseTX" },
174 { DC_VENDORID_MX, DC_DEVICEID_987x5,
175 "Macronix 98715AEC-C 10/100BaseTX" },
176 { DC_VENDORID_MX, DC_DEVICEID_987x5,
177 "Macronix 98725 10/100BaseTX" },
178 { DC_VENDORID_MX, DC_DEVICEID_98727,
179 "Macronix 98727/98732 10/100BaseTX" },
180 { DC_VENDORID_LO, DC_DEVICEID_82C115,
181 "LC82C115 PNIC II 10/100BaseTX" },
182 { DC_VENDORID_LO, DC_DEVICEID_82C168,
183 "82c168 PNIC 10/100BaseTX" },
184 { DC_VENDORID_LO, DC_DEVICEID_82C168,
185 "82c169 PNIC 10/100BaseTX" },
186 { DC_VENDORID_ACCTON, DC_DEVICEID_EN1217,
187 "Accton EN1217 10/100BaseTX" },
188 { DC_VENDORID_ACCTON, DC_DEVICEID_EN2242,
189 "Accton EN2242 MiniPCI 10/100BaseTX" },
190 { DC_VENDORID_XIRCOM, DC_DEVICEID_X3201,
191 "Xircom X3201 10/100BaseTX" },
192 { DC_VENDORID_CONEXANT, DC_DEVICEID_RS7112,
193 "Conexant LANfinity MiniPCI 10/100BaseTX" },
194 { DC_VENDORID_3COM, DC_DEVICEID_3CSOHOB,
195 "3Com OfficeConnect 10/100B" },
196 { DC_VENDORID_ABOCOM, DC_DEVICEID_FE2500,
197 "Abocom FE2500 10/100BaseTX" },
201 static int dc_probe (device_t);
202 static int dc_attach (device_t);
203 static int dc_detach (device_t);
204 static int dc_suspend (device_t);
205 static int dc_resume (device_t);
206 static void dc_acpi (device_t);
207 static const struct dc_type *dc_devtype (device_t);
208 static int dc_newbuf (struct dc_softc *, int, struct mbuf *);
209 static int dc_encap (struct dc_softc *, struct mbuf *,
211 static void dc_pnic_rx_bug_war (struct dc_softc *, int);
212 static int dc_rx_resync (struct dc_softc *);
213 static void dc_rxeof (struct dc_softc *);
214 static void dc_txeof (struct dc_softc *);
215 static void dc_tick (void *);
216 static void dc_tx_underrun (struct dc_softc *);
217 static void dc_intr (void *);
218 static void dc_start (struct ifnet *);
219 static int dc_ioctl (struct ifnet *, u_long, caddr_t,
222 static void dc_npoll (struct ifnet *, struct ifpoll_info *);
223 static void dc_npoll_compat (struct ifnet *, void *, int);
225 static void dc_init (void *);
226 static void dc_stop (struct dc_softc *);
227 static void dc_watchdog (struct ifnet *);
228 static void dc_shutdown (device_t);
229 static int dc_ifmedia_upd (struct ifnet *);
230 static void dc_ifmedia_sts (struct ifnet *, struct ifmediareq *);
232 static void dc_delay (struct dc_softc *);
233 static void dc_eeprom_idle (struct dc_softc *);
234 static void dc_eeprom_putbyte (struct dc_softc *, int);
235 static void dc_eeprom_getword (struct dc_softc *, int, u_int16_t *);
236 static void dc_eeprom_getword_pnic
237 (struct dc_softc *, int, u_int16_t *);
238 static void dc_eeprom_getword_xircom
239 (struct dc_softc *, int, u_int16_t *);
240 static void dc_eeprom_width (struct dc_softc *);
241 static void dc_read_eeprom (struct dc_softc *, caddr_t, int,
244 static void dc_mii_writebit (struct dc_softc *, int);
245 static int dc_mii_readbit (struct dc_softc *);
246 static void dc_mii_sync (struct dc_softc *);
247 static void dc_mii_send (struct dc_softc *, u_int32_t, int);
248 static int dc_mii_readreg (struct dc_softc *, struct dc_mii_frame *);
249 static int dc_mii_writereg (struct dc_softc *, struct dc_mii_frame *);
250 static int dc_miibus_readreg (device_t, int, int);
251 static int dc_miibus_writereg (device_t, int, int, int);
252 static void dc_miibus_statchg (device_t);
253 static void dc_miibus_mediainit (device_t);
255 static u_int32_t dc_crc_mask (struct dc_softc *);
256 static void dc_setcfg (struct dc_softc *, int);
257 static void dc_setfilt_21143 (struct dc_softc *);
258 static void dc_setfilt_asix (struct dc_softc *);
259 static void dc_setfilt_admtek (struct dc_softc *);
260 static void dc_setfilt_xircom (struct dc_softc *);
262 static void dc_setfilt (struct dc_softc *);
264 static void dc_reset (struct dc_softc *);
265 static int dc_list_rx_init (struct dc_softc *);
266 static int dc_list_tx_init (struct dc_softc *);
268 static void dc_read_srom (struct dc_softc *, int);
269 static void dc_parse_21143_srom (struct dc_softc *);
270 static void dc_decode_leaf_sia (struct dc_softc *,
271 struct dc_eblock_sia *);
272 static void dc_decode_leaf_mii (struct dc_softc *,
273 struct dc_eblock_mii *);
274 static void dc_decode_leaf_sym (struct dc_softc *,
275 struct dc_eblock_sym *);
276 static void dc_apply_fixup (struct dc_softc *, int);
277 static uint32_t dc_mchash_xircom(struct dc_softc *, const uint8_t *);
280 #define DC_RES SYS_RES_IOPORT
281 #define DC_RID DC_PCI_CFBIO
283 #define DC_RES SYS_RES_MEMORY
284 #define DC_RID DC_PCI_CFBMA
287 static device_method_t dc_methods[] = {
288 /* Device interface */
289 DEVMETHOD(device_probe, dc_probe),
290 DEVMETHOD(device_attach, dc_attach),
291 DEVMETHOD(device_detach, dc_detach),
292 DEVMETHOD(device_suspend, dc_suspend),
293 DEVMETHOD(device_resume, dc_resume),
294 DEVMETHOD(device_shutdown, dc_shutdown),
297 DEVMETHOD(bus_print_child, bus_generic_print_child),
298 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
301 DEVMETHOD(miibus_readreg, dc_miibus_readreg),
302 DEVMETHOD(miibus_writereg, dc_miibus_writereg),
303 DEVMETHOD(miibus_statchg, dc_miibus_statchg),
304 DEVMETHOD(miibus_mediainit, dc_miibus_mediainit),
309 static driver_t dc_driver = {
312 sizeof(struct dc_softc)
315 static devclass_t dc_devclass;
318 static int dc_quick=1;
319 SYSCTL_INT(_hw, OID_AUTO, dc_quick, CTLFLAG_RW,
320 &dc_quick,0,"do not mdevget in dc driver");
323 DECLARE_DUMMY_MODULE(if_dc);
324 DRIVER_MODULE(if_dc, cardbus, dc_driver, dc_devclass, NULL, NULL);
325 DRIVER_MODULE(if_dc, pci, dc_driver, dc_devclass, NULL, NULL);
326 DRIVER_MODULE(miibus, dc, miibus_driver, miibus_devclass, NULL, NULL);
328 #define DC_SETBIT(sc, reg, x) \
329 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x))
331 #define DC_CLRBIT(sc, reg, x) \
332 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x))
334 #define SIO_SET(x) DC_SETBIT(sc, DC_SIO, (x))
335 #define SIO_CLR(x) DC_CLRBIT(sc, DC_SIO, (x))
338 dc_delay(struct dc_softc *sc)
342 for (idx = (300 / 33) + 1; idx > 0; idx--)
343 CSR_READ_4(sc, DC_BUSCTL);
347 dc_eeprom_width(struct dc_softc *sc)
351 /* Force EEPROM to idle state. */
354 /* Enter EEPROM access mode. */
355 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL);
357 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ);
359 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
361 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS);
366 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_DATAIN);
368 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_DATAIN);
370 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK);
372 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
376 for (i = 1; i <= 12; i++) {
377 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK);
379 if (!(CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT)) {
380 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
384 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
388 /* Turn off EEPROM access mode. */
396 /* Enter EEPROM access mode. */
397 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL);
399 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ);
401 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
403 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS);
406 /* Turn off EEPROM access mode. */
411 dc_eeprom_idle(struct dc_softc *sc)
415 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL);
417 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ);
419 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
421 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS);
424 for (i = 0; i < 25; i++) {
425 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
427 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK);
431 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
433 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CS);
435 CSR_WRITE_4(sc, DC_SIO, 0x00000000);
441 * Send a read command and address to the EEPROM, check for ACK.
444 dc_eeprom_putbyte(struct dc_softc *sc, int addr)
448 d = DC_EECMD_READ >> 6;
451 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_DATAIN);
453 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_DATAIN);
455 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK);
457 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
462 * Feed in each bit and strobe the clock.
464 for (i = sc->dc_romwidth; i--;) {
465 if (addr & (1 << i)) {
466 SIO_SET(DC_SIO_EE_DATAIN);
468 SIO_CLR(DC_SIO_EE_DATAIN);
471 SIO_SET(DC_SIO_EE_CLK);
473 SIO_CLR(DC_SIO_EE_CLK);
481 * Read a word of data stored in the EEPROM at address 'addr.'
482 * The PNIC 82c168/82c169 has its own non-standard way to read
486 dc_eeprom_getword_pnic(struct dc_softc *sc, int addr, u_int16_t *dest)
491 CSR_WRITE_4(sc, DC_PN_SIOCTL, DC_PN_EEOPCODE_READ|addr);
493 for (i = 0; i < DC_TIMEOUT; i++) {
495 r = CSR_READ_4(sc, DC_SIO);
496 if (!(r & DC_PN_SIOCTL_BUSY)) {
497 *dest = (u_int16_t)(r & 0xFFFF);
506 * Read a word of data stored in the EEPROM at address 'addr.'
507 * The Xircom X3201 has its own non-standard way to read
511 dc_eeprom_getword_xircom(struct dc_softc *sc, int addr, u_int16_t *dest)
513 SIO_SET(DC_SIO_ROMSEL | DC_SIO_ROMCTL_READ);
516 CSR_WRITE_4(sc, DC_ROM, addr | 0x160);
517 *dest = (u_int16_t)CSR_READ_4(sc, DC_SIO)&0xff;
519 CSR_WRITE_4(sc, DC_ROM, addr | 0x160);
520 *dest |= ((u_int16_t)CSR_READ_4(sc, DC_SIO)&0xff) << 8;
522 SIO_CLR(DC_SIO_ROMSEL | DC_SIO_ROMCTL_READ);
526 * Read a word of data stored in the EEPROM at address 'addr.'
529 dc_eeprom_getword(struct dc_softc *sc, int addr, u_int16_t *dest)
534 /* Force EEPROM to idle state. */
537 /* Enter EEPROM access mode. */
538 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL);
540 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ);
542 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
544 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS);
548 * Send address of word we want to read.
550 dc_eeprom_putbyte(sc, addr);
553 * Start reading bits from EEPROM.
555 for (i = 0x8000; i; i >>= 1) {
556 SIO_SET(DC_SIO_EE_CLK);
558 if (CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT)
561 SIO_CLR(DC_SIO_EE_CLK);
565 /* Turn off EEPROM access mode. */
574 * Read a sequence of words from the EEPROM.
577 dc_read_eeprom(struct dc_softc *sc, caddr_t dest, int off, int cnt, int swap)
580 u_int16_t word = 0, *ptr;
582 for (i = 0; i < cnt; i++) {
584 dc_eeprom_getword_pnic(sc, off + i, &word);
585 else if (DC_IS_XIRCOM(sc))
586 dc_eeprom_getword_xircom(sc, off + i, &word);
588 dc_eeprom_getword(sc, off + i, &word);
589 ptr = (u_int16_t *)(dest + (i * 2));
600 * The following two routines are taken from the Macronix 98713
601 * Application Notes pp.19-21.
604 * Write a bit to the MII bus.
607 dc_mii_writebit(struct dc_softc *sc, int bit)
610 CSR_WRITE_4(sc, DC_SIO,
611 DC_SIO_ROMCTL_WRITE|DC_SIO_MII_DATAOUT);
613 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_WRITE);
615 DC_SETBIT(sc, DC_SIO, DC_SIO_MII_CLK);
616 DC_CLRBIT(sc, DC_SIO, DC_SIO_MII_CLK);
622 * Read a bit from the MII bus.
625 dc_mii_readbit(struct dc_softc *sc)
627 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_READ|DC_SIO_MII_DIR);
628 CSR_READ_4(sc, DC_SIO);
629 DC_SETBIT(sc, DC_SIO, DC_SIO_MII_CLK);
630 DC_CLRBIT(sc, DC_SIO, DC_SIO_MII_CLK);
631 if (CSR_READ_4(sc, DC_SIO) & DC_SIO_MII_DATAIN)
638 * Sync the PHYs by setting data bit and strobing the clock 32 times.
641 dc_mii_sync(struct dc_softc *sc)
645 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_WRITE);
647 for (i = 0; i < 32; i++)
648 dc_mii_writebit(sc, 1);
654 * Clock a series of bits through the MII.
657 dc_mii_send(struct dc_softc *sc, u_int32_t bits, int cnt)
661 for (i = (0x1 << (cnt - 1)); i; i >>= 1)
662 dc_mii_writebit(sc, bits & i);
666 * Read an PHY register through the MII.
669 dc_mii_readreg(struct dc_softc *sc, struct dc_mii_frame *frame)
674 * Set up frame for RX.
676 frame->mii_stdelim = DC_MII_STARTDELIM;
677 frame->mii_opcode = DC_MII_READOP;
678 frame->mii_turnaround = 0;
687 * Send command/address info.
689 dc_mii_send(sc, frame->mii_stdelim, 2);
690 dc_mii_send(sc, frame->mii_opcode, 2);
691 dc_mii_send(sc, frame->mii_phyaddr, 5);
692 dc_mii_send(sc, frame->mii_regaddr, 5);
696 dc_mii_writebit(sc, 1);
697 dc_mii_writebit(sc, 0);
701 ack = dc_mii_readbit(sc);
704 * Now try reading data bits. If the ack failed, we still
705 * need to clock through 16 cycles to keep the PHY(s) in sync.
708 for(i = 0; i < 16; i++) {
714 for (i = 0x8000; i; i >>= 1) {
716 if (dc_mii_readbit(sc))
717 frame->mii_data |= i;
723 dc_mii_writebit(sc, 0);
724 dc_mii_writebit(sc, 0);
732 * Write to a PHY register through the MII.
735 dc_mii_writereg(struct dc_softc *sc, struct dc_mii_frame *frame)
738 * Set up frame for TX.
741 frame->mii_stdelim = DC_MII_STARTDELIM;
742 frame->mii_opcode = DC_MII_WRITEOP;
743 frame->mii_turnaround = DC_MII_TURNAROUND;
750 dc_mii_send(sc, frame->mii_stdelim, 2);
751 dc_mii_send(sc, frame->mii_opcode, 2);
752 dc_mii_send(sc, frame->mii_phyaddr, 5);
753 dc_mii_send(sc, frame->mii_regaddr, 5);
754 dc_mii_send(sc, frame->mii_turnaround, 2);
755 dc_mii_send(sc, frame->mii_data, 16);
758 dc_mii_writebit(sc, 0);
759 dc_mii_writebit(sc, 0);
765 dc_miibus_readreg(device_t dev, int phy, int reg)
767 struct dc_mii_frame frame;
769 int i, rval, phy_reg = 0;
771 sc = device_get_softc(dev);
772 bzero((char *)&frame, sizeof(frame));
775 * Note: both the AL981 and AN985 have internal PHYs,
776 * however the AL981 provides direct access to the PHY
777 * registers while the AN985 uses a serial MII interface.
778 * The AN985's MII interface is also buggy in that you
779 * can read from any MII address (0 to 31), but only address 1
780 * behaves normally. To deal with both cases, we pretend
781 * that the PHY is at MII address 1.
783 if (DC_IS_ADMTEK(sc) && phy != DC_ADMTEK_PHYADDR)
787 * Note: the ukphy probes of the RS7112 report a PHY at
788 * MII address 0 (possibly HomePNA?) and 1 (ethernet)
789 * so we only respond to correct one.
791 if (DC_IS_CONEXANT(sc) && phy != DC_CONEXANT_PHYADDR)
794 if (sc->dc_pmode != DC_PMODE_MII) {
795 if (phy == (MII_NPHY - 1)) {
799 * Fake something to make the probe
800 * code think there's a PHY here.
802 return(BMSR_MEDIAMASK);
806 return(DC_VENDORID_LO);
807 return(DC_VENDORID_DEC);
811 return(DC_DEVICEID_82C168);
812 return(DC_DEVICEID_21143);
822 if (DC_IS_PNIC(sc)) {
823 CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_READ |
824 (phy << 23) | (reg << 18));
825 for (i = 0; i < DC_TIMEOUT; i++) {
827 rval = CSR_READ_4(sc, DC_PN_MII);
828 if (!(rval & DC_PN_MII_BUSY)) {
830 return(rval == 0xFFFF ? 0 : rval);
836 if (DC_IS_COMET(sc)) {
839 phy_reg = DC_AL_BMCR;
842 phy_reg = DC_AL_BMSR;
845 phy_reg = DC_AL_VENID;
848 phy_reg = DC_AL_DEVID;
851 phy_reg = DC_AL_ANAR;
854 phy_reg = DC_AL_LPAR;
857 phy_reg = DC_AL_ANER;
860 if_printf(&sc->arpcom.ac_if,
861 "phy_read: bad phy register %x\n", reg);
866 rval = CSR_READ_4(sc, phy_reg) & 0x0000FFFF;
873 frame.mii_phyaddr = phy;
874 frame.mii_regaddr = reg;
875 if (sc->dc_type == DC_TYPE_98713) {
876 phy_reg = CSR_READ_4(sc, DC_NETCFG);
877 CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL);
879 dc_mii_readreg(sc, &frame);
880 if (sc->dc_type == DC_TYPE_98713)
881 CSR_WRITE_4(sc, DC_NETCFG, phy_reg);
883 return(frame.mii_data);
887 dc_miibus_writereg(device_t dev, int phy, int reg, int data)
890 struct dc_mii_frame frame;
893 sc = device_get_softc(dev);
894 bzero((char *)&frame, sizeof(frame));
896 if (DC_IS_ADMTEK(sc) && phy != DC_ADMTEK_PHYADDR)
899 if (DC_IS_CONEXANT(sc) && phy != DC_CONEXANT_PHYADDR)
902 if (DC_IS_PNIC(sc)) {
903 CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_WRITE |
904 (phy << 23) | (reg << 10) | data);
905 for (i = 0; i < DC_TIMEOUT; i++) {
906 if (!(CSR_READ_4(sc, DC_PN_MII) & DC_PN_MII_BUSY))
912 if (DC_IS_COMET(sc)) {
915 phy_reg = DC_AL_BMCR;
918 phy_reg = DC_AL_BMSR;
921 phy_reg = DC_AL_VENID;
924 phy_reg = DC_AL_DEVID;
927 phy_reg = DC_AL_ANAR;
930 phy_reg = DC_AL_LPAR;
933 phy_reg = DC_AL_ANER;
936 if_printf(&sc->arpcom.ac_if,
937 "phy_write: bad phy register %x\n", reg);
942 CSR_WRITE_4(sc, phy_reg, data);
946 frame.mii_phyaddr = phy;
947 frame.mii_regaddr = reg;
948 frame.mii_data = data;
950 if (sc->dc_type == DC_TYPE_98713) {
951 phy_reg = CSR_READ_4(sc, DC_NETCFG);
952 CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL);
954 dc_mii_writereg(sc, &frame);
955 if (sc->dc_type == DC_TYPE_98713)
956 CSR_WRITE_4(sc, DC_NETCFG, phy_reg);
962 dc_miibus_statchg(device_t dev)
965 struct mii_data *mii;
968 sc = device_get_softc(dev);
969 if (DC_IS_ADMTEK(sc))
972 mii = device_get_softc(sc->dc_miibus);
973 ifm = &mii->mii_media;
974 if (DC_IS_DAVICOM(sc) &&
975 IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) {
976 dc_setcfg(sc, ifm->ifm_media);
977 sc->dc_if_media = ifm->ifm_media;
979 dc_setcfg(sc, mii->mii_media_active);
980 sc->dc_if_media = mii->mii_media_active;
987 * Special support for DM9102A cards with HomePNA PHYs. Note:
988 * with the Davicom DM9102A/DM9801 eval board that I have, it seems
989 * to be impossible to talk to the management interface of the DM9801
990 * PHY (its MDIO pin is not connected to anything). Consequently,
991 * the driver has to just 'know' about the additional mode and deal
992 * with it itself. *sigh*
995 dc_miibus_mediainit(device_t dev)
998 struct mii_data *mii;
1002 rev = pci_get_revid(dev);
1004 sc = device_get_softc(dev);
1005 mii = device_get_softc(sc->dc_miibus);
1006 ifm = &mii->mii_media;
1008 if (DC_IS_DAVICOM(sc) && rev >= DC_REVISION_DM9102A)
1009 ifmedia_add(ifm, IFM_ETHER | IFM_HPNA_1, 0, NULL);
1014 #define DC_BITS_512 9
1015 #define DC_BITS_128 7
1016 #define DC_BITS_64 6
1019 dc_crc_mask(struct dc_softc *sc)
1022 * The hash table on the PNIC II and the MX98715AEC-C/D/E
1023 * chips is only 128 bits wide.
1025 if (sc->dc_flags & DC_128BIT_HASH)
1026 return ((1 << DC_BITS_128) - 1);
1028 /* The hash table on the MX98715BEC is only 64 bits wide. */
1029 if (sc->dc_flags & DC_64BIT_HASH)
1030 return ((1 << DC_BITS_64) - 1);
1032 return ((1 << DC_BITS_512) - 1);
1036 * 21143-style RX filter setup routine. Filter programming is done by
1037 * downloading a special setup frame into the TX engine. 21143, Macronix,
1038 * PNIC, PNIC II and Davicom chips are programmed this way.
1040 * We always program the chip using 'hash perfect' mode, i.e. one perfect
1041 * address (our node address) and a 512-bit hash filter for multicast
1042 * frames. We also sneak the broadcast address into the hash filter since
1046 dc_setfilt_21143(struct dc_softc *sc)
1048 struct dc_desc *sframe;
1049 u_int32_t h, crc_mask, *sp;
1050 struct ifmultiaddr *ifma;
1054 ifp = &sc->arpcom.ac_if;
1056 i = sc->dc_cdata.dc_tx_prod;
1057 DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT);
1058 sc->dc_cdata.dc_tx_cnt++;
1059 sframe = &sc->dc_ldata->dc_tx_list[i];
1060 sp = (u_int32_t *)&sc->dc_cdata.dc_sbuf;
1061 bzero((char *)sp, DC_SFRAME_LEN);
1063 sframe->dc_data = vtophys(&sc->dc_cdata.dc_sbuf);
1064 sframe->dc_ctl = DC_SFRAME_LEN | DC_TXCTL_SETUP | DC_TXCTL_TLINK |
1065 DC_FILTER_HASHPERF | DC_TXCTL_FINT;
1067 sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)&sc->dc_cdata.dc_sbuf;
1069 /* If we want promiscuous mode, set the allframes bit. */
1070 if (ifp->if_flags & IFF_PROMISC)
1071 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
1073 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
1075 if (ifp->if_flags & IFF_ALLMULTI)
1076 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
1078 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
1080 crc_mask = dc_crc_mask(sc);
1081 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1082 if (ifma->ifma_addr->sa_family != AF_LINK)
1085 LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
1086 ETHER_ADDR_LEN) & crc_mask;
1087 sp[h >> 4] |= 1 << (h & 0xF);
1090 if (ifp->if_flags & IFF_BROADCAST) {
1091 h = ether_crc32_le(ifp->if_broadcastaddr,
1092 ETHER_ADDR_LEN) & crc_mask;
1093 sp[h >> 4] |= 1 << (h & 0xF);
1096 /* Set our MAC address */
1097 sp[39] = ((u_int16_t *)sc->arpcom.ac_enaddr)[0];
1098 sp[40] = ((u_int16_t *)sc->arpcom.ac_enaddr)[1];
1099 sp[41] = ((u_int16_t *)sc->arpcom.ac_enaddr)[2];
1101 sframe->dc_status = DC_TXSTAT_OWN;
1102 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF);
1105 * The PNIC takes an exceedingly long time to process its
1106 * setup frame; wait 10ms after posting the setup frame
1107 * before proceeding, just so it has time to swallow its
1118 dc_setfilt_admtek(struct dc_softc *sc)
1123 u_int32_t hashes[2] = { 0, 0 };
1124 struct ifmultiaddr *ifma;
1126 ifp = &sc->arpcom.ac_if;
1128 /* Init our MAC address */
1129 CSR_WRITE_4(sc, DC_AL_PAR0, *(u_int32_t *)(&sc->arpcom.ac_enaddr[0]));
1130 CSR_WRITE_4(sc, DC_AL_PAR1, *(u_int32_t *)(&sc->arpcom.ac_enaddr[4]));
1132 /* If we want promiscuous mode, set the allframes bit. */
1133 if (ifp->if_flags & IFF_PROMISC)
1134 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
1136 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
1138 if (ifp->if_flags & IFF_ALLMULTI)
1139 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
1141 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
1143 /* first, zot all the existing hash bits */
1144 CSR_WRITE_4(sc, DC_AL_MAR0, 0);
1145 CSR_WRITE_4(sc, DC_AL_MAR1, 0);
1148 * If we're already in promisc or allmulti mode, we
1149 * don't have to bother programming the multicast filter.
1151 if (ifp->if_flags & (IFF_PROMISC|IFF_ALLMULTI))
1154 /* now program new ones */
1155 if (DC_IS_CENTAUR(sc))
1156 crc_mask = dc_crc_mask(sc);
1159 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1160 if (ifma->ifma_addr->sa_family != AF_LINK)
1162 if (DC_IS_CENTAUR(sc)) {
1164 LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
1165 ETHER_ADDR_LEN) & crc_mask;
1168 LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
1170 h = (h >> 26) & crc_mask;
1173 hashes[0] |= (1 << h);
1175 hashes[1] |= (1 << (h - 32));
1178 CSR_WRITE_4(sc, DC_AL_MAR0, hashes[0]);
1179 CSR_WRITE_4(sc, DC_AL_MAR1, hashes[1]);
1185 dc_setfilt_asix(struct dc_softc *sc)
1189 u_int32_t hashes[2] = { 0, 0 };
1190 struct ifmultiaddr *ifma;
1192 ifp = &sc->arpcom.ac_if;
1194 /* Init our MAC address */
1195 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR0);
1196 CSR_WRITE_4(sc, DC_AX_FILTDATA,
1197 *(u_int32_t *)(&sc->arpcom.ac_enaddr[0]));
1198 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR1);
1199 CSR_WRITE_4(sc, DC_AX_FILTDATA,
1200 *(u_int32_t *)(&sc->arpcom.ac_enaddr[4]));
1202 /* If we want promiscuous mode, set the allframes bit. */
1203 if (ifp->if_flags & IFF_PROMISC)
1204 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
1206 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
1208 if (ifp->if_flags & IFF_ALLMULTI)
1209 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
1211 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
1214 * The ASIX chip has a special bit to enable reception
1215 * of broadcast frames.
1217 if (ifp->if_flags & IFF_BROADCAST)
1218 DC_SETBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD);
1220 DC_CLRBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD);
1222 /* first, zot all the existing hash bits */
1223 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0);
1224 CSR_WRITE_4(sc, DC_AX_FILTDATA, 0);
1225 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1);
1226 CSR_WRITE_4(sc, DC_AX_FILTDATA, 0);
1229 * If we're already in promisc or allmulti mode, we
1230 * don't have to bother programming the multicast filter.
1232 if (ifp->if_flags & (IFF_PROMISC|IFF_ALLMULTI))
1235 /* now program new ones */
1236 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1237 if (ifma->ifma_addr->sa_family != AF_LINK)
1240 LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
1242 h = (h >> 26) & 0x3f;
1244 hashes[0] |= (1 << h);
1246 hashes[1] |= (1 << (h - 32));
1249 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0);
1250 CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[0]);
1251 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1);
1252 CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[1]);
1258 dc_setfilt_xircom(struct dc_softc *sc)
1260 struct dc_desc *sframe;
1262 struct ifmultiaddr *ifma;
1266 ifp = &sc->arpcom.ac_if;
1267 KASSERT(ifp->if_flags & IFF_RUNNING,
1268 ("%s is not running yet", ifp->if_xname));
1270 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_TX_ON|DC_NETCFG_RX_ON));
1272 i = sc->dc_cdata.dc_tx_prod;
1273 DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT);
1274 sc->dc_cdata.dc_tx_cnt++;
1275 sframe = &sc->dc_ldata->dc_tx_list[i];
1276 sp = (u_int32_t *)&sc->dc_cdata.dc_sbuf;
1277 bzero(sp, DC_SFRAME_LEN);
1279 sframe->dc_data = vtophys(&sc->dc_cdata.dc_sbuf);
1280 sframe->dc_ctl = DC_SFRAME_LEN | DC_TXCTL_SETUP | DC_TXCTL_TLINK |
1281 DC_FILTER_HASHPERF | DC_TXCTL_FINT;
1283 sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)&sc->dc_cdata.dc_sbuf;
1285 /* If we want promiscuous mode, set the allframes bit. */
1286 if (ifp->if_flags & IFF_PROMISC)
1287 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
1289 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
1291 if (ifp->if_flags & IFF_ALLMULTI)
1292 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
1294 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
1296 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1297 if (ifma->ifma_addr->sa_family != AF_LINK)
1299 h = dc_mchash_xircom(sc,
1300 LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
1301 sp[h >> 4] |= 1 << (h & 0xF);
1304 if (ifp->if_flags & IFF_BROADCAST) {
1305 h = dc_mchash_xircom(sc, (caddr_t)ðerbroadcastaddr);
1306 sp[h >> 4] |= 1 << (h & 0xF);
1309 /* Set our MAC address */
1310 sp[0] = ((u_int16_t *)sc->arpcom.ac_enaddr)[0];
1311 sp[1] = ((u_int16_t *)sc->arpcom.ac_enaddr)[1];
1312 sp[2] = ((u_int16_t *)sc->arpcom.ac_enaddr)[2];
1314 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON);
1315 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ON);
1316 sframe->dc_status = DC_TXSTAT_OWN;
1317 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF);
1328 dc_setfilt(struct dc_softc *sc)
1330 if (DC_IS_INTEL(sc) || DC_IS_MACRONIX(sc) || DC_IS_PNIC(sc) ||
1331 DC_IS_PNICII(sc) || DC_IS_DAVICOM(sc) || DC_IS_CONEXANT(sc))
1332 dc_setfilt_21143(sc);
1335 dc_setfilt_asix(sc);
1337 if (DC_IS_ADMTEK(sc))
1338 dc_setfilt_admtek(sc);
1340 if (DC_IS_XIRCOM(sc))
1341 dc_setfilt_xircom(sc);
1345 * In order to fiddle with the
1346 * 'full-duplex' and '100Mbps' bits in the netconfig register, we
1347 * first have to put the transmit and/or receive logic in the idle state.
1350 dc_setcfg(struct dc_softc *sc, int media)
1355 if (IFM_SUBTYPE(media) == IFM_NONE)
1358 if (CSR_READ_4(sc, DC_NETCFG) & (DC_NETCFG_TX_ON|DC_NETCFG_RX_ON)) {
1360 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_TX_ON|DC_NETCFG_RX_ON));
1362 for (i = 0; i < DC_TIMEOUT; i++) {
1363 isr = CSR_READ_4(sc, DC_ISR);
1364 if ((isr & DC_ISR_TX_IDLE) &&
1365 ((isr & DC_ISR_RX_STATE) == DC_RXSTATE_STOPPED ||
1366 (isr & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT))
1371 if (i == DC_TIMEOUT) {
1372 if_printf(&sc->arpcom.ac_if,
1373 "failed to force tx and rx to idle state\n");
1377 if (IFM_SUBTYPE(media) == IFM_100_TX) {
1378 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL);
1379 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT);
1380 if (sc->dc_pmode == DC_PMODE_MII) {
1383 if (DC_IS_INTEL(sc)) {
1384 /* there's a write enable bit here that reads as 1 */
1385 watchdogreg = CSR_READ_4(sc, DC_WATCHDOG);
1386 watchdogreg &= ~DC_WDOG_CTLWREN;
1387 watchdogreg |= DC_WDOG_JABBERDIS;
1388 CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg);
1390 DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS);
1392 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS|
1393 DC_NETCFG_PORTSEL|DC_NETCFG_SCRAMBLER));
1394 if (sc->dc_type == DC_TYPE_98713)
1395 DC_SETBIT(sc, DC_NETCFG, (DC_NETCFG_PCS|
1396 DC_NETCFG_SCRAMBLER));
1397 if (!DC_IS_DAVICOM(sc))
1398 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL);
1399 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF);
1400 if (DC_IS_INTEL(sc))
1401 dc_apply_fixup(sc, IFM_AUTO);
1403 if (DC_IS_PNIC(sc)) {
1404 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_SPEEDSEL);
1405 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP);
1406 DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL);
1408 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL);
1409 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS);
1410 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER);
1411 if (DC_IS_INTEL(sc))
1413 (media & IFM_GMASK) == IFM_FDX ?
1414 IFM_100_TX|IFM_FDX : IFM_100_TX);
1418 if (IFM_SUBTYPE(media) == IFM_10_T) {
1419 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL);
1420 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT);
1421 if (sc->dc_pmode == DC_PMODE_MII) {
1424 /* there's a write enable bit here that reads as 1 */
1425 if (DC_IS_INTEL(sc)) {
1426 watchdogreg = CSR_READ_4(sc, DC_WATCHDOG);
1427 watchdogreg &= ~DC_WDOG_CTLWREN;
1428 watchdogreg |= DC_WDOG_JABBERDIS;
1429 CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg);
1431 DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS);
1433 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS|
1434 DC_NETCFG_PORTSEL|DC_NETCFG_SCRAMBLER));
1435 if (sc->dc_type == DC_TYPE_98713)
1436 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS);
1437 if (!DC_IS_DAVICOM(sc))
1438 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL);
1439 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF);
1440 if (DC_IS_INTEL(sc))
1441 dc_apply_fixup(sc, IFM_AUTO);
1443 if (DC_IS_PNIC(sc)) {
1444 DC_PN_GPIO_CLRBIT(sc, DC_PN_GPIO_SPEEDSEL);
1445 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP);
1446 DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL);
1448 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL);
1449 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PCS);
1450 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER);
1451 if (DC_IS_INTEL(sc)) {
1452 DC_CLRBIT(sc, DC_SIARESET, DC_SIA_RESET);
1453 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF);
1454 if ((media & IFM_GMASK) == IFM_FDX)
1455 DC_SETBIT(sc, DC_10BTCTRL, 0x7F3D);
1457 DC_SETBIT(sc, DC_10BTCTRL, 0x7F3F);
1458 DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET);
1459 DC_CLRBIT(sc, DC_10BTCTRL,
1460 DC_TCTL_AUTONEGENBL);
1462 (media & IFM_GMASK) == IFM_FDX ?
1463 IFM_10_T|IFM_FDX : IFM_10_T);
1470 * If this is a Davicom DM9102A card with a DM9801 HomePNA
1471 * PHY and we want HomePNA mode, set the portsel bit to turn
1472 * on the external MII port.
1474 if (DC_IS_DAVICOM(sc)) {
1475 if (IFM_SUBTYPE(media) == IFM_HPNA_1) {
1476 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL);
1479 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL);
1483 if ((media & IFM_GMASK) == IFM_FDX) {
1484 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX);
1485 if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc))
1486 DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX);
1488 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX);
1489 if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc))
1490 DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX);
1494 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON|DC_NETCFG_RX_ON);
1500 dc_reset(struct dc_softc *sc)
1504 DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET);
1506 for (i = 0; i < DC_TIMEOUT; i++) {
1508 if (!(CSR_READ_4(sc, DC_BUSCTL) & DC_BUSCTL_RESET))
1512 if (DC_IS_ASIX(sc) || DC_IS_ADMTEK(sc) || DC_IS_XIRCOM(sc) ||
1513 DC_IS_CONEXANT(sc)) {
1515 DC_CLRBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET);
1519 if (i == DC_TIMEOUT)
1520 if_printf(&sc->arpcom.ac_if, "reset never completed!\n");
1522 /* Wait a little while for the chip to get its brains in order. */
1525 CSR_WRITE_4(sc, DC_IMR, 0x00000000);
1526 CSR_WRITE_4(sc, DC_BUSCTL, 0x00000000);
1527 CSR_WRITE_4(sc, DC_NETCFG, 0x00000000);
1530 * Bring the SIA out of reset. In some cases, it looks
1531 * like failing to unreset the SIA soon enough gets it
1532 * into a state where it will never come out of reset
1533 * until we reset the whole chip again.
1535 if (DC_IS_INTEL(sc)) {
1536 DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET);
1537 CSR_WRITE_4(sc, DC_10BTCTRL, 0);
1538 CSR_WRITE_4(sc, DC_WATCHDOG, 0);
1544 static const struct dc_type *
1545 dc_devtype(device_t dev)
1547 const struct dc_type *t;
1552 while(t->dc_name != NULL) {
1553 if ((pci_get_vendor(dev) == t->dc_vid) &&
1554 (pci_get_device(dev) == t->dc_did)) {
1555 /* Check the PCI revision */
1556 rev = pci_get_revid(dev);
1557 if (t->dc_did == DC_DEVICEID_98713 &&
1558 rev >= DC_REVISION_98713A)
1560 if (t->dc_did == DC_DEVICEID_98713_CP &&
1561 rev >= DC_REVISION_98713A)
1563 if (t->dc_did == DC_DEVICEID_987x5 &&
1564 rev >= DC_REVISION_98715AEC_C)
1566 if (t->dc_did == DC_DEVICEID_987x5 &&
1567 rev >= DC_REVISION_98725)
1569 if (t->dc_did == DC_DEVICEID_AX88140A &&
1570 rev >= DC_REVISION_88141)
1572 if (t->dc_did == DC_DEVICEID_82C168 &&
1573 rev >= DC_REVISION_82C169)
1575 if (t->dc_did == DC_DEVICEID_DM9102 &&
1576 rev >= DC_REVISION_DM9102A)
1587 * Probe for a 21143 or clone chip. Check the PCI vendor and device
1588 * IDs against our list and return a device name if we find a match.
1589 * We do a little bit of extra work to identify the exact type of
1590 * chip. The MX98713 and MX98713A have the same PCI vendor/device ID,
1591 * but different revision IDs. The same is true for 98715/98715A
1592 * chips and the 98725, as well as the ASIX and ADMtek chips. In some
1593 * cases, the exact chip revision affects driver behavior.
1596 dc_probe(device_t dev)
1598 const struct dc_type *t;
1600 t = dc_devtype(dev);
1602 struct dc_softc *sc = device_get_softc(dev);
1604 /* Need this info to decide on a chip type. */
1606 device_set_desc(dev, t->dc_name);
1614 dc_acpi(device_t dev)
1616 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
1617 uint32_t iobase, membase, irq;
1618 struct dc_softc *sc;
1620 /* Save important PCI config data. */
1621 iobase = pci_read_config(dev, DC_PCI_CFBIO, 4);
1622 membase = pci_read_config(dev, DC_PCI_CFBMA, 4);
1623 irq = pci_read_config(dev, DC_PCI_CFIT, 4);
1625 sc = device_get_softc(dev);
1626 /* Reset the power state. */
1627 if_printf(&sc->arpcom.ac_if,
1628 "chip is in D%d power mode "
1629 "-- setting to D0\n", pci_get_powerstate(dev));
1630 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
1632 /* Restore PCI config data. */
1633 pci_write_config(dev, DC_PCI_CFBIO, iobase, 4);
1634 pci_write_config(dev, DC_PCI_CFBMA, membase, 4);
1635 pci_write_config(dev, DC_PCI_CFIT, irq, 4);
1640 dc_apply_fixup(struct dc_softc *sc, int media)
1642 struct dc_mediainfo *m;
1650 if (m->dc_media == media)
1658 for (i = 0, p = m->dc_reset_ptr; i < m->dc_reset_len; i++, p += 2) {
1659 reg = (p[0] | (p[1] << 8)) << 16;
1660 CSR_WRITE_4(sc, DC_WATCHDOG, reg);
1663 for (i = 0, p = m->dc_gp_ptr; i < m->dc_gp_len; i++, p += 2) {
1664 reg = (p[0] | (p[1] << 8)) << 16;
1665 CSR_WRITE_4(sc, DC_WATCHDOG, reg);
1672 dc_decode_leaf_sia(struct dc_softc *sc, struct dc_eblock_sia *l)
1674 struct dc_mediainfo *m;
1676 m = kmalloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_INTWAIT | M_ZERO);
1677 switch (l->dc_sia_code & ~DC_SIA_CODE_EXT){
1678 case DC_SIA_CODE_10BT:
1679 m->dc_media = IFM_10_T;
1682 case DC_SIA_CODE_10BT_FDX:
1683 m->dc_media = IFM_10_T|IFM_FDX;
1686 case DC_SIA_CODE_10B2:
1687 m->dc_media = IFM_10_2;
1690 case DC_SIA_CODE_10B5:
1691 m->dc_media = IFM_10_5;
1694 if (l->dc_sia_code & DC_SIA_CODE_EXT){
1697 (u_int8_t *)&l->dc_un.dc_sia_ext.dc_sia_gpio_ctl;
1701 (u_int8_t *)&l->dc_un.dc_sia_noext.dc_sia_gpio_ctl;
1704 m->dc_next = sc->dc_mi;
1707 sc->dc_pmode = DC_PMODE_SIA;
1713 dc_decode_leaf_sym(struct dc_softc *sc, struct dc_eblock_sym *l)
1715 struct dc_mediainfo *m;
1717 m = kmalloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_INTWAIT | M_ZERO);
1718 if (l->dc_sym_code == DC_SYM_CODE_100BT)
1719 m->dc_media = IFM_100_TX;
1721 if (l->dc_sym_code == DC_SYM_CODE_100BT_FDX)
1722 m->dc_media = IFM_100_TX|IFM_FDX;
1725 m->dc_gp_ptr = (u_int8_t *)&l->dc_sym_gpio_ctl;
1727 m->dc_next = sc->dc_mi;
1730 sc->dc_pmode = DC_PMODE_SYM;
1736 dc_decode_leaf_mii(struct dc_softc *sc, struct dc_eblock_mii *l)
1739 struct dc_mediainfo *m;
1741 m = kmalloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_INTWAIT | M_ZERO);
1742 /* We abuse IFM_AUTO to represent MII. */
1743 m->dc_media = IFM_AUTO;
1744 m->dc_gp_len = l->dc_gpr_len;
1747 p += sizeof(struct dc_eblock_mii);
1749 p += 2 * l->dc_gpr_len;
1750 m->dc_reset_len = *p;
1752 m->dc_reset_ptr = p;
1754 m->dc_next = sc->dc_mi;
1761 dc_read_srom(struct dc_softc *sc, int bits)
1766 sc->dc_srom = kmalloc(size, M_DEVBUF, M_INTWAIT);
1767 dc_read_eeprom(sc, (caddr_t)sc->dc_srom, 0, (size / 2), 0);
1771 dc_parse_21143_srom(struct dc_softc *sc)
1773 struct dc_leaf_hdr *lhdr;
1774 struct dc_eblock_hdr *hdr;
1780 loff = sc->dc_srom[27];
1781 lhdr = (struct dc_leaf_hdr *)&(sc->dc_srom[loff]);
1784 ptr += sizeof(struct dc_leaf_hdr) - 1;
1786 * Look if we got a MII media block.
1788 for (i = 0; i < lhdr->dc_mcnt; i++) {
1789 hdr = (struct dc_eblock_hdr *)ptr;
1790 if (hdr->dc_type == DC_EBLOCK_MII)
1793 ptr += (hdr->dc_len & 0x7F);
1798 * Do the same thing again. Only use SIA and SYM media
1799 * blocks if no MII media block is available.
1802 ptr += sizeof(struct dc_leaf_hdr) - 1;
1803 for (i = 0; i < lhdr->dc_mcnt; i++) {
1804 hdr = (struct dc_eblock_hdr *)ptr;
1805 switch(hdr->dc_type) {
1807 dc_decode_leaf_mii(sc, (struct dc_eblock_mii *)hdr);
1811 dc_decode_leaf_sia(sc,
1812 (struct dc_eblock_sia *)hdr);
1816 dc_decode_leaf_sym(sc,
1817 (struct dc_eblock_sym *)hdr);
1820 /* Don't care. Yet. */
1823 ptr += (hdr->dc_len & 0x7F);
1831 * Attach the interface. Allocate softc structures, do ifmedia
1832 * setup and ethernet/BPF attach.
1835 dc_attach(device_t dev)
1838 u_char eaddr[ETHER_ADDR_LEN];
1840 struct dc_softc *sc;
1843 int error = 0, rid, mac_offset;
1846 sc = device_get_softc(dev);
1847 callout_init(&sc->dc_stat_timer);
1849 ifp = &sc->arpcom.ac_if;
1850 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1853 * Handle power management nonsense.
1858 * Map control/status registers.
1860 pci_enable_busmaster(dev);
1863 sc->dc_res = bus_alloc_resource_any(dev, DC_RES, &rid, RF_ACTIVE);
1865 if (sc->dc_res == NULL) {
1866 device_printf(dev, "couldn't map ports/memory\n");
1871 sc->dc_btag = rman_get_bustag(sc->dc_res);
1872 sc->dc_bhandle = rman_get_bushandle(sc->dc_res);
1874 /* Allocate interrupt */
1876 sc->dc_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
1877 RF_SHAREABLE | RF_ACTIVE);
1879 if (sc->dc_irq == NULL) {
1880 device_printf(dev, "couldn't map interrupt\n");
1885 revision = pci_get_revid(dev);
1887 /* Get the eeprom width, but PNIC and XIRCOM have diff eeprom */
1888 if (sc->dc_info->dc_did != DC_DEVICEID_82C168 &&
1889 sc->dc_info->dc_did != DC_DEVICEID_X3201)
1890 dc_eeprom_width(sc);
1892 switch(sc->dc_info->dc_did) {
1893 case DC_DEVICEID_21143:
1894 sc->dc_type = DC_TYPE_21143;
1895 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR;
1896 sc->dc_flags |= DC_REDUCED_MII_POLL;
1897 /* Save EEPROM contents so we can parse them later. */
1898 dc_read_srom(sc, sc->dc_romwidth);
1900 case DC_DEVICEID_DM9009:
1901 case DC_DEVICEID_DM9100:
1902 case DC_DEVICEID_DM9102:
1903 sc->dc_type = DC_TYPE_DM9102;
1904 sc->dc_flags |= DC_TX_COALESCE|DC_TX_INTR_ALWAYS;
1905 sc->dc_flags |= DC_REDUCED_MII_POLL|DC_TX_STORENFWD;
1906 sc->dc_flags |= DC_TX_ALIGN;
1907 sc->dc_pmode = DC_PMODE_MII;
1908 /* Increase the latency timer value. */
1909 command = pci_read_config(dev, DC_PCI_CFLT, 4);
1910 command &= 0xFFFF00FF;
1911 command |= 0x00008000;
1912 pci_write_config(dev, DC_PCI_CFLT, command, 4);
1914 case DC_DEVICEID_AL981:
1915 sc->dc_type = DC_TYPE_AL981;
1916 sc->dc_flags |= DC_TX_USE_TX_INTR;
1917 sc->dc_flags |= DC_TX_ADMTEK_WAR;
1918 sc->dc_pmode = DC_PMODE_MII;
1919 dc_read_srom(sc, sc->dc_romwidth);
1921 case DC_DEVICEID_AN985:
1922 case DC_DEVICEID_FE2500:
1923 case DC_DEVICEID_ADM9511:
1924 case DC_DEVICEID_ADM9513:
1925 case DC_DEVICEID_FA511:
1926 case DC_DEVICEID_EN2242:
1927 case DC_DEVICEID_3CSOHOB:
1928 sc->dc_type = DC_TYPE_AN985;
1929 sc->dc_flags |= DC_64BIT_HASH;
1930 sc->dc_flags |= DC_TX_USE_TX_INTR;
1931 sc->dc_flags |= DC_TX_ADMTEK_WAR;
1932 sc->dc_pmode = DC_PMODE_MII;
1934 case DC_DEVICEID_98713:
1935 case DC_DEVICEID_98713_CP:
1936 if (revision < DC_REVISION_98713A) {
1937 sc->dc_type = DC_TYPE_98713;
1939 if (revision >= DC_REVISION_98713A) {
1940 sc->dc_type = DC_TYPE_98713A;
1941 sc->dc_flags |= DC_21143_NWAY;
1943 sc->dc_flags |= DC_REDUCED_MII_POLL;
1944 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR;
1946 case DC_DEVICEID_987x5:
1947 case DC_DEVICEID_EN1217:
1949 * Macronix MX98715AEC-C/D/E parts have only a
1950 * 128-bit hash table. We need to deal with these
1951 * in the same manner as the PNIC II so that we
1952 * get the right number of bits out of the
1955 if (revision >= DC_REVISION_98715AEC_C &&
1956 revision < DC_REVISION_98725)
1957 sc->dc_flags |= DC_128BIT_HASH;
1958 sc->dc_type = DC_TYPE_987x5;
1959 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR;
1960 sc->dc_flags |= DC_REDUCED_MII_POLL|DC_21143_NWAY;
1962 case DC_DEVICEID_98727:
1963 sc->dc_type = DC_TYPE_987x5;
1964 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR;
1965 sc->dc_flags |= DC_REDUCED_MII_POLL|DC_21143_NWAY;
1967 case DC_DEVICEID_82C115:
1968 sc->dc_type = DC_TYPE_PNICII;
1969 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR|DC_128BIT_HASH;
1970 sc->dc_flags |= DC_REDUCED_MII_POLL|DC_21143_NWAY;
1972 case DC_DEVICEID_82C168:
1973 sc->dc_type = DC_TYPE_PNIC;
1974 sc->dc_flags |= DC_TX_STORENFWD|DC_TX_INTR_ALWAYS;
1975 sc->dc_flags |= DC_PNIC_RX_BUG_WAR;
1976 sc->dc_pnic_rx_buf = kmalloc(DC_RXLEN * 5, M_DEVBUF, M_WAITOK);
1977 if (revision < DC_REVISION_82C169)
1978 sc->dc_pmode = DC_PMODE_SYM;
1980 case DC_DEVICEID_AX88140A:
1981 sc->dc_type = DC_TYPE_ASIX;
1982 sc->dc_flags |= DC_TX_USE_TX_INTR|DC_TX_INTR_FIRSTFRAG;
1983 sc->dc_flags |= DC_REDUCED_MII_POLL;
1984 sc->dc_pmode = DC_PMODE_MII;
1986 case DC_DEVICEID_RS7112:
1987 sc->dc_type = DC_TYPE_CONEXANT;
1988 sc->dc_flags |= DC_TX_INTR_ALWAYS;
1989 sc->dc_flags |= DC_REDUCED_MII_POLL;
1990 sc->dc_pmode = DC_PMODE_MII;
1991 dc_read_srom(sc, sc->dc_romwidth);
1993 case DC_DEVICEID_X3201:
1994 sc->dc_type = DC_TYPE_XIRCOM;
1995 sc->dc_flags |= (DC_TX_INTR_ALWAYS | DC_TX_COALESCE |
1998 * We don't actually need to coalesce, but we're doing
1999 * it to obtain a double word aligned buffer.
2000 * The DC_TX_COALESCE flag is required.
2002 sc->dc_pmode = DC_PMODE_MII;
2005 device_printf(dev, "unknown device: %x\n", sc->dc_info->dc_did);
2009 /* Save the cache line size. */
2010 if (DC_IS_DAVICOM(sc))
2011 sc->dc_cachesize = 0;
2013 sc->dc_cachesize = pci_read_config(dev,
2014 DC_PCI_CFLT, 4) & 0xFF;
2016 /* Reset the adapter. */
2019 /* Take 21143 out of snooze mode */
2020 if (DC_IS_INTEL(sc) || DC_IS_XIRCOM(sc)) {
2021 command = pci_read_config(dev, DC_PCI_CFDD, 4);
2022 command &= ~(DC_CFDD_SNOOZE_MODE|DC_CFDD_SLEEP_MODE);
2023 pci_write_config(dev, DC_PCI_CFDD, command, 4);
2027 * Try to learn something about the supported media.
2028 * We know that ASIX and ADMtek and Davicom devices
2029 * will *always* be using MII media, so that's a no-brainer.
2030 * The tricky ones are the Macronix/PNIC II and the
2033 if (DC_IS_INTEL(sc))
2034 dc_parse_21143_srom(sc);
2035 else if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) {
2036 if (sc->dc_type == DC_TYPE_98713)
2037 sc->dc_pmode = DC_PMODE_MII;
2039 sc->dc_pmode = DC_PMODE_SYM;
2040 } else if (!sc->dc_pmode)
2041 sc->dc_pmode = DC_PMODE_MII;
2044 * Get station address from the EEPROM.
2046 switch(sc->dc_type) {
2048 case DC_TYPE_98713A:
2050 case DC_TYPE_PNICII:
2051 dc_read_eeprom(sc, (caddr_t)&mac_offset,
2052 (DC_EE_NODEADDR_OFFSET / 2), 1, 0);
2053 dc_read_eeprom(sc, (caddr_t)&eaddr, (mac_offset / 2), 3, 0);
2056 dc_read_eeprom(sc, (caddr_t)&eaddr, 0, 3, 1);
2058 case DC_TYPE_DM9102:
2061 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0);
2065 *(u_int32_t *)(&eaddr[0]) = CSR_READ_4(sc,DC_AL_PAR0);
2066 *(u_int16_t *)(&eaddr[4]) = CSR_READ_4(sc,DC_AL_PAR1);
2068 case DC_TYPE_CONEXANT:
2069 bcopy(sc->dc_srom + DC_CONEXANT_EE_NODEADDR, &eaddr, 6);
2071 case DC_TYPE_XIRCOM:
2072 /* The MAC comes from the CIS */
2073 mac = pci_get_ether(dev);
2075 device_printf(dev, "No station address in CIS!\n");
2079 bcopy(mac, eaddr, ETHER_ADDR_LEN);
2082 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0);
2086 sc->dc_ldata = contigmalloc(sizeof(struct dc_list_data), M_DEVBUF,
2087 M_WAITOK | M_ZERO, 0, 0xffffffff, PAGE_SIZE, 0);
2089 if (sc->dc_ldata == NULL) {
2090 device_printf(dev, "no memory for list buffers!\n");
2096 ifp->if_mtu = ETHERMTU;
2097 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
2098 ifp->if_ioctl = dc_ioctl;
2099 ifp->if_start = dc_start;
2100 #ifdef IFPOLL_ENABLE
2101 ifp->if_npoll = dc_npoll;
2103 ifp->if_watchdog = dc_watchdog;
2104 ifp->if_init = dc_init;
2105 ifp->if_baudrate = 10000000;
2106 ifq_set_maxlen(&ifp->if_snd, DC_TX_LIST_CNT - 1);
2107 ifq_set_ready(&ifp->if_snd);
2110 * Do MII setup. If this is a 21143, check for a PHY on the
2111 * MII bus after applying any necessary fixups to twiddle the
2112 * GPIO bits. If we don't end up finding a PHY, restore the
2113 * old selection (SIA only or SIA/SYM) and attach the dcphy
2116 if (DC_IS_INTEL(sc)) {
2117 dc_apply_fixup(sc, IFM_AUTO);
2119 sc->dc_pmode = DC_PMODE_MII;
2123 * Setup General Purpose port mode and data so the tulip can talk
2124 * to the MII. This needs to be done before mii_phy_probe so that
2125 * we can actually see them.
2127 if (DC_IS_XIRCOM(sc)) {
2128 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_WRITE_EN | DC_SIAGP_INT1_EN |
2129 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT);
2131 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_INT1_EN |
2132 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT);
2136 error = mii_phy_probe(dev, &sc->dc_miibus,
2137 dc_ifmedia_upd, dc_ifmedia_sts);
2139 if (error && DC_IS_INTEL(sc)) {
2141 if (sc->dc_pmode != DC_PMODE_SIA)
2142 sc->dc_pmode = DC_PMODE_SYM;
2143 sc->dc_flags |= DC_21143_NWAY;
2144 mii_phy_probe(dev, &sc->dc_miibus,
2145 dc_ifmedia_upd, dc_ifmedia_sts);
2147 * For non-MII cards, we need to have the 21143
2148 * drive the LEDs. Except there are some systems
2149 * like the NEC VersaPro NoteBook PC which have no
2150 * LEDs, and twiddling these bits has adverse effects
2151 * on them. (I.e. you suddenly can't get a link.)
2153 if (pci_read_config(dev, DC_PCI_CSID, 4) != 0x80281033)
2154 sc->dc_flags |= DC_TULIP_LEDS;
2159 device_printf(dev, "MII without any PHY!\n");
2165 * Call MI attach routine.
2167 ether_ifattach(ifp, eaddr, NULL);
2169 if (DC_IS_ADMTEK(sc)) {
2171 * Set automatic TX underrun recovery for the ADMtek chips
2173 DC_SETBIT(sc, DC_AL_CR, DC_AL_CR_ATUR);
2177 * Tell the upper layer(s) we support long frames.
2179 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
2181 error = bus_setup_intr(dev, sc->dc_irq, INTR_MPSAFE,
2182 dc_intr, sc, &sc->dc_intrhand,
2183 ifp->if_serializer);
2185 ether_ifdetach(ifp);
2186 device_printf(dev, "couldn't set up irq\n");
2190 ifp->if_cpuid = rman_get_cpuid(sc->dc_irq);
2191 KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus);
2201 dc_detach(device_t dev)
2203 struct dc_softc *sc = device_get_softc(dev);
2204 struct ifnet *ifp = &sc->arpcom.ac_if;
2205 struct dc_mediainfo *m;
2207 if (device_is_attached(dev)) {
2208 lwkt_serialize_enter(ifp->if_serializer);
2210 bus_teardown_intr(dev, sc->dc_irq, sc->dc_intrhand);
2211 lwkt_serialize_exit(ifp->if_serializer);
2213 ether_ifdetach(ifp);
2217 device_delete_child(dev, sc->dc_miibus);
2218 bus_generic_detach(dev);
2221 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq);
2223 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res);
2226 contigfree(sc->dc_ldata, sizeof(struct dc_list_data), M_DEVBUF);
2227 if (sc->dc_pnic_rx_buf != NULL)
2228 kfree(sc->dc_pnic_rx_buf, M_DEVBUF);
2230 while (sc->dc_mi != NULL) {
2231 m = sc->dc_mi->dc_next;
2232 kfree(sc->dc_mi, M_DEVBUF);
2237 kfree(sc->dc_srom, M_DEVBUF);
2243 * Initialize the transmit descriptors.
2246 dc_list_tx_init(struct dc_softc *sc)
2248 struct dc_chain_data *cd;
2249 struct dc_list_data *ld;
2254 for (i = 0; i < DC_TX_LIST_CNT; i++) {
2255 if (i == (DC_TX_LIST_CNT - 1)) {
2256 ld->dc_tx_list[i].dc_next =
2257 vtophys(&ld->dc_tx_list[0]);
2259 ld->dc_tx_list[i].dc_next =
2260 vtophys(&ld->dc_tx_list[i + 1]);
2262 cd->dc_tx_chain[i] = NULL;
2263 ld->dc_tx_list[i].dc_data = 0;
2264 ld->dc_tx_list[i].dc_ctl = 0;
2267 cd->dc_tx_prod = cd->dc_tx_cons = cd->dc_tx_cnt = 0;
2274 * Initialize the RX descriptors and allocate mbufs for them. Note that
2275 * we arrange the descriptors in a closed ring, so that the last descriptor
2276 * points back to the first.
2279 dc_list_rx_init(struct dc_softc *sc)
2281 struct dc_chain_data *cd;
2282 struct dc_list_data *ld;
2288 for (i = 0; i < DC_RX_LIST_CNT; i++) {
2289 if (dc_newbuf(sc, i, NULL) == ENOBUFS)
2291 if (i == (DC_RX_LIST_CNT - 1)) {
2292 ld->dc_rx_list[i].dc_next =
2293 vtophys(&ld->dc_rx_list[0]);
2295 ld->dc_rx_list[i].dc_next =
2296 vtophys(&ld->dc_rx_list[i + 1]);
2306 * Initialize an RX descriptor and attach an MBUF cluster.
2309 dc_newbuf(struct dc_softc *sc, int i, struct mbuf *m)
2311 struct mbuf *m_new = NULL;
2314 c = &sc->dc_ldata->dc_rx_list[i];
2317 m_new = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR);
2320 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
2323 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
2324 m_new->m_data = m_new->m_ext.ext_buf;
2327 m_adj(m_new, sizeof(u_int64_t));
2330 * If this is a PNIC chip, zero the buffer. This is part
2331 * of the workaround for the receive bug in the 82c168 and
2334 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR)
2335 bzero((char *)mtod(m_new, char *), m_new->m_len);
2337 sc->dc_cdata.dc_rx_chain[i] = m_new;
2338 c->dc_data = vtophys(mtod(m_new, caddr_t));
2339 c->dc_ctl = DC_RXCTL_RLINK | DC_RXLEN;
2340 c->dc_status = DC_RXSTAT_OWN;
2347 * The PNIC chip has a terrible bug in it that manifests itself during
2348 * periods of heavy activity. The exact mode of failure if difficult to
2349 * pinpoint: sometimes it only happens in promiscuous mode, sometimes it
2350 * will happen on slow machines. The bug is that sometimes instead of
2351 * uploading one complete frame during reception, it uploads what looks
2352 * like the entire contents of its FIFO memory. The frame we want is at
2353 * the end of the whole mess, but we never know exactly how much data has
2354 * been uploaded, so salvaging the frame is hard.
2356 * There is only one way to do it reliably, and it's disgusting.
2357 * Here's what we know:
2359 * - We know there will always be somewhere between one and three extra
2360 * descriptors uploaded.
2362 * - We know the desired received frame will always be at the end of the
2363 * total data upload.
2365 * - We know the size of the desired received frame because it will be
2366 * provided in the length field of the status word in the last descriptor.
2368 * Here's what we do:
2370 * - When we allocate buffers for the receive ring, we bzero() them.
2371 * This means that we know that the buffer contents should be all
2372 * zeros, except for data uploaded by the chip.
2374 * - We also force the PNIC chip to upload frames that include the
2375 * ethernet CRC at the end.
2377 * - We gather all of the bogus frame data into a single buffer.
2379 * - We then position a pointer at the end of this buffer and scan
2380 * backwards until we encounter the first non-zero byte of data.
2381 * This is the end of the received frame. We know we will encounter
2382 * some data at the end of the frame because the CRC will always be
2383 * there, so even if the sender transmits a packet of all zeros,
2384 * we won't be fooled.
2386 * - We know the size of the actual received frame, so we subtract
2387 * that value from the current pointer location. This brings us
2388 * to the start of the actual received packet.
2390 * - We copy this into an mbuf and pass it on, along with the actual
2393 * The performance hit is tremendous, but it beats dropping frames all
2397 #define DC_WHOLEFRAME (DC_RXSTAT_FIRSTFRAG|DC_RXSTAT_LASTFRAG)
2399 dc_pnic_rx_bug_war(struct dc_softc *sc, int idx)
2401 struct dc_desc *cur_rx;
2402 struct dc_desc *c = NULL;
2403 struct mbuf *m = NULL;
2406 u_int32_t rxstat = 0;
2408 i = sc->dc_pnic_rx_bug_save;
2409 cur_rx = &sc->dc_ldata->dc_rx_list[idx];
2410 ptr = sc->dc_pnic_rx_buf;
2411 bzero(ptr, DC_RXLEN * 5);
2413 /* Copy all the bytes from the bogus buffers. */
2415 c = &sc->dc_ldata->dc_rx_list[i];
2416 rxstat = c->dc_status;
2417 m = sc->dc_cdata.dc_rx_chain[i];
2418 bcopy(mtod(m, char *), ptr, DC_RXLEN);
2420 /* If this is the last buffer, break out. */
2421 if (i == idx || rxstat & DC_RXSTAT_LASTFRAG)
2423 dc_newbuf(sc, i, m);
2424 DC_INC(i, DC_RX_LIST_CNT);
2427 /* Find the length of the actual receive frame. */
2428 total_len = DC_RXBYTES(rxstat);
2430 /* Scan backwards until we hit a non-zero byte. */
2435 if ((uintptr_t)(ptr) & 0x3)
2438 /* Now find the start of the frame. */
2440 if (ptr < sc->dc_pnic_rx_buf)
2441 ptr = sc->dc_pnic_rx_buf;
2444 * Now copy the salvaged frame to the last mbuf and fake up
2445 * the status word to make it look like a successful
2448 dc_newbuf(sc, i, m);
2449 bcopy(ptr, mtod(m, char *), total_len);
2450 cur_rx->dc_status = rxstat | DC_RXSTAT_FIRSTFRAG;
2456 * This routine searches the RX ring for dirty descriptors in the
2457 * event that the rxeof routine falls out of sync with the chip's
2458 * current descriptor pointer. This may happen sometimes as a result
2459 * of a "no RX buffer available" condition that happens when the chip
2460 * consumes all of the RX buffers before the driver has a chance to
2461 * process the RX ring. This routine may need to be called more than
2462 * once to bring the driver back in sync with the chip, however we
2463 * should still be getting RX DONE interrupts to drive the search
2464 * for new packets in the RX ring, so we should catch up eventually.
2467 dc_rx_resync(struct dc_softc *sc)
2470 struct dc_desc *cur_rx;
2472 pos = sc->dc_cdata.dc_rx_prod;
2474 for (i = 0; i < DC_RX_LIST_CNT; i++) {
2475 cur_rx = &sc->dc_ldata->dc_rx_list[pos];
2476 if (!(cur_rx->dc_status & DC_RXSTAT_OWN))
2478 DC_INC(pos, DC_RX_LIST_CNT);
2481 /* If the ring really is empty, then just return. */
2482 if (i == DC_RX_LIST_CNT)
2485 /* We've fallen behing the chip: catch it. */
2486 sc->dc_cdata.dc_rx_prod = pos;
2492 * A frame has been uploaded: pass the resulting mbuf chain up to
2493 * the higher level protocols.
2496 dc_rxeof(struct dc_softc *sc)
2500 struct dc_desc *cur_rx;
2501 int i, total_len = 0;
2504 ifp = &sc->arpcom.ac_if;
2505 i = sc->dc_cdata.dc_rx_prod;
2507 while(!(sc->dc_ldata->dc_rx_list[i].dc_status & DC_RXSTAT_OWN)) {
2509 #ifdef IFPOLL_ENABLE
2510 if (ifp->if_flags & IFF_NPOLLING) {
2511 if (sc->rxcycles <= 0)
2515 #endif /* IFPOLL_ENABLE */
2516 cur_rx = &sc->dc_ldata->dc_rx_list[i];
2517 rxstat = cur_rx->dc_status;
2518 m = sc->dc_cdata.dc_rx_chain[i];
2519 total_len = DC_RXBYTES(rxstat);
2521 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) {
2522 if ((rxstat & DC_WHOLEFRAME) != DC_WHOLEFRAME) {
2523 if (rxstat & DC_RXSTAT_FIRSTFRAG)
2524 sc->dc_pnic_rx_bug_save = i;
2525 if ((rxstat & DC_RXSTAT_LASTFRAG) == 0) {
2526 DC_INC(i, DC_RX_LIST_CNT);
2529 dc_pnic_rx_bug_war(sc, i);
2530 rxstat = cur_rx->dc_status;
2531 total_len = DC_RXBYTES(rxstat);
2535 sc->dc_cdata.dc_rx_chain[i] = NULL;
2538 * If an error occurs, update stats, clear the
2539 * status word and leave the mbuf cluster in place:
2540 * it should simply get re-used next time this descriptor
2541 * comes up in the ring. However, don't report long
2542 * frames as errors since they could be vlans
2544 if ((rxstat & DC_RXSTAT_RXERR)){
2545 if (!(rxstat & DC_RXSTAT_GIANT) ||
2546 (rxstat & (DC_RXSTAT_CRCERR | DC_RXSTAT_DRIBBLE |
2547 DC_RXSTAT_MIIERE | DC_RXSTAT_COLLSEEN |
2548 DC_RXSTAT_RUNT | DC_RXSTAT_DE))) {
2550 if (rxstat & DC_RXSTAT_COLLSEEN)
2551 ifp->if_collisions++;
2552 dc_newbuf(sc, i, m);
2553 if (rxstat & DC_RXSTAT_CRCERR) {
2554 DC_INC(i, DC_RX_LIST_CNT);
2563 /* No errors; receive the packet. */
2564 total_len -= ETHER_CRC_LEN;
2568 * On the x86 we do not have alignment problems, so try to
2569 * allocate a new buffer for the receive ring, and pass up
2570 * the one where the packet is already, saving the expensive
2571 * copy done in m_devget().
2572 * If we are on an architecture with alignment problems, or
2573 * if the allocation fails, then use m_devget and leave the
2574 * existing buffer in the receive ring.
2576 if (dc_quick && dc_newbuf(sc, i, NULL) == 0) {
2577 m->m_pkthdr.rcvif = ifp;
2578 m->m_pkthdr.len = m->m_len = total_len;
2579 DC_INC(i, DC_RX_LIST_CNT);
2585 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN,
2586 total_len + ETHER_ALIGN, 0, ifp, NULL);
2587 dc_newbuf(sc, i, m);
2588 DC_INC(i, DC_RX_LIST_CNT);
2593 m_adj(m0, ETHER_ALIGN);
2598 ifp->if_input(ifp, m);
2601 sc->dc_cdata.dc_rx_prod = i;
2605 * A frame was downloaded to the chip. It's safe for us to clean up
2610 dc_txeof(struct dc_softc *sc)
2612 struct dc_desc *cur_tx = NULL;
2616 ifp = &sc->arpcom.ac_if;
2619 * Go through our tx list and free mbufs for those
2620 * frames that have been transmitted.
2622 idx = sc->dc_cdata.dc_tx_cons;
2623 while(idx != sc->dc_cdata.dc_tx_prod) {
2626 cur_tx = &sc->dc_ldata->dc_tx_list[idx];
2627 txstat = cur_tx->dc_status;
2629 if (txstat & DC_TXSTAT_OWN)
2632 if (!(cur_tx->dc_ctl & DC_TXCTL_LASTFRAG) ||
2633 cur_tx->dc_ctl & DC_TXCTL_SETUP) {
2634 if (cur_tx->dc_ctl & DC_TXCTL_SETUP) {
2636 * Yes, the PNIC is so brain damaged
2637 * that it will sometimes generate a TX
2638 * underrun error while DMAing the RX
2639 * filter setup frame. If we detect this,
2640 * we have to send the setup frame again,
2641 * or else the filter won't be programmed
2644 if (DC_IS_PNIC(sc)) {
2645 if (txstat & DC_TXSTAT_ERRSUM)
2648 sc->dc_cdata.dc_tx_chain[idx] = NULL;
2650 sc->dc_cdata.dc_tx_cnt--;
2651 DC_INC(idx, DC_TX_LIST_CNT);
2655 if (DC_IS_XIRCOM(sc) || DC_IS_CONEXANT(sc)) {
2657 * XXX: Why does my Xircom taunt me so?
2658 * For some reason Conexant chips like
2659 * setting the CARRLOST flag even when
2660 * the carrier is there. In CURRENT we
2661 * have the same problem for Xircom
2664 if (/*sc->dc_type == DC_TYPE_21143 &&*/
2665 sc->dc_pmode == DC_PMODE_MII &&
2666 ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM|
2667 DC_TXSTAT_NOCARRIER)))
2668 txstat &= ~DC_TXSTAT_ERRSUM;
2670 if (/*sc->dc_type == DC_TYPE_21143 &&*/
2671 sc->dc_pmode == DC_PMODE_MII &&
2672 ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM|
2673 DC_TXSTAT_NOCARRIER|DC_TXSTAT_CARRLOST)))
2674 txstat &= ~DC_TXSTAT_ERRSUM;
2677 if (txstat & DC_TXSTAT_ERRSUM) {
2679 if (txstat & DC_TXSTAT_EXCESSCOLL)
2680 ifp->if_collisions++;
2681 if (txstat & DC_TXSTAT_LATECOLL)
2682 ifp->if_collisions++;
2683 if (!(txstat & DC_TXSTAT_UNDERRUN)) {
2689 ifp->if_collisions += (txstat & DC_TXSTAT_COLLCNT) >> 3;
2692 if (sc->dc_cdata.dc_tx_chain[idx] != NULL) {
2693 m_freem(sc->dc_cdata.dc_tx_chain[idx]);
2694 sc->dc_cdata.dc_tx_chain[idx] = NULL;
2697 sc->dc_cdata.dc_tx_cnt--;
2698 DC_INC(idx, DC_TX_LIST_CNT);
2701 if (idx != sc->dc_cdata.dc_tx_cons) {
2702 /* some buffers have been freed */
2703 sc->dc_cdata.dc_tx_cons = idx;
2704 ifp->if_flags &= ~IFF_OACTIVE;
2706 ifp->if_timer = (sc->dc_cdata.dc_tx_cnt == 0) ? 0 : 5;
2714 struct dc_softc *sc = xsc;
2715 struct ifnet *ifp = &sc->arpcom.ac_if;
2716 struct mii_data *mii;
2719 lwkt_serialize_enter(ifp->if_serializer);
2721 mii = device_get_softc(sc->dc_miibus);
2723 if (sc->dc_flags & DC_REDUCED_MII_POLL) {
2724 if (sc->dc_flags & DC_21143_NWAY) {
2725 r = CSR_READ_4(sc, DC_10BTSTAT);
2726 if (IFM_SUBTYPE(mii->mii_media_active) ==
2727 IFM_100_TX && (r & DC_TSTAT_LS100)) {
2731 if (IFM_SUBTYPE(mii->mii_media_active) ==
2732 IFM_10_T && (r & DC_TSTAT_LS10)) {
2736 if (sc->dc_link == 0)
2739 r = CSR_READ_4(sc, DC_ISR);
2740 if ((r & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT &&
2741 sc->dc_cdata.dc_tx_cnt == 0) {
2743 if (!(mii->mii_media_status & IFM_ACTIVE))
2752 * When the init routine completes, we expect to be able to send
2753 * packets right away, and in fact the network code will send a
2754 * gratuitous ARP the moment the init routine marks the interface
2755 * as running. However, even though the MAC may have been initialized,
2756 * there may be a delay of a few seconds before the PHY completes
2757 * autonegotiation and the link is brought up. Any transmissions
2758 * made during that delay will be lost. Dealing with this is tricky:
2759 * we can't just pause in the init routine while waiting for the
2760 * PHY to come ready since that would bring the whole system to
2761 * a screeching halt for several seconds.
2763 * What we do here is prevent the TX start routine from sending
2764 * any packets until a link has been established. After the
2765 * interface has been initialized, the tick routine will poll
2766 * the state of the PHY until the IFM_ACTIVE flag is set. Until
2767 * that time, packets will stay in the send queue, and once the
2768 * link comes up, they will be flushed out to the wire.
2772 if (mii->mii_media_status & IFM_ACTIVE &&
2773 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
2775 if (!ifq_is_empty(&ifp->if_snd))
2780 if (sc->dc_flags & DC_21143_NWAY && !sc->dc_link)
2781 callout_reset(&sc->dc_stat_timer, hz / 10, dc_tick, sc);
2783 callout_reset(&sc->dc_stat_timer, hz, dc_tick, sc);
2785 lwkt_serialize_exit(ifp->if_serializer);
2789 * A transmit underrun has occurred. Back off the transmit threshold,
2790 * or switch to store and forward mode if we have to.
2793 dc_tx_underrun(struct dc_softc *sc)
2798 if (DC_IS_DAVICOM(sc))
2801 if (DC_IS_INTEL(sc)) {
2803 * The real 21143 requires that the transmitter be idle
2804 * in order to change the transmit threshold or store
2805 * and forward state.
2807 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON);
2809 for (i = 0; i < DC_TIMEOUT; i++) {
2810 isr = CSR_READ_4(sc, DC_ISR);
2811 if (isr & DC_ISR_TX_IDLE)
2815 if (i == DC_TIMEOUT) {
2816 if_printf(&sc->arpcom.ac_if,
2817 "failed to force tx to idle state\n");
2822 if_printf(&sc->arpcom.ac_if, "TX underrun -- ");
2823 sc->dc_txthresh += DC_TXTHRESH_INC;
2824 if (sc->dc_txthresh > DC_TXTHRESH_MAX) {
2825 kprintf("using store and forward mode\n");
2826 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD);
2828 kprintf("increasing TX threshold\n");
2829 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_THRESH);
2830 DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh);
2833 if (DC_IS_INTEL(sc))
2834 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON);
2839 #ifdef IFPOLL_ENABLE
2842 dc_npoll_compat(struct ifnet *ifp, void *arg __unused, int count)
2844 struct dc_softc *sc = ifp->if_softc;
2846 ASSERT_SERIALIZED(ifp->if_serializer);
2848 sc->rxcycles = count;
2851 if (!ifq_is_empty(&ifp->if_snd))
2854 if (sc->dc_npoll.ifpc_stcount-- == 0) {
2857 sc->dc_npoll.ifpc_stcount = sc->dc_npoll.ifpc_stfrac;
2859 status = CSR_READ_4(sc, DC_ISR);
2860 status &= (DC_ISR_RX_WATDOGTIMEO|DC_ISR_RX_NOBUF|
2861 DC_ISR_TX_NOBUF|DC_ISR_TX_IDLE|DC_ISR_TX_UNDERRUN|
2865 /* ack what we have */
2866 CSR_WRITE_4(sc, DC_ISR, status);
2868 if (status & (DC_ISR_RX_WATDOGTIMEO|DC_ISR_RX_NOBUF) ) {
2869 u_int32_t r = CSR_READ_4(sc, DC_FRAMESDISCARDED);
2870 ifp->if_ierrors += (r & 0xffff) + ((r >> 17) & 0x7ff);
2872 if (dc_rx_resync(sc))
2875 /* restart transmit unit if necessary */
2876 if (status & DC_ISR_TX_IDLE && sc->dc_cdata.dc_tx_cnt)
2877 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF);
2879 if (status & DC_ISR_TX_UNDERRUN)
2882 if (status & DC_ISR_BUS_ERR) {
2883 if_printf(ifp, "dc_poll: bus error\n");
2891 dc_npoll(struct ifnet *ifp, struct ifpoll_info *info)
2893 struct dc_softc *sc = ifp->if_softc;
2895 ASSERT_SERIALIZED(ifp->if_serializer);
2898 int cpuid = sc->dc_npoll.ifpc_cpuid;
2900 info->ifpi_rx[cpuid].poll_func = dc_npoll_compat;
2901 info->ifpi_rx[cpuid].arg = NULL;
2902 info->ifpi_rx[cpuid].serializer = ifp->if_serializer;
2904 if (ifp->if_flags & IFF_RUNNING) {
2905 /* Disable interrupts */
2906 CSR_WRITE_4(sc, DC_IMR, 0x00000000);
2907 sc->dc_npoll.ifpc_stcount = 0;
2909 ifp->if_npoll_cpuid = cpuid;
2911 if (ifp->if_flags & IFF_RUNNING) {
2912 /* Re-enable interrupts. */
2913 CSR_WRITE_4(sc, DC_IMR, DC_INTRS);
2915 ifp->if_npoll_cpuid = -1;
2919 #endif /* IFPOLL_ENABLE */
2924 struct dc_softc *sc;
2930 if (sc->suspended) {
2934 ifp = &sc->arpcom.ac_if;
2936 if ( (CSR_READ_4(sc, DC_ISR) & DC_INTRS) == 0)
2939 /* Suppress unwanted interrupts */
2940 if ((ifp->if_flags & IFF_RUNNING) == 0) {
2941 if (CSR_READ_4(sc, DC_ISR) & DC_INTRS)
2946 /* Disable interrupts. */
2947 CSR_WRITE_4(sc, DC_IMR, 0x00000000);
2949 while(((status = CSR_READ_4(sc, DC_ISR)) & DC_INTRS) &&
2950 status != 0xFFFFFFFF) {
2952 CSR_WRITE_4(sc, DC_ISR, status);
2954 if (status & DC_ISR_RX_OK) {
2956 curpkts = ifp->if_ipackets;
2958 if (curpkts == ifp->if_ipackets) {
2959 while(dc_rx_resync(sc))
2964 if (status & (DC_ISR_TX_OK|DC_ISR_TX_NOBUF))
2967 if (status & DC_ISR_TX_IDLE) {
2969 if (sc->dc_cdata.dc_tx_cnt) {
2970 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON);
2971 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF);
2975 if (status & DC_ISR_TX_UNDERRUN)
2978 if ((status & DC_ISR_RX_WATDOGTIMEO)
2979 || (status & DC_ISR_RX_NOBUF)) {
2981 curpkts = ifp->if_ipackets;
2983 if (curpkts == ifp->if_ipackets) {
2984 while(dc_rx_resync(sc))
2989 if (status & DC_ISR_BUS_ERR) {
2995 /* Re-enable interrupts. */
2996 CSR_WRITE_4(sc, DC_IMR, DC_INTRS);
2998 if (!ifq_is_empty(&ifp->if_snd))
3003 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
3004 * pointers to the fragment pointers.
3007 dc_encap(struct dc_softc *sc, struct mbuf *m_head, u_int32_t *txidx)
3009 struct dc_desc *f = NULL;
3011 int frag, cur, cnt = 0;
3014 * Start packing the mbufs in this chain into
3015 * the fragment pointers. Stop when we run out
3016 * of fragments or hit the end of the mbuf chain.
3019 cur = frag = *txidx;
3021 for (m = m_head; m != NULL; m = m->m_next) {
3022 if (m->m_len != 0) {
3023 if (sc->dc_flags & DC_TX_ADMTEK_WAR) {
3024 if (*txidx != sc->dc_cdata.dc_tx_prod &&
3025 frag == (DC_TX_LIST_CNT - 1))
3028 if ((DC_TX_LIST_CNT -
3029 (sc->dc_cdata.dc_tx_cnt + cnt)) < 5)
3032 f = &sc->dc_ldata->dc_tx_list[frag];
3033 f->dc_ctl = DC_TXCTL_TLINK | m->m_len;
3036 f->dc_ctl |= DC_TXCTL_FIRSTFRAG;
3038 f->dc_status = DC_TXSTAT_OWN;
3039 f->dc_data = vtophys(mtod(m, vm_offset_t));
3041 DC_INC(frag, DC_TX_LIST_CNT);
3049 sc->dc_cdata.dc_tx_cnt += cnt;
3050 sc->dc_cdata.dc_tx_chain[cur] = m_head;
3051 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= DC_TXCTL_LASTFRAG;
3052 if (sc->dc_flags & DC_TX_INTR_FIRSTFRAG)
3053 sc->dc_ldata->dc_tx_list[*txidx].dc_ctl |= DC_TXCTL_FINT;
3054 if (sc->dc_flags & DC_TX_INTR_ALWAYS)
3055 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= DC_TXCTL_FINT;
3056 if (sc->dc_flags & DC_TX_USE_TX_INTR && sc->dc_cdata.dc_tx_cnt > 64)
3057 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= DC_TXCTL_FINT;
3058 sc->dc_ldata->dc_tx_list[*txidx].dc_status = DC_TXSTAT_OWN;
3065 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
3066 * to the mbuf data regions directly in the transmit lists. We also save a
3067 * copy of the pointers since the transmit list fragment pointers are
3068 * physical addresses.
3072 dc_start(struct ifnet *ifp)
3074 struct dc_softc *sc;
3075 struct mbuf *m_head, *m_defragged;
3076 int idx, need_trans;
3081 ifq_purge(&ifp->if_snd);
3085 if (ifp->if_flags & IFF_OACTIVE)
3088 idx = sc->dc_cdata.dc_tx_prod;
3091 while(sc->dc_cdata.dc_tx_chain[idx] == NULL) {
3093 m_head = ifq_dequeue(&ifp->if_snd, NULL);
3097 if ((sc->dc_flags & DC_TX_COALESCE) &&
3098 (m_head->m_next != NULL || (sc->dc_flags & DC_TX_ALIGN))) {
3100 * Check first if coalescing allows us to queue
3101 * the packet. We don't want to loose it if
3102 * the TX queue is full.
3104 if ((sc->dc_flags & DC_TX_ADMTEK_WAR) &&
3105 idx != sc->dc_cdata.dc_tx_prod &&
3106 idx == (DC_TX_LIST_CNT - 1)) {
3107 ifp->if_flags |= IFF_OACTIVE;
3108 ifq_prepend(&ifp->if_snd, m_head);
3111 if ((DC_TX_LIST_CNT - sc->dc_cdata.dc_tx_cnt) < 5) {
3112 ifp->if_flags |= IFF_OACTIVE;
3113 ifq_prepend(&ifp->if_snd, m_head);
3117 /* only coalesce if have >1 mbufs */
3118 m_defragged = m_defrag(m_head, MB_DONTWAIT);
3119 if (m_defragged == NULL) {
3120 ifp->if_flags |= IFF_OACTIVE;
3121 ifq_prepend(&ifp->if_snd, m_head);
3124 m_head = m_defragged;
3127 if (dc_encap(sc, m_head, &idx)) {
3130 * Throw away the original packet if the
3131 * defragged packet could not be encapsulated,
3132 * as well as the defragged packet.
3136 ifq_prepend(&ifp->if_snd, m_head);
3138 ifp->if_flags |= IFF_OACTIVE;
3145 * If there's a BPF listener, bounce a copy of this frame
3148 BPF_MTAP(ifp, m_head);
3150 if (sc->dc_flags & DC_TX_ONE) {
3151 ifp->if_flags |= IFF_OACTIVE;
3160 sc->dc_cdata.dc_tx_prod = idx;
3161 if (!(sc->dc_flags & DC_TX_POLL))
3162 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF);
3165 * Set a timeout in case the chip goes out to lunch.
3173 struct dc_softc *sc = xsc;
3174 struct ifnet *ifp = &sc->arpcom.ac_if;
3175 struct mii_data *mii;
3177 mii = device_get_softc(sc->dc_miibus);
3180 * Cancel pending I/O and free all RX/TX buffers.
3186 * Set cache alignment and burst length.
3188 if (DC_IS_ASIX(sc) || DC_IS_DAVICOM(sc))
3189 CSR_WRITE_4(sc, DC_BUSCTL, 0);
3191 CSR_WRITE_4(sc, DC_BUSCTL, DC_BUSCTL_MRME|DC_BUSCTL_MRLE);
3193 * Evenly share the bus between receive and transmit process.
3195 if (DC_IS_INTEL(sc))
3196 DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_ARBITRATION);
3197 if (DC_IS_DAVICOM(sc) || DC_IS_INTEL(sc)) {
3198 DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_USECA);
3200 DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_16LONG);
3202 if (sc->dc_flags & DC_TX_POLL)
3203 DC_SETBIT(sc, DC_BUSCTL, DC_TXPOLL_1);
3204 switch(sc->dc_cachesize) {
3206 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_32LONG);
3209 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_16LONG);
3212 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_8LONG);
3216 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_NONE);
3220 if (sc->dc_flags & DC_TX_STORENFWD)
3221 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD);
3223 if (sc->dc_txthresh > DC_TXTHRESH_MAX) {
3224 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD);
3226 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD);
3227 DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh);
3231 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_NO_RXCRC);
3232 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_BACKOFF);
3234 if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) {
3236 * The app notes for the 98713 and 98715A say that
3237 * in order to have the chips operate properly, a magic
3238 * number must be written to CSR16. Macronix does not
3239 * document the meaning of these bits so there's no way
3240 * to know exactly what they do. The 98713 has a magic
3241 * number all its own; the rest all use a different one.
3243 DC_CLRBIT(sc, DC_MX_MAGICPACKET, 0xFFFF0000);
3244 if (sc->dc_type == DC_TYPE_98713)
3245 DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98713);
3247 DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98715);
3250 if (DC_IS_XIRCOM(sc)) {
3252 * Setup General Purpose Port mode and data so the tulip
3253 * can talk to the MII.
3255 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_WRITE_EN | DC_SIAGP_INT1_EN |
3256 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT);
3258 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_INT1_EN |
3259 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT);
3263 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_THRESH);
3264 DC_SETBIT(sc, DC_NETCFG, DC_TXTHRESH_MIN);
3266 /* Init circular RX list. */
3267 if (dc_list_rx_init(sc) == ENOBUFS) {
3268 if_printf(ifp, "initialization failed: no "
3269 "memory for rx buffers\n");
3275 * Init tx descriptors.
3277 dc_list_tx_init(sc);
3280 * Load the address of the RX list.
3282 CSR_WRITE_4(sc, DC_RXADDR, vtophys(&sc->dc_ldata->dc_rx_list[0]));
3283 CSR_WRITE_4(sc, DC_TXADDR, vtophys(&sc->dc_ldata->dc_tx_list[0]));
3286 * Enable interrupts.
3288 #ifdef IFPOLL_ENABLE
3290 * ... but only if we are not polling, and make sure they are off in
3291 * the case of polling. Some cards (e.g. fxp) turn interrupts on
3294 if (ifp->if_flags & IFF_NPOLLING) {
3295 CSR_WRITE_4(sc, DC_IMR, 0x00000000);
3296 sc->dc_npoll.ifpc_stcount = 0;
3299 CSR_WRITE_4(sc, DC_IMR, DC_INTRS);
3300 CSR_WRITE_4(sc, DC_ISR, 0xFFFFFFFF);
3302 /* Enable transmitter. */
3303 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON);
3306 * If this is an Intel 21143 and we're not using the
3307 * MII port, program the LED control pins so we get
3308 * link and activity indications.
3310 if (sc->dc_flags & DC_TULIP_LEDS) {
3311 CSR_WRITE_4(sc, DC_WATCHDOG,
3312 DC_WDOG_CTLWREN|DC_WDOG_LINK|DC_WDOG_ACTIVITY);
3313 CSR_WRITE_4(sc, DC_WATCHDOG, 0);
3317 * Set IFF_RUNNING here to keep the assertion in dc_setfilt()
3320 ifp->if_flags |= IFF_RUNNING;
3321 ifp->if_flags &= ~IFF_OACTIVE;
3324 * Load the RX/multicast filter. We do this sort of late
3325 * because the filter programming scheme on the 21143 and
3326 * some clones requires DMAing a setup frame via the TX
3327 * engine, and we need the transmitter enabled for that.
3331 /* Enable receiver. */
3332 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ON);
3333 CSR_WRITE_4(sc, DC_RXSTART, 0xFFFFFFFF);
3336 dc_setcfg(sc, sc->dc_if_media);
3338 /* Don't start the ticker if this is a homePNA link. */
3339 if (IFM_SUBTYPE(mii->mii_media.ifm_media) == IFM_HPNA_1)
3342 if (sc->dc_flags & DC_21143_NWAY)
3343 callout_reset(&sc->dc_stat_timer, hz/10, dc_tick, sc);
3345 callout_reset(&sc->dc_stat_timer, hz, dc_tick, sc);
3350 * Set media options.
3353 dc_ifmedia_upd(struct ifnet *ifp)
3355 struct dc_softc *sc;
3356 struct mii_data *mii;
3357 struct ifmedia *ifm;
3360 mii = device_get_softc(sc->dc_miibus);
3362 ifm = &mii->mii_media;
3364 if (DC_IS_DAVICOM(sc) &&
3365 IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1)
3366 dc_setcfg(sc, ifm->ifm_media);
3374 * Report current media status.
3377 dc_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
3379 struct dc_softc *sc;
3380 struct mii_data *mii;
3381 struct ifmedia *ifm;
3384 mii = device_get_softc(sc->dc_miibus);
3386 ifm = &mii->mii_media;
3387 if (DC_IS_DAVICOM(sc)) {
3388 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) {
3389 ifmr->ifm_active = ifm->ifm_media;
3390 ifmr->ifm_status = 0;
3394 ifmr->ifm_active = mii->mii_media_active;
3395 ifmr->ifm_status = mii->mii_media_status;
3401 dc_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
3403 struct dc_softc *sc = ifp->if_softc;
3404 struct ifreq *ifr = (struct ifreq *) data;
3405 struct mii_data *mii;
3410 if (ifp->if_flags & IFF_UP) {
3411 int need_setfilt = (ifp->if_flags ^ sc->dc_if_flags) &
3412 (IFF_PROMISC | IFF_ALLMULTI);
3413 if (ifp->if_flags & IFF_RUNNING) {
3417 sc->dc_txthresh = 0;
3421 if (ifp->if_flags & IFF_RUNNING)
3424 sc->dc_if_flags = ifp->if_flags;
3428 if (ifp->if_flags & IFF_RUNNING)
3433 mii = device_get_softc(sc->dc_miibus);
3434 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
3437 error = ether_ioctl(ifp, command, data);
3445 dc_watchdog(struct ifnet *ifp)
3447 struct dc_softc *sc;
3452 if_printf(ifp, "watchdog timeout\n");
3458 if (!ifq_is_empty(&ifp->if_snd))
3463 * Stop the adapter and free any mbufs allocated to the
3467 dc_stop(struct dc_softc *sc)
3472 ifp = &sc->arpcom.ac_if;
3475 callout_stop(&sc->dc_stat_timer);
3477 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
3479 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_RX_ON|DC_NETCFG_TX_ON));
3480 CSR_WRITE_4(sc, DC_IMR, 0x00000000);
3481 CSR_WRITE_4(sc, DC_TXADDR, 0x00000000);
3482 CSR_WRITE_4(sc, DC_RXADDR, 0x00000000);
3486 * Free data in the RX lists.
3488 for (i = 0; i < DC_RX_LIST_CNT; i++) {
3489 if (sc->dc_cdata.dc_rx_chain[i] != NULL) {
3490 m_freem(sc->dc_cdata.dc_rx_chain[i]);
3491 sc->dc_cdata.dc_rx_chain[i] = NULL;
3494 bzero((char *)&sc->dc_ldata->dc_rx_list,
3495 sizeof(sc->dc_ldata->dc_rx_list));
3498 * Free the TX list buffers.
3500 for (i = 0; i < DC_TX_LIST_CNT; i++) {
3501 if (sc->dc_cdata.dc_tx_chain[i] != NULL) {
3502 if ((sc->dc_ldata->dc_tx_list[i].dc_ctl &
3504 !(sc->dc_ldata->dc_tx_list[i].dc_ctl &
3505 DC_TXCTL_LASTFRAG)) {
3506 sc->dc_cdata.dc_tx_chain[i] = NULL;
3509 m_freem(sc->dc_cdata.dc_tx_chain[i]);
3510 sc->dc_cdata.dc_tx_chain[i] = NULL;
3513 bzero((char *)&sc->dc_ldata->dc_tx_list,
3514 sizeof(sc->dc_ldata->dc_tx_list));
3518 * Stop all chip I/O so that the kernel's probe routines don't
3519 * get confused by errant DMAs when rebooting.
3522 dc_shutdown(device_t dev)
3524 struct dc_softc *sc;
3527 sc = device_get_softc(dev);
3528 ifp = &sc->arpcom.ac_if;
3529 lwkt_serialize_enter(ifp->if_serializer);
3533 lwkt_serialize_exit(ifp->if_serializer);
3537 * Device suspend routine. Stop the interface and save some PCI
3538 * settings in case the BIOS doesn't restore them properly on
3542 dc_suspend(device_t dev)
3544 struct dc_softc *sc = device_get_softc(dev);
3545 struct ifnet *ifp = &sc->arpcom.ac_if;
3547 lwkt_serialize_enter(ifp->if_serializer);
3550 for (i = 0; i < 5; i++)
3551 sc->saved_maps[i] = pci_read_config(dev, PCIR_MAPS + i * 4, 4);
3552 sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4);
3553 sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1);
3554 sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1);
3555 sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1);
3559 lwkt_serialize_exit(ifp->if_serializer);
3564 * Device resume routine. Restore some PCI settings in case the BIOS
3565 * doesn't, re-enable busmastering, and restart the interface if
3569 dc_resume(device_t dev)
3571 struct dc_softc *sc = device_get_softc(dev);
3572 struct ifnet *ifp = &sc->arpcom.ac_if;
3575 lwkt_serialize_enter(ifp->if_serializer);
3578 /* better way to do this? */
3579 for (i = 0; i < 5; i++)
3580 pci_write_config(dev, PCIR_MAPS + i * 4, sc->saved_maps[i], 4);
3581 pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4);
3582 pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1);
3583 pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1);
3584 pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1);
3586 /* reenable busmastering */
3587 pci_enable_busmaster(dev);
3588 pci_enable_io(dev, DC_RES);
3590 /* reinitialize interface if necessary */
3591 if (ifp->if_flags & IFF_UP)
3595 lwkt_serialize_exit(ifp->if_serializer);
3601 dc_mchash_xircom(struct dc_softc *sc, const uint8_t *addr)
3605 /* Compute CRC for the address value. */
3606 crc = ether_crc32_le(addr, ETHER_ADDR_LEN);
3608 if ((crc & 0x180) == 0x180)
3609 return ((crc & 0x0F) + (crc & 0x70) * 3 + (14 << 4));
3611 return ((crc & 0x1F) + ((crc >> 1) & 0xF0) * 3 + (12 << 4));
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