2 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting
3 * Copyright (c) 2002-2008 Atheros Communications, Inc.
5 * Permission to use, copy, modify, and/or distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 * $FreeBSD: head/sys/dev/ath/ath_hal/ar5416/ar5416_reset.c 203930 2010-02-15 17:49:49Z rpaulo $
22 #include "ah_internal.h"
25 #include "ah_eeprom_v14.h"
27 #include "ar5416/ar5416.h"
28 #include "ar5416/ar5416reg.h"
29 #include "ar5416/ar5416phy.h"
31 /* Eeprom versioning macros. Returns true if the version is equal or newer than the ver specified */
32 #define EEP_MINOR(_ah) \
33 (AH_PRIVATE(_ah)->ah_eeversion & AR5416_EEP_VER_MINOR_MASK)
34 #define IS_EEP_MINOR_V2(_ah) (EEP_MINOR(_ah) >= AR5416_EEP_MINOR_VER_2)
35 #define IS_EEP_MINOR_V3(_ah) (EEP_MINOR(_ah) >= AR5416_EEP_MINOR_VER_3)
37 /* Additional Time delay to wait after activiting the Base band */
38 #define BASE_ACTIVATE_DELAY 100 /* 100 usec */
39 #define PLL_SETTLE_DELAY 300 /* 300 usec */
40 #define RTC_PLL_SETTLE_DELAY 1000 /* 1 ms */
42 static void ar5416InitDMA(struct ath_hal *ah);
43 static void ar5416InitBB(struct ath_hal *ah, const struct ieee80211_channel *);
44 static void ar5416InitIMR(struct ath_hal *ah, HAL_OPMODE opmode);
45 static void ar5416InitQoS(struct ath_hal *ah);
46 static void ar5416InitUserSettings(struct ath_hal *ah);
49 static HAL_BOOL ar5416ChannelChange(struct ath_hal *, const struct ieee80211_channel *);
51 static void ar5416SetDeltaSlope(struct ath_hal *, const struct ieee80211_channel *);
53 static HAL_BOOL ar5416SetResetPowerOn(struct ath_hal *ah);
54 static HAL_BOOL ar5416SetReset(struct ath_hal *ah, int type);
55 static void ar5416InitPLL(struct ath_hal *ah, const struct ieee80211_channel *chan);
56 static HAL_BOOL ar5416SetPowerPerRateTable(struct ath_hal *ah,
57 struct ar5416eeprom *pEepData,
58 const struct ieee80211_channel *chan, int16_t *ratesArray,
59 uint16_t cfgCtl, uint16_t AntennaReduction,
60 uint16_t twiceMaxRegulatoryPower,
62 static HAL_BOOL ar5416SetPowerCalTable(struct ath_hal *ah,
63 struct ar5416eeprom *pEepData,
64 const struct ieee80211_channel *chan,
65 int16_t *pTxPowerIndexOffset);
66 static uint16_t ar5416GetMaxEdgePower(uint16_t freq,
67 CAL_CTL_EDGES *pRdEdgesPower, HAL_BOOL is2GHz);
69 static int16_t interpolate(uint16_t target, uint16_t srcLeft,
70 uint16_t srcRight, int16_t targetLeft, int16_t targetRight);
71 static void ar5416Set11nRegs(struct ath_hal *ah, const struct ieee80211_channel *chan);
72 static void ar5416GetGainBoundariesAndPdadcs(struct ath_hal *ah,
73 const struct ieee80211_channel *chan, CAL_DATA_PER_FREQ *pRawDataSet,
74 uint8_t * bChans, uint16_t availPiers,
75 uint16_t tPdGainOverlap, int16_t *pMinCalPower,
76 uint16_t * pPdGainBoundaries, uint8_t * pPDADCValues,
77 uint16_t numXpdGains);
78 static HAL_BOOL getLowerUpperIndex(uint8_t target, uint8_t *pList,
79 uint16_t listSize, uint16_t *indexL, uint16_t *indexR);
80 static HAL_BOOL ar5416FillVpdTable(uint8_t pwrMin, uint8_t pwrMax,
81 uint8_t *pPwrList, uint8_t *pVpdList,
82 uint16_t numIntercepts, uint8_t *pRetVpdList);
85 * Places the device in and out of reset and then places sane
86 * values in the registers based on EEPROM config, initialization
87 * vectors (as determined by the mode), and station configuration
89 * bChannelChange is used to preserve DMA/PCU registers across
90 * a HW Reset during channel change.
93 ar5416Reset(struct ath_hal *ah, HAL_OPMODE opmode,
94 struct ieee80211_channel *chan,
95 HAL_BOOL bChannelChange, HAL_STATUS *status)
97 #define FAIL(_code) do { ecode = _code; goto bad; } while (0)
98 struct ath_hal_5212 *ahp = AH5212(ah);
99 HAL_CHANNEL_INTERNAL *ichan;
100 uint32_t saveDefAntenna, saveLedState;
102 uint16_t rfXpdGain[2];
104 uint32_t powerVal, rssiThrReg;
105 uint32_t ackTpcPow, ctsTpcPow, chirpTpcPow;
108 OS_MARK(ah, AH_MARK_RESET, bChannelChange);
110 /* Bring out of sleep mode */
111 if (!ar5416SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE)) {
112 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: chip did not wakeup\n",
118 * Map public channel to private.
120 ichan = ath_hal_checkchannel(ah, chan);
121 if (ichan == AH_NULL)
130 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid operating mode %u\n",
135 HALASSERT(AH_PRIVATE(ah)->ah_eeversion >= AR_EEPROM_VER14_1);
137 /* XXX Turn on fast channel change for 5416 */
139 * Preserve the bmiss rssi threshold and count threshold
142 rssiThrReg = OS_REG_READ(ah, AR_RSSI_THR);
143 /* If reg is zero, first time thru set to default val */
145 rssiThrReg = INIT_RSSI_THR;
148 * Preserve the antenna on a channel change
150 saveDefAntenna = OS_REG_READ(ah, AR_DEF_ANTENNA);
151 if (saveDefAntenna == 0) /* XXX magic constants */
154 /* Save hardware flag before chip reset clears the register */
155 macStaId1 = OS_REG_READ(ah, AR_STA_ID1) &
156 (AR_STA_ID1_BASE_RATE_11B | AR_STA_ID1_USE_DEFANT);
158 /* Save led state from pci config register */
159 saveLedState = OS_REG_READ(ah, AR_MAC_LED) &
160 (AR_MAC_LED_ASSOC | AR_MAC_LED_MODE |
161 AR_MAC_LED_BLINK_THRESH_SEL | AR_MAC_LED_BLINK_SLOW);
163 if (!ar5416ChipReset(ah, chan)) {
164 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: chip reset failed\n", __func__);
168 /* Restore bmiss rssi & count thresholds */
169 OS_REG_WRITE(ah, AR_RSSI_THR, rssiThrReg);
171 OS_MARK(ah, AH_MARK_RESET_LINE, __LINE__);
172 if (AR_SREV_MERLIN_10_OR_LATER(ah))
173 OS_REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE);
175 if (AR_SREV_KITE(ah)) {
177 val = OS_REG_READ(ah, AR_PHY_HEAVY_CLIP_FACTOR_RIFS);
178 val &= ~AR_PHY_RIFS_INIT_DELAY;
179 OS_REG_WRITE(ah, AR_PHY_HEAVY_CLIP_FACTOR_RIFS, val);
182 AH5416(ah)->ah_writeIni(ah, chan);
184 /* Setup 11n MAC/Phy mode registers */
185 ar5416Set11nRegs(ah, chan);
187 OS_MARK(ah, AH_MARK_RESET_LINE, __LINE__);
189 HALDEBUG(ah, HAL_DEBUG_RESET, ">>>2 %s: AR_PHY_DAG_CTRLCCK=0x%x\n",
190 __func__, OS_REG_READ(ah,AR_PHY_DAG_CTRLCCK));
191 HALDEBUG(ah, HAL_DEBUG_RESET, ">>>2 %s: AR_PHY_ADC_CTL=0x%x\n",
192 __func__, OS_REG_READ(ah,AR_PHY_ADC_CTL));
194 /* Set the mute mask to the correct default */
195 if (AH_PRIVATE(ah)->ah_phyRev >= AR_PHY_CHIP_ID_REV_2)
196 OS_REG_WRITE(ah, AR_SEQ_MASK, 0x0000000F);
198 if (AH_PRIVATE(ah)->ah_phyRev >= AR_PHY_CHIP_ID_REV_3) {
199 /* Clear reg to alllow RX_CLEAR line debug */
200 OS_REG_WRITE(ah, AR_PHY_BLUETOOTH, 0);
202 if (AH_PRIVATE(ah)->ah_phyRev >= AR_PHY_CHIP_ID_REV_4) {
204 /* Enable burst prefetch for the data queues */
205 OS_REG_RMW_FIELD(ah, AR_D_FPCTL, ... );
206 /* Enable double-buffering */
207 OS_REG_CLR_BIT(ah, AR_TXCFG, AR_TXCFG_DBL_BUF_DIS);
211 /* Set ADC/DAC select values */
212 OS_REG_WRITE(ah, AR_PHY_SLEEP_SCAL, 0x0e);
214 if (AH5416(ah)->ah_rx_chainmask == 0x5 ||
215 AH5416(ah)->ah_tx_chainmask == 0x5)
216 OS_REG_WRITE(ah, AR_PHY_ANALOG_SWAP, AR_PHY_SWAP_ALT_CHAIN);
217 /* Setup Chain Masks */
218 OS_REG_WRITE(ah, AR_PHY_RX_CHAINMASK, AH5416(ah)->ah_rx_chainmask);
219 OS_REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, AH5416(ah)->ah_rx_chainmask);
220 OS_REG_WRITE(ah, AR_SELFGEN_MASK, AH5416(ah)->ah_tx_chainmask);
222 /* Setup the transmit power values. */
223 if (!ah->ah_setTxPower(ah, chan, rfXpdGain)) {
224 HALDEBUG(ah, HAL_DEBUG_ANY,
225 "%s: error init'ing transmit power\n", __func__);
229 /* Write the analog registers */
230 if (!ahp->ah_rfHal->setRfRegs(ah, chan,
231 IEEE80211_IS_CHAN_2GHZ(chan) ? 2: 1, rfXpdGain)) {
232 HALDEBUG(ah, HAL_DEBUG_ANY,
233 "%s: ar5212SetRfRegs failed\n", __func__);
237 /* Write delta slope for OFDM enabled modes (A, G, Turbo) */
238 if (IEEE80211_IS_CHAN_OFDM(chan)|| IEEE80211_IS_CHAN_HT(chan))
239 ar5416SetDeltaSlope(ah, chan);
241 AH5416(ah)->ah_spurMitigate(ah, chan);
243 /* Setup board specific options for EEPROM version 3 */
244 if (!ah->ah_setBoardValues(ah, chan)) {
245 HALDEBUG(ah, HAL_DEBUG_ANY,
246 "%s: error setting board options\n", __func__);
250 OS_MARK(ah, AH_MARK_RESET_LINE, __LINE__);
252 OS_REG_WRITE(ah, AR_STA_ID0, LE_READ_4(ahp->ah_macaddr));
253 OS_REG_WRITE(ah, AR_STA_ID1, LE_READ_2(ahp->ah_macaddr + 4)
255 | AR_STA_ID1_RTS_USE_DEF
256 | ahp->ah_staId1Defaults
258 ar5212SetOperatingMode(ah, opmode);
260 /* Set Venice BSSID mask according to current state */
261 OS_REG_WRITE(ah, AR_BSSMSKL, LE_READ_4(ahp->ah_bssidmask));
262 OS_REG_WRITE(ah, AR_BSSMSKU, LE_READ_2(ahp->ah_bssidmask + 4));
264 /* Restore previous led state */
265 OS_REG_WRITE(ah, AR_MAC_LED, OS_REG_READ(ah, AR_MAC_LED) | saveLedState);
267 /* Restore previous antenna */
268 OS_REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
271 OS_REG_WRITE(ah, AR_BSS_ID0, LE_READ_4(ahp->ah_bssid));
272 OS_REG_WRITE(ah, AR_BSS_ID1, LE_READ_2(ahp->ah_bssid + 4));
274 /* Restore bmiss rssi & count thresholds */
275 OS_REG_WRITE(ah, AR_RSSI_THR, ahp->ah_rssiThr);
277 OS_REG_WRITE(ah, AR_ISR, ~0); /* cleared on write */
279 if (!ar5212SetChannel(ah, chan))
282 OS_MARK(ah, AH_MARK_RESET_LINE, __LINE__);
284 /* Set 1:1 QCU to DCU mapping for all queues */
285 for (i = 0; i < AR_NUM_DCU; i++)
286 OS_REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
288 ahp->ah_intrTxqs = 0;
289 for (i = 0; i < AH_PRIVATE(ah)->ah_caps.halTotalQueues; i++)
290 ar5212ResetTxQueue(ah, i);
292 ar5416InitIMR(ah, opmode);
293 ar5212SetCoverageClass(ah, AH_PRIVATE(ah)->ah_coverageClass, 1);
295 ar5416InitUserSettings(ah);
298 * disable seq number generation in hw
300 OS_REG_WRITE(ah, AR_STA_ID1,
301 OS_REG_READ(ah, AR_STA_ID1) | AR_STA_ID1_PRESERVE_SEQNUM);
306 * program OBS bus to see MAC interrupts
308 OS_REG_WRITE(ah, AR_OBS, 8);
310 #ifdef AR5416_INT_MITIGATION
311 OS_REG_WRITE(ah, AR_MIRT, 0);
312 OS_REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500);
313 OS_REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000);
316 ar5416InitBB(ah, chan);
318 /* Setup compression registers */
319 ar5212SetCompRegs(ah); /* XXX not needed? */
322 * 5416 baseband will check the per rate power table
323 * and select the lower of the two
328 powerVal = SM(ackTpcPow, AR_TPC_ACK) |
329 SM(ctsTpcPow, AR_TPC_CTS) |
330 SM(chirpTpcPow, AR_TPC_CHIRP);
331 OS_REG_WRITE(ah, AR_TPC, powerVal);
333 if (!ar5416InitCal(ah, chan))
336 AH_PRIVATE(ah)->ah_opmode = opmode; /* record operating mode */
338 if (bChannelChange && !IEEE80211_IS_CHAN_DFS(chan))
339 chan->ic_state &= ~IEEE80211_CHANSTATE_CWINT;
341 HALDEBUG(ah, HAL_DEBUG_RESET, "%s: done\n", __func__);
343 OS_MARK(ah, AH_MARK_RESET_DONE, 0);
347 OS_MARK(ah, AH_MARK_RESET_DONE, ecode);
348 if (status != AH_NULL)
356 * This channel change evaluates whether the selected hardware can
357 * perform a synthesizer-only channel change (no reset). If the
358 * TX is not stopped, or the RFBus cannot be granted in the given
359 * time, the function returns false as a reset is necessary
362 ar5416ChannelChange(struct ath_hal *ah, const structu ieee80211_channel *chan)
365 uint32_t data, synthDelay, qnum;
366 uint16_t rfXpdGain[4];
367 struct ath_hal_5212 *ahp = AH5212(ah);
368 HAL_CHANNEL_INTERNAL *ichan;
371 * Map public channel to private.
373 ichan = ath_hal_checkchannel(ah, chan);
375 /* TX must be stopped or RF Bus grant will not work */
376 for (qnum = 0; qnum < AH_PRIVATE(ah)->ah_caps.halTotalQueues; qnum++) {
377 if (ar5212NumTxPending(ah, qnum)) {
378 HALDEBUG(ah, HAL_DEBUG_ANY,
379 "%s: frames pending on queue %d\n", __func__, qnum);
385 * Kill last Baseband Rx Frame - Request analog bus grant
387 OS_REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_REQUEST);
388 if (!ath_hal_wait(ah, AR_PHY_RFBUS_GNT, AR_PHY_RFBUS_GRANT_EN, AR_PHY_RFBUS_GRANT_EN)) {
389 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: could not kill baseband rx\n",
394 ar5416Set11nRegs(ah, chan); /* NB: setup 5416-specific regs */
396 /* Change the synth */
397 if (!ar5212SetChannel(ah, chan))
400 /* Setup the transmit power values. */
401 if (!ar5416SetTransmitPower(ah, chan, rfXpdGain)) {
402 HALDEBUG(ah, HAL_DEBUG_ANY,
403 "%s: error init'ing transmit power\n", __func__);
408 * Wait for the frequency synth to settle (synth goes on
409 * via PHY_ACTIVE_EN). Read the phy active delay register.
410 * Value is in 100ns increments.
412 data = OS_REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
413 if (IS_CHAN_CCK(ichan)) {
414 synthDelay = (4 * data) / 22;
416 synthDelay = data / 10;
419 OS_DELAY(synthDelay + BASE_ACTIVATE_DELAY);
421 /* Release the RFBus Grant */
422 OS_REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0);
424 /* Write delta slope for OFDM enabled modes (A, G, Turbo) */
425 if (IEEE80211_IS_CHAN_OFDM(ichan)|| IEEE80211_IS_CHAN_HT(chan)) {
426 HALASSERT(AH_PRIVATE(ah)->ah_eeversion >= AR_EEPROM_VER5_3);
427 ar5212SetSpurMitigation(ah, chan);
428 ar5416SetDeltaSlope(ah, chan);
431 /* XXX spur mitigation for Melin */
433 if (!IEEE80211_IS_CHAN_DFS(chan))
434 chan->ic_state &= ~IEEE80211_CHANSTATE_CWINT;
436 ichan->channel_time = 0;
437 ichan->tsf_last = ar5212GetTsf64(ah);
438 ar5212TxEnable(ah, AH_TRUE);
444 ar5416InitDMA(struct ath_hal *ah)
446 struct ath_hal_5212 *ahp = AH5212(ah);
449 * set AHB_MODE not to do cacheline prefetches
451 OS_REG_SET_BIT(ah, AR_AHB_MODE, AR_AHB_PREFETCH_RD_EN);
454 * let mac dma reads be in 128 byte chunks
456 OS_REG_WRITE(ah, AR_TXCFG,
457 (OS_REG_READ(ah, AR_TXCFG) & ~AR_TXCFG_DMASZ_MASK) | AR_TXCFG_DMASZ_128B);
460 * let mac dma writes be in 128 byte chunks
462 OS_REG_WRITE(ah, AR_RXCFG,
463 (OS_REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_DMASZ_MASK) | AR_RXCFG_DMASZ_128B);
465 /* restore TX trigger level */
466 OS_REG_WRITE(ah, AR_TXCFG,
467 (OS_REG_READ(ah, AR_TXCFG) &~ AR_FTRIG) |
468 SM(ahp->ah_txTrigLev, AR_FTRIG));
471 * Setup receive FIFO threshold to hold off TX activities
473 OS_REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);
476 * reduce the number of usable entries in PCU TXBUF to avoid
479 OS_REG_WRITE(ah, AR_PCU_TXBUF_CTRL, AR_PCU_TXBUF_CTRL_USABLE_SIZE);
483 ar5416InitBB(struct ath_hal *ah, const struct ieee80211_channel *chan)
488 * Wait for the frequency synth to settle (synth goes on
489 * via AR_PHY_ACTIVE_EN). Read the phy active delay register.
490 * Value is in 100ns increments.
492 synthDelay = OS_REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
493 if (IEEE80211_IS_CHAN_CCK(chan)) {
494 synthDelay = (4 * synthDelay) / 22;
499 /* Turn on PLL on 5416 */
500 HALDEBUG(ah, HAL_DEBUG_RESET, "%s %s channel\n",
501 __func__, IEEE80211_IS_CHAN_5GHZ(chan) ? "5GHz" : "2GHz");
502 ar5416InitPLL(ah, chan);
504 /* Activate the PHY (includes baseband activate and synthesizer on) */
505 OS_REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
508 * If the AP starts the calibration before the base band timeout
509 * completes we could get rx_clear false triggering. Add an
510 * extra BASE_ACTIVATE_DELAY usecs to ensure this condition
513 if (IEEE80211_IS_CHAN_HALF(chan)) {
514 OS_DELAY((synthDelay << 1) + BASE_ACTIVATE_DELAY);
515 } else if (IEEE80211_IS_CHAN_QUARTER(chan)) {
516 OS_DELAY((synthDelay << 2) + BASE_ACTIVATE_DELAY);
518 OS_DELAY(synthDelay + BASE_ACTIVATE_DELAY);
523 ar5416InitIMR(struct ath_hal *ah, HAL_OPMODE opmode)
525 struct ath_hal_5212 *ahp = AH5212(ah);
528 * Setup interrupt handling. Note that ar5212ResetTxQueue
529 * manipulates the secondary IMR's as queues are enabled
530 * and disabled. This is done with RMW ops to insure the
531 * settings we make here are preserved.
533 ahp->ah_maskReg = AR_IMR_TXERR | AR_IMR_TXURN
534 | AR_IMR_RXERR | AR_IMR_RXORN
537 #ifdef AR5416_INT_MITIGATION
538 ahp->ah_maskReg |= AR_IMR_TXINTM | AR_IMR_RXINTM
539 | AR_IMR_TXMINTR | AR_IMR_RXMINTR;
541 ahp->ah_maskReg |= AR_IMR_TXOK | AR_IMR_RXOK;
543 if (opmode == HAL_M_HOSTAP)
544 ahp->ah_maskReg |= AR_IMR_MIB;
545 OS_REG_WRITE(ah, AR_IMR, ahp->ah_maskReg);
546 /* Enable bus errors that are OR'd to set the HIUERR bit */
548 OS_REG_WRITE(ah, AR_IMR_S2,
549 OS_REG_READ(ah, AR_IMR_S2) | AR_IMR_S2_GTT | AR_IMR_S2_CST);
554 ar5416InitQoS(struct ath_hal *ah)
557 OS_REG_WRITE(ah, AR_QOS_CONTROL, 0x100aa); /* XXX magic */
558 OS_REG_WRITE(ah, AR_QOS_SELECT, 0x3210); /* XXX magic */
560 /* Turn on NOACK Support for QoS packets */
561 OS_REG_WRITE(ah, AR_NOACK,
562 SM(2, AR_NOACK_2BIT_VALUE) |
563 SM(5, AR_NOACK_BIT_OFFSET) |
564 SM(0, AR_NOACK_BYTE_OFFSET));
567 * initialize TXOP for all TIDs
569 OS_REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL);
570 OS_REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF);
571 OS_REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF);
572 OS_REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF);
573 OS_REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
577 ar5416InitUserSettings(struct ath_hal *ah)
579 struct ath_hal_5212 *ahp = AH5212(ah);
581 /* Restore user-specified settings */
582 if (ahp->ah_miscMode != 0)
583 OS_REG_WRITE(ah, AR_MISC_MODE, ahp->ah_miscMode);
584 if (ahp->ah_sifstime != (u_int) -1)
585 ar5212SetSifsTime(ah, ahp->ah_sifstime);
586 if (ahp->ah_slottime != (u_int) -1)
587 ar5212SetSlotTime(ah, ahp->ah_slottime);
588 if (ahp->ah_acktimeout != (u_int) -1)
589 ar5212SetAckTimeout(ah, ahp->ah_acktimeout);
590 if (ahp->ah_ctstimeout != (u_int) -1)
591 ar5212SetCTSTimeout(ah, ahp->ah_ctstimeout);
592 if (AH_PRIVATE(ah)->ah_diagreg != 0)
593 OS_REG_WRITE(ah, AR_DIAG_SW, AH_PRIVATE(ah)->ah_diagreg);
595 if (ahp->ah_globaltxtimeout != (u_int) -1)
596 ar5416SetGlobalTxTimeout(ah, ahp->ah_globaltxtimeout);
601 * Places the hardware into reset and then pulls it out of reset
604 ar5416ChipReset(struct ath_hal *ah, const struct ieee80211_channel *chan)
606 OS_MARK(ah, AH_MARK_CHIPRESET, chan ? chan->ic_freq : 0);
608 * Warm reset is optimistic.
610 if (AR_SREV_MERLIN_20_OR_LATER(ah) &&
611 ath_hal_eepromGetFlag(ah, AR_EEP_OL_PWRCTRL)) {
612 if (!ar5416SetResetReg(ah, HAL_RESET_POWER_ON))
615 if (!ar5416SetResetReg(ah, HAL_RESET_WARM))
619 /* Bring out of sleep mode (AGAIN) */
620 if (!ar5416SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE))
623 ar5416InitPLL(ah, chan);
626 * Perform warm reset before the mode/PLL/turbo registers
627 * are changed in order to deactivate the radio. Mode changes
628 * with an active radio can result in corrupted shifts to the
631 if (chan != AH_NULL) {
634 /* treat channel B as channel G , no B mode suport in owl */
635 rfMode = IEEE80211_IS_CHAN_CCK(chan) ?
636 AR_PHY_MODE_DYNAMIC : AR_PHY_MODE_OFDM;
637 if (AR_SREV_MERLIN_20(ah) && IS_5GHZ_FAST_CLOCK_EN(ah, chan)) {
638 /* phy mode bits for 5GHz channels require Fast Clock */
639 rfMode |= AR_PHY_MODE_DYNAMIC
640 | AR_PHY_MODE_DYN_CCK_DISABLE;
641 } else if (!AR_SREV_MERLIN_10_OR_LATER(ah)) {
642 rfMode |= IEEE80211_IS_CHAN_5GHZ(chan) ?
643 AR_PHY_MODE_RF5GHZ : AR_PHY_MODE_RF2GHZ;
645 OS_REG_WRITE(ah, AR_PHY_MODE, rfMode);
651 * Delta slope coefficient computation.
652 * Required for OFDM operation.
655 ar5416GetDeltaSlopeValues(struct ath_hal *ah, uint32_t coef_scaled,
656 uint32_t *coef_mantissa, uint32_t *coef_exponent)
658 #define COEF_SCALE_S 24
659 uint32_t coef_exp, coef_man;
661 * ALGO -> coef_exp = 14-floor(log2(coef));
662 * floor(log2(x)) is the highest set bit position
664 for (coef_exp = 31; coef_exp > 0; coef_exp--)
665 if ((coef_scaled >> coef_exp) & 0x1)
667 /* A coef_exp of 0 is a legal bit position but an unexpected coef_exp */
669 coef_exp = 14 - (coef_exp - COEF_SCALE_S);
672 * ALGO -> coef_man = floor(coef* 2^coef_exp+0.5);
673 * The coefficient is already shifted up for scaling
675 coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1));
677 *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp);
678 *coef_exponent = coef_exp - 16;
684 ar5416SetDeltaSlope(struct ath_hal *ah, const struct ieee80211_channel *chan)
686 #define INIT_CLOCKMHZSCALED 0x64000000
687 uint32_t coef_scaled, ds_coef_exp, ds_coef_man;
688 uint32_t clockMhzScaled;
690 CHAN_CENTERS centers;
692 /* half and quarter rate can divide the scaled clock by 2 or 4 respectively */
693 /* scale for selected channel bandwidth */
694 clockMhzScaled = INIT_CLOCKMHZSCALED;
695 if (IEEE80211_IS_CHAN_TURBO(chan))
696 clockMhzScaled <<= 1;
697 else if (IEEE80211_IS_CHAN_HALF(chan))
698 clockMhzScaled >>= 1;
699 else if (IEEE80211_IS_CHAN_QUARTER(chan))
700 clockMhzScaled >>= 2;
703 * ALGO -> coef = 1e8/fcarrier*fclock/40;
704 * scaled coef to provide precision for this floating calculation
706 ar5416GetChannelCenters(ah, chan, ¢ers);
707 coef_scaled = clockMhzScaled / centers.synth_center;
709 ar5416GetDeltaSlopeValues(ah, coef_scaled, &ds_coef_man, &ds_coef_exp);
711 OS_REG_RMW_FIELD(ah, AR_PHY_TIMING3,
712 AR_PHY_TIMING3_DSC_MAN, ds_coef_man);
713 OS_REG_RMW_FIELD(ah, AR_PHY_TIMING3,
714 AR_PHY_TIMING3_DSC_EXP, ds_coef_exp);
718 * scaled coeff is 9/10 that of normal coeff
720 coef_scaled = (9 * coef_scaled)/10;
722 ar5416GetDeltaSlopeValues(ah, coef_scaled, &ds_coef_man, &ds_coef_exp);
725 OS_REG_RMW_FIELD(ah, AR_PHY_HALFGI,
726 AR_PHY_HALFGI_DSC_MAN, ds_coef_man);
727 OS_REG_RMW_FIELD(ah, AR_PHY_HALFGI,
728 AR_PHY_HALFGI_DSC_EXP, ds_coef_exp);
729 #undef INIT_CLOCKMHZSCALED
733 * Set a limit on the overall output power. Used for dynamic
734 * transmit power control and the like.
736 * NB: limit is in units of 0.5 dbM.
739 ar5416SetTxPowerLimit(struct ath_hal *ah, uint32_t limit)
741 uint16_t dummyXpdGains[2];
743 AH_PRIVATE(ah)->ah_powerLimit = AH_MIN(limit, MAX_RATE_POWER);
744 return ar5416SetTransmitPower(ah, AH_PRIVATE(ah)->ah_curchan,
749 ar5416GetChipPowerLimits(struct ath_hal *ah,
750 struct ieee80211_channel *chan)
752 struct ath_hal_5212 *ahp = AH5212(ah);
753 int16_t minPower, maxPower;
756 * Get Pier table max and min powers.
758 if (ahp->ah_rfHal->getChannelMaxMinPower(ah, chan, &maxPower, &minPower)) {
759 /* NB: rf code returns 1/4 dBm units, convert */
760 chan->ic_maxpower = maxPower / 2;
761 chan->ic_minpower = minPower / 2;
763 HALDEBUG(ah, HAL_DEBUG_ANY,
764 "%s: no min/max power for %u/0x%x\n",
765 __func__, chan->ic_freq, chan->ic_flags);
766 chan->ic_maxpower = AR5416_MAX_RATE_POWER;
767 chan->ic_minpower = 0;
769 HALDEBUG(ah, HAL_DEBUG_RESET,
770 "Chan %d: MaxPow = %d MinPow = %d\n",
771 chan->ic_freq, chan->ic_maxpower, chan->ic_minpower);
775 /* XXX gag, this is sick */
776 typedef enum Ar5416_Rates {
777 rate6mb, rate9mb, rate12mb, rate18mb,
778 rate24mb, rate36mb, rate48mb, rate54mb,
779 rate1l, rate2l, rate2s, rate5_5l,
780 rate5_5s, rate11l, rate11s, rateXr,
781 rateHt20_0, rateHt20_1, rateHt20_2, rateHt20_3,
782 rateHt20_4, rateHt20_5, rateHt20_6, rateHt20_7,
783 rateHt40_0, rateHt40_1, rateHt40_2, rateHt40_3,
784 rateHt40_4, rateHt40_5, rateHt40_6, rateHt40_7,
785 rateDupCck, rateDupOfdm, rateExtCck, rateExtOfdm,
789 /**************************************************************
790 * ar5416SetTransmitPower
792 * Set the transmit power in the baseband for the given
793 * operating channel and mode.
796 ar5416SetTransmitPower(struct ath_hal *ah,
797 const struct ieee80211_channel *chan, uint16_t *rfXpdGain)
799 #define POW_SM(_r, _s) (((_r) & 0x3f) << (_s))
801 MODAL_EEP_HEADER *pModal;
802 struct ath_hal_5212 *ahp = AH5212(ah);
803 int16_t ratesArray[Ar5416RateSize];
804 int16_t txPowerIndexOffset = 0;
805 uint8_t ht40PowerIncForPdadc = 2;
810 uint16_t twiceAntennaReduction;
811 uint16_t twiceMaxRegulatoryPower;
813 HAL_EEPROM_v14 *ee = AH_PRIVATE(ah)->ah_eeprom;
814 struct ar5416eeprom *pEepData = &ee->ee_base;
816 HALASSERT(AH_PRIVATE(ah)->ah_eeversion >= AR_EEPROM_VER14_1);
818 /* Setup info for the actual eeprom */
819 OS_MEMZERO(ratesArray, sizeof(ratesArray));
820 cfgCtl = ath_hal_getctl(ah, chan);
821 powerLimit = chan->ic_maxregpower * 2;
822 twiceAntennaReduction = chan->ic_maxantgain;
823 twiceMaxRegulatoryPower = AH_MIN(MAX_RATE_POWER, AH_PRIVATE(ah)->ah_powerLimit);
824 pModal = &pEepData->modalHeader[IEEE80211_IS_CHAN_2GHZ(chan)];
825 HALDEBUG(ah, HAL_DEBUG_RESET, "%s Channel=%u CfgCtl=%u\n",
826 __func__,chan->ic_freq, cfgCtl );
828 if (IS_EEP_MINOR_V2(ah)) {
829 ht40PowerIncForPdadc = pModal->ht40PowerIncForPdadc;
832 if (!ar5416SetPowerPerRateTable(ah, pEepData, chan,
833 &ratesArray[0],cfgCtl,
834 twiceAntennaReduction,
835 twiceMaxRegulatoryPower, powerLimit)) {
836 HALDEBUG(ah, HAL_DEBUG_ANY,
837 "%s: unable to set tx power per rate table\n", __func__);
841 if (!ar5416SetPowerCalTable(ah, pEepData, chan, &txPowerIndexOffset)) {
842 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: unable to set power table\n",
847 maxPower = AH_MAX(ratesArray[rate6mb], ratesArray[rateHt20_0]);
849 if (IEEE80211_IS_CHAN_2GHZ(chan)) {
850 maxPower = AH_MAX(maxPower, ratesArray[rate1l]);
853 if (IEEE80211_IS_CHAN_HT40(chan)) {
854 maxPower = AH_MAX(maxPower, ratesArray[rateHt40_0]);
857 ahp->ah_tx6PowerInHalfDbm = maxPower;
858 AH_PRIVATE(ah)->ah_maxPowerLevel = maxPower;
859 ahp->ah_txPowerIndexOffset = txPowerIndexOffset;
862 * txPowerIndexOffset is set by the SetPowerTable() call -
863 * adjust the rate table (0 offset if rates EEPROM not loaded)
865 for (i = 0; i < NELEM(ratesArray); i++) {
866 ratesArray[i] = (int16_t)(txPowerIndexOffset + ratesArray[i]);
867 if (ratesArray[i] > AR5416_MAX_RATE_POWER)
868 ratesArray[i] = AR5416_MAX_RATE_POWER;
871 #ifdef AH_EEPROM_DUMP
872 ar5416PrintPowerPerRate(ah, ratesArray);
875 /* Write the OFDM power per rate set */
876 OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE1,
877 POW_SM(ratesArray[rate18mb], 24)
878 | POW_SM(ratesArray[rate12mb], 16)
879 | POW_SM(ratesArray[rate9mb], 8)
880 | POW_SM(ratesArray[rate6mb], 0)
882 OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE2,
883 POW_SM(ratesArray[rate54mb], 24)
884 | POW_SM(ratesArray[rate48mb], 16)
885 | POW_SM(ratesArray[rate36mb], 8)
886 | POW_SM(ratesArray[rate24mb], 0)
889 if (IEEE80211_IS_CHAN_2GHZ(chan)) {
890 /* Write the CCK power per rate set */
891 OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE3,
892 POW_SM(ratesArray[rate2s], 24)
893 | POW_SM(ratesArray[rate2l], 16)
894 | POW_SM(ratesArray[rateXr], 8) /* XR target power */
895 | POW_SM(ratesArray[rate1l], 0)
897 OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE4,
898 POW_SM(ratesArray[rate11s], 24)
899 | POW_SM(ratesArray[rate11l], 16)
900 | POW_SM(ratesArray[rate5_5s], 8)
901 | POW_SM(ratesArray[rate5_5l], 0)
903 HALDEBUG(ah, HAL_DEBUG_RESET,
904 "%s AR_PHY_POWER_TX_RATE3=0x%x AR_PHY_POWER_TX_RATE4=0x%x\n",
905 __func__, OS_REG_READ(ah,AR_PHY_POWER_TX_RATE3),
906 OS_REG_READ(ah,AR_PHY_POWER_TX_RATE4));
909 /* Write the HT20 power per rate set */
910 OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE5,
911 POW_SM(ratesArray[rateHt20_3], 24)
912 | POW_SM(ratesArray[rateHt20_2], 16)
913 | POW_SM(ratesArray[rateHt20_1], 8)
914 | POW_SM(ratesArray[rateHt20_0], 0)
916 OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE6,
917 POW_SM(ratesArray[rateHt20_7], 24)
918 | POW_SM(ratesArray[rateHt20_6], 16)
919 | POW_SM(ratesArray[rateHt20_5], 8)
920 | POW_SM(ratesArray[rateHt20_4], 0)
923 if (IEEE80211_IS_CHAN_HT40(chan)) {
924 /* Write the HT40 power per rate set */
925 /* Correct PAR difference between HT40 and HT20/LEGACY */
926 OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE7,
927 POW_SM(ratesArray[rateHt40_3] + ht40PowerIncForPdadc, 24)
928 | POW_SM(ratesArray[rateHt40_2] + ht40PowerIncForPdadc, 16)
929 | POW_SM(ratesArray[rateHt40_1] + ht40PowerIncForPdadc, 8)
930 | POW_SM(ratesArray[rateHt40_0] + ht40PowerIncForPdadc, 0)
932 OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE8,
933 POW_SM(ratesArray[rateHt40_7] + ht40PowerIncForPdadc, 24)
934 | POW_SM(ratesArray[rateHt40_6] + ht40PowerIncForPdadc, 16)
935 | POW_SM(ratesArray[rateHt40_5] + ht40PowerIncForPdadc, 8)
936 | POW_SM(ratesArray[rateHt40_4] + ht40PowerIncForPdadc, 0)
938 /* Write the Dup/Ext 40 power per rate set */
939 OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE9,
940 POW_SM(ratesArray[rateExtOfdm], 24)
941 | POW_SM(ratesArray[rateExtCck], 16)
942 | POW_SM(ratesArray[rateDupOfdm], 8)
943 | POW_SM(ratesArray[rateDupCck], 0)
947 /* Write the Power subtraction for dynamic chain changing, for per-packet powertx */
948 OS_REG_WRITE(ah, AR_PHY_POWER_TX_SUB,
949 POW_SM(pModal->pwrDecreaseFor3Chain, 6)
950 | POW_SM(pModal->pwrDecreaseFor2Chain, 0)
957 * Exported call to check for a recent gain reading and return
958 * the current state of the thermal calibration gain engine.
961 ar5416GetRfgain(struct ath_hal *ah)
963 return HAL_RFGAIN_INACTIVE;
967 * Places all of hardware into reset
970 ar5416Disable(struct ath_hal *ah)
972 if (!ar5212SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE))
974 return ar5416SetResetReg(ah, HAL_RESET_COLD);
978 * Places the PHY and Radio chips into reset. A full reset
979 * must be called to leave this state. The PCI/MAC/PCU are
980 * not placed into reset as we must receive interrupt to
981 * re-enable the hardware.
984 ar5416PhyDisable(struct ath_hal *ah)
986 return ar5416SetResetReg(ah, HAL_RESET_WARM);
990 * Write the given reset bit mask into the reset register
993 ar5416SetResetReg(struct ath_hal *ah, uint32_t type)
996 case HAL_RESET_POWER_ON:
997 return ar5416SetResetPowerOn(ah);
1000 return ar5416SetReset(ah, type);
1002 HALASSERT(AH_FALSE);
1008 ar5416SetResetPowerOn(struct ath_hal *ah)
1010 /* Power On Reset (Hard Reset) */
1015 * If the MAC was running, previously calling
1016 * reset will wake up the MAC but it may go back to sleep
1017 * before we can start polling.
1018 * Set force wake stops that
1019 * This must be called before initiating a hard reset.
1021 OS_REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1022 AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
1025 * RTC reset and clear
1027 OS_REG_WRITE(ah, AR_RC, AR_RC_AHB);
1028 OS_REG_WRITE(ah, AR_RTC_RESET, 0);
1030 OS_REG_WRITE(ah, AR_RC, 0);
1032 OS_REG_WRITE(ah, AR_RTC_RESET, 1);
1035 * Poll till RTC is ON
1037 if (!ath_hal_wait(ah, AR_RTC_STATUS, AR_RTC_PM_STATUS_M, AR_RTC_STATUS_ON)) {
1038 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: RTC not waking up\n", __func__);
1042 return ar5416SetReset(ah, HAL_RESET_COLD);
1046 ar5416SetReset(struct ath_hal *ah, int type)
1048 uint32_t tmpReg, mask;
1053 OS_REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1054 AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
1059 tmpReg = OS_REG_READ(ah, AR_INTR_SYNC_CAUSE);
1060 if (tmpReg & (AR_INTR_SYNC_LOCAL_TIMEOUT|AR_INTR_SYNC_RADM_CPL_TIMEOUT)) {
1061 OS_REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
1062 OS_REG_WRITE(ah, AR_RC, AR_RC_AHB|AR_RC_HOSTIF);
1064 OS_REG_WRITE(ah, AR_RC, AR_RC_AHB);
1068 * Set Mac(BB,Phy) Warm Reset
1071 case HAL_RESET_WARM:
1072 OS_REG_WRITE(ah, AR_RTC_RC, AR_RTC_RC_MAC_WARM);
1074 case HAL_RESET_COLD:
1075 OS_REG_WRITE(ah, AR_RTC_RC, AR_RTC_RC_MAC_WARM|AR_RTC_RC_MAC_COLD);
1078 HALASSERT(AH_FALSE);
1083 * Clear resets and force wakeup
1085 OS_REG_WRITE(ah, AR_RTC_RC, 0);
1086 if (!ath_hal_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0)) {
1087 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: RTC stuck in MAC reset\n", __func__);
1091 /* Clear AHB reset */
1092 OS_REG_WRITE(ah, AR_RC, 0);
1094 if (type == HAL_RESET_COLD) {
1095 if (isBigEndian()) {
1097 * Set CFG, little-endian for register
1098 * and descriptor accesses.
1100 mask = INIT_CONFIG_STATUS | AR_CFG_SWRD | AR_CFG_SWRG;
1101 #ifndef AH_NEED_DESC_SWAP
1102 mask |= AR_CFG_SWTD;
1104 HALDEBUG(ah, HAL_DEBUG_RESET,
1105 "%s Applying descriptor swap\n", __func__);
1106 OS_REG_WRITE(ah, AR_CFG, LE_READ_4(&mask));
1108 OS_REG_WRITE(ah, AR_CFG, INIT_CONFIG_STATUS);
1111 ar5416InitPLL(ah, AH_NULL);
1116 #ifndef IS_5GHZ_FAST_CLOCK_EN
1117 #define IS_5GHZ_FAST_CLOCK_EN(ah, chan) AH_FALSE
1121 ar5416InitPLL(struct ath_hal *ah, const struct ieee80211_channel *chan)
1125 if (AR_SREV_MERLIN_20(ah) &&
1126 chan != AH_NULL && IEEE80211_IS_CHAN_5GHZ(chan)) {
1128 * PLL WAR for Merlin 2.0/2.1
1129 * When doing fast clock, set PLL to 0x142c
1130 * Else, set PLL to 0x2850 to prevent reset-to-reset variation
1132 pll = IS_5GHZ_FAST_CLOCK_EN(ah, chan) ? 0x142c : 0x2850;
1133 } else if (AR_SREV_MERLIN_10_OR_LATER(ah)) {
1134 pll = SM(0x5, AR_RTC_SOWL_PLL_REFDIV);
1135 if (chan != AH_NULL) {
1136 if (IEEE80211_IS_CHAN_HALF(chan))
1137 pll |= SM(0x1, AR_RTC_SOWL_PLL_CLKSEL);
1138 else if (IEEE80211_IS_CHAN_QUARTER(chan))
1139 pll |= SM(0x2, AR_RTC_SOWL_PLL_CLKSEL);
1140 else if (IEEE80211_IS_CHAN_5GHZ(chan))
1141 pll |= SM(0x28, AR_RTC_SOWL_PLL_DIV);
1143 pll |= SM(0x2c, AR_RTC_SOWL_PLL_DIV);
1145 pll |= SM(0x2c, AR_RTC_SOWL_PLL_DIV);
1146 } else if (AR_SREV_SOWL_10_OR_LATER(ah)) {
1147 pll = SM(0x5, AR_RTC_SOWL_PLL_REFDIV);
1148 if (chan != AH_NULL) {
1149 if (IEEE80211_IS_CHAN_HALF(chan))
1150 pll |= SM(0x1, AR_RTC_SOWL_PLL_CLKSEL);
1151 else if (IEEE80211_IS_CHAN_QUARTER(chan))
1152 pll |= SM(0x2, AR_RTC_SOWL_PLL_CLKSEL);
1153 else if (IEEE80211_IS_CHAN_5GHZ(chan))
1154 pll |= SM(0x50, AR_RTC_SOWL_PLL_DIV);
1156 pll |= SM(0x58, AR_RTC_SOWL_PLL_DIV);
1158 pll |= SM(0x58, AR_RTC_SOWL_PLL_DIV);
1160 pll = AR_RTC_PLL_REFDIV_5 | AR_RTC_PLL_DIV2;
1161 if (chan != AH_NULL) {
1162 if (IEEE80211_IS_CHAN_HALF(chan))
1163 pll |= SM(0x1, AR_RTC_PLL_CLKSEL);
1164 else if (IEEE80211_IS_CHAN_QUARTER(chan))
1165 pll |= SM(0x2, AR_RTC_PLL_CLKSEL);
1166 else if (IEEE80211_IS_CHAN_5GHZ(chan))
1167 pll |= SM(0xa, AR_RTC_PLL_DIV);
1169 pll |= SM(0xb, AR_RTC_PLL_DIV);
1171 pll |= SM(0xb, AR_RTC_PLL_DIV);
1173 OS_REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
1176 * For multi-band owl, switch between bands by reiniting the PLL.
1179 OS_DELAY(RTC_PLL_SETTLE_DELAY);
1181 OS_REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_SLEEP_DERIVED_CLK);
1185 * Read EEPROM header info and program the device for correct operation
1186 * given the channel value.
1189 ar5416SetBoardValues(struct ath_hal *ah, const struct ieee80211_channel *chan)
1191 const HAL_EEPROM_v14 *ee = AH_PRIVATE(ah)->ah_eeprom;
1192 const struct ar5416eeprom *eep = &ee->ee_base;
1193 const MODAL_EEP_HEADER *pModal;
1194 int i, regChainOffset;
1195 uint8_t txRxAttenLocal; /* workaround for eeprom versions <= 14.2 */
1197 HALASSERT(AH_PRIVATE(ah)->ah_eeversion >= AR_EEPROM_VER14_1);
1198 pModal = &eep->modalHeader[IEEE80211_IS_CHAN_2GHZ(chan)];
1200 /* NB: workaround for eeprom versions <= 14.2 */
1201 txRxAttenLocal = IEEE80211_IS_CHAN_2GHZ(chan) ? 23 : 44;
1203 OS_REG_WRITE(ah, AR_PHY_SWITCH_COM, pModal->antCtrlCommon);
1204 for (i = 0; i < AR5416_MAX_CHAINS; i++) {
1205 if (AR_SREV_MERLIN(ah)) {
1208 if (AR_SREV_OWL_20_OR_LATER(ah) &&
1209 (AH5416(ah)->ah_rx_chainmask == 0x5 ||
1210 AH5416(ah)->ah_tx_chainmask == 0x5) && i != 0) {
1211 /* Regs are swapped from chain 2 to 1 for 5416 2_0 with
1212 * only chains 0 and 2 populated
1214 regChainOffset = (i == 1) ? 0x2000 : 0x1000;
1216 regChainOffset = i * 0x1000;
1219 OS_REG_WRITE(ah, AR_PHY_SWITCH_CHAIN_0 + regChainOffset, pModal->antCtrlChain[i]);
1220 OS_REG_WRITE(ah, AR_PHY_TIMING_CTRL4 + regChainOffset,
1221 (OS_REG_READ(ah, AR_PHY_TIMING_CTRL4 + regChainOffset) &
1222 ~(AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF | AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF)) |
1223 SM(pModal->iqCalICh[i], AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF) |
1224 SM(pModal->iqCalQCh[i], AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF));
1227 * Large signal upgrade.
1231 if ((i == 0) || AR_SREV_OWL_20_OR_LATER(ah)) {
1232 OS_REG_WRITE(ah, AR_PHY_RXGAIN + regChainOffset,
1233 (OS_REG_READ(ah, AR_PHY_RXGAIN + regChainOffset) & ~AR_PHY_RXGAIN_TXRX_ATTEN) |
1234 SM(IS_EEP_MINOR_V3(ah) ? pModal->txRxAttenCh[i] : txRxAttenLocal,
1235 AR_PHY_RXGAIN_TXRX_ATTEN));
1237 OS_REG_WRITE(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
1238 (OS_REG_READ(ah, AR_PHY_GAIN_2GHZ + regChainOffset) & ~AR_PHY_GAIN_2GHZ_RXTX_MARGIN) |
1239 SM(pModal->rxTxMarginCh[i], AR_PHY_GAIN_2GHZ_RXTX_MARGIN));
1243 OS_REG_RMW_FIELD(ah, AR_PHY_SETTLING, AR_PHY_SETTLING_SWITCH, pModal->switchSettling);
1244 OS_REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ, AR_PHY_DESIRED_SZ_ADC, pModal->adcDesiredSize);
1245 OS_REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ, AR_PHY_DESIRED_SZ_PGA, pModal->pgaDesiredSize);
1246 OS_REG_WRITE(ah, AR_PHY_RF_CTL4,
1247 SM(pModal->txEndToXpaOff, AR_PHY_RF_CTL4_TX_END_XPAA_OFF)
1248 | SM(pModal->txEndToXpaOff, AR_PHY_RF_CTL4_TX_END_XPAB_OFF)
1249 | SM(pModal->txFrameToXpaOn, AR_PHY_RF_CTL4_FRAME_XPAA_ON)
1250 | SM(pModal->txFrameToXpaOn, AR_PHY_RF_CTL4_FRAME_XPAB_ON));
1252 OS_REG_RMW_FIELD(ah, AR_PHY_RF_CTL3, AR_PHY_TX_END_TO_A2_RX_ON, pModal->txEndToRxOn);
1254 if (AR_SREV_MERLIN_10_OR_LATER(ah)) {
1255 OS_REG_RMW_FIELD(ah, AR_PHY_CCA, AR9280_PHY_CCA_THRESH62,
1257 OS_REG_RMW_FIELD(ah, AR_PHY_EXT_CCA0, AR_PHY_EXT_CCA0_THRESH62,
1260 OS_REG_RMW_FIELD(ah, AR_PHY_CCA, AR_PHY_CCA_THRESH62,
1262 OS_REG_RMW_FIELD(ah, AR_PHY_EXT_CCA0, AR_PHY_EXT_CCA_THRESH62,
1266 /* Minor Version Specific application */
1267 if (IS_EEP_MINOR_V2(ah)) {
1268 OS_REG_RMW_FIELD(ah, AR_PHY_RF_CTL2, AR_PHY_TX_FRAME_TO_DATA_START, pModal->txFrameToDataStart);
1269 OS_REG_RMW_FIELD(ah, AR_PHY_RF_CTL2, AR_PHY_TX_FRAME_TO_PA_ON, pModal->txFrameToPaOn);
1272 if (IS_EEP_MINOR_V3(ah)) {
1273 if (IEEE80211_IS_CHAN_HT40(chan)) {
1274 /* Overwrite switch settling with HT40 value */
1275 OS_REG_RMW_FIELD(ah, AR_PHY_SETTLING, AR_PHY_SETTLING_SWITCH, pModal->swSettleHt40);
1278 if ((AR_SREV_OWL_20_OR_LATER(ah)) &&
1279 ( AH5416(ah)->ah_rx_chainmask == 0x5 || AH5416(ah)->ah_tx_chainmask == 0x5)){
1280 /* Reg Offsets are swapped for logical mapping */
1281 OS_REG_WRITE(ah, AR_PHY_GAIN_2GHZ + 0x1000, (OS_REG_READ(ah, AR_PHY_GAIN_2GHZ + 0x1000) & ~AR_PHY_GAIN_2GHZ_BSW_MARGIN) |
1282 SM(pModal->bswMargin[2], AR_PHY_GAIN_2GHZ_BSW_MARGIN));
1283 OS_REG_WRITE(ah, AR_PHY_GAIN_2GHZ + 0x1000, (OS_REG_READ(ah, AR_PHY_GAIN_2GHZ + 0x1000) & ~AR_PHY_GAIN_2GHZ_BSW_ATTEN) |
1284 SM(pModal->bswAtten[2], AR_PHY_GAIN_2GHZ_BSW_ATTEN));
1285 OS_REG_WRITE(ah, AR_PHY_GAIN_2GHZ + 0x2000, (OS_REG_READ(ah, AR_PHY_GAIN_2GHZ + 0x2000) & ~AR_PHY_GAIN_2GHZ_BSW_MARGIN) |
1286 SM(pModal->bswMargin[1], AR_PHY_GAIN_2GHZ_BSW_MARGIN));
1287 OS_REG_WRITE(ah, AR_PHY_GAIN_2GHZ + 0x2000, (OS_REG_READ(ah, AR_PHY_GAIN_2GHZ + 0x2000) & ~AR_PHY_GAIN_2GHZ_BSW_ATTEN) |
1288 SM(pModal->bswAtten[1], AR_PHY_GAIN_2GHZ_BSW_ATTEN));
1290 OS_REG_WRITE(ah, AR_PHY_GAIN_2GHZ + 0x1000, (OS_REG_READ(ah, AR_PHY_GAIN_2GHZ + 0x1000) & ~AR_PHY_GAIN_2GHZ_BSW_MARGIN) |
1291 SM(pModal->bswMargin[1], AR_PHY_GAIN_2GHZ_BSW_MARGIN));
1292 OS_REG_WRITE(ah, AR_PHY_GAIN_2GHZ + 0x1000, (OS_REG_READ(ah, AR_PHY_GAIN_2GHZ + 0x1000) & ~AR_PHY_GAIN_2GHZ_BSW_ATTEN) |
1293 SM(pModal->bswAtten[1], AR_PHY_GAIN_2GHZ_BSW_ATTEN));
1294 OS_REG_WRITE(ah, AR_PHY_GAIN_2GHZ + 0x2000, (OS_REG_READ(ah, AR_PHY_GAIN_2GHZ + 0x2000) & ~AR_PHY_GAIN_2GHZ_BSW_MARGIN) |
1295 SM(pModal->bswMargin[2],AR_PHY_GAIN_2GHZ_BSW_MARGIN));
1296 OS_REG_WRITE(ah, AR_PHY_GAIN_2GHZ + 0x2000, (OS_REG_READ(ah, AR_PHY_GAIN_2GHZ + 0x2000) & ~AR_PHY_GAIN_2GHZ_BSW_ATTEN) |
1297 SM(pModal->bswAtten[2], AR_PHY_GAIN_2GHZ_BSW_ATTEN));
1299 OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ, AR_PHY_GAIN_2GHZ_BSW_MARGIN, pModal->bswMargin[0]);
1300 OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ, AR_PHY_GAIN_2GHZ_BSW_ATTEN, pModal->bswAtten[0]);
1306 * Helper functions common for AP/CB/XB
1310 * ar5416SetPowerPerRateTable
1312 * Sets the transmit power in the baseband for the given
1313 * operating channel and mode.
1316 ar5416SetPowerPerRateTable(struct ath_hal *ah, struct ar5416eeprom *pEepData,
1317 const struct ieee80211_channel *chan,
1318 int16_t *ratesArray, uint16_t cfgCtl,
1319 uint16_t AntennaReduction,
1320 uint16_t twiceMaxRegulatoryPower,
1321 uint16_t powerLimit)
1323 /* Local defines to distinguish between extension and control CTL's */
1324 #define EXT_ADDITIVE (0x8000)
1325 #define CTL_11A_EXT (CTL_11A | EXT_ADDITIVE)
1326 #define CTL_11G_EXT (CTL_11G | EXT_ADDITIVE)
1327 #define CTL_11B_EXT (CTL_11B | EXT_ADDITIVE)
1329 uint16_t twiceMaxEdgePower = AR5416_MAX_RATE_POWER;
1331 int16_t twiceLargestAntenna;
1333 CAL_TARGET_POWER_LEG targetPowerOfdm, targetPowerCck = {0, {0, 0, 0, 0}};
1334 CAL_TARGET_POWER_LEG targetPowerOfdmExt = {0, {0, 0, 0, 0}}, targetPowerCckExt = {0, {0, 0, 0, 0}};
1335 CAL_TARGET_POWER_HT targetPowerHt20, targetPowerHt40 = {0, {0, 0, 0, 0}};
1336 int16_t scaledPower, minCtlPower;
1338 #define SUB_NUM_CTL_MODES_AT_5G_40 2 /* excluding HT40, EXT-OFDM */
1339 #define SUB_NUM_CTL_MODES_AT_2G_40 3 /* excluding HT40, EXT-OFDM, EXT-CCK */
1340 static const uint16_t ctlModesFor11a[] = {
1341 CTL_11A, CTL_5GHT20, CTL_11A_EXT, CTL_5GHT40
1343 static const uint16_t ctlModesFor11g[] = {
1344 CTL_11B, CTL_11G, CTL_2GHT20, CTL_11B_EXT, CTL_11G_EXT, CTL_2GHT40
1346 const uint16_t *pCtlMode;
1347 uint16_t numCtlModes, ctlMode, freq;
1348 CHAN_CENTERS centers;
1350 ar5416GetChannelCenters(ah, chan, ¢ers);
1352 /* Compute TxPower reduction due to Antenna Gain */
1354 twiceLargestAntenna = AH_MAX(AH_MAX(
1355 pEepData->modalHeader[IEEE80211_IS_CHAN_2GHZ(chan)].antennaGainCh[0],
1356 pEepData->modalHeader[IEEE80211_IS_CHAN_2GHZ(chan)].antennaGainCh[1]),
1357 pEepData->modalHeader[IEEE80211_IS_CHAN_2GHZ(chan)].antennaGainCh[2]);
1359 /* Turn it back on if we need to calculate per chain antenna gain reduction */
1360 /* Use only if the expected gain > 6dbi */
1361 /* Chain 0 is always used */
1362 twiceLargestAntenna = pEepData->modalHeader[IEEE80211_IS_CHAN_2GHZ(chan)].antennaGainCh[0];
1364 /* Look at antenna gains of Chains 1 and 2 if the TX mask is set */
1365 if (ahp->ah_tx_chainmask & 0x2)
1366 twiceLargestAntenna = AH_MAX(twiceLargestAntenna,
1367 pEepData->modalHeader[IEEE80211_IS_CHAN_2GHZ(chan)].antennaGainCh[1]);
1369 if (ahp->ah_tx_chainmask & 0x4)
1370 twiceLargestAntenna = AH_MAX(twiceLargestAntenna,
1371 pEepData->modalHeader[IEEE80211_IS_CHAN_2GHZ(chan)].antennaGainCh[2]);
1373 twiceLargestAntenna = (int16_t)AH_MIN((AntennaReduction) - twiceLargestAntenna, 0);
1375 /* XXX setup for 5212 use (really used?) */
1376 ath_hal_eepromSet(ah,
1377 IEEE80211_IS_CHAN_2GHZ(chan) ? AR_EEP_ANTGAINMAX_2 : AR_EEP_ANTGAINMAX_5,
1378 twiceLargestAntenna);
1381 * scaledPower is the minimum of the user input power level and
1382 * the regulatory allowed power level
1384 scaledPower = AH_MIN(powerLimit, twiceMaxRegulatoryPower + twiceLargestAntenna);
1386 /* Reduce scaled Power by number of chains active to get to per chain tx power level */
1387 /* TODO: better value than these? */
1388 switch (owl_get_ntxchains(AH5416(ah)->ah_tx_chainmask)) {
1392 scaledPower -= pEepData->modalHeader[IEEE80211_IS_CHAN_2GHZ(chan)].pwrDecreaseFor2Chain;
1395 scaledPower -= pEepData->modalHeader[IEEE80211_IS_CHAN_2GHZ(chan)].pwrDecreaseFor3Chain;
1398 return AH_FALSE; /* Unsupported number of chains */
1401 scaledPower = AH_MAX(0, scaledPower);
1403 /* Get target powers from EEPROM - our baseline for TX Power */
1404 if (IEEE80211_IS_CHAN_2GHZ(chan)) {
1405 /* Setup for CTL modes */
1406 numCtlModes = NELEM(ctlModesFor11g) - SUB_NUM_CTL_MODES_AT_2G_40; /* CTL_11B, CTL_11G, CTL_2GHT20 */
1407 pCtlMode = ctlModesFor11g;
1409 ar5416GetTargetPowersLeg(ah, chan, pEepData->calTargetPowerCck,
1410 AR5416_NUM_2G_CCK_TARGET_POWERS, &targetPowerCck, 4, AH_FALSE);
1411 ar5416GetTargetPowersLeg(ah, chan, pEepData->calTargetPower2G,
1412 AR5416_NUM_2G_20_TARGET_POWERS, &targetPowerOfdm, 4, AH_FALSE);
1413 ar5416GetTargetPowers(ah, chan, pEepData->calTargetPower2GHT20,
1414 AR5416_NUM_2G_20_TARGET_POWERS, &targetPowerHt20, 8, AH_FALSE);
1416 if (IEEE80211_IS_CHAN_HT40(chan)) {
1417 numCtlModes = NELEM(ctlModesFor11g); /* All 2G CTL's */
1419 ar5416GetTargetPowers(ah, chan, pEepData->calTargetPower2GHT40,
1420 AR5416_NUM_2G_40_TARGET_POWERS, &targetPowerHt40, 8, AH_TRUE);
1421 /* Get target powers for extension channels */
1422 ar5416GetTargetPowersLeg(ah, chan, pEepData->calTargetPowerCck,
1423 AR5416_NUM_2G_CCK_TARGET_POWERS, &targetPowerCckExt, 4, AH_TRUE);
1424 ar5416GetTargetPowersLeg(ah, chan, pEepData->calTargetPower2G,
1425 AR5416_NUM_2G_20_TARGET_POWERS, &targetPowerOfdmExt, 4, AH_TRUE);
1428 /* Setup for CTL modes */
1429 numCtlModes = NELEM(ctlModesFor11a) - SUB_NUM_CTL_MODES_AT_5G_40; /* CTL_11A, CTL_5GHT20 */
1430 pCtlMode = ctlModesFor11a;
1432 ar5416GetTargetPowersLeg(ah, chan, pEepData->calTargetPower5G,
1433 AR5416_NUM_5G_20_TARGET_POWERS, &targetPowerOfdm, 4, AH_FALSE);
1434 ar5416GetTargetPowers(ah, chan, pEepData->calTargetPower5GHT20,
1435 AR5416_NUM_5G_20_TARGET_POWERS, &targetPowerHt20, 8, AH_FALSE);
1437 if (IEEE80211_IS_CHAN_HT40(chan)) {
1438 numCtlModes = NELEM(ctlModesFor11a); /* All 5G CTL's */
1440 ar5416GetTargetPowers(ah, chan, pEepData->calTargetPower5GHT40,
1441 AR5416_NUM_5G_40_TARGET_POWERS, &targetPowerHt40, 8, AH_TRUE);
1442 ar5416GetTargetPowersLeg(ah, chan, pEepData->calTargetPower5G,
1443 AR5416_NUM_5G_20_TARGET_POWERS, &targetPowerOfdmExt, 4, AH_TRUE);
1448 * For MIMO, need to apply regulatory caps individually across dynamically
1449 * running modes: CCK, OFDM, HT20, HT40
1451 * The outer loop walks through each possible applicable runtime mode.
1452 * The inner loop walks through each ctlIndex entry in EEPROM.
1453 * The ctl value is encoded as [7:4] == test group, [3:0] == test mode.
1456 for (ctlMode = 0; ctlMode < numCtlModes; ctlMode++) {
1457 HAL_BOOL isHt40CtlMode = (pCtlMode[ctlMode] == CTL_5GHT40) ||
1458 (pCtlMode[ctlMode] == CTL_2GHT40);
1459 if (isHt40CtlMode) {
1460 freq = centers.ctl_center;
1461 } else if (pCtlMode[ctlMode] & EXT_ADDITIVE) {
1462 freq = centers.ext_center;
1464 freq = centers.ctl_center;
1467 /* walk through each CTL index stored in EEPROM */
1468 for (i = 0; (i < AR5416_NUM_CTLS) && pEepData->ctlIndex[i]; i++) {
1469 uint16_t twiceMinEdgePower;
1471 /* compare test group from regulatory channel list with test mode from pCtlMode list */
1472 if ((((cfgCtl & ~CTL_MODE_M) | (pCtlMode[ctlMode] & CTL_MODE_M)) == pEepData->ctlIndex[i]) ||
1473 (((cfgCtl & ~CTL_MODE_M) | (pCtlMode[ctlMode] & CTL_MODE_M)) ==
1474 ((pEepData->ctlIndex[i] & CTL_MODE_M) | SD_NO_CTL))) {
1475 rep = &(pEepData->ctlData[i]);
1476 twiceMinEdgePower = ar5416GetMaxEdgePower(freq,
1477 rep->ctlEdges[owl_get_ntxchains(AH5416(ah)->ah_tx_chainmask) - 1],
1478 IEEE80211_IS_CHAN_2GHZ(chan));
1479 if ((cfgCtl & ~CTL_MODE_M) == SD_NO_CTL) {
1480 /* Find the minimum of all CTL edge powers that apply to this channel */
1481 twiceMaxEdgePower = AH_MIN(twiceMaxEdgePower, twiceMinEdgePower);
1484 twiceMaxEdgePower = twiceMinEdgePower;
1489 minCtlPower = (uint8_t)AH_MIN(twiceMaxEdgePower, scaledPower);
1490 /* Apply ctl mode to correct target power set */
1491 switch(pCtlMode[ctlMode]) {
1493 for (i = 0; i < NELEM(targetPowerCck.tPow2x); i++) {
1494 targetPowerCck.tPow2x[i] = (uint8_t)AH_MIN(targetPowerCck.tPow2x[i], minCtlPower);
1499 for (i = 0; i < NELEM(targetPowerOfdm.tPow2x); i++) {
1500 targetPowerOfdm.tPow2x[i] = (uint8_t)AH_MIN(targetPowerOfdm.tPow2x[i], minCtlPower);
1505 for (i = 0; i < NELEM(targetPowerHt20.tPow2x); i++) {
1506 targetPowerHt20.tPow2x[i] = (uint8_t)AH_MIN(targetPowerHt20.tPow2x[i], minCtlPower);
1510 targetPowerCckExt.tPow2x[0] = (uint8_t)AH_MIN(targetPowerCckExt.tPow2x[0], minCtlPower);
1514 targetPowerOfdmExt.tPow2x[0] = (uint8_t)AH_MIN(targetPowerOfdmExt.tPow2x[0], minCtlPower);
1518 for (i = 0; i < NELEM(targetPowerHt40.tPow2x); i++) {
1519 targetPowerHt40.tPow2x[i] = (uint8_t)AH_MIN(targetPowerHt40.tPow2x[i], minCtlPower);
1526 } /* end ctl mode checking */
1528 /* Set rates Array from collected data */
1529 ratesArray[rate6mb] = ratesArray[rate9mb] = ratesArray[rate12mb] = ratesArray[rate18mb] = ratesArray[rate24mb] = targetPowerOfdm.tPow2x[0];
1530 ratesArray[rate36mb] = targetPowerOfdm.tPow2x[1];
1531 ratesArray[rate48mb] = targetPowerOfdm.tPow2x[2];
1532 ratesArray[rate54mb] = targetPowerOfdm.tPow2x[3];
1533 ratesArray[rateXr] = targetPowerOfdm.tPow2x[0];
1535 for (i = 0; i < NELEM(targetPowerHt20.tPow2x); i++) {
1536 ratesArray[rateHt20_0 + i] = targetPowerHt20.tPow2x[i];
1539 if (IEEE80211_IS_CHAN_2GHZ(chan)) {
1540 ratesArray[rate1l] = targetPowerCck.tPow2x[0];
1541 ratesArray[rate2s] = ratesArray[rate2l] = targetPowerCck.tPow2x[1];
1542 ratesArray[rate5_5s] = ratesArray[rate5_5l] = targetPowerCck.tPow2x[2];
1543 ratesArray[rate11s] = ratesArray[rate11l] = targetPowerCck.tPow2x[3];
1545 if (IEEE80211_IS_CHAN_HT40(chan)) {
1546 for (i = 0; i < NELEM(targetPowerHt40.tPow2x); i++) {
1547 ratesArray[rateHt40_0 + i] = targetPowerHt40.tPow2x[i];
1549 ratesArray[rateDupOfdm] = targetPowerHt40.tPow2x[0];
1550 ratesArray[rateDupCck] = targetPowerHt40.tPow2x[0];
1551 ratesArray[rateExtOfdm] = targetPowerOfdmExt.tPow2x[0];
1552 if (IEEE80211_IS_CHAN_2GHZ(chan)) {
1553 ratesArray[rateExtCck] = targetPowerCckExt.tPow2x[0];
1561 #undef SUB_NUM_CTL_MODES_AT_5G_40
1562 #undef SUB_NUM_CTL_MODES_AT_2G_40
1565 /**************************************************************************
1568 * Get channel value from binary representation held in eeprom
1569 * RETURNS: the frequency in MHz
1572 fbin2freq(uint8_t fbin, HAL_BOOL is2GHz)
1575 * Reserved value 0xFF provides an empty definition both as
1576 * an fbin and as a frequency - do not convert
1578 if (fbin == AR5416_BCHAN_UNUSED) {
1582 return (uint16_t)((is2GHz) ? (2300 + fbin) : (4800 + 5 * fbin));
1586 * ar5416GetMaxEdgePower
1588 * Find the maximum conformance test limit for the given channel and CTL info
1591 ar5416GetMaxEdgePower(uint16_t freq, CAL_CTL_EDGES *pRdEdgesPower, HAL_BOOL is2GHz)
1593 uint16_t twiceMaxEdgePower = AR5416_MAX_RATE_POWER;
1596 /* Get the edge power */
1597 for (i = 0; (i < AR5416_NUM_BAND_EDGES) && (pRdEdgesPower[i].bChannel != AR5416_BCHAN_UNUSED) ; i++) {
1599 * If there's an exact channel match or an inband flag set
1600 * on the lower channel use the given rdEdgePower
1602 if (freq == fbin2freq(pRdEdgesPower[i].bChannel, is2GHz)) {
1603 twiceMaxEdgePower = MS(pRdEdgesPower[i].tPowerFlag, CAL_CTL_EDGES_POWER);
1605 } else if ((i > 0) && (freq < fbin2freq(pRdEdgesPower[i].bChannel, is2GHz))) {
1606 if (fbin2freq(pRdEdgesPower[i - 1].bChannel, is2GHz) < freq && (pRdEdgesPower[i - 1].tPowerFlag & CAL_CTL_EDGES_FLAG) != 0) {
1607 twiceMaxEdgePower = MS(pRdEdgesPower[i - 1].tPowerFlag, CAL_CTL_EDGES_POWER);
1609 /* Leave loop - no more affecting edges possible in this monotonic increasing list */
1613 HALASSERT(twiceMaxEdgePower > 0);
1614 return twiceMaxEdgePower;
1617 /**************************************************************
1618 * ar5416GetTargetPowers
1620 * Return the rates of target power for the given target power table
1621 * channel, and number of channels
1624 ar5416GetTargetPowers(struct ath_hal *ah, const struct ieee80211_channel *chan,
1625 CAL_TARGET_POWER_HT *powInfo, uint16_t numChannels,
1626 CAL_TARGET_POWER_HT *pNewPower, uint16_t numRates,
1627 HAL_BOOL isHt40Target)
1631 int matchIndex = -1, lowIndex = -1;
1633 CHAN_CENTERS centers;
1635 ar5416GetChannelCenters(ah, chan, ¢ers);
1636 freq = isHt40Target ? centers.synth_center : centers.ctl_center;
1638 /* Copy the target powers into the temp channel list */
1639 if (freq <= fbin2freq(powInfo[0].bChannel, IEEE80211_IS_CHAN_2GHZ(chan))) {
1642 for (i = 0; (i < numChannels) && (powInfo[i].bChannel != AR5416_BCHAN_UNUSED); i++) {
1643 if (freq == fbin2freq(powInfo[i].bChannel, IEEE80211_IS_CHAN_2GHZ(chan))) {
1646 } else if ((freq < fbin2freq(powInfo[i].bChannel, IEEE80211_IS_CHAN_2GHZ(chan))) &&
1647 (freq > fbin2freq(powInfo[i - 1].bChannel, IEEE80211_IS_CHAN_2GHZ(chan))))
1653 if ((matchIndex == -1) && (lowIndex == -1)) {
1654 HALASSERT(freq > fbin2freq(powInfo[i - 1].bChannel, IEEE80211_IS_CHAN_2GHZ(chan)));
1659 if (matchIndex != -1) {
1660 OS_MEMCPY(pNewPower, &powInfo[matchIndex], sizeof(*pNewPower));
1662 HALASSERT(lowIndex != -1);
1664 * Get the lower and upper channels, target powers,
1665 * and interpolate between them.
1667 clo = fbin2freq(powInfo[lowIndex].bChannel, IEEE80211_IS_CHAN_2GHZ(chan));
1668 chi = fbin2freq(powInfo[lowIndex + 1].bChannel, IEEE80211_IS_CHAN_2GHZ(chan));
1670 for (i = 0; i < numRates; i++) {
1671 pNewPower->tPow2x[i] = (uint8_t)interpolate(freq, clo, chi,
1672 powInfo[lowIndex].tPow2x[i], powInfo[lowIndex + 1].tPow2x[i]);
1676 /**************************************************************
1677 * ar5416GetTargetPowersLeg
1679 * Return the four rates of target power for the given target power table
1680 * channel, and number of channels
1683 ar5416GetTargetPowersLeg(struct ath_hal *ah,
1684 const struct ieee80211_channel *chan,
1685 CAL_TARGET_POWER_LEG *powInfo, uint16_t numChannels,
1686 CAL_TARGET_POWER_LEG *pNewPower, uint16_t numRates,
1687 HAL_BOOL isExtTarget)
1691 int matchIndex = -1, lowIndex = -1;
1693 CHAN_CENTERS centers;
1695 ar5416GetChannelCenters(ah, chan, ¢ers);
1696 freq = (isExtTarget) ? centers.ext_center :centers.ctl_center;
1698 /* Copy the target powers into the temp channel list */
1699 if (freq <= fbin2freq(powInfo[0].bChannel, IEEE80211_IS_CHAN_2GHZ(chan))) {
1702 for (i = 0; (i < numChannels) && (powInfo[i].bChannel != AR5416_BCHAN_UNUSED); i++) {
1703 if (freq == fbin2freq(powInfo[i].bChannel, IEEE80211_IS_CHAN_2GHZ(chan))) {
1706 } else if ((freq < fbin2freq(powInfo[i].bChannel, IEEE80211_IS_CHAN_2GHZ(chan))) &&
1707 (freq > fbin2freq(powInfo[i - 1].bChannel, IEEE80211_IS_CHAN_2GHZ(chan))))
1713 if ((matchIndex == -1) && (lowIndex == -1)) {
1714 HALASSERT(freq > fbin2freq(powInfo[i - 1].bChannel, IEEE80211_IS_CHAN_2GHZ(chan)));
1719 if (matchIndex != -1) {
1720 OS_MEMCPY(pNewPower, &powInfo[matchIndex], sizeof(*pNewPower));
1722 HALASSERT(lowIndex != -1);
1724 * Get the lower and upper channels, target powers,
1725 * and interpolate between them.
1727 clo = fbin2freq(powInfo[lowIndex].bChannel, IEEE80211_IS_CHAN_2GHZ(chan));
1728 chi = fbin2freq(powInfo[lowIndex + 1].bChannel, IEEE80211_IS_CHAN_2GHZ(chan));
1730 for (i = 0; i < numRates; i++) {
1731 pNewPower->tPow2x[i] = (uint8_t)interpolate(freq, clo, chi,
1732 powInfo[lowIndex].tPow2x[i], powInfo[lowIndex + 1].tPow2x[i]);
1737 /**************************************************************
1738 * ar5416SetPowerCalTable
1740 * Pull the PDADC piers from cal data and interpolate them across the given
1741 * points as well as from the nearest pier(s) to get a power detector
1742 * linear voltage to power level table.
1745 ar5416SetPowerCalTable(struct ath_hal *ah, struct ar5416eeprom *pEepData,
1746 const struct ieee80211_channel *chan, int16_t *pTxPowerIndexOffset)
1748 CAL_DATA_PER_FREQ *pRawDataset;
1749 uint8_t *pCalBChans = AH_NULL;
1750 uint16_t pdGainOverlap_t2;
1751 static uint8_t pdadcValues[AR5416_NUM_PDADC_VALUES];
1752 uint16_t gainBoundaries[AR5416_PD_GAINS_IN_MASK];
1753 uint16_t numPiers, i, j;
1754 int16_t tMinCalPower;
1755 uint16_t numXpdGain, xpdMask;
1756 uint16_t xpdGainValues[AR5416_NUM_PD_GAINS];
1757 uint32_t reg32, regOffset, regChainOffset;
1759 OS_MEMZERO(xpdGainValues, sizeof(xpdGainValues));
1761 xpdMask = pEepData->modalHeader[IEEE80211_IS_CHAN_2GHZ(chan)].xpdGain;
1763 if (IS_EEP_MINOR_V2(ah)) {
1764 pdGainOverlap_t2 = pEepData->modalHeader[IEEE80211_IS_CHAN_2GHZ(chan)].pdGainOverlap;
1766 pdGainOverlap_t2 = (uint16_t)(MS(OS_REG_READ(ah, AR_PHY_TPCRG5), AR_PHY_TPCRG5_PD_GAIN_OVERLAP));
1769 if (IEEE80211_IS_CHAN_2GHZ(chan)) {
1770 pCalBChans = pEepData->calFreqPier2G;
1771 numPiers = AR5416_NUM_2G_CAL_PIERS;
1773 pCalBChans = pEepData->calFreqPier5G;
1774 numPiers = AR5416_NUM_5G_CAL_PIERS;
1778 /* Calculate the value of xpdgains from the xpdGain Mask */
1779 for (i = 1; i <= AR5416_PD_GAINS_IN_MASK; i++) {
1780 if ((xpdMask >> (AR5416_PD_GAINS_IN_MASK - i)) & 1) {
1781 if (numXpdGain >= AR5416_NUM_PD_GAINS) {
1785 xpdGainValues[numXpdGain] = (uint16_t)(AR5416_PD_GAINS_IN_MASK - i);
1790 /* Write the detector gain biases and their number */
1791 OS_REG_WRITE(ah, AR_PHY_TPCRG1, (OS_REG_READ(ah, AR_PHY_TPCRG1) &
1792 ~(AR_PHY_TPCRG1_NUM_PD_GAIN | AR_PHY_TPCRG1_PD_GAIN_1 | AR_PHY_TPCRG1_PD_GAIN_2 | AR_PHY_TPCRG1_PD_GAIN_3)) |
1793 SM(numXpdGain - 1, AR_PHY_TPCRG1_NUM_PD_GAIN) | SM(xpdGainValues[0], AR_PHY_TPCRG1_PD_GAIN_1 ) |
1794 SM(xpdGainValues[1], AR_PHY_TPCRG1_PD_GAIN_2) | SM(xpdGainValues[2], AR_PHY_TPCRG1_PD_GAIN_3));
1796 for (i = 0; i < AR5416_MAX_CHAINS; i++) {
1798 if (AR_SREV_OWL_20_OR_LATER(ah) &&
1799 ( AH5416(ah)->ah_rx_chainmask == 0x5 || AH5416(ah)->ah_tx_chainmask == 0x5) && (i != 0)) {
1800 /* Regs are swapped from chain 2 to 1 for 5416 2_0 with
1801 * only chains 0 and 2 populated
1803 regChainOffset = (i == 1) ? 0x2000 : 0x1000;
1805 regChainOffset = i * 0x1000;
1808 if (pEepData->baseEepHeader.txMask & (1 << i)) {
1809 if (IEEE80211_IS_CHAN_2GHZ(chan)) {
1810 pRawDataset = pEepData->calPierData2G[i];
1812 pRawDataset = pEepData->calPierData5G[i];
1815 ar5416GetGainBoundariesAndPdadcs(ah, chan, pRawDataset,
1816 pCalBChans, numPiers,
1818 &tMinCalPower, gainBoundaries,
1819 pdadcValues, numXpdGain);
1821 if ((i == 0) || AR_SREV_OWL_20_OR_LATER(ah)) {
1823 * Note the pdadc table may not start at 0 dBm power, could be
1824 * negative or greater than 0. Need to offset the power
1825 * values by the amount of minPower for griffin
1828 OS_REG_WRITE(ah, AR_PHY_TPCRG5 + regChainOffset,
1829 SM(pdGainOverlap_t2, AR_PHY_TPCRG5_PD_GAIN_OVERLAP) |
1830 SM(gainBoundaries[0], AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1) |
1831 SM(gainBoundaries[1], AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2) |
1832 SM(gainBoundaries[2], AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3) |
1833 SM(gainBoundaries[3], AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4));
1836 /* Write the power values into the baseband power table */
1837 regOffset = AR_PHY_BASE + (672 << 2) + regChainOffset;
1839 for (j = 0; j < 32; j++) {
1840 reg32 = ((pdadcValues[4*j + 0] & 0xFF) << 0) |
1841 ((pdadcValues[4*j + 1] & 0xFF) << 8) |
1842 ((pdadcValues[4*j + 2] & 0xFF) << 16) |
1843 ((pdadcValues[4*j + 3] & 0xFF) << 24) ;
1844 OS_REG_WRITE(ah, regOffset, reg32);
1847 ath_hal_printf(ah, "PDADC: Chain %d | PDADC %3d Value %3d | PDADC %3d Value %3d | PDADC %3d Value %3d | PDADC %3d Value %3d |\n",
1849 4*j, pdadcValues[4*j],
1850 4*j+1, pdadcValues[4*j + 1],
1851 4*j+2, pdadcValues[4*j + 2],
1852 4*j+3, pdadcValues[4*j + 3]);
1858 *pTxPowerIndexOffset = 0;
1863 /**************************************************************
1864 * ar5416GetGainBoundariesAndPdadcs
1866 * Uses the data points read from EEPROM to reconstruct the pdadc power table
1867 * Called by ar5416SetPowerCalTable only.
1870 ar5416GetGainBoundariesAndPdadcs(struct ath_hal *ah,
1871 const struct ieee80211_channel *chan,
1872 CAL_DATA_PER_FREQ *pRawDataSet,
1873 uint8_t * bChans, uint16_t availPiers,
1874 uint16_t tPdGainOverlap, int16_t *pMinCalPower, uint16_t * pPdGainBoundaries,
1875 uint8_t * pPDADCValues, uint16_t numXpdGains)
1879 int16_t ss; /* potentially -ve index for taking care of pdGainOverlap */
1880 uint16_t idxL, idxR, numPiers; /* Pier indexes */
1882 /* filled out Vpd table for all pdGains (chanL) */
1883 static uint8_t vpdTableL[AR5416_NUM_PD_GAINS][AR5416_MAX_PWR_RANGE_IN_HALF_DB];
1885 /* filled out Vpd table for all pdGains (chanR) */
1886 static uint8_t vpdTableR[AR5416_NUM_PD_GAINS][AR5416_MAX_PWR_RANGE_IN_HALF_DB];
1888 /* filled out Vpd table for all pdGains (interpolated) */
1889 static uint8_t vpdTableI[AR5416_NUM_PD_GAINS][AR5416_MAX_PWR_RANGE_IN_HALF_DB];
1891 uint8_t *pVpdL, *pVpdR, *pPwrL, *pPwrR;
1892 uint8_t minPwrT4[AR5416_NUM_PD_GAINS];
1893 uint8_t maxPwrT4[AR5416_NUM_PD_GAINS];
1896 uint16_t sizeCurrVpdTable, maxIndex, tgtIndex;
1898 int16_t minDelta = 0;
1899 CHAN_CENTERS centers;
1901 ar5416GetChannelCenters(ah, chan, ¢ers);
1903 /* Trim numPiers for the number of populated channel Piers */
1904 for (numPiers = 0; numPiers < availPiers; numPiers++) {
1905 if (bChans[numPiers] == AR5416_BCHAN_UNUSED) {
1910 /* Find pier indexes around the current channel */
1911 match = getLowerUpperIndex((uint8_t)FREQ2FBIN(centers.synth_center, IEEE80211_IS_CHAN_2GHZ(chan)),
1912 bChans, numPiers, &idxL, &idxR);
1915 /* Directly fill both vpd tables from the matching index */
1916 for (i = 0; i < numXpdGains; i++) {
1917 minPwrT4[i] = pRawDataSet[idxL].pwrPdg[i][0];
1918 maxPwrT4[i] = pRawDataSet[idxL].pwrPdg[i][4];
1919 ar5416FillVpdTable(minPwrT4[i], maxPwrT4[i], pRawDataSet[idxL].pwrPdg[i],
1920 pRawDataSet[idxL].vpdPdg[i], AR5416_PD_GAIN_ICEPTS, vpdTableI[i]);
1923 for (i = 0; i < numXpdGains; i++) {
1924 pVpdL = pRawDataSet[idxL].vpdPdg[i];
1925 pPwrL = pRawDataSet[idxL].pwrPdg[i];
1926 pVpdR = pRawDataSet[idxR].vpdPdg[i];
1927 pPwrR = pRawDataSet[idxR].pwrPdg[i];
1929 /* Start Vpd interpolation from the max of the minimum powers */
1930 minPwrT4[i] = AH_MAX(pPwrL[0], pPwrR[0]);
1932 /* End Vpd interpolation from the min of the max powers */
1933 maxPwrT4[i] = AH_MIN(pPwrL[AR5416_PD_GAIN_ICEPTS - 1], pPwrR[AR5416_PD_GAIN_ICEPTS - 1]);
1934 HALASSERT(maxPwrT4[i] > minPwrT4[i]);
1936 /* Fill pier Vpds */
1937 ar5416FillVpdTable(minPwrT4[i], maxPwrT4[i], pPwrL, pVpdL, AR5416_PD_GAIN_ICEPTS, vpdTableL[i]);
1938 ar5416FillVpdTable(minPwrT4[i], maxPwrT4[i], pPwrR, pVpdR, AR5416_PD_GAIN_ICEPTS, vpdTableR[i]);
1940 /* Interpolate the final vpd */
1941 for (j = 0; j <= (maxPwrT4[i] - minPwrT4[i]) / 2; j++) {
1942 vpdTableI[i][j] = (uint8_t)(interpolate((uint16_t)FREQ2FBIN(centers.synth_center, IEEE80211_IS_CHAN_2GHZ(chan)),
1943 bChans[idxL], bChans[idxR], vpdTableL[i][j], vpdTableR[i][j]));
1947 *pMinCalPower = (int16_t)(minPwrT4[0] / 2);
1949 k = 0; /* index for the final table */
1950 for (i = 0; i < numXpdGains; i++) {
1951 if (i == (numXpdGains - 1)) {
1952 pPdGainBoundaries[i] = (uint16_t)(maxPwrT4[i] / 2);
1954 pPdGainBoundaries[i] = (uint16_t)((maxPwrT4[i] + minPwrT4[i+1]) / 4);
1957 pPdGainBoundaries[i] = (uint16_t)AH_MIN(AR5416_MAX_RATE_POWER, pPdGainBoundaries[i]);
1959 /* NB: only applies to owl 1.0 */
1960 if ((i == 0) && !AR_SREV_OWL_20_OR_LATER(ah) ) {
1962 * fix the gain delta, but get a delta that can be applied to min to
1963 * keep the upper power values accurate, don't think max needs to
1964 * be adjusted because should not be at that area of the table?
1966 minDelta = pPdGainBoundaries[0] - 23;
1967 pPdGainBoundaries[0] = 23;
1973 /* Find starting index for this pdGain */
1975 ss = 0; /* for the first pdGain, start from index 0 */
1977 /* need overlap entries extrapolated below. */
1978 ss = (int16_t)((pPdGainBoundaries[i-1] - (minPwrT4[i] / 2)) - tPdGainOverlap + 1 + minDelta);
1980 vpdStep = (int16_t)(vpdTableI[i][1] - vpdTableI[i][0]);
1981 vpdStep = (int16_t)((vpdStep < 1) ? 1 : vpdStep);
1983 *-ve ss indicates need to extrapolate data below for this pdGain
1985 while ((ss < 0) && (k < (AR5416_NUM_PDADC_VALUES - 1))) {
1986 tmpVal = (int16_t)(vpdTableI[i][0] + ss * vpdStep);
1987 pPDADCValues[k++] = (uint8_t)((tmpVal < 0) ? 0 : tmpVal);
1991 sizeCurrVpdTable = (uint8_t)((maxPwrT4[i] - minPwrT4[i]) / 2 +1);
1992 tgtIndex = (uint8_t)(pPdGainBoundaries[i] + tPdGainOverlap - (minPwrT4[i] / 2));
1993 maxIndex = (tgtIndex < sizeCurrVpdTable) ? tgtIndex : sizeCurrVpdTable;
1995 while ((ss < maxIndex) && (k < (AR5416_NUM_PDADC_VALUES - 1))) {
1996 pPDADCValues[k++] = vpdTableI[i][ss++];
1999 vpdStep = (int16_t)(vpdTableI[i][sizeCurrVpdTable - 1] - vpdTableI[i][sizeCurrVpdTable - 2]);
2000 vpdStep = (int16_t)((vpdStep < 1) ? 1 : vpdStep);
2002 * for last gain, pdGainBoundary == Pmax_t2, so will
2003 * have to extrapolate
2005 if (tgtIndex >= maxIndex) { /* need to extrapolate above */
2006 while ((ss <= tgtIndex) && (k < (AR5416_NUM_PDADC_VALUES - 1))) {
2007 tmpVal = (int16_t)((vpdTableI[i][sizeCurrVpdTable - 1] +
2008 (ss - maxIndex +1) * vpdStep));
2009 pPDADCValues[k++] = (uint8_t)((tmpVal > 255) ? 255 : tmpVal);
2012 } /* extrapolated above */
2013 } /* for all pdGainUsed */
2015 /* Fill out pdGainBoundaries - only up to 2 allowed here, but hardware allows up to 4 */
2016 while (i < AR5416_PD_GAINS_IN_MASK) {
2017 pPdGainBoundaries[i] = pPdGainBoundaries[i-1];
2021 while (k < AR5416_NUM_PDADC_VALUES) {
2022 pPDADCValues[k] = pPDADCValues[k-1];
2028 /**************************************************************
2029 * getLowerUppderIndex
2031 * Return indices surrounding the value in sorted integer lists.
2032 * Requirement: the input list must be monotonically increasing
2033 * and populated up to the list size
2034 * Returns: match is set if an index in the array matches exactly
2035 * or a the target is before or after the range of the array.
2038 getLowerUpperIndex(uint8_t target, uint8_t *pList, uint16_t listSize,
2039 uint16_t *indexL, uint16_t *indexR)
2044 * Check first and last elements for beyond ordered array cases.
2046 if (target <= pList[0]) {
2047 *indexL = *indexR = 0;
2050 if (target >= pList[listSize-1]) {
2051 *indexL = *indexR = (uint16_t)(listSize - 1);
2055 /* look for value being near or between 2 values in list */
2056 for (i = 0; i < listSize - 1; i++) {
2058 * If value is close to the current value of the list
2059 * then target is not between values, it is one of the values
2061 if (pList[i] == target) {
2062 *indexL = *indexR = i;
2066 * Look for value being between current value and next value
2067 * if so return these 2 values
2069 if (target < pList[i + 1]) {
2071 *indexR = (uint16_t)(i + 1);
2076 *indexL = *indexR = 0;
2080 /**************************************************************
2081 * ar5416FillVpdTable
2083 * Fill the Vpdlist for indices Pmax-Pmin
2084 * Note: pwrMin, pwrMax and Vpdlist are all in dBm * 4
2087 ar5416FillVpdTable(uint8_t pwrMin, uint8_t pwrMax, uint8_t *pPwrList,
2088 uint8_t *pVpdList, uint16_t numIntercepts, uint8_t *pRetVpdList)
2091 uint8_t currPwr = pwrMin;
2092 uint16_t idxL, idxR;
2094 HALASSERT(pwrMax > pwrMin);
2095 for (i = 0; i <= (pwrMax - pwrMin) / 2; i++) {
2096 getLowerUpperIndex(currPwr, pPwrList, numIntercepts,
2099 idxR = 1; /* extrapolate below */
2100 if (idxL == numIntercepts - 1)
2101 idxL = (uint16_t)(numIntercepts - 2); /* extrapolate above */
2102 if (pPwrList[idxL] == pPwrList[idxR])
2105 k = (uint16_t)( ((currPwr - pPwrList[idxL]) * pVpdList[idxR] + (pPwrList[idxR] - currPwr) * pVpdList[idxL]) /
2106 (pPwrList[idxR] - pPwrList[idxL]) );
2108 pRetVpdList[i] = (uint8_t)k;
2109 currPwr += 2; /* half dB steps */
2115 /**************************************************************************
2118 * Returns signed interpolated or the scaled up interpolated value
2121 interpolate(uint16_t target, uint16_t srcLeft, uint16_t srcRight,
2122 int16_t targetLeft, int16_t targetRight)
2126 if (srcRight == srcLeft) {
2129 rv = (int16_t)( ((target - srcLeft) * targetRight +
2130 (srcRight - target) * targetLeft) / (srcRight - srcLeft) );
2136 ar5416Set11nRegs(struct ath_hal *ah, const struct ieee80211_channel *chan)
2139 HAL_HT_MACMODE macmode; /* MAC - 20/40 mode */
2141 if (!IEEE80211_IS_CHAN_HT(chan))
2144 /* Enable 11n HT, 20 MHz */
2145 phymode = AR_PHY_FC_HT_EN | AR_PHY_FC_SHORT_GI_40
2146 | AR_PHY_FC_SINGLE_HT_LTF1 | AR_PHY_FC_WALSH;
2148 /* Configure baseband for dynamic 20/40 operation */
2149 if (IEEE80211_IS_CHAN_HT40(chan)) {
2150 phymode |= AR_PHY_FC_DYN2040_EN | AR_PHY_FC_SHORT_GI_40;
2152 /* Configure control (primary) channel at +-10MHz */
2153 if (IEEE80211_IS_CHAN_HT40U(chan))
2154 phymode |= AR_PHY_FC_DYN2040_PRI_CH;
2156 /* Configure 20/25 spacing */
2157 if (ht->ht_extprotspacing == HAL_HT_EXTPROTSPACING_25)
2158 phymode |= AR_PHY_FC_DYN2040_EXT_CH;
2160 macmode = HAL_HT_MACMODE_2040;
2162 macmode = HAL_HT_MACMODE_20;
2163 OS_REG_WRITE(ah, AR_PHY_TURBO, phymode);
2165 /* Configure MAC for 20/40 operation */
2166 ar5416Set11nMac2040(ah, macmode);
2168 /* global transmit timeout (25 TUs default)*/
2169 /* XXX - put this elsewhere??? */
2170 OS_REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S) ;
2172 /* carrier sense timeout */
2173 OS_REG_SET_BIT(ah, AR_GTTM, AR_GTTM_CST_USEC);
2174 OS_REG_WRITE(ah, AR_CST, 1 << AR_CST_TIMEOUT_LIMIT_S);
2178 ar5416GetChannelCenters(struct ath_hal *ah,
2179 const struct ieee80211_channel *chan, CHAN_CENTERS *centers)
2181 uint16_t freq = ath_hal_gethwchannel(ah, chan);
2183 centers->ctl_center = freq;
2184 centers->synth_center = freq;
2186 * In 20/40 phy mode, the center frequency is
2187 * "between" the control and extension channels.
2189 if (IEEE80211_IS_CHAN_HT40U(chan)) {
2190 centers->synth_center += HT40_CHANNEL_CENTER_SHIFT;
2191 centers->ext_center =
2192 centers->synth_center + HT40_CHANNEL_CENTER_SHIFT;
2193 } else if (IEEE80211_IS_CHAN_HT40D(chan)) {
2194 centers->synth_center -= HT40_CHANNEL_CENTER_SHIFT;
2195 centers->ext_center =
2196 centers->synth_center - HT40_CHANNEL_CENTER_SHIFT;
2198 centers->ext_center = freq;