Merge branch 'vendor/LIBARCHIVE'
[dragonfly.git] / sys / dev / netif / bge / if_bge.c
1 /*
2  * Copyright (c) 2001 Wind River Systems
3  * Copyright (c) 1997, 1998, 1999, 2001
4  *      Bill Paul <wpaul@windriver.com>.  All rights reserved.
5  *
6  * Redistribution and use in source and binary forms, with or without
7  * modification, are permitted provided that the following conditions
8  * are met:
9  * 1. Redistributions of source code must retain the above copyright
10  *    notice, this list of conditions and the following disclaimer.
11  * 2. Redistributions in binary form must reproduce the above copyright
12  *    notice, this list of conditions and the following disclaimer in the
13  *    documentation and/or other materials provided with the distribution.
14  * 3. All advertising materials mentioning features or use of this software
15  *    must display the following acknowledgement:
16  *      This product includes software developed by Bill Paul.
17  * 4. Neither the name of the author nor the names of any co-contributors
18  *    may be used to endorse or promote products derived from this software
19  *    without specific prior written permission.
20  *
21  * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
22  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24  * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
25  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
31  * THE POSSIBILITY OF SUCH DAMAGE.
32  *
33  * $FreeBSD: src/sys/dev/bge/if_bge.c,v 1.3.2.39 2005/07/03 03:41:18 silby Exp $
34  */
35
36 /*
37  * Broadcom BCM570x family gigabit ethernet driver for FreeBSD.
38  * 
39  * Written by Bill Paul <wpaul@windriver.com>
40  * Senior Engineer, Wind River Systems
41  */
42
43 /*
44  * The Broadcom BCM5700 is based on technology originally developed by
45  * Alteon Networks as part of the Tigon I and Tigon II gigabit ethernet
46  * MAC chips. The BCM5700, sometimes refered to as the Tigon III, has
47  * two on-board MIPS R4000 CPUs and can have as much as 16MB of external
48  * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo
49  * frames, highly configurable RX filtering, and 16 RX and TX queues
50  * (which, along with RX filter rules, can be used for QOS applications).
51  * Other features, such as TCP segmentation, may be available as part
52  * of value-added firmware updates. Unlike the Tigon I and Tigon II,
53  * firmware images can be stored in hardware and need not be compiled
54  * into the driver.
55  *
56  * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will
57  * function in a 32-bit/64-bit 33/66Mhz bus, or a 64-bit/133Mhz bus.
58  * 
59  * The BCM5701 is a single-chip solution incorporating both the BCM5700
60  * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5701
61  * does not support external SSRAM.
62  *
63  * Broadcom also produces a variation of the BCM5700 under the "Altima"
64  * brand name, which is functionally similar but lacks PCI-X support.
65  *
66  * Without external SSRAM, you can only have at most 4 TX rings,
67  * and the use of the mini RX ring is disabled. This seems to imply
68  * that these features are simply not available on the BCM5701. As a
69  * result, this driver does not implement any support for the mini RX
70  * ring.
71  */
72
73 #include "opt_polling.h"
74
75 #include <sys/param.h>
76 #include <sys/bus.h>
77 #include <sys/endian.h>
78 #include <sys/kernel.h>
79 #include <sys/ktr.h>
80 #include <sys/interrupt.h>
81 #include <sys/mbuf.h>
82 #include <sys/malloc.h>
83 #include <sys/queue.h>
84 #include <sys/rman.h>
85 #include <sys/serialize.h>
86 #include <sys/socket.h>
87 #include <sys/sockio.h>
88 #include <sys/sysctl.h>
89
90 #include <net/bpf.h>
91 #include <net/ethernet.h>
92 #include <net/if.h>
93 #include <net/if_arp.h>
94 #include <net/if_dl.h>
95 #include <net/if_media.h>
96 #include <net/if_types.h>
97 #include <net/ifq_var.h>
98 #include <net/vlan/if_vlan_var.h>
99 #include <net/vlan/if_vlan_ether.h>
100
101 #include <dev/netif/mii_layer/mii.h>
102 #include <dev/netif/mii_layer/miivar.h>
103 #include <dev/netif/mii_layer/brgphyreg.h>
104
105 #include <bus/pci/pcidevs.h>
106 #include <bus/pci/pcireg.h>
107 #include <bus/pci/pcivar.h>
108
109 #include <dev/netif/bge/if_bgereg.h>
110 #include <dev/netif/bge/if_bgevar.h>
111
112 /* "device miibus" required.  See GENERIC if you get errors here. */
113 #include "miibus_if.h"
114
115 #define BGE_CSUM_FEATURES       (CSUM_IP | CSUM_TCP)
116
117 static const struct bge_type {
118         uint16_t                bge_vid;
119         uint16_t                bge_did;
120         char                    *bge_name;
121 } bge_devs[] = {
122         { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C996,
123                 "3COM 3C996 Gigabit Ethernet" },
124
125         { PCI_VENDOR_ALTEON, PCI_PRODUCT_ALTEON_BCM5700,
126                 "Alteon BCM5700 Gigabit Ethernet" },
127         { PCI_VENDOR_ALTEON, PCI_PRODUCT_ALTEON_BCM5701,
128                 "Alteon BCM5701 Gigabit Ethernet" },
129
130         { PCI_VENDOR_ALTIMA, PCI_PRODUCT_ALTIMA_AC1000,
131                 "Altima AC1000 Gigabit Ethernet" },
132         { PCI_VENDOR_ALTIMA, PCI_PRODUCT_ALTIMA_AC1001,
133                 "Altima AC1002 Gigabit Ethernet" },
134         { PCI_VENDOR_ALTIMA, PCI_PRODUCT_ALTIMA_AC9100,
135                 "Altima AC9100 Gigabit Ethernet" },
136
137         { PCI_VENDOR_APPLE, PCI_PRODUCT_APPLE_BCM5701,
138                 "Apple BCM5701 Gigabit Ethernet" },
139
140         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5700,
141                 "Broadcom BCM5700 Gigabit Ethernet" },
142         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5701,
143                 "Broadcom BCM5701 Gigabit Ethernet" },
144         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5702,
145                 "Broadcom BCM5702 Gigabit Ethernet" },
146         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5702X,
147                 "Broadcom BCM5702X Gigabit Ethernet" },
148         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5702_ALT,
149                 "Broadcom BCM5702 Gigabit Ethernet" },
150         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5703,
151                 "Broadcom BCM5703 Gigabit Ethernet" },
152         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5703X,
153                 "Broadcom BCM5703X Gigabit Ethernet" },
154         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5703A3,
155                 "Broadcom BCM5703 Gigabit Ethernet" },
156         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5704C,
157                 "Broadcom BCM5704C Dual Gigabit Ethernet" },
158         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5704S,
159                 "Broadcom BCM5704S Dual Gigabit Ethernet" },
160         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5704S_ALT,
161                 "Broadcom BCM5704S Dual Gigabit Ethernet" },
162         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705,
163                 "Broadcom BCM5705 Gigabit Ethernet" },
164         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705F,
165                 "Broadcom BCM5705F Gigabit Ethernet" },
166         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705K,
167                 "Broadcom BCM5705K Gigabit Ethernet" },
168         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705M,
169                 "Broadcom BCM5705M Gigabit Ethernet" },
170         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705M_ALT,
171                 "Broadcom BCM5705M Gigabit Ethernet" },
172         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5714,
173                 "Broadcom BCM5714C Gigabit Ethernet" },
174         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5714S,
175                 "Broadcom BCM5714S Gigabit Ethernet" },
176         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5715,
177                 "Broadcom BCM5715 Gigabit Ethernet" },
178         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5715S,
179                 "Broadcom BCM5715S Gigabit Ethernet" },
180         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5720,
181                 "Broadcom BCM5720 Gigabit Ethernet" },
182         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5721,
183                 "Broadcom BCM5721 Gigabit Ethernet" },
184         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5722,
185                 "Broadcom BCM5722 Gigabit Ethernet" },
186         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5723,
187                 "Broadcom BCM5723 Gigabit Ethernet" },
188         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5750,
189                 "Broadcom BCM5750 Gigabit Ethernet" },
190         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5750M,
191                 "Broadcom BCM5750M Gigabit Ethernet" },
192         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5751,
193                 "Broadcom BCM5751 Gigabit Ethernet" },
194         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5751F,
195                 "Broadcom BCM5751F Gigabit Ethernet" },
196         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5751M,
197                 "Broadcom BCM5751M Gigabit Ethernet" },
198         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5752,
199                 "Broadcom BCM5752 Gigabit Ethernet" },
200         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5752M,
201                 "Broadcom BCM5752M Gigabit Ethernet" },
202         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5753,
203                 "Broadcom BCM5753 Gigabit Ethernet" },
204         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5753F,
205                 "Broadcom BCM5753F Gigabit Ethernet" },
206         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5753M,
207                 "Broadcom BCM5753M Gigabit Ethernet" },
208         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5754,
209                 "Broadcom BCM5754 Gigabit Ethernet" },
210         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5754M,
211                 "Broadcom BCM5754M Gigabit Ethernet" },
212         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5755,
213                 "Broadcom BCM5755 Gigabit Ethernet" },
214         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5755M,
215                 "Broadcom BCM5755M Gigabit Ethernet" },
216         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5756,
217                 "Broadcom BCM5756 Gigabit Ethernet" },
218         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5761,
219                 "Broadcom BCM5761 Gigabit Ethernet" },
220         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5761E,
221                 "Broadcom BCM5761E Gigabit Ethernet" },
222         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5761S,
223                 "Broadcom BCM5761S Gigabit Ethernet" },
224         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5761SE,
225                 "Broadcom BCM5761SE Gigabit Ethernet" },
226         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5764,
227                 "Broadcom BCM5764 Gigabit Ethernet" },
228         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5780,
229                 "Broadcom BCM5780 Gigabit Ethernet" },
230         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5780S,
231                 "Broadcom BCM5780S Gigabit Ethernet" },
232         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5781,
233                 "Broadcom BCM5781 Gigabit Ethernet" },
234         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5782,
235                 "Broadcom BCM5782 Gigabit Ethernet" },
236         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5784,
237                 "Broadcom BCM5784 Gigabit Ethernet" },
238         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5785F,
239                 "Broadcom BCM5785F Gigabit Ethernet" },
240         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5785G,
241                 "Broadcom BCM5785G Gigabit Ethernet" },
242         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5786,
243                 "Broadcom BCM5786 Gigabit Ethernet" },
244         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5787,
245                 "Broadcom BCM5787 Gigabit Ethernet" },
246         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5787F,
247                 "Broadcom BCM5787F Gigabit Ethernet" },
248         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5787M,
249                 "Broadcom BCM5787M Gigabit Ethernet" },
250         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5788,
251                 "Broadcom BCM5788 Gigabit Ethernet" },
252         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5789,
253                 "Broadcom BCM5789 Gigabit Ethernet" },
254         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5901,
255                 "Broadcom BCM5901 Fast Ethernet" },
256         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5901A2,
257                 "Broadcom BCM5901A2 Fast Ethernet" },
258         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5903M,
259                 "Broadcom BCM5903M Fast Ethernet" },
260         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5906,
261                 "Broadcom BCM5906 Fast Ethernet"},
262         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5906M,
263                 "Broadcom BCM5906M Fast Ethernet"},
264         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57760,
265                 "Broadcom BCM57760 Gigabit Ethernet"},
266         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57780,
267                 "Broadcom BCM57780 Gigabit Ethernet"},
268         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57788,
269                 "Broadcom BCM57788 Gigabit Ethernet"},
270         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57790,
271                 "Broadcom BCM57790 Gigabit Ethernet"},
272         { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK_9DX1,
273                 "SysKonnect Gigabit Ethernet" },
274
275         { 0, 0, NULL }
276 };
277
278 #define BGE_IS_JUMBO_CAPABLE(sc)        ((sc)->bge_flags & BGE_FLAG_JUMBO)
279 #define BGE_IS_5700_FAMILY(sc)          ((sc)->bge_flags & BGE_FLAG_5700_FAMILY)
280 #define BGE_IS_5705_PLUS(sc)            ((sc)->bge_flags & BGE_FLAG_5705_PLUS)
281 #define BGE_IS_5714_FAMILY(sc)          ((sc)->bge_flags & BGE_FLAG_5714_FAMILY)
282 #define BGE_IS_575X_PLUS(sc)            ((sc)->bge_flags & BGE_FLAG_575X_PLUS)
283 #define BGE_IS_5755_PLUS(sc)            ((sc)->bge_flags & BGE_FLAG_5755_PLUS)
284 #define BGE_IS_5788(sc)                 ((sc)->bge_flags & BGE_FLAG_5788)
285
286 #define BGE_IS_CRIPPLED(sc)             \
287         (BGE_IS_5788((sc)) || (sc)->bge_asicrev == BGE_ASICREV_BCM5700)
288
289 typedef int     (*bge_eaddr_fcn_t)(struct bge_softc *, uint8_t[]);
290
291 static int      bge_probe(device_t);
292 static int      bge_attach(device_t);
293 static int      bge_detach(device_t);
294 static void     bge_txeof(struct bge_softc *, uint16_t);
295 static void     bge_rxeof(struct bge_softc *, uint16_t);
296
297 static void     bge_tick(void *);
298 static void     bge_stats_update(struct bge_softc *);
299 static void     bge_stats_update_regs(struct bge_softc *);
300 static struct mbuf *
301                 bge_defrag_shortdma(struct mbuf *);
302 static int      bge_encap(struct bge_softc *, struct mbuf **, uint32_t *);
303
304 #ifdef DEVICE_POLLING
305 static void     bge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count);
306 #endif
307 static void     bge_intr(void *);
308 static void     bge_intr_status_tag(void *);
309 static void     bge_enable_intr(struct bge_softc *);
310 static void     bge_disable_intr(struct bge_softc *);
311 static void     bge_start(struct ifnet *);
312 static int      bge_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
313 static void     bge_init(void *);
314 static void     bge_stop(struct bge_softc *);
315 static void     bge_watchdog(struct ifnet *);
316 static void     bge_shutdown(device_t);
317 static int      bge_suspend(device_t);
318 static int      bge_resume(device_t);
319 static int      bge_ifmedia_upd(struct ifnet *);
320 static void     bge_ifmedia_sts(struct ifnet *, struct ifmediareq *);
321
322 static uint8_t  bge_nvram_getbyte(struct bge_softc *, int, uint8_t *);
323 static int      bge_read_nvram(struct bge_softc *, caddr_t, int, int);
324
325 static uint8_t  bge_eeprom_getbyte(struct bge_softc *, uint32_t, uint8_t *);
326 static int      bge_read_eeprom(struct bge_softc *, caddr_t, uint32_t, size_t);
327
328 static void     bge_setmulti(struct bge_softc *);
329 static void     bge_setpromisc(struct bge_softc *);
330
331 static int      bge_alloc_jumbo_mem(struct bge_softc *);
332 static void     bge_free_jumbo_mem(struct bge_softc *);
333 static struct bge_jslot
334                 *bge_jalloc(struct bge_softc *);
335 static void     bge_jfree(void *);
336 static void     bge_jref(void *);
337 static int      bge_newbuf_std(struct bge_softc *, int, int);
338 static int      bge_newbuf_jumbo(struct bge_softc *, int, int);
339 static void     bge_setup_rxdesc_std(struct bge_softc *, int);
340 static void     bge_setup_rxdesc_jumbo(struct bge_softc *, int);
341 static int      bge_init_rx_ring_std(struct bge_softc *);
342 static void     bge_free_rx_ring_std(struct bge_softc *);
343 static int      bge_init_rx_ring_jumbo(struct bge_softc *);
344 static void     bge_free_rx_ring_jumbo(struct bge_softc *);
345 static void     bge_free_tx_ring(struct bge_softc *);
346 static int      bge_init_tx_ring(struct bge_softc *);
347
348 static int      bge_chipinit(struct bge_softc *);
349 static int      bge_blockinit(struct bge_softc *);
350 static void     bge_stop_block(struct bge_softc *, bus_size_t, uint32_t);
351
352 static uint32_t bge_readmem_ind(struct bge_softc *, uint32_t);
353 static void     bge_writemem_ind(struct bge_softc *, uint32_t, uint32_t);
354 #ifdef notdef
355 static uint32_t bge_readreg_ind(struct bge_softc *, uint32_t);
356 #endif
357 static void     bge_writereg_ind(struct bge_softc *, uint32_t, uint32_t);
358 static void     bge_writemem_direct(struct bge_softc *, uint32_t, uint32_t);
359 static void     bge_writembx(struct bge_softc *, int, int);
360
361 static int      bge_miibus_readreg(device_t, int, int);
362 static int      bge_miibus_writereg(device_t, int, int, int);
363 static void     bge_miibus_statchg(device_t);
364 static void     bge_bcm5700_link_upd(struct bge_softc *, uint32_t);
365 static void     bge_tbi_link_upd(struct bge_softc *, uint32_t);
366 static void     bge_copper_link_upd(struct bge_softc *, uint32_t);
367 static void     bge_autopoll_link_upd(struct bge_softc *, uint32_t);
368 static void     bge_link_poll(struct bge_softc *);
369
370 static void     bge_reset(struct bge_softc *);
371
372 static int      bge_dma_alloc(struct bge_softc *);
373 static void     bge_dma_free(struct bge_softc *);
374 static int      bge_dma_block_alloc(struct bge_softc *, bus_size_t,
375                                     bus_dma_tag_t *, bus_dmamap_t *,
376                                     void **, bus_addr_t *);
377 static void     bge_dma_block_free(bus_dma_tag_t, bus_dmamap_t, void *);
378
379 static int      bge_get_eaddr_mem(struct bge_softc *, uint8_t[]);
380 static int      bge_get_eaddr_nvram(struct bge_softc *, uint8_t[]);
381 static int      bge_get_eaddr_eeprom(struct bge_softc *, uint8_t[]);
382 static int      bge_get_eaddr(struct bge_softc *, uint8_t[]);
383
384 static void     bge_coal_change(struct bge_softc *);
385 static int      bge_sysctl_rx_coal_ticks(SYSCTL_HANDLER_ARGS);
386 static int      bge_sysctl_tx_coal_ticks(SYSCTL_HANDLER_ARGS);
387 static int      bge_sysctl_rx_coal_bds(SYSCTL_HANDLER_ARGS);
388 static int      bge_sysctl_tx_coal_bds(SYSCTL_HANDLER_ARGS);
389 static int      bge_sysctl_rx_coal_ticks_int(SYSCTL_HANDLER_ARGS);
390 static int      bge_sysctl_tx_coal_ticks_int(SYSCTL_HANDLER_ARGS);
391 static int      bge_sysctl_rx_coal_bds_int(SYSCTL_HANDLER_ARGS);
392 static int      bge_sysctl_tx_coal_bds_int(SYSCTL_HANDLER_ARGS);
393 static int      bge_sysctl_coal_chg(SYSCTL_HANDLER_ARGS, uint32_t *,
394                     int, int, uint32_t);
395
396 /*
397  * Set following tunable to 1 for some IBM blade servers with the DNLK
398  * switch module. Auto negotiation is broken for those configurations.
399  */
400 static int      bge_fake_autoneg = 0;
401 TUNABLE_INT("hw.bge.fake_autoneg", &bge_fake_autoneg);
402
403 #if !defined(KTR_IF_BGE)
404 #define KTR_IF_BGE      KTR_ALL
405 #endif
406 KTR_INFO_MASTER(if_bge);
407 KTR_INFO(KTR_IF_BGE, if_bge, intr, 0, "intr");
408 KTR_INFO(KTR_IF_BGE, if_bge, rx_pkt, 1, "rx_pkt");
409 KTR_INFO(KTR_IF_BGE, if_bge, tx_pkt, 2, "tx_pkt");
410 #define logif(name)     KTR_LOG(if_bge_ ## name)
411
412 static device_method_t bge_methods[] = {
413         /* Device interface */
414         DEVMETHOD(device_probe,         bge_probe),
415         DEVMETHOD(device_attach,        bge_attach),
416         DEVMETHOD(device_detach,        bge_detach),
417         DEVMETHOD(device_shutdown,      bge_shutdown),
418         DEVMETHOD(device_suspend,       bge_suspend),
419         DEVMETHOD(device_resume,        bge_resume),
420
421         /* bus interface */
422         DEVMETHOD(bus_print_child,      bus_generic_print_child),
423         DEVMETHOD(bus_driver_added,     bus_generic_driver_added),
424
425         /* MII interface */
426         DEVMETHOD(miibus_readreg,       bge_miibus_readreg),
427         DEVMETHOD(miibus_writereg,      bge_miibus_writereg),
428         DEVMETHOD(miibus_statchg,       bge_miibus_statchg),
429
430         { 0, 0 }
431 };
432
433 static DEFINE_CLASS_0(bge, bge_driver, bge_methods, sizeof(struct bge_softc));
434 static devclass_t bge_devclass;
435
436 DECLARE_DUMMY_MODULE(if_bge);
437 DRIVER_MODULE(if_bge, pci, bge_driver, bge_devclass, NULL, NULL);
438 DRIVER_MODULE(miibus, bge, miibus_driver, miibus_devclass, NULL, NULL);
439
440 static uint32_t
441 bge_readmem_ind(struct bge_softc *sc, uint32_t off)
442 {
443         device_t dev = sc->bge_dev;
444         uint32_t val;
445
446         if (sc->bge_asicrev == BGE_ASICREV_BCM5906 &&
447             off >= BGE_STATS_BLOCK && off < BGE_SEND_RING_1_TO_4)
448                 return 0;
449
450         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
451         val = pci_read_config(dev, BGE_PCI_MEMWIN_DATA, 4);
452         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4);
453         return (val);
454 }
455
456 static void
457 bge_writemem_ind(struct bge_softc *sc, uint32_t off, uint32_t val)
458 {
459         device_t dev = sc->bge_dev;
460
461         if (sc->bge_asicrev == BGE_ASICREV_BCM5906 &&
462             off >= BGE_STATS_BLOCK && off < BGE_SEND_RING_1_TO_4)
463                 return;
464
465         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
466         pci_write_config(dev, BGE_PCI_MEMWIN_DATA, val, 4);
467         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4);
468 }
469
470 #ifdef notdef
471 static uint32_t
472 bge_readreg_ind(struct bge_softc *sc, uin32_t off)
473 {
474         device_t dev = sc->bge_dev;
475
476         pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4);
477         return(pci_read_config(dev, BGE_PCI_REG_DATA, 4));
478 }
479 #endif
480
481 static void
482 bge_writereg_ind(struct bge_softc *sc, uint32_t off, uint32_t val)
483 {
484         device_t dev = sc->bge_dev;
485
486         pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4);
487         pci_write_config(dev, BGE_PCI_REG_DATA, val, 4);
488 }
489
490 static void
491 bge_writemem_direct(struct bge_softc *sc, uint32_t off, uint32_t val)
492 {
493         CSR_WRITE_4(sc, off, val);
494 }
495
496 static void
497 bge_writembx(struct bge_softc *sc, int off, int val)
498 {
499         if (sc->bge_asicrev == BGE_ASICREV_BCM5906)
500                 off += BGE_LPMBX_IRQ0_HI - BGE_MBX_IRQ0_HI;
501
502         CSR_WRITE_4(sc, off, val);
503         if (sc->bge_mbox_reorder)
504                 CSR_READ_4(sc, off);
505 }
506
507 static uint8_t
508 bge_nvram_getbyte(struct bge_softc *sc, int addr, uint8_t *dest)
509 {
510         uint32_t access, byte = 0;
511         int i;
512
513         /* Lock. */
514         CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1);
515         for (i = 0; i < 8000; i++) {
516                 if (CSR_READ_4(sc, BGE_NVRAM_SWARB) & BGE_NVRAMSWARB_GNT1)
517                         break;
518                 DELAY(20);
519         }
520         if (i == 8000)
521                 return (1);
522
523         /* Enable access. */
524         access = CSR_READ_4(sc, BGE_NVRAM_ACCESS);
525         CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access | BGE_NVRAMACC_ENABLE);
526
527         CSR_WRITE_4(sc, BGE_NVRAM_ADDR, addr & 0xfffffffc);
528         CSR_WRITE_4(sc, BGE_NVRAM_CMD, BGE_NVRAM_READCMD);
529         for (i = 0; i < BGE_TIMEOUT * 10; i++) {
530                 DELAY(10);
531                 if (CSR_READ_4(sc, BGE_NVRAM_CMD) & BGE_NVRAMCMD_DONE) {
532                         DELAY(10);
533                         break;
534                 }
535         }
536
537         if (i == BGE_TIMEOUT * 10) {
538                 if_printf(&sc->arpcom.ac_if, "nvram read timed out\n");
539                 return (1);
540         }
541
542         /* Get result. */
543         byte = CSR_READ_4(sc, BGE_NVRAM_RDDATA);
544
545         *dest = (bswap32(byte) >> ((addr % 4) * 8)) & 0xFF;
546
547         /* Disable access. */
548         CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access);
549
550         /* Unlock. */
551         CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_CLR1);
552         CSR_READ_4(sc, BGE_NVRAM_SWARB);
553
554         return (0);
555 }
556
557 /*
558  * Read a sequence of bytes from NVRAM.
559  */
560 static int
561 bge_read_nvram(struct bge_softc *sc, caddr_t dest, int off, int cnt)
562 {
563         int err = 0, i;
564         uint8_t byte = 0;
565
566         if (sc->bge_asicrev != BGE_ASICREV_BCM5906)
567                 return (1);
568
569         for (i = 0; i < cnt; i++) {
570                 err = bge_nvram_getbyte(sc, off + i, &byte);
571                 if (err)
572                         break;
573                 *(dest + i) = byte;
574         }
575
576         return (err ? 1 : 0);
577 }
578
579 /*
580  * Read a byte of data stored in the EEPROM at address 'addr.' The
581  * BCM570x supports both the traditional bitbang interface and an
582  * auto access interface for reading the EEPROM. We use the auto
583  * access method.
584  */
585 static uint8_t
586 bge_eeprom_getbyte(struct bge_softc *sc, uint32_t addr, uint8_t *dest)
587 {
588         int i;
589         uint32_t byte = 0;
590
591         /*
592          * Enable use of auto EEPROM access so we can avoid
593          * having to use the bitbang method.
594          */
595         BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM);
596
597         /* Reset the EEPROM, load the clock period. */
598         CSR_WRITE_4(sc, BGE_EE_ADDR,
599             BGE_EEADDR_RESET|BGE_EEHALFCLK(BGE_HALFCLK_384SCL));
600         DELAY(20);
601
602         /* Issue the read EEPROM command. */
603         CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr);
604
605         /* Wait for completion */
606         for(i = 0; i < BGE_TIMEOUT * 10; i++) {
607                 DELAY(10);
608                 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE)
609                         break;
610         }
611
612         if (i == BGE_TIMEOUT) {
613                 if_printf(&sc->arpcom.ac_if, "eeprom read timed out\n");
614                 return(1);
615         }
616
617         /* Get result. */
618         byte = CSR_READ_4(sc, BGE_EE_DATA);
619
620         *dest = (byte >> ((addr % 4) * 8)) & 0xFF;
621
622         return(0);
623 }
624
625 /*
626  * Read a sequence of bytes from the EEPROM.
627  */
628 static int
629 bge_read_eeprom(struct bge_softc *sc, caddr_t dest, uint32_t off, size_t len)
630 {
631         size_t i;
632         int err;
633         uint8_t byte;
634
635         for (byte = 0, err = 0, i = 0; i < len; i++) {
636                 err = bge_eeprom_getbyte(sc, off + i, &byte);
637                 if (err)
638                         break;
639                 *(dest + i) = byte;
640         }
641
642         return(err ? 1 : 0);
643 }
644
645 static int
646 bge_miibus_readreg(device_t dev, int phy, int reg)
647 {
648         struct bge_softc *sc = device_get_softc(dev);
649         uint32_t val;
650         int i;
651
652         KASSERT(phy == sc->bge_phyno,
653             ("invalid phyno %d, should be %d", phy, sc->bge_phyno));
654
655         /* Clear the autopoll bit if set, otherwise may trigger PCI errors. */
656         if (sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) {
657                 CSR_WRITE_4(sc, BGE_MI_MODE,
658                     sc->bge_mi_mode & ~BGE_MIMODE_AUTOPOLL);
659                 DELAY(80);
660         }
661
662         CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ | BGE_MICOMM_BUSY |
663             BGE_MIPHY(phy) | BGE_MIREG(reg));
664
665         /* Poll for the PHY register access to complete. */
666         for (i = 0; i < BGE_TIMEOUT; i++) {
667                 DELAY(10);
668                 val = CSR_READ_4(sc, BGE_MI_COMM);
669                 if ((val & BGE_MICOMM_BUSY) == 0) {
670                         DELAY(5);
671                         val = CSR_READ_4(sc, BGE_MI_COMM);
672                         break;
673                 }
674         }
675         if (i == BGE_TIMEOUT) {
676                 if_printf(&sc->arpcom.ac_if, "PHY read timed out "
677                     "(phy %d, reg %d, val 0x%08x)\n", phy, reg, val);
678                 val = 0;
679         }
680
681         /* Restore the autopoll bit if necessary. */
682         if (sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) {
683                 CSR_WRITE_4(sc, BGE_MI_MODE, sc->bge_mi_mode);
684                 DELAY(80);
685         }
686
687         if (val & BGE_MICOMM_READFAIL)
688                 return 0;
689
690         return (val & 0xFFFF);
691 }
692
693 static int
694 bge_miibus_writereg(device_t dev, int phy, int reg, int val)
695 {
696         struct bge_softc *sc = device_get_softc(dev);
697         int i;
698
699         KASSERT(phy == sc->bge_phyno,
700             ("invalid phyno %d, should be %d", phy, sc->bge_phyno));
701
702         if (sc->bge_asicrev == BGE_ASICREV_BCM5906 &&
703             (reg == BRGPHY_MII_1000CTL || reg == BRGPHY_MII_AUXCTL))
704                return 0;
705
706         /* Clear the autopoll bit if set, otherwise may trigger PCI errors. */
707         if (sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) {
708                 CSR_WRITE_4(sc, BGE_MI_MODE,
709                     sc->bge_mi_mode & ~BGE_MIMODE_AUTOPOLL);
710                 DELAY(80);
711         }
712
713         CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE | BGE_MICOMM_BUSY |
714             BGE_MIPHY(phy) | BGE_MIREG(reg) | val);
715
716         for (i = 0; i < BGE_TIMEOUT; i++) {
717                 DELAY(10);
718                 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY)) {
719                         DELAY(5);
720                         CSR_READ_4(sc, BGE_MI_COMM); /* dummy read */
721                         break;
722                 }
723         }
724         if (i == BGE_TIMEOUT) {
725                 if_printf(&sc->arpcom.ac_if, "PHY write timed out "
726                     "(phy %d, reg %d, val %d)\n", phy, reg, val);
727         }
728
729         /* Restore the autopoll bit if necessary. */
730         if (sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) {
731                 CSR_WRITE_4(sc, BGE_MI_MODE, sc->bge_mi_mode);
732                 DELAY(80);
733         }
734
735         return 0;
736 }
737
738 static void
739 bge_miibus_statchg(device_t dev)
740 {
741         struct bge_softc *sc;
742         struct mii_data *mii;
743
744         sc = device_get_softc(dev);
745         mii = device_get_softc(sc->bge_miibus);
746
747         if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
748             (IFM_ACTIVE | IFM_AVALID)) {
749                 switch (IFM_SUBTYPE(mii->mii_media_active)) {
750                 case IFM_10_T:
751                 case IFM_100_TX:
752                         sc->bge_link = 1;
753                         break;
754                 case IFM_1000_T:
755                 case IFM_1000_SX:
756                 case IFM_2500_SX:
757                         if (sc->bge_asicrev != BGE_ASICREV_BCM5906)
758                                 sc->bge_link = 1;
759                         else
760                                 sc->bge_link = 0;
761                         break;
762                 default:
763                         sc->bge_link = 0;
764                         break;
765                 }
766         } else {
767                 sc->bge_link = 0;
768         }
769         if (sc->bge_link == 0)
770                 return;
771
772         BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_PORTMODE);
773         if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T ||
774             IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) {
775                 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_GMII);
776         } else {
777                 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_MII);
778         }
779
780         if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
781                 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX);
782         } else {
783                 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX);
784         }
785 }
786
787 /*
788  * Memory management for jumbo frames.
789  */
790 static int
791 bge_alloc_jumbo_mem(struct bge_softc *sc)
792 {
793         struct ifnet *ifp = &sc->arpcom.ac_if;
794         struct bge_jslot *entry;
795         uint8_t *ptr;
796         bus_addr_t paddr;
797         int i, error;
798
799         /*
800          * Create tag for jumbo mbufs.
801          * This is really a bit of a kludge. We allocate a special
802          * jumbo buffer pool which (thanks to the way our DMA
803          * memory allocation works) will consist of contiguous
804          * pages. This means that even though a jumbo buffer might
805          * be larger than a page size, we don't really need to
806          * map it into more than one DMA segment. However, the
807          * default mbuf tag will result in multi-segment mappings,
808          * so we have to create a special jumbo mbuf tag that
809          * lets us get away with mapping the jumbo buffers as
810          * a single segment. I think eventually the driver should
811          * be changed so that it uses ordinary mbufs and cluster
812          * buffers, i.e. jumbo frames can span multiple DMA
813          * descriptors. But that's a project for another day.
814          */
815
816         /*
817          * Create DMA stuffs for jumbo RX ring.
818          */
819         error = bge_dma_block_alloc(sc, BGE_JUMBO_RX_RING_SZ,
820                                     &sc->bge_cdata.bge_rx_jumbo_ring_tag,
821                                     &sc->bge_cdata.bge_rx_jumbo_ring_map,
822                                     (void *)&sc->bge_ldata.bge_rx_jumbo_ring,
823                                     &sc->bge_ldata.bge_rx_jumbo_ring_paddr);
824         if (error) {
825                 if_printf(ifp, "could not create jumbo RX ring\n");
826                 return error;
827         }
828
829         /*
830          * Create DMA stuffs for jumbo buffer block.
831          */
832         error = bge_dma_block_alloc(sc, BGE_JMEM,
833                                     &sc->bge_cdata.bge_jumbo_tag,
834                                     &sc->bge_cdata.bge_jumbo_map,
835                                     (void **)&sc->bge_ldata.bge_jumbo_buf,
836                                     &paddr);
837         if (error) {
838                 if_printf(ifp, "could not create jumbo buffer\n");
839                 return error;
840         }
841
842         SLIST_INIT(&sc->bge_jfree_listhead);
843
844         /*
845          * Now divide it up into 9K pieces and save the addresses
846          * in an array. Note that we play an evil trick here by using
847          * the first few bytes in the buffer to hold the the address
848          * of the softc structure for this interface. This is because
849          * bge_jfree() needs it, but it is called by the mbuf management
850          * code which will not pass it to us explicitly.
851          */
852         for (i = 0, ptr = sc->bge_ldata.bge_jumbo_buf; i < BGE_JSLOTS; i++) {
853                 entry = &sc->bge_cdata.bge_jslots[i];
854                 entry->bge_sc = sc;
855                 entry->bge_buf = ptr;
856                 entry->bge_paddr = paddr;
857                 entry->bge_inuse = 0;
858                 entry->bge_slot = i;
859                 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, entry, jslot_link);
860
861                 ptr += BGE_JLEN;
862                 paddr += BGE_JLEN;
863         }
864         return 0;
865 }
866
867 static void
868 bge_free_jumbo_mem(struct bge_softc *sc)
869 {
870         /* Destroy jumbo RX ring. */
871         bge_dma_block_free(sc->bge_cdata.bge_rx_jumbo_ring_tag,
872                            sc->bge_cdata.bge_rx_jumbo_ring_map,
873                            sc->bge_ldata.bge_rx_jumbo_ring);
874
875         /* Destroy jumbo buffer block. */
876         bge_dma_block_free(sc->bge_cdata.bge_jumbo_tag,
877                            sc->bge_cdata.bge_jumbo_map,
878                            sc->bge_ldata.bge_jumbo_buf);
879 }
880
881 /*
882  * Allocate a jumbo buffer.
883  */
884 static struct bge_jslot *
885 bge_jalloc(struct bge_softc *sc)
886 {
887         struct bge_jslot *entry;
888
889         lwkt_serialize_enter(&sc->bge_jslot_serializer);
890         entry = SLIST_FIRST(&sc->bge_jfree_listhead);
891         if (entry) {
892                 SLIST_REMOVE_HEAD(&sc->bge_jfree_listhead, jslot_link);
893                 entry->bge_inuse = 1;
894         } else {
895                 if_printf(&sc->arpcom.ac_if, "no free jumbo buffers\n");
896         }
897         lwkt_serialize_exit(&sc->bge_jslot_serializer);
898         return(entry);
899 }
900
901 /*
902  * Adjust usage count on a jumbo buffer.
903  */
904 static void
905 bge_jref(void *arg)
906 {
907         struct bge_jslot *entry = (struct bge_jslot *)arg;
908         struct bge_softc *sc = entry->bge_sc;
909
910         if (sc == NULL)
911                 panic("bge_jref: can't find softc pointer!");
912
913         if (&sc->bge_cdata.bge_jslots[entry->bge_slot] != entry) {
914                 panic("bge_jref: asked to reference buffer "
915                     "that we don't manage!");
916         } else if (entry->bge_inuse == 0) {
917                 panic("bge_jref: buffer already free!");
918         } else {
919                 atomic_add_int(&entry->bge_inuse, 1);
920         }
921 }
922
923 /*
924  * Release a jumbo buffer.
925  */
926 static void
927 bge_jfree(void *arg)
928 {
929         struct bge_jslot *entry = (struct bge_jslot *)arg;
930         struct bge_softc *sc = entry->bge_sc;
931
932         if (sc == NULL)
933                 panic("bge_jfree: can't find softc pointer!");
934
935         if (&sc->bge_cdata.bge_jslots[entry->bge_slot] != entry) {
936                 panic("bge_jfree: asked to free buffer that we don't manage!");
937         } else if (entry->bge_inuse == 0) {
938                 panic("bge_jfree: buffer already free!");
939         } else {
940                 /*
941                  * Possible MP race to 0, use the serializer.  The atomic insn
942                  * is still needed for races against bge_jref().
943                  */
944                 lwkt_serialize_enter(&sc->bge_jslot_serializer);
945                 atomic_subtract_int(&entry->bge_inuse, 1);
946                 if (entry->bge_inuse == 0) {
947                         SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, 
948                                           entry, jslot_link);
949                 }
950                 lwkt_serialize_exit(&sc->bge_jslot_serializer);
951         }
952 }
953
954
955 /*
956  * Intialize a standard receive ring descriptor.
957  */
958 static int
959 bge_newbuf_std(struct bge_softc *sc, int i, int init)
960 {
961         struct mbuf *m_new = NULL;
962         bus_dma_segment_t seg;
963         bus_dmamap_t map;
964         int error, nsegs;
965
966         m_new = m_getcl(init ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR);
967         if (m_new == NULL)
968                 return ENOBUFS;
969         m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
970
971         if ((sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) == 0)
972                 m_adj(m_new, ETHER_ALIGN);
973
974         error = bus_dmamap_load_mbuf_segment(sc->bge_cdata.bge_rx_mtag,
975                         sc->bge_cdata.bge_rx_tmpmap, m_new,
976                         &seg, 1, &nsegs, BUS_DMA_NOWAIT);
977         if (error) {
978                 m_freem(m_new);
979                 return error;
980         }
981
982         if (!init) {
983                 bus_dmamap_sync(sc->bge_cdata.bge_rx_mtag,
984                                 sc->bge_cdata.bge_rx_std_dmamap[i],
985                                 BUS_DMASYNC_POSTREAD);
986                 bus_dmamap_unload(sc->bge_cdata.bge_rx_mtag,
987                         sc->bge_cdata.bge_rx_std_dmamap[i]);
988         }
989
990         map = sc->bge_cdata.bge_rx_tmpmap;
991         sc->bge_cdata.bge_rx_tmpmap = sc->bge_cdata.bge_rx_std_dmamap[i];
992         sc->bge_cdata.bge_rx_std_dmamap[i] = map;
993
994         sc->bge_cdata.bge_rx_std_chain[i].bge_mbuf = m_new;
995         sc->bge_cdata.bge_rx_std_chain[i].bge_paddr = seg.ds_addr;
996
997         bge_setup_rxdesc_std(sc, i);
998         return 0;
999 }
1000
1001 static void
1002 bge_setup_rxdesc_std(struct bge_softc *sc, int i)
1003 {
1004         struct bge_rxchain *rc;
1005         struct bge_rx_bd *r;
1006
1007         rc = &sc->bge_cdata.bge_rx_std_chain[i];
1008         r = &sc->bge_ldata.bge_rx_std_ring[i];
1009
1010         r->bge_addr.bge_addr_lo = BGE_ADDR_LO(rc->bge_paddr);
1011         r->bge_addr.bge_addr_hi = BGE_ADDR_HI(rc->bge_paddr);
1012         r->bge_len = rc->bge_mbuf->m_len;
1013         r->bge_idx = i;
1014         r->bge_flags = BGE_RXBDFLAG_END;
1015 }
1016
1017 /*
1018  * Initialize a jumbo receive ring descriptor. This allocates
1019  * a jumbo buffer from the pool managed internally by the driver.
1020  */
1021 static int
1022 bge_newbuf_jumbo(struct bge_softc *sc, int i, int init)
1023 {
1024         struct mbuf *m_new = NULL;
1025         struct bge_jslot *buf;
1026         bus_addr_t paddr;
1027
1028         /* Allocate the mbuf. */
1029         MGETHDR(m_new, init ? MB_WAIT : MB_DONTWAIT, MT_DATA);
1030         if (m_new == NULL)
1031                 return ENOBUFS;
1032
1033         /* Allocate the jumbo buffer */
1034         buf = bge_jalloc(sc);
1035         if (buf == NULL) {
1036                 m_freem(m_new);
1037                 return ENOBUFS;
1038         }
1039
1040         /* Attach the buffer to the mbuf. */
1041         m_new->m_ext.ext_arg = buf;
1042         m_new->m_ext.ext_buf = buf->bge_buf;
1043         m_new->m_ext.ext_free = bge_jfree;
1044         m_new->m_ext.ext_ref = bge_jref;
1045         m_new->m_ext.ext_size = BGE_JUMBO_FRAMELEN;
1046
1047         m_new->m_flags |= M_EXT;
1048
1049         m_new->m_data = m_new->m_ext.ext_buf;
1050         m_new->m_len = m_new->m_pkthdr.len = m_new->m_ext.ext_size;
1051
1052         paddr = buf->bge_paddr;
1053         if ((sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) == 0) {
1054                 m_adj(m_new, ETHER_ALIGN);
1055                 paddr += ETHER_ALIGN;
1056         }
1057
1058         /* Save necessary information */
1059         sc->bge_cdata.bge_rx_jumbo_chain[i].bge_mbuf = m_new;
1060         sc->bge_cdata.bge_rx_jumbo_chain[i].bge_paddr = paddr;
1061
1062         /* Set up the descriptor. */
1063         bge_setup_rxdesc_jumbo(sc, i);
1064         return 0;
1065 }
1066
1067 static void
1068 bge_setup_rxdesc_jumbo(struct bge_softc *sc, int i)
1069 {
1070         struct bge_rx_bd *r;
1071         struct bge_rxchain *rc;
1072
1073         r = &sc->bge_ldata.bge_rx_jumbo_ring[i];
1074         rc = &sc->bge_cdata.bge_rx_jumbo_chain[i];
1075
1076         r->bge_addr.bge_addr_lo = BGE_ADDR_LO(rc->bge_paddr);
1077         r->bge_addr.bge_addr_hi = BGE_ADDR_HI(rc->bge_paddr);
1078         r->bge_len = rc->bge_mbuf->m_len;
1079         r->bge_idx = i;
1080         r->bge_flags = BGE_RXBDFLAG_END|BGE_RXBDFLAG_JUMBO_RING;
1081 }
1082
1083 static int
1084 bge_init_rx_ring_std(struct bge_softc *sc)
1085 {
1086         int i, error;
1087
1088         for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
1089                 error = bge_newbuf_std(sc, i, 1);
1090                 if (error)
1091                         return error;
1092         };
1093
1094         sc->bge_std = BGE_STD_RX_RING_CNT - 1;
1095         bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std);
1096
1097         return(0);
1098 }
1099
1100 static void
1101 bge_free_rx_ring_std(struct bge_softc *sc)
1102 {
1103         int i;
1104
1105         for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
1106                 struct bge_rxchain *rc = &sc->bge_cdata.bge_rx_std_chain[i];
1107
1108                 if (rc->bge_mbuf != NULL) {
1109                         bus_dmamap_unload(sc->bge_cdata.bge_rx_mtag,
1110                                           sc->bge_cdata.bge_rx_std_dmamap[i]);
1111                         m_freem(rc->bge_mbuf);
1112                         rc->bge_mbuf = NULL;
1113                 }
1114                 bzero(&sc->bge_ldata.bge_rx_std_ring[i],
1115                     sizeof(struct bge_rx_bd));
1116         }
1117 }
1118
1119 static int
1120 bge_init_rx_ring_jumbo(struct bge_softc *sc)
1121 {
1122         struct bge_rcb *rcb;
1123         int i, error;
1124
1125         for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
1126                 error = bge_newbuf_jumbo(sc, i, 1);
1127                 if (error)
1128                         return error;
1129         };
1130
1131         sc->bge_jumbo = BGE_JUMBO_RX_RING_CNT - 1;
1132
1133         rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb;
1134         rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0, 0);
1135         CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
1136
1137         bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo);
1138
1139         return(0);
1140 }
1141
1142 static void
1143 bge_free_rx_ring_jumbo(struct bge_softc *sc)
1144 {
1145         int i;
1146
1147         for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
1148                 struct bge_rxchain *rc = &sc->bge_cdata.bge_rx_jumbo_chain[i];
1149
1150                 if (rc->bge_mbuf != NULL) {
1151                         m_freem(rc->bge_mbuf);
1152                         rc->bge_mbuf = NULL;
1153                 }
1154                 bzero(&sc->bge_ldata.bge_rx_jumbo_ring[i],
1155                     sizeof(struct bge_rx_bd));
1156         }
1157 }
1158
1159 static void
1160 bge_free_tx_ring(struct bge_softc *sc)
1161 {
1162         int i;
1163
1164         for (i = 0; i < BGE_TX_RING_CNT; i++) {
1165                 if (sc->bge_cdata.bge_tx_chain[i] != NULL) {
1166                         bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag,
1167                                           sc->bge_cdata.bge_tx_dmamap[i]);
1168                         m_freem(sc->bge_cdata.bge_tx_chain[i]);
1169                         sc->bge_cdata.bge_tx_chain[i] = NULL;
1170                 }
1171                 bzero(&sc->bge_ldata.bge_tx_ring[i],
1172                     sizeof(struct bge_tx_bd));
1173         }
1174 }
1175
1176 static int
1177 bge_init_tx_ring(struct bge_softc *sc)
1178 {
1179         sc->bge_txcnt = 0;
1180         sc->bge_tx_saved_considx = 0;
1181         sc->bge_tx_prodidx = 0;
1182
1183         /* Initialize transmit producer index for host-memory send ring. */
1184         bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx);
1185
1186         /* 5700 b2 errata */
1187         if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
1188                 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx);
1189
1190         bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0);
1191         /* 5700 b2 errata */
1192         if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
1193                 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0);
1194
1195         return(0);
1196 }
1197
1198 static void
1199 bge_setmulti(struct bge_softc *sc)
1200 {
1201         struct ifnet *ifp;
1202         struct ifmultiaddr *ifma;
1203         uint32_t hashes[4] = { 0, 0, 0, 0 };
1204         int h, i;
1205
1206         ifp = &sc->arpcom.ac_if;
1207
1208         if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
1209                 for (i = 0; i < 4; i++)
1210                         CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0xFFFFFFFF);
1211                 return;
1212         }
1213
1214         /* First, zot all the existing filters. */
1215         for (i = 0; i < 4; i++)
1216                 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0);
1217
1218         /* Now program new ones. */
1219         TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1220                 if (ifma->ifma_addr->sa_family != AF_LINK)
1221                         continue;
1222                 h = ether_crc32_le(
1223                     LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
1224                     ETHER_ADDR_LEN) & 0x7f;
1225                 hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F);
1226         }
1227
1228         for (i = 0; i < 4; i++)
1229                 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]);
1230 }
1231
1232 /*
1233  * Do endian, PCI and DMA initialization. Also check the on-board ROM
1234  * self-test results.
1235  */
1236 static int
1237 bge_chipinit(struct bge_softc *sc)
1238 {
1239         int i;
1240         uint32_t dma_rw_ctl;
1241         uint16_t val;
1242
1243         /* Set endian type before we access any non-PCI registers. */
1244         pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL,
1245             BGE_INIT | sc->bge_pci_miscctl, 4);
1246
1247         /* Clear the MAC control register */
1248         CSR_WRITE_4(sc, BGE_MAC_MODE, 0);
1249
1250         /*
1251          * Clear the MAC statistics block in the NIC's
1252          * internal memory.
1253          */
1254         for (i = BGE_STATS_BLOCK;
1255             i < BGE_STATS_BLOCK_END + 1; i += sizeof(uint32_t))
1256                 BGE_MEMWIN_WRITE(sc, i, 0);
1257
1258         for (i = BGE_STATUS_BLOCK;
1259             i < BGE_STATUS_BLOCK_END + 1; i += sizeof(uint32_t))
1260                 BGE_MEMWIN_WRITE(sc, i, 0);
1261
1262         if (sc->bge_chiprev == BGE_CHIPREV_5704_BX) {
1263                 /*
1264                  * Fix data corruption caused by non-qword write with WB.
1265                  * Fix master abort in PCI mode.
1266                  * Fix PCI latency timer.
1267                  */
1268                 val = pci_read_config(sc->bge_dev, BGE_PCI_MSI_DATA + 2, 2);
1269                 val |= (1 << 10) | (1 << 12) | (1 << 13);
1270                 pci_write_config(sc->bge_dev, BGE_PCI_MSI_DATA + 2, val, 2);
1271         }
1272
1273         /* Set up the PCI DMA control register. */
1274         if (sc->bge_flags & BGE_FLAG_PCIE) {
1275                 /* PCI Express */
1276                 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
1277                     (0xf << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
1278                     (0x2 << BGE_PCIDMARWCTL_WR_WAT_SHIFT);
1279         } else if (sc->bge_flags & BGE_FLAG_PCIX) {
1280                 /* PCI-X bus */
1281                 if (BGE_IS_5714_FAMILY(sc)) {
1282                         dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD;
1283                         dma_rw_ctl &= ~BGE_PCIDMARWCTL_ONEDMA_ATONCE; /* XXX */
1284                         /* XXX magic values, Broadcom-supplied Linux driver */
1285                         if (sc->bge_asicrev == BGE_ASICREV_BCM5780) {
1286                                 dma_rw_ctl |= (1 << 20) | (1 << 18) | 
1287                                     BGE_PCIDMARWCTL_ONEDMA_ATONCE;
1288                         } else {
1289                                 dma_rw_ctl |= (1 << 20) | (1 << 18) | (1 << 15);
1290                         }
1291                 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5703) {
1292                         /*
1293                          * In the BCM5703, the DMA read watermark should
1294                          * be set to less than or equal to the maximum
1295                          * memory read byte count of the PCI-X command
1296                          * register.
1297                          */
1298                         dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
1299                             (0x4 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
1300                             (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT);
1301                 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5704) {
1302                         /*
1303                          * The 5704 uses a different encoding of read/write
1304                          * watermarks.
1305                          */
1306                         dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
1307                             (0x7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
1308                             (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT);
1309                 } else {
1310                         dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
1311                             (0x3 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
1312                             (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT) |
1313                             (0x0F);
1314                 }
1315
1316                 /*
1317                  * 5703 and 5704 need ONEDMA_AT_ONCE as a workaround
1318                  * for hardware bugs.
1319                  */
1320                 if (sc->bge_asicrev == BGE_ASICREV_BCM5703 ||
1321                     sc->bge_asicrev == BGE_ASICREV_BCM5704) {
1322                         uint32_t tmp;
1323
1324                         tmp = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1f;
1325                         if (tmp == 0x6 || tmp == 0x7)
1326                                 dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE;
1327                 }
1328         } else {
1329                 /* Conventional PCI bus */
1330                 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
1331                     (0x7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
1332                     (0x7 << BGE_PCIDMARWCTL_WR_WAT_SHIFT) |
1333                     (0x0F);
1334         }
1335
1336         if (sc->bge_asicrev == BGE_ASICREV_BCM5703 ||
1337             sc->bge_asicrev == BGE_ASICREV_BCM5704 ||
1338             sc->bge_asicrev == BGE_ASICREV_BCM5705)
1339                 dma_rw_ctl &= ~BGE_PCIDMARWCTL_MINDMA;
1340         pci_write_config(sc->bge_dev, BGE_PCI_DMA_RW_CTL, dma_rw_ctl, 4);
1341
1342         /*
1343          * Set up general mode register.
1344          */
1345         CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS|
1346             BGE_MODECTL_MAC_ATTN_INTR|BGE_MODECTL_HOST_SEND_BDS|
1347             BGE_MODECTL_TX_NO_PHDR_CSUM);
1348
1349         /*
1350          * BCM5701 B5 have a bug causing data corruption when using
1351          * 64-bit DMA reads, which can be terminated early and then
1352          * completed later as 32-bit accesses, in combination with
1353          * certain bridges.
1354          */
1355         if (sc->bge_asicrev == BGE_ASICREV_BCM5701 &&
1356             sc->bge_chipid == BGE_CHIPID_BCM5701_B5)
1357                 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_FORCE_PCI32);
1358
1359         /*
1360          * Disable memory write invalidate.  Apparently it is not supported
1361          * properly by these devices.
1362          */
1363         PCI_CLRBIT(sc->bge_dev, BGE_PCI_CMD, PCIM_CMD_MWIEN, 4);
1364
1365         /* Set the timer prescaler (always 66Mhz) */
1366         CSR_WRITE_4(sc, BGE_MISC_CFG, 65 << 1/*BGE_32BITTIME_66MHZ*/);
1367
1368         if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
1369                 DELAY(40);      /* XXX */
1370
1371                 /* Put PHY into ready state */
1372                 BGE_CLRBIT(sc, BGE_MISC_CFG, BGE_MISCCFG_EPHY_IDDQ);
1373                 CSR_READ_4(sc, BGE_MISC_CFG); /* Flush */
1374                 DELAY(40);
1375         }
1376
1377         return(0);
1378 }
1379
1380 static int
1381 bge_blockinit(struct bge_softc *sc)
1382 {
1383         struct bge_rcb *rcb;
1384         bus_size_t vrcb;
1385         bge_hostaddr taddr;
1386         uint32_t val;
1387         int i, limit;
1388
1389         /*
1390          * Initialize the memory window pointer register so that
1391          * we can access the first 32K of internal NIC RAM. This will
1392          * allow us to set up the TX send ring RCBs and the RX return
1393          * ring RCBs, plus other things which live in NIC memory.
1394          */
1395         CSR_WRITE_4(sc, BGE_PCI_MEMWIN_BASEADDR, 0);
1396
1397         /* Note: the BCM5704 has a smaller mbuf space than other chips. */
1398
1399         if (!BGE_IS_5705_PLUS(sc)) {
1400                 /* Configure mbuf memory pool */
1401                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, BGE_BUFFPOOL_1);
1402                 if (sc->bge_asicrev == BGE_ASICREV_BCM5704)
1403                         CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000);
1404                 else
1405                         CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000);
1406
1407                 /* Configure DMA resource pool */
1408                 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR,
1409                     BGE_DMA_DESCRIPTORS);
1410                 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000);
1411         }
1412
1413         /* Configure mbuf pool watermarks */
1414         if (!BGE_IS_5705_PLUS(sc)) {
1415                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50);
1416                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20);
1417                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60);
1418         } else if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
1419                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
1420                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x04);
1421                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x10);
1422         } else {
1423                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
1424                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10);
1425                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60);
1426         }
1427
1428         /* Configure DMA resource watermarks */
1429         CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5);
1430         CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10);
1431
1432         /* Enable buffer manager */
1433         CSR_WRITE_4(sc, BGE_BMAN_MODE,
1434             BGE_BMANMODE_ENABLE|BGE_BMANMODE_LOMBUF_ATTN);
1435
1436         /* Poll for buffer manager start indication */
1437         for (i = 0; i < BGE_TIMEOUT; i++) {
1438                 if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE)
1439                         break;
1440                 DELAY(10);
1441         }
1442
1443         if (i == BGE_TIMEOUT) {
1444                 if_printf(&sc->arpcom.ac_if,
1445                           "buffer manager failed to start\n");
1446                 return(ENXIO);
1447         }
1448
1449         /* Enable flow-through queues */
1450         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
1451         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
1452
1453         /* Wait until queue initialization is complete */
1454         for (i = 0; i < BGE_TIMEOUT; i++) {
1455                 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0)
1456                         break;
1457                 DELAY(10);
1458         }
1459
1460         if (i == BGE_TIMEOUT) {
1461                 if_printf(&sc->arpcom.ac_if,
1462                           "flow-through queue init failed\n");
1463                 return(ENXIO);
1464         }
1465
1466         /*
1467          * Summary of rings supported by the controller:
1468          *
1469          * Standard Receive Producer Ring
1470          * - This ring is used to feed receive buffers for "standard"
1471          *   sized frames (typically 1536 bytes) to the controller.
1472          *
1473          * Jumbo Receive Producer Ring
1474          * - This ring is used to feed receive buffers for jumbo sized
1475          *   frames (i.e. anything bigger than the "standard" frames)
1476          *   to the controller.
1477          *
1478          * Mini Receive Producer Ring
1479          * - This ring is used to feed receive buffers for "mini"
1480          *   sized frames to the controller.
1481          * - This feature required external memory for the controller
1482          *   but was never used in a production system.  Should always
1483          *   be disabled.
1484          *
1485          * Receive Return Ring
1486          * - After the controller has placed an incoming frame into a
1487          *   receive buffer that buffer is moved into a receive return
1488          *   ring.  The driver is then responsible to passing the
1489          *   buffer up to the stack.  Many versions of the controller
1490          *   support multiple RR rings.
1491          *
1492          * Send Ring
1493          * - This ring is used for outgoing frames.  Many versions of
1494          *   the controller support multiple send rings.
1495          */
1496
1497         /* Initialize the standard receive producer ring control block. */
1498         rcb = &sc->bge_ldata.bge_info.bge_std_rx_rcb;
1499         rcb->bge_hostaddr.bge_addr_lo =
1500             BGE_ADDR_LO(sc->bge_ldata.bge_rx_std_ring_paddr);
1501         rcb->bge_hostaddr.bge_addr_hi =
1502             BGE_ADDR_HI(sc->bge_ldata.bge_rx_std_ring_paddr);
1503         if (BGE_IS_5705_PLUS(sc)) {
1504                 /*
1505                  * Bits 31-16: Programmable ring size (512, 256, 128, 64, 32)
1506                  * Bits 15-2 : Reserved (should be 0)
1507                  * Bit 1     : 1 = Ring Disabled, 0 = Ring Enabled
1508                  * Bit 0     : Reserved
1509                  */
1510                 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0);
1511         } else {
1512                 /*
1513                  * Ring size is always XXX entries
1514                  * Bits 31-16: Maximum RX frame size
1515                  * Bits 15-2 : Reserved (should be 0)
1516                  * Bit 1     : 1 = Ring Disabled, 0 = Ring Enabled
1517                  * Bit 0     : Reserved
1518                  */
1519                 rcb->bge_maxlen_flags =
1520                     BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 0);
1521         }
1522         rcb->bge_nicaddr = BGE_STD_RX_RINGS;
1523         /* Write the standard receive producer ring control block. */
1524         CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi);
1525         CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo);
1526         CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
1527         CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr);
1528         /* Reset the standard receive producer ring producer index. */
1529         bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, 0);
1530
1531         /*
1532          * Initialize the jumbo RX producer ring control
1533          * block.  We set the 'ring disabled' bit in the
1534          * flags field until we're actually ready to start
1535          * using this ring (i.e. once we set the MTU
1536          * high enough to require it).
1537          */
1538         if (BGE_IS_JUMBO_CAPABLE(sc)) {
1539                 rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb;
1540                 /* Get the jumbo receive producer ring RCB parameters. */
1541                 rcb->bge_hostaddr.bge_addr_lo =
1542                     BGE_ADDR_LO(sc->bge_ldata.bge_rx_jumbo_ring_paddr);
1543                 rcb->bge_hostaddr.bge_addr_hi =
1544                     BGE_ADDR_HI(sc->bge_ldata.bge_rx_jumbo_ring_paddr);
1545                 rcb->bge_maxlen_flags =
1546                     BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN,
1547                     BGE_RCB_FLAG_RING_DISABLED);
1548                 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS;
1549                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI,
1550                     rcb->bge_hostaddr.bge_addr_hi);
1551                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO,
1552                     rcb->bge_hostaddr.bge_addr_lo);
1553                 /* Program the jumbo receive producer ring RCB parameters. */
1554                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS,
1555                     rcb->bge_maxlen_flags);
1556                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr);
1557                 /* Reset the jumbo receive producer ring producer index. */
1558                 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0);
1559         }
1560
1561         /* Disable the mini receive producer ring RCB. */
1562         if (BGE_IS_5700_FAMILY(sc)) {
1563                 rcb = &sc->bge_ldata.bge_info.bge_mini_rx_rcb;
1564                 rcb->bge_maxlen_flags =
1565                     BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED);
1566                 CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS,
1567                     rcb->bge_maxlen_flags);
1568                 /* Reset the mini receive producer ring producer index. */
1569                 bge_writembx(sc, BGE_MBX_RX_MINI_PROD_LO, 0);
1570         }
1571
1572         /* Choose de-pipeline mode for BCM5906 A0, A1 and A2. */
1573         if (sc->bge_asicrev == BGE_ASICREV_BCM5906 &&
1574             (sc->bge_chipid == BGE_CHIPID_BCM5906_A0 ||
1575              sc->bge_chipid == BGE_CHIPID_BCM5906_A1 ||
1576              sc->bge_chipid == BGE_CHIPID_BCM5906_A2)) {
1577                 CSR_WRITE_4(sc, BGE_ISO_PKT_TX,
1578                     (CSR_READ_4(sc, BGE_ISO_PKT_TX) & ~3) | 2);
1579         }
1580
1581         /*
1582          * The BD ring replenish thresholds control how often the
1583          * hardware fetches new BD's from the producer rings in host
1584          * memory.  Setting the value too low on a busy system can
1585          * starve the hardware and recue the throughpout.
1586          *
1587          * Set the BD ring replentish thresholds. The recommended
1588          * values are 1/8th the number of descriptors allocated to
1589          * each ring.
1590          */
1591         if (BGE_IS_5705_PLUS(sc))
1592                 val = 8;
1593         else
1594                 val = BGE_STD_RX_RING_CNT / 8;
1595         CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, val);
1596         if (BGE_IS_JUMBO_CAPABLE(sc)) {
1597                 CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH,
1598                     BGE_JUMBO_RX_RING_CNT/8);
1599         }
1600
1601         /*
1602          * Disable all send rings by setting the 'ring disabled' bit
1603          * in the flags field of all the TX send ring control blocks,
1604          * located in NIC memory.
1605          */
1606         if (!BGE_IS_5705_PLUS(sc)) {
1607                 /* 5700 to 5704 had 16 send rings. */
1608                 limit = BGE_TX_RINGS_EXTSSRAM_MAX;
1609         } else {
1610                 limit = 1;
1611         }
1612         vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB;
1613         for (i = 0; i < limit; i++) {
1614                 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1615                     BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED));
1616                 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
1617                 vrcb += sizeof(struct bge_rcb);
1618         }
1619
1620         /* Configure send ring RCB 0 (we use only the first ring) */
1621         vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB;
1622         BGE_HOSTADDR(taddr, sc->bge_ldata.bge_tx_ring_paddr);
1623         RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi);
1624         RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo);
1625         RCB_WRITE_4(sc, vrcb, bge_nicaddr,
1626             BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT));
1627         RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1628             BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0));
1629
1630         /*
1631          * Disable all receive return rings by setting the
1632          * 'ring diabled' bit in the flags field of all the receive
1633          * return ring control blocks, located in NIC memory.
1634          */
1635         if (!BGE_IS_5705_PLUS(sc))
1636                 limit = BGE_RX_RINGS_MAX;
1637         else if (sc->bge_asicrev == BGE_ASICREV_BCM5755)
1638                 limit = 4;
1639         else
1640                 limit = 1;
1641         /* Disable all receive return rings. */
1642         vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB;
1643         for (i = 0; i < limit; i++) {
1644                 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, 0);
1645                 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, 0);
1646                 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1647                     BGE_RCB_FLAG_RING_DISABLED);
1648                 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
1649                 bge_writembx(sc, BGE_MBX_RX_CONS0_LO +
1650                     (i * (sizeof(uint64_t))), 0);
1651                 vrcb += sizeof(struct bge_rcb);
1652         }
1653
1654         /*
1655          * Set up receive return ring 0.  Note that the NIC address
1656          * for RX return rings is 0x0.  The return rings live entirely
1657          * within the host, so the nicaddr field in the RCB isn't used.
1658          */
1659         vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB;
1660         BGE_HOSTADDR(taddr, sc->bge_ldata.bge_rx_return_ring_paddr);
1661         RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi);
1662         RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo);
1663         RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
1664         RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1665             BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 0));
1666
1667         /* Set random backoff seed for TX */
1668         CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF,
1669             sc->arpcom.ac_enaddr[0] + sc->arpcom.ac_enaddr[1] +
1670             sc->arpcom.ac_enaddr[2] + sc->arpcom.ac_enaddr[3] +
1671             sc->arpcom.ac_enaddr[4] + sc->arpcom.ac_enaddr[5] +
1672             BGE_TX_BACKOFF_SEED_MASK);
1673
1674         /* Set inter-packet gap */
1675         CSR_WRITE_4(sc, BGE_TX_LENGTHS, 0x2620);
1676
1677         /*
1678          * Specify which ring to use for packets that don't match
1679          * any RX rules.
1680          */
1681         CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08);
1682
1683         /*
1684          * Configure number of RX lists. One interrupt distribution
1685          * list, sixteen active lists, one bad frames class.
1686          */
1687         CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181);
1688
1689         /* Inialize RX list placement stats mask. */
1690         CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF);
1691         CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1);
1692
1693         /* Disable host coalescing until we get it set up */
1694         CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000);
1695
1696         /* Poll to make sure it's shut down. */
1697         for (i = 0; i < BGE_TIMEOUT; i++) {
1698                 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE))
1699                         break;
1700                 DELAY(10);
1701         }
1702
1703         if (i == BGE_TIMEOUT) {
1704                 if_printf(&sc->arpcom.ac_if,
1705                           "host coalescing engine failed to idle\n");
1706                 return(ENXIO);
1707         }
1708
1709         /* Set up host coalescing defaults */
1710         CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks);
1711         CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks);
1712         CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_coal_bds);
1713         CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_coal_bds);
1714         if (!BGE_IS_5705_PLUS(sc)) {
1715                 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT,
1716                     sc->bge_rx_coal_ticks_int);
1717                 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT,
1718                     sc->bge_tx_coal_ticks_int);
1719         }
1720         /*
1721          * NOTE:
1722          * The datasheet (57XX-PG105-R) says BCM5705+ do not
1723          * have following two registers; obviously it is wrong.
1724          */
1725         CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, sc->bge_rx_coal_bds_int);
1726         CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, sc->bge_tx_coal_bds_int);
1727
1728         /* Set up address of statistics block */
1729         if (!BGE_IS_5705_PLUS(sc)) {
1730                 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI,
1731                     BGE_ADDR_HI(sc->bge_ldata.bge_stats_paddr));
1732                 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO,
1733                     BGE_ADDR_LO(sc->bge_ldata.bge_stats_paddr));
1734
1735                 CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK);
1736                 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK);
1737                 CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks);
1738         }
1739
1740         /* Set up address of status block */
1741         bzero(sc->bge_ldata.bge_status_block, BGE_STATUS_BLK_SZ);
1742         CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI,
1743             BGE_ADDR_HI(sc->bge_ldata.bge_status_block_paddr));
1744         CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO,
1745             BGE_ADDR_LO(sc->bge_ldata.bge_status_block_paddr));
1746
1747         /*
1748          * Set up status block partail update size.
1749          *
1750          * Because only single TX ring, RX produce ring and Rx return ring
1751          * are used, ask device to update only minimum part of status block
1752          * except for BCM5700 AX/BX, whose status block partial update size
1753          * can't be configured.
1754          */
1755         if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
1756             sc->bge_chipid != BGE_CHIPID_BCM5700_C0) {
1757                 /* XXX Actually reserved on BCM5700 AX/BX */
1758                 val = BGE_STATBLKSZ_FULL;
1759         } else {
1760                 val = BGE_STATBLKSZ_32BYTE;
1761         }
1762 #if 0
1763         /*
1764          * Does not seem to have visible effect in both
1765          * bulk data (1472B UDP datagram) and tiny data
1766          * (18B UDP datagram) TX tests.
1767          */
1768         if (!BGE_IS_CRIPPLED(sc))
1769                 val |= BGE_HCCMODE_CLRTICK_TX;
1770 #endif
1771
1772         /* Turn on host coalescing state machine */
1773         CSR_WRITE_4(sc, BGE_HCC_MODE, val | BGE_HCCMODE_ENABLE);
1774
1775         /* Turn on RX BD completion state machine and enable attentions */
1776         CSR_WRITE_4(sc, BGE_RBDC_MODE,
1777             BGE_RBDCMODE_ENABLE|BGE_RBDCMODE_ATTN);
1778
1779         /* Turn on RX list placement state machine */
1780         CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
1781
1782         /* Turn on RX list selector state machine. */
1783         if (!BGE_IS_5705_PLUS(sc))
1784                 CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE);
1785
1786         val = BGE_MACMODE_TXDMA_ENB | BGE_MACMODE_RXDMA_ENB |
1787             BGE_MACMODE_RX_STATS_CLEAR | BGE_MACMODE_TX_STATS_CLEAR |
1788             BGE_MACMODE_RX_STATS_ENB | BGE_MACMODE_TX_STATS_ENB |
1789             BGE_MACMODE_FRMHDR_DMA_ENB;
1790
1791         if (sc->bge_flags & BGE_FLAG_TBI)
1792                 val |= BGE_PORTMODE_TBI;
1793         else if (sc->bge_flags & BGE_FLAG_MII_SERDES)
1794                 val |= BGE_PORTMODE_GMII;
1795         else
1796                 val |= BGE_PORTMODE_MII;
1797
1798         /* Turn on DMA, clear stats */
1799         CSR_WRITE_4(sc, BGE_MAC_MODE, val);
1800
1801         /* Set misc. local control, enable interrupts on attentions */
1802         CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN);
1803
1804 #ifdef notdef
1805         /* Assert GPIO pins for PHY reset */
1806         BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0|
1807             BGE_MLC_MISCIO_OUT1|BGE_MLC_MISCIO_OUT2);
1808         BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0|
1809             BGE_MLC_MISCIO_OUTEN1|BGE_MLC_MISCIO_OUTEN2);
1810 #endif
1811
1812         /* Turn on DMA completion state machine */
1813         if (!BGE_IS_5705_PLUS(sc))
1814                 CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE);
1815
1816         /* Turn on write DMA state machine */
1817         val = BGE_WDMAMODE_ENABLE|BGE_WDMAMODE_ALL_ATTNS;
1818         if (BGE_IS_5755_PLUS(sc)) {
1819                 /* Enable host coalescing bug fix. */
1820                 val |= BGE_WDMAMODE_STATUS_TAG_FIX;
1821         }
1822         if (sc->bge_asicrev == BGE_ASICREV_BCM5785) {
1823                 /* Request larger DMA burst size to get better performance. */
1824                 val |= BGE_WDMAMODE_BURST_ALL_DATA;
1825         }
1826         CSR_WRITE_4(sc, BGE_WDMA_MODE, val);
1827         DELAY(40);
1828
1829         if (sc->bge_asicrev == BGE_ASICREV_BCM5761 ||
1830             sc->bge_asicrev == BGE_ASICREV_BCM5784 ||
1831             sc->bge_asicrev == BGE_ASICREV_BCM5785 ||
1832             sc->bge_asicrev == BGE_ASICREV_BCM57780) {
1833                 /*
1834                  * Enable fix for read DMA FIFO overruns.
1835                  * The fix is to limit the number of RX BDs
1836                  * the hardware would fetch at a fime.
1837                  */
1838                 val = CSR_READ_4(sc, BGE_RDMA_RSRVCTRL);
1839                 CSR_WRITE_4(sc, BGE_RDMA_RSRVCTRL,
1840                     val| BGE_RDMA_RSRVCTRL_FIFO_OFLW_FIX);
1841         }
1842
1843         /* Turn on read DMA state machine */
1844         val = BGE_RDMAMODE_ENABLE | BGE_RDMAMODE_ALL_ATTNS;
1845         if (sc->bge_asicrev == BGE_ASICREV_BCM5784 ||
1846             sc->bge_asicrev == BGE_ASICREV_BCM5785 ||
1847             sc->bge_asicrev == BGE_ASICREV_BCM57780)
1848                 val |= BGE_RDMAMODE_BD_SBD_CRPT_ATTN |
1849                   BGE_RDMAMODE_MBUF_RBD_CRPT_ATTN |
1850                   BGE_RDMAMODE_MBUF_SBD_CRPT_ATTN;
1851         if (sc->bge_flags & BGE_FLAG_PCIE)
1852                 val |= BGE_RDMAMODE_FIFO_LONG_BURST;
1853         CSR_WRITE_4(sc, BGE_RDMA_MODE, val);
1854         DELAY(40);
1855
1856         /* Turn on RX data completion state machine */
1857         CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
1858
1859         /* Turn on RX BD initiator state machine */
1860         CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
1861
1862         /* Turn on RX data and RX BD initiator state machine */
1863         CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE);
1864
1865         /* Turn on Mbuf cluster free state machine */
1866         if (!BGE_IS_5705_PLUS(sc))
1867                 CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE);
1868
1869         /* Turn on send BD completion state machine */
1870         CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
1871
1872         /* Turn on send data completion state machine */
1873         val = BGE_SDCMODE_ENABLE;
1874         if (sc->bge_asicrev == BGE_ASICREV_BCM5761)
1875                 val |= BGE_SDCMODE_CDELAY; 
1876         CSR_WRITE_4(sc, BGE_SDC_MODE, val);
1877
1878         /* Turn on send data initiator state machine */
1879         CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
1880
1881         /* Turn on send BD initiator state machine */
1882         CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
1883
1884         /* Turn on send BD selector state machine */
1885         CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
1886
1887         CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF);
1888         CSR_WRITE_4(sc, BGE_SDI_STATS_CTL,
1889             BGE_SDISTATSCTL_ENABLE|BGE_SDISTATSCTL_FASTER);
1890
1891         /* ack/clear link change events */
1892         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED|
1893             BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE|
1894             BGE_MACSTAT_LINK_CHANGED);
1895         CSR_WRITE_4(sc, BGE_MI_STS, 0);
1896
1897         /*
1898          * Enable attention when the link has changed state for
1899          * devices that use auto polling.
1900          */
1901         if (sc->bge_flags & BGE_FLAG_TBI) {
1902                 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK);
1903         } else {
1904                 if (sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) {
1905                         CSR_WRITE_4(sc, BGE_MI_MODE, sc->bge_mi_mode);
1906                         DELAY(80);
1907                 }
1908                 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
1909                     sc->bge_chipid != BGE_CHIPID_BCM5700_B2) {
1910                         CSR_WRITE_4(sc, BGE_MAC_EVT_ENB,
1911                             BGE_EVTENB_MI_INTERRUPT);
1912                 }
1913         }
1914
1915         /*
1916          * Clear any pending link state attention.
1917          * Otherwise some link state change events may be lost until attention
1918          * is cleared by bge_intr() -> bge_softc.bge_link_upd() sequence.
1919          * It's not necessary on newer BCM chips - perhaps enabling link
1920          * state change attentions implies clearing pending attention.
1921          */
1922         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED|
1923             BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE|
1924             BGE_MACSTAT_LINK_CHANGED);
1925
1926         /* Enable link state change attentions. */
1927         BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED);
1928
1929         return(0);
1930 }
1931
1932 /*
1933  * Probe for a Broadcom chip. Check the PCI vendor and device IDs
1934  * against our list and return its name if we find a match. Note
1935  * that since the Broadcom controller contains VPD support, we
1936  * can get the device name string from the controller itself instead
1937  * of the compiled-in string. This is a little slow, but it guarantees
1938  * we'll always announce the right product name.
1939  */
1940 static int
1941 bge_probe(device_t dev)
1942 {
1943         const struct bge_type *t;
1944         uint16_t product, vendor;
1945
1946         product = pci_get_device(dev);
1947         vendor = pci_get_vendor(dev);
1948
1949         for (t = bge_devs; t->bge_name != NULL; t++) {
1950                 if (vendor == t->bge_vid && product == t->bge_did)
1951                         break;
1952         }
1953         if (t->bge_name == NULL)
1954                 return(ENXIO);
1955
1956         device_set_desc(dev, t->bge_name);
1957         return(0);
1958 }
1959
1960 static int
1961 bge_attach(device_t dev)
1962 {
1963         struct ifnet *ifp;
1964         struct bge_softc *sc;
1965         uint32_t hwcfg = 0, misccfg;
1966         int error = 0, rid, capmask;
1967         uint8_t ether_addr[ETHER_ADDR_LEN];
1968         uint16_t product, vendor;
1969         driver_intr_t *intr_func;
1970         uintptr_t mii_priv = 0;
1971
1972         sc = device_get_softc(dev);
1973         sc->bge_dev = dev;
1974         callout_init(&sc->bge_stat_timer);
1975         lwkt_serialize_init(&sc->bge_jslot_serializer);
1976
1977 #ifndef BURN_BRIDGES
1978         if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
1979                 uint32_t irq, mem;
1980
1981                 irq = pci_read_config(dev, PCIR_INTLINE, 4);
1982                 mem = pci_read_config(dev, BGE_PCI_BAR0, 4);
1983
1984                 device_printf(dev, "chip is in D%d power mode "
1985                     "-- setting to D0\n", pci_get_powerstate(dev));
1986
1987                 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
1988
1989                 pci_write_config(dev, PCIR_INTLINE, irq, 4);
1990                 pci_write_config(dev, BGE_PCI_BAR0, mem, 4);
1991         }
1992 #endif  /* !BURN_BRIDGE */
1993
1994         /*
1995          * Map control/status registers.
1996          */
1997         pci_enable_busmaster(dev);
1998
1999         rid = BGE_PCI_BAR0;
2000         sc->bge_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
2001             RF_ACTIVE);
2002
2003         if (sc->bge_res == NULL) {
2004                 device_printf(dev, "couldn't map memory\n");
2005                 return ENXIO;
2006         }
2007
2008         sc->bge_btag = rman_get_bustag(sc->bge_res);
2009         sc->bge_bhandle = rman_get_bushandle(sc->bge_res);
2010
2011         /* Save various chip information */
2012         sc->bge_chipid =
2013             pci_read_config(dev, BGE_PCI_MISC_CTL, 4) >>
2014             BGE_PCIMISCCTL_ASICREV_SHIFT;
2015         if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_USE_PRODID_REG)
2016                 sc->bge_chipid = pci_read_config(dev, BGE_PCI_PRODID_ASICREV, 4);
2017         sc->bge_asicrev = BGE_ASICREV(sc->bge_chipid);
2018         sc->bge_chiprev = BGE_CHIPREV(sc->bge_chipid);
2019
2020         /* Save chipset family. */
2021         switch (sc->bge_asicrev) {
2022         case BGE_ASICREV_BCM5755:
2023         case BGE_ASICREV_BCM5761:
2024         case BGE_ASICREV_BCM5784:
2025         case BGE_ASICREV_BCM5785:
2026         case BGE_ASICREV_BCM5787:
2027         case BGE_ASICREV_BCM57780:
2028             sc->bge_flags |= BGE_FLAG_5755_PLUS | BGE_FLAG_575X_PLUS |
2029                 BGE_FLAG_5705_PLUS;
2030             break;
2031
2032         case BGE_ASICREV_BCM5700:
2033         case BGE_ASICREV_BCM5701:
2034         case BGE_ASICREV_BCM5703:
2035         case BGE_ASICREV_BCM5704:
2036                 sc->bge_flags |= BGE_FLAG_5700_FAMILY | BGE_FLAG_JUMBO;
2037                 break;
2038
2039         case BGE_ASICREV_BCM5714_A0:
2040         case BGE_ASICREV_BCM5780:
2041         case BGE_ASICREV_BCM5714:
2042                 sc->bge_flags |= BGE_FLAG_5714_FAMILY;
2043                 /* Fall through */
2044
2045         case BGE_ASICREV_BCM5750:
2046         case BGE_ASICREV_BCM5752:
2047         case BGE_ASICREV_BCM5906:
2048                 sc->bge_flags |= BGE_FLAG_575X_PLUS;
2049                 /* Fall through */
2050
2051         case BGE_ASICREV_BCM5705:
2052                 sc->bge_flags |= BGE_FLAG_5705_PLUS;
2053                 break;
2054         }
2055
2056         if (sc->bge_asicrev == BGE_ASICREV_BCM5906)
2057                 sc->bge_flags |= BGE_FLAG_NO_EEPROM;
2058
2059         misccfg = CSR_READ_4(sc, BGE_MISC_CFG) & BGE_MISCCFG_BOARD_ID_MASK;
2060         if (sc->bge_asicrev == BGE_ASICREV_BCM5705 &&
2061             (misccfg == BGE_MISCCFG_BOARD_ID_5788 ||
2062              misccfg == BGE_MISCCFG_BOARD_ID_5788M))
2063                 sc->bge_flags |= BGE_FLAG_5788;
2064
2065         /* BCM5755 or higher and BCM5906 have short DMA bug. */
2066         if (BGE_IS_5755_PLUS(sc) || sc->bge_asicrev == BGE_ASICREV_BCM5906)
2067                 sc->bge_flags |= BGE_FLAG_SHORTDMA;
2068
2069         /*
2070          * Check if this is a PCI-X or PCI Express device.
2071          */
2072         if (BGE_IS_5705_PLUS(sc)) {
2073                 if (pci_is_pcie(dev)) {
2074                         sc->bge_flags |= BGE_FLAG_PCIE;
2075                         sc->bge_pciecap = pci_get_pciecap_ptr(sc->bge_dev);
2076                         pcie_set_max_readrq(dev, PCIEM_DEVCTL_MAX_READRQ_4096);
2077                 }
2078         } else {
2079                 /*
2080                  * Check if the device is in PCI-X Mode.
2081                  * (This bit is not valid on PCI Express controllers.)
2082                  */
2083                 if ((pci_read_config(sc->bge_dev, BGE_PCI_PCISTATE, 4) &
2084                     BGE_PCISTATE_PCI_BUSMODE) == 0) {
2085                         sc->bge_flags |= BGE_FLAG_PCIX;
2086                         sc->bge_pcixcap = pci_get_pcixcap_ptr(sc->bge_dev);
2087                         sc->bge_mbox_reorder = device_getenv_int(sc->bge_dev,
2088                             "mbox_reorder", 0);
2089                 }
2090         }
2091         device_printf(dev, "CHIP ID 0x%08x; "
2092                       "ASIC REV 0x%02x; CHIP REV 0x%02x; %s\n",
2093                       sc->bge_chipid, sc->bge_asicrev, sc->bge_chiprev,
2094                       (sc->bge_flags & BGE_FLAG_PCIX) ? "PCI-X"
2095                       : ((sc->bge_flags & BGE_FLAG_PCIE) ?
2096                         "PCI-E" : "PCI"));
2097
2098         /*
2099          * The 40bit DMA bug applies to the 5714/5715 controllers and is
2100          * not actually a MAC controller bug but an issue with the embedded
2101          * PCIe to PCI-X bridge in the device. Use 40bit DMA workaround.
2102          */
2103         if (BGE_IS_5714_FAMILY(sc) && (sc->bge_flags & BGE_FLAG_PCIX))
2104                 sc->bge_flags |= BGE_FLAG_MAXADDR_40BIT;
2105
2106         /* Identify the chips that use an CPMU. */
2107         if (sc->bge_asicrev == BGE_ASICREV_BCM5784 ||
2108             sc->bge_asicrev == BGE_ASICREV_BCM5761 ||
2109             sc->bge_asicrev == BGE_ASICREV_BCM5785 ||
2110             sc->bge_asicrev == BGE_ASICREV_BCM57780)
2111                 sc->bge_flags |= BGE_FLAG_CPMU;
2112
2113         /*
2114          * When using the BCM5701 in PCI-X mode, data corruption has
2115          * been observed in the first few bytes of some received packets.
2116          * Aligning the packet buffer in memory eliminates the corruption.
2117          * Unfortunately, this misaligns the packet payloads.  On platforms
2118          * which do not support unaligned accesses, we will realign the
2119          * payloads by copying the received packets.
2120          */
2121         if (sc->bge_asicrev == BGE_ASICREV_BCM5701 &&
2122             (sc->bge_flags & BGE_FLAG_PCIX))
2123                 sc->bge_flags |= BGE_FLAG_RX_ALIGNBUG;
2124
2125         if (!BGE_IS_CRIPPLED(sc)) {
2126                 if (device_getenv_int(dev, "status_tag", 1)) {
2127                         sc->bge_flags |= BGE_FLAG_STATUS_TAG;
2128                         sc->bge_pci_miscctl = BGE_PCIMISCCTL_TAGGED_STATUS;
2129                         if (bootverbose)
2130                                 device_printf(dev, "enable status tag\n");
2131                 }
2132         }
2133
2134         /*
2135          * Set various PHY quirk flags.
2136          */
2137         product = pci_get_device(dev);
2138         vendor = pci_get_vendor(dev);
2139
2140         if ((sc->bge_asicrev == BGE_ASICREV_BCM5700 ||
2141              sc->bge_asicrev == BGE_ASICREV_BCM5701) &&
2142             pci_get_subvendor(dev) == PCI_VENDOR_DELL)
2143                 mii_priv |= BRGPHY_FLAG_NO_3LED;
2144
2145         capmask = MII_CAPMASK_DEFAULT;
2146         if ((sc->bge_asicrev == BGE_ASICREV_BCM5703 &&
2147              (misccfg == 0x4000 || misccfg == 0x8000)) ||
2148             (sc->bge_asicrev == BGE_ASICREV_BCM5705 &&
2149              vendor == PCI_VENDOR_BROADCOM &&
2150              (product == PCI_PRODUCT_BROADCOM_BCM5901 ||
2151               product == PCI_PRODUCT_BROADCOM_BCM5901A2 ||
2152               product == PCI_PRODUCT_BROADCOM_BCM5705F)) ||
2153             (vendor == PCI_VENDOR_BROADCOM &&
2154              (product == PCI_PRODUCT_BROADCOM_BCM5751F ||
2155               product == PCI_PRODUCT_BROADCOM_BCM5753F ||
2156               product == PCI_PRODUCT_BROADCOM_BCM5787F)) ||
2157             product == PCI_PRODUCT_BROADCOM_BCM57790 ||
2158             sc->bge_asicrev == BGE_ASICREV_BCM5906) {
2159                 /* 10/100 only */
2160                 capmask &= ~BMSR_EXTSTAT;
2161         }
2162
2163         mii_priv |= BRGPHY_FLAG_WIRESPEED;
2164         if (sc->bge_asicrev == BGE_ASICREV_BCM5700 ||
2165             (sc->bge_asicrev == BGE_ASICREV_BCM5705 &&
2166              (sc->bge_chipid != BGE_CHIPID_BCM5705_A0 &&
2167               sc->bge_chipid != BGE_CHIPID_BCM5705_A1)) ||
2168             sc->bge_asicrev == BGE_ASICREV_BCM5906)
2169                 mii_priv &= ~BRGPHY_FLAG_WIRESPEED;
2170
2171         if (sc->bge_chipid == BGE_CHIPID_BCM5701_A0 ||
2172             sc->bge_chipid == BGE_CHIPID_BCM5701_B0)
2173                 mii_priv |= BRGPHY_FLAG_CRC_BUG;
2174
2175         if (sc->bge_chiprev == BGE_CHIPREV_5703_AX ||
2176             sc->bge_chiprev == BGE_CHIPREV_5704_AX)
2177                 mii_priv |= BRGPHY_FLAG_ADC_BUG;
2178
2179         if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0)
2180                 mii_priv |= BRGPHY_FLAG_5704_A0;
2181
2182         if (sc->bge_asicrev == BGE_ASICREV_BCM5906)
2183                 mii_priv |= BRGPHY_FLAG_5906;
2184
2185         if (BGE_IS_5705_PLUS(sc) &&
2186             sc->bge_asicrev != BGE_ASICREV_BCM5906 &&
2187             /* sc->bge_asicrev != BGE_ASICREV_BCM5717 && */
2188             sc->bge_asicrev != BGE_ASICREV_BCM5785 &&
2189             /* sc->bge_asicrev != BGE_ASICREV_BCM57765 && */
2190             sc->bge_asicrev != BGE_ASICREV_BCM57780) {
2191                 if (sc->bge_asicrev == BGE_ASICREV_BCM5755 ||
2192                     sc->bge_asicrev == BGE_ASICREV_BCM5761 ||
2193                     sc->bge_asicrev == BGE_ASICREV_BCM5784 ||
2194                     sc->bge_asicrev == BGE_ASICREV_BCM5787) {
2195                         if (product != PCI_PRODUCT_BROADCOM_BCM5722 &&
2196                             product != PCI_PRODUCT_BROADCOM_BCM5756)
2197                                 mii_priv |= BRGPHY_FLAG_JITTER_BUG;
2198                         if (product == PCI_PRODUCT_BROADCOM_BCM5755M)
2199                                 mii_priv |= BRGPHY_FLAG_ADJUST_TRIM;
2200                 } else {
2201                         mii_priv |= BRGPHY_FLAG_BER_BUG;
2202                 }
2203         }
2204
2205         /* Allocate interrupt */
2206         rid = 0;
2207         sc->bge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
2208             RF_SHAREABLE | RF_ACTIVE);
2209         if (sc->bge_irq == NULL) {
2210                 device_printf(dev, "couldn't map interrupt\n");
2211                 error = ENXIO;
2212                 goto fail;
2213         }
2214
2215         /* Initialize if_name earlier, so if_printf could be used */
2216         ifp = &sc->arpcom.ac_if;
2217         if_initname(ifp, device_get_name(dev), device_get_unit(dev));
2218
2219         /* Try to reset the chip. */
2220         bge_reset(sc);
2221
2222         if (bge_chipinit(sc)) {
2223                 device_printf(dev, "chip initialization failed\n");
2224                 error = ENXIO;
2225                 goto fail;
2226         }
2227
2228         /*
2229          * Get station address
2230          */
2231         error = bge_get_eaddr(sc, ether_addr);
2232         if (error) {
2233                 device_printf(dev, "failed to read station address\n");
2234                 goto fail;
2235         }
2236
2237         /* 5705/5750 limits RX return ring to 512 entries. */
2238         if (BGE_IS_5705_PLUS(sc))
2239                 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT_5705;
2240         else
2241                 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT;
2242
2243         error = bge_dma_alloc(sc);
2244         if (error)
2245                 goto fail;
2246
2247         /* Set default tuneable values. */
2248         sc->bge_stat_ticks = BGE_TICKS_PER_SEC;
2249         sc->bge_rx_coal_ticks = BGE_RX_COAL_TICKS_DEF;
2250         sc->bge_tx_coal_ticks = BGE_TX_COAL_TICKS_DEF;
2251         sc->bge_rx_coal_bds = BGE_RX_COAL_BDS_DEF;
2252         sc->bge_tx_coal_bds = BGE_TX_COAL_BDS_DEF;
2253         if (sc->bge_flags & BGE_FLAG_STATUS_TAG) {
2254                 sc->bge_rx_coal_ticks_int = BGE_RX_COAL_TICKS_DEF;
2255                 sc->bge_tx_coal_ticks_int = BGE_TX_COAL_TICKS_DEF;
2256                 sc->bge_rx_coal_bds_int = BGE_RX_COAL_BDS_DEF;
2257                 sc->bge_tx_coal_bds_int = BGE_TX_COAL_BDS_DEF;
2258         } else {
2259                 sc->bge_rx_coal_ticks_int = BGE_RX_COAL_TICKS_MIN;
2260                 sc->bge_tx_coal_ticks_int = BGE_TX_COAL_TICKS_MIN;
2261                 sc->bge_rx_coal_bds_int = BGE_RX_COAL_BDS_MIN;
2262                 sc->bge_tx_coal_bds_int = BGE_TX_COAL_BDS_MIN;
2263         }
2264
2265         /* Set up ifnet structure */
2266         ifp->if_softc = sc;
2267         ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
2268         ifp->if_ioctl = bge_ioctl;
2269         ifp->if_start = bge_start;
2270 #ifdef DEVICE_POLLING
2271         ifp->if_poll = bge_poll;
2272 #endif
2273         ifp->if_watchdog = bge_watchdog;
2274         ifp->if_init = bge_init;
2275         ifp->if_mtu = ETHERMTU;
2276         ifp->if_capabilities = IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU;
2277         ifq_set_maxlen(&ifp->if_snd, BGE_TX_RING_CNT - 1);
2278         ifq_set_ready(&ifp->if_snd);
2279
2280         /*
2281          * 5700 B0 chips do not support checksumming correctly due
2282          * to hardware bugs.
2283          */
2284         if (sc->bge_chipid != BGE_CHIPID_BCM5700_B0) {
2285                 ifp->if_capabilities |= IFCAP_HWCSUM;
2286                 ifp->if_hwassist = BGE_CSUM_FEATURES;
2287         }
2288         ifp->if_capenable = ifp->if_capabilities;
2289
2290         /*
2291          * Figure out what sort of media we have by checking the
2292          * hardware config word in the first 32k of NIC internal memory,
2293          * or fall back to examining the EEPROM if necessary.
2294          * Note: on some BCM5700 cards, this value appears to be unset.
2295          * If that's the case, we have to rely on identifying the NIC
2296          * by its PCI subsystem ID, as we do below for the SysKonnect
2297          * SK-9D41.
2298          */
2299         if (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_SIG) == BGE_MAGIC_NUMBER) {
2300                 hwcfg = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_NICCFG);
2301         } else {
2302                 if (bge_read_eeprom(sc, (caddr_t)&hwcfg, BGE_EE_HWCFG_OFFSET,
2303                                     sizeof(hwcfg))) {
2304                         device_printf(dev, "failed to read EEPROM\n");
2305                         error = ENXIO;
2306                         goto fail;
2307                 }
2308                 hwcfg = ntohl(hwcfg);
2309         }
2310
2311         /* The SysKonnect SK-9D41 is a 1000baseSX card. */
2312         if (pci_get_subvendor(dev) == PCI_PRODUCT_SCHNEIDERKOCH_SK_9D41 ||
2313             (hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER) {
2314                 if (BGE_IS_5714_FAMILY(sc))
2315                         sc->bge_flags |= BGE_FLAG_MII_SERDES;
2316                 else
2317                         sc->bge_flags |= BGE_FLAG_TBI;
2318         }
2319
2320         /* Setup MI MODE */
2321         if (sc->bge_flags & BGE_FLAG_CPMU)
2322                 sc->bge_mi_mode = BGE_MIMODE_500KHZ_CONST;
2323         else
2324                 sc->bge_mi_mode = BGE_MIMODE_BASE;
2325         if (BGE_IS_5700_FAMILY(sc) || sc->bge_asicrev == BGE_ASICREV_BCM5705) {
2326                 /* Enable auto polling for BCM570[0-5]. */
2327                 sc->bge_mi_mode |= BGE_MIMODE_AUTOPOLL;
2328         }
2329
2330         /* Setup link status update stuffs */
2331         if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
2332             sc->bge_chipid != BGE_CHIPID_BCM5700_B2) {
2333                 sc->bge_link_upd = bge_bcm5700_link_upd;
2334                 sc->bge_link_chg = BGE_MACSTAT_MI_INTERRUPT;
2335         } else if (sc->bge_flags & BGE_FLAG_TBI) {
2336                 sc->bge_link_upd = bge_tbi_link_upd;
2337                 sc->bge_link_chg = BGE_MACSTAT_LINK_CHANGED;
2338         } else if (sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) {
2339                 sc->bge_link_upd = bge_autopoll_link_upd;
2340                 sc->bge_link_chg = BGE_MACSTAT_LINK_CHANGED;
2341         } else {
2342                 sc->bge_link_upd = bge_copper_link_upd;
2343                 sc->bge_link_chg = BGE_MACSTAT_LINK_CHANGED;
2344         }
2345
2346         /*
2347          * Broadcom's own driver always assumes the internal
2348          * PHY is at GMII address 1.  On some chips, the PHY responds
2349          * to accesses at all addresses, which could cause us to
2350          * bogusly attach the PHY 32 times at probe type.  Always
2351          * restricting the lookup to address 1 is simpler than
2352          * trying to figure out which chips revisions should be
2353          * special-cased.
2354          */
2355         sc->bge_phyno = 1;
2356
2357         if (sc->bge_flags & BGE_FLAG_TBI) {
2358                 ifmedia_init(&sc->bge_ifmedia, IFM_IMASK,
2359                     bge_ifmedia_upd, bge_ifmedia_sts);
2360                 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL);
2361                 ifmedia_add(&sc->bge_ifmedia,
2362                     IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL);
2363                 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL);
2364                 ifmedia_set(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO);
2365                 sc->bge_ifmedia.ifm_media = sc->bge_ifmedia.ifm_cur->ifm_media;
2366         } else {
2367                 struct mii_probe_args mii_args;
2368
2369                 mii_probe_args_init(&mii_args, bge_ifmedia_upd, bge_ifmedia_sts);
2370                 mii_args.mii_probemask = 1 << sc->bge_phyno;
2371                 mii_args.mii_capmask = capmask;
2372                 mii_args.mii_privtag = MII_PRIVTAG_BRGPHY;
2373                 mii_args.mii_priv = mii_priv;
2374
2375                 error = mii_probe(dev, &sc->bge_miibus, &mii_args);
2376                 if (error) {
2377                         device_printf(dev, "MII without any PHY!\n");
2378                         goto fail;
2379                 }
2380         }
2381
2382         /*
2383          * Create sysctl nodes.
2384          */
2385         sysctl_ctx_init(&sc->bge_sysctl_ctx);
2386         sc->bge_sysctl_tree = SYSCTL_ADD_NODE(&sc->bge_sysctl_ctx,
2387                                               SYSCTL_STATIC_CHILDREN(_hw),
2388                                               OID_AUTO,
2389                                               device_get_nameunit(dev),
2390                                               CTLFLAG_RD, 0, "");
2391         if (sc->bge_sysctl_tree == NULL) {
2392                 device_printf(dev, "can't add sysctl node\n");
2393                 error = ENXIO;
2394                 goto fail;
2395         }
2396
2397         SYSCTL_ADD_PROC(&sc->bge_sysctl_ctx,
2398                         SYSCTL_CHILDREN(sc->bge_sysctl_tree),
2399                         OID_AUTO, "rx_coal_ticks",
2400                         CTLTYPE_INT | CTLFLAG_RW,
2401                         sc, 0, bge_sysctl_rx_coal_ticks, "I",
2402                         "Receive coalescing ticks (usec).");
2403         SYSCTL_ADD_PROC(&sc->bge_sysctl_ctx,
2404                         SYSCTL_CHILDREN(sc->bge_sysctl_tree),
2405                         OID_AUTO, "tx_coal_ticks",
2406                         CTLTYPE_INT | CTLFLAG_RW,
2407                         sc, 0, bge_sysctl_tx_coal_ticks, "I",
2408                         "Transmit coalescing ticks (usec).");
2409         SYSCTL_ADD_PROC(&sc->bge_sysctl_ctx,
2410                         SYSCTL_CHILDREN(sc->bge_sysctl_tree),
2411                         OID_AUTO, "rx_coal_bds",
2412                         CTLTYPE_INT | CTLFLAG_RW,
2413                         sc, 0, bge_sysctl_rx_coal_bds, "I",
2414                         "Receive max coalesced BD count.");
2415         SYSCTL_ADD_PROC(&sc->bge_sysctl_ctx,
2416                         SYSCTL_CHILDREN(sc->bge_sysctl_tree),
2417                         OID_AUTO, "tx_coal_bds",
2418                         CTLTYPE_INT | CTLFLAG_RW,
2419                         sc, 0, bge_sysctl_tx_coal_bds, "I",
2420                         "Transmit max coalesced BD count.");
2421         if (sc->bge_flags & BGE_FLAG_PCIE) {
2422                 /*
2423                  * A common design characteristic for many Broadcom
2424                  * client controllers is that they only support a
2425                  * single outstanding DMA read operation on the PCIe
2426                  * bus. This means that it will take twice as long to
2427                  * fetch a TX frame that is split into header and
2428                  * payload buffers as it does to fetch a single,
2429                  * contiguous TX frame (2 reads vs. 1 read). For these
2430                  * controllers, coalescing buffers to reduce the number
2431                  * of memory reads is effective way to get maximum
2432                  * performance(about 940Mbps).  Without collapsing TX
2433                  * buffers the maximum TCP bulk transfer performance
2434                  * is about 850Mbps. However forcing coalescing mbufs
2435                  * consumes a lot of CPU cycles, so leave it off by
2436                  * default.
2437                  */
2438                 SYSCTL_ADD_INT(&sc->bge_sysctl_ctx,
2439                                SYSCTL_CHILDREN(sc->bge_sysctl_tree),
2440                                OID_AUTO, "force_defrag", CTLFLAG_RW,
2441                                &sc->bge_force_defrag, 0,
2442                                "Force defragment on TX path");
2443         }
2444         if (sc->bge_flags & BGE_FLAG_STATUS_TAG) {
2445                 if (!BGE_IS_5705_PLUS(sc)) {
2446                         SYSCTL_ADD_PROC(&sc->bge_sysctl_ctx,
2447                             SYSCTL_CHILDREN(sc->bge_sysctl_tree), OID_AUTO,
2448                             "rx_coal_ticks_int", CTLTYPE_INT | CTLFLAG_RW,
2449                             sc, 0, bge_sysctl_rx_coal_ticks_int, "I",
2450                             "Receive coalescing ticks "
2451                             "during interrupt (usec).");
2452                         SYSCTL_ADD_PROC(&sc->bge_sysctl_ctx,
2453                             SYSCTL_CHILDREN(sc->bge_sysctl_tree), OID_AUTO,
2454                             "tx_coal_ticks_int", CTLTYPE_INT | CTLFLAG_RW,
2455                             sc, 0, bge_sysctl_tx_coal_ticks_int, "I",
2456                             "Transmit coalescing ticks "
2457                             "during interrupt (usec).");
2458                 }
2459                 SYSCTL_ADD_PROC(&sc->bge_sysctl_ctx,
2460                     SYSCTL_CHILDREN(sc->bge_sysctl_tree), OID_AUTO,
2461                     "rx_coal_bds_int", CTLTYPE_INT | CTLFLAG_RW,
2462                     sc, 0, bge_sysctl_rx_coal_bds_int, "I",
2463                     "Receive max coalesced BD count during interrupt.");
2464                 SYSCTL_ADD_PROC(&sc->bge_sysctl_ctx,
2465                     SYSCTL_CHILDREN(sc->bge_sysctl_tree), OID_AUTO,
2466                     "tx_coal_bds_int", CTLTYPE_INT | CTLFLAG_RW,
2467                     sc, 0, bge_sysctl_tx_coal_bds_int, "I",
2468                     "Transmit max coalesced BD count during interrupt.");
2469         }
2470
2471         /*
2472          * Call MI attach routine.
2473          */
2474         ether_ifattach(ifp, ether_addr, NULL);
2475
2476         if (sc->bge_flags & BGE_FLAG_STATUS_TAG)
2477                 intr_func = bge_intr_status_tag;
2478         else
2479                 intr_func = bge_intr;
2480
2481         error = bus_setup_intr(dev, sc->bge_irq, INTR_MPSAFE, intr_func, sc,
2482             &sc->bge_intrhand, ifp->if_serializer);
2483         if (error) {
2484                 ether_ifdetach(ifp);
2485                 device_printf(dev, "couldn't set up irq\n");
2486                 goto fail;
2487         }
2488
2489         ifp->if_cpuid = rman_get_cpuid(sc->bge_irq);
2490         KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus);
2491
2492         return(0);
2493 fail:
2494         bge_detach(dev);
2495         return(error);
2496 }
2497
2498 static int
2499 bge_detach(device_t dev)
2500 {
2501         struct bge_softc *sc = device_get_softc(dev);
2502
2503         if (device_is_attached(dev)) {
2504                 struct ifnet *ifp = &sc->arpcom.ac_if;
2505
2506                 lwkt_serialize_enter(ifp->if_serializer);
2507                 bge_stop(sc);
2508                 bge_reset(sc);
2509                 bus_teardown_intr(dev, sc->bge_irq, sc->bge_intrhand);
2510                 lwkt_serialize_exit(ifp->if_serializer);
2511
2512                 ether_ifdetach(ifp);
2513         }
2514
2515         if (sc->bge_flags & BGE_FLAG_TBI)
2516                 ifmedia_removeall(&sc->bge_ifmedia);
2517         if (sc->bge_miibus)
2518                 device_delete_child(dev, sc->bge_miibus);
2519         bus_generic_detach(dev);
2520
2521         if (sc->bge_irq != NULL)
2522                 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->bge_irq);
2523
2524         if (sc->bge_res != NULL)
2525                 bus_release_resource(dev, SYS_RES_MEMORY,
2526                     BGE_PCI_BAR0, sc->bge_res);
2527
2528         if (sc->bge_sysctl_tree != NULL)
2529                 sysctl_ctx_free(&sc->bge_sysctl_ctx);
2530
2531         bge_dma_free(sc);
2532
2533         return 0;
2534 }
2535
2536 static void
2537 bge_reset(struct bge_softc *sc)
2538 {
2539         device_t dev;
2540         uint32_t cachesize, command, pcistate, reset;
2541         void (*write_op)(struct bge_softc *, uint32_t, uint32_t);
2542         int i, val = 0;
2543
2544         dev = sc->bge_dev;
2545
2546         if (BGE_IS_575X_PLUS(sc) && !BGE_IS_5714_FAMILY(sc) &&
2547             sc->bge_asicrev != BGE_ASICREV_BCM5906) {
2548                 if (sc->bge_flags & BGE_FLAG_PCIE)
2549                         write_op = bge_writemem_direct;
2550                 else
2551                         write_op = bge_writemem_ind;
2552         } else {
2553                 write_op = bge_writereg_ind;
2554         }
2555
2556         /* Save some important PCI state. */
2557         cachesize = pci_read_config(dev, BGE_PCI_CACHESZ, 4);
2558         command = pci_read_config(dev, BGE_PCI_CMD, 4);
2559         pcistate = pci_read_config(dev, BGE_PCI_PCISTATE, 4);
2560
2561         pci_write_config(dev, BGE_PCI_MISC_CTL,
2562             BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR|
2563             BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_PCISTATE_RW|
2564             sc->bge_pci_miscctl, 4);
2565
2566         /* Disable fastboot on controllers that support it. */
2567         if (sc->bge_asicrev == BGE_ASICREV_BCM5752 ||
2568             BGE_IS_5755_PLUS(sc)) {
2569                 if (bootverbose)
2570                         if_printf(&sc->arpcom.ac_if, "Disabling fastboot\n");
2571                 CSR_WRITE_4(sc, BGE_FASTBOOT_PC, 0x0);
2572         }
2573
2574         /*
2575          * Write the magic number to SRAM at offset 0xB50.
2576          * When firmware finishes its initialization it will
2577          * write ~BGE_MAGIC_NUMBER to the same location.
2578          */
2579         bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER);
2580
2581         reset = BGE_MISCCFG_RESET_CORE_CLOCKS|(65<<1);
2582
2583         /* XXX: Broadcom Linux driver. */
2584         if (sc->bge_flags & BGE_FLAG_PCIE) {
2585                 if (CSR_READ_4(sc, 0x7e2c) == 0x60)     /* PCIE 1.0 */
2586                         CSR_WRITE_4(sc, 0x7e2c, 0x20);
2587                 if (sc->bge_chipid != BGE_CHIPID_BCM5750_A0) {
2588                         /* Prevent PCIE link training during global reset */
2589                         CSR_WRITE_4(sc, BGE_MISC_CFG, (1<<29));
2590                         reset |= (1<<29);
2591                 }
2592         }
2593
2594         /* 
2595          * Set GPHY Power Down Override to leave GPHY
2596          * powered up in D0 uninitialized.
2597          */
2598         if (BGE_IS_5705_PLUS(sc) && (sc->bge_flags & BGE_FLAG_CPMU) == 0)
2599                 reset |= BGE_MISCCFG_GPHY_PD_OVERRIDE;
2600
2601         /* Issue global reset */
2602         write_op(sc, BGE_MISC_CFG, reset);
2603
2604         if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
2605                 uint32_t status, ctrl;
2606
2607                 status = CSR_READ_4(sc, BGE_VCPU_STATUS);
2608                 CSR_WRITE_4(sc, BGE_VCPU_STATUS,
2609                     status | BGE_VCPU_STATUS_DRV_RESET);
2610                 ctrl = CSR_READ_4(sc, BGE_VCPU_EXT_CTRL);
2611                 CSR_WRITE_4(sc, BGE_VCPU_EXT_CTRL,
2612                     ctrl & ~BGE_VCPU_EXT_CTRL_HALT_CPU);
2613         }
2614
2615         DELAY(1000);
2616
2617         /* XXX: Broadcom Linux driver. */
2618         if (sc->bge_flags & BGE_FLAG_PCIE) {
2619                 uint16_t devctl;
2620
2621                 if (sc->bge_chipid == BGE_CHIPID_BCM5750_A0) {
2622                         uint32_t v;
2623
2624                         DELAY(500000); /* wait for link training to complete */
2625                         v = pci_read_config(dev, 0xc4, 4);
2626                         pci_write_config(dev, 0xc4, v | (1<<15), 4);
2627                 }
2628
2629                 /* Clear enable no snoop and disable relaxed ordering. */
2630                 devctl = pci_read_config(dev,
2631                     sc->bge_pciecap + PCIER_DEVCTRL, 2);
2632                 devctl &= ~(PCIEM_DEVCTL_RELAX_ORDER | PCIEM_DEVCTL_NOSNOOP);
2633                 pci_write_config(dev, sc->bge_pciecap + PCIER_DEVCTRL,
2634                     devctl, 2);
2635
2636                 /* Clear error status. */
2637                 pci_write_config(dev, sc->bge_pciecap + PCIER_DEVSTS,
2638                     PCIEM_DEVSTS_CORR_ERR |
2639                     PCIEM_DEVSTS_NFATAL_ERR |
2640                     PCIEM_DEVSTS_FATAL_ERR |
2641                     PCIEM_DEVSTS_UNSUPP_REQ, 2);
2642         }
2643
2644         /* Reset some of the PCI state that got zapped by reset */
2645         pci_write_config(dev, BGE_PCI_MISC_CTL,
2646             BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR|
2647             BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_PCISTATE_RW|
2648             sc->bge_pci_miscctl, 4);
2649         pci_write_config(dev, BGE_PCI_CACHESZ, cachesize, 4);
2650         pci_write_config(dev, BGE_PCI_CMD, command, 4);
2651         write_op(sc, BGE_MISC_CFG, (65 << 1));
2652
2653         /*
2654          * Disable PCI-X relaxed ordering to ensure status block update
2655          * comes first then packet buffer DMA. Otherwise driver may
2656          * read stale status block.
2657          */
2658         if (sc->bge_flags & BGE_FLAG_PCIX) {
2659                 uint16_t devctl;
2660
2661                 devctl = pci_read_config(dev,
2662                     sc->bge_pcixcap + PCIXR_COMMAND, 2);
2663                 devctl &= ~PCIXM_COMMAND_ERO;
2664                 if (sc->bge_asicrev == BGE_ASICREV_BCM5703) {
2665                         devctl &= ~PCIXM_COMMAND_MAX_READ;
2666                         devctl |= PCIXM_COMMAND_MAX_READ_2048;
2667                 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5704) {
2668                         devctl &= ~(PCIXM_COMMAND_MAX_SPLITS |
2669                             PCIXM_COMMAND_MAX_READ);
2670                         devctl |= PCIXM_COMMAND_MAX_READ_2048;
2671                 }
2672                 pci_write_config(dev, sc->bge_pcixcap + PCIXR_COMMAND,
2673                     devctl, 2);
2674         }
2675
2676         /* Enable memory arbiter. */
2677         if (BGE_IS_5714_FAMILY(sc)) {
2678                 uint32_t val;
2679
2680                 val = CSR_READ_4(sc, BGE_MARB_MODE);
2681                 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE | val);
2682         } else {
2683                 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
2684         }
2685
2686         if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
2687                 for (i = 0; i < BGE_TIMEOUT; i++) {
2688                         val = CSR_READ_4(sc, BGE_VCPU_STATUS);
2689                         if (val & BGE_VCPU_STATUS_INIT_DONE)
2690                                 break;
2691                         DELAY(100);
2692                 }
2693                 if (i == BGE_TIMEOUT) {
2694                         if_printf(&sc->arpcom.ac_if, "reset timed out\n");
2695                         return;
2696                 }
2697         } else {
2698                 /*
2699                  * Poll until we see the 1's complement of the magic number.
2700                  * This indicates that the firmware initialization
2701                  * is complete.
2702                  */
2703                 for (i = 0; i < BGE_FIRMWARE_TIMEOUT; i++) {
2704                         val = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM);
2705                         if (val == ~BGE_MAGIC_NUMBER)
2706                                 break;
2707                         DELAY(10);
2708                 }
2709                 if (i == BGE_FIRMWARE_TIMEOUT) {
2710                         if_printf(&sc->arpcom.ac_if, "firmware handshake "
2711                                   "timed out, found 0x%08x\n", val);
2712                         return;
2713                 }
2714         }
2715
2716         /*
2717          * XXX Wait for the value of the PCISTATE register to
2718          * return to its original pre-reset state. This is a
2719          * fairly good indicator of reset completion. If we don't
2720          * wait for the reset to fully complete, trying to read
2721          * from the device's non-PCI registers may yield garbage
2722          * results.
2723          */
2724         for (i = 0; i < BGE_TIMEOUT; i++) {
2725                 if (pci_read_config(dev, BGE_PCI_PCISTATE, 4) == pcistate)
2726                         break;
2727                 DELAY(10);
2728         }
2729
2730         /* Fix up byte swapping */
2731         CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS |
2732             BGE_MODECTL_BYTESWAP_DATA);
2733
2734         CSR_WRITE_4(sc, BGE_MAC_MODE, 0);
2735
2736         /*
2737          * The 5704 in TBI mode apparently needs some special
2738          * adjustment to insure the SERDES drive level is set
2739          * to 1.2V.
2740          */
2741         if (sc->bge_asicrev == BGE_ASICREV_BCM5704 &&
2742             (sc->bge_flags & BGE_FLAG_TBI)) {
2743                 uint32_t serdescfg;
2744
2745                 serdescfg = CSR_READ_4(sc, BGE_SERDES_CFG);
2746                 serdescfg = (serdescfg & ~0xFFF) | 0x880;
2747                 CSR_WRITE_4(sc, BGE_SERDES_CFG, serdescfg);
2748         }
2749
2750         /* XXX: Broadcom Linux driver. */
2751         if ((sc->bge_flags & BGE_FLAG_PCIE) &&
2752             sc->bge_chipid != BGE_CHIPID_BCM5750_A0 &&
2753             sc->bge_asicrev != BGE_ASICREV_BCM5785) {
2754                 uint32_t v;
2755
2756                 /* Enable Data FIFO protection. */
2757                 v = CSR_READ_4(sc, 0x7c00);
2758                 CSR_WRITE_4(sc, 0x7c00, v | (1<<25));
2759         }
2760
2761         DELAY(10000);
2762 }
2763
2764 /*
2765  * Frame reception handling. This is called if there's a frame
2766  * on the receive return list.
2767  *
2768  * Note: we have to be able to handle two possibilities here:
2769  * 1) the frame is from the jumbo recieve ring
2770  * 2) the frame is from the standard receive ring
2771  */
2772
2773 static void
2774 bge_rxeof(struct bge_softc *sc, uint16_t rx_prod)
2775 {
2776         struct ifnet *ifp;
2777         int stdcnt = 0, jumbocnt = 0;
2778
2779         ifp = &sc->arpcom.ac_if;
2780
2781         while (sc->bge_rx_saved_considx != rx_prod) {
2782                 struct bge_rx_bd        *cur_rx;
2783                 uint32_t                rxidx;
2784                 struct mbuf             *m = NULL;
2785                 uint16_t                vlan_tag = 0;
2786                 int                     have_tag = 0;
2787
2788                 cur_rx =
2789             &sc->bge_ldata.bge_rx_return_ring[sc->bge_rx_saved_considx];
2790
2791                 rxidx = cur_rx->bge_idx;
2792                 BGE_INC(sc->bge_rx_saved_considx, sc->bge_return_ring_cnt);
2793                 logif(rx_pkt);
2794
2795                 if (cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) {
2796                         have_tag = 1;
2797                         vlan_tag = cur_rx->bge_vlan_tag;
2798                 }
2799
2800                 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) {
2801                         BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT);
2802                         jumbocnt++;
2803
2804                         if (rxidx != sc->bge_jumbo) {
2805                                 ifp->if_ierrors++;
2806                                 if_printf(ifp, "sw jumbo index(%d) "
2807                                     "and hw jumbo index(%d) mismatch, drop!\n",
2808                                     sc->bge_jumbo, rxidx);
2809                                 bge_setup_rxdesc_jumbo(sc, rxidx);
2810                                 continue;
2811                         }
2812
2813                         m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx].bge_mbuf;
2814                         if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
2815                                 ifp->if_ierrors++;
2816                                 bge_setup_rxdesc_jumbo(sc, sc->bge_jumbo);
2817                                 continue;
2818                         }
2819                         if (bge_newbuf_jumbo(sc, sc->bge_jumbo, 0)) {
2820                                 ifp->if_ierrors++;
2821                                 bge_setup_rxdesc_jumbo(sc, sc->bge_jumbo);
2822                                 continue;
2823                         }
2824                 } else {
2825                         BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT);
2826                         stdcnt++;
2827
2828                         if (rxidx != sc->bge_std) {
2829                                 ifp->if_ierrors++;
2830                                 if_printf(ifp, "sw std index(%d) "
2831                                     "and hw std index(%d) mismatch, drop!\n",
2832                                     sc->bge_std, rxidx);
2833                                 bge_setup_rxdesc_std(sc, rxidx);
2834                                 continue;
2835                         }
2836
2837                         m = sc->bge_cdata.bge_rx_std_chain[rxidx].bge_mbuf;
2838                         if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
2839                                 ifp->if_ierrors++;
2840                                 bge_setup_rxdesc_std(sc, sc->bge_std);
2841                                 continue;
2842                         }
2843                         if (bge_newbuf_std(sc, sc->bge_std, 0)) {
2844                                 ifp->if_ierrors++;
2845                                 bge_setup_rxdesc_std(sc, sc->bge_std);
2846                                 continue;
2847                         }
2848                 }
2849
2850                 ifp->if_ipackets++;
2851 #if !defined(__i386__) && !defined(__x86_64__)
2852                 /*
2853                  * The x86 allows unaligned accesses, but for other
2854                  * platforms we must make sure the payload is aligned.
2855                  */
2856                 if (sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) {
2857                         bcopy(m->m_data, m->m_data + ETHER_ALIGN,
2858                             cur_rx->bge_len);
2859                         m->m_data += ETHER_ALIGN;
2860                 }
2861 #endif
2862                 m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN;
2863                 m->m_pkthdr.rcvif = ifp;
2864
2865                 if (ifp->if_capenable & IFCAP_RXCSUM) {
2866                         if (cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) {
2867                                 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
2868                                 if ((cur_rx->bge_ip_csum ^ 0xffff) == 0)
2869                                         m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
2870                         }
2871                         if ((cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM) &&
2872                             m->m_pkthdr.len >= BGE_MIN_FRAMELEN) {
2873                                 m->m_pkthdr.csum_data =
2874                                         cur_rx->bge_tcp_udp_csum;
2875                                 m->m_pkthdr.csum_flags |=
2876                                         CSUM_DATA_VALID | CSUM_PSEUDO_HDR;
2877                         }
2878                 }
2879
2880                 /*
2881                  * If we received a packet with a vlan tag, pass it
2882                  * to vlan_input() instead of ether_input().
2883                  */
2884                 if (have_tag) {
2885                         m->m_flags |= M_VLANTAG;
2886                         m->m_pkthdr.ether_vlantag = vlan_tag;
2887                         have_tag = vlan_tag = 0;
2888                 }
2889                 ifp->if_input(ifp, m);
2890         }
2891
2892         bge_writembx(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx);
2893         if (stdcnt)
2894                 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std);
2895         if (jumbocnt)
2896                 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo);
2897 }
2898
2899 static void
2900 bge_txeof(struct bge_softc *sc, uint16_t tx_cons)
2901 {
2902         struct bge_tx_bd *cur_tx = NULL;
2903         struct ifnet *ifp;
2904
2905         ifp = &sc->arpcom.ac_if;
2906
2907         /*
2908          * Go through our tx ring and free mbufs for those
2909          * frames that have been sent.
2910          */
2911         while (sc->bge_tx_saved_considx != tx_cons) {
2912                 uint32_t idx = 0;
2913
2914                 idx = sc->bge_tx_saved_considx;
2915                 cur_tx = &sc->bge_ldata.bge_tx_ring[idx];
2916                 if (cur_tx->bge_flags & BGE_TXBDFLAG_END)
2917                         ifp->if_opackets++;
2918                 if (sc->bge_cdata.bge_tx_chain[idx] != NULL) {
2919                         bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag,
2920                             sc->bge_cdata.bge_tx_dmamap[idx]);
2921                         m_freem(sc->bge_cdata.bge_tx_chain[idx]);
2922                         sc->bge_cdata.bge_tx_chain[idx] = NULL;
2923                 }
2924                 sc->bge_txcnt--;
2925                 BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT);
2926                 logif(tx_pkt);
2927         }
2928
2929         if (cur_tx != NULL &&
2930             (BGE_TX_RING_CNT - sc->bge_txcnt) >=
2931             (BGE_NSEG_RSVD + BGE_NSEG_SPARE))
2932                 ifp->if_flags &= ~IFF_OACTIVE;
2933
2934         if (sc->bge_txcnt == 0)
2935                 ifp->if_timer = 0;
2936
2937         if (!ifq_is_empty(&ifp->if_snd))
2938                 if_devstart(ifp);
2939 }
2940
2941 #ifdef DEVICE_POLLING
2942
2943 static void
2944 bge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
2945 {
2946         struct bge_softc *sc = ifp->if_softc;
2947         struct bge_status_block *sblk = sc->bge_ldata.bge_status_block;
2948         uint16_t rx_prod, tx_cons;
2949
2950         switch(cmd) {
2951         case POLL_REGISTER:
2952                 bge_disable_intr(sc);
2953                 break;
2954         case POLL_DEREGISTER:
2955                 bge_enable_intr(sc);
2956                 break;
2957         case POLL_AND_CHECK_STATUS:
2958                 /*
2959                  * Process link state changes.
2960                  */
2961                 bge_link_poll(sc);
2962                 /* Fall through */
2963         case POLL_ONLY:
2964                 if (sc->bge_flags & BGE_FLAG_STATUS_TAG) {
2965                         sc->bge_status_tag = sblk->bge_status_tag;
2966                         /*
2967                          * Use a load fence to ensure that status_tag
2968                          * is saved  before rx_prod and tx_cons.
2969                          */
2970                         cpu_lfence();
2971                 }
2972                 rx_prod = sblk->bge_idx[0].bge_rx_prod_idx;
2973                 tx_cons = sblk->bge_idx[0].bge_tx_cons_idx;
2974                 if (ifp->if_flags & IFF_RUNNING) {
2975                         rx_prod = sblk->bge_idx[0].bge_rx_prod_idx;
2976                         if (sc->bge_rx_saved_considx != rx_prod)
2977                                 bge_rxeof(sc, rx_prod);
2978
2979                         tx_cons = sblk->bge_idx[0].bge_tx_cons_idx;
2980                         if (sc->bge_tx_saved_considx != tx_cons)
2981                                 bge_txeof(sc, tx_cons);
2982                 }
2983                 break;
2984         }
2985 }
2986
2987 #endif
2988
2989 static void
2990 bge_intr(void *xsc)
2991 {
2992         struct bge_softc *sc = xsc;
2993         struct ifnet *ifp = &sc->arpcom.ac_if;
2994
2995         logif(intr);
2996
2997         /*
2998          * Ack the interrupt by writing something to BGE_MBX_IRQ0_LO.  Don't
2999          * disable interrupts by writing nonzero like we used to, since with
3000          * our current organization this just gives complications and
3001          * pessimizations for re-enabling interrupts.  We used to have races
3002          * instead of the necessary complications.  Disabling interrupts
3003          * would just reduce the chance of a status update while we are
3004          * running (by switching to the interrupt-mode coalescence
3005          * parameters), but this chance is already very low so it is more
3006          * efficient to get another interrupt than prevent it.
3007          *
3008          * We do the ack first to ensure another interrupt if there is a
3009          * status update after the ack.  We don't check for the status
3010          * changing later because it is more efficient to get another
3011          * interrupt than prevent it, not quite as above (not checking is
3012          * a smaller optimization than not toggling the interrupt enable,
3013          * since checking doesn't involve PCI accesses and toggling require
3014          * the status check).  So toggling would probably be a pessimization
3015          * even with MSI.  It would only be needed for using a task queue.
3016          */
3017         bge_writembx(sc, BGE_MBX_IRQ0_LO, 0);
3018
3019         /*
3020          * Process link state changes.
3021          */
3022         bge_link_poll(sc);
3023
3024         if (ifp->if_flags & IFF_RUNNING) {
3025                 struct bge_status_block *sblk = sc->bge_ldata.bge_status_block;
3026                 uint16_t rx_prod, tx_cons;
3027
3028                 rx_prod = sblk->bge_idx[0].bge_rx_prod_idx;
3029                 if (sc->bge_rx_saved_considx != rx_prod)
3030                         bge_rxeof(sc, rx_prod);
3031
3032                 tx_cons = sblk->bge_idx[0].bge_tx_cons_idx;
3033                 if (sc->bge_tx_saved_considx != tx_cons)
3034                         bge_txeof(sc, tx_cons);
3035         }
3036
3037         if (sc->bge_coal_chg)
3038                 bge_coal_change(sc);
3039 }
3040
3041 static void
3042 bge_intr_status_tag(void *xsc)
3043 {
3044         struct bge_softc *sc = xsc;
3045         struct ifnet *ifp = &sc->arpcom.ac_if;
3046         struct bge_status_block *sblk = sc->bge_ldata.bge_status_block;
3047         uint16_t rx_prod, tx_cons;
3048         uint32_t status;
3049
3050         if (sc->bge_status_tag == sblk->bge_status_tag) {
3051                 uint32_t val;
3052
3053                 val = pci_read_config(sc->bge_dev, BGE_PCI_PCISTATE, 4);
3054                 if (val & BGE_PCISTAT_INTR_NOTACT)
3055                         return;
3056         }
3057
3058         /*
3059          * NOTE:
3060          * Interrupt will have to be disabled if tagged status
3061          * is used, else interrupt will always be asserted on
3062          * certain chips (at least on BCM5750 AX/BX).
3063          */
3064         bge_writembx(sc, BGE_MBX_IRQ0_LO, 1);
3065
3066         sc->bge_status_tag = sblk->bge_status_tag;
3067         /*
3068          * Use a load fence to ensure that status_tag is saved 
3069          * before rx_prod, tx_cons and status.
3070          */
3071         cpu_lfence();
3072
3073         rx_prod = sblk->bge_idx[0].bge_rx_prod_idx;
3074         tx_cons = sblk->bge_idx[0].bge_tx_cons_idx;
3075         status = sblk->bge_status;
3076
3077         if ((status & BGE_STATFLAG_LINKSTATE_CHANGED) || sc->bge_link_evt)
3078                 bge_link_poll(sc);
3079
3080         if (ifp->if_flags & IFF_RUNNING) {
3081                 if (sc->bge_rx_saved_considx != rx_prod)
3082                         bge_rxeof(sc, rx_prod);
3083
3084                 if (sc->bge_tx_saved_considx != tx_cons)
3085                         bge_txeof(sc, tx_cons);
3086         }
3087
3088         bge_writembx(sc, BGE_MBX_IRQ0_LO, sc->bge_status_tag << 24);
3089
3090         if (sc->bge_coal_chg)
3091                 bge_coal_change(sc);
3092 }
3093
3094 static void
3095 bge_tick(void *xsc)
3096 {
3097         struct bge_softc *sc = xsc;
3098         struct ifnet *ifp = &sc->arpcom.ac_if;
3099
3100         lwkt_serialize_enter(ifp->if_serializer);
3101
3102         if (BGE_IS_5705_PLUS(sc))
3103                 bge_stats_update_regs(sc);
3104         else
3105                 bge_stats_update(sc);
3106
3107         if (sc->bge_flags & BGE_FLAG_TBI) {
3108                 /*
3109                  * Since in TBI mode auto-polling can't be used we should poll
3110                  * link status manually. Here we register pending link event
3111                  * and trigger interrupt.
3112                  */
3113                 sc->bge_link_evt++;
3114                 if (BGE_IS_CRIPPLED(sc))
3115                         BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET);
3116                 else
3117                         BGE_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW);
3118         } else if (!sc->bge_link) {
3119                 mii_tick(device_get_softc(sc->bge_miibus));
3120         }
3121
3122         callout_reset(&sc->bge_stat_timer, hz, bge_tick, sc);
3123
3124         lwkt_serialize_exit(ifp->if_serializer);
3125 }
3126
3127 static void
3128 bge_stats_update_regs(struct bge_softc *sc)
3129 {
3130         struct ifnet *ifp = &sc->arpcom.ac_if;
3131         struct bge_mac_stats_regs stats;
3132         uint32_t *s;
3133         int i;
3134
3135         s = (uint32_t *)&stats;
3136         for (i = 0; i < sizeof(struct bge_mac_stats_regs); i += 4) {
3137                 *s = CSR_READ_4(sc, BGE_RX_STATS + i);
3138                 s++;
3139         }
3140
3141         ifp->if_collisions +=
3142            (stats.dot3StatsSingleCollisionFrames +
3143            stats.dot3StatsMultipleCollisionFrames +
3144            stats.dot3StatsExcessiveCollisions +
3145            stats.dot3StatsLateCollisions) -
3146            ifp->if_collisions;
3147 }
3148
3149 static void
3150 bge_stats_update(struct bge_softc *sc)
3151 {
3152         struct ifnet *ifp = &sc->arpcom.ac_if;
3153         bus_size_t stats;
3154
3155         stats = BGE_MEMWIN_START + BGE_STATS_BLOCK;
3156
3157 #define READ_STAT(sc, stats, stat)      \
3158         CSR_READ_4(sc, stats + offsetof(struct bge_stats, stat))
3159
3160         ifp->if_collisions +=
3161            (READ_STAT(sc, stats,
3162                 txstats.dot3StatsSingleCollisionFrames.bge_addr_lo) +
3163             READ_STAT(sc, stats,
3164                 txstats.dot3StatsMultipleCollisionFrames.bge_addr_lo) +
3165             READ_STAT(sc, stats,
3166                 txstats.dot3StatsExcessiveCollisions.bge_addr_lo) +
3167             READ_STAT(sc, stats,
3168                 txstats.dot3StatsLateCollisions.bge_addr_lo)) -
3169            ifp->if_collisions;
3170
3171 #undef READ_STAT
3172
3173 #ifdef notdef
3174         ifp->if_collisions +=
3175            (sc->bge_rdata->bge_info.bge_stats.dot3StatsSingleCollisionFrames +
3176            sc->bge_rdata->bge_info.bge_stats.dot3StatsMultipleCollisionFrames +
3177            sc->bge_rdata->bge_info.bge_stats.dot3StatsExcessiveCollisions +
3178            sc->bge_rdata->bge_info.bge_stats.dot3StatsLateCollisions) -
3179            ifp->if_collisions;
3180 #endif
3181 }
3182
3183 /*
3184  * Encapsulate an mbuf chain in the tx ring  by coupling the mbuf data
3185  * pointers to descriptors.
3186  */
3187 static int
3188 bge_encap(struct bge_softc *sc, struct mbuf **m_head0, uint32_t *txidx)
3189 {
3190         struct bge_tx_bd *d = NULL;
3191         uint16_t csum_flags = 0;
3192         bus_dma_segment_t segs[BGE_NSEG_NEW];
3193         bus_dmamap_t map;
3194         int error, maxsegs, nsegs, idx, i;
3195         struct mbuf *m_head = *m_head0, *m_new;
3196
3197         if (m_head->m_pkthdr.csum_flags) {
3198                 if (m_head->m_pkthdr.csum_flags & CSUM_IP)
3199                         csum_flags |= BGE_TXBDFLAG_IP_CSUM;
3200                 if (m_head->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP))
3201                         csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM;
3202                 if (m_head->m_flags & M_LASTFRAG)
3203                         csum_flags |= BGE_TXBDFLAG_IP_FRAG_END;
3204                 else if (m_head->m_flags & M_FRAG)
3205                         csum_flags |= BGE_TXBDFLAG_IP_FRAG;
3206         }
3207
3208         idx = *txidx;
3209         map = sc->bge_cdata.bge_tx_dmamap[idx];
3210
3211         maxsegs = (BGE_TX_RING_CNT - sc->bge_txcnt) - BGE_NSEG_RSVD;
3212         KASSERT(maxsegs >= BGE_NSEG_SPARE,
3213                 ("not enough segments %d", maxsegs));
3214
3215         if (maxsegs > BGE_NSEG_NEW)
3216                 maxsegs = BGE_NSEG_NEW;
3217
3218         /*
3219          * Pad outbound frame to BGE_MIN_FRAMELEN for an unusual reason.
3220          * The bge hardware will pad out Tx runts to BGE_MIN_FRAMELEN,
3221          * but when such padded frames employ the bge IP/TCP checksum
3222          * offload, the hardware checksum assist gives incorrect results
3223          * (possibly from incorporating its own padding into the UDP/TCP
3224          * checksum; who knows).  If we pad such runts with zeros, the
3225          * onboard checksum comes out correct.
3226          */
3227         if ((csum_flags & BGE_TXBDFLAG_TCP_UDP_CSUM) &&
3228             m_head->m_pkthdr.len < BGE_MIN_FRAMELEN) {
3229                 error = m_devpad(m_head, BGE_MIN_FRAMELEN);
3230                 if (error)
3231                         goto back;
3232         }
3233
3234         if ((sc->bge_flags & BGE_FLAG_SHORTDMA) && m_head->m_next != NULL) {
3235                 m_new = bge_defrag_shortdma(m_head);
3236                 if (m_new == NULL) {
3237                         error = ENOBUFS;
3238                         goto back;
3239                 }
3240                 *m_head0 = m_head = m_new;
3241         }
3242         if (sc->bge_force_defrag && (sc->bge_flags & BGE_FLAG_PCIE) &&
3243             m_head->m_next != NULL) {
3244                 /*
3245                  * Forcefully defragment mbuf chain to overcome hardware
3246                  * limitation which only support a single outstanding
3247                  * DMA read operation.  If it fails, keep moving on using
3248                  * the original mbuf chain.
3249                  */
3250                 m_new = m_defrag(m_head, MB_DONTWAIT);
3251                 if (m_new != NULL)
3252                         *m_head0 = m_head = m_new;
3253         }
3254
3255         error = bus_dmamap_load_mbuf_defrag(sc->bge_cdata.bge_tx_mtag, map,
3256                         m_head0, segs, maxsegs, &nsegs, BUS_DMA_NOWAIT);
3257         if (error)
3258                 goto back;
3259
3260         m_head = *m_head0;
3261         bus_dmamap_sync(sc->bge_cdata.bge_tx_mtag, map, BUS_DMASYNC_PREWRITE);
3262
3263         for (i = 0; ; i++) {
3264                 d = &sc->bge_ldata.bge_tx_ring[idx];
3265
3266                 d->bge_addr.bge_addr_lo = BGE_ADDR_LO(segs[i].ds_addr);
3267                 d->bge_addr.bge_addr_hi = BGE_ADDR_HI(segs[i].ds_addr);
3268                 d->bge_len = segs[i].ds_len;
3269                 d->bge_flags = csum_flags;
3270
3271                 if (i == nsegs - 1)
3272                         break;
3273                 BGE_INC(idx, BGE_TX_RING_CNT);
3274         }
3275         /* Mark the last segment as end of packet... */
3276         d->bge_flags |= BGE_TXBDFLAG_END;
3277
3278         /* Set vlan tag to the first segment of the packet. */
3279         d = &sc->bge_ldata.bge_tx_ring[*txidx];
3280         if (m_head->m_flags & M_VLANTAG) {
3281                 d->bge_flags |= BGE_TXBDFLAG_VLAN_TAG;
3282                 d->bge_vlan_tag = m_head->m_pkthdr.ether_vlantag;
3283         } else {
3284                 d->bge_vlan_tag = 0;
3285         }
3286
3287         /*
3288          * Insure that the map for this transmission is placed at
3289          * the array index of the last descriptor in this chain.
3290          */
3291         sc->bge_cdata.bge_tx_dmamap[*txidx] = sc->bge_cdata.bge_tx_dmamap[idx];
3292         sc->bge_cdata.bge_tx_dmamap[idx] = map;
3293         sc->bge_cdata.bge_tx_chain[idx] = m_head;
3294         sc->bge_txcnt += nsegs;
3295
3296         BGE_INC(idx, BGE_TX_RING_CNT);
3297         *txidx = idx;
3298 back:
3299         if (error) {
3300                 m_freem(*m_head0);
3301                 *m_head0 = NULL;
3302         }
3303         return error;
3304 }
3305
3306 /*
3307  * Main transmit routine. To avoid having to do mbuf copies, we put pointers
3308  * to the mbuf data regions directly in the transmit descriptors.
3309  */
3310 static void
3311 bge_start(struct ifnet *ifp)
3312 {
3313         struct bge_softc *sc = ifp->if_softc;
3314         struct mbuf *m_head = NULL;
3315         uint32_t prodidx;
3316         int need_trans;
3317
3318         if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING)
3319                 return;
3320
3321         prodidx = sc->bge_tx_prodidx;
3322
3323         need_trans = 0;
3324         while (sc->bge_cdata.bge_tx_chain[prodidx] == NULL) {
3325                 m_head = ifq_dequeue(&ifp->if_snd, NULL);
3326                 if (m_head == NULL)
3327                         break;
3328
3329                 /*
3330                  * XXX
3331                  * The code inside the if() block is never reached since we
3332                  * must mark CSUM_IP_FRAGS in our if_hwassist to start getting
3333                  * requests to checksum TCP/UDP in a fragmented packet.
3334                  * 
3335                  * XXX
3336                  * safety overkill.  If this is a fragmented packet chain
3337                  * with delayed TCP/UDP checksums, then only encapsulate
3338                  * it if we have enough descriptors to handle the entire
3339                  * chain at once.
3340                  * (paranoia -- may not actually be needed)
3341                  */
3342                 if ((m_head->m_flags & M_FIRSTFRAG) &&
3343                     (m_head->m_pkthdr.csum_flags & CSUM_DELAY_DATA)) {
3344                         if ((BGE_TX_RING_CNT - sc->bge_txcnt) <
3345                             m_head->m_pkthdr.csum_data + BGE_NSEG_RSVD) {
3346                                 ifp->if_flags |= IFF_OACTIVE;
3347                                 ifq_prepend(&ifp->if_snd, m_head);
3348                                 break;
3349                         }
3350                 }
3351
3352                 /*
3353                  * Sanity check: avoid coming within BGE_NSEG_RSVD
3354                  * descriptors of the end of the ring.  Also make
3355                  * sure there are BGE_NSEG_SPARE descriptors for
3356                  * jumbo buffers' defragmentation.
3357                  */
3358                 if ((BGE_TX_RING_CNT - sc->bge_txcnt) <
3359                     (BGE_NSEG_RSVD + BGE_NSEG_SPARE)) {
3360                         ifp->if_flags |= IFF_OACTIVE;
3361                         ifq_prepend(&ifp->if_snd, m_head);
3362                         break;
3363                 }
3364
3365                 /*
3366                  * Pack the data into the transmit ring. If we
3367                  * don't have room, set the OACTIVE flag and wait
3368                  * for the NIC to drain the ring.
3369                  */
3370                 if (bge_encap(sc, &m_head, &prodidx)) {
3371                         ifp->if_flags |= IFF_OACTIVE;
3372                         ifp->if_oerrors++;
3373                         break;
3374                 }
3375                 need_trans = 1;
3376
3377                 ETHER_BPF_MTAP(ifp, m_head);
3378         }
3379
3380         if (!need_trans)
3381                 return;
3382
3383         /* Transmit */
3384         bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx);
3385         /* 5700 b2 errata */
3386         if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
3387                 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx);
3388
3389         sc->bge_tx_prodidx = prodidx;
3390
3391         /*
3392          * Set a timeout in case the chip goes out to lunch.
3393          */
3394         ifp->if_timer = 5;
3395 }
3396
3397 static void
3398 bge_init(void *xsc)
3399 {
3400         struct bge_softc *sc = xsc;
3401         struct ifnet *ifp = &sc->arpcom.ac_if;
3402         uint16_t *m;
3403         uint32_t mode;
3404
3405         ASSERT_SERIALIZED(ifp->if_serializer);
3406
3407         /* Cancel pending I/O and flush buffers. */
3408         bge_stop(sc);
3409         bge_reset(sc);
3410         bge_chipinit(sc);
3411
3412         /*
3413          * Init the various state machines, ring
3414          * control blocks and firmware.
3415          */
3416         if (bge_blockinit(sc)) {
3417                 if_printf(ifp, "initialization failure\n");
3418                 bge_stop(sc);
3419                 return;
3420         }
3421
3422         /* Specify MTU. */
3423         CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu +
3424             ETHER_HDR_LEN + ETHER_CRC_LEN + EVL_ENCAPLEN);
3425
3426         /* Load our MAC address. */
3427         m = (uint16_t *)&sc->arpcom.ac_enaddr[0];
3428         CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0]));
3429         CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2]));
3430
3431         /* Enable or disable promiscuous mode as needed. */
3432         bge_setpromisc(sc);
3433
3434         /* Program multicast filter. */
3435         bge_setmulti(sc);
3436
3437         /* Init RX ring. */
3438         if (bge_init_rx_ring_std(sc)) {
3439                 if_printf(ifp, "RX ring initialization failed\n");
3440                 bge_stop(sc);
3441                 return;
3442         }
3443
3444         /*
3445          * Workaround for a bug in 5705 ASIC rev A0. Poll the NIC's
3446          * memory to insure that the chip has in fact read the first
3447          * entry of the ring.
3448          */
3449         if (sc->bge_chipid == BGE_CHIPID_BCM5705_A0) {
3450                 uint32_t                v, i;
3451                 for (i = 0; i < 10; i++) {
3452                         DELAY(20);
3453                         v = bge_readmem_ind(sc, BGE_STD_RX_RINGS + 8);
3454                         if (v == (MCLBYTES - ETHER_ALIGN))
3455                                 break;
3456                 }
3457                 if (i == 10)
3458                         if_printf(ifp, "5705 A0 chip failed to load RX ring\n");
3459         }
3460
3461         /* Init jumbo RX ring. */
3462         if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) {
3463                 if (bge_init_rx_ring_jumbo(sc)) {
3464                         if_printf(ifp, "Jumbo RX ring initialization failed\n");
3465                         bge_stop(sc);
3466                         return;
3467                 }
3468         }
3469
3470         /* Init our RX return ring index */
3471         sc->bge_rx_saved_considx = 0;
3472
3473         /* Init TX ring. */
3474         bge_init_tx_ring(sc);
3475
3476         /* Enable TX MAC state machine lockup fix. */
3477         mode = CSR_READ_4(sc, BGE_TX_MODE);
3478         if (BGE_IS_5755_PLUS(sc) || sc->bge_asicrev == BGE_ASICREV_BCM5906)
3479                 mode |= BGE_TXMODE_MBUF_LOCKUP_FIX;
3480         /* Turn on transmitter */
3481         CSR_WRITE_4(sc, BGE_TX_MODE, mode | BGE_TXMODE_ENABLE);
3482
3483         /* Turn on receiver */
3484         BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);
3485
3486         /*
3487          * Set the number of good frames to receive after RX MBUF
3488          * Low Watermark has been reached.  After the RX MAC receives
3489          * this number of frames, it will drop subsequent incoming
3490          * frames until the MBUF High Watermark is reached.
3491          */
3492         CSR_WRITE_4(sc, BGE_MAX_RX_FRAME_LOWAT, 2);
3493
3494         /* Tell firmware we're alive. */
3495         BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
3496
3497         /* Enable host interrupts if polling(4) is not enabled. */
3498         PCI_SETBIT(sc->bge_dev, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA, 4);
3499 #ifdef DEVICE_POLLING
3500         if (ifp->if_flags & IFF_POLLING)
3501                 bge_disable_intr(sc);
3502         else
3503 #endif
3504         bge_enable_intr(sc);
3505
3506         bge_ifmedia_upd(ifp);
3507
3508         ifp->if_flags |= IFF_RUNNING;
3509         ifp->if_flags &= ~IFF_OACTIVE;
3510
3511         callout_reset(&sc->bge_stat_timer, hz, bge_tick, sc);
3512 }
3513
3514 /*
3515  * Set media options.
3516  */
3517 static int
3518 bge_ifmedia_upd(struct ifnet *ifp)
3519 {
3520         struct bge_softc *sc = ifp->if_softc;
3521
3522         /* If this is a 1000baseX NIC, enable the TBI port. */
3523         if (sc->bge_flags & BGE_FLAG_TBI) {
3524                 struct ifmedia *ifm = &sc->bge_ifmedia;
3525
3526                 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
3527                         return(EINVAL);
3528
3529                 switch(IFM_SUBTYPE(ifm->ifm_media)) {
3530                 case IFM_AUTO:
3531                         /*
3532                          * The BCM5704 ASIC appears to have a special
3533                          * mechanism for programming the autoneg
3534                          * advertisement registers in TBI mode.
3535                          */
3536                         if (!bge_fake_autoneg &&
3537                             sc->bge_asicrev == BGE_ASICREV_BCM5704) {
3538                                 uint32_t sgdig;
3539
3540                                 CSR_WRITE_4(sc, BGE_TX_TBI_AUTONEG, 0);
3541                                 sgdig = CSR_READ_4(sc, BGE_SGDIG_CFG);
3542                                 sgdig |= BGE_SGDIGCFG_AUTO |
3543                                          BGE_SGDIGCFG_PAUSE_CAP |
3544                                          BGE_SGDIGCFG_ASYM_PAUSE;
3545                                 CSR_WRITE_4(sc, BGE_SGDIG_CFG,
3546                                             sgdig | BGE_SGDIGCFG_SEND);
3547                                 DELAY(5);
3548                                 CSR_WRITE_4(sc, BGE_SGDIG_CFG, sgdig);
3549                         }
3550                         break;
3551                 case IFM_1000_SX:
3552                         if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) {
3553                                 BGE_CLRBIT(sc, BGE_MAC_MODE,
3554                                     BGE_MACMODE_HALF_DUPLEX);
3555                         } else {
3556                                 BGE_SETBIT(sc, BGE_MAC_MODE,
3557                                     BGE_MACMODE_HALF_DUPLEX);
3558                         }
3559                         break;
3560                 default:
3561                         return(EINVAL);
3562                 }
3563         } else {
3564                 struct mii_data *mii = device_get_softc(sc->bge_miibus);
3565
3566                 sc->bge_link_evt++;
3567                 sc->bge_link = 0;
3568                 if (mii->mii_instance) {
3569                         struct mii_softc *miisc;
3570
3571                         LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
3572                                 mii_phy_reset(miisc);
3573                 }
3574                 mii_mediachg(mii);
3575
3576                 /*
3577                  * Force an interrupt so that we will call bge_link_upd
3578                  * if needed and clear any pending link state attention.
3579                  * Without this we are not getting any further interrupts
3580                  * for link state changes and thus will not UP the link and
3581                  * not be able to send in bge_start.  The only way to get
3582                  * things working was to receive a packet and get an RX
3583                  * intr.
3584                  *
3585                  * bge_tick should help for fiber cards and we might not
3586                  * need to do this here if BGE_FLAG_TBI is set but as
3587                  * we poll for fiber anyway it should not harm.
3588                  */
3589                 if (BGE_IS_CRIPPLED(sc))
3590                         BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET);
3591                 else
3592                         BGE_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW);
3593         }
3594         return(0);
3595 }
3596
3597 /*
3598  * Report current media status.
3599  */
3600 static void
3601 bge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
3602 {
3603         struct bge_softc *sc = ifp->if_softc;
3604
3605         if (sc->bge_flags & BGE_FLAG_TBI) {
3606                 ifmr->ifm_status = IFM_AVALID;
3607                 ifmr->ifm_active = IFM_ETHER;
3608                 if (CSR_READ_4(sc, BGE_MAC_STS) &
3609                     BGE_MACSTAT_TBI_PCS_SYNCHED) {
3610                         ifmr->ifm_status |= IFM_ACTIVE;
3611                 } else {
3612                         ifmr->ifm_active |= IFM_NONE;
3613                         return;
3614                 }
3615
3616                 ifmr->ifm_active |= IFM_1000_SX;
3617                 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX)
3618                         ifmr->ifm_active |= IFM_HDX;    
3619                 else
3620                         ifmr->ifm_active |= IFM_FDX;
3621         } else {
3622                 struct mii_data *mii = device_get_softc(sc->bge_miibus);
3623
3624                 mii_pollstat(mii);
3625                 ifmr->ifm_active = mii->mii_media_active;
3626                 ifmr->ifm_status = mii->mii_media_status;
3627         }
3628 }
3629
3630 static int
3631 bge_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
3632 {
3633         struct bge_softc *sc = ifp->if_softc;
3634         struct ifreq *ifr = (struct ifreq *)data;
3635         int mask, error = 0;
3636
3637         ASSERT_SERIALIZED(ifp->if_serializer);
3638
3639         switch (command) {
3640         case SIOCSIFMTU:
3641                 if ((!BGE_IS_JUMBO_CAPABLE(sc) && ifr->ifr_mtu > ETHERMTU) ||
3642                     (BGE_IS_JUMBO_CAPABLE(sc) &&
3643                      ifr->ifr_mtu > BGE_JUMBO_MTU)) {
3644                         error = EINVAL;
3645                 } else if (ifp->if_mtu != ifr->ifr_mtu) {
3646                         ifp->if_mtu = ifr->ifr_mtu;
3647                         if (ifp->if_flags & IFF_RUNNING)
3648                                 bge_init(sc);
3649                 }
3650                 break;
3651         case SIOCSIFFLAGS:
3652                 if (ifp->if_flags & IFF_UP) {
3653                         if (ifp->if_flags & IFF_RUNNING) {
3654                                 mask = ifp->if_flags ^ sc->bge_if_flags;
3655
3656                                 /*
3657                                  * If only the state of the PROMISC flag
3658                                  * changed, then just use the 'set promisc
3659                                  * mode' command instead of reinitializing
3660                                  * the entire NIC. Doing a full re-init
3661                                  * means reloading the firmware and waiting
3662                                  * for it to start up, which may take a
3663                                  * second or two.  Similarly for ALLMULTI.
3664                                  */
3665                                 if (mask & IFF_PROMISC)
3666                                         bge_setpromisc(sc);
3667                                 if (mask & IFF_ALLMULTI)
3668                                         bge_setmulti(sc);
3669                         } else {
3670                                 bge_init(sc);
3671                         }
3672                 } else if (ifp->if_flags & IFF_RUNNING) {
3673                         bge_stop(sc);
3674                 }
3675                 sc->bge_if_flags = ifp->if_flags;
3676                 break;
3677         case SIOCADDMULTI:
3678         case SIOCDELMULTI:
3679                 if (ifp->if_flags & IFF_RUNNING)
3680                         bge_setmulti(sc);
3681                 break;
3682         case SIOCSIFMEDIA:
3683         case SIOCGIFMEDIA:
3684                 if (sc->bge_flags & BGE_FLAG_TBI) {
3685                         error = ifmedia_ioctl(ifp, ifr,
3686                             &sc->bge_ifmedia, command);
3687                 } else {
3688                         struct mii_data *mii;
3689
3690                         mii = device_get_softc(sc->bge_miibus);
3691                         error = ifmedia_ioctl(ifp, ifr,
3692                                               &mii->mii_media, command);
3693                 }
3694                 break;
3695         case SIOCSIFCAP:
3696                 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
3697                 if (mask & IFCAP_HWCSUM) {
3698                         ifp->if_capenable ^= (mask & IFCAP_HWCSUM);
3699                         if (IFCAP_HWCSUM & ifp->if_capenable)
3700                                 ifp->if_hwassist = BGE_CSUM_FEATURES;
3701                         else
3702                                 ifp->if_hwassist = 0;
3703                 }
3704                 break;
3705         default:
3706                 error = ether_ioctl(ifp, command, data);
3707                 break;
3708         }
3709         return error;
3710 }
3711
3712 static void
3713 bge_watchdog(struct ifnet *ifp)
3714 {
3715         struct bge_softc *sc = ifp->if_softc;
3716
3717         if_printf(ifp, "watchdog timeout -- resetting\n");
3718
3719         bge_init(sc);
3720
3721         ifp->if_oerrors++;
3722
3723         if (!ifq_is_empty(&ifp->if_snd))
3724                 if_devstart(ifp);
3725 }
3726
3727 /*
3728  * Stop the adapter and free any mbufs allocated to the
3729  * RX and TX lists.
3730  */
3731 static void
3732 bge_stop(struct bge_softc *sc)
3733 {
3734         struct ifnet *ifp = &sc->arpcom.ac_if;
3735
3736         ASSERT_SERIALIZED(ifp->if_serializer);
3737
3738         callout_stop(&sc->bge_stat_timer);
3739
3740         /*
3741          * Disable all of the receiver blocks
3742          */
3743         bge_stop_block(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);
3744         bge_stop_block(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
3745         bge_stop_block(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
3746         if (BGE_IS_5700_FAMILY(sc))
3747                 bge_stop_block(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE);
3748         bge_stop_block(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE);
3749         bge_stop_block(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
3750         bge_stop_block(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE);
3751
3752         /*
3753          * Disable all of the transmit blocks
3754          */
3755         bge_stop_block(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
3756         bge_stop_block(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
3757         bge_stop_block(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
3758         bge_stop_block(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE);
3759         bge_stop_block(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE);
3760         if (BGE_IS_5700_FAMILY(sc))
3761                 bge_stop_block(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE);
3762         bge_stop_block(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
3763
3764         /*
3765          * Shut down all of the memory managers and related
3766          * state machines.
3767          */
3768         bge_stop_block(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE);
3769         bge_stop_block(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE);
3770         if (BGE_IS_5700_FAMILY(sc))
3771                 bge_stop_block(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE);
3772         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
3773         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
3774         if (!BGE_IS_5705_PLUS(sc)) {
3775                 BGE_CLRBIT(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE);
3776                 BGE_CLRBIT(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
3777         }
3778
3779         /* Disable host interrupts. */
3780         bge_disable_intr(sc);
3781
3782         /*
3783          * Tell firmware we're shutting down.
3784          */
3785         BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
3786
3787         /* Free the RX lists. */
3788         bge_free_rx_ring_std(sc);
3789
3790         /* Free jumbo RX list. */
3791         if (BGE_IS_JUMBO_CAPABLE(sc))
3792                 bge_free_rx_ring_jumbo(sc);
3793
3794         /* Free TX buffers. */
3795         bge_free_tx_ring(sc);
3796
3797         sc->bge_status_tag = 0;
3798         sc->bge_link = 0;
3799         sc->bge_coal_chg = 0;
3800
3801         sc->bge_tx_saved_considx = BGE_TXCONS_UNSET;
3802
3803         ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
3804         ifp->if_timer = 0;
3805 }
3806
3807 /*
3808  * Stop all chip I/O so that the kernel's probe routines don't
3809  * get confused by errant DMAs when rebooting.
3810  */
3811 static void
3812 bge_shutdown(device_t dev)
3813 {
3814         struct bge_softc *sc = device_get_softc(dev);
3815         struct ifnet *ifp = &sc->arpcom.ac_if;
3816
3817         lwkt_serialize_enter(ifp->if_serializer);
3818         bge_stop(sc);
3819         bge_reset(sc);
3820         lwkt_serialize_exit(ifp->if_serializer);
3821 }
3822
3823 static int
3824 bge_suspend(device_t dev)
3825 {
3826         struct bge_softc *sc = device_get_softc(dev);
3827         struct ifnet *ifp = &sc->arpcom.ac_if;
3828
3829         lwkt_serialize_enter(ifp->if_serializer);
3830         bge_stop(sc);
3831         lwkt_serialize_exit(ifp->if_serializer);
3832
3833         return 0;
3834 }
3835
3836 static int
3837 bge_resume(device_t dev)
3838 {
3839         struct bge_softc *sc = device_get_softc(dev);
3840         struct ifnet *ifp = &sc->arpcom.ac_if;
3841
3842         lwkt_serialize_enter(ifp->if_serializer);
3843
3844         if (ifp->if_flags & IFF_UP) {
3845                 bge_init(sc);
3846
3847                 if (!ifq_is_empty(&ifp->if_snd))
3848                         if_devstart(ifp);
3849         }
3850
3851         lwkt_serialize_exit(ifp->if_serializer);
3852
3853         return 0;
3854 }
3855
3856 static void
3857 bge_setpromisc(struct bge_softc *sc)
3858 {
3859         struct ifnet *ifp = &sc->arpcom.ac_if;
3860
3861         if (ifp->if_flags & IFF_PROMISC)
3862                 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
3863         else
3864                 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
3865 }
3866
3867 static void
3868 bge_dma_free(struct bge_softc *sc)
3869 {
3870         int i;
3871
3872         /* Destroy RX mbuf DMA stuffs. */
3873         if (sc->bge_cdata.bge_rx_mtag != NULL) {
3874                 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
3875                         bus_dmamap_destroy(sc->bge_cdata.bge_rx_mtag,
3876                             sc->bge_cdata.bge_rx_std_dmamap[i]);
3877                 }
3878                 bus_dmamap_destroy(sc->bge_cdata.bge_rx_mtag,
3879                                    sc->bge_cdata.bge_rx_tmpmap);
3880                 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_mtag);
3881         }
3882
3883         /* Destroy TX mbuf DMA stuffs. */
3884         if (sc->bge_cdata.bge_tx_mtag != NULL) {
3885                 for (i = 0; i < BGE_TX_RING_CNT; i++) {
3886                         bus_dmamap_destroy(sc->bge_cdata.bge_tx_mtag,
3887                             sc->bge_cdata.bge_tx_dmamap[i]);
3888                 }
3889                 bus_dma_tag_destroy(sc->bge_cdata.bge_tx_mtag);
3890         }
3891
3892         /* Destroy standard RX ring */
3893         bge_dma_block_free(sc->bge_cdata.bge_rx_std_ring_tag,
3894                            sc->bge_cdata.bge_rx_std_ring_map,
3895                            sc->bge_ldata.bge_rx_std_ring);
3896
3897         if (BGE_IS_JUMBO_CAPABLE(sc))
3898                 bge_free_jumbo_mem(sc);
3899
3900         /* Destroy RX return ring */
3901         bge_dma_block_free(sc->bge_cdata.bge_rx_return_ring_tag,
3902                            sc->bge_cdata.bge_rx_return_ring_map,
3903                            sc->bge_ldata.bge_rx_return_ring);
3904
3905         /* Destroy TX ring */
3906         bge_dma_block_free(sc->bge_cdata.bge_tx_ring_tag,
3907                            sc->bge_cdata.bge_tx_ring_map,
3908                            sc->bge_ldata.bge_tx_ring);
3909
3910         /* Destroy status block */
3911         bge_dma_block_free(sc->bge_cdata.bge_status_tag,
3912                            sc->bge_cdata.bge_status_map,
3913                            sc->bge_ldata.bge_status_block);
3914
3915         /* Destroy statistics block */
3916         bge_dma_block_free(sc->bge_cdata.bge_stats_tag,
3917                            sc->bge_cdata.bge_stats_map,
3918                            sc->bge_ldata.bge_stats);
3919
3920         /* Destroy the parent tag */
3921         if (sc->bge_cdata.bge_parent_tag != NULL)
3922                 bus_dma_tag_destroy(sc->bge_cdata.bge_parent_tag);
3923 }
3924
3925 static int
3926 bge_dma_alloc(struct bge_softc *sc)
3927 {
3928         struct ifnet *ifp = &sc->arpcom.ac_if;
3929         int i, error;
3930         bus_addr_t lowaddr;
3931
3932         lowaddr = BUS_SPACE_MAXADDR;
3933         if (sc->bge_flags & BGE_FLAG_MAXADDR_40BIT)
3934                 lowaddr = BGE_DMA_MAXADDR_40BIT;
3935
3936         /*
3937          * Allocate the parent bus DMA tag appropriate for PCI.
3938          *
3939          * All of the NetExtreme/NetLink controllers have 4GB boundary
3940          * DMA bug.
3941          * Whenever an address crosses a multiple of the 4GB boundary
3942          * (including 4GB, 8Gb, 12Gb, etc.) and makes the transition