sys/net/i4b/layer1/ifpi/i4b_ifpi_pci.c

   1 /*
   2  *   Copyright (c) 1999, 2000 Gary Jennejohn. All rights reserved.
   3  *
   4  *   Redistribution and use in source and binary forms, with or without
   5  *   modification, are permitted provided that the following conditions
   6  *   are met:
   7  *
   8  *   1. Redistributions of source code must retain the above copyright
   9  *      notice, this list of conditions and the following disclaimer.
  10  *   2. Redistributions in binary form must reproduce the above copyright
  11  *      notice, this list of conditions and the following disclaimer in the
  12  *      documentation and/or other materials provided with the distribution.
  13  *   3. Neither the name of the author nor the names of any co-contributors
  14  *      may be used to endorse or promote products derived from this software
  15  *      without specific prior written permission.
  16  *   4. Altered versions must be plainly marked as such, and must not be
  17  *      misrepresented as being the original software and/or documentation.
  18  *
  19  *   THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  20  *   ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  21  *   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  22  *   ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  23  *   FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  24  *   DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  25  *   OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  26  *   HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  27  *   LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  28  *   OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  29  *   SUCH DAMAGE.
  30  *
  31  *---------------------------------------------------------------------------
  32  *
  33  *      i4b_ifpi_pci.c: AVM Fritz!Card PCI hardware driver
  34  *      --------------------------------------------------
  35  *
  36  *      $Id: i4b_ifpi_pci.c,v 1.4 2000/06/02 11:58:56 hm Exp $
  37  *
  38  * $FreeBSD: src/sys/i4b/layer1/ifpi/i4b_ifpi_pci.c,v 1.6.2.1 2001/08/10 14:08:37 obrien Exp $
  39  *
  40  *      last edit-date: [Fri Jan 12 17:01:26 2001]
  41  *
  42  *---------------------------------------------------------------------------*/
  43
  44 #include "use_ifpi.h"
  45 #include "use_pci.h"
  46 #include "opt_i4b.h"
  47
  48 #if (NIFPI > 0) && (NPCI > 0)
  49
  50 #include <sys/param.h>
  51 #include <sys/kernel.h>
  52 #include <sys/systm.h>
  53 #include <sys/mbuf.h>
  54 #include <sys/bus.h>
  55 #include <sys/rman.h>
  56 #include <sys/socket.h>
  57 #include <sys/thread2.h>
  58
  59 #include <bus/pci/pcireg.h>
  60 #include <bus/pci/pcivar.h>
  61
  62 #include <net/if.h>
  63 #include <net/i4b/include/machine/i4b_debug.h>
  64 #include <net/i4b/include/machine/i4b_ioctl.h>
  65 #include <net/i4b/include/machine/i4b_trace.h>
  66
  67 #include "../../include/i4b_global.h"
  68 #include "../../include/i4b_mbuf.h"
  69
  70 #include "../i4b_l1.h"
  71 #include "../isic/i4b_isic.h"
  72 #include "../isic/i4b_isac.h"
  73 #include "../isic/i4b_hscx.h"
  74
  75 #include "i4b_ifpi_ext.h"
  76
  77 #define PCI_AVMA1_VID 0x1244
  78 #define PCI_AVMA1_DID 0x0a00
  79
  80 /* prototypes */
  81 static void avma1pp_disable(device_t);
  82
  83 static void avma1pp_intr(void *);
  84 static void hscx_write_reg(int, u_int, u_int, struct l1_softc *);
  85 static u_char hscx_read_reg(int, u_int, struct l1_softc *);
  86 static u_int hscx_read_reg_int(int, u_int, struct l1_softc *);
  87 static void hscx_read_fifo(int, void *, size_t, struct l1_softc *);
  88 static void hscx_write_fifo(int, void *, size_t, struct l1_softc *);
  89 static void avma1pp_hscx_int_handler(struct l1_softc *);
  90 static void avma1pp_hscx_intr(int, u_int, struct l1_softc *);
  91 static void avma1pp_init_linktab(struct l1_softc *);
  92 static void avma1pp_bchannel_setup(int, int, int, int);
  93 static void avma1pp_bchannel_start(int, int);
  94 static void avma1pp_hscx_init(struct l1_softc *, int, int);
  95 static void avma1pp_bchannel_stat(int, int, bchan_statistics_t *);
  96 static void avma1pp_set_linktab(int, int, drvr_link_t *);
  97 static isdn_link_t * avma1pp_ret_linktab(int, int);
  98 static int avma1pp_pci_probe(device_t);
  99 static int avma1pp_hscx_fifo(l1_bchan_state_t *, struct l1_softc *);
 100 int avma1pp_attach_avma1pp(device_t);
 101 static void ifpi_isac_intr(struct l1_softc *sc);
 102
 103 static device_method_t avma1pp_pci_methods[] = {
 104         /* Device interface */
 105         DEVMETHOD(device_probe,         avma1pp_pci_probe),
 106         DEVMETHOD(device_attach,        avma1pp_attach_avma1pp),
 107         DEVMETHOD(device_shutdown,      avma1pp_disable),
 108
 109         /* bus interface */
 110         DEVMETHOD(bus_print_child,      bus_generic_print_child),
 111         DEVMETHOD(bus_driver_added,     bus_generic_driver_added),
 112
 113         { 0, 0 }
 114 };
 115
 116 #if 0 /* use what's in l1_softc */
 117 /* a minimal softc for the Fritz!Card PCI */
 118 struct avma1pp_softc
 119 {
 120         bus_space_handle_t      avma1pp_bhandle;
 121         bus_space_tag_t         avma1pp_btag;
 122         void                    *avma1pp_intrhand;
 123         struct resource         *avma1pp_irq;
 124         struct resource         *avma1pp_res;
 125         /* pointer to ifpi_sc */
 126         struct l1_softc *avma1pp_isc;
 127 };
 128 #endif
 129
 130 static driver_t avma1pp_pci_driver = {
 131         "ifpi",
 132         avma1pp_pci_methods,
 133         sizeof(struct l1_softc)
 134 };
 135
 136 static devclass_t avma1pp_pci_devclass;
 137
 138 DRIVER_MODULE(avma1pp, pci, avma1pp_pci_driver, avma1pp_pci_devclass, NULL, NULL);
 139
 140 /* jump table for multiplex routines */
 141
 142 struct i4b_l1mux_func avma1pp_l1mux_func = {
 143         avma1pp_ret_linktab,
 144         avma1pp_set_linktab,
 145         ifpi_mph_command_req,
 146         ifpi_ph_data_req,
 147         ifpi_ph_activate_req,
 148 };
 149
 150 struct l1_softc *ifpi_scp[IFPI_MAXUNIT];
 151
 152 /*---------------------------------------------------------------------------*
 153  *      AVM PCI Fritz!Card special registers
 154  *---------------------------------------------------------------------------*/
 155
 156 /*
 157  *      register offsets from i/o base
 158  */
 159 #define STAT0_OFFSET            0x02
 160 #define STAT1_OFFSET            0x03
 161 #define ADDR_REG_OFFSET         0x04
 162 /*#define MODREG_OFFSET         0x06
 163 #define VERREG_OFFSET           0x07*/
 164
 165 /* these 2 are used to select an ISAC register set */
 166 #define ISAC_LO_REG_OFFSET      0x04
 167 #define ISAC_HI_REG_OFFSET      0x06
 168
 169 /* offset higher than this goes to the HI register set */
 170 #define MAX_LO_REG_OFFSET       0x2f
 171
 172 /* mask for the offset */
 173 #define ISAC_REGSET_MASK        0x0f
 174
 175 /* the offset from the base to the ISAC registers */
 176 #define ISAC_REG_OFFSET         0x10
 177
 178 /* the offset from the base to the ISAC FIFO */
 179 #define ISAC_FIFO               0x02
 180
 181 /* not really the HSCX, but sort of */
 182 #define HSCX_FIFO               0x00
 183 #define HSCX_STAT               0x04
 184
 185 /*
 186  *      AVM PCI Status Latch 0 read only bits
 187  */
 188 #define ASL_IRQ_ISAC            0x01    /* ISAC  interrupt, active low */
 189 #define ASL_IRQ_HSCX            0x02    /* HSX   interrupt, active low */
 190 #define ASL_IRQ_TIMER           0x04    /* Timer interrupt, active low */
 191 #define ASL_IRQ_BCHAN           ASL_IRQ_HSCX
 192 /* actually active LOW */
 193 #define ASL_IRQ_Pending         (ASL_IRQ_ISAC | ASL_IRQ_HSCX | ASL_IRQ_TIMER)
 194
 195 /*
 196  *      AVM Status Latch 0 write only bits
 197  */
 198 #define ASL_RESET_ALL           0x01  /* reset siemens IC's, active 1 */
 199 #define ASL_TIMERDISABLE        0x02  /* active high */
 200 #define ASL_TIMERRESET          0x04  /* active high */
 201 #define ASL_ENABLE_INT          0x08  /* active high */
 202 #define ASL_TESTBIT             0x10  /* active high */
 203
 204 /*
 205  *      AVM Status Latch 1 write only bits
 206  */
 207 #define ASL1_INTSEL              0x0f  /* active high */
 208 #define ASL1_ENABLE_IOM          0x80  /* active high */
 209
 210 /*
 211  * "HSCX" mode bits
 212  */
 213 #define  HSCX_MODE_ITF_FLG      0x01
 214 #define  HSCX_MODE_TRANS        0x02
 215 #define  HSCX_MODE_CCR_7        0x04
 216 #define  HSCX_MODE_CCR_16       0x08
 217 #define  HSCX_MODE_TESTLOOP     0x80
 218
 219 /*
 220  * "HSCX" status bits
 221  */
 222 #define  HSCX_STAT_RME          0x01
 223 #define  HSCX_STAT_RDO          0x10
 224 #define  HSCX_STAT_CRCVFRRAB    0x0E
 225 #define  HSCX_STAT_CRCVFR       0x06
 226 #define  HSCX_STAT_RML_MASK     0x3f00
 227
 228 /*
 229  * "HSCX" interrupt bits
 230  */
 231 #define  HSCX_INT_XPR           0x80
 232 #define  HSCX_INT_XDU           0x40
 233 #define  HSCX_INT_RPR           0x20
 234 #define  HSCX_INT_MASK          0xE0
 235
 236 /*
 237  * "HSCX" command bits
 238  */
 239 #define  HSCX_CMD_XRS           0x80
 240 #define  HSCX_CMD_XME           0x01
 241 #define  HSCX_CMD_RRS           0x20
 242 #define  HSCX_CMD_XML_MASK      0x3f00
 243
 244 /*
 245  * Commands and parameters are sent to the "HSCX" as a long, but the
 246  * fields are handled as bytes.
 247  *
 248  * The long contains:
 249  *      (prot << 16)|(txl << 8)|cmd
 250  *
 251  * where:
 252  *      prot = protocol to use
 253  *      txl = transmit length
 254  *      cmd = the command to be executed
 255  *
 256  * The fields are defined as u_char in struct l1_softc.
 257  *
 258  * Macro to coalesce the byte fields into a u_int
 259  */
 260 #define AVMA1PPSETCMDLONG(f) (f) = ((sc->avma1pp_cmd) | (sc->avma1pp_txl << 8) \
 261                                         | (sc->avma1pp_prot << 16))
 262
 263 /*
 264  * to prevent deactivating the "HSCX" when both channels are active we
 265  * define an HSCX_ACTIVE flag which is or'd into the channel's state
 266  * flag in avma1pp_bchannel_setup upon active and cleared upon deactivation.
 267  * It is set high to allow room for new flags.
 268  */
 269 #define HSCX_AVMA1PP_ACTIVE     0x1000
 270
 271 /*---------------------------------------------------------------------------*
 272  *      AVM read fifo routines
 273  *---------------------------------------------------------------------------*/
 274
 275 static void
 276 avma1pp_read_fifo(struct l1_softc *sc, int what, void *buf, size_t size)
 277 {
 278         bus_space_handle_t bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
 279         bus_space_tag_t btag = rman_get_bustag(sc->sc_resources.io_base[0]);
 280
 281         switch (what) {
 282                 case ISIC_WHAT_ISAC:
 283                         bus_space_write_1(btag, bhandle,  ADDR_REG_OFFSET, ISAC_FIFO);
 284                         bus_space_read_multi_1(btag, bhandle,  ISAC_REG_OFFSET, buf, size);
 285                         break;
 286                 case ISIC_WHAT_HSCXA:
 287                         hscx_read_fifo(0, buf, size, sc);
 288                         break;
 289                 case ISIC_WHAT_HSCXB:
 290                         hscx_read_fifo(1, buf, size, sc);
 291                         break;
 292         }
 293 }
 294
 295 static void
 296 hscx_read_fifo(int chan, void *buf, size_t len, struct l1_softc *sc)
 297 {
 298         u_int32_t *ip;
 299         size_t cnt;
 300         bus_space_handle_t bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
 301         bus_space_tag_t btag = rman_get_bustag(sc->sc_resources.io_base[0]);
 302
 303         bus_space_write_4(btag, bhandle, ADDR_REG_OFFSET, chan);
 304         ip = (u_int32_t *)buf;
 305         cnt = 0;
 306         /* what if len isn't a multiple of sizeof(int) and buf is */
 307         /* too small ???? */
 308         while (cnt < len)
 309         {
 310                 *ip++ = bus_space_read_4(btag, bhandle, ISAC_REG_OFFSET);
 311                 cnt += 4;
 312         }
 313 }
 314
 315 /*---------------------------------------------------------------------------*
 316  *      AVM write fifo routines
 317  *---------------------------------------------------------------------------*/
 318 static void
 319 avma1pp_write_fifo(struct l1_softc *sc, int what, void *buf, size_t size)
 320 {
 321         bus_space_handle_t bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
 322         bus_space_tag_t btag = rman_get_bustag(sc->sc_resources.io_base[0]);
 323
 324         switch (what) {
 325                 case ISIC_WHAT_ISAC:
 326                         bus_space_write_1(btag, bhandle,  ADDR_REG_OFFSET, ISAC_FIFO);
 327                         bus_space_write_multi_1(btag, bhandle,  ISAC_REG_OFFSET, (u_int8_t*)buf, size);
 328                         break;
 329                 case ISIC_WHAT_HSCXA:
 330                         hscx_write_fifo(0, buf, size, sc);
 331                         break;
 332                 case ISIC_WHAT_HSCXB:
 333                         hscx_write_fifo(1, buf, size, sc);
 334                         break;
 335         }
 336 }
 337
 338 static void
 339 hscx_write_fifo(int chan, void *buf, size_t len, struct l1_softc *sc)
 340 {
 341         u_int32_t *ip;
 342         size_t cnt;
 343         l1_bchan_state_t *Bchan = &sc->sc_chan[chan];
 344         bus_space_handle_t bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
 345         bus_space_tag_t btag = rman_get_bustag(sc->sc_resources.io_base[0]);
 346
 347
 348         sc->avma1pp_cmd &= ~HSCX_CMD_XME;
 349         sc->avma1pp_txl = 0;
 350         if (Bchan->out_mbuf_cur == NULL)
 351         {
 352           if (Bchan->bprot != BPROT_NONE)
 353                  sc->avma1pp_cmd |= HSCX_CMD_XME;
 354         }
 355         if (len != sc->sc_bfifolen)
 356                 sc->avma1pp_txl = len;
 357
 358         cnt = 0; /* borrow cnt */
 359         AVMA1PPSETCMDLONG(cnt);
 360         hscx_write_reg(chan, HSCX_STAT, cnt, sc);
 361
 362         ip = (u_int32_t *)buf;
 363         cnt = 0;
 364         while (cnt < len)
 365         {
 366                 bus_space_write_4(btag, bhandle, ISAC_REG_OFFSET, *ip);
 367                 ip++;
 368                 cnt += 4;
 369         }
 370 }
 371
 372 /*---------------------------------------------------------------------------*
 373  *      AVM write register routines
 374  *---------------------------------------------------------------------------*/
 375
 376 static void
 377 avma1pp_write_reg(struct l1_softc *sc, int what, bus_size_t offs, u_int8_t data)
 378 {
 379         u_char reg_bank;
 380         bus_space_handle_t bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
 381         bus_space_tag_t btag = rman_get_bustag(sc->sc_resources.io_base[0]);
 382
 383         switch (what) {
 384                 case ISIC_WHAT_ISAC:
 385                         reg_bank = (offs > MAX_LO_REG_OFFSET) ? ISAC_HI_REG_OFFSET:ISAC_LO_REG_OFFSET;
 386 #ifdef AVMA1PCI_DEBUG
 387                         kprintf("write_reg bank %d  off %ld.. ", (int)reg_bank, (long)offs);
 388 #endif
 389                         /* set the register bank */
 390                         bus_space_write_1(btag, bhandle, ADDR_REG_OFFSET, reg_bank);
 391                         bus_space_write_1(btag, bhandle, ISAC_REG_OFFSET + (offs & ISAC_REGSET_MASK), data);
 392                         break;
 393                 case ISIC_WHAT_HSCXA:
 394                         hscx_write_reg(0, offs, data, sc);
 395                         break;
 396                 case ISIC_WHAT_HSCXB:
 397                         hscx_write_reg(1, offs, data, sc);
 398                         break;
 399         }
 400 }
 401
 402 static void
 403 hscx_write_reg(int chan, u_int off, u_int val, struct l1_softc *sc)
 404 {
 405         bus_space_handle_t bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
 406         bus_space_tag_t btag = rman_get_bustag(sc->sc_resources.io_base[0]);
 407
 408         /* point at the correct channel */
 409         bus_space_write_4(btag, bhandle, ADDR_REG_OFFSET, chan);
 410         bus_space_write_4(btag, bhandle, ISAC_REG_OFFSET + off, val);
 411 }
 412
 413 /*---------------------------------------------------------------------------*
 414  *      AVM read register routines
 415  *---------------------------------------------------------------------------*/
 416 static u_int8_t
 417 avma1pp_read_reg(struct l1_softc *sc, int what, bus_size_t offs)
 418 {
 419         u_char reg_bank;
 420         bus_space_handle_t bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
 421         bus_space_tag_t btag = rman_get_bustag(sc->sc_resources.io_base[0]);
 422
 423         switch (what) {
 424                 case ISIC_WHAT_ISAC:
 425                         reg_bank = (offs > MAX_LO_REG_OFFSET) ? ISAC_HI_REG_OFFSET:ISAC_LO_REG_OFFSET;
 426 #ifdef AVMA1PCI_DEBUG
 427                         kprintf("read_reg bank %d  off %ld.. ", (int)reg_bank, (long)offs);
 428 #endif
 429                         /* set the register bank */
 430                         bus_space_write_1(btag, bhandle, ADDR_REG_OFFSET, reg_bank);
 431                         return(bus_space_read_1(btag, bhandle, ISAC_REG_OFFSET +
 432                                 (offs & ISAC_REGSET_MASK)));
 433                 case ISIC_WHAT_HSCXA:
 434                         return hscx_read_reg(0, offs, sc);
 435                 case ISIC_WHAT_HSCXB:
 436                         return hscx_read_reg(1, offs, sc);
 437         }
 438         return 0;
 439 }
 440
 441 static u_char
 442 hscx_read_reg(int chan, u_int off, struct l1_softc *sc)
 443 {
 444         return(hscx_read_reg_int(chan, off, sc) & 0xff);
 445 }
 446
 447 /*
 448  * need to be able to return an int because the RBCH is in the 2nd
 449  * byte.
 450  */
 451 static u_int
 452 hscx_read_reg_int(int chan, u_int off, struct l1_softc *sc)
 453 {
 454         bus_space_handle_t bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
 455         bus_space_tag_t btag = rman_get_bustag(sc->sc_resources.io_base[0]);
 456
 457         /* point at the correct channel */
 458         bus_space_write_4(btag, bhandle, ADDR_REG_OFFSET, chan);
 459         return(bus_space_read_4(btag, bhandle, ISAC_REG_OFFSET + off));
 460 }
 461
 462 /*---------------------------------------------------------------------------*
 463  *      avma1pp_probe - probe for a card
 464  *---------------------------------------------------------------------------*/
 465 static int
 466 avma1pp_pci_probe(device_t dev)
 467 {
 468         u_int16_t               did, vid;
 469
 470         vid = pci_get_vendor(dev);
 471         did = pci_get_device(dev);
 472
 473         if ((vid == PCI_AVMA1_VID) && (did == PCI_AVMA1_DID)) {
 474                 device_set_desc(dev, "AVM Fritz!Card PCI");
 475                 return(0);
 476         }
 477
 478         return(ENXIO);
 479 }
 480
 481 /*---------------------------------------------------------------------------*
 482  *      avma1pp_attach_avma1pp - attach Fritz!Card PCI
 483  *---------------------------------------------------------------------------*/
 484 int
 485 avma1pp_attach_avma1pp(device_t dev)
 486 {
 487         struct l1_softc *sc;
 488         u_int v;
 489         int unit, error = 0;
 490         u_int16_t did, vid;
 491         void *ih = 0;
 492         bus_space_handle_t bhandle;
 493         bus_space_tag_t btag;
 494
 495         crit_enter();
 496
 497         vid = pci_get_vendor(dev);
 498         did = pci_get_device(dev);
 499         sc = device_get_softc(dev);
 500         unit = device_get_unit(dev);
 501         bzero(sc, sizeof(struct l1_softc));
 502
 503         /* probably not really required */
 504         if(unit > IFPI_MAXUNIT) {
 505                 kprintf("avma1pp%d: Error, unit > IFPI_MAXUNIT!\n", unit);
 506                 crit_exit();
 507                 return(ENXIO);
 508         }
 509
 510         if ((vid != PCI_AVMA1_VID) && (did != PCI_AVMA1_DID)) {
 511                 kprintf("avma1pp%d: unknown device!?\n", unit);
 512                 goto fail;
 513         }
 514
 515         ifpi_scp[unit] = sc;
 516
 517         sc->sc_resources.io_rid[0] = PCIR_MAPS+4;
 518         sc->sc_resources.io_base[0] = bus_alloc_resource(dev, SYS_RES_IOPORT,
 519                 &sc->sc_resources.io_rid[0],
 520                 0, ~0, 1, RF_ACTIVE);
 521
 522         if (sc->sc_resources.io_base[0] == NULL) {
 523                 kprintf("avma1pp%d: couldn't map IO port\n", unit);
 524                 error = ENXIO;
 525                 goto fail;
 526         }
 527
 528         bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
 529         btag = rman_get_bustag(sc->sc_resources.io_base[0]);
 530
 531         /* Allocate interrupt */
 532         sc->sc_resources.irq_rid = 0;
 533         sc->sc_resources.irq = bus_alloc_resource(dev, SYS_RES_IRQ,
 534                 &sc->sc_resources.irq_rid, 0, ~0, 1, RF_SHAREABLE | RF_ACTIVE);
 535
 536         if (sc->sc_resources.irq == NULL) {
 537                 bus_release_resource(dev, SYS_RES_IOPORT, PCIR_MAPS+4, sc->sc_resources.io_base[0]);
 538                 kprintf("avma1pp%d: couldn't map interrupt\n", unit);
 539                 error = ENXIO;
 540                 goto fail;
 541         }
 542
 543         error = bus_setup_intr(dev, sc->sc_resources.irq, 0,
 544                                avma1pp_intr, sc, &ih, NULL);
 545
 546         if (error) {
 547                 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_resources.irq);
 548                 bus_release_resource(dev, SYS_RES_IOPORT, PCIR_MAPS+4, sc->sc_resources.io_base[0]);
 549                 kprintf("avma1pp%d: couldn't set up irq\n", unit);
 550                 goto fail;
 551         }
 552
 553         sc->sc_unit = unit;
 554
 555         /* end of new-bus stuff */
 556
 557         ISAC_BASE = (caddr_t)ISIC_WHAT_ISAC;
 558
 559         HSCX_A_BASE = (caddr_t)ISIC_WHAT_HSCXA;
 560         HSCX_B_BASE = (caddr_t)ISIC_WHAT_HSCXB;
 561
 562         /* setup access routines */
 563
 564         sc->clearirq = NULL;
 565         sc->readreg = avma1pp_read_reg;
 566         sc->writereg = avma1pp_write_reg;
 567
 568         sc->readfifo = avma1pp_read_fifo;
 569         sc->writefifo = avma1pp_write_fifo;
 570
 571         /* setup card type */
 572
 573         sc->sc_cardtyp = CARD_TYPEP_AVMA1PCI;
 574
 575         /* setup IOM bus type */
 576
 577         sc->sc_bustyp = BUS_TYPE_IOM2;
 578
 579         /* set up some other miscellaneous things */
 580         sc->sc_ipac = 0;
 581         sc->sc_bfifolen = HSCX_FIFO_LEN;
 582
 583         /* reset the card */
 584         /* the Linux driver does this to clear any pending ISAC interrupts */
 585         v = 0;
 586         v = ISAC_READ(I_STAR);
 587 #ifdef AVMA1PCI_DEBUG
 588         kprintf("avma1pp_attach: I_STAR %x...", v);
 589 #endif
 590         v = ISAC_READ(I_MODE);
 591 #ifdef AVMA1PCI_DEBUG
 592         kprintf("avma1pp_attach: I_MODE %x...", v);
 593 #endif
 594         v = ISAC_READ(I_ADF2);
 595 #ifdef AVMA1PCI_DEBUG
 596         kprintf("avma1pp_attach: I_ADF2 %x...", v);
 597 #endif
 598         v = ISAC_READ(I_ISTA);
 599 #ifdef AVMA1PCI_DEBUG
 600         kprintf("avma1pp_attach: I_ISTA %x...", v);
 601 #endif
 602         if (v & ISAC_ISTA_EXI)
 603         {
 604                  v = ISAC_READ(I_EXIR);
 605 #ifdef AVMA1PCI_DEBUG
 606                  kprintf("avma1pp_attach: I_EXIR %x...", v);
 607 #endif
 608         }
 609         v = ISAC_READ(I_CIRR);
 610 #ifdef AVMA1PCI_DEBUG
 611         kprintf("avma1pp_attach: I_CIRR %x...", v);
 612 #endif
 613         ISAC_WRITE(I_MASK, 0xff);
 614         /* the Linux driver does this to clear any pending HSCX interrupts */
 615         v = hscx_read_reg_int(0, HSCX_STAT, sc);
 616 #ifdef AVMA1PCI_DEBUG
 617         kprintf("avma1pp_attach: 0 HSCX_STAT %x...", v);
 618 #endif
 619         v = hscx_read_reg_int(1, HSCX_STAT, sc);
 620 #ifdef AVMA1PCI_DEBUG
 621         kprintf("avma1pp_attach: 1 HSCX_STAT %x\n", v);
 622 #endif
 623
 624         bus_space_write_1(btag, bhandle, STAT0_OFFSET, ASL_RESET_ALL|ASL_TIMERDISABLE);
 625         DELAY(SEC_DELAY/100); /* 10 ms */
 626         bus_space_write_1(btag, bhandle, STAT0_OFFSET, ASL_TIMERRESET|ASL_ENABLE_INT|ASL_TIMERDISABLE);
 627         DELAY(SEC_DELAY/100); /* 10 ms */
 628 #ifdef AVMA1PCI_DEBUG
 629         bus_space_write_1(btag, bhandle, STAT1_OFFSET, ASL1_ENABLE_IOM|sc->sc_irq);
 630         DELAY(SEC_DELAY/100); /* 10 ms */
 631         v = bus_space_read_1(btag, bhandle, STAT1_OFFSET);
 632         kprintf("after reset: S1 %#x\n", v);
 633
 634         v = bus_space_read_4(btag, bhandle, 0);
 635         kprintf("avma1pp_attach_avma1pp: v %#x\n", v);
 636 #endif
 637
 638    /* from here to the end would normally be done in isic_pciattach */
 639
 640          kprintf("ifpi%d: ISAC %s (IOM-%c)\n", unit,
 641                 "2085 Version A1/A2 or 2086/2186 Version 1.1",
 642                  sc->sc_bustyp == BUS_TYPE_IOM1 ? '1' : '2');
 643
 644         /* init the ISAC */
 645         ifpi_isac_init(sc);
 646
 647         /* init the "HSCX" */
 648         avma1pp_bchannel_setup(sc->sc_unit, HSCX_CH_A, BPROT_NONE, 0);
 649
 650         avma1pp_bchannel_setup(sc->sc_unit, HSCX_CH_B, BPROT_NONE, 0);
 651
 652         /* can't use the normal B-Channel stuff */
 653         avma1pp_init_linktab(sc);
 654
 655         /* set trace level */
 656
 657         sc->sc_trace = TRACE_OFF;
 658
 659         sc->sc_state = ISAC_IDLE;
 660
 661         sc->sc_ibuf = NULL;
 662         sc->sc_ib = NULL;
 663         sc->sc_ilen = 0;
 664
 665         sc->sc_obuf = NULL;
 666         sc->sc_op = NULL;
 667         sc->sc_ol = 0;
 668         sc->sc_freeflag = 0;
 669
 670         sc->sc_obuf2 = NULL;
 671         sc->sc_freeflag2 = 0;
 672
 673         callout_init(&sc->sc_T3_timeout);
 674         callout_init(&sc->sc_T4_timeout);
 675
 676         /* init higher protocol layers */
 677
 678         i4b_l1_mph_status_ind(L0IFPIUNIT(sc->sc_unit), STI_ATTACH, sc->sc_cardtyp, &avma1pp_l1mux_func);
 679
 680   fail:
 681         crit_exit();
 682         return(error);
 683 }
 684
 685 /*
 686  * this is the real interrupt routine
 687  */
 688 static void
 689 avma1pp_hscx_intr(int h_chan, u_int stat, struct l1_softc *sc)
 690 {
 691         l1_bchan_state_t *chan = &sc->sc_chan[h_chan];
 692         int activity = -1;
 693         u_int param = 0;
 694
 695         NDBGL1(L1_H_IRQ, "%#x", stat);
 696
 697         if((stat & HSCX_INT_XDU) && (chan->bprot != BPROT_NONE))/* xmit data underrun */
 698         {
 699                 chan->stat_XDU++;
 700                 NDBGL1(L1_H_XFRERR, "xmit data underrun");
 701                 /* abort the transmission */
 702                 sc->avma1pp_txl = 0;
 703                 sc->avma1pp_cmd |= HSCX_CMD_XRS;
 704                 AVMA1PPSETCMDLONG(param);
 705                 hscx_write_reg(h_chan, HSCX_STAT, param, sc);
 706                 sc->avma1pp_cmd &= ~HSCX_CMD_XRS;
 707                 AVMA1PPSETCMDLONG(param);
 708                 hscx_write_reg(h_chan, HSCX_STAT, param, sc);
 709
 710                 if (chan->out_mbuf_head != NULL)  /* don't continue to transmit this buffer */
 711                 {
 712                         i4b_Bfreembuf(chan->out_mbuf_head);
 713                         chan->out_mbuf_cur = chan->out_mbuf_head = NULL;
 714                 }
 715         }
 716
 717         /*
 718          * The following is based on examination of the Linux driver.
 719          *
 720          * The logic here is different than with a "real" HSCX; all kinds
 721          * of information (interrupt/status bits) are in stat.
 722          *              HSCX_INT_RPR indicates a receive interrupt
 723          *                      HSCX_STAT_RDO indicates an overrun condition, abort -
 724          *                      otherwise read the bytes ((stat & HSCX_STZT_RML_MASK) >> 8)
 725          *                      HSCX_STAT_RME indicates end-of-frame and apparently any
 726          *                      CRC/framing errors are only reported in this state.
 727          *                              if ((stat & HSCX_STAT_CRCVFRRAB) != HSCX_STAT_CRCVFR)
 728          *                                      CRC/framing error
 729          */
 730
 731         if(stat & HSCX_INT_RPR)
 732         {
 733                 int fifo_data_len;
 734                 int error = 0;
 735                 /* always have to read the FIFO, so use a scratch buffer */
 736                 u_char scrbuf[HSCX_FIFO_LEN];
 737
 738                 if(stat & HSCX_STAT_RDO)
 739                 {
 740                         chan->stat_RDO++;
 741                         NDBGL1(L1_H_XFRERR, "receive data overflow");
 742                         error++;
 743                 }
 744
 745                 /*
 746                  * check whether we're receiving data for an inactive B-channel
 747                  * and discard it. This appears to happen for telephony when
 748                  * both B-channels are active and one is deactivated. Since
 749                  * it is not really possible to deactivate the channel in that
 750                  * case (the ASIC seems to deactivate _both_ channels), the
 751                  * "deactivated" channel keeps receiving data which can lead
 752                  * to exhaustion of mbufs and a kernel panic.
 753                  *
 754                  * This is a hack, but it's the only solution I can think of
 755                  * without having the documentation for the ASIC.
 756                  * GJ - 28 Nov 1999
 757                  */
 758                  if (chan->state == HSCX_IDLE)
 759                  {
 760                         NDBGL1(L1_H_XFRERR, "toss data from %d", h_chan);
 761                         error++;
 762                  }
 763
 764                 fifo_data_len = ((stat & HSCX_STAT_RML_MASK) >> 8);
 765
 766                 if(fifo_data_len == 0)
 767                         fifo_data_len = sc->sc_bfifolen;
 768
 769                 /* ALWAYS read data from HSCX fifo */
 770
 771                 HSCX_RDFIFO(h_chan, scrbuf, fifo_data_len);
 772                 chan->rxcount += fifo_data_len;
 773
 774                 /* all error conditions checked, now decide and take action */
 775
 776                 if(error == 0)
 777                 {
 778                         if(chan->in_mbuf == NULL)
 779                         {
 780                                 if((chan->in_mbuf = i4b_Bgetmbuf(BCH_MAX_DATALEN)) == NULL)
 781                                         panic("L1 avma1pp_hscx_intr: RME, cannot allocate mbuf!\n");
 782                                 chan->in_cbptr = chan->in_mbuf->m_data;
 783                                 chan->in_len = 0;
 784                         }
 785
 786                         if((chan->in_len + fifo_data_len) <= BCH_MAX_DATALEN)
 787                         {
 788                                 /* OK to copy the data */
 789                                 bcopy(scrbuf, chan->in_cbptr, fifo_data_len);
 790                                 chan->in_cbptr += fifo_data_len;
 791                                 chan->in_len += fifo_data_len;
 792
 793                                 /* setup mbuf data length */
 794
 795                                 chan->in_mbuf->m_len = chan->in_len;
 796                                 chan->in_mbuf->m_pkthdr.len = chan->in_len;
 797
 798                                 if(sc->sc_trace & TRACE_B_RX)
 799                                 {
 800                                         i4b_trace_hdr_t hdr;
 801                                         hdr.unit = L0IFPIUNIT(sc->sc_unit);
 802                                         hdr.type = (h_chan == HSCX_CH_A ? TRC_CH_B1 : TRC_CH_B2);
 803                                         hdr.dir = FROM_NT;
 804                                         hdr.count = ++sc->sc_trace_bcount;
 805                                         MICROTIME(hdr.time);
 806                                         i4b_l1_trace_ind(&hdr, chan->in_mbuf->m_len, chan->in_mbuf->m_data);
 807                                 }
 808
 809                                 if (stat & HSCX_STAT_RME)
 810                                 {
 811                                   if((stat & HSCX_STAT_CRCVFRRAB) == HSCX_STAT_CRCVFR)
 812                                   {
 813                                          (*chan->isic_drvr_linktab->bch_rx_data_ready)(chan->isic_drvr_linktab->unit);
 814                                          activity = ACT_RX;
 815
 816                                          /* mark buffer ptr as unused */
 817
 818                                          chan->in_mbuf = NULL;
 819                                          chan->in_cbptr = NULL;
 820                                          chan->in_len = 0;
 821                                   }
 822                                   else
 823                                   {
 824                                                 chan->stat_CRC++;
 825                                                 NDBGL1(L1_H_XFRERR, "CRC/RAB");
 826                                           if (chan->in_mbuf != NULL)
 827                                           {
 828                                                   i4b_Bfreembuf(chan->in_mbuf);
 829                                                   chan->in_mbuf = NULL;
 830                                                   chan->in_cbptr = NULL;
 831                                                   chan->in_len = 0;
 832                                           }
 833                                   }
 834                                 }
 835                         } /* END enough space in mbuf */
 836                         else
 837                         {
 838                                  if(chan->bprot == BPROT_NONE)
 839                                  {
 840                                           /* setup mbuf data length */
 841
 842                                           chan->in_mbuf->m_len = chan->in_len;
 843                                           chan->in_mbuf->m_pkthdr.len = chan->in_len;
 844
 845                                           if(sc->sc_trace & TRACE_B_RX)
 846                                           {
 847                                                         i4b_trace_hdr_t hdr;
 848                                                         hdr.unit = L0IFPIUNIT(sc->sc_unit);
 849                                                         hdr.type = (h_chan == HSCX_CH_A ? TRC_CH_B1 : TRC_CH_B2);
 850                                                         hdr.dir = FROM_NT;
 851                                                         hdr.count = ++sc->sc_trace_bcount;
 852                                                         MICROTIME(hdr.time);
 853                                                         i4b_l1_trace_ind(&hdr, chan->in_mbuf->m_len, chan->in_mbuf->m_data);
 854                                                 }
 855
 856                                           if(!(i4b_l1_bchan_tel_silence(chan->in_mbuf->m_data, chan->in_mbuf->m_len)))
 857                                                  activity = ACT_RX;
 858
 859                                           /* move rx'd data to rx queue */
 860
 861                                           if(!(IF_QFULL(&chan->rx_queue)))
 862                                           {
 863                                                 IF_ENQUEUE(&chan->rx_queue, chan->in_mbuf);
 864                                           }
 865                                           else
 866                                           {
 867                                                 i4b_Bfreembuf(chan->in_mbuf);
 868                                           }
 869                                           /* signal upper layer that data are available */
 870                                           (*chan->isic_drvr_linktab->bch_rx_data_ready)(chan->isic_drvr_linktab->unit);
 871
 872                                           /* alloc new buffer */
 873
 874                                           if((chan->in_mbuf = i4b_Bgetmbuf(BCH_MAX_DATALEN)) == NULL)
 875                                                  panic("L1 avma1pp_hscx_intr: RPF, cannot allocate new mbuf!\n");
 876
 877                                           /* setup new data ptr */
 878
 879                                           chan->in_cbptr = chan->in_mbuf->m_data;
 880
 881                                           /* OK to copy the data */
 882                                           bcopy(scrbuf, chan->in_cbptr, fifo_data_len);
 883
 884                                           chan->in_cbptr += fifo_data_len;
 885                                           chan->in_len = fifo_data_len;
 886
 887                                           chan->rxcount += fifo_data_len;
 888                                         }
 889                                  else
 890                                         {
 891                                           NDBGL1(L1_H_XFRERR, "RAWHDLC rx buffer overflow in RPF, in_len=%d", chan->in_len);
 892                                           chan->in_cbptr = chan->in_mbuf->m_data;
 893                                           chan->in_len = 0;
 894                                         }
 895                           }
 896                 } /* if(error == 0) */
 897                 else
 898                 {
 899                         /* land here for RDO */
 900                         if (chan->in_mbuf != NULL)
 901                         {
 902                                 i4b_Bfreembuf(chan->in_mbuf);
 903                                 chan->in_mbuf = NULL;
 904                                 chan->in_cbptr = NULL;
 905                                 chan->in_len = 0;
 906                         }
 907                         sc->avma1pp_txl = 0;
 908                         sc->avma1pp_cmd |= HSCX_CMD_RRS;
 909                         AVMA1PPSETCMDLONG(param);
 910                         hscx_write_reg(h_chan, HSCX_STAT, param, sc);
 911                         sc->avma1pp_cmd &= ~HSCX_CMD_RRS;
 912                         AVMA1PPSETCMDLONG(param);
 913                         hscx_write_reg(h_chan, HSCX_STAT, param, sc);
 914                 }
 915         }
 916
 917
 918         /* transmit fifo empty, new data can be written to fifo */
 919
 920         if(stat & HSCX_INT_XPR)
 921         {
 922                 /*
 923                  * for a description what is going on here, please have
 924                  * a look at isic_bchannel_start() in i4b_bchan.c !
 925                  */
 926
 927                 NDBGL1(L1_H_IRQ, "unit %d, chan %d - XPR, Tx Fifo Empty!", sc->sc_unit, h_chan);
 928
 929                 if(chan->out_mbuf_cur == NULL)  /* last frame is transmitted */
 930                 {
 931                         IF_DEQUEUE(&chan->tx_queue, chan->out_mbuf_head);
 932
 933                         if(chan->out_mbuf_head == NULL)
 934                         {
 935                                 chan->state &= ~HSCX_TX_ACTIVE;
 936                                 (*chan->isic_drvr_linktab->bch_tx_queue_empty)(chan->isic_drvr_linktab->unit);
 937                         }
 938                         else
 939                         {
 940                                 chan->state |= HSCX_TX_ACTIVE;
 941                                 chan->out_mbuf_cur = chan->out_mbuf_head;
 942                                 chan->out_mbuf_cur_ptr = chan->out_mbuf_cur->m_data;
 943                                 chan->out_mbuf_cur_len = chan->out_mbuf_cur->m_len;
 944
 945                                 if(sc->sc_trace & TRACE_B_TX)
 946                                 {
 947                                         i4b_trace_hdr_t hdr;
 948                                         hdr.unit = L0IFPIUNIT(sc->sc_unit);
 949                                         hdr.type = (h_chan == HSCX_CH_A ? TRC_CH_B1 : TRC_CH_B2);
 950                                         hdr.dir = FROM_TE;
 951                                         hdr.count = ++sc->sc_trace_bcount;
 952                                         MICROTIME(hdr.time);
 953                                         i4b_l1_trace_ind(&hdr, chan->out_mbuf_cur->m_len, chan->out_mbuf_cur->m_data);
 954                                 }
 955
 956                                 if(chan->bprot == BPROT_NONE)
 957                                 {
 958                                         if(!(i4b_l1_bchan_tel_silence(chan->out_mbuf_cur->m_data, chan->out_mbuf_cur->m_len)))
 959                                                 activity = ACT_TX;
 960                                 }
 961                                 else
 962                                 {
 963                                         activity = ACT_TX;
 964                                 }
 965                         }
 966                 }
 967
 968                 avma1pp_hscx_fifo(chan, sc);
 969         }
 970
 971         /* call timeout handling routine */
 972
 973         if(activity == ACT_RX || activity == ACT_TX)
 974                 (*chan->isic_drvr_linktab->bch_activity)(chan->isic_drvr_linktab->unit, activity);
 975 }
 976
 977 /*
 978  * this is the main routine which checks each channel and then calls
 979  * the real interrupt routine as appropriate
 980  */
 981 static void
 982 avma1pp_hscx_int_handler(struct l1_softc *sc)
 983 {
 984         u_int stat;
 985
 986         /* has to be a u_int because the byte count is in the 2nd byte */
 987         stat = hscx_read_reg_int(0, HSCX_STAT, sc);
 988         if (stat & HSCX_INT_MASK)
 989           avma1pp_hscx_intr(0, stat, sc);
 990         stat = hscx_read_reg_int(1, HSCX_STAT, sc);
 991         if (stat & HSCX_INT_MASK)
 992           avma1pp_hscx_intr(1, stat, sc);
 993 }
 994
 995 static void
 996 avma1pp_disable(device_t dev)
 997 {
 998         struct l1_softc *sc = device_get_softc(dev);
 999         bus_space_handle_t bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
1000         bus_space_tag_t btag = rman_get_bustag(sc->sc_resources.io_base[0]);
1001
1002         bus_space_write_1(btag, bhandle, STAT0_OFFSET, ASL_RESET_ALL|ASL_TIMERDISABLE);
1003 }
1004
1005 static void
1006 avma1pp_intr(void *xsc)
1007 {
1008         u_char stat;
1009         struct l1_softc *sc;
1010         bus_space_handle_t bhandle;
1011         bus_space_tag_t btag;
1012
1013         sc = xsc;
1014         bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
1015         btag = rman_get_bustag(sc->sc_resources.io_base[0]);
1016
1017         stat = bus_space_read_1(btag, bhandle, STAT0_OFFSET);
1018         NDBGL1(L1_H_IRQ, "stat %x", stat);
1019         /* was there an interrupt from this card ? */
1020         if ((stat & ASL_IRQ_Pending) == ASL_IRQ_Pending)
1021                 return; /* no */
1022         /* interrupts are low active */
1023         if (!(stat & ASL_IRQ_TIMER))
1024           NDBGL1(L1_H_IRQ, "timer interrupt ???");
1025         if (!(stat & ASL_IRQ_HSCX))
1026         {
1027           NDBGL1(L1_H_IRQ, "HSCX");
1028                 avma1pp_hscx_int_handler(sc);
1029         }
1030         if (!(stat & ASL_IRQ_ISAC))
1031         {
1032           NDBGL1(L1_H_IRQ, "ISAC");
1033                 ifpi_isac_intr(sc);
1034         }
1035 }
1036
1037 static void
1038 avma1pp_hscx_init(struct l1_softc *sc, int h_chan, int activate)
1039 {
1040         l1_bchan_state_t *chan = &sc->sc_chan[h_chan];
1041         u_int param = 0;
1042
1043         NDBGL1(L1_BCHAN, "unit=%d, channel=%d, %s",
1044                 sc->sc_unit, h_chan, activate ? "activate" : "deactivate");
1045
1046         if (activate == 0)
1047         {
1048                 /* only deactivate if both channels are idle */
1049                 if (sc->sc_chan[HSCX_CH_A].state != HSCX_IDLE ||
1050                         sc->sc_chan[HSCX_CH_B].state != HSCX_IDLE)
1051                 {
1052                         return;
1053                 }
1054                 sc->avma1pp_cmd = HSCX_CMD_XRS|HSCX_CMD_RRS;
1055                 sc->avma1pp_prot = HSCX_MODE_TRANS;
1056                 AVMA1PPSETCMDLONG(param);
1057                 hscx_write_reg(h_chan, HSCX_STAT, param, sc);
1058                 return;
1059         }
1060         if(chan->bprot == BPROT_RHDLC)
1061         {
1062                   NDBGL1(L1_BCHAN, "BPROT_RHDLC");
1063
1064                 /* HDLC Frames, transparent mode 0 */
1065                 sc->avma1pp_cmd = HSCX_CMD_XRS|HSCX_CMD_RRS;
1066                 sc->avma1pp_prot = HSCX_MODE_ITF_FLG;
1067                 AVMA1PPSETCMDLONG(param);
1068                 hscx_write_reg(h_chan, HSCX_STAT, param, sc);
1069                 sc->avma1pp_cmd = HSCX_CMD_XRS;
1070                 AVMA1PPSETCMDLONG(param);
1071                 hscx_write_reg(h_chan, HSCX_STAT, param, sc);
1072                 sc->avma1pp_cmd = 0;
1073         }
1074         else
1075         {
1076                   NDBGL1(L1_BCHAN, "BPROT_NONE??");
1077
1078                 /* Raw Telephony, extended transparent mode 1 */
1079                 sc->avma1pp_cmd = HSCX_CMD_XRS|HSCX_CMD_RRS;
1080                 sc->avma1pp_prot = HSCX_MODE_TRANS;
1081                 AVMA1PPSETCMDLONG(param);
1082                 hscx_write_reg(h_chan, HSCX_STAT, param, sc);
1083                 sc->avma1pp_cmd = HSCX_CMD_XRS;
1084                 AVMA1PPSETCMDLONG(param);
1085                 hscx_write_reg(h_chan, HSCX_STAT, param, sc);
1086                 sc->avma1pp_cmd = 0;
1087         }
1088 }
1089
1090 static void
1091 avma1pp_bchannel_setup(int unit, int h_chan, int bprot, int activate)
1092 {
1093         struct l1_softc *sc = ifpi_scp[unit];
1094         l1_bchan_state_t *chan = &sc->sc_chan[h_chan];
1095
1096         crit_enter();
1097
1098         if(activate == 0)
1099         {
1100                 /* deactivation */
1101                 chan->state = HSCX_IDLE;
1102                 avma1pp_hscx_init(sc, h_chan, activate);
1103         }
1104
1105         NDBGL1(L1_BCHAN, "unit=%d, channel=%d, %s",
1106                 sc->sc_unit, h_chan, activate ? "activate" : "deactivate");
1107
1108         /* general part */
1109
1110         chan->unit = sc->sc_unit;       /* unit number */
1111         chan->channel = h_chan;         /* B channel */
1112         chan->bprot = bprot;            /* B channel protocol */
1113         chan->state = HSCX_IDLE;        /* B channel state */
1114
1115         /* receiver part */
1116
1117         chan->rx_queue.ifq_maxlen = IFQ_MAXLEN;
1118
1119         i4b_Bcleanifq(&chan->rx_queue); /* clean rx queue */
1120
1121         chan->rxcount = 0;              /* reset rx counter */
1122
1123         i4b_Bfreembuf(chan->in_mbuf);   /* clean rx mbuf */
1124
1125         chan->in_mbuf = NULL;           /* reset mbuf ptr */
1126         chan->in_cbptr = NULL;          /* reset mbuf curr ptr */
1127         chan->in_len = 0;               /* reset mbuf data len */
1128
1129         /* transmitter part */
1130
1131         chan->tx_queue.ifq_maxlen = IFQ_MAXLEN;
1132
1133         i4b_Bcleanifq(&chan->tx_queue); /* clean tx queue */
1134
1135         chan->txcount = 0;              /* reset tx counter */
1136
1137         i4b_Bfreembuf(chan->out_mbuf_head);     /* clean tx mbuf */
1138
1139         chan->out_mbuf_head = NULL;     /* reset head mbuf ptr */
1140         chan->out_mbuf_cur = NULL;      /* reset current mbuf ptr */
1141         chan->out_mbuf_cur_ptr = NULL;  /* reset current mbuf data ptr */
1142         chan->out_mbuf_cur_len = 0;     /* reset current mbuf data cnt */
1143
1144         if(activate != 0)
1145         {
1146                 /* activation */
1147                 avma1pp_hscx_init(sc, h_chan, activate);
1148                 chan->state |= HSCX_AVMA1PP_ACTIVE;
1149         }
1150
1151         crit_exit();
1152 }
1153
1154 static void
1155 avma1pp_bchannel_start(int unit, int h_chan)
1156 {
1157         struct l1_softc *sc = ifpi_scp[unit];
1158         l1_bchan_state_t *chan = &sc->sc_chan[h_chan];
1159         int activity = -1;
1160
1161         crit_enter();
1162         if(chan->state & HSCX_TX_ACTIVE)        /* already running ? */
1163         {
1164                 crit_exit();
1165                 return;                         /* yes, leave */
1166         }
1167
1168         /* get next mbuf from queue */
1169
1170         IF_DEQUEUE(&chan->tx_queue, chan->out_mbuf_head);
1171
1172         if(chan->out_mbuf_head == NULL)         /* queue empty ? */
1173         {
1174                 crit_exit();
1175                 return;                         /* yes, exit */
1176         }
1177
1178         /* init current mbuf values */
1179
1180         chan->out_mbuf_cur = chan->out_mbuf_head;
1181         chan->out_mbuf_cur_len = chan->out_mbuf_cur->m_len;
1182         chan->out_mbuf_cur_ptr = chan->out_mbuf_cur->m_data;
1183
1184         /* activity indicator for timeout handling */
1185
1186         if(chan->bprot == BPROT_NONE)
1187         {
1188                 if(!(i4b_l1_bchan_tel_silence(chan->out_mbuf_cur->m_data, chan->out_mbuf_cur->m_len)))
1189                         activity = ACT_TX;
1190         }
1191         else
1192         {
1193                 activity = ACT_TX;
1194         }
1195
1196         chan->state |= HSCX_TX_ACTIVE;          /* we start transmitting */
1197
1198         if(sc->sc_trace & TRACE_B_TX)   /* if trace, send mbuf to trace dev */
1199         {
1200                 i4b_trace_hdr_t hdr;
1201                 hdr.unit = L0IFPIUNIT(sc->sc_unit);
1202                 hdr.type = (h_chan == HSCX_CH_A ? TRC_CH_B1 : TRC_CH_B2);
1203                 hdr.dir = FROM_TE;
1204                 hdr.count = ++sc->sc_trace_bcount;
1205                 MICROTIME(hdr.time);
1206                 i4b_l1_trace_ind(&hdr, chan->out_mbuf_cur->m_len, chan->out_mbuf_cur->m_data);
1207         }
1208
1209         avma1pp_hscx_fifo(chan, sc);
1210
1211         /* call timeout handling routine */
1212
1213         if(activity == ACT_RX || activity == ACT_TX)
1214                 (*chan->isic_drvr_linktab->bch_activity)(chan->isic_drvr_linktab->unit, activity);
1215
1216         crit_exit();
1217 }
1218
1219 /*---------------------------------------------------------------------------*
1220  *      return the address of isic drivers linktab
1221  *---------------------------------------------------------------------------*/
1222 static isdn_link_t *
1223 avma1pp_ret_linktab(int unit, int channel)
1224 {
1225         struct l1_softc *sc = ifpi_scp[unit];
1226         l1_bchan_state_t *chan = &sc->sc_chan[channel];
1227
1228         return(&chan->isic_isdn_linktab);
1229 }
1230
1231 /*---------------------------------------------------------------------------*
1232  *      set the driver linktab in the b channel softc
1233  *---------------------------------------------------------------------------*/
1234 static void
1235 avma1pp_set_linktab(int unit, int channel, drvr_link_t *dlt)
1236 {
1237         struct l1_softc *sc = ifpi_scp[unit];
1238         l1_bchan_state_t *chan = &sc->sc_chan[channel];
1239
1240         chan->isic_drvr_linktab = dlt;
1241 }
1242
1243
1244 /*---------------------------------------------------------------------------*
1245  *      initialize our local linktab
1246  *---------------------------------------------------------------------------*/
1247 static void
1248 avma1pp_init_linktab(struct l1_softc *sc)
1249 {
1250         l1_bchan_state_t *chan = &sc->sc_chan[HSCX_CH_A];
1251         isdn_link_t *lt = &chan->isic_isdn_linktab;
1252
1253         /* make sure the hardware driver is known to layer 4 */
1254         /* avoid overwriting if already set */
1255         if (ctrl_types[CTRL_PASSIVE].set_linktab == NULL)
1256         {
1257                 ctrl_types[CTRL_PASSIVE].set_linktab = avma1pp_set_linktab;
1258                 ctrl_types[CTRL_PASSIVE].get_linktab = avma1pp_ret_linktab;
1259         }
1260
1261         /* local setup */
1262         lt->unit = sc->sc_unit;
1263         lt->channel = HSCX_CH_A;
1264         lt->bch_config = avma1pp_bchannel_setup;
1265         lt->bch_tx_start = avma1pp_bchannel_start;
1266         lt->bch_stat = avma1pp_bchannel_stat;
1267         lt->tx_queue = &chan->tx_queue;
1268
1269         /* used by non-HDLC data transfers, i.e. telephony drivers */
1270         lt->rx_queue = &chan->rx_queue;
1271
1272         /* used by HDLC data transfers, i.e. ipr and isp drivers */
1273         lt->rx_mbuf = &chan->in_mbuf;
1274
1275         chan = &sc->sc_chan[HSCX_CH_B];
1276         lt = &chan->isic_isdn_linktab;
1277
1278         lt->unit = sc->sc_unit;
1279         lt->channel = HSCX_CH_B;
1280         lt->bch_config = avma1pp_bchannel_setup;
1281         lt->bch_tx_start = avma1pp_bchannel_start;
1282         lt->bch_stat = avma1pp_bchannel_stat;
1283         lt->tx_queue = &chan->tx_queue;
1284
1285         /* used by non-HDLC data transfers, i.e. telephony drivers */
1286         lt->rx_queue = &chan->rx_queue;
1287
1288         /* used by HDLC data transfers, i.e. ipr and isp drivers */
1289         lt->rx_mbuf = &chan->in_mbuf;
1290 }
1291
1292 /*
1293  * use this instead of isic_bchannel_stat in i4b_bchan.c because it's static
1294  */
1295 static void
1296 avma1pp_bchannel_stat(int unit, int h_chan, bchan_statistics_t *bsp)
1297 {
1298         struct l1_softc *sc = ifpi_scp[unit];
1299         l1_bchan_state_t *chan = &sc->sc_chan[h_chan];
1300
1301         crit_enter();
1302
1303         bsp->outbytes = chan->txcount;
1304         bsp->inbytes = chan->rxcount;
1305
1306         chan->txcount = 0;
1307         chan->rxcount = 0;
1308
1309         crit_exit();
1310 }
1311
1312 /*---------------------------------------------------------------------------*
1313  *      fill HSCX fifo with data from the current mbuf
1314  *      Put this here until it can go into i4b_hscx.c
1315  *---------------------------------------------------------------------------*/
1316 static int
1317 avma1pp_hscx_fifo(l1_bchan_state_t *chan, struct l1_softc *sc)
1318 {
1319         int len;
1320         int nextlen;
1321         int i;
1322         int cmd = 0;
1323         /* using a scratch buffer simplifies writing to the FIFO */
1324         u_char scrbuf[HSCX_FIFO_LEN];
1325
1326         len = 0;
1327
1328         /*
1329          * fill the HSCX tx fifo with data from the current mbuf. if
1330          * current mbuf holds less data than HSCX fifo length, try to
1331          * get the next mbuf from (a possible) mbuf chain. if there is
1332          * not enough data in a single mbuf or in a chain, then this
1333          * is the last mbuf and we tell the HSCX that it has to send
1334          * CRC and closing flag
1335          */
1336
1337         while(chan->out_mbuf_cur && len != sc->sc_bfifolen)
1338         {
1339                 nextlen = min(chan->out_mbuf_cur_len, sc->sc_bfifolen - len);
1340
1341 #ifdef NOTDEF
1342                 kprintf("i:mh=%p, mc=%p, mcp=%p, mcl=%d l=%d nl=%d # ",
1343                         chan->out_mbuf_head,
1344                         chan->out_mbuf_cur,
1345                         chan->out_mbuf_cur_ptr,
1346                         chan->out_mbuf_cur_len,
1347                         len,
1348                         nextlen);
1349 #endif
1350
1351                 cmd |= HSCX_CMDR_XTF;
1352                 /* collect the data in the scratch buffer */
1353                 for (i = 0; i < nextlen; i++)
1354                         scrbuf[i + len] = chan->out_mbuf_cur_ptr[i];
1355
1356                 len += nextlen;
1357                 chan->txcount += nextlen;
1358
1359                 chan->out_mbuf_cur_ptr += nextlen;
1360                 chan->out_mbuf_cur_len -= nextlen;
1361
1362                 if(chan->out_mbuf_cur_len == 0)
1363                 {
1364                         if((chan->out_mbuf_cur = chan->out_mbuf_cur->m_next) != NULL)
1365                         {
1366                                 chan->out_mbuf_cur_ptr = chan->out_mbuf_cur->m_data;
1367                                 chan->out_mbuf_cur_len = chan->out_mbuf_cur->m_len;
1368
1369                                 if(sc->sc_trace & TRACE_B_TX)
1370                                 {
1371                                         i4b_trace_hdr_t hdr;
1372                                         hdr.unit = L0IFPIUNIT(sc->sc_unit);
1373                                         hdr.type = (chan->channel == HSCX_CH_A ? TRC_CH_B1 : TRC_CH_B2);
1374                                         hdr.dir = FROM_TE;
1375                                         hdr.count = ++sc->sc_trace_bcount;
1376                                         MICROTIME(hdr.time);
1377                                         i4b_l1_trace_ind(&hdr, chan->out_mbuf_cur->m_len, chan->out_mbuf_cur->m_data);
1378                                 }
1379                         }
1380                         else
1381                         {
1382                                 if (chan->bprot != BPROT_NONE)
1383                                         cmd |= HSCX_CMDR_XME;
1384                                 i4b_Bfreembuf(chan->out_mbuf_head);
1385                                 chan->out_mbuf_head = NULL;
1386                         }
1387                 }
1388         }
1389         /* write what we have from the scratch buf to the HSCX fifo */
1390         if (len != 0)
1391                 HSCX_WRFIFO(chan->channel, scrbuf, len);
1392         return(cmd);
1393 }
1394
1395 /*---------------------------------------------------------------------------*
1396  *      ifpi - ISAC interrupt routine
1397  *---------------------------------------------------------------------------*/
1398 static void
1399 ifpi_isac_intr(struct l1_softc *sc)
1400 {
1401         u_char isac_irq_stat;
1402
1403         for(;;)
1404         {
1405                 /* get isac irq status */
1406                 isac_irq_stat = ISAC_READ(I_ISTA);
1407
1408                 if(isac_irq_stat)
1409                         ifpi_isac_irq(sc, isac_irq_stat); /* isac handler */
1410                 else
1411                         break;
1412         }
1413
1414         ISAC_WRITE(I_MASK, 0xff);
1415
1416         DELAY(100);
1417
1418         ISAC_WRITE(I_MASK, ISAC_IMASK);
1419 }
1420
1421 /*---------------------------------------------------------------------------*
1422  *      ifpi_recover - try to recover from irq lockup
1423  *---------------------------------------------------------------------------*/
1424 void
1425 ifpi_recover(struct l1_softc *sc)
1426 {
1427         u_char byte;
1428
1429         /* get isac irq status */
1430
1431         byte = ISAC_READ(I_ISTA);
1432
1433         NDBGL1(L1_ERROR, "  ISAC: ISTA = 0x%x", byte);
1434
1435         if(byte & ISAC_ISTA_EXI)
1436                 NDBGL1(L1_ERROR, "  ISAC: EXIR = 0x%x", (u_char)ISAC_READ(I_EXIR));
1437
1438         if(byte & ISAC_ISTA_CISQ)
1439         {
1440                 byte = ISAC_READ(I_CIRR);
1441
1442                 NDBGL1(L1_ERROR, "  ISAC: CISQ = 0x%x", byte);
1443
1444                 if(byte & ISAC_CIRR_SQC)
1445                         NDBGL1(L1_ERROR, "  ISAC: SQRR = 0x%x", (u_char)ISAC_READ(I_SQRR));
1446         }
1447
1448         NDBGL1(L1_ERROR, "  ISAC: IMASK = 0x%x", ISAC_IMASK);
1449
1450         ISAC_WRITE(I_MASK, 0xff);
1451         DELAY(100);
1452         ISAC_WRITE(I_MASK, ISAC_IMASK);
1453 }
1454
1455
1456 #endif /* NIFPI > 0 */