2 * Copyright (c) 1991 The Regents of the University of California.
3 * Copyright (c) 1996, by Steve Passe. All rights reserved.
4 * Copyright (c) 2005,2008 The DragonFly Project. All rights reserved.
7 * This code is derived from software contributed to The DragonFly Project
8 * by Matthew Dillon <dillon@backplane.com>
10 * This code is derived from software contributed to Berkeley by
13 * Redistribution and use in source and binary forms, with or without
14 * modification, are permitted provided that the following conditions
17 * 1. Redistributions of source code must retain the above copyright
18 * notice, this list of conditions and the following disclaimer.
19 * 2. Redistributions in binary form must reproduce the above copyright
20 * notice, this list of conditions and the following disclaimer in
21 * the documentation and/or other materials provided with the
23 * 3. Neither the name of The DragonFly Project nor the names of its
24 * contributors may be used to endorse or promote products derived
25 * from this software without specific, prior written permission.
27 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
29 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
30 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
31 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
32 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
33 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
34 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
35 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
36 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
37 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
40 * $DragonFly: src/sys/platform/pc64/apic/apic_abi.c,v 1.1 2008/08/29 17:07:12 dillon Exp $
43 #include <sys/param.h>
44 #include <sys/systm.h>
45 #include <sys/kernel.h>
46 #include <sys/machintr.h>
47 #include <sys/interrupt.h>
50 #include <machine/smp.h>
51 #include <machine/segments.h>
52 #include <machine/md_var.h>
53 #include <machine/intr_machdep.h>
54 #include <machine/globaldata.h>
56 #include <sys/thread2.h>
58 #include <machine_base/isa/isa_intr.h>
59 #include <machine_base/icu/icu.h>
60 #include <machine_base/icu/icu_var.h>
61 #include <machine_base/apic/ioapic.h>
62 #include <machine_base/apic/ioapic_abi.h>
63 #include <machine_base/apic/ioapic_ipl.h>
64 #include <machine_base/apic/apicreg.h>
66 #define IOAPIC_HWI_VECTORS IDT_HWI_VECTORS
79 IDTVEC(ioapic_intr10),
80 IDTVEC(ioapic_intr11),
81 IDTVEC(ioapic_intr12),
82 IDTVEC(ioapic_intr13),
83 IDTVEC(ioapic_intr14),
84 IDTVEC(ioapic_intr15),
85 IDTVEC(ioapic_intr16),
86 IDTVEC(ioapic_intr17),
87 IDTVEC(ioapic_intr18),
88 IDTVEC(ioapic_intr19),
89 IDTVEC(ioapic_intr20),
90 IDTVEC(ioapic_intr21),
91 IDTVEC(ioapic_intr22),
92 IDTVEC(ioapic_intr23),
93 IDTVEC(ioapic_intr24),
94 IDTVEC(ioapic_intr25),
95 IDTVEC(ioapic_intr26),
96 IDTVEC(ioapic_intr27),
97 IDTVEC(ioapic_intr28),
98 IDTVEC(ioapic_intr29),
99 IDTVEC(ioapic_intr30),
100 IDTVEC(ioapic_intr31),
101 IDTVEC(ioapic_intr32),
102 IDTVEC(ioapic_intr33),
103 IDTVEC(ioapic_intr34),
104 IDTVEC(ioapic_intr35),
105 IDTVEC(ioapic_intr36),
106 IDTVEC(ioapic_intr37),
107 IDTVEC(ioapic_intr38),
108 IDTVEC(ioapic_intr39),
109 IDTVEC(ioapic_intr40),
110 IDTVEC(ioapic_intr41),
111 IDTVEC(ioapic_intr42),
112 IDTVEC(ioapic_intr43),
113 IDTVEC(ioapic_intr44),
114 IDTVEC(ioapic_intr45),
115 IDTVEC(ioapic_intr46),
116 IDTVEC(ioapic_intr47),
117 IDTVEC(ioapic_intr48),
118 IDTVEC(ioapic_intr49),
119 IDTVEC(ioapic_intr50),
120 IDTVEC(ioapic_intr51),
121 IDTVEC(ioapic_intr52),
122 IDTVEC(ioapic_intr53),
123 IDTVEC(ioapic_intr54),
124 IDTVEC(ioapic_intr55),
125 IDTVEC(ioapic_intr56),
126 IDTVEC(ioapic_intr57),
127 IDTVEC(ioapic_intr58),
128 IDTVEC(ioapic_intr59),
129 IDTVEC(ioapic_intr60),
130 IDTVEC(ioapic_intr61),
131 IDTVEC(ioapic_intr62),
132 IDTVEC(ioapic_intr63),
133 IDTVEC(ioapic_intr64),
134 IDTVEC(ioapic_intr65),
135 IDTVEC(ioapic_intr66),
136 IDTVEC(ioapic_intr67),
137 IDTVEC(ioapic_intr68),
138 IDTVEC(ioapic_intr69),
139 IDTVEC(ioapic_intr70),
140 IDTVEC(ioapic_intr71),
141 IDTVEC(ioapic_intr72),
142 IDTVEC(ioapic_intr73),
143 IDTVEC(ioapic_intr74),
144 IDTVEC(ioapic_intr75),
145 IDTVEC(ioapic_intr76),
146 IDTVEC(ioapic_intr77),
147 IDTVEC(ioapic_intr78),
148 IDTVEC(ioapic_intr79),
149 IDTVEC(ioapic_intr80),
150 IDTVEC(ioapic_intr81),
151 IDTVEC(ioapic_intr82),
152 IDTVEC(ioapic_intr83),
153 IDTVEC(ioapic_intr84),
154 IDTVEC(ioapic_intr85),
155 IDTVEC(ioapic_intr86),
156 IDTVEC(ioapic_intr87),
157 IDTVEC(ioapic_intr88),
158 IDTVEC(ioapic_intr89),
159 IDTVEC(ioapic_intr90),
160 IDTVEC(ioapic_intr91),
161 IDTVEC(ioapic_intr92),
162 IDTVEC(ioapic_intr93),
163 IDTVEC(ioapic_intr94),
164 IDTVEC(ioapic_intr95),
165 IDTVEC(ioapic_intr96),
166 IDTVEC(ioapic_intr97),
167 IDTVEC(ioapic_intr98),
168 IDTVEC(ioapic_intr99),
169 IDTVEC(ioapic_intr100),
170 IDTVEC(ioapic_intr101),
171 IDTVEC(ioapic_intr102),
172 IDTVEC(ioapic_intr103),
173 IDTVEC(ioapic_intr104),
174 IDTVEC(ioapic_intr105),
175 IDTVEC(ioapic_intr106),
176 IDTVEC(ioapic_intr107),
177 IDTVEC(ioapic_intr108),
178 IDTVEC(ioapic_intr109),
179 IDTVEC(ioapic_intr110),
180 IDTVEC(ioapic_intr111),
181 IDTVEC(ioapic_intr112),
182 IDTVEC(ioapic_intr113),
183 IDTVEC(ioapic_intr114),
184 IDTVEC(ioapic_intr115),
185 IDTVEC(ioapic_intr116),
186 IDTVEC(ioapic_intr117),
187 IDTVEC(ioapic_intr118),
188 IDTVEC(ioapic_intr119),
189 IDTVEC(ioapic_intr120),
190 IDTVEC(ioapic_intr121),
191 IDTVEC(ioapic_intr122),
192 IDTVEC(ioapic_intr123),
193 IDTVEC(ioapic_intr124),
194 IDTVEC(ioapic_intr125),
195 IDTVEC(ioapic_intr126),
196 IDTVEC(ioapic_intr127),
197 IDTVEC(ioapic_intr128),
198 IDTVEC(ioapic_intr129),
199 IDTVEC(ioapic_intr130),
200 IDTVEC(ioapic_intr131),
201 IDTVEC(ioapic_intr132),
202 IDTVEC(ioapic_intr133),
203 IDTVEC(ioapic_intr134),
204 IDTVEC(ioapic_intr135),
205 IDTVEC(ioapic_intr136),
206 IDTVEC(ioapic_intr137),
207 IDTVEC(ioapic_intr138),
208 IDTVEC(ioapic_intr139),
209 IDTVEC(ioapic_intr140),
210 IDTVEC(ioapic_intr141),
211 IDTVEC(ioapic_intr142),
212 IDTVEC(ioapic_intr143),
213 IDTVEC(ioapic_intr144),
214 IDTVEC(ioapic_intr145),
215 IDTVEC(ioapic_intr146),
216 IDTVEC(ioapic_intr147),
217 IDTVEC(ioapic_intr148),
218 IDTVEC(ioapic_intr149),
219 IDTVEC(ioapic_intr150),
220 IDTVEC(ioapic_intr151),
221 IDTVEC(ioapic_intr152),
222 IDTVEC(ioapic_intr153),
223 IDTVEC(ioapic_intr154),
224 IDTVEC(ioapic_intr155),
225 IDTVEC(ioapic_intr156),
226 IDTVEC(ioapic_intr157),
227 IDTVEC(ioapic_intr158),
228 IDTVEC(ioapic_intr159),
229 IDTVEC(ioapic_intr160),
230 IDTVEC(ioapic_intr161),
231 IDTVEC(ioapic_intr162),
232 IDTVEC(ioapic_intr163),
233 IDTVEC(ioapic_intr164),
234 IDTVEC(ioapic_intr165),
235 IDTVEC(ioapic_intr166),
236 IDTVEC(ioapic_intr167),
237 IDTVEC(ioapic_intr168),
238 IDTVEC(ioapic_intr169),
239 IDTVEC(ioapic_intr170),
240 IDTVEC(ioapic_intr171),
241 IDTVEC(ioapic_intr172),
242 IDTVEC(ioapic_intr173),
243 IDTVEC(ioapic_intr174),
244 IDTVEC(ioapic_intr175),
245 IDTVEC(ioapic_intr176),
246 IDTVEC(ioapic_intr177),
247 IDTVEC(ioapic_intr178),
248 IDTVEC(ioapic_intr179),
249 IDTVEC(ioapic_intr180),
250 IDTVEC(ioapic_intr181),
251 IDTVEC(ioapic_intr182),
252 IDTVEC(ioapic_intr183),
253 IDTVEC(ioapic_intr184),
254 IDTVEC(ioapic_intr185),
255 IDTVEC(ioapic_intr186),
256 IDTVEC(ioapic_intr187),
257 IDTVEC(ioapic_intr188),
258 IDTVEC(ioapic_intr189),
259 IDTVEC(ioapic_intr190),
260 IDTVEC(ioapic_intr191);
262 static inthand_t *ioapic_intr[IOAPIC_HWI_VECTORS] = {
263 &IDTVEC(ioapic_intr0),
264 &IDTVEC(ioapic_intr1),
265 &IDTVEC(ioapic_intr2),
266 &IDTVEC(ioapic_intr3),
267 &IDTVEC(ioapic_intr4),
268 &IDTVEC(ioapic_intr5),
269 &IDTVEC(ioapic_intr6),
270 &IDTVEC(ioapic_intr7),
271 &IDTVEC(ioapic_intr8),
272 &IDTVEC(ioapic_intr9),
273 &IDTVEC(ioapic_intr10),
274 &IDTVEC(ioapic_intr11),
275 &IDTVEC(ioapic_intr12),
276 &IDTVEC(ioapic_intr13),
277 &IDTVEC(ioapic_intr14),
278 &IDTVEC(ioapic_intr15),
279 &IDTVEC(ioapic_intr16),
280 &IDTVEC(ioapic_intr17),
281 &IDTVEC(ioapic_intr18),
282 &IDTVEC(ioapic_intr19),
283 &IDTVEC(ioapic_intr20),
284 &IDTVEC(ioapic_intr21),
285 &IDTVEC(ioapic_intr22),
286 &IDTVEC(ioapic_intr23),
287 &IDTVEC(ioapic_intr24),
288 &IDTVEC(ioapic_intr25),
289 &IDTVEC(ioapic_intr26),
290 &IDTVEC(ioapic_intr27),
291 &IDTVEC(ioapic_intr28),
292 &IDTVEC(ioapic_intr29),
293 &IDTVEC(ioapic_intr30),
294 &IDTVEC(ioapic_intr31),
295 &IDTVEC(ioapic_intr32),
296 &IDTVEC(ioapic_intr33),
297 &IDTVEC(ioapic_intr34),
298 &IDTVEC(ioapic_intr35),
299 &IDTVEC(ioapic_intr36),
300 &IDTVEC(ioapic_intr37),
301 &IDTVEC(ioapic_intr38),
302 &IDTVEC(ioapic_intr39),
303 &IDTVEC(ioapic_intr40),
304 &IDTVEC(ioapic_intr41),
305 &IDTVEC(ioapic_intr42),
306 &IDTVEC(ioapic_intr43),
307 &IDTVEC(ioapic_intr44),
308 &IDTVEC(ioapic_intr45),
309 &IDTVEC(ioapic_intr46),
310 &IDTVEC(ioapic_intr47),
311 &IDTVEC(ioapic_intr48),
312 &IDTVEC(ioapic_intr49),
313 &IDTVEC(ioapic_intr50),
314 &IDTVEC(ioapic_intr51),
315 &IDTVEC(ioapic_intr52),
316 &IDTVEC(ioapic_intr53),
317 &IDTVEC(ioapic_intr54),
318 &IDTVEC(ioapic_intr55),
319 &IDTVEC(ioapic_intr56),
320 &IDTVEC(ioapic_intr57),
321 &IDTVEC(ioapic_intr58),
322 &IDTVEC(ioapic_intr59),
323 &IDTVEC(ioapic_intr60),
324 &IDTVEC(ioapic_intr61),
325 &IDTVEC(ioapic_intr62),
326 &IDTVEC(ioapic_intr63),
327 &IDTVEC(ioapic_intr64),
328 &IDTVEC(ioapic_intr65),
329 &IDTVEC(ioapic_intr66),
330 &IDTVEC(ioapic_intr67),
331 &IDTVEC(ioapic_intr68),
332 &IDTVEC(ioapic_intr69),
333 &IDTVEC(ioapic_intr70),
334 &IDTVEC(ioapic_intr71),
335 &IDTVEC(ioapic_intr72),
336 &IDTVEC(ioapic_intr73),
337 &IDTVEC(ioapic_intr74),
338 &IDTVEC(ioapic_intr75),
339 &IDTVEC(ioapic_intr76),
340 &IDTVEC(ioapic_intr77),
341 &IDTVEC(ioapic_intr78),
342 &IDTVEC(ioapic_intr79),
343 &IDTVEC(ioapic_intr80),
344 &IDTVEC(ioapic_intr81),
345 &IDTVEC(ioapic_intr82),
346 &IDTVEC(ioapic_intr83),
347 &IDTVEC(ioapic_intr84),
348 &IDTVEC(ioapic_intr85),
349 &IDTVEC(ioapic_intr86),
350 &IDTVEC(ioapic_intr87),
351 &IDTVEC(ioapic_intr88),
352 &IDTVEC(ioapic_intr89),
353 &IDTVEC(ioapic_intr90),
354 &IDTVEC(ioapic_intr91),
355 &IDTVEC(ioapic_intr92),
356 &IDTVEC(ioapic_intr93),
357 &IDTVEC(ioapic_intr94),
358 &IDTVEC(ioapic_intr95),
359 &IDTVEC(ioapic_intr96),
360 &IDTVEC(ioapic_intr97),
361 &IDTVEC(ioapic_intr98),
362 &IDTVEC(ioapic_intr99),
363 &IDTVEC(ioapic_intr100),
364 &IDTVEC(ioapic_intr101),
365 &IDTVEC(ioapic_intr102),
366 &IDTVEC(ioapic_intr103),
367 &IDTVEC(ioapic_intr104),
368 &IDTVEC(ioapic_intr105),
369 &IDTVEC(ioapic_intr106),
370 &IDTVEC(ioapic_intr107),
371 &IDTVEC(ioapic_intr108),
372 &IDTVEC(ioapic_intr109),
373 &IDTVEC(ioapic_intr110),
374 &IDTVEC(ioapic_intr111),
375 &IDTVEC(ioapic_intr112),
376 &IDTVEC(ioapic_intr113),
377 &IDTVEC(ioapic_intr114),
378 &IDTVEC(ioapic_intr115),
379 &IDTVEC(ioapic_intr116),
380 &IDTVEC(ioapic_intr117),
381 &IDTVEC(ioapic_intr118),
382 &IDTVEC(ioapic_intr119),
383 &IDTVEC(ioapic_intr120),
384 &IDTVEC(ioapic_intr121),
385 &IDTVEC(ioapic_intr122),
386 &IDTVEC(ioapic_intr123),
387 &IDTVEC(ioapic_intr124),
388 &IDTVEC(ioapic_intr125),
389 &IDTVEC(ioapic_intr126),
390 &IDTVEC(ioapic_intr127),
391 &IDTVEC(ioapic_intr128),
392 &IDTVEC(ioapic_intr129),
393 &IDTVEC(ioapic_intr130),
394 &IDTVEC(ioapic_intr131),
395 &IDTVEC(ioapic_intr132),
396 &IDTVEC(ioapic_intr133),
397 &IDTVEC(ioapic_intr134),
398 &IDTVEC(ioapic_intr135),
399 &IDTVEC(ioapic_intr136),
400 &IDTVEC(ioapic_intr137),
401 &IDTVEC(ioapic_intr138),
402 &IDTVEC(ioapic_intr139),
403 &IDTVEC(ioapic_intr140),
404 &IDTVEC(ioapic_intr141),
405 &IDTVEC(ioapic_intr142),
406 &IDTVEC(ioapic_intr143),
407 &IDTVEC(ioapic_intr144),
408 &IDTVEC(ioapic_intr145),
409 &IDTVEC(ioapic_intr146),
410 &IDTVEC(ioapic_intr147),
411 &IDTVEC(ioapic_intr148),
412 &IDTVEC(ioapic_intr149),
413 &IDTVEC(ioapic_intr150),
414 &IDTVEC(ioapic_intr151),
415 &IDTVEC(ioapic_intr152),
416 &IDTVEC(ioapic_intr153),
417 &IDTVEC(ioapic_intr154),
418 &IDTVEC(ioapic_intr155),
419 &IDTVEC(ioapic_intr156),
420 &IDTVEC(ioapic_intr157),
421 &IDTVEC(ioapic_intr158),
422 &IDTVEC(ioapic_intr159),
423 &IDTVEC(ioapic_intr160),
424 &IDTVEC(ioapic_intr161),
425 &IDTVEC(ioapic_intr162),
426 &IDTVEC(ioapic_intr163),
427 &IDTVEC(ioapic_intr164),
428 &IDTVEC(ioapic_intr165),
429 &IDTVEC(ioapic_intr166),
430 &IDTVEC(ioapic_intr167),
431 &IDTVEC(ioapic_intr168),
432 &IDTVEC(ioapic_intr169),
433 &IDTVEC(ioapic_intr170),
434 &IDTVEC(ioapic_intr171),
435 &IDTVEC(ioapic_intr172),
436 &IDTVEC(ioapic_intr173),
437 &IDTVEC(ioapic_intr174),
438 &IDTVEC(ioapic_intr175),
439 &IDTVEC(ioapic_intr176),
440 &IDTVEC(ioapic_intr177),
441 &IDTVEC(ioapic_intr178),
442 &IDTVEC(ioapic_intr179),
443 &IDTVEC(ioapic_intr180),
444 &IDTVEC(ioapic_intr181),
445 &IDTVEC(ioapic_intr182),
446 &IDTVEC(ioapic_intr183),
447 &IDTVEC(ioapic_intr184),
448 &IDTVEC(ioapic_intr185),
449 &IDTVEC(ioapic_intr186),
450 &IDTVEC(ioapic_intr187),
451 &IDTVEC(ioapic_intr188),
452 &IDTVEC(ioapic_intr189),
453 &IDTVEC(ioapic_intr190),
454 &IDTVEC(ioapic_intr191)
457 #define IOAPIC_HWI_SYSCALL (IDT_OFFSET_SYSCALL - IDT_OFFSET)
459 static struct ioapic_irqmap {
460 int im_type; /* IOAPIC_IMT_ */
461 enum intr_trigger im_trig;
462 enum intr_polarity im_pola;
464 uint32_t im_flags; /* IOAPIC_IMF_ */
465 } ioapic_irqmaps[IOAPIC_HWI_VECTORS];
467 #define IOAPIC_IMT_UNUSED 0
468 #define IOAPIC_IMT_RESERVED 1
469 #define IOAPIC_IMT_LINE 2
470 #define IOAPIC_IMT_SYSCALL 3
472 #define IOAPIC_IMF_CONF 0x1
474 extern void IOAPIC_INTREN(int);
475 extern void IOAPIC_INTRDIS(int);
477 extern int imcr_present;
479 static void ioapic_abi_intr_setup(int, int);
480 static void ioapic_abi_intr_teardown(int);
481 static void ioapic_finalize(void);
482 static void ioapic_cleanup(void);
483 static void ioapic_setdefault(void);
484 static void ioapic_stabilize(void);
485 static void ioapic_initmap(void);
486 static void ioapic_intr_config(int, enum intr_trigger, enum intr_polarity);
487 static void ioapic_abi_intren(int);
488 static void ioapic_abi_intrdis(int);
490 struct machintr_abi MachIntrABI_IOAPIC = {
492 .intrdis = ioapic_abi_intrdis,
493 .intren = ioapic_abi_intren,
494 .intr_setup = ioapic_abi_intr_setup,
495 .intr_teardown = ioapic_abi_intr_teardown,
496 .finalize = ioapic_finalize,
497 .cleanup = ioapic_cleanup,
498 .setdefault = ioapic_setdefault,
499 .stabilize = ioapic_stabilize,
500 .initmap = ioapic_initmap,
501 .intr_config = ioapic_intr_config
504 static int ioapic_abi_extint_irq = -1;
506 struct ioapic_irqinfo ioapic_irqs[IOAPIC_HWI_VECTORS];
509 ioapic_abi_intren(int irq)
511 if (irq < 0 || irq >= IOAPIC_HWI_VECTORS) {
512 kprintf("ioapic_abi_intren invalid irq %d\n", irq);
519 ioapic_abi_intrdis(int irq)
521 if (irq < 0 || irq >= IOAPIC_HWI_VECTORS) {
522 kprintf("ioapic_abi_intrdis invalid irq %d\n", irq);
529 ioapic_finalize(void)
531 KKASSERT(MachIntrABI.type == MACHINTR_IOAPIC);
532 KKASSERT(ioapic_enable);
535 * If an IMCR is present, program bit 0 to disconnect the 8259
539 outb(0x22, 0x70); /* select IMCR */
540 outb(0x23, 0x01); /* disconnect 8259 */
545 * This routine is called after physical interrupts are enabled but before
546 * the critical section is released. We need to clean out any interrupts
547 * that had already been posted to the cpu.
552 bzero(mdcpu->gd_ipending, sizeof(mdcpu->gd_ipending));
555 /* Must never be called */
557 ioapic_stabilize(void)
559 panic("ioapic_stabilize is called\n");
563 ioapic_abi_intr_setup(int intr, int flags)
569 KKASSERT(intr >= 0 && intr < IOAPIC_HWI_VECTORS &&
570 intr != IOAPIC_HWI_SYSCALL);
571 KKASSERT(ioapic_irqs[intr].io_addr != NULL);
576 vector = IDT_OFFSET + intr;
577 setidt(vector, ioapic_intr[intr], SDT_SYSIGT, SEL_KPL, 0);
580 * Now reprogram the vector in the IO APIC. In order to avoid
581 * losing an EOI for a level interrupt, which is vector based,
582 * make sure that the IO APIC is programmed for edge-triggering
583 * first, then reprogrammed with the new vector. This should
588 select = ioapic_irqs[intr].io_idx;
589 value = ioapic_read(ioapic_irqs[intr].io_addr, select);
590 value |= IOART_INTMSET;
592 ioapic_write(ioapic_irqs[intr].io_addr, select,
593 (value & ~APIC_TRIGMOD_MASK));
594 ioapic_write(ioapic_irqs[intr].io_addr, select,
595 (value & ~IOART_INTVEC) | vector);
599 machintr_intren(intr);
605 ioapic_abi_intr_teardown(int intr)
611 KKASSERT(intr >= 0 && intr < IOAPIC_HWI_VECTORS &&
612 intr != IOAPIC_HWI_SYSCALL);
613 KKASSERT(ioapic_irqs[intr].io_addr != NULL);
619 * Teardown an interrupt vector. The vector should already be
620 * installed in the cpu's IDT, but make sure.
622 machintr_intrdis(intr);
624 vector = IDT_OFFSET + intr;
625 setidt(vector, ioapic_intr[intr], SDT_SYSIGT, SEL_KPL, 0);
628 * In order to avoid losing an EOI for a level interrupt, which
629 * is vector based, make sure that the IO APIC is programmed for
630 * edge-triggering first, then reprogrammed with the new vector.
631 * This should clear the IRR bit.
635 select = ioapic_irqs[intr].io_idx;
636 value = ioapic_read(ioapic_irqs[intr].io_addr, select);
638 ioapic_write(ioapic_irqs[intr].io_addr, select,
639 (value & ~APIC_TRIGMOD_MASK));
640 ioapic_write(ioapic_irqs[intr].io_addr, select,
641 (value & ~IOART_INTVEC) | vector);
649 ioapic_setdefault(void)
653 for (intr = 0; intr < IOAPIC_HWI_VECTORS; ++intr) {
654 if (intr == IOAPIC_HWI_SYSCALL)
656 setidt(IDT_OFFSET + intr, ioapic_intr[intr], SDT_SYSIGT,
666 for (i = 0; i < IOAPIC_HWI_VECTORS; ++i)
667 ioapic_irqmaps[i].im_gsi = -1;
668 ioapic_irqmaps[IOAPIC_HWI_SYSCALL].im_type = IOAPIC_IMT_SYSCALL;
672 ioapic_abi_set_irqmap(int irq, int gsi, enum intr_trigger trig,
673 enum intr_polarity pola)
675 struct ioapic_irqinfo *info;
676 struct ioapic_irqmap *map;
680 KKASSERT(trig == INTR_TRIGGER_EDGE || trig == INTR_TRIGGER_LEVEL);
681 KKASSERT(pola == INTR_POLARITY_HIGH || pola == INTR_POLARITY_LOW);
683 KKASSERT(irq >= 0 && irq < IOAPIC_HWI_VECTORS);
684 map = &ioapic_irqmaps[irq];
686 KKASSERT(map->im_type == IOAPIC_IMT_UNUSED);
687 map->im_type = IOAPIC_IMT_LINE;
694 kprintf("IOAPIC: irq %d -> gsi %d %s/%s\n",
696 intr_str_trigger(map->im_trig),
697 intr_str_polarity(map->im_pola));
700 pin = ioapic_gsi_pin(map->im_gsi);
701 ioaddr = ioapic_gsi_ioaddr(map->im_gsi);
703 info = &ioapic_irqs[irq];
707 info->io_addr = ioaddr;
708 info->io_idx = IOAPIC_REDTBL + (2 * pin);
709 info->io_flags = IOAPIC_IRQI_FLAG_MASKED;
710 if (map->im_trig == INTR_TRIGGER_LEVEL)
711 info->io_flags |= IOAPIC_IRQI_FLAG_LEVEL;
713 ioapic_pin_setup(ioaddr, pin, IDT_OFFSET + irq,
714 map->im_trig, map->im_pola);
720 ioapic_abi_fixup_irqmap(void)
724 for (i = 0; i < ISA_IRQ_CNT; ++i) {
725 struct ioapic_irqmap *map = &ioapic_irqmaps[i];
727 if (map->im_type == IOAPIC_IMT_UNUSED) {
728 map->im_type = IOAPIC_IMT_RESERVED;
730 kprintf("IOAPIC: irq %d reserved\n", i);
736 ioapic_abi_find_gsi(int gsi, enum intr_trigger trig, enum intr_polarity pola)
740 KKASSERT(trig == INTR_TRIGGER_EDGE || trig == INTR_TRIGGER_LEVEL);
741 KKASSERT(pola == INTR_POLARITY_HIGH || pola == INTR_POLARITY_LOW);
743 for (irq = 0; irq < IOAPIC_HWI_VECTORS; ++irq) {
744 const struct ioapic_irqmap *map = &ioapic_irqmaps[irq];
746 if (map->im_gsi == gsi) {
747 KKASSERT(map->im_type == IOAPIC_IMT_LINE);
749 if (map->im_flags & IOAPIC_IMF_CONF) {
750 if (map->im_trig != trig ||
751 map->im_pola != pola)
761 ioapic_abi_find_irq(int irq, enum intr_trigger trig, enum intr_polarity pola)
763 const struct ioapic_irqmap *map;
765 KKASSERT(trig == INTR_TRIGGER_EDGE || trig == INTR_TRIGGER_LEVEL);
766 KKASSERT(pola == INTR_POLARITY_HIGH || pola == INTR_POLARITY_LOW);
768 if (irq < 0 || irq >= IOAPIC_HWI_VECTORS)
770 map = &ioapic_irqmaps[irq];
772 if (map->im_type != IOAPIC_IMT_LINE)
775 if (map->im_flags & IOAPIC_IMF_CONF) {
776 if (map->im_trig != trig || map->im_pola != pola)
783 ioapic_intr_config(int irq, enum intr_trigger trig, enum intr_polarity pola)
785 struct ioapic_irqinfo *info;
786 struct ioapic_irqmap *map;
790 KKASSERT(trig == INTR_TRIGGER_EDGE || trig == INTR_TRIGGER_LEVEL);
791 KKASSERT(pola == INTR_POLARITY_HIGH || pola == INTR_POLARITY_LOW);
793 KKASSERT(irq >= 0 && irq < IOAPIC_HWI_VECTORS);
794 map = &ioapic_irqmaps[irq];
796 KKASSERT(map->im_type == IOAPIC_IMT_LINE);
799 if (map->im_flags & IOAPIC_IMF_CONF) {
800 if (trig != map->im_trig) {
801 panic("ioapic_intr_config: trig %s -> %s\n",
802 intr_str_trigger(map->im_trig),
803 intr_str_trigger(trig));
805 if (pola != map->im_pola) {
806 panic("ioapic_intr_config: pola %s -> %s\n",
807 intr_str_polarity(map->im_pola),
808 intr_str_polarity(pola));
813 map->im_flags |= IOAPIC_IMF_CONF;
815 if (trig == map->im_trig && pola == map->im_pola)
819 kprintf("IOAPIC: irq %d, gsi %d %s/%s -> %s/%s\n",
821 intr_str_trigger(map->im_trig),
822 intr_str_polarity(map->im_pola),
823 intr_str_trigger(trig),
824 intr_str_polarity(pola));
829 pin = ioapic_gsi_pin(map->im_gsi);
830 ioaddr = ioapic_gsi_ioaddr(map->im_gsi);
832 info = &ioapic_irqs[irq];
836 info->io_flags &= ~IOAPIC_IRQI_FLAG_LEVEL;
837 if (map->im_trig == INTR_TRIGGER_LEVEL)
838 info->io_flags |= IOAPIC_IRQI_FLAG_LEVEL;
840 ioapic_pin_setup(ioaddr, pin, IDT_OFFSET + irq,
841 map->im_trig, map->im_pola);
847 ioapic_abi_extint_irqmap(int irq)
849 struct ioapic_irqinfo *info;
850 struct ioapic_irqmap *map;
854 vec = IDT_OFFSET + irq;
856 if (ioapic_abi_extint_irq == irq)
858 else if (ioapic_abi_extint_irq >= 0)
861 error = icu_ioapic_extint(irq, vec);
865 map = &ioapic_irqmaps[irq];
867 KKASSERT(map->im_type == IOAPIC_IMT_RESERVED ||
868 map->im_type == IOAPIC_IMT_LINE);
869 if (map->im_type == IOAPIC_IMT_LINE) {
870 if (map->im_flags & IOAPIC_IMF_CONF)
873 ioapic_abi_extint_irq = irq;
875 map->im_type = IOAPIC_IMT_LINE;
876 map->im_trig = INTR_TRIGGER_EDGE;
877 map->im_pola = INTR_POLARITY_HIGH;
878 map->im_flags = IOAPIC_IMF_CONF;
880 map->im_gsi = ioapic_extpin_gsi();
881 KKASSERT(map->im_gsi >= 0);
884 kprintf("IOAPIC: irq %d -> extint gsi %d %s/%s\n",
886 intr_str_trigger(map->im_trig),
887 intr_str_polarity(map->im_pola));
890 pin = ioapic_gsi_pin(map->im_gsi);
891 ioaddr = ioapic_gsi_ioaddr(map->im_gsi);
893 info = &ioapic_irqs[irq];
897 info->io_addr = ioaddr;
898 info->io_idx = IOAPIC_REDTBL + (2 * pin);
899 info->io_flags = IOAPIC_IRQI_FLAG_MASKED;
901 ioapic_extpin_setup(ioaddr, pin, vec);