2 * Copyright (c) 2007 The DragonFly Project. All rights reserved.
4 * This code is derived from software contributed to The DragonFly Project
5 * by Sepherosa Ziehau <sepherosa@gmail.com>
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * 3. Neither the name of The DragonFly Project nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific, prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
24 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
25 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
26 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
27 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
28 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
29 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
31 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
34 * $DragonFly: src/sys/dev/netif/bwi/if_bwi.c,v 1.17 2008/01/10 13:01:40 sephe Exp $
37 #include <sys/param.h>
38 #include <sys/bitops.h>
39 #include <sys/endian.h>
40 #include <sys/kernel.h>
42 #include <sys/malloc.h>
45 #include <sys/serialize.h>
46 #include <sys/socket.h>
47 #include <sys/sockio.h>
48 #include <sys/sysctl.h>
50 #include <net/ethernet.h>
53 #include <net/if_arp.h>
54 #include <net/if_dl.h>
55 #include <net/if_media.h>
56 #include <net/ifq_var.h>
58 #include <netproto/802_11/ieee80211_radiotap.h>
59 #include <netproto/802_11/ieee80211_var.h>
61 #include <bus/pci/pcireg.h>
62 #include <bus/pci/pcivar.h>
63 #include <bus/pci/pcidevs.h>
65 #include <dev/netif/bwi/if_bwireg.h>
66 #include <dev/netif/bwi/if_bwivar.h>
67 #include <dev/netif/bwi/bwimac.h>
68 #include <dev/netif/bwi/bwirf.h>
70 struct bwi_clock_freq {
75 struct bwi_myaddr_bssid {
76 uint8_t myaddr[IEEE80211_ADDR_LEN];
77 uint8_t bssid[IEEE80211_ADDR_LEN];
80 static int bwi_probe(device_t);
81 static int bwi_attach(device_t);
82 static int bwi_detach(device_t);
83 static int bwi_shutdown(device_t);
85 static void bwi_init(void *);
86 static int bwi_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
87 static void bwi_start(struct ifnet *);
88 static void bwi_watchdog(struct ifnet *);
89 static int bwi_newstate(struct ieee80211com *, enum ieee80211_state, int);
90 static void bwi_updateslot(struct ifnet *);
91 static int bwi_media_change(struct ifnet *);
93 static void bwi_next_scan(void *);
94 static void bwi_calibrate(void *);
96 static int bwi_stop(struct bwi_softc *);
97 static int bwi_newbuf(struct bwi_softc *, int, int);
98 static int bwi_encap(struct bwi_softc *, int, struct mbuf *,
99 struct ieee80211_node **, int);
101 static void bwi_init_rxdesc_ring32(struct bwi_softc *, uint32_t,
102 bus_addr_t, int, int);
103 static void bwi_reset_rx_ring32(struct bwi_softc *, uint32_t);
105 static int bwi_init_tx_ring32(struct bwi_softc *, int);
106 static int bwi_init_rx_ring32(struct bwi_softc *);
107 static int bwi_init_txstats32(struct bwi_softc *);
108 static void bwi_free_tx_ring32(struct bwi_softc *, int);
109 static void bwi_free_rx_ring32(struct bwi_softc *);
110 static void bwi_free_txstats32(struct bwi_softc *);
111 static void bwi_setup_rx_desc32(struct bwi_softc *, int, bus_addr_t, int);
112 static void bwi_setup_tx_desc32(struct bwi_softc *, struct bwi_ring_data *,
113 int, bus_addr_t, int);
114 static int bwi_rxeof32(struct bwi_softc *);
115 static void bwi_start_tx32(struct bwi_softc *, uint32_t, int);
116 static void bwi_txeof_status32(struct bwi_softc *);
118 static int bwi_init_tx_ring64(struct bwi_softc *, int);
119 static int bwi_init_rx_ring64(struct bwi_softc *);
120 static int bwi_init_txstats64(struct bwi_softc *);
121 static void bwi_free_tx_ring64(struct bwi_softc *, int);
122 static void bwi_free_rx_ring64(struct bwi_softc *);
123 static void bwi_free_txstats64(struct bwi_softc *);
124 static void bwi_setup_rx_desc64(struct bwi_softc *, int, bus_addr_t, int);
125 static void bwi_setup_tx_desc64(struct bwi_softc *, struct bwi_ring_data *,
126 int, bus_addr_t, int);
127 static int bwi_rxeof64(struct bwi_softc *);
128 static void bwi_start_tx64(struct bwi_softc *, uint32_t, int);
129 static void bwi_txeof_status64(struct bwi_softc *);
131 static void bwi_intr(void *);
132 static int bwi_rxeof(struct bwi_softc *, int);
133 static void _bwi_txeof(struct bwi_softc *, uint16_t, int, int);
134 static void bwi_txeof(struct bwi_softc *);
135 static void bwi_txeof_status(struct bwi_softc *, int);
136 static void bwi_enable_intrs(struct bwi_softc *, uint32_t);
137 static void bwi_disable_intrs(struct bwi_softc *, uint32_t);
138 static int bwi_calc_rssi(struct bwi_softc *, const struct bwi_rxbuf_hdr *);
139 static void bwi_rx_radiotap(struct bwi_softc *, struct mbuf *,
140 struct bwi_rxbuf_hdr *, const void *, int, int);
142 static int bwi_dma_alloc(struct bwi_softc *);
143 static void bwi_dma_free(struct bwi_softc *);
144 static int bwi_dma_ring_alloc(struct bwi_softc *, bus_dma_tag_t,
145 struct bwi_ring_data *, bus_size_t,
147 static int bwi_dma_mbuf_create(struct bwi_softc *);
148 static void bwi_dma_mbuf_destroy(struct bwi_softc *, int, int);
149 static int bwi_dma_txstats_alloc(struct bwi_softc *, uint32_t, bus_size_t);
150 static void bwi_dma_txstats_free(struct bwi_softc *);
151 static void bwi_dma_ring_addr(void *, bus_dma_segment_t *, int, int);
152 static void bwi_dma_buf_addr(void *, bus_dma_segment_t *, int,
155 static void bwi_power_on(struct bwi_softc *, int);
156 static int bwi_power_off(struct bwi_softc *, int);
157 static int bwi_set_clock_mode(struct bwi_softc *, enum bwi_clock_mode);
158 static int bwi_set_clock_delay(struct bwi_softc *);
159 static void bwi_get_clock_freq(struct bwi_softc *, struct bwi_clock_freq *);
160 static int bwi_get_pwron_delay(struct bwi_softc *sc);
161 static void bwi_set_addr_filter(struct bwi_softc *, uint16_t,
163 static void bwi_set_bssid(struct bwi_softc *, const uint8_t *);
164 static int bwi_set_chan(struct bwi_softc *, struct ieee80211_channel *);
166 static void bwi_get_card_flags(struct bwi_softc *);
167 static void bwi_get_eaddr(struct bwi_softc *, uint16_t, uint8_t *);
169 static int bwi_bus_attach(struct bwi_softc *);
170 static int bwi_bbp_attach(struct bwi_softc *);
171 static int bwi_bbp_power_on(struct bwi_softc *, enum bwi_clock_mode);
172 static void bwi_bbp_power_off(struct bwi_softc *);
174 static const char *bwi_regwin_name(const struct bwi_regwin *);
175 static uint32_t bwi_regwin_disable_bits(struct bwi_softc *);
176 static void bwi_regwin_info(struct bwi_softc *, uint16_t *, uint8_t *);
177 static int bwi_regwin_select(struct bwi_softc *, int);
179 static void bwi_led_attach(struct bwi_softc *);
180 static void bwi_led_newstate(struct bwi_softc *, enum ieee80211_state);
181 static void bwi_led_event(struct bwi_softc *, int);
182 static void bwi_led_blink_start(struct bwi_softc *, int, int);
183 static void bwi_led_blink_next(void *);
184 static void bwi_led_blink_end(void *);
186 static const struct bwi_dev {
191 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM4301,
192 "Broadcom BCM4301 802.11 Wireless Lan" },
194 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM4307,
195 "Broadcom BCM4307 802.11 Wireless Lan" },
197 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM4311,
198 "Broadcom BCM4311 802.11 Wireless Lan" },
200 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM4312,
201 "Broadcom BCM4312 802.11 Wireless Lan" },
203 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM4306_1,
204 "Broadcom BCM4306 802.11 Wireless Lan" },
206 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM4306_2,
207 "Broadcom BCM4306 802.11 Wireless Lan" },
209 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM4306_3,
210 "Broadcom BCM4306 802.11 Wireless Lan" },
212 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM4309,
213 "Broadcom BCM4309 802.11 Wireless Lan" },
215 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM4318,
216 "Broadcom BCM4318 802.11 Wireless Lan" },
218 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM4319,
219 "Broadcom BCM4319 802.11 Wireless Lan" }
222 static device_method_t bwi_methods[] = {
223 DEVMETHOD(device_probe, bwi_probe),
224 DEVMETHOD(device_attach, bwi_attach),
225 DEVMETHOD(device_detach, bwi_detach),
226 DEVMETHOD(device_shutdown, bwi_shutdown),
228 DEVMETHOD(device_suspend, bwi_suspend),
229 DEVMETHOD(device_resume, bwi_resume),
234 static driver_t bwi_driver = {
237 sizeof(struct bwi_softc)
240 static devclass_t bwi_devclass;
242 DRIVER_MODULE(bwi, pci, bwi_driver, bwi_devclass, 0, 0);
243 DRIVER_MODULE(bwi, cardbus, bwi_driver, bwi_devclass, 0, 0);
245 MODULE_DEPEND(bwi, wlan, 1, 1, 1);
246 MODULE_DEPEND(bwi, wlan_ratectl_onoe, 1, 1, 1);
248 MODULE_DEPEND(bwi, wlan_ratectl_amrr, 1, 1, 1);
250 MODULE_DEPEND(bwi, pci, 1, 1, 1);
251 MODULE_DEPEND(bwi, cardbus, 1, 1, 1);
253 static const struct {
257 } bwi_bbpid_map[] = {
258 { 0x4301, 0x4301, 0x4301 },
259 { 0x4305, 0x4307, 0x4307 },
260 { 0x4403, 0x4403, 0x4402 },
261 { 0x4610, 0x4615, 0x4610 },
262 { 0x4710, 0x4715, 0x4710 },
263 { 0x4720, 0x4725, 0x4309 }
266 static const struct {
269 } bwi_regwin_count[] = {
282 #define CLKSRC(src) \
283 [BWI_CLKSRC_ ## src] = { \
284 .freq_min = BWI_CLKSRC_ ##src## _FMIN, \
285 .freq_max = BWI_CLKSRC_ ##src## _FMAX \
288 static const struct {
291 } bwi_clkfreq[BWI_CLKSRC_MAX] = {
299 #define VENDOR_LED_ACT(vendor) \
301 .vid = PCI_VENDOR_##vendor, \
302 .led_act = { BWI_VENDOR_LED_ACT_##vendor } \
305 static const struct {
307 uint8_t led_act[BWI_LED_MAX];
308 } bwi_vendor_led_act[] = {
309 VENDOR_LED_ACT(COMPAQ),
310 VENDOR_LED_ACT(LINKSYS)
313 static const uint8_t bwi_default_led_act[BWI_LED_MAX] =
314 { BWI_VENDOR_LED_ACT_DEFAULT };
316 #undef VENDOR_LED_ACT
318 static const struct {
321 } bwi_led_duration[109] = {
338 #ifdef BWI_DEBUG_VERBOSE
339 static uint32_t bwi_debug = BWI_DBG_ATTACH | BWI_DBG_INIT | BWI_DBG_TXPOWER;
341 static uint32_t bwi_debug;
343 TUNABLE_INT("hw.bwi.debug", (int *)&bwi_debug);
344 #endif /* BWI_DEBUG */
346 static const uint8_t bwi_zero_addr[IEEE80211_ADDR_LEN];
348 static const struct ieee80211_rateset bwi_rateset_11b =
349 { 4, { 2, 4, 11, 22 } };
350 static const struct ieee80211_rateset bwi_rateset_11g =
351 { 12, { 2, 4, 11, 22, 12, 18, 24, 36, 48, 72, 96, 108 } };
354 bwi_read_sprom(struct bwi_softc *sc, uint16_t ofs)
356 return CSR_READ_2(sc, ofs + BWI_SPROM_START);
360 bwi_setup_desc32(struct bwi_softc *sc, struct bwi_desc32 *desc_array,
361 int ndesc, int desc_idx, bus_addr_t paddr, int buf_len,
364 struct bwi_desc32 *desc = &desc_array[desc_idx];
365 uint32_t ctrl, addr, addr_hi, addr_lo;
367 addr_lo = __SHIFTOUT(paddr, BWI_DESC32_A_ADDR_MASK);
368 addr_hi = __SHIFTOUT(paddr, BWI_DESC32_A_FUNC_MASK);
370 addr = __SHIFTIN(addr_lo, BWI_DESC32_A_ADDR_MASK) |
371 __SHIFTIN(BWI_DESC32_A_FUNC_TXRX, BWI_DESC32_A_FUNC_MASK);
373 ctrl = __SHIFTIN(buf_len, BWI_DESC32_C_BUFLEN_MASK) |
374 __SHIFTIN(addr_hi, BWI_DESC32_C_ADDRHI_MASK);
375 if (desc_idx == ndesc - 1)
376 ctrl |= BWI_DESC32_C_EOR;
379 ctrl |= BWI_DESC32_C_FRAME_START |
380 BWI_DESC32_C_FRAME_END |
384 desc->addr = htole32(addr);
385 desc->ctrl = htole32(ctrl);
388 /* XXX does not belong here */
390 bwi_rate2plcp(uint8_t rate)
392 rate &= IEEE80211_RATE_VAL;
397 case 11: return 0x37;
398 case 22: return 0x6e;
399 case 44: return 0xdc;
408 case 108: return 0xc;
411 panic("unsupported rate %u\n", rate);
415 /* XXX does not belong here */
416 #define IEEE80211_OFDM_PLCP_RATE_MASK __BITS(3, 0)
417 #define IEEE80211_OFDM_PLCP_LEN_MASK __BITS(16, 5)
420 bwi_ofdm_plcp_header(uint32_t *plcp0, int pkt_len, uint8_t rate)
424 plcp = __SHIFTIN(bwi_rate2plcp(rate), IEEE80211_OFDM_PLCP_RATE_MASK) |
425 __SHIFTIN(pkt_len, IEEE80211_OFDM_PLCP_LEN_MASK);
426 *plcp0 = htole32(plcp);
429 /* XXX does not belong here */
430 struct ieee80211_ds_plcp_hdr {
437 #define IEEE80211_DS_PLCP_SERVICE_LOCKED 0x04
438 #define IEEE80211_DS_PLCL_SERVICE_PBCC 0x08
439 #define IEEE80211_DS_PLCP_SERVICE_LENEXT5 0x20
440 #define IEEE80211_DS_PLCP_SERVICE_LENEXT6 0x40
441 #define IEEE80211_DS_PLCP_SERVICE_LENEXT7 0x80
444 bwi_ds_plcp_header(struct ieee80211_ds_plcp_hdr *plcp, int pkt_len,
447 int len, service, pkt_bitlen;
449 pkt_bitlen = pkt_len * NBBY;
450 len = howmany(pkt_bitlen * 2, rate);
452 service = IEEE80211_DS_PLCP_SERVICE_LOCKED;
453 if (rate == (11 * 2)) {
457 * PLCP service field needs to be adjusted,
458 * if TX rate is 11Mbytes/s
460 pkt_bitlen1 = len * 11;
461 if (pkt_bitlen1 - pkt_bitlen >= NBBY)
462 service |= IEEE80211_DS_PLCP_SERVICE_LENEXT7;
465 plcp->i_signal = bwi_rate2plcp(rate);
466 plcp->i_service = service;
467 plcp->i_length = htole16(len);
468 /* NOTE: do NOT touch i_crc */
472 bwi_plcp_header(void *plcp, int pkt_len, uint8_t rate)
474 enum ieee80211_modtype modtype;
477 * Assume caller has zeroed 'plcp'
480 modtype = ieee80211_rate2modtype(rate);
481 if (modtype == IEEE80211_MODTYPE_OFDM)
482 bwi_ofdm_plcp_header(plcp, pkt_len, rate);
483 else if (modtype == IEEE80211_MODTYPE_DS)
484 bwi_ds_plcp_header(plcp, pkt_len, rate);
486 panic("unsupport modulation type %u\n", modtype);
489 static __inline uint8_t
490 bwi_ofdm_plcp2rate(const uint32_t *plcp0)
495 plcp = le32toh(*plcp0);
496 plcp_rate = __SHIFTOUT(plcp, IEEE80211_OFDM_PLCP_RATE_MASK);
497 return ieee80211_plcp2rate(plcp_rate, 1);
500 static __inline uint8_t
501 bwi_ds_plcp2rate(const struct ieee80211_ds_plcp_hdr *hdr)
503 return ieee80211_plcp2rate(hdr->i_signal, 0);
507 bwi_probe(device_t dev)
509 const struct bwi_dev *b;
512 did = pci_get_device(dev);
513 vid = pci_get_vendor(dev);
515 for (b = bwi_devices; b->desc != NULL; ++b) {
516 if (b->did == did && b->vid == vid) {
517 device_set_desc(dev, b->desc);
525 bwi_attach(device_t dev)
527 struct bwi_softc *sc = device_get_softc(dev);
528 struct ieee80211com *ic = &sc->sc_ic;
529 struct ifnet *ifp = &ic->ic_if;
534 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
538 * Initialize sysctl variables
540 sc->sc_fw_version = BWI_FW_VERSION3;
541 sc->sc_dwell_time = 200;
542 sc->sc_led_idle = (2350 * hz) / 1000;
543 sc->sc_led_blink = 1;
544 sc->sc_txpwr_calib = 1;
546 sc->sc_debug = bwi_debug;
549 callout_init(&sc->sc_scan_ch);
550 callout_init(&sc->sc_calib_ch);
553 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
556 /* XXX Save more PCIR */
557 irq = pci_read_config(dev, PCIR_INTLINE, 4);
558 mem = pci_read_config(dev, BWI_PCIR_BAR, 4);
560 device_printf(dev, "chip is in D%d power mode "
561 "-- setting to D0\n", pci_get_powerstate(dev));
563 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
565 pci_write_config(dev, PCIR_INTLINE, irq, 4);
566 pci_write_config(dev, BWI_PCIR_BAR, mem, 4);
568 #endif /* !BURN_BRIDGE */
570 pci_enable_busmaster(dev);
572 /* Get more PCI information */
573 sc->sc_pci_revid = pci_get_revid(dev);
574 sc->sc_pci_subvid = pci_get_subvendor(dev);
575 sc->sc_pci_subdid = pci_get_subdevice(dev);
580 sc->sc_mem_rid = BWI_PCIR_BAR;
581 sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
582 &sc->sc_mem_rid, RF_ACTIVE);
583 if (sc->sc_mem_res == NULL) {
584 device_printf(dev, "can't allocate IO memory\n");
587 sc->sc_mem_bt = rman_get_bustag(sc->sc_mem_res);
588 sc->sc_mem_bh = rman_get_bushandle(sc->sc_mem_res);
594 sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ,
596 RF_SHAREABLE | RF_ACTIVE);
597 if (sc->sc_irq_res == NULL) {
598 device_printf(dev, "can't allocate irq\n");
606 sysctl_ctx_init(&sc->sc_sysctl_ctx);
607 sc->sc_sysctl_tree = SYSCTL_ADD_NODE(&sc->sc_sysctl_ctx,
608 SYSCTL_STATIC_CHILDREN(_hw),
610 device_get_nameunit(dev),
612 if (sc->sc_sysctl_tree == NULL) {
613 device_printf(dev, "can't add sysctl node\n");
618 SYSCTL_ADD_UINT(&sc->sc_sysctl_ctx,
619 SYSCTL_CHILDREN(sc->sc_sysctl_tree), OID_AUTO,
620 "dwell_time", CTLFLAG_RW, &sc->sc_dwell_time, 0,
621 "Channel dwell time during scan (msec)");
622 SYSCTL_ADD_UINT(&sc->sc_sysctl_ctx,
623 SYSCTL_CHILDREN(sc->sc_sysctl_tree), OID_AUTO,
624 "fw_version", CTLFLAG_RD, &sc->sc_fw_version, 0,
626 SYSCTL_ADD_UINT(&sc->sc_sysctl_ctx,
627 SYSCTL_CHILDREN(sc->sc_sysctl_tree), OID_AUTO,
628 "led_idle", CTLFLAG_RW, &sc->sc_led_idle, 0,
629 "# ticks before LED enters idle state");
630 SYSCTL_ADD_INT(&sc->sc_sysctl_ctx,
631 SYSCTL_CHILDREN(sc->sc_sysctl_tree), OID_AUTO,
632 "led_blink", CTLFLAG_RW, &sc->sc_led_blink, 0,
633 "Allow LED to blink");
634 SYSCTL_ADD_INT(&sc->sc_sysctl_ctx,
635 SYSCTL_CHILDREN(sc->sc_sysctl_tree), OID_AUTO,
636 "txpwr_calib", CTLFLAG_RW, &sc->sc_txpwr_calib, 0,
637 "Enable software TX power calibration");
639 SYSCTL_ADD_UINT(&sc->sc_sysctl_ctx,
640 SYSCTL_CHILDREN(sc->sc_sysctl_tree), OID_AUTO,
641 "debug", CTLFLAG_RW, &sc->sc_debug, 0, "Debug flags");
646 error = bwi_bbp_attach(sc);
650 error = bwi_bbp_power_on(sc, BWI_CLOCK_MODE_FAST);
654 if (BWI_REGWIN_EXIST(&sc->sc_com_regwin)) {
655 error = bwi_set_clock_delay(sc);
659 error = bwi_set_clock_mode(sc, BWI_CLOCK_MODE_FAST);
663 error = bwi_get_pwron_delay(sc);
668 error = bwi_bus_attach(sc);
672 bwi_get_card_flags(sc);
676 for (i = 0; i < sc->sc_nmac; ++i) {
677 struct bwi_regwin *old;
679 mac = &sc->sc_mac[i];
680 error = bwi_regwin_switch(sc, &mac->mac_regwin, &old);
684 error = bwi_mac_lateattach(mac);
688 error = bwi_regwin_switch(sc, old, NULL);
694 * XXX First MAC is known to exist
697 mac = &sc->sc_mac[0];
700 bwi_bbp_power_off(sc);
702 error = bwi_dma_alloc(sc);
707 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
708 ifp->if_init = bwi_init;
709 ifp->if_ioctl = bwi_ioctl;
710 ifp->if_start = bwi_start;
711 ifp->if_watchdog = bwi_watchdog;
712 ifq_set_maxlen(&ifp->if_snd, IFQ_MAXLEN);
713 ifq_set_ready(&ifp->if_snd);
716 sc->sc_locale = __SHIFTOUT(bwi_read_sprom(sc, BWI_SPROM_CARD_INFO),
717 BWI_SPROM_CARD_INFO_LOCALE);
718 DPRINTF(sc, BWI_DBG_ATTACH, "locale: %d\n", sc->sc_locale);
721 * Setup ratesets, phytype, channels and get MAC address
723 if (phy->phy_mode == IEEE80211_MODE_11B ||
724 phy->phy_mode == IEEE80211_MODE_11G) {
727 ic->ic_sup_rates[IEEE80211_MODE_11B] = bwi_rateset_11b;
729 if (phy->phy_mode == IEEE80211_MODE_11B) {
730 chan_flags = IEEE80211_CHAN_B;
731 ic->ic_phytype = IEEE80211_T_DS;
733 chan_flags = IEEE80211_CHAN_CCK |
734 IEEE80211_CHAN_OFDM |
737 ic->ic_phytype = IEEE80211_T_OFDM;
738 ic->ic_sup_rates[IEEE80211_MODE_11G] =
742 /* XXX depend on locale */
743 for (i = 1; i <= 14; ++i) {
744 ic->ic_channels[i].ic_freq =
745 ieee80211_ieee2mhz(i, IEEE80211_CHAN_2GHZ);
746 ic->ic_channels[i].ic_flags = chan_flags;
749 bwi_get_eaddr(sc, BWI_SPROM_11BG_EADDR, ic->ic_myaddr);
750 if (IEEE80211_IS_MULTICAST(ic->ic_myaddr)) {
751 bwi_get_eaddr(sc, BWI_SPROM_11A_EADDR, ic->ic_myaddr);
752 if (IEEE80211_IS_MULTICAST(ic->ic_myaddr)) {
753 device_printf(dev, "invalid MAC address: "
754 "%6D\n", ic->ic_myaddr, ":");
757 } else if (phy->phy_mode == IEEE80211_MODE_11A) {
762 panic("unknown phymode %d\n", phy->phy_mode);
765 ic->ic_caps = IEEE80211_C_SHSLOT |
766 IEEE80211_C_SHPREAMBLE |
769 ic->ic_state = IEEE80211_S_INIT;
770 ic->ic_opmode = IEEE80211_M_STA;
772 ic->ic_ratectl.rc_st_ratectl_cap = IEEE80211_RATECTL_CAP_ONOE;
773 ic->ic_ratectl.rc_st_ratectl = IEEE80211_RATECTL_ONOE;
775 ic->ic_updateslot = bwi_updateslot;
777 ieee80211_ifattach(ic);
779 ic->ic_headroom = sizeof(struct bwi_txbuf_hdr);
780 ic->ic_flags_ext |= IEEE80211_FEXT_SWBMISS;
782 sc->sc_newstate = ic->ic_newstate;
783 ic->ic_newstate = bwi_newstate;
785 ieee80211_media_init(ic, bwi_media_change, ieee80211_media_status);
790 bpfattach_dlt(ifp, DLT_IEEE802_11_RADIO,
791 sizeof(struct ieee80211_frame) + sizeof(sc->sc_tx_th),
794 sc->sc_tx_th_len = roundup(sizeof(sc->sc_tx_th), sizeof(uint32_t));
795 sc->sc_tx_th.wt_ihdr.it_len = htole16(sc->sc_tx_th_len);
796 sc->sc_tx_th.wt_ihdr.it_present = htole32(BWI_TX_RADIOTAP_PRESENT);
798 sc->sc_rx_th_len = roundup(sizeof(sc->sc_rx_th), sizeof(uint32_t));
799 sc->sc_rx_th.wr_ihdr.it_len = htole16(sc->sc_rx_th_len);
800 sc->sc_rx_th.wr_ihdr.it_present = htole32(BWI_RX_RADIOTAP_PRESENT);
802 error = bus_setup_intr(dev, sc->sc_irq_res, INTR_MPSAFE, bwi_intr, sc,
803 &sc->sc_irq_handle, ifp->if_serializer);
805 device_printf(dev, "can't setup intr\n");
807 ieee80211_ifdetach(ic);
812 ieee80211_announce(ic);
821 bwi_detach(device_t dev)
823 struct bwi_softc *sc = device_get_softc(dev);
825 if (device_is_attached(dev)) {
826 struct ifnet *ifp = &sc->sc_ic.ic_if;
829 lwkt_serialize_enter(ifp->if_serializer);
831 bus_teardown_intr(dev, sc->sc_irq_res, sc->sc_irq_handle);
832 lwkt_serialize_exit(ifp->if_serializer);
835 ieee80211_ifdetach(&sc->sc_ic);
837 for (i = 0; i < sc->sc_nmac; ++i)
838 bwi_mac_detach(&sc->sc_mac[i]);
841 if (sc->sc_sysctl_tree != NULL)
842 sysctl_ctx_free(&sc->sc_sysctl_ctx);
844 if (sc->sc_irq_res != NULL) {
845 bus_release_resource(dev, SYS_RES_IRQ, sc->sc_irq_rid,
849 if (sc->sc_mem_res != NULL) {
850 bus_release_resource(dev, SYS_RES_MEMORY, sc->sc_mem_rid,
860 bwi_shutdown(device_t dev)
862 struct bwi_softc *sc = device_get_softc(dev);
863 struct ifnet *ifp = &sc->sc_ic.ic_if;
865 lwkt_serialize_enter(ifp->if_serializer);
867 lwkt_serialize_exit(ifp->if_serializer);
872 bwi_power_on(struct bwi_softc *sc, int with_pll)
874 uint32_t gpio_in, gpio_out, gpio_en;
877 gpio_in = pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_IN, 4);
878 if (gpio_in & BWI_PCIM_GPIO_PWR_ON)
881 gpio_out = pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_OUT, 4);
882 gpio_en = pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_ENABLE, 4);
884 gpio_out |= BWI_PCIM_GPIO_PWR_ON;
885 gpio_en |= BWI_PCIM_GPIO_PWR_ON;
887 /* Turn off PLL first */
888 gpio_out |= BWI_PCIM_GPIO_PLL_PWR_OFF;
889 gpio_en |= BWI_PCIM_GPIO_PLL_PWR_OFF;
892 pci_write_config(sc->sc_dev, BWI_PCIR_GPIO_OUT, gpio_out, 4);
893 pci_write_config(sc->sc_dev, BWI_PCIR_GPIO_ENABLE, gpio_en, 4);
898 gpio_out &= ~BWI_PCIM_GPIO_PLL_PWR_OFF;
899 pci_write_config(sc->sc_dev, BWI_PCIR_GPIO_OUT, gpio_out, 4);
904 /* Clear "Signaled Target Abort" */
905 status = pci_read_config(sc->sc_dev, PCIR_STATUS, 2);
906 status &= ~PCIM_STATUS_STABORT;
907 pci_write_config(sc->sc_dev, PCIR_STATUS, status, 2);
911 bwi_power_off(struct bwi_softc *sc, int with_pll)
913 uint32_t gpio_out, gpio_en;
915 pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_IN, 4); /* dummy read */
916 gpio_out = pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_OUT, 4);
917 gpio_en = pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_ENABLE, 4);
919 gpio_out &= ~BWI_PCIM_GPIO_PWR_ON;
920 gpio_en |= BWI_PCIM_GPIO_PWR_ON;
922 gpio_out |= BWI_PCIM_GPIO_PLL_PWR_OFF;
923 gpio_en |= BWI_PCIM_GPIO_PLL_PWR_OFF;
926 pci_write_config(sc->sc_dev, BWI_PCIR_GPIO_OUT, gpio_out, 4);
927 pci_write_config(sc->sc_dev, BWI_PCIR_GPIO_ENABLE, gpio_en, 4);
932 bwi_regwin_switch(struct bwi_softc *sc, struct bwi_regwin *rw,
933 struct bwi_regwin **old_rw)
940 if (!BWI_REGWIN_EXIST(rw))
943 if (sc->sc_cur_regwin != rw) {
944 error = bwi_regwin_select(sc, rw->rw_id);
946 if_printf(&sc->sc_ic.ic_if, "can't select regwin %d\n",
953 *old_rw = sc->sc_cur_regwin;
954 sc->sc_cur_regwin = rw;
959 bwi_regwin_select(struct bwi_softc *sc, int id)
961 uint32_t win = BWI_PCIM_REGWIN(id);
965 for (i = 0; i < RETRY_MAX; ++i) {
966 pci_write_config(sc->sc_dev, BWI_PCIR_SEL_REGWIN, win, 4);
967 if (pci_read_config(sc->sc_dev, BWI_PCIR_SEL_REGWIN, 4) == win)
977 bwi_regwin_info(struct bwi_softc *sc, uint16_t *type, uint8_t *rev)
981 val = CSR_READ_4(sc, BWI_ID_HI);
982 *type = BWI_ID_HI_REGWIN_TYPE(val);
983 *rev = BWI_ID_HI_REGWIN_REV(val);
985 DPRINTF(sc, BWI_DBG_ATTACH, "regwin: type 0x%03x, rev %d, "
986 "vendor 0x%04x\n", *type, *rev,
987 __SHIFTOUT(val, BWI_ID_HI_REGWIN_VENDOR_MASK));
991 bwi_bbp_attach(struct bwi_softc *sc)
993 #define N(arr) (int)(sizeof(arr) / sizeof(arr[0]))
994 uint16_t bbp_id, rw_type;
997 int error, nregwin, i;
1000 * Get 0th regwin information
1001 * NOTE: 0th regwin should exist
1003 error = bwi_regwin_select(sc, 0);
1005 device_printf(sc->sc_dev, "can't select regwin 0\n");
1008 bwi_regwin_info(sc, &rw_type, &rw_rev);
1015 if (rw_type == BWI_REGWIN_T_COM) {
1016 info = CSR_READ_4(sc, BWI_INFO);
1017 bbp_id = __SHIFTOUT(info, BWI_INFO_BBPID_MASK);
1019 BWI_CREATE_REGWIN(&sc->sc_com_regwin, 0, rw_type, rw_rev);
1021 sc->sc_cap = CSR_READ_4(sc, BWI_CAPABILITY);
1023 uint16_t did = pci_get_device(sc->sc_dev);
1024 uint8_t revid = pci_get_revid(sc->sc_dev);
1026 for (i = 0; i < N(bwi_bbpid_map); ++i) {
1027 if (did >= bwi_bbpid_map[i].did_min &&
1028 did <= bwi_bbpid_map[i].did_max) {
1029 bbp_id = bwi_bbpid_map[i].bbp_id;
1034 device_printf(sc->sc_dev, "no BBP id for device id "
1039 info = __SHIFTIN(revid, BWI_INFO_BBPREV_MASK) |
1040 __SHIFTIN(0, BWI_INFO_BBPPKG_MASK);
1044 * Find out number of regwins
1047 if (rw_type == BWI_REGWIN_T_COM && rw_rev >= 4) {
1048 nregwin = __SHIFTOUT(info, BWI_INFO_NREGWIN_MASK);
1050 for (i = 0; i < N(bwi_regwin_count); ++i) {
1051 if (bwi_regwin_count[i].bbp_id == bbp_id) {
1052 nregwin = bwi_regwin_count[i].nregwin;
1057 device_printf(sc->sc_dev, "no number of win for "
1058 "BBP id 0x%04x\n", bbp_id);
1063 /* Record BBP id/rev for later using */
1064 sc->sc_bbp_id = bbp_id;
1065 sc->sc_bbp_rev = __SHIFTOUT(info, BWI_INFO_BBPREV_MASK);
1066 sc->sc_bbp_pkg = __SHIFTOUT(info, BWI_INFO_BBPPKG_MASK);
1067 device_printf(sc->sc_dev, "BBP: id 0x%04x, rev 0x%x, pkg %d\n",
1068 sc->sc_bbp_id, sc->sc_bbp_rev, sc->sc_bbp_pkg);
1070 DPRINTF(sc, BWI_DBG_ATTACH, "nregwin %d, cap 0x%08x\n",
1071 nregwin, sc->sc_cap);
1074 * Create rest of the regwins
1077 /* Don't re-create common regwin, if it is already created */
1078 i = BWI_REGWIN_EXIST(&sc->sc_com_regwin) ? 1 : 0;
1080 for (; i < nregwin; ++i) {
1082 * Get regwin information
1084 error = bwi_regwin_select(sc, i);
1086 device_printf(sc->sc_dev,
1087 "can't select regwin %d\n", i);
1090 bwi_regwin_info(sc, &rw_type, &rw_rev);
1094 * 1) Bus (PCI/PCIE) regwin
1096 * Ignore rest types of regwin
1098 if (rw_type == BWI_REGWIN_T_BUSPCI ||
1099 rw_type == BWI_REGWIN_T_BUSPCIE) {
1100 if (BWI_REGWIN_EXIST(&sc->sc_bus_regwin)) {
1101 device_printf(sc->sc_dev,
1102 "bus regwin already exists\n");
1104 BWI_CREATE_REGWIN(&sc->sc_bus_regwin, i,
1107 } else if (rw_type == BWI_REGWIN_T_MAC) {
1108 /* XXX ignore return value */
1109 bwi_mac_attach(sc, i, rw_rev);
1113 /* At least one MAC shold exist */
1114 if (!BWI_REGWIN_EXIST(&sc->sc_mac[0].mac_regwin)) {
1115 device_printf(sc->sc_dev, "no MAC was found\n");
1118 KKASSERT(sc->sc_nmac > 0);
1120 /* Bus regwin must exist */
1121 if (!BWI_REGWIN_EXIST(&sc->sc_bus_regwin)) {
1122 device_printf(sc->sc_dev, "no bus regwin was found\n");
1126 /* Start with first MAC */
1127 error = bwi_regwin_switch(sc, &sc->sc_mac[0].mac_regwin, NULL);
1136 bwi_bus_init(struct bwi_softc *sc, struct bwi_mac *mac)
1138 struct bwi_regwin *old, *bus;
1142 bus = &sc->sc_bus_regwin;
1143 KKASSERT(sc->sc_cur_regwin == &mac->mac_regwin);
1146 * Tell bus to generate requested interrupts
1148 if (bus->rw_rev < 6 && bus->rw_type == BWI_REGWIN_T_BUSPCI) {
1150 * NOTE: Read BWI_FLAGS from MAC regwin
1152 val = CSR_READ_4(sc, BWI_FLAGS);
1154 error = bwi_regwin_switch(sc, bus, &old);
1158 CSR_SETBITS_4(sc, BWI_INTRVEC, (val & BWI_FLAGS_INTR_MASK));
1162 mac_mask = 1 << mac->mac_id;
1164 error = bwi_regwin_switch(sc, bus, &old);
1168 val = pci_read_config(sc->sc_dev, BWI_PCIR_INTCTL, 4);
1169 val |= mac_mask << 8;
1170 pci_write_config(sc->sc_dev, BWI_PCIR_INTCTL, val, 4);
1173 if (sc->sc_flags & BWI_F_BUS_INITED)
1176 if (bus->rw_type == BWI_REGWIN_T_BUSPCI) {
1178 * Enable prefetch and burst
1180 CSR_SETBITS_4(sc, BWI_BUS_CONFIG,
1181 BWI_BUS_CONFIG_PREFETCH | BWI_BUS_CONFIG_BURST);
1183 if (bus->rw_rev < 5) {
1184 struct bwi_regwin *com = &sc->sc_com_regwin;
1187 * Configure timeouts for bus operation
1191 * Set service timeout and request timeout
1193 CSR_SETBITS_4(sc, BWI_CONF_LO,
1194 __SHIFTIN(BWI_CONF_LO_SERVTO, BWI_CONF_LO_SERVTO_MASK) |
1195 __SHIFTIN(BWI_CONF_LO_REQTO, BWI_CONF_LO_REQTO_MASK));
1198 * If there is common regwin, we switch to that regwin
1199 * and switch back to bus regwin once we have done.
1201 if (BWI_REGWIN_EXIST(com)) {
1202 error = bwi_regwin_switch(sc, com, NULL);
1207 /* Let bus know what we have changed */
1208 CSR_WRITE_4(sc, BWI_BUS_ADDR, BWI_BUS_ADDR_MAGIC);
1209 CSR_READ_4(sc, BWI_BUS_ADDR); /* Flush */
1210 CSR_WRITE_4(sc, BWI_BUS_DATA, 0);
1211 CSR_READ_4(sc, BWI_BUS_DATA); /* Flush */
1213 if (BWI_REGWIN_EXIST(com)) {
1214 error = bwi_regwin_switch(sc, bus, NULL);
1218 } else if (bus->rw_rev >= 11) {
1220 * Enable memory read multiple
1222 CSR_SETBITS_4(sc, BWI_BUS_CONFIG, BWI_BUS_CONFIG_MRM);
1228 sc->sc_flags |= BWI_F_BUS_INITED;
1230 return bwi_regwin_switch(sc, old, NULL);
1234 bwi_get_card_flags(struct bwi_softc *sc)
1236 sc->sc_card_flags = bwi_read_sprom(sc, BWI_SPROM_CARD_FLAGS);
1237 if (sc->sc_card_flags == 0xffff)
1238 sc->sc_card_flags = 0;
1240 if (sc->sc_pci_subvid == PCI_VENDOR_APPLE &&
1241 sc->sc_pci_subdid == 0x4e && /* XXX */
1242 sc->sc_pci_revid > 0x40)
1243 sc->sc_card_flags |= BWI_CARD_F_PA_GPIO9;
1245 DPRINTF(sc, BWI_DBG_ATTACH, "card flags 0x%04x\n", sc->sc_card_flags);
1249 bwi_get_eaddr(struct bwi_softc *sc, uint16_t eaddr_ofs, uint8_t *eaddr)
1253 for (i = 0; i < 3; ++i) {
1254 *((uint16_t *)eaddr + i) =
1255 htobe16(bwi_read_sprom(sc, eaddr_ofs + 2 * i));
1260 bwi_get_clock_freq(struct bwi_softc *sc, struct bwi_clock_freq *freq)
1262 struct bwi_regwin *com;
1267 bzero(freq, sizeof(*freq));
1268 com = &sc->sc_com_regwin;
1270 KKASSERT(BWI_REGWIN_EXIST(com));
1271 KKASSERT(sc->sc_cur_regwin == com);
1272 KKASSERT(sc->sc_cap & BWI_CAP_CLKMODE);
1275 * Calculate clock frequency
1279 if (com->rw_rev < 6) {
1280 val = pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_OUT, 4);
1281 if (val & BWI_PCIM_GPIO_OUT_CLKSRC) {
1282 src = BWI_CLKSRC_PCI;
1285 src = BWI_CLKSRC_CS_OSC;
1288 } else if (com->rw_rev < 10) {
1289 val = CSR_READ_4(sc, BWI_CLOCK_CTRL);
1291 src = __SHIFTOUT(val, BWI_CLOCK_CTRL_CLKSRC);
1292 if (src == BWI_CLKSRC_LP_OSC) {
1295 div = (__SHIFTOUT(val, BWI_CLOCK_CTRL_FDIV) + 1) << 2;
1297 /* Unknown source */
1298 if (src >= BWI_CLKSRC_MAX)
1299 src = BWI_CLKSRC_CS_OSC;
1302 val = CSR_READ_4(sc, BWI_CLOCK_INFO);
1304 src = BWI_CLKSRC_CS_OSC;
1305 div = (__SHIFTOUT(val, BWI_CLOCK_INFO_FDIV) + 1) << 2;
1308 KKASSERT(src >= 0 && src < BWI_CLKSRC_MAX);
1311 DPRINTF(sc, BWI_DBG_ATTACH, "clksrc %s\n",
1312 src == BWI_CLKSRC_PCI ? "PCI" :
1313 (src == BWI_CLKSRC_LP_OSC ? "LP_OSC" : "CS_OSC"));
1315 freq->clkfreq_min = bwi_clkfreq[src].freq_min / div;
1316 freq->clkfreq_max = bwi_clkfreq[src].freq_max / div;
1318 DPRINTF(sc, BWI_DBG_ATTACH, "clkfreq min %u, max %u\n",
1319 freq->clkfreq_min, freq->clkfreq_max);
1323 bwi_set_clock_mode(struct bwi_softc *sc, enum bwi_clock_mode clk_mode)
1325 struct bwi_regwin *old, *com;
1326 uint32_t clk_ctrl, clk_src;
1327 int error, pwr_off = 0;
1329 com = &sc->sc_com_regwin;
1330 if (!BWI_REGWIN_EXIST(com))
1333 if (com->rw_rev >= 10 || com->rw_rev < 6)
1337 * For common regwin whose rev is [6, 10), the chip
1338 * must be capable to change clock mode.
1340 if ((sc->sc_cap & BWI_CAP_CLKMODE) == 0)
1343 error = bwi_regwin_switch(sc, com, &old);
1347 if (clk_mode == BWI_CLOCK_MODE_FAST)
1348 bwi_power_on(sc, 0); /* Don't turn on PLL */
1350 clk_ctrl = CSR_READ_4(sc, BWI_CLOCK_CTRL);
1351 clk_src = __SHIFTOUT(clk_ctrl, BWI_CLOCK_CTRL_CLKSRC);
1354 case BWI_CLOCK_MODE_FAST:
1355 clk_ctrl &= ~BWI_CLOCK_CTRL_SLOW;
1356 clk_ctrl |= BWI_CLOCK_CTRL_IGNPLL;
1358 case BWI_CLOCK_MODE_SLOW:
1359 clk_ctrl |= BWI_CLOCK_CTRL_SLOW;
1361 case BWI_CLOCK_MODE_DYN:
1362 clk_ctrl &= ~(BWI_CLOCK_CTRL_SLOW |
1363 BWI_CLOCK_CTRL_IGNPLL |
1364 BWI_CLOCK_CTRL_NODYN);
1365 if (clk_src != BWI_CLKSRC_CS_OSC) {
1366 clk_ctrl |= BWI_CLOCK_CTRL_NODYN;
1371 CSR_WRITE_4(sc, BWI_CLOCK_CTRL, clk_ctrl);
1374 bwi_power_off(sc, 0); /* Leave PLL as it is */
1376 return bwi_regwin_switch(sc, old, NULL);
1380 bwi_set_clock_delay(struct bwi_softc *sc)
1382 struct bwi_regwin *old, *com;
1385 com = &sc->sc_com_regwin;
1386 if (!BWI_REGWIN_EXIST(com))
1389 error = bwi_regwin_switch(sc, com, &old);
1393 if (sc->sc_bbp_id == BWI_BBPID_BCM4321) {
1394 if (sc->sc_bbp_rev == 0)
1395 CSR_WRITE_4(sc, BWI_CONTROL, BWI_CONTROL_MAGIC0);
1396 else if (sc->sc_bbp_rev == 1)
1397 CSR_WRITE_4(sc, BWI_CONTROL, BWI_CONTROL_MAGIC1);
1400 if (sc->sc_cap & BWI_CAP_CLKMODE) {
1401 if (com->rw_rev >= 10) {
1402 CSR_FILT_SETBITS_4(sc, BWI_CLOCK_INFO, 0xffff, 0x40000);
1404 struct bwi_clock_freq freq;
1406 bwi_get_clock_freq(sc, &freq);
1407 CSR_WRITE_4(sc, BWI_PLL_ON_DELAY,
1408 howmany(freq.clkfreq_max * 150, 1000000));
1409 CSR_WRITE_4(sc, BWI_FREQ_SEL_DELAY,
1410 howmany(freq.clkfreq_max * 15, 1000000));
1414 return bwi_regwin_switch(sc, old, NULL);
1420 struct bwi_softc *sc = xsc;
1421 struct ieee80211com *ic = &sc->sc_ic;
1422 struct ifnet *ifp = &ic->ic_if;
1423 struct bwi_mac *mac;
1426 ASSERT_SERIALIZED(ifp->if_serializer);
1428 error = bwi_stop(sc);
1430 if_printf(ifp, "can't stop\n");
1434 bwi_bbp_power_on(sc, BWI_CLOCK_MODE_FAST);
1438 mac = &sc->sc_mac[0];
1439 error = bwi_regwin_switch(sc, &mac->mac_regwin, NULL);
1443 error = bwi_mac_init(mac);
1447 bwi_bbp_power_on(sc, BWI_CLOCK_MODE_DYN);
1449 bcopy(IF_LLADDR(ifp), ic->ic_myaddr, sizeof(ic->ic_myaddr));
1451 bwi_set_bssid(sc, bwi_zero_addr); /* Clear BSSID */
1452 bwi_set_addr_filter(sc, BWI_ADDR_FILTER_MYADDR, ic->ic_myaddr);
1454 bwi_mac_reset_hwkeys(mac);
1456 if ((mac->mac_flags & BWI_MAC_F_HAS_TXSTATS) == 0) {
1461 * Drain any possible pending TX status
1463 for (i = 0; i < NRETRY; ++i) {
1464 if ((CSR_READ_4(sc, BWI_TXSTATUS0) &
1465 BWI_TXSTATUS0_VALID) == 0)
1467 CSR_READ_4(sc, BWI_TXSTATUS1);
1470 if_printf(ifp, "can't drain TX status\n");
1474 if (mac->mac_phy.phy_mode == IEEE80211_MODE_11G)
1475 bwi_mac_updateslot(mac, 1);
1478 error = bwi_mac_start(mac);
1483 bwi_enable_intrs(sc, BWI_INIT_INTRS);
1485 ifp->if_flags |= IFF_RUNNING;
1486 ifp->if_flags &= ~IFF_OACTIVE;
1488 if (ic->ic_opmode != IEEE80211_M_MONITOR) {
1489 if (ic->ic_roaming != IEEE80211_ROAMING_MANUAL)
1490 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1);
1492 ieee80211_new_state(ic, IEEE80211_S_RUN, -1);
1500 bwi_ioctl(struct ifnet *ifp, u_long cmd, caddr_t req, struct ucred *cr)
1502 struct bwi_softc *sc = ifp->if_softc;
1505 ASSERT_SERIALIZED(ifp->if_serializer);
1509 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) ==
1510 (IFF_UP | IFF_RUNNING)) {
1511 struct bwi_mac *mac;
1514 KKASSERT(sc->sc_cur_regwin->rw_type ==
1516 mac = (struct bwi_mac *)sc->sc_cur_regwin;
1518 if ((ifp->if_flags & IFF_PROMISC) &&
1519 (sc->sc_flags & BWI_F_PROMISC) == 0) {
1521 sc->sc_flags |= BWI_F_PROMISC;
1522 } else if ((ifp->if_flags & IFF_PROMISC) == 0 &&
1523 (sc->sc_flags & BWI_F_PROMISC)) {
1525 sc->sc_flags &= ~BWI_F_PROMISC;
1529 bwi_mac_set_promisc(mac, promisc);
1532 if (ifp->if_flags & IFF_UP) {
1533 if ((ifp->if_flags & IFF_RUNNING) == 0)
1536 if (ifp->if_flags & IFF_RUNNING)
1541 error = ieee80211_ioctl(&sc->sc_ic, cmd, req, cr);
1545 if (error == ENETRESET) {
1546 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) ==
1547 (IFF_UP | IFF_RUNNING))
1555 bwi_start(struct ifnet *ifp)
1557 struct bwi_softc *sc = ifp->if_softc;
1558 struct ieee80211com *ic = &sc->sc_ic;
1559 struct bwi_txbuf_data *tbd = &sc->sc_tx_bdata[BWI_TX_DATA_RING];
1562 ASSERT_SERIALIZED(ifp->if_serializer);
1564 if ((ifp->if_flags & IFF_OACTIVE) ||
1565 (ifp->if_flags & IFF_RUNNING) == 0)
1571 while (tbd->tbd_buf[idx].tb_mbuf == NULL) {
1572 struct ieee80211_frame *wh;
1573 struct ieee80211_node *ni;
1577 if (!IF_QEMPTY(&ic->ic_mgtq)) {
1578 IF_DEQUEUE(&ic->ic_mgtq, m);
1580 ni = (struct ieee80211_node *)m->m_pkthdr.rcvif;
1581 m->m_pkthdr.rcvif = NULL;
1584 } else if (!ifq_is_empty(&ifp->if_snd)) {
1585 struct ether_header *eh;
1587 if (ic->ic_state != IEEE80211_S_RUN)
1590 m = ifq_dequeue(&ifp->if_snd, NULL);
1594 if (m->m_len < sizeof(*eh)) {
1595 m = m_pullup(m, sizeof(*eh));
1601 eh = mtod(m, struct ether_header *);
1603 ni = ieee80211_find_txnode(ic, eh->ether_dhost);
1614 m = ieee80211_encap(ic, m, ni);
1616 ieee80211_free_node(ni);
1624 if (ic->ic_rawbpf != NULL)
1625 bpf_mtap(ic->ic_rawbpf, m);
1627 wh = mtod(m, struct ieee80211_frame *);
1628 if (wh->i_fc[1] & IEEE80211_FC1_WEP) {
1629 if (ieee80211_crypto_encap(ic, ni, m) == NULL) {
1630 ieee80211_free_node(ni);
1636 wh = NULL; /* Catch any invalid use */
1638 if (bwi_encap(sc, idx, m, &ni, mgt_pkt) != 0) {
1639 /* 'm' is freed in bwi_encap() if we reach here */
1641 ieee80211_free_node(ni);
1648 idx = (idx + 1) % BWI_TX_NDESC;
1650 if (tbd->tbd_used + BWI_TX_NSPRDESC >= BWI_TX_NDESC) {
1651 ifp->if_flags |= IFF_OACTIVE;
1658 sc->sc_tx_timer = 5;
1663 bwi_watchdog(struct ifnet *ifp)
1665 struct bwi_softc *sc = ifp->if_softc;
1667 ASSERT_SERIALIZED(ifp->if_serializer);
1671 if ((ifp->if_flags & IFF_RUNNING) == 0)
1674 if (sc->sc_tx_timer) {
1675 if (--sc->sc_tx_timer == 0) {
1676 if_printf(ifp, "watchdog timeout\n");
1683 ieee80211_watchdog(&sc->sc_ic);
1687 bwi_stop(struct bwi_softc *sc)
1689 struct ieee80211com *ic = &sc->sc_ic;
1690 struct ifnet *ifp = &ic->ic_if;
1691 struct bwi_mac *mac;
1692 int i, error, pwr_off = 0;
1694 ASSERT_SERIALIZED(ifp->if_serializer);
1696 ieee80211_new_state(ic, IEEE80211_S_INIT, -1);
1698 if (ifp->if_flags & IFF_RUNNING) {
1699 KKASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC);
1700 mac = (struct bwi_mac *)sc->sc_cur_regwin;
1702 bwi_disable_intrs(sc, BWI_ALL_INTRS);
1703 CSR_READ_4(sc, BWI_MAC_INTR_MASK);
1707 for (i = 0; i < sc->sc_nmac; ++i) {
1708 struct bwi_regwin *old_rw;
1710 mac = &sc->sc_mac[i];
1711 if ((mac->mac_flags & BWI_MAC_F_INITED) == 0)
1714 error = bwi_regwin_switch(sc, &mac->mac_regwin, &old_rw);
1718 bwi_mac_shutdown(mac);
1721 bwi_regwin_switch(sc, old_rw, NULL);
1725 bwi_bbp_power_off(sc);
1727 sc->sc_tx_timer = 0;
1729 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1736 struct bwi_softc *sc = xsc;
1737 struct ifnet *ifp = &sc->sc_ic.ic_if;
1738 uint32_t intr_status;
1739 uint32_t txrx_intr_status[BWI_TXRX_NRING];
1740 int i, txrx_error, tx = 0, rx_data = -1;
1742 ASSERT_SERIALIZED(ifp->if_serializer);
1744 if ((ifp->if_flags & IFF_RUNNING) == 0)
1748 * Get interrupt status
1750 intr_status = CSR_READ_4(sc, BWI_MAC_INTR_STATUS);
1751 if (intr_status == 0xffffffff) /* Not for us */
1754 DPRINTF(sc, BWI_DBG_INTR, "intr status 0x%08x\n", intr_status);
1756 intr_status &= CSR_READ_4(sc, BWI_MAC_INTR_MASK);
1757 if (intr_status == 0) /* Nothing is interesting */
1761 DPRINTF(sc, BWI_DBG_INTR, "%s\n", "TX/RX intr");
1762 for (i = 0; i < BWI_TXRX_NRING; ++i) {
1765 if (BWI_TXRX_IS_RX(i))
1766 mask = BWI_TXRX_RX_INTRS;
1768 mask = BWI_TXRX_TX_INTRS;
1770 txrx_intr_status[i] =
1771 CSR_READ_4(sc, BWI_TXRX_INTR_STATUS(i)) & mask;
1773 _DPRINTF(sc, BWI_DBG_INTR, ", %d 0x%08x",
1774 i, txrx_intr_status[i]);
1776 if (txrx_intr_status[i] & BWI_TXRX_INTR_ERROR) {
1777 if_printf(ifp, "intr fatal TX/RX (%d) error 0x%08x\n",
1778 i, txrx_intr_status[i]);
1782 _DPRINTF(sc, BWI_DBG_INTR, "%s\n", "");
1785 * Acknowledge interrupt
1787 CSR_WRITE_4(sc, BWI_MAC_INTR_STATUS, intr_status);
1789 for (i = 0; i < BWI_TXRX_NRING; ++i)
1790 CSR_WRITE_4(sc, BWI_TXRX_INTR_STATUS(i), txrx_intr_status[i]);
1792 /* Disable all interrupts */
1793 bwi_disable_intrs(sc, BWI_ALL_INTRS);
1795 if (intr_status & BWI_INTR_PHY_TXERR)
1796 if_printf(ifp, "intr PHY TX error\n");
1799 /* TODO: reset device */
1802 if (intr_status & BWI_INTR_TBTT) {
1803 KKASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC);
1804 bwi_mac_config_ps((struct bwi_mac *)sc->sc_cur_regwin);
1807 if (intr_status & BWI_INTR_EO_ATIM)
1808 if_printf(ifp, "EO_ATIM\n");
1810 if (intr_status & BWI_INTR_PMQ) {
1812 if ((CSR_READ_4(sc, BWI_MAC_PS_STATUS) & 0x8) == 0)
1815 CSR_WRITE_2(sc, BWI_MAC_PS_STATUS, 0x2);
1818 if (intr_status & BWI_INTR_NOISE)
1819 if_printf(ifp, "intr noise\n");
1821 if (txrx_intr_status[0] & BWI_TXRX_INTR_RX)
1822 rx_data = sc->sc_rxeof(sc);
1824 if (txrx_intr_status[3] & BWI_TXRX_INTR_RX) {
1825 sc->sc_txeof_status(sc);
1829 if (intr_status & BWI_INTR_TX_DONE) {
1834 /* Re-enable interrupts */
1835 bwi_enable_intrs(sc, BWI_INIT_INTRS);
1837 if (sc->sc_blink_led != NULL && sc->sc_led_blink) {
1838 int evt = BWI_LED_EVENT_NONE;
1840 if (tx && rx_data > 0) {
1841 if (sc->sc_rx_rate > sc->sc_tx_rate)
1842 evt = BWI_LED_EVENT_RX;
1844 evt = BWI_LED_EVENT_TX;
1846 evt = BWI_LED_EVENT_TX;
1847 } else if (rx_data > 0) {
1848 evt = BWI_LED_EVENT_RX;
1849 } else if (rx_data == 0) {
1850 evt = BWI_LED_EVENT_POLL;
1853 if (evt != BWI_LED_EVENT_NONE)
1854 bwi_led_event(sc, evt);
1859 bwi_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg)
1861 struct bwi_softc *sc = ic->ic_if.if_softc;
1862 struct ifnet *ifp = &ic->ic_if;
1865 ASSERT_SERIALIZED(ifp->if_serializer);
1867 callout_stop(&sc->sc_scan_ch);
1868 callout_stop(&sc->sc_calib_ch);
1870 ieee80211_ratectl_newstate(ic, nstate);
1871 bwi_led_newstate(sc, nstate);
1873 if (nstate == IEEE80211_S_INIT)
1876 error = bwi_set_chan(sc, ic->ic_curchan);
1878 if_printf(ifp, "can't set channel to %u\n",
1879 ieee80211_chan2ieee(ic, ic->ic_curchan));
1883 if (ic->ic_opmode == IEEE80211_M_MONITOR) {
1885 } else if (nstate == IEEE80211_S_RUN) {
1886 struct bwi_mac *mac;
1888 bwi_set_bssid(sc, ic->ic_bss->ni_bssid);
1890 KKASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC);
1891 mac = (struct bwi_mac *)sc->sc_cur_regwin;
1893 /* Initial TX power calibration */
1894 bwi_mac_calibrate_txpower(mac);
1896 bwi_set_bssid(sc, bwi_zero_addr);
1900 error = sc->sc_newstate(ic, nstate, arg);
1902 if (nstate == IEEE80211_S_SCAN) {
1903 callout_reset(&sc->sc_scan_ch,
1904 (sc->sc_dwell_time * hz) / 1000,
1906 } else if (nstate == IEEE80211_S_RUN) {
1907 /* XXX 15 seconds */
1908 callout_reset(&sc->sc_calib_ch, hz * 15, bwi_calibrate, sc);
1914 bwi_media_change(struct ifnet *ifp)
1918 ASSERT_SERIALIZED(ifp->if_serializer);
1920 error = ieee80211_media_change(ifp);
1921 if (error != ENETRESET)
1924 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == (IFF_UP | IFF_RUNNING))
1925 bwi_init(ifp->if_softc);
1930 bwi_dma_alloc(struct bwi_softc *sc)
1932 int error, i, has_txstats;
1933 bus_addr_t lowaddr = 0;
1934 bus_size_t tx_ring_sz, rx_ring_sz, desc_sz = 0;
1935 uint32_t txrx_ctrl_step = 0;
1938 for (i = 0; i < sc->sc_nmac; ++i) {
1939 if (sc->sc_mac[i].mac_flags & BWI_MAC_F_HAS_TXSTATS) {
1945 switch (sc->sc_bus_space) {
1946 case BWI_BUS_SPACE_30BIT:
1947 case BWI_BUS_SPACE_32BIT:
1948 if (sc->sc_bus_space == BWI_BUS_SPACE_30BIT)
1949 lowaddr = BWI_BUS_SPACE_MAXADDR;
1951 lowaddr = BUS_SPACE_MAXADDR_32BIT;
1952 desc_sz = sizeof(struct bwi_desc32);
1953 txrx_ctrl_step = 0x20;
1955 sc->sc_init_tx_ring = bwi_init_tx_ring32;
1956 sc->sc_free_tx_ring = bwi_free_tx_ring32;
1957 sc->sc_init_rx_ring = bwi_init_rx_ring32;
1958 sc->sc_free_rx_ring = bwi_free_rx_ring32;
1959 sc->sc_setup_rxdesc = bwi_setup_rx_desc32;
1960 sc->sc_setup_txdesc = bwi_setup_tx_desc32;
1961 sc->sc_rxeof = bwi_rxeof32;
1962 sc->sc_start_tx = bwi_start_tx32;
1964 sc->sc_init_txstats = bwi_init_txstats32;
1965 sc->sc_free_txstats = bwi_free_txstats32;
1966 sc->sc_txeof_status = bwi_txeof_status32;
1970 case BWI_BUS_SPACE_64BIT:
1971 lowaddr = BUS_SPACE_MAXADDR; /* XXX */
1972 desc_sz = sizeof(struct bwi_desc64);
1973 txrx_ctrl_step = 0x40;
1975 sc->sc_init_tx_ring = bwi_init_tx_ring64;
1976 sc->sc_free_tx_ring = bwi_free_tx_ring64;
1977 sc->sc_init_rx_ring = bwi_init_rx_ring64;
1978 sc->sc_free_rx_ring = bwi_free_rx_ring64;
1979 sc->sc_setup_rxdesc = bwi_setup_rx_desc64;
1980 sc->sc_setup_txdesc = bwi_setup_tx_desc64;
1981 sc->sc_rxeof = bwi_rxeof64;
1982 sc->sc_start_tx = bwi_start_tx64;
1984 sc->sc_init_txstats = bwi_init_txstats64;
1985 sc->sc_free_txstats = bwi_free_txstats64;
1986 sc->sc_txeof_status = bwi_txeof_status64;
1991 KKASSERT(lowaddr != 0);
1992 KKASSERT(desc_sz != 0);
1993 KKASSERT(txrx_ctrl_step != 0);
1995 tx_ring_sz = roundup(desc_sz * BWI_TX_NDESC, BWI_RING_ALIGN);
1996 rx_ring_sz = roundup(desc_sz * BWI_RX_NDESC, BWI_RING_ALIGN);
1999 * Create top level DMA tag
2001 error = bus_dma_tag_create(NULL, BWI_ALIGN, 0,
2002 lowaddr, BUS_SPACE_MAXADDR,
2005 BUS_SPACE_UNRESTRICTED,
2006 BUS_SPACE_MAXSIZE_32BIT,
2007 0, &sc->sc_parent_dtag);
2009 device_printf(sc->sc_dev, "can't create parent DMA tag\n");
2013 #define TXRX_CTRL(idx) (BWI_TXRX_CTRL_BASE + (idx) * txrx_ctrl_step)
2016 * Create TX ring DMA stuffs
2018 error = bus_dma_tag_create(sc->sc_parent_dtag, BWI_RING_ALIGN, 0,
2019 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
2021 tx_ring_sz, 1, BUS_SPACE_MAXSIZE_32BIT,
2022 0, &sc->sc_txring_dtag);
2024 device_printf(sc->sc_dev, "can't create TX ring DMA tag\n");
2028 for (i = 0; i < BWI_TX_NRING; ++i) {
2029 error = bwi_dma_ring_alloc(sc, sc->sc_txring_dtag,
2030 &sc->sc_tx_rdata[i], tx_ring_sz,
2033 device_printf(sc->sc_dev, "%dth TX ring "
2034 "DMA alloc failed\n", i);
2040 * Create RX ring DMA stuffs
2042 error = bus_dma_tag_create(sc->sc_parent_dtag, BWI_RING_ALIGN, 0,
2043 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
2045 rx_ring_sz, 1, BUS_SPACE_MAXSIZE_32BIT,
2046 0, &sc->sc_rxring_dtag);
2048 device_printf(sc->sc_dev, "can't create RX ring DMA tag\n");
2052 error = bwi_dma_ring_alloc(sc, sc->sc_rxring_dtag, &sc->sc_rx_rdata,
2053 rx_ring_sz, TXRX_CTRL(0));
2055 device_printf(sc->sc_dev, "RX ring DMA alloc failed\n");
2060 error = bwi_dma_txstats_alloc(sc, TXRX_CTRL(3), desc_sz);
2062 device_printf(sc->sc_dev,
2063 "TX stats DMA alloc failed\n");
2070 return bwi_dma_mbuf_create(sc);
2074 bwi_dma_free(struct bwi_softc *sc)
2076 if (sc->sc_txring_dtag != NULL) {
2079 for (i = 0; i < BWI_TX_NRING; ++i) {
2080 struct bwi_ring_data *rd = &sc->sc_tx_rdata[i];
2082 if (rd->rdata_desc != NULL) {
2083 bus_dmamap_unload(sc->sc_txring_dtag,
2085 bus_dmamem_free(sc->sc_txring_dtag,
2090 bus_dma_tag_destroy(sc->sc_txring_dtag);
2093 if (sc->sc_rxring_dtag != NULL) {
2094 struct bwi_ring_data *rd = &sc->sc_rx_rdata;
2096 if (rd->rdata_desc != NULL) {
2097 bus_dmamap_unload(sc->sc_rxring_dtag, rd->rdata_dmap);
2098 bus_dmamem_free(sc->sc_rxring_dtag, rd->rdata_desc,
2101 bus_dma_tag_destroy(sc->sc_rxring_dtag);
2104 bwi_dma_txstats_free(sc);
2105 bwi_dma_mbuf_destroy(sc, BWI_TX_NRING, 1);
2107 if (sc->sc_parent_dtag != NULL)
2108 bus_dma_tag_destroy(sc->sc_parent_dtag);
2112 bwi_dma_ring_alloc(struct bwi_softc *sc, bus_dma_tag_t dtag,
2113 struct bwi_ring_data *rd, bus_size_t size,
2118 error = bus_dmamem_alloc(dtag, &rd->rdata_desc,
2119 BUS_DMA_WAITOK | BUS_DMA_ZERO,
2122 device_printf(sc->sc_dev, "can't allocate DMA mem\n");
2126 error = bus_dmamap_load(dtag, rd->rdata_dmap, rd->rdata_desc, size,
2127 bwi_dma_ring_addr, &rd->rdata_paddr,
2130 device_printf(sc->sc_dev, "can't load DMA mem\n");
2131 bus_dmamem_free(dtag, rd->rdata_desc, rd->rdata_dmap);
2132 rd->rdata_desc = NULL;
2136 rd->rdata_txrx_ctrl = txrx_ctrl;
2141 bwi_dma_txstats_alloc(struct bwi_softc *sc, uint32_t ctrl_base,
2144 struct bwi_txstats_data *st;
2145 bus_size_t dma_size;
2148 st = kmalloc(sizeof(*st), M_DEVBUF, M_WAITOK | M_ZERO);
2149 sc->sc_txstats = st;
2152 * Create TX stats descriptor DMA stuffs
2154 dma_size = roundup(desc_sz * BWI_TXSTATS_NDESC, BWI_RING_ALIGN);
2156 error = bus_dma_tag_create(sc->sc_parent_dtag, BWI_RING_ALIGN, 0,
2157 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
2159 dma_size, 1, BUS_SPACE_MAXSIZE_32BIT,
2160 0, &st->stats_ring_dtag);
2162 device_printf(sc->sc_dev, "can't create txstats ring "
2167 error = bus_dmamem_alloc(st->stats_ring_dtag, &st->stats_ring,
2168 BUS_DMA_WAITOK | BUS_DMA_ZERO,
2169 &st->stats_ring_dmap);
2171 device_printf(sc->sc_dev, "can't allocate txstats ring "
2173 bus_dma_tag_destroy(st->stats_ring_dtag);
2174 st->stats_ring_dtag = NULL;
2178 error = bus_dmamap_load(st->stats_ring_dtag, st->stats_ring_dmap,
2179 st->stats_ring, dma_size,
2180 bwi_dma_ring_addr, &st->stats_ring_paddr,
2183 device_printf(sc->sc_dev, "can't load txstats ring DMA mem\n");
2184 bus_dmamem_free(st->stats_ring_dtag, st->stats_ring,
2185 st->stats_ring_dmap);
2186 bus_dma_tag_destroy(st->stats_ring_dtag);
2187 st->stats_ring_dtag = NULL;
2192 * Create TX stats DMA stuffs
2194 dma_size = roundup(sizeof(struct bwi_txstats) * BWI_TXSTATS_NDESC,
2197 error = bus_dma_tag_create(sc->sc_parent_dtag, BWI_ALIGN, 0,
2198 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
2200 dma_size, 1, BUS_SPACE_MAXSIZE_32BIT,
2201 0, &st->stats_dtag);
2203 device_printf(sc->sc_dev, "can't create txstats DMA tag\n");
2207 error = bus_dmamem_alloc(st->stats_dtag, (void **)&st->stats,
2208 BUS_DMA_WAITOK | BUS_DMA_ZERO,
2211 device_printf(sc->sc_dev, "can't allocate txstats DMA mem\n");
2212 bus_dma_tag_destroy(st->stats_dtag);
2213 st->stats_dtag = NULL;
2217 error = bus_dmamap_load(st->stats_dtag, st->stats_dmap, st->stats,
2218 dma_size, bwi_dma_ring_addr, &st->stats_paddr,
2221 device_printf(sc->sc_dev, "can't load txstats DMA mem\n");
2222 bus_dmamem_free(st->stats_dtag, st->stats, st->stats_dmap);
2223 bus_dma_tag_destroy(st->stats_dtag);
2224 st->stats_dtag = NULL;
2228 st->stats_ctrl_base = ctrl_base;
2233 bwi_dma_txstats_free(struct bwi_softc *sc)
2235 struct bwi_txstats_data *st;
2237 if (sc->sc_txstats == NULL)
2239 st = sc->sc_txstats;
2241 if (st->stats_ring_dtag != NULL) {
2242 bus_dmamap_unload(st->stats_ring_dtag, st->stats_ring_dmap);
2243 bus_dmamem_free(st->stats_ring_dtag, st->stats_ring,
2244 st->stats_ring_dmap);
2245 bus_dma_tag_destroy(st->stats_ring_dtag);
2248 if (st->stats_dtag != NULL) {
2249 bus_dmamap_unload(st->stats_dtag, st->stats_dmap);
2250 bus_dmamem_free(st->stats_dtag, st->stats, st->stats_dmap);
2251 bus_dma_tag_destroy(st->stats_dtag);
2254 kfree(st, M_DEVBUF);
2258 bwi_dma_ring_addr(void *arg, bus_dma_segment_t *seg, int nseg, int error)
2260 KASSERT(nseg == 1, ("too many segments\n"));
2261 *((bus_addr_t *)arg) = seg->ds_addr;
2265 bwi_dma_mbuf_create(struct bwi_softc *sc)
2267 struct bwi_rxbuf_data *rbd = &sc->sc_rx_bdata;
2268 int i, j, k, ntx, error;
2271 * Create TX/RX mbuf DMA tag
2273 error = bus_dma_tag_create(sc->sc_parent_dtag, 1, 0,
2274 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
2275 NULL, NULL, MCLBYTES, 1,
2276 BUS_SPACE_MAXSIZE_32BIT,
2277 0, &sc->sc_buf_dtag);
2279 device_printf(sc->sc_dev, "can't create mbuf DMA tag\n");
2286 * Create TX mbuf DMA map
2288 for (i = 0; i < BWI_TX_NRING; ++i) {
2289 struct bwi_txbuf_data *tbd = &sc->sc_tx_bdata[i];
2291 for (j = 0; j < BWI_TX_NDESC; ++j) {
2292 error = bus_dmamap_create(sc->sc_buf_dtag, 0,
2293 &tbd->tbd_buf[j].tb_dmap);
2295 device_printf(sc->sc_dev, "can't create "
2296 "%dth tbd, %dth DMA map\n", i, j);
2299 for (k = 0; k < j; ++k) {
2300 bus_dmamap_destroy(sc->sc_buf_dtag,
2301 tbd->tbd_buf[k].tb_dmap);
2310 * Create RX mbuf DMA map and a spare DMA map
2312 error = bus_dmamap_create(sc->sc_buf_dtag, 0,
2313 &rbd->rbd_tmp_dmap);
2315 device_printf(sc->sc_dev,
2316 "can't create spare RX buf DMA map\n");
2320 for (j = 0; j < BWI_RX_NDESC; ++j) {
2321 error = bus_dmamap_create(sc->sc_buf_dtag, 0,
2322 &rbd->rbd_buf[j].rb_dmap);
2324 device_printf(sc->sc_dev, "can't create %dth "
2325 "RX buf DMA map\n", j);
2327 for (k = 0; k < j; ++k) {
2328 bus_dmamap_destroy(sc->sc_buf_dtag,
2329 rbd->rbd_buf[j].rb_dmap);
2331 bus_dmamap_destroy(sc->sc_buf_dtag,
2339 bwi_dma_mbuf_destroy(sc, ntx, 0);
2344 bwi_dma_mbuf_destroy(struct bwi_softc *sc, int ntx, int nrx)
2348 if (sc->sc_buf_dtag == NULL)
2351 for (i = 0; i < ntx; ++i) {
2352 struct bwi_txbuf_data *tbd = &sc->sc_tx_bdata[i];
2354 for (j = 0; j < BWI_TX_NDESC; ++j) {
2355 struct bwi_txbuf *tb = &tbd->tbd_buf[j];
2357 if (tb->tb_mbuf != NULL) {
2358 bus_dmamap_unload(sc->sc_buf_dtag,
2360 m_freem(tb->tb_mbuf);
2362 if (tb->tb_ni != NULL)
2363 ieee80211_free_node(tb->tb_ni);
2364 bus_dmamap_destroy(sc->sc_buf_dtag, tb->tb_dmap);
2369 struct bwi_rxbuf_data *rbd = &sc->sc_rx_bdata;
2371 bus_dmamap_destroy(sc->sc_buf_dtag, rbd->rbd_tmp_dmap);
2372 for (j = 0; j < BWI_RX_NDESC; ++j) {
2373 struct bwi_rxbuf *rb = &rbd->rbd_buf[j];
2375 if (rb->rb_mbuf != NULL) {
2376 bus_dmamap_unload(sc->sc_buf_dtag,
2378 m_freem(rb->rb_mbuf);
2380 bus_dmamap_destroy(sc->sc_buf_dtag, rb->rb_dmap);
2384 bus_dma_tag_destroy(sc->sc_buf_dtag);
2385 sc->sc_buf_dtag = NULL;
2389 bwi_enable_intrs(struct bwi_softc *sc, uint32_t enable_intrs)
2391 CSR_SETBITS_4(sc, BWI_MAC_INTR_MASK, enable_intrs);
2395 bwi_disable_intrs(struct bwi_softc *sc, uint32_t disable_intrs)
2397 CSR_CLRBITS_4(sc, BWI_MAC_INTR_MASK, disable_intrs);
2401 bwi_init_tx_ring32(struct bwi_softc *sc, int ring_idx)
2403 struct bwi_ring_data *rd;
2404 struct bwi_txbuf_data *tbd;
2405 uint32_t val, addr_hi, addr_lo;
2407 KKASSERT(ring_idx < BWI_TX_NRING);
2408 rd = &sc->sc_tx_rdata[ring_idx];
2409 tbd = &sc->sc_tx_bdata[ring_idx];
2414 bzero(rd->rdata_desc, sizeof(struct bwi_desc32) * BWI_TX_NDESC);
2415 bus_dmamap_sync(sc->sc_txring_dtag, rd->rdata_dmap,
2416 BUS_DMASYNC_PREWRITE);
2418 addr_lo = __SHIFTOUT(rd->rdata_paddr, BWI_TXRX32_RINGINFO_ADDR_MASK);
2419 addr_hi = __SHIFTOUT(rd->rdata_paddr, BWI_TXRX32_RINGINFO_FUNC_MASK);
2421 val = __SHIFTIN(addr_lo, BWI_TXRX32_RINGINFO_ADDR_MASK) |
2422 __SHIFTIN(BWI_TXRX32_RINGINFO_FUNC_TXRX,
2423 BWI_TXRX32_RINGINFO_FUNC_MASK);
2424 CSR_WRITE_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_RINGINFO, val);
2426 val = __SHIFTIN(addr_hi, BWI_TXRX32_CTRL_ADDRHI_MASK) |
2427 BWI_TXRX32_CTRL_ENABLE;
2428 CSR_WRITE_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_CTRL, val);
2434 bwi_init_rxdesc_ring32(struct bwi_softc *sc, uint32_t ctrl_base,
2435 bus_addr_t paddr, int hdr_size, int ndesc)
2437 uint32_t val, addr_hi, addr_lo;
2439 addr_lo = __SHIFTOUT(paddr, BWI_TXRX32_RINGINFO_ADDR_MASK);
2440 addr_hi = __SHIFTOUT(paddr, BWI_TXRX32_RINGINFO_FUNC_MASK);
2442 val = __SHIFTIN(addr_lo, BWI_TXRX32_RINGINFO_ADDR_MASK) |
2443 __SHIFTIN(BWI_TXRX32_RINGINFO_FUNC_TXRX,
2444 BWI_TXRX32_RINGINFO_FUNC_MASK);
2445 CSR_WRITE_4(sc, ctrl_base + BWI_RX32_RINGINFO, val);
2447 val = __SHIFTIN(hdr_size, BWI_RX32_CTRL_HDRSZ_MASK) |
2448 __SHIFTIN(addr_hi, BWI_TXRX32_CTRL_ADDRHI_MASK) |
2449 BWI_TXRX32_CTRL_ENABLE;
2450 CSR_WRITE_4(sc, ctrl_base + BWI_RX32_CTRL, val);
2452 CSR_WRITE_4(sc, ctrl_base + BWI_RX32_INDEX,
2453 (ndesc - 1) * sizeof(struct bwi_desc32));
2457 bwi_init_rx_ring32(struct bwi_softc *sc)
2459 struct bwi_ring_data *rd = &sc->sc_rx_rdata;
2462 sc->sc_rx_bdata.rbd_idx = 0;
2464 for (i = 0; i < BWI_RX_NDESC; ++i) {
2465 error = bwi_newbuf(sc, i, 1);
2467 if_printf(&sc->sc_ic.ic_if,
2468 "can't allocate %dth RX buffer\n", i);
2472 bus_dmamap_sync(sc->sc_rxring_dtag, rd->rdata_dmap,
2473 BUS_DMASYNC_PREWRITE);
2475 bwi_init_rxdesc_ring32(sc, rd->rdata_txrx_ctrl, rd->rdata_paddr,
2476 sizeof(struct bwi_rxbuf_hdr), BWI_RX_NDESC);
2481 bwi_init_txstats32(struct bwi_softc *sc)
2483 struct bwi_txstats_data *st = sc->sc_txstats;
2484 bus_addr_t stats_paddr;
2487 bzero(st->stats, BWI_TXSTATS_NDESC * sizeof(struct bwi_txstats));
2488 bus_dmamap_sync(st->stats_dtag, st->stats_dmap, BUS_DMASYNC_PREWRITE);
2492 stats_paddr = st->stats_paddr;
2493 for (i = 0; i < BWI_TXSTATS_NDESC; ++i) {
2494 bwi_setup_desc32(sc, st->stats_ring, BWI_TXSTATS_NDESC, i,
2495 stats_paddr, sizeof(struct bwi_txstats), 0);
2496 stats_paddr += sizeof(struct bwi_txstats);
2498 bus_dmamap_sync(st->stats_ring_dtag, st->stats_ring_dmap,
2499 BUS_DMASYNC_PREWRITE);
2501 bwi_init_rxdesc_ring32(sc, st->stats_ctrl_base,
2502 st->stats_ring_paddr, 0, BWI_TXSTATS_NDESC);
2507 bwi_setup_rx_desc32(struct bwi_softc *sc, int buf_idx, bus_addr_t paddr,
2510 struct bwi_ring_data *rd = &sc->sc_rx_rdata;
2512 KKASSERT(buf_idx < BWI_RX_NDESC);
2513 bwi_setup_desc32(sc, rd->rdata_desc, BWI_RX_NDESC, buf_idx,
2518 bwi_setup_tx_desc32(struct bwi_softc *sc, struct bwi_ring_data *rd,
2519 int buf_idx, bus_addr_t paddr, int buf_len)
2521 KKASSERT(buf_idx < BWI_TX_NDESC);
2522 bwi_setup_desc32(sc, rd->rdata_desc, BWI_TX_NDESC, buf_idx,
2527 bwi_init_tx_ring64(struct bwi_softc *sc, int ring_idx)
2534 bwi_init_rx_ring64(struct bwi_softc *sc)
2541 bwi_init_txstats64(struct bwi_softc *sc)
2548 bwi_setup_rx_desc64(struct bwi_softc *sc, int buf_idx, bus_addr_t paddr,
2555 bwi_setup_tx_desc64(struct bwi_softc *sc, struct bwi_ring_data *rd,
2556 int buf_idx, bus_addr_t paddr, int buf_len)
2562 bwi_dma_buf_addr(void *arg, bus_dma_segment_t *seg, int nseg,
2563 bus_size_t mapsz __unused, int error)
2566 KASSERT(nseg == 1, ("too many segments(%d)\n", nseg));
2567 *((bus_addr_t *)arg) = seg->ds_addr;
2572 bwi_newbuf(struct bwi_softc *sc, int buf_idx, int init)
2574 struct bwi_rxbuf_data *rbd = &sc->sc_rx_bdata;
2575 struct bwi_rxbuf *rxbuf = &rbd->rbd_buf[buf_idx];
2576 struct bwi_rxbuf_hdr *hdr;
2582 KKASSERT(buf_idx < BWI_RX_NDESC);
2584 m = m_getcl(init ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR);
2589 * If the NIC is up and running, we need to:
2590 * - Clear RX buffer's header.
2591 * - Restore RX descriptor settings.
2598 m->m_len = m->m_pkthdr.len = MCLBYTES;
2601 * Try to load RX buf into temporary DMA map
2603 error = bus_dmamap_load_mbuf(sc->sc_buf_dtag, rbd->rbd_tmp_dmap, m,
2604 bwi_dma_buf_addr, &paddr,
2605 init ? BUS_DMA_WAITOK : BUS_DMA_NOWAIT);
2610 * See the comment above
2619 bus_dmamap_unload(sc->sc_buf_dtag, rxbuf->rb_dmap);
2621 rxbuf->rb_paddr = paddr;
2624 * Swap RX buf's DMA map with the loaded temporary one
2626 map = rxbuf->rb_dmap;
2627 rxbuf->rb_dmap = rbd->rbd_tmp_dmap;
2628 rbd->rbd_tmp_dmap = map;
2632 * Clear RX buf header
2634 hdr = mtod(rxbuf->rb_mbuf, struct bwi_rxbuf_hdr *);
2635 bzero(hdr, sizeof(*hdr));
2636 bus_dmamap_sync(sc->sc_buf_dtag, rxbuf->rb_dmap, BUS_DMASYNC_PREWRITE);
2639 * Setup RX buf descriptor
2641 sc->sc_setup_rxdesc(sc, buf_idx, rxbuf->rb_paddr,
2642 rxbuf->rb_mbuf->m_len - sizeof(*hdr));
2647 bwi_set_addr_filter(struct bwi_softc *sc, uint16_t addr_ofs,
2648 const uint8_t *addr)
2652 CSR_WRITE_2(sc, BWI_ADDR_FILTER_CTRL,
2653 BWI_ADDR_FILTER_CTRL_SET | addr_ofs);
2655 for (i = 0; i < (IEEE80211_ADDR_LEN / 2); ++i) {
2658 addr_val = (uint16_t)addr[i * 2] |
2659 (((uint16_t)addr[(i * 2) + 1]) << 8);
2660 CSR_WRITE_2(sc, BWI_ADDR_FILTER_DATA, addr_val);
2665 bwi_set_chan(struct bwi_softc *sc, struct ieee80211_channel *c)
2667 struct ieee80211com *ic = &sc->sc_ic;
2668 struct ifnet *ifp = &ic->ic_if;
2669 struct bwi_mac *mac;
2673 ASSERT_SERIALIZED(ifp->if_serializer);
2675 KKASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC);
2676 mac = (struct bwi_mac *)sc->sc_cur_regwin;
2678 chan = ieee80211_chan2ieee(ic, c);
2680 bwi_rf_set_chan(mac, chan, 0);
2683 * Setup radio tap channel freq and flags
2685 if (IEEE80211_IS_CHAN_G(c))
2686 flags = IEEE80211_CHAN_G;
2688 flags = IEEE80211_CHAN_B;
2690 sc->sc_tx_th.wt_chan_freq = sc->sc_rx_th.wr_chan_freq =
2691 htole16(c->ic_freq);
2692 sc->sc_tx_th.wt_chan_flags = sc->sc_rx_th.wr_chan_flags =
2699 bwi_next_scan(void *xsc)
2701 struct bwi_softc *sc = xsc;
2702 struct ieee80211com *ic = &sc->sc_ic;
2703 struct ifnet *ifp = &ic->ic_if;
2705 lwkt_serialize_enter(ifp->if_serializer);
2707 if (ic->ic_state == IEEE80211_S_SCAN)
2708 ieee80211_next_scan(ic);
2710 lwkt_serialize_exit(ifp->if_serializer);
2714 bwi_rxeof(struct bwi_softc *sc, int end_idx)
2716 struct bwi_ring_data *rd = &sc->sc_rx_rdata;
2717 struct bwi_rxbuf_data *rbd = &sc->sc_rx_bdata;
2718 struct ieee80211com *ic = &sc->sc_ic;
2719 struct ifnet *ifp = &ic->ic_if;
2720 int idx, rx_data = 0;
2723 while (idx != end_idx) {
2724 struct bwi_rxbuf *rb = &rbd->rbd_buf[idx];
2725 struct bwi_rxbuf_hdr *hdr;
2726 struct ieee80211_frame_min *wh;
2727 struct ieee80211_node *ni;
2731 int buflen, wh_ofs, hdr_extra, rssi, type, rate;
2734 bus_dmamap_sync(sc->sc_buf_dtag, rb->rb_dmap,
2735 BUS_DMASYNC_POSTREAD);
2737 if (bwi_newbuf(sc, idx, 0)) {
2742 hdr = mtod(m, struct bwi_rxbuf_hdr *);
2743 flags2 = le16toh(hdr->rxh_flags2);
2746 if (flags2 & BWI_RXH_F2_TYPE2FRAME)
2748 wh_ofs = hdr_extra + 6; /* XXX magic number */
2750 buflen = le16toh(hdr->rxh_buflen);
2751 if (buflen < BWI_FRAME_MIN_LEN(wh_ofs)) {
2752 if_printf(ifp, "short frame %d, hdr_extra %d\n",
2759 plcp = ((const uint8_t *)(hdr + 1) + hdr_extra);
2760 rssi = bwi_calc_rssi(sc, hdr);
2762 m->m_pkthdr.rcvif = ifp;
2763 m->m_len = m->m_pkthdr.len = buflen + sizeof(*hdr);
2764 m_adj(m, sizeof(*hdr) + wh_ofs);
2766 if (htole16(hdr->rxh_flags1) & BWI_RXH_F1_OFDM)
2767 rate = bwi_ofdm_plcp2rate(plcp);
2769 rate = bwi_ds_plcp2rate(plcp);
2772 if (sc->sc_drvbpf != NULL)
2773 bwi_rx_radiotap(sc, m, hdr, plcp, rate, rssi);
2775 m_adj(m, -IEEE80211_CRC_LEN);
2777 wh = mtod(m, struct ieee80211_frame_min *);
2778 ni = ieee80211_find_rxnode(ic, wh);
2780 type = ieee80211_input(ic, m, ni, rssi - BWI_NOISE_FLOOR,
2781 le16toh(hdr->rxh_tsf));
2782 ieee80211_free_node(ni);
2784 if (type == IEEE80211_FC0_TYPE_DATA) {
2786 sc->sc_rx_rate = rate;
2789 idx = (idx + 1) % BWI_RX_NDESC;
2793 bus_dmamap_sync(sc->sc_rxring_dtag, rd->rdata_dmap,
2794 BUS_DMASYNC_PREWRITE);
2799 bwi_rxeof32(struct bwi_softc *sc)
2801 uint32_t val, rx_ctrl;
2802 int end_idx, rx_data;
2804 rx_ctrl = sc->sc_rx_rdata.rdata_txrx_ctrl;
2806 val = CSR_READ_4(sc, rx_ctrl + BWI_RX32_STATUS);
2807 end_idx = __SHIFTOUT(val, BWI_RX32_STATUS_INDEX_MASK) /
2808 sizeof(struct bwi_desc32);
2810 rx_data = bwi_rxeof(sc, end_idx);
2812 CSR_WRITE_4(sc, rx_ctrl + BWI_RX32_INDEX,
2813 end_idx * sizeof(struct bwi_desc32));
2819 bwi_rxeof64(struct bwi_softc *sc)
2826 bwi_reset_rx_ring32(struct bwi_softc *sc, uint32_t rx_ctrl)
2830 CSR_WRITE_4(sc, rx_ctrl + BWI_RX32_CTRL, 0);
2834 for (i = 0; i < NRETRY; ++i) {
2837 status = CSR_READ_4(sc, rx_ctrl + BWI_RX32_STATUS);
2838 if (__SHIFTOUT(status, BWI_RX32_STATUS_STATE_MASK) ==
2839 BWI_RX32_STATUS_STATE_DISABLED)
2845 if_printf(&sc->sc_ic.ic_if, "reset rx ring timedout\n");
2849 CSR_WRITE_4(sc, rx_ctrl + BWI_RX32_RINGINFO, 0);
2853 bwi_free_txstats32(struct bwi_softc *sc)
2855 bwi_reset_rx_ring32(sc, sc->sc_txstats->stats_ctrl_base);
2859 bwi_free_rx_ring32(struct bwi_softc *sc)
2861 struct bwi_ring_data *rd = &sc->sc_rx_rdata;
2862 struct bwi_rxbuf_data *rbd = &sc->sc_rx_bdata;
2865 bwi_reset_rx_ring32(sc, rd->rdata_txrx_ctrl);
2867 for (i = 0; i < BWI_RX_NDESC; ++i) {
2868 struct bwi_rxbuf *rb = &rbd->rbd_buf[i];
2870 if (rb->rb_mbuf != NULL) {
2871 bus_dmamap_unload(sc->sc_buf_dtag, rb->rb_dmap);
2872 m_freem(rb->rb_mbuf);
2879 bwi_free_tx_ring32(struct bwi_softc *sc, int ring_idx)
2881 struct bwi_ring_data *rd;
2882 struct bwi_txbuf_data *tbd;
2883 struct ifnet *ifp = &sc->sc_ic.ic_if;
2884 uint32_t state, val;
2887 KKASSERT(ring_idx < BWI_TX_NRING);
2888 rd = &sc->sc_tx_rdata[ring_idx];
2889 tbd = &sc->sc_tx_bdata[ring_idx];
2893 for (i = 0; i < NRETRY; ++i) {
2894 val = CSR_READ_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_STATUS);
2895 state = __SHIFTOUT(val, BWI_TX32_STATUS_STATE_MASK);
2896 if (state == BWI_TX32_STATUS_STATE_DISABLED ||
2897 state == BWI_TX32_STATUS_STATE_IDLE ||
2898 state == BWI_TX32_STATUS_STATE_STOPPED)
2904 if_printf(ifp, "wait for TX ring(%d) stable timed out\n",
2908 CSR_WRITE_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_CTRL, 0);
2909 for (i = 0; i < NRETRY; ++i) {
2910 val = CSR_READ_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_STATUS);
2911 state = __SHIFTOUT(val, BWI_TX32_STATUS_STATE_MASK);
2912 if (state == BWI_TX32_STATUS_STATE_DISABLED)
2918 if_printf(ifp, "reset TX ring (%d) timed out\n", ring_idx);
2924 CSR_WRITE_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_RINGINFO, 0);
2926 for (i = 0; i < BWI_TX_NDESC; ++i) {
2927 struct bwi_txbuf *tb = &tbd->tbd_buf[i];
2929 if (tb->tb_mbuf != NULL) {
2930 bus_dmamap_unload(sc->sc_buf_dtag, tb->tb_dmap);
2931 m_freem(tb->tb_mbuf);
2934 if (tb->tb_ni != NULL) {
2935 ieee80211_free_node(tb->tb_ni);
2942 bwi_free_txstats64(struct bwi_softc *sc)
2948 bwi_free_rx_ring64(struct bwi_softc *sc)
2954 bwi_free_tx_ring64(struct bwi_softc *sc, int ring_idx)
2960 bwi_encap(struct bwi_softc *sc, int idx, struct mbuf *m,
2961 struct ieee80211_node **ni0, int mgt_pkt)
2963 struct ieee80211com *ic = &sc->sc_ic;
2964 struct ieee80211_node *ni = *ni0;
2965 struct bwi_ring_data *rd = &sc->sc_tx_rdata[BWI_TX_DATA_RING];
2966 struct bwi_txbuf_data *tbd = &sc->sc_tx_bdata[BWI_TX_DATA_RING];
2967 struct bwi_txbuf *tb = &tbd->tbd_buf[idx];
2968 struct bwi_mac *mac;
2969 struct bwi_txbuf_hdr *hdr;
2970 struct ieee80211_frame *wh;
2971 uint8_t rate, rate_fb;
2975 int pkt_len, error, mcast_pkt = 0;
2981 KKASSERT(ni != NULL);
2982 KKASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC);
2983 mac = (struct bwi_mac *)sc->sc_cur_regwin;
2985 wh = mtod(m, struct ieee80211_frame *);
2987 /* Get 802.11 frame len before prepending TX header */
2988 pkt_len = m->m_pkthdr.len + IEEE80211_CRC_LEN;
2993 bzero(tb->tb_rateidx, sizeof(tb->tb_rateidx));
2995 if (ic->ic_fixed_rate != IEEE80211_FIXED_RATE_NONE) {
2998 rate = IEEE80211_RS_RATE(&ni->ni_rates,
3001 if (ic->ic_fixed_rate >= 1)
3002 idx = ic->ic_fixed_rate - 1;
3005 rate_fb = IEEE80211_RS_RATE(&ni->ni_rates, idx);
3007 tb->tb_rateidx_cnt = ieee80211_ratectl_findrate(ni,
3008 m->m_pkthdr.len, tb->tb_rateidx, BWI_NTXRATE);
3010 rate = IEEE80211_RS_RATE(&ni->ni_rates,
3012 if (tb->tb_rateidx_cnt == BWI_NTXRATE) {
3013 rate_fb = IEEE80211_RS_RATE(&ni->ni_rates,
3018 tb->tb_buflen = m->m_pkthdr.len;
3021 /* Fixed at 1Mbits/s for mgt frames */
3022 rate = rate_fb = (1 * 2);
3025 if (IEEE80211_IS_MULTICAST(wh->i_addr1)) {
3026 rate = rate_fb = ic->ic_mcast_rate;
3030 if (rate == 0 || rate_fb == 0) {
3031 /* XXX this should not happen */
3032 if_printf(&ic->ic_if, "invalid rate %u or fallback rate %u",
3034 rate = rate_fb = (1 * 2); /* Force 1Mbits/s */
3036 sc->sc_tx_rate = rate;
3041 if (sc->sc_drvbpf != NULL) {
3042 sc->sc_tx_th.wt_flags = 0;
3043 if (wh->i_fc[1] & IEEE80211_FC1_WEP)
3044 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_WEP;
3045 if (ieee80211_rate2modtype(rate) == IEEE80211_MODTYPE_DS &&
3046 (ic->ic_flags & IEEE80211_F_SHPREAMBLE) &&
3048 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_SHORTPRE;
3050 sc->sc_tx_th.wt_rate = rate;
3052 bpf_ptap(sc->sc_drvbpf, m, &sc->sc_tx_th, sc->sc_tx_th_len);
3056 * Setup the embedded TX header
3058 M_PREPEND(m, sizeof(*hdr), MB_DONTWAIT);
3060 if_printf(&ic->ic_if, "prepend TX header failed\n");
3063 hdr = mtod(m, struct bwi_txbuf_hdr *);
3065 bzero(hdr, sizeof(*hdr));
3067 bcopy(wh->i_fc, hdr->txh_fc, sizeof(hdr->txh_fc));
3068 bcopy(wh->i_addr1, hdr->txh_addr1, sizeof(hdr->txh_addr1));
3074 ack_rate = ieee80211_ack_rate(ni, rate_fb);
3075 dur = ieee80211_txtime(ni,
3076 sizeof(struct ieee80211_frame_ack) + IEEE80211_CRC_LEN,
3077 ack_rate, ic->ic_flags & ~IEEE80211_F_SHPREAMBLE);
3079 hdr->txh_fb_duration = htole16(dur);
3082 hdr->txh_id = __SHIFTIN(BWI_TX_DATA_RING, BWI_TXH_ID_RING_MASK) |
3083 __SHIFTIN(idx, BWI_TXH_ID_IDX_MASK);
3085 bwi_plcp_header(hdr->txh_plcp, pkt_len, rate);
3086 bwi_plcp_header(hdr->txh_fb_plcp, pkt_len, rate_fb);
3088 phy_ctrl = __SHIFTIN(mac->mac_rf.rf_ant_mode,
3089 BWI_TXH_PHY_C_ANTMODE_MASK);
3090 if (ieee80211_rate2modtype(rate) == IEEE80211_MODTYPE_OFDM)
3091 phy_ctrl |= BWI_TXH_PHY_C_OFDM;
3092 else if ((ic->ic_flags & IEEE80211_F_SHPREAMBLE) && rate != (2 * 1))
3093 phy_ctrl |= BWI_TXH_PHY_C_SHPREAMBLE;
3095 mac_ctrl = BWI_TXH_MAC_C_HWSEQ | BWI_TXH_MAC_C_FIRST_FRAG;
3096 if (!IEEE80211_IS_MULTICAST(wh->i_addr1))
3097 mac_ctrl |= BWI_TXH_MAC_C_ACK;
3098 if (ieee80211_rate2modtype(rate_fb) == IEEE80211_MODTYPE_OFDM)
3099 mac_ctrl |= BWI_TXH_MAC_C_FB_OFDM;
3101 hdr->txh_mac_ctrl = htole32(mac_ctrl);
3102 hdr->txh_phy_ctrl = htole16(phy_ctrl);
3104 /* Catch any further usage */
3109 error = bus_dmamap_load_mbuf(sc->sc_buf_dtag, tb->tb_dmap, m,
3110 bwi_dma_buf_addr, &paddr, BUS_DMA_NOWAIT);
3111 if (error && error != EFBIG) {
3112 if_printf(&ic->ic_if, "can't load TX buffer (1) %d\n", error);
3116 if (error) { /* error == EFBIG */
3119 m_new = m_defrag(m, MB_DONTWAIT);
3120 if (m_new == NULL) {
3121 if_printf(&ic->ic_if, "can't defrag TX buffer\n");
3128 error = bus_dmamap_load_mbuf(sc->sc_buf_dtag, tb->tb_dmap, m,
3129 bwi_dma_buf_addr, &paddr,
3132 if_printf(&ic->ic_if, "can't load TX buffer (2) %d\n",
3139 bus_dmamap_sync(sc->sc_buf_dtag, tb->tb_dmap, BUS_DMASYNC_PREWRITE);
3141 if (mgt_pkt || mcast_pkt) {
3142 /* Don't involve mcast/mgt packets into TX rate control */
3143 ieee80211_free_node(ni);
3150 p = mtod(m, const uint8_t *);
3151 for (i = 0; i < m->m_pkthdr.len; ++i) {
3152 if (i != 0 && i % 8 == 0)
3154 kprintf("%02x ", p[i]);
3159 DPRINTF(sc, BWI_DBG_TX, "idx %d, pkt_len %d, buflen %d\n",
3160 idx, pkt_len, m->m_pkthdr.len);
3162 /* Setup TX descriptor */
3163 sc->sc_setup_txdesc(sc, rd, idx, paddr, m->m_pkthdr.len);
3164 bus_dmamap_sync(sc->sc_txring_dtag, rd->rdata_dmap,
3165 BUS_DMASYNC_PREWRITE);
3168 sc->sc_start_tx(sc, rd->rdata_txrx_ctrl, idx);
3177 bwi_start_tx32(struct bwi_softc *sc, uint32_t tx_ctrl, int idx)
3179 idx = (idx + 1) % BWI_TX_NDESC;
3180 CSR_WRITE_4(sc, tx_ctrl + BWI_TX32_INDEX,
3181 idx * sizeof(struct bwi_desc32));
3185 bwi_start_tx64(struct bwi_softc *sc, uint32_t tx_ctrl, int idx)
3191 bwi_txeof_status32(struct bwi_softc *sc)
3193 struct ifnet *ifp = &sc->sc_ic.ic_if;
3194 uint32_t val, ctrl_base;
3197 ctrl_base = sc->sc_txstats->stats_ctrl_base;
3199 val = CSR_READ_4(sc, ctrl_base + BWI_RX32_STATUS);
3200 end_idx = __SHIFTOUT(val, BWI_RX32_STATUS_INDEX_MASK) /
3201 sizeof(struct bwi_desc32);
3203 bwi_txeof_status(sc, end_idx);
3205 CSR_WRITE_4(sc, ctrl_base + BWI_RX32_INDEX,
3206 end_idx * sizeof(struct bwi_desc32));
3208 if ((ifp->if_flags & IFF_OACTIVE) == 0)
3213 bwi_txeof_status64(struct bwi_softc *sc)
3219 _bwi_txeof(struct bwi_softc *sc, uint16_t tx_id, int acked, int data_txcnt)
3221 struct ifnet *ifp = &sc->sc_ic.ic_if;
3222 struct bwi_txbuf_data *tbd;
3223 struct bwi_txbuf *tb;
3224 int ring_idx, buf_idx;
3227 if_printf(ifp, "zero tx id\n");
3231 ring_idx = __SHIFTOUT(tx_id, BWI_TXH_ID_RING_MASK);
3232 buf_idx = __SHIFTOUT(tx_id, BWI_TXH_ID_IDX_MASK);
3234 KKASSERT(ring_idx == BWI_TX_DATA_RING);
3235 KKASSERT(buf_idx < BWI_TX_NDESC);
3237 tbd = &sc->sc_tx_bdata[ring_idx];
3238 KKASSERT(tbd->tbd_used > 0);
3241 tb = &tbd->tbd_buf[buf_idx];
3243 DPRINTF(sc, BWI_DBG_TXEOF, "txeof idx %d, "
3244 "acked %d, data_txcnt %d, ni %p\n",
3245 buf_idx, acked, data_txcnt, tb->tb_ni);
3247 bus_dmamap_unload(sc->sc_buf_dtag, tb->tb_dmap);
3248 m_freem(tb->tb_mbuf);
3251 if (tb->tb_ni != NULL) {
3252 struct ieee80211_ratectl_res res[BWI_NTXRATE];
3255 if (data_txcnt <= BWI_SHRETRY_FB || tb->tb_rateidx_cnt == 1) {
3257 res[0].rc_res_rateidx = tb->tb_rateidx[0];
3258 res[0].rc_res_tries = data_txcnt;
3260 res_len = BWI_NTXRATE;
3261 res[0].rc_res_rateidx = tb->tb_rateidx[0];
3262 res[0].rc_res_tries = BWI_SHRETRY_FB;
3263 res[1].rc_res_rateidx = tb->tb_rateidx[1];
3264 res[1].rc_res_tries = data_txcnt - BWI_SHRETRY_FB;
3268 retry = data_txcnt > 0 ? data_txcnt - 1 : 0;
3272 ieee80211_ratectl_tx_complete(tb->tb_ni, tb->tb_buflen,
3273 res, res_len, retry, 0, !acked);
3275 ieee80211_free_node(tb->tb_ni);
3279 if (tbd->tbd_used == 0)
3280 sc->sc_tx_timer = 0;
3282 ifp->if_flags &= ~IFF_OACTIVE;
3286 bwi_txeof_status(struct bwi_softc *sc, int end_idx)
3288 struct bwi_txstats_data *st = sc->sc_txstats;
3291 bus_dmamap_sync(st->stats_dtag, st->stats_dmap, BUS_DMASYNC_POSTREAD);
3293 idx = st->stats_idx;
3294 while (idx != end_idx) {
3295 const struct bwi_txstats *stats = &st->stats[idx];
3297 if ((stats->txs_flags & BWI_TXS_F_PENDING) == 0) {
3300 data_txcnt = __SHIFTOUT(stats->txs_txcnt,
3301 BWI_TXS_TXCNT_DATA);
3302 _bwi_txeof(sc, le16toh(stats->txs_id),
3303 stats->txs_flags & BWI_TXS_F_ACKED,
3306 idx = (idx + 1) % BWI_TXSTATS_NDESC;
3308 st->stats_idx = idx;
3312 bwi_txeof(struct bwi_softc *sc)
3314 struct ifnet *ifp = &sc->sc_ic.ic_if;
3317 uint32_t tx_status0, tx_status1;
3321 tx_status0 = CSR_READ_4(sc, BWI_TXSTATUS0);
3322 if ((tx_status0 & BWI_TXSTATUS0_VALID) == 0)
3324 tx_status1 = CSR_READ_4(sc, BWI_TXSTATUS1);
3326 tx_id = __SHIFTOUT(tx_status0, BWI_TXSTATUS0_TXID_MASK);
3327 data_txcnt = __SHIFTOUT(tx_status0,
3328 BWI_TXSTATUS0_DATA_TXCNT_MASK);
3330 if (tx_status0 & (BWI_TXSTATUS0_AMPDU | BWI_TXSTATUS0_PENDING))
3333 _bwi_txeof(sc, tx_id, tx_status0 & BWI_TXSTATUS0_ACKED,
3337 if ((ifp->if_flags & IFF_OACTIVE) == 0)
3342 bwi_bbp_power_on(struct bwi_softc *sc, enum bwi_clock_mode clk_mode)
3344 bwi_power_on(sc, 1);
3345 return bwi_set_clock_mode(sc, clk_mode);
3349 bwi_bbp_power_off(struct bwi_softc *sc)
3351 bwi_set_clock_mode(sc, BWI_CLOCK_MODE_SLOW);
3352 bwi_power_off(sc, 1);
3356 bwi_get_pwron_delay(struct bwi_softc *sc)
3358 struct bwi_regwin *com, *old;
3359 struct bwi_clock_freq freq;
3363 com = &sc->sc_com_regwin;
3364 KKASSERT(BWI_REGWIN_EXIST(com));
3366 if ((sc->sc_cap & BWI_CAP_CLKMODE) == 0)
3369 error = bwi_regwin_switch(sc, com, &old);
3373 bwi_get_clock_freq(sc, &freq);
3375 val = CSR_READ_4(sc, BWI_PLL_ON_DELAY);
3376 sc->sc_pwron_delay = howmany((val + 2) * 1000000, freq.clkfreq_min);
3377 DPRINTF(sc, BWI_DBG_ATTACH, "power on delay %u\n", sc->sc_pwron_delay);
3379 return bwi_regwin_switch(sc, old, NULL);
3383 bwi_bus_attach(struct bwi_softc *sc)
3385 struct bwi_regwin *bus, *old;
3388 bus = &sc->sc_bus_regwin;
3390 error = bwi_regwin_switch(sc, bus, &old);
3394 if (!bwi_regwin_is_enabled(sc, bus))
3395 bwi_regwin_enable(sc, bus, 0);
3397 /* Disable interripts */
3398 CSR_WRITE_4(sc, BWI_INTRVEC, 0);
3400 return bwi_regwin_switch(sc, old, NULL);
3404 bwi_regwin_name(const struct bwi_regwin *rw)
3406 switch (rw->rw_type) {
3407 case BWI_REGWIN_T_COM:
3409 case BWI_REGWIN_T_BUSPCI:
3411 case BWI_REGWIN_T_MAC:
3413 case BWI_REGWIN_T_BUSPCIE:
3416 panic("unknown regwin type 0x%04x\n", rw->rw_type);
3421 bwi_regwin_disable_bits(struct bwi_softc *sc)
3425 /* XXX cache this */
3426 busrev = __SHIFTOUT(CSR_READ_4(sc, BWI_ID_LO), BWI_ID_LO_BUSREV_MASK);
3427 DPRINTF(sc, BWI_DBG_ATTACH | BWI_DBG_INIT | BWI_DBG_MISC,
3428 "bus rev %u\n", busrev);
3430 if (busrev == BWI_BUSREV_0)
3431 return BWI_STATE_LO_DISABLE1;
3432 else if (busrev == BWI_BUSREV_1)
3433 return BWI_STATE_LO_DISABLE2;
3435 return (BWI_STATE_LO_DISABLE1 | BWI_STATE_LO_DISABLE2);
3439 bwi_regwin_is_enabled(struct bwi_softc *sc, struct bwi_regwin *rw)
3441 uint32_t val, disable_bits;
3443 disable_bits = bwi_regwin_disable_bits(sc);
3444 val = CSR_READ_4(sc, BWI_STATE_LO);
3446 if ((val & (BWI_STATE_LO_CLOCK |
3447 BWI_STATE_LO_RESET |
3448 disable_bits)) == BWI_STATE_LO_CLOCK) {
3449 DPRINTF(sc, BWI_DBG_ATTACH | BWI_DBG_INIT, "%s is enabled\n",
3450 bwi_regwin_name(rw));
3453 DPRINTF(sc, BWI_DBG_ATTACH | BWI_DBG_INIT, "%s is disabled\n",
3454 bwi_regwin_name(rw));
3460 bwi_regwin_disable(struct bwi_softc *sc, struct bwi_regwin *rw, uint32_t flags)
3462 uint32_t state_lo, disable_bits;
3465 state_lo = CSR_READ_4(sc, BWI_STATE_LO);
3468 * If current regwin is in 'reset' state, it was already disabled.
3470 if (state_lo & BWI_STATE_LO_RESET) {
3471 DPRINTF(sc, BWI_DBG_ATTACH | BWI_DBG_INIT,
3472 "%s was already disabled\n", bwi_regwin_name(rw));
3476 disable_bits = bwi_regwin_disable_bits(sc);
3479 * Disable normal clock
3481 state_lo = BWI_STATE_LO_CLOCK | disable_bits;
3482 CSR_WRITE_4(sc, BWI_STATE_LO, state_lo);
3485 * Wait until normal clock is disabled
3488 for (i = 0; i < NRETRY; ++i) {
3489 state_lo = CSR_READ_4(sc, BWI_STATE_LO);
3490 if (state_lo & disable_bits)
3495 device_printf(sc->sc_dev, "%s disable clock timeout\n",
3496 bwi_regwin_name(rw));
3499 for (i = 0; i < NRETRY; ++i) {
3502 state_hi = CSR_READ_4(sc, BWI_STATE_HI);
3503 if ((state_hi & BWI_STATE_HI_BUSY) == 0)
3508 device_printf(sc->sc_dev, "%s wait BUSY unset timeout\n",
3509 bwi_regwin_name(rw));
3514 * Reset and disable regwin with gated clock
3516 state_lo = BWI_STATE_LO_RESET | disable_bits |
3517 BWI_STATE_LO_CLOCK | BWI_STATE_LO_GATED_CLOCK |
3518 __SHIFTIN(flags, BWI_STATE_LO_FLAGS_MASK);
3519 CSR_WRITE_4(sc, BWI_STATE_LO, state_lo);
3521 /* Flush pending bus write */
3522 CSR_READ_4(sc, BWI_STATE_LO);
3525 /* Reset and disable regwin */
3526 state_lo = BWI_STATE_LO_RESET | disable_bits |
3527 __SHIFTIN(flags, BWI_STATE_LO_FLAGS_MASK);
3528 CSR_WRITE_4(sc, BWI_STATE_LO, state_lo);
3530 /* Flush pending bus write */
3531 CSR_READ_4(sc, BWI_STATE_LO);
3536 bwi_regwin_enable(struct bwi_softc *sc, struct bwi_regwin *rw, uint32_t flags)
3538 uint32_t state_lo, state_hi, imstate;
3540 bwi_regwin_disable(sc, rw, flags);
3542 /* Reset regwin with gated clock */
3543 state_lo = BWI_STATE_LO_RESET |
3544 BWI_STATE_LO_CLOCK |
3545 BWI_STATE_LO_GATED_CLOCK |
3546 __SHIFTIN(flags, BWI_STATE_LO_FLAGS_MASK);
3547 CSR_WRITE_4(sc, BWI_STATE_LO, state_lo);
3549 /* Flush pending bus write */
3550 CSR_READ_4(sc, BWI_STATE_LO);
3553 state_hi = CSR_READ_4(sc, BWI_STATE_HI);
3554 if (state_hi & BWI_STATE_HI_SERROR)
3555 CSR_WRITE_4(sc, BWI_STATE_HI, 0);
3557 imstate = CSR_READ_4(sc, BWI_IMSTATE);
3558 if (imstate & (BWI_IMSTATE_INBAND_ERR | BWI_IMSTATE_TIMEOUT)) {
3559 imstate &= ~(BWI_IMSTATE_INBAND_ERR | BWI_IMSTATE_TIMEOUT);
3560 CSR_WRITE_4(sc, BWI_IMSTATE, imstate);
3563 /* Enable regwin with gated clock */
3564 state_lo = BWI_STATE_LO_CLOCK |
3565 BWI_STATE_LO_GATED_CLOCK |
3566 __SHIFTIN(flags, BWI_STATE_LO_FLAGS_MASK);
3567 CSR_WRITE_4(sc, BWI_STATE_LO, state_lo);
3569 /* Flush pending bus write */
3570 CSR_READ_4(sc, BWI_STATE_LO);
3573 /* Enable regwin with normal clock */
3574 state_lo = BWI_STATE_LO_CLOCK |
3575 __SHIFTIN(flags, BWI_STATE_LO_FLAGS_MASK);
3576 CSR_WRITE_4(sc, BWI_STATE_LO, state_lo);
3578 /* Flush pending bus write */
3579 CSR_READ_4(sc, BWI_STATE_LO);
3584 bwi_set_bssid(struct bwi_softc *sc, const uint8_t *bssid)
3586 struct ieee80211com *ic = &sc->sc_ic;
3587 struct bwi_mac *mac;
3588 struct bwi_myaddr_bssid buf;
3593 KKASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC);
3594 mac = (struct bwi_mac *)sc->sc_cur_regwin;
3596 bwi_set_addr_filter(sc, BWI_ADDR_FILTER_BSSID, bssid);
3598 bcopy(ic->ic_myaddr, buf.myaddr, sizeof(buf.myaddr));
3599 bcopy(bssid, buf.bssid, sizeof(buf.bssid));
3601 n = sizeof(buf) / sizeof(val);
3602 p = (const uint8_t *)&buf;
3603 for (i = 0; i < n; ++i) {
3607 for (j = 0; j < sizeof(val); ++j)
3608 val |= ((uint32_t)(*p++)) << (j * 8);
3610 TMPLT_WRITE_4(mac, 0x20 + (i * sizeof(val)), val);
3615 bwi_updateslot(struct ifnet *ifp)
3617 struct bwi_softc *sc = ifp->if_softc;
3618 struct ieee80211com *ic = &sc->sc_ic;
3619 struct bwi_mac *mac;
3621 if ((ifp->if_flags & IFF_RUNNING) == 0)
3624 ASSERT_SERIALIZED(ifp->if_serializer);
3626 DPRINTF(sc, BWI_DBG_80211, "%s\n", __func__);
3628 KKASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC);
3629 mac = (struct bwi_mac *)sc->sc_cur_regwin;
3631 bwi_mac_updateslot(mac, (ic->ic_flags & IEEE80211_F_SHSLOT));
3635 bwi_calibrate(void *xsc)
3637 struct bwi_softc *sc = xsc;
3638 struct ieee80211com *ic = &sc->sc_ic;
3639 struct ifnet *ifp = &ic->ic_if;
3641 lwkt_serialize_enter(ifp->if_serializer);
3643 if (ic->ic_state == IEEE80211_S_RUN) {
3644 struct bwi_mac *mac;
3646 KKASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC);
3647 mac = (struct bwi_mac *)sc->sc_cur_regwin;
3649 if (ic->ic_opmode != IEEE80211_M_MONITOR)
3650 bwi_mac_calibrate_txpower(mac);
3652 /* XXX 15 seconds */
3653 callout_reset(&sc->sc_calib_ch, hz * 15, bwi_calibrate, sc);
3656 lwkt_serialize_exit(ifp->if_serializer);
3660 bwi_calc_rssi(struct bwi_softc *sc, const struct bwi_rxbuf_hdr *hdr)
3662 struct bwi_mac *mac;
3664 KKASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC);
3665 mac = (struct bwi_mac *)sc->sc_cur_regwin;
3667 return bwi_rf_calc_rssi(mac, hdr);
3671 bwi_rx_radiotap(struct bwi_softc *sc, struct mbuf *m,
3672 struct bwi_rxbuf_hdr *hdr, const void *plcp,
3675 const struct ieee80211_frame_min *wh;
3677 KKASSERT(sc->sc_drvbpf != NULL);
3679 sc->sc_rx_th.wr_flags = IEEE80211_RADIOTAP_F_FCS;
3680 if (htole16(hdr->rxh_flags1) & BWI_RXH_F1_SHPREAMBLE)
3681 sc->sc_rx_th.wr_flags |= IEEE80211_RADIOTAP_F_SHORTPRE;
3683 wh = mtod(m, const struct ieee80211_frame_min *);
3684 if (wh->i_fc[1] & IEEE80211_FC1_WEP)
3685 sc->sc_rx_th.wr_flags |= IEEE80211_RADIOTAP_F_WEP;
3687 sc->sc_rx_th.wr_tsf = hdr->rxh_tsf; /* No endian convertion */
3688 sc->sc_rx_th.wr_rate = rate;
3689 sc->sc_rx_th.wr_antsignal = rssi;
3690 sc->sc_rx_th.wr_antnoise = BWI_NOISE_FLOOR;
3692 bpf_ptap(sc->sc_drvbpf, m, &sc->sc_rx_th, sc->sc_rx_th_len);
3696 bwi_led_attach(struct bwi_softc *sc)
3698 const uint8_t *led_act = NULL;
3699 uint16_t gpio, val[BWI_LED_MAX];
3702 #define N(arr) (int)(sizeof(arr) / sizeof(arr[0]))
3704 for (i = 0; i < N(bwi_vendor_led_act); ++i) {
3705 if (sc->sc_pci_subvid == bwi_vendor_led_act[i].vid) {
3706 led_act = bwi_vendor_led_act[i].led_act;
3710 if (led_act == NULL)
3711 led_act = bwi_default_led_act;
3715 gpio = bwi_read_sprom(sc, BWI_SPROM_GPIO01);
3716 val[0] = __SHIFTOUT(gpio, BWI_SPROM_GPIO_0);
3717 val[1] = __SHIFTOUT(gpio, BWI_SPROM_GPIO_1);
3719 gpio = bwi_read_sprom(sc, BWI_SPROM_GPIO23);
3720 val[2] = __SHIFTOUT(gpio, BWI_SPROM_GPIO_2);
3721 val[3] = __SHIFTOUT(gpio, BWI_SPROM_GPIO_3);
3723 for (i = 0; i < BWI_LED_MAX; ++i) {
3724 struct bwi_led *led = &sc->sc_leds[i];
3726 if (val[i] == 0xff) {
3727 led->l_act = led_act[i];
3729 if (val[i] & BWI_LED_ACT_LOW)
3730 led->l_flags |= BWI_LED_F_ACTLOW;
3731 led->l_act = __SHIFTOUT(val[i], BWI_LED_ACT_MASK);
3733 led->l_mask = (1 << i);
3735 if (led->l_act == BWI_LED_ACT_BLINK_SLOW ||
3736 led->l_act == BWI_LED_ACT_BLINK_POLL ||
3737 led->l_act == BWI_LED_ACT_BLINK) {
3738 led->l_flags |= BWI_LED_F_BLINK;
3739 if (led->l_act == BWI_LED_ACT_BLINK_POLL)
3740 led->l_flags |= BWI_LED_F_POLLABLE;
3741 else if (led->l_act == BWI_LED_ACT_BLINK_SLOW)
3742 led->l_flags |= BWI_LED_F_SLOW;
3744 if (sc->sc_blink_led == NULL) {
3745 sc->sc_blink_led = led;
3746 if (led->l_flags & BWI_LED_F_SLOW)
3747 BWI_LED_SLOWDOWN(sc->sc_led_idle);
3751 DPRINTF(sc, BWI_DBG_LED | BWI_DBG_ATTACH,
3752 "%dth led, act %d, lowact %d\n", i,
3753 led->l_act, led->l_flags & BWI_LED_F_ACTLOW);
3755 callout_init(&sc->sc_led_blink_ch);
3758 static __inline uint16_t
3759 bwi_led_onoff(const struct bwi_led *led, uint16_t val, int on)
3761 if (led->l_flags & BWI_LED_F_ACTLOW)
3766 val &= ~led->l_mask;
3771 bwi_led_newstate(struct bwi_softc *sc, enum ieee80211_state nstate)
3773 struct ieee80211com *ic = &sc->sc_ic;
3777 if (nstate == IEEE80211_S_INIT) {
3778 callout_stop(&sc->sc_led_blink_ch);
3779 sc->sc_led_blinking = 0;
3782 if ((ic->ic_if.if_flags & IFF_RUNNING) == 0)
3785 val = CSR_READ_2(sc, BWI_MAC_GPIO_CTRL);
3786 for (i = 0; i < BWI_LED_MAX; ++i) {
3787 struct bwi_led *led = &sc->sc_leds[i];
3790 if (led->l_act == BWI_LED_ACT_UNKN ||
3791 led->l_act == BWI_LED_ACT_NULL)
3794 if ((led->l_flags & BWI_LED_F_BLINK) &&
3795 nstate != IEEE80211_S_INIT)
3798 switch (led->l_act) {
3799 case BWI_LED_ACT_ON: /* Always on */
3802 case BWI_LED_ACT_OFF: /* Always off */
3803 case BWI_LED_ACT_5GHZ: /* TODO: 11A */
3809 case IEEE80211_S_INIT:
3812 case IEEE80211_S_RUN:
3813 if (led->l_act == BWI_LED_ACT_11G &&
3814 ic->ic_curmode != IEEE80211_MODE_11G)
3818 if (led->l_act == BWI_LED_ACT_ASSOC)
3825 val = bwi_led_onoff(led, val, on);
3827 CSR_WRITE_2(sc, BWI_MAC_GPIO_CTRL, val);
3831 bwi_led_event(struct bwi_softc *sc, int event)
3833 struct bwi_led *led = sc->sc_blink_led;
3836 if (event == BWI_LED_EVENT_POLL) {
3837 if ((led->l_flags & BWI_LED_F_POLLABLE) == 0)
3839 if (ticks - sc->sc_led_ticks < sc->sc_led_idle)
3843 sc->sc_led_ticks = ticks;
3844 if (sc->sc_led_blinking)
3848 case BWI_LED_EVENT_RX:
3849 rate = sc->sc_rx_rate;
3851 case BWI_LED_EVENT_TX:
3852 rate = sc->sc_tx_rate;
3854 case BWI_LED_EVENT_POLL:
3858 panic("unknown LED event %d\n", event);
3861 bwi_led_blink_start(sc, bwi_led_duration[rate].on_dur,
3862 bwi_led_duration[rate].off_dur);
3866 bwi_led_blink_start(struct bwi_softc *sc, int on_dur, int off_dur)
3868 struct bwi_led *led = sc->sc_blink_led;
3871 val = CSR_READ_2(sc, BWI_MAC_GPIO_CTRL);
3872 val = bwi_led_onoff(led, val, 1);
3873 CSR_WRITE_2(sc, BWI_MAC_GPIO_CTRL, val);
3875 if (led->l_flags & BWI_LED_F_SLOW) {
3876 BWI_LED_SLOWDOWN(on_dur);
3877 BWI_LED_SLOWDOWN(off_dur);
3880 sc->sc_led_blinking = 1;
3881 sc->sc_led_blink_offdur = off_dur;
3883 callout_reset(&sc->sc_led_blink_ch, on_dur, bwi_led_blink_next, sc);
3887 bwi_led_blink_next(void *xsc)
3889 struct bwi_softc *sc = xsc;
3892 val = CSR_READ_2(sc, BWI_MAC_GPIO_CTRL);
3893 val = bwi_led_onoff(sc->sc_blink_led, val, 0);
3894 CSR_WRITE_2(sc, BWI_MAC_GPIO_CTRL, val);
3896 callout_reset(&sc->sc_led_blink_ch, sc->sc_led_blink_offdur,
3897 bwi_led_blink_end, sc);
3901 bwi_led_blink_end(void *xsc)
3903 struct bwi_softc *sc = xsc;
3905 sc->sc_led_blinking = 0;