2 * Copyright (c) 1989, 1990 William F. Jolitz.
3 * Copyright (c) 1990 The Regents of the University of California.
4 * Copyright (c) 2007 The FreeBSD Foundation
5 * Copyright (c) 2008 The DragonFly Project.
6 * Copyright (c) 2008 Jordan Gordeev.
9 * Portions of this software were developed by A. Joseph Koshy under
10 * sponsorship from the FreeBSD Foundation and Google, Inc.
12 * Redistribution and use in source and binary forms, with or without
13 * modification, are permitted provided that the following conditions
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in the
19 * documentation and/or other materials provided with the distribution.
20 * 4. Neither the name of the University nor the names of its contributors
21 * may be used to endorse or promote products derived from this software
22 * without specific prior written permission.
24 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
30 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
38 #include "opt_atpic.h"
40 #include "opt_compat.h"
42 #include <machine/asmacros.h>
43 #include <machine/psl.h>
44 #include <machine/trap.h>
45 #include <machine/segments.h>
51 /*****************************************************************************/
53 /*****************************************************************************/
55 * Trap and fault vector routines.
57 * All traps are 'interrupt gates', SDT_SYSIGT. An interrupt gate pushes
58 * state on the stack but also disables interrupts. This is important for
59 * us for the use of the swapgs instruction. We cannot be interrupted
60 * until the GS.base value is correct. For most traps, we automatically
61 * then enable interrupts if the interrupted context had them enabled.
62 * This is equivalent to the i386 port's use of SDT_SYS386TGT.
64 * The cpu will push a certain amount of state onto the kernel stack for
65 * the current process. See x86_64/include/frame.h.
66 * This includes the current RFLAGS (status register, which includes
67 * the interrupt disable state prior to the trap), the code segment register,
68 * and the return instruction pointer are pushed by the cpu. The cpu
69 * will also push an 'error' code for certain traps. We push a dummy
70 * error code for those traps where the cpu doesn't in order to maintain
71 * a consistent frame. We also push a contrived 'trap number'.
73 * The cpu does not push the general registers, we must do that, and we
74 * must restore them prior to calling 'iret'. The cpu adjusts the %cs and
75 * %ss segment registers, but does not mess with %ds, %es, or %fs. Thus we
76 * must load them with appropriate values for supervisor mode operation.
83 * Interrupts are enabled for all traps, otherwise horrible livelocks
84 * can occur with the smp_invltlb and cpusync ode.
87 #define TRAP_NOEN(a) \
89 movq $0,TF_XFLAGS(%rsp) ; \
90 movq $(a),TF_TRAPNO(%rsp) ; \
91 movq $0,TF_ADDR(%rsp) ; \
92 movq $0,TF_ERR(%rsp) ; \
96 /* Regular traps; The cpu does not supply tf_err for these. */
99 movq $0,TF_XFLAGS(%rsp) ; \
100 movq $(a),TF_TRAPNO(%rsp) ; \
101 movq $0,TF_ADDR(%rsp) ; \
102 movq $0,TF_ERR(%rsp) ; \
129 /* This group of traps have tf_err already pushed by the cpu */
130 #define TRAP_ERR(a) \
132 movq $(a),TF_TRAPNO(%rsp) ; \
133 movq $0,TF_ADDR(%rsp) ; \
134 movq $0,TF_XFLAGS(%rsp) ; \
146 * alltraps entry point. Use swapgs if this is the first time in the
147 * kernel from userland. Reenable interrupts if they were enabled
148 * before the trap. This approximates SDT_SYS386TGT on the i386 port.
153 .type alltraps,@function
155 /* Fixup %gs if coming from userland */
156 testb $SEL_RPL_MASK,TF_CS(%rsp)
160 testq $PSL_I,TF_RFLAGS(%rsp)
164 movq %rdi,TF_RDI(%rsp)
165 alltraps_pushregs_no_rdi:
166 movq %rsi,TF_RSI(%rsp)
167 movq %rdx,TF_RDX(%rsp)
168 movq %rcx,TF_RCX(%rsp)
171 movq %rax,TF_RAX(%rsp)
172 movq %rbx,TF_RBX(%rsp)
173 movq %rbp,TF_RBP(%rsp)
174 movq %r10,TF_R10(%rsp)
175 movq %r11,TF_R11(%rsp)
176 movq %r12,TF_R12(%rsp)
177 movq %r13,TF_R13(%rsp)
178 movq %r14,TF_R14(%rsp)
179 movq %r15,TF_R15(%rsp)
180 FAKE_MCOUNT(TF_RIP(%rsp))
182 .type calltrap,@function
187 jmp doreti /* Handle any pending ASTs */
190 * alltraps_noen entry point. Unlike alltraps above, we want to
191 * leave the interrupts disabled. This corresponds to
192 * SDT_SYS386IGT on the i386 port.
196 .type alltraps_noen,@function
198 /* Fixup %gs if coming from userland */
199 testb $SEL_RPL_MASK,TF_CS(%rsp)
202 jmp alltraps_pushregs
206 movq $T_DOUBLEFLT,TF_TRAPNO(%rsp)
207 movq $0,TF_ADDR(%rsp)
209 movq $0,TF_XFLAGS(%rsp)
210 movq %rdi,TF_RDI(%rsp)
211 movq %rsi,TF_RSI(%rsp)
212 movq %rdx,TF_RDX(%rsp)
213 movq %rcx,TF_RCX(%rsp)
216 movq %rax,TF_RAX(%rsp)
217 movq %rbx,TF_RBX(%rsp)
218 movq %rbp,TF_RBP(%rsp)
219 movq %r10,TF_R10(%rsp)
220 movq %r11,TF_R11(%rsp)
221 movq %r12,TF_R12(%rsp)
222 movq %r13,TF_R13(%rsp)
223 movq %r14,TF_R14(%rsp)
224 movq %r15,TF_R15(%rsp)
225 testb $SEL_RPL_MASK,TF_CS(%rsp)
229 call dblfault_handler
235 movq $T_PAGEFLT,TF_TRAPNO(%rsp)
236 /* Fixup %gs if coming from userland */
237 testb $SEL_RPL_MASK,TF_CS(%rsp)
241 movq %rdi,TF_RDI(%rsp) /* free up a GP register */
242 movq %cr2,%rdi /* preserve %cr2 before .. */
243 movq %rdi,TF_ADDR(%rsp) /* enabling interrupts. */
244 movq $0,TF_XFLAGS(%rsp)
245 testq $PSL_I,TF_RFLAGS(%rsp)
246 jz alltraps_pushregs_no_rdi
248 jmp alltraps_pushregs_no_rdi
251 * We have to special-case this one. If we get a trap in doreti() at
252 * the iretq stage, we'll reenter with the wrong gs state. We'll have
253 * to do a special the swapgs in this case even coming from the kernel.
254 * XXX linux has a trap handler for their equivalent of load_gs().
258 movq $T_PROTFLT,TF_TRAPNO(%rsp)
259 movq $0,TF_ADDR(%rsp)
260 movq $0,TF_XFLAGS(%rsp)
261 movq %rdi,TF_RDI(%rsp) /* free up a GP register */
264 * Fixup %gs if coming from userland. Handle the special case where
265 * %fs faults in doreti at the iretq instruction itself.
267 leaq doreti_iret(%rip),%rdi
268 cmpq %rdi,TF_RIP(%rsp) /* special iretq fault case */
270 testb $SEL_RPL_MASK,TF_CS(%rsp) /* check if from userland */
275 testq $PSL_I,TF_RFLAGS(%rsp)
276 jz alltraps_pushregs_no_rdi
278 jmp alltraps_pushregs_no_rdi
281 * Fast syscall entry point. We enter here with just our new %cs/%ss set,
282 * and the new privilige level. We are still running on the old user stack
283 * pointer. We have to juggle a few things around to find our stack etc.
284 * swapgs gives us access to our PCPU space only.
288 movq %rsp,PCPU(scratch_rsp)
289 movq PCPU(common_tss) + TSS_RSP0, %rsp
290 /* Now emulate a trapframe. Make the 8 byte alignment odd for call. */
292 /* defer TF_RSP till we have a spare register */
293 movq %r11,TF_RFLAGS(%rsp)
294 movq %rcx,TF_RIP(%rsp) /* %rcx original value is in %r10 */
295 movq PCPU(scratch_rsp),%r11 /* %r11 already saved */
296 movq %r11,TF_RSP(%rsp) /* user stack pointer */
298 movq $KUDSEL,TF_SS(%rsp)
299 movq $KUCSEL,TF_CS(%rsp)
301 movq $T_FAST_SYSCALL,TF_TRAPNO(%rsp) /* for the vkernel */
302 movq $0,TF_XFLAGS(%rsp) /* note: used in signal frame */
303 movq %rdi,TF_RDI(%rsp) /* arg 1 */
304 movq %rsi,TF_RSI(%rsp) /* arg 2 */
305 movq %rdx,TF_RDX(%rsp) /* arg 3 */
306 movq %r10,TF_RCX(%rsp) /* arg 4 */
307 movq %r8,TF_R8(%rsp) /* arg 5 */
308 movq %r9,TF_R9(%rsp) /* arg 6 */
309 movq %rax,TF_RAX(%rsp) /* syscall number */
310 movq %rbx,TF_RBX(%rsp) /* C preserved */
311 movq %rbp,TF_RBP(%rsp) /* C preserved */
312 movq %r12,TF_R12(%rsp) /* C preserved */
313 movq %r13,TF_R13(%rsp) /* C preserved */
314 movq %r14,TF_R14(%rsp) /* C preserved */
315 movq %r15,TF_R15(%rsp) /* C preserved */
316 FAKE_MCOUNT(TF_RIP(%rsp))
323 * Here for CYA insurance, in case a "syscall" instruction gets
324 * issued from 32 bit compatability mode. MSR_CSTAR has to point
325 * to *something* if EFER_SCE is enabled.
327 IDTVEC(fast_syscall32)
331 * NMI handling is special.
333 * First, NMIs do not respect the state of the processor's RFLAGS.IF
334 * bit and the NMI handler may be invoked at any time, including when
335 * the processor is in a critical section with RFLAGS.IF == 0. In
336 * particular, this means that the processor's GS.base values could be
337 * inconsistent on entry to the handler, and so we need to read
338 * MSR_GSBASE to determine if a 'swapgs' is needed. We use '%ebx', a
339 * C-preserved register, to remember whether to swap GS back on the
342 * Second, the processor treats NMIs specially, blocking further NMIs
343 * until an 'iretq' instruction is executed. We therefore need to
344 * execute the NMI handler with interrupts disabled to prevent a
345 * nested interrupt from executing an 'iretq' instruction and
346 * inadvertently taking the processor out of NMI mode.
348 * Third, the NMI handler runs on its own stack (tss_ist1), shared
349 * with the double fault handler.
354 movq $(T_NMI),TF_TRAPNO(%rsp)
355 movq $0,TF_ADDR(%rsp)
357 movq $0,TF_XFLAGS(%rsp)
358 movq %rdi,TF_RDI(%rsp)
359 movq %rsi,TF_RSI(%rsp)
360 movq %rdx,TF_RDX(%rsp)
361 movq %rcx,TF_RCX(%rsp)
364 movq %rax,TF_RAX(%rsp)
365 movq %rbx,TF_RBX(%rsp)
366 movq %rbp,TF_RBP(%rsp)
367 movq %r10,TF_R10(%rsp)
368 movq %r11,TF_R11(%rsp)
369 movq %r12,TF_R12(%rsp)
370 movq %r13,TF_R13(%rsp)
371 movq %r14,TF_R14(%rsp)
372 movq %r15,TF_R15(%rsp)
374 testb $SEL_RPL_MASK,TF_CS(%rsp)
375 jnz nmi_needswapgs /* we came from userland */
376 movl $MSR_GSBASE,%ecx
378 cmpl $VM_MAX_USER_ADDRESS >> 32,%edx
379 jae nmi_calltrap /* GS.base holds a kernel VA */
383 /* Note: this label is also used by ddb and gdb: */
385 FAKE_MCOUNT(TF_RIP(%rsp))
393 movq TF_RDI(%rsp),%rdi
394 movq TF_RSI(%rsp),%rsi
395 movq TF_RDX(%rsp),%rdx
396 movq TF_RCX(%rsp),%rcx
399 movq TF_RAX(%rsp),%rax
400 movq TF_RBX(%rsp),%rbx
401 movq TF_RBP(%rsp),%rbp
402 movq TF_R10(%rsp),%r10
403 movq TF_R11(%rsp),%r11
404 movq TF_R12(%rsp),%r12
405 movq TF_R13(%rsp),%r13
406 movq TF_R14(%rsp),%r14
407 movq TF_R15(%rsp),%r15
412 * This function is what cpu_heavy_restore jumps to after a new process
413 * is created. The LWKT subsystem switches while holding a critical
414 * section and we maintain that abstraction here (e.g. because
415 * cpu_heavy_restore needs it due to PCB_*() manipulation), then get out of
416 * it before calling the initial function (typically fork_return()) and/or
417 * returning to user mode.
419 * The MP lock is not held at any point but the critcount is bumped
420 * on entry to prevent interruption of the trampoline at a bad point.
422 ENTRY(fork_trampoline)
423 movq PCPU(curthread),%rax
424 decl TD_CRITCOUNT(%rax)
427 * cpu_set_fork_handler intercepts this function call to
428 * have this call a non-return function to stay in kernel mode.
430 * initproc has its own fork handler, start_init(), which DOES
433 * %rbx - chaining function (typically fork_return)
434 * %r12 -> %rdi (argument)
435 * frame-> %rsi (trap frame)
437 * void (func:rbx)(arg:rdi, trapframe:rsi)
439 movq %rsp, %rsi /* pass trapframe by reference */
440 movq %r12, %rdi /* arg1 */
441 call *%rbx /* function */
443 /* cut from syscall */
449 * Return via doreti to handle ASTs.
451 * trapframe is at the top of the stack.
457 * To efficiently implement classification of trap and interrupt handlers
458 * for profiling, there must be only trap handlers between the labels btrap
459 * and bintr, and only interrupt handlers between the labels bintr and
460 * eintr. This is implemented (partly) by including files that contain
461 * some of the handlers. Before including the files, set up a normal asm
462 * environment so that the included files doen't need to know that they are
472 #include <x86_64/ia32/ia32_exception.S>
482 #include <x86_64/x86_64/apic_vector.S>
491 #include <x86_64/isa/atpic_vector.S>