bce: Switch to IFQ subqueue functions and use per-TX queue watchdog
[dragonfly.git] / sys / dev / netif / bce / if_bce.c
1 /*-
2  * Copyright (c) 2006-2007 Broadcom Corporation
3  *      David Christensen <davidch@broadcom.com>.  All rights reserved.
4  *
5  * Redistribution and use in source and binary forms, with or without
6  * modification, are permitted provided that the following conditions
7  * are met:
8  *
9  * 1. Redistributions of source code must retain the above copyright
10  *    notice, this list of conditions and the following disclaimer.
11  * 2. Redistributions in binary form must reproduce the above copyright
12  *    notice, this list of conditions and the following disclaimer in the
13  *    documentation and/or other materials provided with the distribution.
14  * 3. Neither the name of Broadcom Corporation nor the name of its contributors
15  *    may be used to endorse or promote products derived from this software
16  *    without specific prior written consent.
17  *
18  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS'
19  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21  * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
22  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
28  * THE POSSIBILITY OF SUCH DAMAGE.
29  *
30  * $FreeBSD: src/sys/dev/bce/if_bce.c,v 1.31 2007/05/16 23:34:11 davidch Exp $
31  */
32
33 /*
34  * The following controllers are supported by this driver:
35  *   BCM5706C A2, A3
36  *   BCM5706S A2, A3
37  *   BCM5708C B1, B2
38  *   BCM5708S B1, B2
39  *   BCM5709C A1, B2, C0
40  *   BCM5716  C0
41  *
42  * The following controllers are not supported by this driver:
43  *   BCM5706C A0, A1
44  *   BCM5706S A0, A1
45  *   BCM5708C A0, B0
46  *   BCM5708S A0, B0
47  *   BCM5709C A0, B0, B1
48  *   BCM5709S A0, A1, B0, B1, B2, C0
49  */
50
51 #include "opt_bce.h"
52 #include "opt_ifpoll.h"
53
54 #include <sys/param.h>
55 #include <sys/bus.h>
56 #include <sys/endian.h>
57 #include <sys/kernel.h>
58 #include <sys/interrupt.h>
59 #include <sys/mbuf.h>
60 #include <sys/malloc.h>
61 #include <sys/queue.h>
62 #include <sys/rman.h>
63 #include <sys/serialize.h>
64 #include <sys/socket.h>
65 #include <sys/sockio.h>
66 #include <sys/sysctl.h>
67
68 #include <netinet/ip.h>
69 #include <netinet/tcp.h>
70
71 #include <net/bpf.h>
72 #include <net/ethernet.h>
73 #include <net/if.h>
74 #include <net/if_arp.h>
75 #include <net/if_dl.h>
76 #include <net/if_media.h>
77 #include <net/if_poll.h>
78 #include <net/if_types.h>
79 #include <net/ifq_var.h>
80 #include <net/vlan/if_vlan_var.h>
81 #include <net/vlan/if_vlan_ether.h>
82
83 #include <dev/netif/mii_layer/mii.h>
84 #include <dev/netif/mii_layer/miivar.h>
85 #include <dev/netif/mii_layer/brgphyreg.h>
86
87 #include <bus/pci/pcireg.h>
88 #include <bus/pci/pcivar.h>
89
90 #include "miibus_if.h"
91
92 #include <dev/netif/bce/if_bcereg.h>
93 #include <dev/netif/bce/if_bcefw.h>
94
95 #define BCE_MSI_CKINTVL         ((10 * hz) / 1000)      /* 10ms */
96
97 /****************************************************************************/
98 /* PCI Device ID Table                                                      */
99 /*                                                                          */
100 /* Used by bce_probe() to identify the devices supported by this driver.    */
101 /****************************************************************************/
102 #define BCE_DEVDESC_MAX         64
103
104 static struct bce_type bce_devs[] = {
105         /* BCM5706C Controllers and OEM boards. */
106         { BRCM_VENDORID, BRCM_DEVICEID_BCM5706,  HP_VENDORID, 0x3101,
107                 "HP NC370T Multifunction Gigabit Server Adapter" },
108         { BRCM_VENDORID, BRCM_DEVICEID_BCM5706,  HP_VENDORID, 0x3106,
109                 "HP NC370i Multifunction Gigabit Server Adapter" },
110         { BRCM_VENDORID, BRCM_DEVICEID_BCM5706,  HP_VENDORID, 0x3070,
111                 "HP NC380T PCIe DP Multifunc Gig Server Adapter" },
112         { BRCM_VENDORID, BRCM_DEVICEID_BCM5706,  HP_VENDORID, 0x1709,
113                 "HP NC371i Multifunction Gigabit Server Adapter" },
114         { BRCM_VENDORID, BRCM_DEVICEID_BCM5706,  PCI_ANY_ID,  PCI_ANY_ID,
115                 "Broadcom NetXtreme II BCM5706 1000Base-T" },
116
117         /* BCM5706S controllers and OEM boards. */
118         { BRCM_VENDORID, BRCM_DEVICEID_BCM5706S, HP_VENDORID, 0x3102,
119                 "HP NC370F Multifunction Gigabit Server Adapter" },
120         { BRCM_VENDORID, BRCM_DEVICEID_BCM5706S, PCI_ANY_ID,  PCI_ANY_ID,
121                 "Broadcom NetXtreme II BCM5706 1000Base-SX" },
122
123         /* BCM5708C controllers and OEM boards. */
124         { BRCM_VENDORID, BRCM_DEVICEID_BCM5708,  HP_VENDORID, 0x7037,
125                 "HP NC373T PCIe Multifunction Gig Server Adapter" },
126         { BRCM_VENDORID, BRCM_DEVICEID_BCM5708,  HP_VENDORID, 0x7038,
127                 "HP NC373i Multifunction Gigabit Server Adapter" },
128         { BRCM_VENDORID, BRCM_DEVICEID_BCM5708,  HP_VENDORID, 0x7045,
129                 "HP NC374m PCIe Multifunction Adapter" },
130         { BRCM_VENDORID, BRCM_DEVICEID_BCM5708,  PCI_ANY_ID,  PCI_ANY_ID,
131                 "Broadcom NetXtreme II BCM5708 1000Base-T" },
132
133         /* BCM5708S controllers and OEM boards. */
134         { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S,  HP_VENDORID, 0x1706,
135                 "HP NC373m Multifunction Gigabit Server Adapter" },
136         { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S,  HP_VENDORID, 0x703b,
137                 "HP NC373i Multifunction Gigabit Server Adapter" },
138         { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S,  HP_VENDORID, 0x703d,
139                 "HP NC373F PCIe Multifunc Giga Server Adapter" },
140         { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S,  PCI_ANY_ID,  PCI_ANY_ID,
141                 "Broadcom NetXtreme II BCM5708S 1000Base-T" },
142
143         /* BCM5709C controllers and OEM boards. */
144         { BRCM_VENDORID, BRCM_DEVICEID_BCM5709,  HP_VENDORID, 0x7055,
145                 "HP NC382i DP Multifunction Gigabit Server Adapter" },
146         { BRCM_VENDORID, BRCM_DEVICEID_BCM5709,  HP_VENDORID, 0x7059,
147                 "HP NC382T PCIe DP Multifunction Gigabit Server Adapter" },
148         { BRCM_VENDORID, BRCM_DEVICEID_BCM5709,  PCI_ANY_ID,  PCI_ANY_ID,
149                 "Broadcom NetXtreme II BCM5709 1000Base-T" },
150
151         /* BCM5709S controllers and OEM boards. */
152         { BRCM_VENDORID, BRCM_DEVICEID_BCM5709S,  HP_VENDORID, 0x171d,
153                 "HP NC382m DP 1GbE Multifunction BL-c Adapter" },
154         { BRCM_VENDORID, BRCM_DEVICEID_BCM5709S,  HP_VENDORID, 0x7056,
155                 "HP NC382i DP Multifunction Gigabit Server Adapter" },
156         { BRCM_VENDORID, BRCM_DEVICEID_BCM5709S,  PCI_ANY_ID,  PCI_ANY_ID,
157                 "Broadcom NetXtreme II BCM5709 1000Base-SX" },
158
159         /* BCM5716 controllers and OEM boards. */
160         { BRCM_VENDORID, BRCM_DEVICEID_BCM5716,   PCI_ANY_ID,  PCI_ANY_ID,
161                 "Broadcom NetXtreme II BCM5716 1000Base-T" },
162
163         { 0, 0, 0, 0, NULL }
164 };
165
166
167 /****************************************************************************/
168 /* Supported Flash NVRAM device data.                                       */
169 /****************************************************************************/
170 static const struct flash_spec flash_table[] =
171 {
172 #define BUFFERED_FLAGS          (BCE_NV_BUFFERED | BCE_NV_TRANSLATE)
173 #define NONBUFFERED_FLAGS       (BCE_NV_WREN)
174
175         /* Slow EEPROM */
176         {0x00000000, 0x40830380, 0x009f0081, 0xa184a053, 0xaf000400,
177          BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
178          SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
179          "EEPROM - slow"},
180         /* Expansion entry 0001 */
181         {0x08000002, 0x4b808201, 0x00050081, 0x03840253, 0xaf020406,
182          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
183          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
184          "Entry 0001"},
185         /* Saifun SA25F010 (non-buffered flash) */
186         /* strap, cfg1, & write1 need updates */
187         {0x04000001, 0x47808201, 0x00050081, 0x03840253, 0xaf020406,
188          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
189          SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*2,
190          "Non-buffered flash (128kB)"},
191         /* Saifun SA25F020 (non-buffered flash) */
192         /* strap, cfg1, & write1 need updates */
193         {0x0c000003, 0x4f808201, 0x00050081, 0x03840253, 0xaf020406,
194          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
195          SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*4,
196          "Non-buffered flash (256kB)"},
197         /* Expansion entry 0100 */
198         {0x11000000, 0x53808201, 0x00050081, 0x03840253, 0xaf020406,
199          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
200          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
201          "Entry 0100"},
202         /* Entry 0101: ST M45PE10 (non-buffered flash, TetonII B0) */
203         {0x19000002, 0x5b808201, 0x000500db, 0x03840253, 0xaf020406,
204          NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
205          ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*2,
206          "Entry 0101: ST M45PE10 (128kB non-bufferred)"},
207         /* Entry 0110: ST M45PE20 (non-buffered flash)*/
208         {0x15000001, 0x57808201, 0x000500db, 0x03840253, 0xaf020406,
209          NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
210          ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*4,
211          "Entry 0110: ST M45PE20 (256kB non-bufferred)"},
212         /* Saifun SA25F005 (non-buffered flash) */
213         /* strap, cfg1, & write1 need updates */
214         {0x1d000003, 0x5f808201, 0x00050081, 0x03840253, 0xaf020406,
215          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
216          SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE,
217          "Non-buffered flash (64kB)"},
218         /* Fast EEPROM */
219         {0x22000000, 0x62808380, 0x009f0081, 0xa184a053, 0xaf000400,
220          BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
221          SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
222          "EEPROM - fast"},
223         /* Expansion entry 1001 */
224         {0x2a000002, 0x6b808201, 0x00050081, 0x03840253, 0xaf020406,
225          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
226          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
227          "Entry 1001"},
228         /* Expansion entry 1010 */
229         {0x26000001, 0x67808201, 0x00050081, 0x03840253, 0xaf020406,
230          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
231          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
232          "Entry 1010"},
233         /* ATMEL AT45DB011B (buffered flash) */
234         {0x2e000003, 0x6e808273, 0x00570081, 0x68848353, 0xaf000400,
235          BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
236          BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE,
237          "Buffered flash (128kB)"},
238         /* Expansion entry 1100 */
239         {0x33000000, 0x73808201, 0x00050081, 0x03840253, 0xaf020406,
240          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
241          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
242          "Entry 1100"},
243         /* Expansion entry 1101 */
244         {0x3b000002, 0x7b808201, 0x00050081, 0x03840253, 0xaf020406,
245          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
246          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
247          "Entry 1101"},
248         /* Ateml Expansion entry 1110 */
249         {0x37000001, 0x76808273, 0x00570081, 0x68848353, 0xaf000400,
250          BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
251          BUFFERED_FLASH_BYTE_ADDR_MASK, 0,
252          "Entry 1110 (Atmel)"},
253         /* ATMEL AT45DB021B (buffered flash) */
254         {0x3f000003, 0x7e808273, 0x00570081, 0x68848353, 0xaf000400,
255          BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
256          BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE*2,
257          "Buffered flash (256kB)"},
258 };
259
260 /*
261  * The BCM5709 controllers transparently handle the
262  * differences between Atmel 264 byte pages and all
263  * flash devices which use 256 byte pages, so no
264  * logical-to-physical mapping is required in the
265  * driver.
266  */
267 static struct flash_spec flash_5709 = {
268         .flags          = BCE_NV_BUFFERED,
269         .page_bits      = BCM5709_FLASH_PAGE_BITS,
270         .page_size      = BCM5709_FLASH_PAGE_SIZE,
271         .addr_mask      = BCM5709_FLASH_BYTE_ADDR_MASK,
272         .total_size     = BUFFERED_FLASH_TOTAL_SIZE * 2,
273         .name           = "5709/5716 buffered flash (256kB)",
274 };
275
276
277 /****************************************************************************/
278 /* DragonFly device entry points.                                           */
279 /****************************************************************************/
280 static int      bce_probe(device_t);
281 static int      bce_attach(device_t);
282 static int      bce_detach(device_t);
283 static void     bce_shutdown(device_t);
284 static int      bce_miibus_read_reg(device_t, int, int);
285 static int      bce_miibus_write_reg(device_t, int, int, int);
286 static void     bce_miibus_statchg(device_t);
287
288 /****************************************************************************/
289 /* BCE Register/Memory Access Routines                                      */
290 /****************************************************************************/
291 static uint32_t bce_reg_rd_ind(struct bce_softc *, uint32_t);
292 static void     bce_reg_wr_ind(struct bce_softc *, uint32_t, uint32_t);
293 static void     bce_shmem_wr(struct bce_softc *, uint32_t, uint32_t);
294 static uint32_t bce_shmem_rd(struct bce_softc *, u32);
295 static void     bce_ctx_wr(struct bce_softc *, uint32_t, uint32_t, uint32_t);
296
297 /****************************************************************************/
298 /* BCE NVRAM Access Routines                                                */
299 /****************************************************************************/
300 static int      bce_acquire_nvram_lock(struct bce_softc *);
301 static int      bce_release_nvram_lock(struct bce_softc *);
302 static void     bce_enable_nvram_access(struct bce_softc *);
303 static void     bce_disable_nvram_access(struct bce_softc *);
304 static int      bce_nvram_read_dword(struct bce_softc *, uint32_t, uint8_t *,
305                     uint32_t);
306 static int      bce_init_nvram(struct bce_softc *);
307 static int      bce_nvram_read(struct bce_softc *, uint32_t, uint8_t *, int);
308 static int      bce_nvram_test(struct bce_softc *);
309
310 /****************************************************************************/
311 /* BCE DMA Allocate/Free Routines                                           */
312 /****************************************************************************/
313 static int      bce_dma_alloc(struct bce_softc *);
314 static void     bce_dma_free(struct bce_softc *);
315 static void     bce_dma_map_addr(void *, bus_dma_segment_t *, int, int);
316
317 /****************************************************************************/
318 /* BCE Firmware Synchronization and Load                                    */
319 /****************************************************************************/
320 static int      bce_fw_sync(struct bce_softc *, uint32_t);
321 static void     bce_load_rv2p_fw(struct bce_softc *, uint32_t *,
322                     uint32_t, uint32_t);
323 static void     bce_load_cpu_fw(struct bce_softc *, struct cpu_reg *,
324                     struct fw_info *);
325 static void     bce_start_cpu(struct bce_softc *, struct cpu_reg *);
326 static void     bce_halt_cpu(struct bce_softc *, struct cpu_reg *);
327 static void     bce_start_rxp_cpu(struct bce_softc *);
328 static void     bce_init_rxp_cpu(struct bce_softc *);
329 static void     bce_init_txp_cpu(struct bce_softc *);
330 static void     bce_init_tpat_cpu(struct bce_softc *);
331 static void     bce_init_cp_cpu(struct bce_softc *);
332 static void     bce_init_com_cpu(struct bce_softc *);
333 static void     bce_init_cpus(struct bce_softc *);
334
335 static void     bce_stop(struct bce_softc *);
336 static int      bce_reset(struct bce_softc *, uint32_t);
337 static int      bce_chipinit(struct bce_softc *);
338 static int      bce_blockinit(struct bce_softc *);
339 static void     bce_probe_pci_caps(struct bce_softc *);
340 static void     bce_print_adapter_info(struct bce_softc *);
341 static void     bce_get_media(struct bce_softc *);
342 static void     bce_mgmt_init(struct bce_softc *);
343 static int      bce_init_ctx(struct bce_softc *);
344 static void     bce_get_mac_addr(struct bce_softc *);
345 static void     bce_set_mac_addr(struct bce_softc *);
346 static void     bce_set_rx_mode(struct bce_softc *);
347 static void     bce_coal_change(struct bce_softc *);
348 static void     bce_setup_serialize(struct bce_softc *);
349 static void     bce_serialize_skipmain(struct bce_softc *);
350 static void     bce_deserialize_skipmain(struct bce_softc *);
351
352 static int      bce_create_tx_ring(struct bce_tx_ring *);
353 static void     bce_destroy_tx_ring(struct bce_tx_ring *);
354 static void     bce_init_tx_context(struct bce_tx_ring *);
355 static int      bce_init_tx_chain(struct bce_tx_ring *);
356 static void     bce_free_tx_chain(struct bce_tx_ring *);
357 static void     bce_xmit(struct bce_tx_ring *);
358 static int      bce_encap(struct bce_tx_ring *, struct mbuf **, int *);
359 static int      bce_tso_setup(struct bce_tx_ring *, struct mbuf **,
360                     uint16_t *, uint16_t *);
361
362 static int      bce_create_rx_ring(struct bce_rx_ring *);
363 static void     bce_destroy_rx_ring(struct bce_rx_ring *);
364 static void     bce_init_rx_context(struct bce_rx_ring *);
365 static int      bce_init_rx_chain(struct bce_rx_ring *);
366 static void     bce_free_rx_chain(struct bce_rx_ring *);
367 static int      bce_newbuf_std(struct bce_rx_ring *, uint16_t *, uint16_t *,
368                     uint32_t *, int);
369 static void     bce_setup_rxdesc_std(struct bce_rx_ring *, uint16_t,
370                     uint32_t *);
371
372 static void     bce_start(struct ifnet *, struct ifaltq_subque *);
373 static int      bce_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
374 static void     bce_watchdog(struct ifaltq_subque *);
375 static int      bce_ifmedia_upd(struct ifnet *);
376 static void     bce_ifmedia_sts(struct ifnet *, struct ifmediareq *);
377 static void     bce_init(void *);
378 #ifdef IFPOLL_ENABLE
379 static void     bce_npoll(struct ifnet *, struct ifpoll_info *);
380 static void     bce_npoll_rx(struct ifnet *, void *, int);
381 static void     bce_npoll_tx(struct ifnet *, void *, int);
382 static void     bce_npoll_status(struct ifnet *);
383 #endif
384 static void     bce_serialize(struct ifnet *, enum ifnet_serialize);
385 static void     bce_deserialize(struct ifnet *, enum ifnet_serialize);
386 static int      bce_tryserialize(struct ifnet *, enum ifnet_serialize);
387 #ifdef INVARIANTS
388 static void     bce_serialize_assert(struct ifnet *, enum ifnet_serialize,
389                     boolean_t);
390 #endif
391
392 static void     bce_intr(struct bce_softc *);
393 static void     bce_intr_legacy(void *);
394 static void     bce_intr_msi(void *);
395 static void     bce_intr_msi_oneshot(void *);
396 static void     bce_tx_intr(struct bce_tx_ring *, uint16_t);
397 static void     bce_rx_intr(struct bce_rx_ring *, int, uint16_t);
398 static void     bce_phy_intr(struct bce_softc *);
399 static void     bce_disable_intr(struct bce_softc *);
400 static void     bce_enable_intr(struct bce_softc *);
401 static void     bce_reenable_intr(struct bce_softc *);
402 static void     bce_check_msi(void *);
403
404 static void     bce_stats_update(struct bce_softc *);
405 static void     bce_tick(void *);
406 static void     bce_tick_serialized(struct bce_softc *);
407 static void     bce_pulse(void *);
408
409 static void     bce_add_sysctls(struct bce_softc *);
410 static int      bce_sysctl_tx_bds_int(SYSCTL_HANDLER_ARGS);
411 static int      bce_sysctl_tx_bds(SYSCTL_HANDLER_ARGS);
412 static int      bce_sysctl_tx_ticks_int(SYSCTL_HANDLER_ARGS);
413 static int      bce_sysctl_tx_ticks(SYSCTL_HANDLER_ARGS);
414 static int      bce_sysctl_rx_bds_int(SYSCTL_HANDLER_ARGS);
415 static int      bce_sysctl_rx_bds(SYSCTL_HANDLER_ARGS);
416 static int      bce_sysctl_rx_ticks_int(SYSCTL_HANDLER_ARGS);
417 static int      bce_sysctl_rx_ticks(SYSCTL_HANDLER_ARGS);
418 #ifdef IFPOLL_ENABLE
419 static int      bce_sysctl_npoll_offset(SYSCTL_HANDLER_ARGS);
420 #endif
421 static int      bce_sysctl_coal_change(SYSCTL_HANDLER_ARGS,
422                     uint32_t *, uint32_t);
423
424 /*
425  * NOTE:
426  * Don't set bce_tx_ticks_int/bce_tx_ticks to 1023.  Linux's bnx2
427  * takes 1023 as the TX ticks limit.  However, using 1023 will
428  * cause 5708(B2) to generate extra interrupts (~2000/s) even when
429  * there is _no_ network activity on the NIC.
430  */
431 static uint32_t bce_tx_bds_int = 255;           /* bcm: 20 */
432 static uint32_t bce_tx_bds = 255;               /* bcm: 20 */
433 static uint32_t bce_tx_ticks_int = 1022;        /* bcm: 80 */
434 static uint32_t bce_tx_ticks = 1022;            /* bcm: 80 */
435 static uint32_t bce_rx_bds_int = 128;           /* bcm: 6 */
436 static uint32_t bce_rx_bds = 0;                 /* bcm: 6 */
437 static uint32_t bce_rx_ticks_int = 150;         /* bcm: 18 */
438 static uint32_t bce_rx_ticks = 150;             /* bcm: 18 */
439
440 static int      bce_tx_wreg = 8;
441
442 static int      bce_msi_enable = 1;
443
444 static int      bce_rx_pages = RX_PAGES_DEFAULT;
445 static int      bce_tx_pages = TX_PAGES_DEFAULT;
446
447 TUNABLE_INT("hw.bce.tx_bds_int", &bce_tx_bds_int);
448 TUNABLE_INT("hw.bce.tx_bds", &bce_tx_bds);
449 TUNABLE_INT("hw.bce.tx_ticks_int", &bce_tx_ticks_int);
450 TUNABLE_INT("hw.bce.tx_ticks", &bce_tx_ticks);
451 TUNABLE_INT("hw.bce.rx_bds_int", &bce_rx_bds_int);
452 TUNABLE_INT("hw.bce.rx_bds", &bce_rx_bds);
453 TUNABLE_INT("hw.bce.rx_ticks_int", &bce_rx_ticks_int);
454 TUNABLE_INT("hw.bce.rx_ticks", &bce_rx_ticks);
455 TUNABLE_INT("hw.bce.msi.enable", &bce_msi_enable);
456 TUNABLE_INT("hw.bce.rx_pages", &bce_rx_pages);
457 TUNABLE_INT("hw.bce.tx_pages", &bce_tx_pages);
458 TUNABLE_INT("hw.bce.tx_wreg", &bce_tx_wreg);
459
460 /****************************************************************************/
461 /* DragonFly device dispatch table.                                         */
462 /****************************************************************************/
463 static device_method_t bce_methods[] = {
464         /* Device interface */
465         DEVMETHOD(device_probe,         bce_probe),
466         DEVMETHOD(device_attach,        bce_attach),
467         DEVMETHOD(device_detach,        bce_detach),
468         DEVMETHOD(device_shutdown,      bce_shutdown),
469
470         /* bus interface */
471         DEVMETHOD(bus_print_child,      bus_generic_print_child),
472         DEVMETHOD(bus_driver_added,     bus_generic_driver_added),
473
474         /* MII interface */
475         DEVMETHOD(miibus_readreg,       bce_miibus_read_reg),
476         DEVMETHOD(miibus_writereg,      bce_miibus_write_reg),
477         DEVMETHOD(miibus_statchg,       bce_miibus_statchg),
478
479         DEVMETHOD_END
480 };
481
482 static driver_t bce_driver = {
483         "bce",
484         bce_methods,
485         sizeof(struct bce_softc)
486 };
487
488 static devclass_t bce_devclass;
489
490
491 DECLARE_DUMMY_MODULE(if_bce);
492 MODULE_DEPEND(bce, miibus, 1, 1, 1);
493 DRIVER_MODULE(if_bce, pci, bce_driver, bce_devclass, NULL, NULL);
494 DRIVER_MODULE(miibus, bce, miibus_driver, miibus_devclass, NULL, NULL);
495
496
497 /****************************************************************************/
498 /* Device probe function.                                                   */
499 /*                                                                          */
500 /* Compares the device to the driver's list of supported devices and        */
501 /* reports back to the OS whether this is the right driver for the device.  */
502 /*                                                                          */
503 /* Returns:                                                                 */
504 /*   BUS_PROBE_DEFAULT on success, positive value on failure.               */
505 /****************************************************************************/
506 static int
507 bce_probe(device_t dev)
508 {
509         struct bce_type *t;
510         uint16_t vid, did, svid, sdid;
511
512         /* Get the data for the device to be probed. */
513         vid  = pci_get_vendor(dev);
514         did  = pci_get_device(dev);
515         svid = pci_get_subvendor(dev);
516         sdid = pci_get_subdevice(dev);
517
518         /* Look through the list of known devices for a match. */
519         for (t = bce_devs; t->bce_name != NULL; ++t) {
520                 if (vid == t->bce_vid && did == t->bce_did && 
521                     (svid == t->bce_svid || t->bce_svid == PCI_ANY_ID) &&
522                     (sdid == t->bce_sdid || t->bce_sdid == PCI_ANY_ID)) {
523                         uint32_t revid = pci_read_config(dev, PCIR_REVID, 4);
524                         char *descbuf;
525
526                         descbuf = kmalloc(BCE_DEVDESC_MAX, M_TEMP, M_WAITOK);
527
528                         /* Print out the device identity. */
529                         ksnprintf(descbuf, BCE_DEVDESC_MAX, "%s (%c%d)",
530                                   t->bce_name,
531                                   ((revid & 0xf0) >> 4) + 'A', revid & 0xf);
532
533                         device_set_desc_copy(dev, descbuf);
534                         kfree(descbuf, M_TEMP);
535                         return 0;
536                 }
537         }
538         return ENXIO;
539 }
540
541
542 /****************************************************************************/
543 /* PCI Capabilities Probe Function.                                         */
544 /*                                                                          */
545 /* Walks the PCI capabiites list for the device to find what features are   */
546 /* supported.                                                               */
547 /*                                                                          */
548 /* Returns:                                                                 */
549 /*   None.                                                                  */
550 /****************************************************************************/
551 static void
552 bce_print_adapter_info(struct bce_softc *sc)
553 {
554         device_printf(sc->bce_dev, "ASIC (0x%08X); ", sc->bce_chipid);
555
556         kprintf("Rev (%c%d); ", ((BCE_CHIP_ID(sc) & 0xf000) >> 12) + 'A',
557                 ((BCE_CHIP_ID(sc) & 0x0ff0) >> 4));
558
559         /* Bus info. */
560         if (sc->bce_flags & BCE_PCIE_FLAG) {
561                 kprintf("Bus (PCIe x%d, ", sc->link_width);
562                 switch (sc->link_speed) {
563                 case 1:
564                         kprintf("2.5Gbps); ");
565                         break;
566                 case 2:
567                         kprintf("5Gbps); ");
568                         break;
569                 default:
570                         kprintf("Unknown link speed); ");
571                         break;
572                 }
573         } else {
574                 kprintf("Bus (PCI%s, %s, %dMHz); ",
575                     ((sc->bce_flags & BCE_PCIX_FLAG) ? "-X" : ""),
576                     ((sc->bce_flags & BCE_PCI_32BIT_FLAG) ? "32-bit" : "64-bit"),
577                     sc->bus_speed_mhz);
578         }
579
580         /* Firmware version and device features. */
581         kprintf("B/C (%s)", sc->bce_bc_ver);
582
583         if ((sc->bce_flags & BCE_MFW_ENABLE_FLAG) ||
584             (sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG)) {
585                 kprintf("; Flags(");
586                 if (sc->bce_flags & BCE_MFW_ENABLE_FLAG)
587                         kprintf("MFW[%s]", sc->bce_mfw_ver);
588                 if (sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG)
589                         kprintf(" 2.5G");
590                 kprintf(")");
591         }
592         kprintf("\n");
593 }
594
595
596 /****************************************************************************/
597 /* PCI Capabilities Probe Function.                                         */
598 /*                                                                          */
599 /* Walks the PCI capabiites list for the device to find what features are   */
600 /* supported.                                                               */
601 /*                                                                          */
602 /* Returns:                                                                 */
603 /*   None.                                                                  */
604 /****************************************************************************/
605 static void
606 bce_probe_pci_caps(struct bce_softc *sc)
607 {
608         device_t dev = sc->bce_dev;
609         uint8_t ptr;
610
611         if (pci_is_pcix(dev))
612                 sc->bce_cap_flags |= BCE_PCIX_CAPABLE_FLAG;
613
614         ptr = pci_get_pciecap_ptr(dev);
615         if (ptr) {
616                 uint16_t link_status = pci_read_config(dev, ptr + 0x12, 2);
617
618                 sc->link_speed = link_status & 0xf;
619                 sc->link_width = (link_status >> 4) & 0x3f;
620                 sc->bce_cap_flags |= BCE_PCIE_CAPABLE_FLAG;
621                 sc->bce_flags |= BCE_PCIE_FLAG;
622         }
623 }
624
625
626 /****************************************************************************/
627 /* Device attach function.                                                  */
628 /*                                                                          */
629 /* Allocates device resources, performs secondary chip identification,      */
630 /* resets and initializes the hardware, and initializes driver instance     */
631 /* variables.                                                               */
632 /*                                                                          */
633 /* Returns:                                                                 */
634 /*   0 on success, positive value on failure.                               */
635 /****************************************************************************/
636 static int
637 bce_attach(device_t dev)
638 {
639         struct bce_softc *sc = device_get_softc(dev);
640         struct ifnet *ifp = &sc->arpcom.ac_if;
641         uint32_t val;
642         u_int irq_flags;
643         void (*irq_handle)(void *);
644         int rid, rc = 0;
645         int i, j;
646         struct mii_probe_args mii_args;
647         uintptr_t mii_priv = 0;
648 #ifdef IFPOLL_ENABLE
649         int offset, offset_def;
650 #endif
651
652         sc->bce_dev = dev;
653         if_initname(ifp, device_get_name(dev), device_get_unit(dev));
654
655         lwkt_serialize_init(&sc->main_serialize);
656
657         pci_enable_busmaster(dev);
658
659         bce_probe_pci_caps(sc);
660
661         /* Allocate PCI memory resources. */
662         rid = PCIR_BAR(0);
663         sc->bce_res_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
664                                                  RF_ACTIVE | PCI_RF_DENSE);
665         if (sc->bce_res_mem == NULL) {
666                 device_printf(dev, "PCI memory allocation failed\n");
667                 return ENXIO;
668         }
669         sc->bce_btag = rman_get_bustag(sc->bce_res_mem);
670         sc->bce_bhandle = rman_get_bushandle(sc->bce_res_mem);
671
672         /*
673          * Configure byte swap and enable indirect register access.
674          * Rely on CPU to do target byte swapping on big endian systems.
675          * Access to registers outside of PCI configurtion space are not
676          * valid until this is done.
677          */
678         pci_write_config(dev, BCE_PCICFG_MISC_CONFIG,
679                          BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
680                          BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP, 4);
681
682         /* Save ASIC revsion info. */
683         sc->bce_chipid =  REG_RD(sc, BCE_MISC_ID);
684
685         /* Weed out any non-production controller revisions. */
686         switch (BCE_CHIP_ID(sc)) {
687         case BCE_CHIP_ID_5706_A0:
688         case BCE_CHIP_ID_5706_A1:
689         case BCE_CHIP_ID_5708_A0:
690         case BCE_CHIP_ID_5708_B0:
691         case BCE_CHIP_ID_5709_A0:
692         case BCE_CHIP_ID_5709_B0:
693         case BCE_CHIP_ID_5709_B1:
694 #ifdef foo
695         /* 5709C B2 seems to work fine */
696         case BCE_CHIP_ID_5709_B2:
697 #endif
698                 device_printf(dev, "Unsupported chip id 0x%08x!\n",
699                               BCE_CHIP_ID(sc));
700                 rc = ENODEV;
701                 goto fail;
702         }
703
704         mii_priv |= BRGPHY_FLAG_WIRESPEED;
705         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
706                 if (BCE_CHIP_REV(sc) == BCE_CHIP_REV_Ax ||
707                     BCE_CHIP_REV(sc) == BCE_CHIP_REV_Bx)
708                         mii_priv |= BRGPHY_FLAG_NO_EARLYDAC;
709         } else {
710                 mii_priv |= BRGPHY_FLAG_BER_BUG;
711         }
712
713         /*
714          * Find the base address for shared memory access.
715          * Newer versions of bootcode use a signature and offset
716          * while older versions use a fixed address.
717          */
718         val = REG_RD_IND(sc, BCE_SHM_HDR_SIGNATURE);
719         if ((val & BCE_SHM_HDR_SIGNATURE_SIG_MASK) ==
720             BCE_SHM_HDR_SIGNATURE_SIG) {
721                 /* Multi-port devices use different offsets in shared memory. */
722                 sc->bce_shmem_base = REG_RD_IND(sc,
723                     BCE_SHM_HDR_ADDR_0 + (pci_get_function(sc->bce_dev) << 2));
724         } else {
725                 sc->bce_shmem_base = HOST_VIEW_SHMEM_BASE;
726         }
727
728         /* Fetch the bootcode revision. */
729         val = bce_shmem_rd(sc, BCE_DEV_INFO_BC_REV);
730         for (i = 0, j = 0; i < 3; i++) {
731                 uint8_t num;
732                 int k, skip0;
733
734                 num = (uint8_t)(val >> (24 - (i * 8)));
735                 for (k = 100, skip0 = 1; k >= 1; num %= k, k /= 10) {
736                         if (num >= k || !skip0 || k == 1) {
737                                 sc->bce_bc_ver[j++] = (num / k) + '0';
738                                 skip0 = 0;
739                         }
740                 }
741                 if (i != 2)
742                         sc->bce_bc_ver[j++] = '.';
743         }
744
745         /* Check if any management firwmare is running. */
746         val = bce_shmem_rd(sc, BCE_PORT_FEATURE);
747         if (val & BCE_PORT_FEATURE_ASF_ENABLED) {
748                 sc->bce_flags |= BCE_MFW_ENABLE_FLAG;
749
750                 /* Allow time for firmware to enter the running state. */
751                 for (i = 0; i < 30; i++) {
752                         val = bce_shmem_rd(sc, BCE_BC_STATE_CONDITION);
753                         if (val & BCE_CONDITION_MFW_RUN_MASK)
754                                 break;
755                         DELAY(10000);
756                 }
757         }
758
759         /* Check the current bootcode state. */
760         val = bce_shmem_rd(sc, BCE_BC_STATE_CONDITION) &
761             BCE_CONDITION_MFW_RUN_MASK;
762         if (val != BCE_CONDITION_MFW_RUN_UNKNOWN &&
763             val != BCE_CONDITION_MFW_RUN_NONE) {
764                 uint32_t addr = bce_shmem_rd(sc, BCE_MFW_VER_PTR);
765
766                 for (i = 0, j = 0; j < 3; j++) {
767                         val = bce_reg_rd_ind(sc, addr + j * 4);
768                         val = bswap32(val);
769                         memcpy(&sc->bce_mfw_ver[i], &val, 4);
770                         i += 4;
771                 }
772         }
773
774         /* Get PCI bus information (speed and type). */
775         val = REG_RD(sc, BCE_PCICFG_MISC_STATUS);
776         if (val & BCE_PCICFG_MISC_STATUS_PCIX_DET) {
777                 uint32_t clkreg;
778
779                 sc->bce_flags |= BCE_PCIX_FLAG;
780
781                 clkreg = REG_RD(sc, BCE_PCICFG_PCI_CLOCK_CONTROL_BITS) &
782                          BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET;
783                 switch (clkreg) {
784                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ:
785                         sc->bus_speed_mhz = 133;
786                         break;
787
788                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ:
789                         sc->bus_speed_mhz = 100;
790                         break;
791
792                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ:
793                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ:
794                         sc->bus_speed_mhz = 66;
795                         break;
796
797                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ:
798                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ:
799                         sc->bus_speed_mhz = 50;
800                         break;
801
802                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW:
803                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ:
804                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ:
805                         sc->bus_speed_mhz = 33;
806                         break;
807                 }
808         } else {
809                 if (val & BCE_PCICFG_MISC_STATUS_M66EN)
810                         sc->bus_speed_mhz = 66;
811                 else
812                         sc->bus_speed_mhz = 33;
813         }
814
815         if (val & BCE_PCICFG_MISC_STATUS_32BIT_DET)
816                 sc->bce_flags |= BCE_PCI_32BIT_FLAG;
817
818         /* Reset the controller. */
819         rc = bce_reset(sc, BCE_DRV_MSG_CODE_RESET);
820         if (rc != 0)
821                 goto fail;
822
823         /* Initialize the controller. */
824         rc = bce_chipinit(sc);
825         if (rc != 0) {
826                 device_printf(dev, "Controller initialization failed!\n");
827                 goto fail;
828         }
829
830         /* Perform NVRAM test. */
831         rc = bce_nvram_test(sc);
832         if (rc != 0) {
833                 device_printf(dev, "NVRAM test failed!\n");
834                 goto fail;
835         }
836
837         /* Fetch the permanent Ethernet MAC address. */
838         bce_get_mac_addr(sc);
839
840         /*
841          * Trip points control how many BDs
842          * should be ready before generating an
843          * interrupt while ticks control how long
844          * a BD can sit in the chain before
845          * generating an interrupt.  Set the default 
846          * values for the RX and TX rings.
847          */
848
849 #ifdef BCE_DRBUG
850         /* Force more frequent interrupts. */
851         sc->bce_tx_quick_cons_trip_int = 1;
852         sc->bce_tx_quick_cons_trip     = 1;
853         sc->bce_tx_ticks_int           = 0;
854         sc->bce_tx_ticks               = 0;
855
856         sc->bce_rx_quick_cons_trip_int = 1;
857         sc->bce_rx_quick_cons_trip     = 1;
858         sc->bce_rx_ticks_int           = 0;
859         sc->bce_rx_ticks               = 0;
860 #else
861         sc->bce_tx_quick_cons_trip_int = bce_tx_bds_int;
862         sc->bce_tx_quick_cons_trip     = bce_tx_bds;
863         sc->bce_tx_ticks_int           = bce_tx_ticks_int;
864         sc->bce_tx_ticks               = bce_tx_ticks;
865
866         sc->bce_rx_quick_cons_trip_int = bce_rx_bds_int;
867         sc->bce_rx_quick_cons_trip     = bce_rx_bds;
868         sc->bce_rx_ticks_int           = bce_rx_ticks_int;
869         sc->bce_rx_ticks               = bce_rx_ticks;
870 #endif
871
872         /* Update statistics once every second. */
873         sc->bce_stats_ticks = 1000000 & 0xffff00;
874
875         /* Find the media type for the adapter. */
876         bce_get_media(sc);
877
878         /* Find out RX/TX ring count */
879         sc->ring_cnt = 1; /* XXX */
880
881         /* Allocate DMA memory resources. */
882         rc = bce_dma_alloc(sc);
883         if (rc != 0) {
884                 device_printf(dev, "DMA resource allocation failed!\n");
885                 goto fail;
886         }
887
888 #ifdef IFPOLL_ENABLE
889         /*
890          * NPOLLING RX/TX CPU offset
891          */
892         if (sc->ring_cnt == ncpus2) {
893                 offset = 0;
894         } else {
895                 offset_def = (sc->ring_cnt * device_get_unit(dev)) % ncpus2;
896                 offset = device_getenv_int(dev, "npoll.offset", offset_def);
897                 if (offset >= ncpus2 ||
898                     offset % sc->ring_cnt != 0) {
899                         device_printf(dev, "invalid npoll.offset %d, use %d\n",
900                             offset, offset_def);
901                         offset = offset_def;
902                 }
903         }
904         sc->npoll_ofs = offset;
905 #endif
906
907         /* Allocate PCI IRQ resources. */
908         sc->bce_irq_type = pci_alloc_1intr(dev, bce_msi_enable,
909             &sc->bce_irq_rid, &irq_flags);
910
911         sc->bce_res_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ,
912             &sc->bce_irq_rid, irq_flags);
913         if (sc->bce_res_irq == NULL) {
914                 device_printf(dev, "PCI map interrupt failed\n");
915                 rc = ENXIO;
916                 goto fail;
917         }
918
919         if (sc->bce_irq_type == PCI_INTR_TYPE_LEGACY) {
920                 irq_handle = bce_intr_legacy;
921         } else if (sc->bce_irq_type == PCI_INTR_TYPE_MSI) {
922                 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
923                         irq_handle = bce_intr_msi_oneshot;
924                         sc->bce_flags |= BCE_ONESHOT_MSI_FLAG;
925                 } else {
926                         irq_handle = bce_intr_msi;
927                         sc->bce_flags |= BCE_CHECK_MSI_FLAG;
928                 }
929         } else {
930                 panic("%s: unsupported intr type %d",
931                     device_get_nameunit(dev), sc->bce_irq_type);
932         }
933
934         /* Setup serializer */
935         bce_setup_serialize(sc);
936
937         /* Initialize the ifnet interface. */
938         ifp->if_softc = sc;
939         ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
940         ifp->if_ioctl = bce_ioctl;
941         ifp->if_start = bce_start;
942         ifp->if_init = bce_init;
943         ifp->if_serialize = bce_serialize;
944         ifp->if_deserialize = bce_deserialize;
945         ifp->if_tryserialize = bce_tryserialize;
946 #ifdef INVARIANTS
947         ifp->if_serialize_assert = bce_serialize_assert;
948 #endif
949 #ifdef IFPOLL_ENABLE
950         ifp->if_npoll = bce_npoll;
951 #endif
952
953         ifp->if_mtu = ETHERMTU;
954         ifp->if_hwassist = BCE_CSUM_FEATURES | CSUM_TSO;
955         ifp->if_capabilities = BCE_IF_CAPABILITIES;
956         ifp->if_capenable = ifp->if_capabilities;
957
958         if (sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG)
959                 ifp->if_baudrate = IF_Gbps(2.5);
960         else
961                 ifp->if_baudrate = IF_Gbps(1);
962
963         ifq_set_maxlen(&ifp->if_snd, USABLE_TX_BD(&sc->tx_rings[0]));
964         ifq_set_ready(&ifp->if_snd);
965         ifq_set_subq_cnt(&ifp->if_snd, sc->ring_cnt);
966
967         /*
968          * Look for our PHY.
969          */
970         mii_probe_args_init(&mii_args, bce_ifmedia_upd, bce_ifmedia_sts);
971         mii_args.mii_probemask = 1 << sc->bce_phy_addr;
972         mii_args.mii_privtag = MII_PRIVTAG_BRGPHY;
973         mii_args.mii_priv = mii_priv;
974
975         rc = mii_probe(dev, &sc->bce_miibus, &mii_args);
976         if (rc != 0) {
977                 device_printf(dev, "PHY probe failed!\n");
978                 goto fail;
979         }
980
981         /* Attach to the Ethernet interface list. */
982         ether_ifattach(ifp, sc->eaddr, NULL);
983
984         callout_init_mp(&sc->bce_tick_callout);
985         callout_init_mp(&sc->bce_pulse_callout);
986         callout_init_mp(&sc->bce_ckmsi_callout);
987
988         /* Hookup IRQ last. */
989         rc = bus_setup_intr(dev, sc->bce_res_irq, INTR_MPSAFE, irq_handle, sc,
990             &sc->bce_intrhand, &sc->main_serialize);
991         if (rc != 0) {
992                 device_printf(dev, "Failed to setup IRQ!\n");
993                 ether_ifdetach(ifp);
994                 goto fail;
995         }
996
997         sc->bce_intr_cpuid = rman_get_cpuid(sc->bce_res_irq);
998
999         for (i = 0; i < sc->ring_cnt; ++i) {
1000                 struct ifaltq_subque *ifsq = ifq_get_subq(&ifp->if_snd, i);
1001                 struct bce_tx_ring *txr = &sc->tx_rings[i];
1002
1003                 ifsq_set_cpuid(ifsq, sc->bce_intr_cpuid); /* XXX */
1004                 ifsq_set_priv(ifsq, txr);
1005                 txr->ifsq = ifsq;
1006
1007                 ifsq_watchdog_init(&txr->tx_watchdog, ifsq, bce_watchdog);
1008         }
1009
1010         /* Add the supported sysctls to the kernel. */
1011         bce_add_sysctls(sc);
1012
1013         /*
1014          * The chip reset earlier notified the bootcode that
1015          * a driver is present.  We now need to start our pulse
1016          * routine so that the bootcode is reminded that we're
1017          * still running.
1018          */
1019         bce_pulse(sc);
1020
1021         /* Get the firmware running so IPMI still works */
1022         bce_mgmt_init(sc);
1023
1024         if (bootverbose)
1025                 bce_print_adapter_info(sc);
1026
1027         return 0;
1028 fail:
1029         bce_detach(dev);
1030         return(rc);
1031 }
1032
1033
1034 /****************************************************************************/
1035 /* Device detach function.                                                  */
1036 /*                                                                          */
1037 /* Stops the controller, resets the controller, and releases resources.     */
1038 /*                                                                          */
1039 /* Returns:                                                                 */
1040 /*   0 on success, positive value on failure.                               */
1041 /****************************************************************************/
1042 static int
1043 bce_detach(device_t dev)
1044 {
1045         struct bce_softc *sc = device_get_softc(dev);
1046
1047         if (device_is_attached(dev)) {
1048                 struct ifnet *ifp = &sc->arpcom.ac_if;
1049                 uint32_t msg;
1050
1051                 ifnet_serialize_all(ifp);
1052
1053                 /* Stop and reset the controller. */
1054                 callout_stop(&sc->bce_pulse_callout);
1055                 bce_stop(sc);
1056                 if (sc->bce_flags & BCE_NO_WOL_FLAG)
1057                         msg = BCE_DRV_MSG_CODE_UNLOAD_LNK_DN;
1058                 else
1059                         msg = BCE_DRV_MSG_CODE_UNLOAD;
1060                 bce_reset(sc, msg);
1061                 bus_teardown_intr(dev, sc->bce_res_irq, sc->bce_intrhand);
1062
1063                 ifnet_deserialize_all(ifp);
1064
1065                 ether_ifdetach(ifp);
1066         }
1067
1068         /* If we have a child device on the MII bus remove it too. */
1069         if (sc->bce_miibus)
1070                 device_delete_child(dev, sc->bce_miibus);
1071         bus_generic_detach(dev);
1072
1073         if (sc->bce_res_irq != NULL) {
1074                 bus_release_resource(dev, SYS_RES_IRQ, sc->bce_irq_rid,
1075                     sc->bce_res_irq);
1076         }
1077
1078         if (sc->bce_irq_type == PCI_INTR_TYPE_MSI)
1079                 pci_release_msi(dev);
1080
1081         if (sc->bce_res_mem != NULL) {
1082                 bus_release_resource(dev, SYS_RES_MEMORY, PCIR_BAR(0),
1083                                      sc->bce_res_mem);
1084         }
1085
1086         bce_dma_free(sc);
1087
1088         if (sc->bce_sysctl_tree != NULL)
1089                 sysctl_ctx_free(&sc->bce_sysctl_ctx);
1090
1091         return 0;
1092 }
1093
1094
1095 /****************************************************************************/
1096 /* Device shutdown function.                                                */
1097 /*                                                                          */
1098 /* Stops and resets the controller.                                         */
1099 /*                                                                          */
1100 /* Returns:                                                                 */
1101 /*   Nothing                                                                */
1102 /****************************************************************************/
1103 static void
1104 bce_shutdown(device_t dev)
1105 {
1106         struct bce_softc *sc = device_get_softc(dev);
1107         struct ifnet *ifp = &sc->arpcom.ac_if;
1108         uint32_t msg;
1109
1110         ifnet_serialize_all(ifp);
1111
1112         bce_stop(sc);
1113         if (sc->bce_flags & BCE_NO_WOL_FLAG)
1114                 msg = BCE_DRV_MSG_CODE_UNLOAD_LNK_DN;
1115         else
1116                 msg = BCE_DRV_MSG_CODE_UNLOAD;
1117         bce_reset(sc, msg);
1118
1119         ifnet_deserialize_all(ifp);
1120 }
1121
1122
1123 /****************************************************************************/
1124 /* Indirect register read.                                                  */
1125 /*                                                                          */
1126 /* Reads NetXtreme II registers using an index/data register pair in PCI    */
1127 /* configuration space.  Using this mechanism avoids issues with posted     */
1128 /* reads but is much slower than memory-mapped I/O.                         */
1129 /*                                                                          */
1130 /* Returns:                                                                 */
1131 /*   The value of the register.                                             */
1132 /****************************************************************************/
1133 static uint32_t
1134 bce_reg_rd_ind(struct bce_softc *sc, uint32_t offset)
1135 {
1136         device_t dev = sc->bce_dev;
1137
1138         pci_write_config(dev, BCE_PCICFG_REG_WINDOW_ADDRESS, offset, 4);
1139         return pci_read_config(dev, BCE_PCICFG_REG_WINDOW, 4);
1140 }
1141
1142
1143 /****************************************************************************/
1144 /* Indirect register write.                                                 */
1145 /*                                                                          */
1146 /* Writes NetXtreme II registers using an index/data register pair in PCI   */
1147 /* configuration space.  Using this mechanism avoids issues with posted     */
1148 /* writes but is muchh slower than memory-mapped I/O.                       */
1149 /*                                                                          */
1150 /* Returns:                                                                 */
1151 /*   Nothing.                                                               */
1152 /****************************************************************************/
1153 static void
1154 bce_reg_wr_ind(struct bce_softc *sc, uint32_t offset, uint32_t val)
1155 {
1156         device_t dev = sc->bce_dev;
1157
1158         pci_write_config(dev, BCE_PCICFG_REG_WINDOW_ADDRESS, offset, 4);
1159         pci_write_config(dev, BCE_PCICFG_REG_WINDOW, val, 4);
1160 }
1161
1162
1163 /****************************************************************************/
1164 /* Shared memory write.                                                     */
1165 /*                                                                          */
1166 /* Writes NetXtreme II shared memory region.                                */
1167 /*                                                                          */
1168 /* Returns:                                                                 */
1169 /*   Nothing.                                                               */
1170 /****************************************************************************/
1171 static void
1172 bce_shmem_wr(struct bce_softc *sc, uint32_t offset, uint32_t val)
1173 {
1174         bce_reg_wr_ind(sc, sc->bce_shmem_base + offset, val);
1175 }
1176
1177
1178 /****************************************************************************/
1179 /* Shared memory read.                                                      */
1180 /*                                                                          */
1181 /* Reads NetXtreme II shared memory region.                                 */
1182 /*                                                                          */
1183 /* Returns:                                                                 */
1184 /*   The 32 bit value read.                                                 */
1185 /****************************************************************************/
1186 static u32
1187 bce_shmem_rd(struct bce_softc *sc, uint32_t offset)
1188 {
1189         return bce_reg_rd_ind(sc, sc->bce_shmem_base + offset);
1190 }
1191
1192
1193 /****************************************************************************/
1194 /* Context memory write.                                                    */
1195 /*                                                                          */
1196 /* The NetXtreme II controller uses context memory to track connection      */
1197 /* information for L2 and higher network protocols.                         */
1198 /*                                                                          */
1199 /* Returns:                                                                 */
1200 /*   Nothing.                                                               */
1201 /****************************************************************************/
1202 static void
1203 bce_ctx_wr(struct bce_softc *sc, uint32_t cid_addr, uint32_t ctx_offset,
1204     uint32_t ctx_val)
1205 {
1206         uint32_t idx, offset = ctx_offset + cid_addr;
1207         uint32_t val, retry_cnt = 5;
1208
1209         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
1210             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
1211                 REG_WR(sc, BCE_CTX_CTX_DATA, ctx_val);
1212                 REG_WR(sc, BCE_CTX_CTX_CTRL, (offset | BCE_CTX_CTX_CTRL_WRITE_REQ));
1213
1214                 for (idx = 0; idx < retry_cnt; idx++) {
1215                         val = REG_RD(sc, BCE_CTX_CTX_CTRL);
1216                         if ((val & BCE_CTX_CTX_CTRL_WRITE_REQ) == 0)
1217                                 break;
1218                         DELAY(5);
1219                 }
1220
1221                 if (val & BCE_CTX_CTX_CTRL_WRITE_REQ) {
1222                         device_printf(sc->bce_dev,
1223                             "Unable to write CTX memory: "
1224                             "cid_addr = 0x%08X, offset = 0x%08X!\n",
1225                             cid_addr, ctx_offset);
1226                 }
1227         } else {
1228                 REG_WR(sc, BCE_CTX_DATA_ADR, offset);
1229                 REG_WR(sc, BCE_CTX_DATA, ctx_val);
1230         }
1231 }
1232
1233
1234 /****************************************************************************/
1235 /* PHY register read.                                                       */
1236 /*                                                                          */
1237 /* Implements register reads on the MII bus.                                */
1238 /*                                                                          */
1239 /* Returns:                                                                 */
1240 /*   The value of the register.                                             */
1241 /****************************************************************************/
1242 static int
1243 bce_miibus_read_reg(device_t dev, int phy, int reg)
1244 {
1245         struct bce_softc *sc = device_get_softc(dev);
1246         uint32_t val;
1247         int i;
1248
1249         /* Make sure we are accessing the correct PHY address. */
1250         KASSERT(phy == sc->bce_phy_addr,
1251             ("invalid phyno %d, should be %d\n", phy, sc->bce_phy_addr));
1252
1253         if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) {
1254                 val = REG_RD(sc, BCE_EMAC_MDIO_MODE);
1255                 val &= ~BCE_EMAC_MDIO_MODE_AUTO_POLL;
1256
1257                 REG_WR(sc, BCE_EMAC_MDIO_MODE, val);
1258                 REG_RD(sc, BCE_EMAC_MDIO_MODE);
1259
1260                 DELAY(40);
1261         }
1262
1263         val = BCE_MIPHY(phy) | BCE_MIREG(reg) |
1264               BCE_EMAC_MDIO_COMM_COMMAND_READ | BCE_EMAC_MDIO_COMM_DISEXT |
1265               BCE_EMAC_MDIO_COMM_START_BUSY;
1266         REG_WR(sc, BCE_EMAC_MDIO_COMM, val);
1267
1268         for (i = 0; i < BCE_PHY_TIMEOUT; i++) {
1269                 DELAY(10);
1270
1271                 val = REG_RD(sc, BCE_EMAC_MDIO_COMM);
1272                 if (!(val & BCE_EMAC_MDIO_COMM_START_BUSY)) {
1273                         DELAY(5);
1274
1275                         val = REG_RD(sc, BCE_EMAC_MDIO_COMM);
1276                         val &= BCE_EMAC_MDIO_COMM_DATA;
1277                         break;
1278                 }
1279         }
1280
1281         if (val & BCE_EMAC_MDIO_COMM_START_BUSY) {
1282                 if_printf(&sc->arpcom.ac_if,
1283                           "Error: PHY read timeout! phy = %d, reg = 0x%04X\n",
1284                           phy, reg);
1285                 val = 0x0;
1286         } else {
1287                 val = REG_RD(sc, BCE_EMAC_MDIO_COMM);
1288         }
1289
1290         if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) {
1291                 val = REG_RD(sc, BCE_EMAC_MDIO_MODE);
1292                 val |= BCE_EMAC_MDIO_MODE_AUTO_POLL;
1293
1294                 REG_WR(sc, BCE_EMAC_MDIO_MODE, val);
1295                 REG_RD(sc, BCE_EMAC_MDIO_MODE);
1296
1297                 DELAY(40);
1298         }
1299         return (val & 0xffff);
1300 }
1301
1302
1303 /****************************************************************************/
1304 /* PHY register write.                                                      */
1305 /*                                                                          */
1306 /* Implements register writes on the MII bus.                               */
1307 /*                                                                          */
1308 /* Returns:                                                                 */
1309 /*   The value of the register.                                             */
1310 /****************************************************************************/
1311 static int
1312 bce_miibus_write_reg(device_t dev, int phy, int reg, int val)
1313 {
1314         struct bce_softc *sc = device_get_softc(dev);
1315         uint32_t val1;
1316         int i;
1317
1318         /* Make sure we are accessing the correct PHY address. */
1319         KASSERT(phy == sc->bce_phy_addr,
1320             ("invalid phyno %d, should be %d\n", phy, sc->bce_phy_addr));
1321
1322         if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) {
1323                 val1 = REG_RD(sc, BCE_EMAC_MDIO_MODE);
1324                 val1 &= ~BCE_EMAC_MDIO_MODE_AUTO_POLL;
1325
1326                 REG_WR(sc, BCE_EMAC_MDIO_MODE, val1);
1327                 REG_RD(sc, BCE_EMAC_MDIO_MODE);
1328
1329                 DELAY(40);
1330         }
1331
1332         val1 = BCE_MIPHY(phy) | BCE_MIREG(reg) | val |
1333                 BCE_EMAC_MDIO_COMM_COMMAND_WRITE |
1334                 BCE_EMAC_MDIO_COMM_START_BUSY | BCE_EMAC_MDIO_COMM_DISEXT;
1335         REG_WR(sc, BCE_EMAC_MDIO_COMM, val1);
1336
1337         for (i = 0; i < BCE_PHY_TIMEOUT; i++) {
1338                 DELAY(10);
1339
1340                 val1 = REG_RD(sc, BCE_EMAC_MDIO_COMM);
1341                 if (!(val1 & BCE_EMAC_MDIO_COMM_START_BUSY)) {
1342                         DELAY(5);
1343                         break;
1344                 }
1345         }
1346
1347         if (val1 & BCE_EMAC_MDIO_COMM_START_BUSY)
1348                 if_printf(&sc->arpcom.ac_if, "PHY write timeout!\n");
1349
1350         if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) {
1351                 val1 = REG_RD(sc, BCE_EMAC_MDIO_MODE);
1352                 val1 |= BCE_EMAC_MDIO_MODE_AUTO_POLL;
1353
1354                 REG_WR(sc, BCE_EMAC_MDIO_MODE, val1);
1355                 REG_RD(sc, BCE_EMAC_MDIO_MODE);
1356
1357                 DELAY(40);
1358         }
1359         return 0;
1360 }
1361
1362
1363 /****************************************************************************/
1364 /* MII bus status change.                                                   */
1365 /*                                                                          */
1366 /* Called by the MII bus driver when the PHY establishes link to set the    */
1367 /* MAC interface registers.                                                 */
1368 /*                                                                          */
1369 /* Returns:                                                                 */
1370 /*   Nothing.                                                               */
1371 /****************************************************************************/
1372 static void
1373 bce_miibus_statchg(device_t dev)
1374 {
1375         struct bce_softc *sc = device_get_softc(dev);
1376         struct mii_data *mii = device_get_softc(sc->bce_miibus);
1377
1378         BCE_CLRBIT(sc, BCE_EMAC_MODE, BCE_EMAC_MODE_PORT);
1379
1380         /*
1381          * Set MII or GMII interface based on the speed negotiated
1382          * by the PHY.
1383          */
1384         if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T || 
1385             IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) {
1386                 BCE_SETBIT(sc, BCE_EMAC_MODE, BCE_EMAC_MODE_PORT_GMII);
1387         } else {
1388                 BCE_SETBIT(sc, BCE_EMAC_MODE, BCE_EMAC_MODE_PORT_MII);
1389         }
1390
1391         /*
1392          * Set half or full duplex based on the duplicity negotiated
1393          * by the PHY.
1394          */
1395         if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
1396                 BCE_CLRBIT(sc, BCE_EMAC_MODE, BCE_EMAC_MODE_HALF_DUPLEX);
1397         } else {
1398                 BCE_SETBIT(sc, BCE_EMAC_MODE, BCE_EMAC_MODE_HALF_DUPLEX);
1399         }
1400 }
1401
1402
1403 /****************************************************************************/
1404 /* Acquire NVRAM lock.                                                      */
1405 /*                                                                          */
1406 /* Before the NVRAM can be accessed the caller must acquire an NVRAM lock.  */
1407 /* Locks 0 and 2 are reserved, lock 1 is used by firmware and lock 2 is     */
1408 /* for use by the driver.                                                   */
1409 /*                                                                          */
1410 /* Returns:                                                                 */
1411 /*   0 on success, positive value on failure.                               */
1412 /****************************************************************************/
1413 static int
1414 bce_acquire_nvram_lock(struct bce_softc *sc)
1415 {
1416         uint32_t val;
1417         int j;
1418
1419         /* Request access to the flash interface. */
1420         REG_WR(sc, BCE_NVM_SW_ARB, BCE_NVM_SW_ARB_ARB_REQ_SET2);
1421         for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
1422                 val = REG_RD(sc, BCE_NVM_SW_ARB);
1423                 if (val & BCE_NVM_SW_ARB_ARB_ARB2)
1424                         break;
1425
1426                 DELAY(5);
1427         }
1428
1429         if (j >= NVRAM_TIMEOUT_COUNT) {
1430                 return EBUSY;
1431         }
1432         return 0;
1433 }
1434
1435
1436 /****************************************************************************/
1437 /* Release NVRAM lock.                                                      */
1438 /*                                                                          */
1439 /* When the caller is finished accessing NVRAM the lock must be released.   */
1440 /* Locks 0 and 2 are reserved, lock 1 is used by firmware and lock 2 is     */
1441 /* for use by the driver.                                                   */
1442 /*                                                                          */
1443 /* Returns:                                                                 */
1444 /*   0 on success, positive value on failure.                               */
1445 /****************************************************************************/
1446 static int
1447 bce_release_nvram_lock(struct bce_softc *sc)
1448 {
1449         int j;
1450         uint32_t val;
1451
1452         /*
1453          * Relinquish nvram interface.
1454          */
1455         REG_WR(sc, BCE_NVM_SW_ARB, BCE_NVM_SW_ARB_ARB_REQ_CLR2);
1456
1457         for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
1458                 val = REG_RD(sc, BCE_NVM_SW_ARB);
1459                 if (!(val & BCE_NVM_SW_ARB_ARB_ARB2))
1460                         break;
1461
1462                 DELAY(5);
1463         }
1464
1465         if (j >= NVRAM_TIMEOUT_COUNT) {
1466                 return EBUSY;
1467         }
1468         return 0;
1469 }
1470
1471
1472 /****************************************************************************/
1473 /* Enable NVRAM access.                                                     */
1474 /*                                                                          */
1475 /* Before accessing NVRAM for read or write operations the caller must      */
1476 /* enabled NVRAM access.                                                    */
1477 /*                                                                          */
1478 /* Returns:                                                                 */
1479 /*   Nothing.                                                               */
1480 /****************************************************************************/
1481 static void
1482 bce_enable_nvram_access(struct bce_softc *sc)
1483 {
1484         uint32_t val;
1485
1486         val = REG_RD(sc, BCE_NVM_ACCESS_ENABLE);
1487         /* Enable both bits, even on read. */
1488         REG_WR(sc, BCE_NVM_ACCESS_ENABLE,
1489                val | BCE_NVM_ACCESS_ENABLE_EN | BCE_NVM_ACCESS_ENABLE_WR_EN);
1490 }
1491
1492
1493 /****************************************************************************/
1494 /* Disable NVRAM access.                                                    */
1495 /*                                                                          */
1496 /* When the caller is finished accessing NVRAM access must be disabled.     */
1497 /*                                                                          */
1498 /* Returns:                                                                 */
1499 /*   Nothing.                                                               */
1500 /****************************************************************************/
1501 static void
1502 bce_disable_nvram_access(struct bce_softc *sc)
1503 {
1504         uint32_t val;
1505
1506         val = REG_RD(sc, BCE_NVM_ACCESS_ENABLE);
1507
1508         /* Disable both bits, even after read. */
1509         REG_WR(sc, BCE_NVM_ACCESS_ENABLE,
1510                val & ~(BCE_NVM_ACCESS_ENABLE_EN | BCE_NVM_ACCESS_ENABLE_WR_EN));
1511 }
1512
1513
1514 /****************************************************************************/
1515 /* Read a dword (32 bits) from NVRAM.                                       */
1516 /*                                                                          */
1517 /* Read a 32 bit word from NVRAM.  The caller is assumed to have already    */
1518 /* obtained the NVRAM lock and enabled the controller for NVRAM access.     */
1519 /*                                                                          */
1520 /* Returns:                                                                 */
1521 /*   0 on success and the 32 bit value read, positive value on failure.     */
1522 /****************************************************************************/
1523 static int
1524 bce_nvram_read_dword(struct bce_softc *sc, uint32_t offset, uint8_t *ret_val,
1525                      uint32_t cmd_flags)
1526 {
1527         uint32_t cmd;
1528         int i, rc = 0;
1529
1530         /* Build the command word. */
1531         cmd = BCE_NVM_COMMAND_DOIT | cmd_flags;
1532
1533         /* Calculate the offset for buffered flash. */
1534         if (sc->bce_flash_info->flags & BCE_NV_TRANSLATE) {
1535                 offset = ((offset / sc->bce_flash_info->page_size) <<
1536                           sc->bce_flash_info->page_bits) +
1537                          (offset % sc->bce_flash_info->page_size);
1538         }
1539
1540         /*
1541          * Clear the DONE bit separately, set the address to read,
1542          * and issue the read.
1543          */
1544         REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_DONE);
1545         REG_WR(sc, BCE_NVM_ADDR, offset & BCE_NVM_ADDR_NVM_ADDR_VALUE);
1546         REG_WR(sc, BCE_NVM_COMMAND, cmd);
1547
1548         /* Wait for completion. */
1549         for (i = 0; i < NVRAM_TIMEOUT_COUNT; i++) {
1550                 uint32_t val;
1551
1552                 DELAY(5);
1553
1554                 val = REG_RD(sc, BCE_NVM_COMMAND);
1555                 if (val & BCE_NVM_COMMAND_DONE) {
1556                         val = REG_RD(sc, BCE_NVM_READ);
1557
1558                         val = be32toh(val);
1559                         memcpy(ret_val, &val, 4);
1560                         break;
1561                 }
1562         }
1563
1564         /* Check for errors. */
1565         if (i >= NVRAM_TIMEOUT_COUNT) {
1566                 if_printf(&sc->arpcom.ac_if,
1567                           "Timeout error reading NVRAM at offset 0x%08X!\n",
1568                           offset);
1569                 rc = EBUSY;
1570         }
1571         return rc;
1572 }
1573
1574
1575 /****************************************************************************/
1576 /* Initialize NVRAM access.                                                 */
1577 /*                                                                          */
1578 /* Identify the NVRAM device in use and prepare the NVRAM interface to      */
1579 /* access that device.                                                      */
1580 /*                                                                          */
1581 /* Returns:                                                                 */
1582 /*   0 on success, positive value on failure.                               */
1583 /****************************************************************************/
1584 static int
1585 bce_init_nvram(struct bce_softc *sc)
1586 {
1587         uint32_t val;
1588         int j, entry_count, rc = 0;
1589         const struct flash_spec *flash;
1590
1591         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
1592             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
1593                 sc->bce_flash_info = &flash_5709;
1594                 goto bce_init_nvram_get_flash_size;
1595         }
1596
1597         /* Determine the selected interface. */
1598         val = REG_RD(sc, BCE_NVM_CFG1);
1599
1600         entry_count = sizeof(flash_table) / sizeof(struct flash_spec);
1601
1602         /*
1603          * Flash reconfiguration is required to support additional
1604          * NVRAM devices not directly supported in hardware.
1605          * Check if the flash interface was reconfigured
1606          * by the bootcode.
1607          */
1608
1609         if (val & 0x40000000) {
1610                 /* Flash interface reconfigured by bootcode. */
1611                 for (j = 0, flash = flash_table; j < entry_count;
1612                      j++, flash++) {
1613                         if ((val & FLASH_BACKUP_STRAP_MASK) ==
1614                             (flash->config1 & FLASH_BACKUP_STRAP_MASK)) {
1615                                 sc->bce_flash_info = flash;
1616                                 break;
1617                         }
1618                 }
1619         } else {
1620                 /* Flash interface not yet reconfigured. */
1621                 uint32_t mask;
1622
1623                 if (val & (1 << 23))
1624                         mask = FLASH_BACKUP_STRAP_MASK;
1625                 else
1626                         mask = FLASH_STRAP_MASK;
1627
1628                 /* Look for the matching NVRAM device configuration data. */
1629                 for (j = 0, flash = flash_table; j < entry_count;
1630                      j++, flash++) {
1631                         /* Check if the device matches any of the known devices. */
1632                         if ((val & mask) == (flash->strapping & mask)) {
1633                                 /* Found a device match. */
1634                                 sc->bce_flash_info = flash;
1635
1636                                 /* Request access to the flash interface. */
1637                                 rc = bce_acquire_nvram_lock(sc);
1638                                 if (rc != 0)
1639                                         return rc;
1640
1641                                 /* Reconfigure the flash interface. */
1642                                 bce_enable_nvram_access(sc);
1643                                 REG_WR(sc, BCE_NVM_CFG1, flash->config1);
1644                                 REG_WR(sc, BCE_NVM_CFG2, flash->config2);
1645                                 REG_WR(sc, BCE_NVM_CFG3, flash->config3);
1646                                 REG_WR(sc, BCE_NVM_WRITE1, flash->write1);
1647                                 bce_disable_nvram_access(sc);
1648                                 bce_release_nvram_lock(sc);
1649                                 break;
1650                         }
1651                 }
1652         }
1653
1654         /* Check if a matching device was found. */
1655         if (j == entry_count) {
1656                 sc->bce_flash_info = NULL;
1657                 if_printf(&sc->arpcom.ac_if, "Unknown Flash NVRAM found!\n");
1658                 return ENODEV;
1659         }
1660
1661 bce_init_nvram_get_flash_size:
1662         /* Write the flash config data to the shared memory interface. */
1663         val = bce_shmem_rd(sc, BCE_SHARED_HW_CFG_CONFIG2) &
1664             BCE_SHARED_HW_CFG2_NVM_SIZE_MASK;
1665         if (val)
1666                 sc->bce_flash_size = val;
1667         else
1668                 sc->bce_flash_size = sc->bce_flash_info->total_size;
1669
1670         return rc;
1671 }
1672
1673
1674 /****************************************************************************/
1675 /* Read an arbitrary range of data from NVRAM.                              */
1676 /*                                                                          */
1677 /* Prepares the NVRAM interface for access and reads the requested data     */
1678 /* into the supplied buffer.                                                */
1679 /*                                                                          */
1680 /* Returns:                                                                 */
1681 /*   0 on success and the data read, positive value on failure.             */
1682 /****************************************************************************/
1683 static int
1684 bce_nvram_read(struct bce_softc *sc, uint32_t offset, uint8_t *ret_buf,
1685                int buf_size)
1686 {
1687         uint32_t cmd_flags, offset32, len32, extra;
1688         int rc = 0;
1689
1690         if (buf_size == 0)
1691                 return 0;
1692
1693         /* Request access to the flash interface. */
1694         rc = bce_acquire_nvram_lock(sc);
1695         if (rc != 0)
1696                 return rc;
1697
1698         /* Enable access to flash interface */
1699         bce_enable_nvram_access(sc);
1700
1701         len32 = buf_size;
1702         offset32 = offset;
1703         extra = 0;
1704
1705         cmd_flags = 0;
1706
1707         /* XXX should we release nvram lock if read_dword() fails? */
1708         if (offset32 & 3) {
1709                 uint8_t buf[4];
1710                 uint32_t pre_len;
1711
1712                 offset32 &= ~3;
1713                 pre_len = 4 - (offset & 3);
1714
1715                 if (pre_len >= len32) {
1716                         pre_len = len32;
1717                         cmd_flags = BCE_NVM_COMMAND_FIRST | BCE_NVM_COMMAND_LAST;
1718                 } else {
1719                         cmd_flags = BCE_NVM_COMMAND_FIRST;
1720                 }
1721
1722                 rc = bce_nvram_read_dword(sc, offset32, buf, cmd_flags);
1723                 if (rc)
1724                         return rc;
1725
1726                 memcpy(ret_buf, buf + (offset & 3), pre_len);
1727
1728                 offset32 += 4;
1729                 ret_buf += pre_len;
1730                 len32 -= pre_len;
1731         }
1732
1733         if (len32 & 3) {
1734                 extra = 4 - (len32 & 3);
1735                 len32 = (len32 + 4) & ~3;
1736         }
1737
1738         if (len32 == 4) {
1739                 uint8_t buf[4];
1740
1741                 if (cmd_flags)
1742                         cmd_flags = BCE_NVM_COMMAND_LAST;
1743                 else
1744                         cmd_flags = BCE_NVM_COMMAND_FIRST |
1745                                     BCE_NVM_COMMAND_LAST;
1746
1747                 rc = bce_nvram_read_dword(sc, offset32, buf, cmd_flags);
1748
1749                 memcpy(ret_buf, buf, 4 - extra);
1750         } else if (len32 > 0) {
1751                 uint8_t buf[4];
1752
1753                 /* Read the first word. */
1754                 if (cmd_flags)
1755                         cmd_flags = 0;
1756                 else
1757                         cmd_flags = BCE_NVM_COMMAND_FIRST;
1758
1759                 rc = bce_nvram_read_dword(sc, offset32, ret_buf, cmd_flags);
1760
1761                 /* Advance to the next dword. */
1762                 offset32 += 4;
1763                 ret_buf += 4;
1764                 len32 -= 4;
1765
1766                 while (len32 > 4 && rc == 0) {
1767                         rc = bce_nvram_read_dword(sc, offset32, ret_buf, 0);
1768
1769                         /* Advance to the next dword. */
1770                         offset32 += 4;
1771                         ret_buf += 4;
1772                         len32 -= 4;
1773                 }
1774
1775                 if (rc)
1776                         goto bce_nvram_read_locked_exit;
1777
1778                 cmd_flags = BCE_NVM_COMMAND_LAST;
1779                 rc = bce_nvram_read_dword(sc, offset32, buf, cmd_flags);
1780
1781                 memcpy(ret_buf, buf, 4 - extra);
1782         }
1783
1784 bce_nvram_read_locked_exit:
1785         /* Disable access to flash interface and release the lock. */
1786         bce_disable_nvram_access(sc);
1787         bce_release_nvram_lock(sc);
1788
1789         return rc;
1790 }
1791
1792
1793 /****************************************************************************/
1794 /* Verifies that NVRAM is accessible and contains valid data.               */
1795 /*                                                                          */
1796 /* Reads the configuration data from NVRAM and verifies that the CRC is     */
1797 /* correct.                                                                 */
1798 /*                                                                          */
1799 /* Returns:                                                                 */
1800 /*   0 on success, positive value on failure.                               */
1801 /****************************************************************************/
1802 static int
1803 bce_nvram_test(struct bce_softc *sc)
1804 {
1805         uint32_t buf[BCE_NVRAM_SIZE / 4];
1806         uint32_t magic, csum;
1807         uint8_t *data = (uint8_t *)buf;
1808         int rc = 0;
1809
1810         /*
1811          * Check that the device NVRAM is valid by reading
1812          * the magic value at offset 0.
1813          */
1814         rc = bce_nvram_read(sc, 0, data, 4);
1815         if (rc != 0)
1816                 return rc;
1817
1818         magic = be32toh(buf[0]);
1819         if (magic != BCE_NVRAM_MAGIC) {
1820                 if_printf(&sc->arpcom.ac_if,
1821                           "Invalid NVRAM magic value! Expected: 0x%08X, "
1822                           "Found: 0x%08X\n", BCE_NVRAM_MAGIC, magic);
1823                 return ENODEV;
1824         }
1825
1826         /*
1827          * Verify that the device NVRAM includes valid
1828          * configuration data.
1829          */
1830         rc = bce_nvram_read(sc, 0x100, data, BCE_NVRAM_SIZE);
1831         if (rc != 0)
1832                 return rc;
1833
1834         csum = ether_crc32_le(data, 0x100);
1835         if (csum != BCE_CRC32_RESIDUAL) {
1836                 if_printf(&sc->arpcom.ac_if,
1837                           "Invalid Manufacturing Information NVRAM CRC! "
1838                           "Expected: 0x%08X, Found: 0x%08X\n",
1839                           BCE_CRC32_RESIDUAL, csum);
1840                 return ENODEV;
1841         }
1842
1843         csum = ether_crc32_le(data + 0x100, 0x100);
1844         if (csum != BCE_CRC32_RESIDUAL) {
1845                 if_printf(&sc->arpcom.ac_if,
1846                           "Invalid Feature Configuration Information "
1847                           "NVRAM CRC! Expected: 0x%08X, Found: 08%08X\n",
1848                           BCE_CRC32_RESIDUAL, csum);
1849                 rc = ENODEV;
1850         }
1851         return rc;
1852 }
1853
1854
1855 /****************************************************************************/
1856 /* Identifies the current media type of the controller and sets the PHY     */
1857 /* address.                                                                 */
1858 /*                                                                          */
1859 /* Returns:                                                                 */
1860 /*   Nothing.                                                               */
1861 /****************************************************************************/
1862 static void
1863 bce_get_media(struct bce_softc *sc)
1864 {
1865         uint32_t val;
1866
1867         sc->bce_phy_addr = 1;
1868
1869         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
1870             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
1871                 uint32_t val = REG_RD(sc, BCE_MISC_DUAL_MEDIA_CTRL);
1872                 uint32_t bond_id = val & BCE_MISC_DUAL_MEDIA_CTRL_BOND_ID;
1873                 uint32_t strap;
1874
1875                 /*
1876                  * The BCM5709S is software configurable
1877                  * for Copper or SerDes operation.
1878                  */
1879                 if (bond_id == BCE_MISC_DUAL_MEDIA_CTRL_BOND_ID_C) {
1880                         return;
1881                 } else if (bond_id == BCE_MISC_DUAL_MEDIA_CTRL_BOND_ID_S) {
1882                         sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG;
1883                         return;
1884                 }
1885
1886                 if (val & BCE_MISC_DUAL_MEDIA_CTRL_STRAP_OVERRIDE) {
1887                         strap = (val & BCE_MISC_DUAL_MEDIA_CTRL_PHY_CTRL) >> 21;
1888                 } else {
1889                         strap =
1890                         (val & BCE_MISC_DUAL_MEDIA_CTRL_PHY_CTRL_STRAP) >> 8;
1891                 }
1892
1893                 if (pci_get_function(sc->bce_dev) == 0) {
1894                         switch (strap) {
1895                         case 0x4:
1896                         case 0x5:
1897                         case 0x6:
1898                                 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG;
1899                                 break;
1900                         }
1901                 } else {
1902                         switch (strap) {
1903                         case 0x1:
1904                         case 0x2:
1905                         case 0x4:
1906                                 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG;
1907                                 break;
1908                         }
1909                 }
1910         } else if (BCE_CHIP_BOND_ID(sc) & BCE_CHIP_BOND_ID_SERDES_BIT) {
1911                 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG;
1912         }
1913
1914         if (sc->bce_phy_flags & BCE_PHY_SERDES_FLAG) {
1915                 sc->bce_flags |= BCE_NO_WOL_FLAG;
1916                 if (BCE_CHIP_NUM(sc) != BCE_CHIP_NUM_5706) {
1917                         sc->bce_phy_addr = 2;
1918                         val = bce_shmem_rd(sc, BCE_SHARED_HW_CFG_CONFIG);
1919                         if (val & BCE_SHARED_HW_CFG_PHY_2_5G)
1920                                 sc->bce_phy_flags |= BCE_PHY_2_5G_CAPABLE_FLAG;
1921                 }
1922         } else if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5706) ||
1923             (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5708)) {
1924                 sc->bce_phy_flags |= BCE_PHY_CRC_FIX_FLAG;
1925         }
1926 }
1927
1928
1929 static void
1930 bce_destroy_tx_ring(struct bce_tx_ring *txr)
1931 {
1932         int i;
1933
1934         /* Destroy the TX buffer descriptor DMA stuffs. */
1935         if (txr->tx_bd_chain_tag != NULL) {
1936                 for (i = 0; i < txr->tx_pages; i++) {
1937                         if (txr->tx_bd_chain[i] != NULL) {
1938                                 bus_dmamap_unload(txr->tx_bd_chain_tag,
1939                                     txr->tx_bd_chain_map[i]);
1940                                 bus_dmamem_free(txr->tx_bd_chain_tag,
1941                                     txr->tx_bd_chain[i],
1942                                     txr->tx_bd_chain_map[i]);
1943                         }
1944                 }
1945                 bus_dma_tag_destroy(txr->tx_bd_chain_tag);
1946         }
1947
1948         /* Destroy the TX mbuf DMA stuffs. */
1949         if (txr->tx_mbuf_tag != NULL) {
1950                 for (i = 0; i < TOTAL_TX_BD(txr); i++) {
1951                         /* Must have been unloaded in bce_stop() */
1952                         KKASSERT(txr->tx_mbuf_ptr[i] == NULL);
1953                         bus_dmamap_destroy(txr->tx_mbuf_tag,
1954                             txr->tx_mbuf_map[i]);
1955                 }
1956                 bus_dma_tag_destroy(txr->tx_mbuf_tag);
1957         }
1958
1959         if (txr->tx_bd_chain_map != NULL)
1960                 kfree(txr->tx_bd_chain_map, M_DEVBUF);
1961         if (txr->tx_bd_chain != NULL)
1962                 kfree(txr->tx_bd_chain, M_DEVBUF);
1963         if (txr->tx_bd_chain_paddr != NULL)
1964                 kfree(txr->tx_bd_chain_paddr, M_DEVBUF);
1965
1966         if (txr->tx_mbuf_map != NULL)
1967                 kfree(txr->tx_mbuf_map, M_DEVBUF);
1968         if (txr->tx_mbuf_ptr != NULL)
1969                 kfree(txr->tx_mbuf_ptr, M_DEVBUF);
1970 }
1971
1972
1973 static void
1974 bce_destroy_rx_ring(struct bce_rx_ring *rxr)
1975 {
1976         int i;
1977
1978         /* Destroy the RX buffer descriptor DMA stuffs. */
1979         if (rxr->rx_bd_chain_tag != NULL) {
1980                 for (i = 0; i < rxr->rx_pages; i++) {
1981                         if (rxr->rx_bd_chain[i] != NULL) {
1982                                 bus_dmamap_unload(rxr->rx_bd_chain_tag,
1983                                     rxr->rx_bd_chain_map[i]);
1984                                 bus_dmamem_free(rxr->rx_bd_chain_tag,
1985                                     rxr->rx_bd_chain[i],
1986                                     rxr->rx_bd_chain_map[i]);
1987                         }
1988                 }
1989                 bus_dma_tag_destroy(rxr->rx_bd_chain_tag);
1990         }
1991
1992         /* Destroy the RX mbuf DMA stuffs. */
1993         if (rxr->rx_mbuf_tag != NULL) {
1994                 for (i = 0; i < TOTAL_RX_BD(rxr); i++) {
1995                         /* Must have been unloaded in bce_stop() */
1996                         KKASSERT(rxr->rx_mbuf_ptr[i] == NULL);
1997                         bus_dmamap_destroy(rxr->rx_mbuf_tag,
1998                             rxr->rx_mbuf_map[i]);
1999                 }
2000                 bus_dmamap_destroy(rxr->rx_mbuf_tag, rxr->rx_mbuf_tmpmap);
2001                 bus_dma_tag_destroy(rxr->rx_mbuf_tag);
2002         }
2003
2004         if (rxr->rx_bd_chain_map != NULL)
2005                 kfree(rxr->rx_bd_chain_map, M_DEVBUF);
2006         if (rxr->rx_bd_chain != NULL)
2007                 kfree(rxr->rx_bd_chain, M_DEVBUF);
2008         if (rxr->rx_bd_chain_paddr != NULL)
2009                 kfree(rxr->rx_bd_chain_paddr, M_DEVBUF);
2010
2011         if (rxr->rx_mbuf_map != NULL)
2012                 kfree(rxr->rx_mbuf_map, M_DEVBUF);
2013         if (rxr->rx_mbuf_ptr != NULL)
2014                 kfree(rxr->rx_mbuf_ptr, M_DEVBUF);
2015         if (rxr->rx_mbuf_paddr != NULL)
2016                 kfree(rxr->rx_mbuf_paddr, M_DEVBUF);
2017 }
2018
2019
2020 /****************************************************************************/
2021 /* Free any DMA memory owned by the driver.                                 */
2022 /*                                                                          */
2023 /* Scans through each data structre that requires DMA memory and frees      */
2024 /* the memory if allocated.                                                 */
2025 /*                                                                          */
2026 /* Returns:                                                                 */
2027 /*   Nothing.                                                               */
2028 /****************************************************************************/
2029 static void
2030 bce_dma_free(struct bce_softc *sc)
2031 {
2032         int i;
2033
2034         /* Destroy the status block. */
2035         if (sc->status_tag != NULL) {
2036                 if (sc->status_block != NULL) {
2037                         bus_dmamap_unload(sc->status_tag, sc->status_map);
2038                         bus_dmamem_free(sc->status_tag, sc->status_block,
2039                                         sc->status_map);
2040                 }
2041                 bus_dma_tag_destroy(sc->status_tag);
2042         }
2043
2044         /* Destroy the statistics block. */
2045         if (sc->stats_tag != NULL) {
2046                 if (sc->stats_block != NULL) {
2047                         bus_dmamap_unload(sc->stats_tag, sc->stats_map);
2048                         bus_dmamem_free(sc->stats_tag, sc->stats_block,
2049                                         sc->stats_map);
2050                 }
2051                 bus_dma_tag_destroy(sc->stats_tag);
2052         }
2053
2054         /* Destroy the CTX DMA stuffs. */
2055         if (sc->ctx_tag != NULL) {
2056                 for (i = 0; i < sc->ctx_pages; i++) {
2057                         if (sc->ctx_block[i] != NULL) {
2058                                 bus_dmamap_unload(sc->ctx_tag, sc->ctx_map[i]);
2059                                 bus_dmamem_free(sc->ctx_tag, sc->ctx_block[i],
2060                                                 sc->ctx_map[i]);
2061                         }
2062                 }
2063                 bus_dma_tag_destroy(sc->ctx_tag);
2064         }
2065
2066         /* Free TX rings */
2067         if (sc->tx_rings != NULL) {
2068                 for (i = 0; i < sc->ring_cnt; ++i)
2069                         bce_destroy_tx_ring(&sc->tx_rings[i]);
2070                 kfree(sc->tx_rings, M_DEVBUF);
2071         }
2072
2073         /* Free RX rings */
2074         if (sc->rx_rings != NULL) {
2075                 for (i = 0; i < sc->ring_cnt; ++i)
2076                         bce_destroy_rx_ring(&sc->rx_rings[i]);
2077                 kfree(sc->rx_rings, M_DEVBUF);
2078         }
2079
2080         /* Destroy the parent tag */
2081         if (sc->parent_tag != NULL)
2082                 bus_dma_tag_destroy(sc->parent_tag);
2083 }
2084
2085
2086 /****************************************************************************/
2087 /* Get DMA memory from the OS.                                              */
2088 /*                                                                          */
2089 /* Validates that the OS has provided DMA buffers in response to a          */
2090 /* bus_dmamap_load() call and saves the physical address of those buffers.  */
2091 /* When the callback is used the OS will return 0 for the mapping function  */
2092 /* (bus_dmamap_load()) so we use the value of map_arg->maxsegs to pass any  */
2093 /* failures back to the caller.                                             */
2094 /*                                                                          */
2095 /* Returns:                                                                 */
2096 /*   Nothing.                                                               */
2097 /****************************************************************************/
2098 static void
2099 bce_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
2100 {
2101         bus_addr_t *busaddr = arg;
2102
2103         /* Check for an error and signal the caller that an error occurred. */
2104         if (error)
2105                 return;
2106
2107         KASSERT(nseg == 1, ("only one segment is allowed"));
2108         *busaddr = segs->ds_addr;
2109 }
2110
2111
2112 static int
2113 bce_create_tx_ring(struct bce_tx_ring *txr)
2114 {
2115         int pages, rc, i;
2116
2117         lwkt_serialize_init(&txr->tx_serialize);
2118         txr->tx_wreg = bce_tx_wreg;
2119
2120         pages = device_getenv_int(txr->sc->bce_dev, "tx_pages", bce_tx_pages);
2121         if (pages <= 0 || pages > TX_PAGES_MAX || !powerof2(pages)) {
2122                 device_printf(txr->sc->bce_dev, "invalid # of TX pages\n");
2123                 pages = TX_PAGES_DEFAULT;
2124         }
2125         txr->tx_pages = pages;
2126
2127         txr->tx_bd_chain_map = kmalloc(sizeof(bus_dmamap_t) * txr->tx_pages,
2128             M_DEVBUF, M_WAITOK | M_ZERO);
2129         txr->tx_bd_chain = kmalloc(sizeof(struct tx_bd *) * txr->tx_pages,
2130             M_DEVBUF, M_WAITOK | M_ZERO);
2131         txr->tx_bd_chain_paddr = kmalloc(sizeof(bus_addr_t) * txr->tx_pages,
2132             M_DEVBUF, M_WAITOK | M_ZERO);
2133
2134         txr->tx_mbuf_map = kmalloc(sizeof(bus_dmamap_t) * TOTAL_TX_BD(txr),
2135             M_DEVBUF, M_WAITOK | M_ZERO);
2136         txr->tx_mbuf_ptr = kmalloc(sizeof(struct mbuf *) * TOTAL_TX_BD(txr),
2137             M_DEVBUF, M_WAITOK | M_ZERO);
2138
2139         /*
2140          * Create a DMA tag for the TX buffer descriptor chain,
2141          * allocate and clear the  memory, and fetch the
2142          * physical address of the block.
2143          */
2144         rc = bus_dma_tag_create(txr->sc->parent_tag, BCM_PAGE_SIZE, 0,
2145             BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL,
2146             BCE_TX_CHAIN_PAGE_SZ, 1, BCE_TX_CHAIN_PAGE_SZ,
2147             0, &txr->tx_bd_chain_tag);
2148         if (rc != 0) {
2149                 device_printf(txr->sc->bce_dev, "Could not allocate "
2150                     "TX descriptor chain DMA tag!\n");
2151                 return rc;
2152         }
2153
2154         for (i = 0; i < txr->tx_pages; i++) {
2155                 bus_addr_t busaddr;
2156
2157                 rc = bus_dmamem_alloc(txr->tx_bd_chain_tag,
2158                     (void **)&txr->tx_bd_chain[i],
2159                     BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT,
2160                     &txr->tx_bd_chain_map[i]);
2161                 if (rc != 0) {
2162                         device_printf(txr->sc->bce_dev,
2163                             "Could not allocate %dth TX descriptor "
2164                             "chain DMA memory!\n", i);
2165                         return rc;
2166                 }
2167
2168                 rc = bus_dmamap_load(txr->tx_bd_chain_tag,
2169                     txr->tx_bd_chain_map[i],
2170                     txr->tx_bd_chain[i],
2171                     BCE_TX_CHAIN_PAGE_SZ,
2172                     bce_dma_map_addr, &busaddr,
2173                     BUS_DMA_WAITOK);
2174                 if (rc != 0) {
2175                         if (rc == EINPROGRESS) {
2176                                 panic("%s coherent memory loading "
2177                                     "is still in progress!",
2178                                     txr->sc->arpcom.ac_if.if_xname);
2179                         }
2180                         device_printf(txr->sc->bce_dev, "Could not map %dth "
2181                             "TX descriptor chain DMA memory!\n", i);
2182                         bus_dmamem_free(txr->tx_bd_chain_tag,
2183                             txr->tx_bd_chain[i],
2184                             txr->tx_bd_chain_map[i]);
2185                         txr->tx_bd_chain[i] = NULL;
2186                         return rc;
2187                 }
2188
2189                 txr->tx_bd_chain_paddr[i] = busaddr;
2190         }
2191
2192         /* Create a DMA tag for TX mbufs. */
2193         rc = bus_dma_tag_create(txr->sc->parent_tag, 1, 0,
2194             BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL,
2195             IP_MAXPACKET + sizeof(struct ether_vlan_header),
2196             BCE_MAX_SEGMENTS, PAGE_SIZE,
2197             BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE,
2198             &txr->tx_mbuf_tag);
2199         if (rc != 0) {
2200                 device_printf(txr->sc->bce_dev,
2201                     "Could not allocate TX mbuf DMA tag!\n");
2202                 return rc;
2203         }
2204
2205         /* Create DMA maps for the TX mbufs clusters. */
2206         for (i = 0; i < TOTAL_TX_BD(txr); i++) {
2207                 rc = bus_dmamap_create(txr->tx_mbuf_tag,
2208                     BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE,
2209                     &txr->tx_mbuf_map[i]);
2210                 if (rc != 0) {
2211                         int j;
2212
2213                         for (j = 0; j < i; ++j) {
2214                                 bus_dmamap_destroy(txr->tx_mbuf_tag,
2215                                     txr->tx_mbuf_map[i]);
2216                         }
2217                         bus_dma_tag_destroy(txr->tx_mbuf_tag);
2218                         txr->tx_mbuf_tag = NULL;
2219
2220                         device_printf(txr->sc->bce_dev, "Unable to create "
2221                             "%dth TX mbuf DMA map!\n", i);
2222                         return rc;
2223                 }
2224         }
2225         return 0;
2226 }
2227
2228
2229 static int
2230 bce_create_rx_ring(struct bce_rx_ring *rxr)
2231 {
2232         int pages, rc, i;
2233
2234         lwkt_serialize_init(&rxr->rx_serialize);
2235
2236         pages = device_getenv_int(rxr->sc->bce_dev, "rx_pages", bce_rx_pages);
2237         if (pages <= 0 || pages > RX_PAGES_MAX || !powerof2(pages)) {
2238                 device_printf(rxr->sc->bce_dev, "invalid # of RX pages\n");
2239                 pages = RX_PAGES_DEFAULT;
2240         }
2241         rxr->rx_pages = pages;
2242
2243         rxr->rx_bd_chain_map = kmalloc(sizeof(bus_dmamap_t) * rxr->rx_pages,
2244             M_DEVBUF, M_WAITOK | M_ZERO);
2245         rxr->rx_bd_chain = kmalloc(sizeof(struct rx_bd *) * rxr->rx_pages,
2246             M_DEVBUF, M_WAITOK | M_ZERO);
2247         rxr->rx_bd_chain_paddr = kmalloc(sizeof(bus_addr_t) * rxr->rx_pages,
2248             M_DEVBUF, M_WAITOK | M_ZERO);
2249
2250         rxr->rx_mbuf_map = kmalloc(sizeof(bus_dmamap_t) * TOTAL_RX_BD(rxr),
2251             M_DEVBUF, M_WAITOK | M_ZERO);
2252         rxr->rx_mbuf_ptr = kmalloc(sizeof(struct mbuf *) * TOTAL_RX_BD(rxr),
2253             M_DEVBUF, M_WAITOK | M_ZERO);
2254         rxr->rx_mbuf_paddr = kmalloc(sizeof(bus_addr_t) * TOTAL_RX_BD(rxr),
2255             M_DEVBUF, M_WAITOK | M_ZERO);
2256
2257         /*
2258          * Create a DMA tag for the RX buffer descriptor chain,
2259          * allocate and clear the  memory, and fetch the physical
2260          * address of the blocks.
2261          */
2262         rc = bus_dma_tag_create(rxr->sc->parent_tag, BCM_PAGE_SIZE, 0,
2263             BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL,
2264             BCE_RX_CHAIN_PAGE_SZ, 1, BCE_RX_CHAIN_PAGE_SZ,
2265             0, &rxr->rx_bd_chain_tag);
2266         if (rc != 0) {
2267                 device_printf(rxr->sc->bce_dev, "Could not allocate "
2268                     "RX descriptor chain DMA tag!\n");
2269                 return rc;
2270         }
2271
2272         for (i = 0; i < rxr->rx_pages; i++) {
2273                 bus_addr_t busaddr;
2274
2275                 rc = bus_dmamem_alloc(rxr->rx_bd_chain_tag,
2276                     (void **)&rxr->rx_bd_chain[i],
2277                     BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT,
2278                     &rxr->rx_bd_chain_map[i]);
2279                 if (rc != 0) {
2280                         device_printf(rxr->sc->bce_dev,
2281                             "Could not allocate %dth RX descriptor "
2282                             "chain DMA memory!\n", i);
2283                         return rc;
2284                 }
2285
2286                 rc = bus_dmamap_load(rxr->rx_bd_chain_tag,
2287                     rxr->rx_bd_chain_map[i],
2288                     rxr->rx_bd_chain[i],
2289                     BCE_RX_CHAIN_PAGE_SZ,
2290                     bce_dma_map_addr, &busaddr,
2291                     BUS_DMA_WAITOK);
2292                 if (rc != 0) {
2293                         if (rc == EINPROGRESS) {
2294                                 panic("%s coherent memory loading "
2295                                     "is still in progress!",
2296                                     rxr->sc->arpcom.ac_if.if_xname);
2297                         }
2298                         device_printf(rxr->sc->bce_dev,
2299                             "Could not map %dth RX descriptor "
2300                             "chain DMA memory!\n", i);
2301                         bus_dmamem_free(rxr->rx_bd_chain_tag,
2302                             rxr->rx_bd_chain[i],
2303                             rxr->rx_bd_chain_map[i]);
2304                         rxr->rx_bd_chain[i] = NULL;
2305                         return rc;
2306                 }
2307
2308                 rxr->rx_bd_chain_paddr[i] = busaddr;
2309         }
2310
2311         /* Create a DMA tag for RX mbufs. */
2312         rc = bus_dma_tag_create(rxr->sc->parent_tag, BCE_DMA_RX_ALIGN, 0,
2313             BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL,
2314             MCLBYTES, 1, MCLBYTES,
2315             BUS_DMA_ALLOCNOW | BUS_DMA_ALIGNED | BUS_DMA_WAITOK,
2316             &rxr->rx_mbuf_tag);
2317         if (rc != 0) {
2318                 device_printf(rxr->sc->bce_dev,
2319                     "Could not allocate RX mbuf DMA tag!\n");
2320                 return rc;
2321         }
2322
2323         /* Create tmp DMA map for RX mbuf clusters. */
2324         rc = bus_dmamap_create(rxr->rx_mbuf_tag, BUS_DMA_WAITOK,
2325             &rxr->rx_mbuf_tmpmap);
2326         if (rc != 0) {
2327                 bus_dma_tag_destroy(rxr->rx_mbuf_tag);
2328                 rxr->rx_mbuf_tag = NULL;
2329
2330                 device_printf(rxr->sc->bce_dev,
2331                     "Could not create RX mbuf tmp DMA map!\n");
2332                 return rc;
2333         }
2334
2335         /* Create DMA maps for the RX mbuf clusters. */
2336         for (i = 0; i < TOTAL_RX_BD(rxr); i++) {
2337                 rc = bus_dmamap_create(rxr->rx_mbuf_tag, BUS_DMA_WAITOK,
2338                     &rxr->rx_mbuf_map[i]);
2339                 if (rc != 0) {
2340                         int j;
2341
2342                         for (j = 0; j < i; ++j) {
2343                                 bus_dmamap_destroy(rxr->rx_mbuf_tag,
2344                                     rxr->rx_mbuf_map[j]);
2345                         }
2346                         bus_dma_tag_destroy(rxr->rx_mbuf_tag);
2347                         rxr->rx_mbuf_tag = NULL;
2348
2349                         device_printf(rxr->sc->bce_dev, "Unable to create "
2350                             "%dth RX mbuf DMA map!\n", i);
2351                         return rc;
2352                 }
2353         }
2354         return 0;
2355 }
2356
2357
2358 /****************************************************************************/
2359 /* Allocate any DMA memory needed by the driver.                            */
2360 /*                                                                          */
2361 /* Allocates DMA memory needed for the various global structures needed by  */
2362 /* hardware.                                                                */
2363 /*                                                                          */
2364 /* Memory alignment requirements:                                           */
2365 /* -----------------+----------+----------+----------+----------+           */
2366 /*  Data Structure  |   5706   |   5708   |   5709   |   5716   |           */
2367 /* -----------------+----------+----------+----------+----------+           */
2368 /* Status Block     | 8 bytes  | 8 bytes  | 16 bytes | 16 bytes |           */
2369 /* Statistics Block | 8 bytes  | 8 bytes  | 16 bytes | 16 bytes |           */
2370 /* RX Buffers       | 16 bytes | 16 bytes | 16 bytes | 16 bytes |           */
2371 /* PG Buffers       |   none   |   none   |   none   |   none   |           */
2372 /* TX Buffers       |   none   |   none   |   none   |   none   |           */
2373 /* Chain Pages(1)   |   4KiB   |   4KiB   |   4KiB   |   4KiB   |           */
2374 /* Context Pages(1) |   N/A    |   N/A    |   4KiB   |   4KiB   |           */
2375 /* -----------------+----------+----------+----------+----------+           */
2376 /*                                                                          */
2377 /* (1) Must align with CPU page size (BCM_PAGE_SZIE).                       */
2378 /*                                                                          */
2379 /* Returns:                                                                 */
2380 /*   0 for success, positive value for failure.                             */
2381 /****************************************************************************/
2382 static int
2383 bce_dma_alloc(struct bce_softc *sc)
2384 {
2385         struct ifnet *ifp = &sc->arpcom.ac_if;
2386         int i, rc = 0;
2387         bus_addr_t busaddr, max_busaddr;
2388         bus_size_t status_align, stats_align;
2389
2390         /*
2391          * The embedded PCIe to PCI-X bridge (EPB) 
2392          * in the 5708 cannot address memory above 
2393          * 40 bits (E7_5708CB1_23043 & E6_5708SB1_23043). 
2394          */
2395         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5708)
2396                 max_busaddr = BCE_BUS_SPACE_MAXADDR;
2397         else
2398                 max_busaddr = BUS_SPACE_MAXADDR;
2399
2400         /*
2401          * BCM5709 and BCM5716 uses host memory as cache for context memory.
2402          */
2403         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
2404             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
2405                 sc->ctx_pages = BCE_CTX_BLK_SZ / BCM_PAGE_SIZE;
2406                 if (sc->ctx_pages == 0)
2407                         sc->ctx_pages = 1;
2408                 if (sc->ctx_pages > BCE_CTX_PAGES) {
2409                         device_printf(sc->bce_dev, "excessive ctx pages %d\n",
2410                             sc->ctx_pages);
2411                         return ENOMEM;
2412                 }
2413                 status_align = 16;
2414                 stats_align = 16;
2415         } else {
2416                 status_align = 8;
2417                 stats_align = 8;
2418         }
2419
2420         /*
2421          * Allocate the parent bus DMA tag appropriate for PCI.
2422          */
2423         rc = bus_dma_tag_create(NULL, 1, BCE_DMA_BOUNDARY,
2424                                 max_busaddr, BUS_SPACE_MAXADDR,
2425                                 NULL, NULL,
2426                                 BUS_SPACE_MAXSIZE_32BIT, 0,
2427                                 BUS_SPACE_MAXSIZE_32BIT,
2428                                 0, &sc->parent_tag);
2429         if (rc != 0) {
2430                 if_printf(ifp, "Could not allocate parent DMA tag!\n");
2431                 return rc;
2432         }
2433
2434         /*
2435          * Allocate status block.
2436          */
2437         sc->status_block = bus_dmamem_coherent_any(sc->parent_tag,
2438                                 status_align, BCE_STATUS_BLK_SZ,
2439                                 BUS_DMA_WAITOK | BUS_DMA_ZERO,
2440                                 &sc->status_tag, &sc->status_map,
2441                                 &sc->status_block_paddr);
2442         if (sc->status_block == NULL) {
2443                 if_printf(ifp, "Could not allocate status block!\n");
2444                 return ENOMEM;
2445         }
2446
2447         /*
2448          * Allocate statistics block.
2449          */
2450         sc->stats_block = bus_dmamem_coherent_any(sc->parent_tag,
2451                                 stats_align, BCE_STATS_BLK_SZ,
2452                                 BUS_DMA_WAITOK | BUS_DMA_ZERO,
2453                                 &sc->stats_tag, &sc->stats_map,
2454                                 &sc->stats_block_paddr);
2455         if (sc->stats_block == NULL) {
2456                 if_printf(ifp, "Could not allocate statistics block!\n");
2457                 return ENOMEM;
2458         }
2459
2460         /*
2461          * Allocate context block, if needed
2462          */
2463         if (sc->ctx_pages != 0) {
2464                 rc = bus_dma_tag_create(sc->parent_tag, BCM_PAGE_SIZE, 0,
2465                                         BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
2466                                         NULL, NULL,
2467                                         BCM_PAGE_SIZE, 1, BCM_PAGE_SIZE,
2468                                         0, &sc->ctx_tag);
2469                 if (rc != 0) {
2470                         if_printf(ifp, "Could not allocate "
2471                                   "context block DMA tag!\n");
2472                         return rc;
2473                 }
2474
2475                 for (i = 0; i < sc->ctx_pages; i++) {
2476                         rc = bus_dmamem_alloc(sc->ctx_tag,
2477                                               (void **)&sc->ctx_block[i],
2478                                               BUS_DMA_WAITOK | BUS_DMA_ZERO |
2479                                               BUS_DMA_COHERENT,
2480                                               &sc->ctx_map[i]);
2481                         if (rc != 0) {
2482                                 if_printf(ifp, "Could not allocate %dth context "
2483                                           "DMA memory!\n", i);
2484                                 return rc;
2485                         }
2486
2487                         rc = bus_dmamap_load(sc->ctx_tag, sc->ctx_map[i],
2488                                              sc->ctx_block[i], BCM_PAGE_SIZE,
2489                                              bce_dma_map_addr, &busaddr,
2490                                              BUS_DMA_WAITOK);
2491                         if (rc != 0) {
2492                                 if (rc == EINPROGRESS) {
2493                                         panic("%s coherent memory loading "
2494                                               "is still in progress!", ifp->if_xname);
2495                                 }
2496                                 if_printf(ifp, "Could not map %dth context "
2497                                           "DMA memory!\n", i);
2498                                 bus_dmamem_free(sc->ctx_tag, sc->ctx_block[i],
2499                                                 sc->ctx_map[i]);
2500                                 sc->ctx_block[i] = NULL;
2501                                 return rc;
2502                         }
2503                         sc->ctx_paddr[i] = busaddr;
2504                 }
2505         }
2506
2507         sc->tx_rings = kmalloc_cachealign(
2508             sizeof(struct bce_tx_ring) * sc->ring_cnt, M_DEVBUF,
2509             M_WAITOK | M_ZERO);
2510         for (i = 0; i < sc->ring_cnt; ++i) {
2511                 sc->tx_rings[i].sc = sc;
2512
2513                 rc = bce_create_tx_ring(&sc->tx_rings[i]);
2514                 if (rc != 0) {
2515                         device_printf(sc->bce_dev,
2516                             "can't create %dth tx ring\n", i);
2517                         return rc;
2518                 }
2519         }
2520
2521         sc->rx_rings = kmalloc_cachealign(
2522             sizeof(struct bce_rx_ring) * sc->ring_cnt, M_DEVBUF,
2523             M_WAITOK | M_ZERO);
2524         for (i = 0; i < sc->ring_cnt; ++i) {
2525                 sc->rx_rings[i].sc = sc;
2526
2527                 rc = bce_create_rx_ring(&sc->rx_rings[i]);
2528                 if (rc != 0) {
2529                         device_printf(sc->bce_dev,
2530                             "can't create %dth rx ring\n", i);
2531                         return rc;
2532                 }
2533         }
2534
2535         return 0;
2536 }
2537
2538
2539 /****************************************************************************/
2540 /* Firmware synchronization.                                                */
2541 /*                                                                          */
2542 /* Before performing certain events such as a chip reset, synchronize with  */
2543 /* the firmware first.                                                      */
2544 /*                                                                          */
2545 /* Returns:                                                                 */
2546 /*   0 for success, positive value for failure.                             */
2547 /****************************************************************************/
2548 static int
2549 bce_fw_sync(struct bce_softc *sc, uint32_t msg_data)
2550 {
2551         int i, rc = 0;
2552         uint32_t val;
2553
2554         /* Don't waste any time if we've timed out before. */
2555         if (sc->bce_fw_timed_out)
2556                 return EBUSY;
2557
2558         /* Increment the message sequence number. */
2559         sc->bce_fw_wr_seq++;
2560         msg_data |= sc->bce_fw_wr_seq;
2561
2562         /* Send the message to the bootcode driver mailbox. */
2563         bce_shmem_wr(sc, BCE_DRV_MB, msg_data);
2564
2565         /* Wait for the bootcode to acknowledge the message. */
2566         for (i = 0; i < FW_ACK_TIME_OUT_MS; i++) {
2567                 /* Check for a response in the bootcode firmware mailbox. */
2568                 val = bce_shmem_rd(sc, BCE_FW_MB);
2569                 if ((val & BCE_FW_MSG_ACK) == (msg_data & BCE_DRV_MSG_SEQ))
2570                         break;
2571                 DELAY(1000);
2572         }
2573
2574         /* If we've timed out, tell the bootcode that we've stopped waiting. */
2575         if ((val & BCE_FW_MSG_ACK) != (msg_data & BCE_DRV_MSG_SEQ) &&
2576             (msg_data & BCE_DRV_MSG_DATA) != BCE_DRV_MSG_DATA_WAIT0) {
2577                 if_printf(&sc->arpcom.ac_if,
2578                           "Firmware synchronization timeout! "
2579                           "msg_data = 0x%08X\n", msg_data);
2580
2581                 msg_data &= ~BCE_DRV_MSG_CODE;
2582                 msg_data |= BCE_DRV_MSG_CODE_FW_TIMEOUT;
2583
2584                 bce_shmem_wr(sc, BCE_DRV_MB, msg_data);
2585
2586                 sc->bce_fw_timed_out = 1;
2587                 rc = EBUSY;
2588         }
2589         return rc;
2590 }
2591
2592
2593 /****************************************************************************/
2594 /* Load Receive Virtual 2 Physical (RV2P) processor firmware.               */
2595 /*                                                                          */
2596 /* Returns:                                                                 */
2597 /*   Nothing.                                                               */
2598 /****************************************************************************/
2599 static void
2600 bce_load_rv2p_fw(struct bce_softc *sc, uint32_t *rv2p_code,
2601                  uint32_t rv2p_code_len, uint32_t rv2p_proc)
2602 {
2603         int i;
2604         uint32_t val;
2605
2606         for (i = 0; i < rv2p_code_len; i += 8) {
2607                 REG_WR(sc, BCE_RV2P_INSTR_HIGH, *rv2p_code);
2608                 rv2p_code++;
2609                 REG_WR(sc, BCE_RV2P_INSTR_LOW, *rv2p_code);
2610                 rv2p_code++;
2611
2612                 if (rv2p_proc == RV2P_PROC1) {
2613                         val = (i / 8) | BCE_RV2P_PROC1_ADDR_CMD_RDWR;
2614                         REG_WR(sc, BCE_RV2P_PROC1_ADDR_CMD, val);
2615                 } else {
2616                         val = (i / 8) | BCE_RV2P_PROC2_ADDR_CMD_RDWR;
2617                         REG_WR(sc, BCE_RV2P_PROC2_ADDR_CMD, val);
2618                 }
2619         }
2620
2621         /* Reset the processor, un-stall is done later. */
2622         if (rv2p_proc == RV2P_PROC1)
2623                 REG_WR(sc, BCE_RV2P_COMMAND, BCE_RV2P_COMMAND_PROC1_RESET);
2624         else
2625                 REG_WR(sc, BCE_RV2P_COMMAND, BCE_RV2P_COMMAND_PROC2_RESET);
2626 }
2627
2628
2629 /****************************************************************************/
2630 /* Load RISC processor firmware.                                            */
2631 /*                                                                          */
2632 /* Loads firmware from the file if_bcefw.h into the scratchpad memory       */
2633 /* associated with a particular processor.                                  */
2634 /*                                                                          */
2635 /* Returns:                                                                 */
2636 /*   Nothing.                                                               */
2637 /****************************************************************************/
2638 static void
2639 bce_load_cpu_fw(struct bce_softc *sc, struct cpu_reg *cpu_reg,
2640                 struct fw_info *fw)
2641 {
2642         uint32_t offset;
2643         int j;
2644
2645         bce_halt_cpu(sc, cpu_reg);
2646
2647         /* Load the Text area. */
2648         offset = cpu_reg->spad_base + (fw->text_addr - cpu_reg->mips_view_base);
2649         if (fw->text) {
2650                 for (j = 0; j < (fw->text_len / 4); j++, offset += 4)
2651                         REG_WR_IND(sc, offset, fw->text[j]);
2652         }
2653
2654         /* Load the Data area. */
2655         offset = cpu_reg->spad_base + (fw->data_addr - cpu_reg->mips_view_base);
2656         if (fw->data) {
2657                 for (j = 0; j < (fw->data_len / 4); j++, offset += 4)
2658                         REG_WR_IND(sc, offset, fw->data[j]);
2659         }
2660
2661         /* Load the SBSS area. */
2662         offset = cpu_reg->spad_base + (fw->sbss_addr - cpu_reg->mips_view_base);
2663         if (fw->sbss) {
2664                 for (j = 0; j < (fw->sbss_len / 4); j++, offset += 4)
2665                         REG_WR_IND(sc, offset, fw->sbss[j]);
2666         }
2667
2668         /* Load the BSS area. */
2669         offset = cpu_reg->spad_base + (fw->bss_addr - cpu_reg->mips_view_base);
2670         if (fw->bss) {
2671                 for (j = 0; j < (fw->bss_len/4); j++, offset += 4)
2672                         REG_WR_IND(sc, offset, fw->bss[j]);
2673         }
2674
2675         /* Load the Read-Only area. */
2676         offset = cpu_reg->spad_base +
2677                 (fw->rodata_addr - cpu_reg->mips_view_base);
2678         if (fw->rodata) {
2679                 for (j = 0; j < (fw->rodata_len / 4); j++, offset += 4)
2680                         REG_WR_IND(sc, offset, fw->rodata[j]);
2681         }
2682
2683         /* Clear the pre-fetch instruction and set the FW start address. */
2684         REG_WR_IND(sc, cpu_reg->inst, 0);
2685         REG_WR_IND(sc, cpu_reg->pc, fw->start_addr);
2686 }
2687
2688
2689 /****************************************************************************/
2690 /* Starts the RISC processor.                                               */
2691 /*                                                                          */
2692 /* Assumes the CPU starting address has already been set.                   */
2693 /*                                                                          */
2694 /* Returns:                                                                 */
2695 /*   Nothing.                                                               */
2696 /****************************************************************************/
2697 static void
2698 bce_start_cpu(struct bce_softc *sc, struct cpu_reg *cpu_reg)
2699 {
2700         uint32_t val;
2701
2702         /* Start the CPU. */
2703         val = REG_RD_IND(sc, cpu_reg->mode);
2704         val &= ~cpu_reg->mode_value_halt;
2705         REG_WR_IND(sc, cpu_reg->state, cpu_reg->state_value_clear);
2706         REG_WR_IND(sc, cpu_reg->mode, val);
2707 }
2708
2709
2710 /****************************************************************************/
2711 /* Halts the RISC processor.                                                */
2712 /*                                                                          */
2713 /* Returns:                                                                 */
2714 /*   Nothing.                                                               */
2715 /****************************************************************************/
2716 static void
2717 bce_halt_cpu(struct bce_softc *sc, struct cpu_reg *cpu_reg)
2718 {
2719         uint32_t val;
2720
2721         /* Halt the CPU. */
2722         val = REG_RD_IND(sc, cpu_reg->mode);
2723         val |= cpu_reg->mode_value_halt;
2724         REG_WR_IND(sc, cpu_reg->mode, val);
2725         REG_WR_IND(sc, cpu_reg->state, cpu_reg->state_value_clear);
2726 }
2727
2728
2729 /****************************************************************************/
2730 /* Start the RX CPU.                                                        */
2731 /*                                                                          */
2732 /* Returns:                                                                 */
2733 /*   Nothing.                                                               */
2734 /****************************************************************************/
2735 static void
2736 bce_start_rxp_cpu(struct bce_softc *sc)
2737 {
2738         struct cpu_reg cpu_reg;
2739
2740         cpu_reg.mode = BCE_RXP_CPU_MODE;
2741         cpu_reg.mode_value_halt = BCE_RXP_CPU_MODE_SOFT_HALT;
2742         cpu_reg.mode_value_sstep = BCE_RXP_CPU_MODE_STEP_ENA;
2743         cpu_reg.state = BCE_RXP_CPU_STATE;
2744         cpu_reg.state_value_clear = 0xffffff;
2745         cpu_reg.gpr0 = BCE_RXP_CPU_REG_FILE;
2746         cpu_reg.evmask = BCE_RXP_CPU_EVENT_MASK;
2747         cpu_reg.pc = BCE_RXP_CPU_PROGRAM_COUNTER;
2748         cpu_reg.inst = BCE_RXP_CPU_INSTRUCTION;
2749         cpu_reg.bp = BCE_RXP_CPU_HW_BREAKPOINT;
2750         cpu_reg.spad_base = BCE_RXP_SCRATCH;
2751         cpu_reg.mips_view_base = 0x8000000;
2752
2753         bce_start_cpu(sc, &cpu_reg);
2754 }
2755
2756
2757 /****************************************************************************/
2758 /* Initialize the RX CPU.                                                   */
2759 /*                                                                          */
2760 /* Returns:                                                                 */
2761 /*   Nothing.                                                               */
2762 /****************************************************************************/
2763 static void
2764 bce_init_rxp_cpu(struct bce_softc *sc)
2765 {
2766         struct cpu_reg cpu_reg;
2767         struct fw_info fw;
2768
2769         cpu_reg.mode = BCE_RXP_CPU_MODE;
2770         cpu_reg.mode_value_halt = BCE_RXP_CPU_MODE_SOFT_HALT;
2771         cpu_reg.mode_value_sstep = BCE_RXP_CPU_MODE_STEP_ENA;
2772         cpu_reg.state = BCE_RXP_CPU_STATE;
2773         cpu_reg.state_value_clear = 0xffffff;
2774         cpu_reg.gpr0 = BCE_RXP_CPU_REG_FILE;
2775         cpu_reg.evmask = BCE_RXP_CPU_EVENT_MASK;
2776         cpu_reg.pc = BCE_RXP_CPU_PROGRAM_COUNTER;
2777         cpu_reg.inst = BCE_RXP_CPU_INSTRUCTION;
2778         cpu_reg.bp = BCE_RXP_CPU_HW_BREAKPOINT;
2779         cpu_reg.spad_base = BCE_RXP_SCRATCH;
2780         cpu_reg.mips_view_base = 0x8000000;
2781
2782         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
2783             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
2784                 fw.ver_major = bce_RXP_b09FwReleaseMajor;
2785                 fw.ver_minor = bce_RXP_b09FwReleaseMinor;
2786                 fw.ver_fix = bce_RXP_b09FwReleaseFix;
2787                 fw.start_addr = bce_RXP_b09FwStartAddr;
2788
2789                 fw.text_addr = bce_RXP_b09FwTextAddr;
2790                 fw.text_len = bce_RXP_b09FwTextLen;
2791                 fw.text_index = 0;
2792                 fw.text = bce_RXP_b09FwText;
2793
2794                 fw.data_addr = bce_RXP_b09FwDataAddr;
2795                 fw.data_len = bce_RXP_b09FwDataLen;
2796                 fw.data_index = 0;
2797                 fw.data = bce_RXP_b09FwData;
2798
2799                 fw.sbss_addr = bce_RXP_b09FwSbssAddr;
2800                 fw.sbss_len = bce_RXP_b09FwSbssLen;
2801                 fw.sbss_index = 0;
2802                 fw.sbss = bce_RXP_b09FwSbss;
2803
2804                 fw.bss_addr = bce_RXP_b09FwBssAddr;
2805                 fw.bss_len = bce_RXP_b09FwBssLen;
2806                 fw.bss_index = 0;
2807                 fw.bss = bce_RXP_b09FwBss;
2808
2809                 fw.rodata_addr = bce_RXP_b09FwRodataAddr;
2810                 fw.rodata_len = bce_RXP_b09FwRodataLen;
2811                 fw.rodata_index = 0;
2812                 fw.rodata = bce_RXP_b09FwRodata;
2813         } else {
2814                 fw.ver_major = bce_RXP_b06FwReleaseMajor;
2815                 fw.ver_minor = bce_RXP_b06FwReleaseMinor;
2816                 fw.ver_fix = bce_RXP_b06FwReleaseFix;
2817                 fw.start_addr = bce_RXP_b06FwStartAddr;
2818
2819                 fw.text_addr = bce_RXP_b06FwTextAddr;
2820                 fw.text_len = bce_RXP_b06FwTextLen;
2821                 fw.text_index = 0;
2822                 fw.text = bce_RXP_b06FwText;
2823
2824                 fw.data_addr = bce_RXP_b06FwDataAddr;
2825                 fw.data_len = bce_RXP_b06FwDataLen;
2826                 fw.data_index = 0;
2827                 fw.data = bce_RXP_b06FwData;
2828
2829                 fw.sbss_addr = bce_RXP_b06FwSbssAddr;
2830                 fw.sbss_len = bce_RXP_b06FwSbssLen;
2831                 fw.sbss_index = 0;
2832                 fw.sbss = bce_RXP_b06FwSbss;
2833
2834                 fw.bss_addr = bce_RXP_b06FwBssAddr;
2835                 fw.bss_len = bce_RXP_b06FwBssLen;
2836                 fw.bss_index = 0;
2837                 fw.bss = bce_RXP_b06FwBss;
2838
2839                 fw.rodata_addr = bce_RXP_b06FwRodataAddr;
2840                 fw.rodata_len = bce_RXP_b06FwRodataLen;
2841                 fw.rodata_index = 0;
2842                 fw.rodata = bce_RXP_b06FwRodata;
2843         }
2844
2845         bce_load_cpu_fw(sc, &cpu_reg, &fw);
2846         /* Delay RXP start until initialization is complete. */
2847 }
2848
2849
2850 /****************************************************************************/
2851 /* Initialize the TX CPU.                                                   */
2852 /*                                                                          */
2853 /* Returns:                                                                 */
2854 /*   Nothing.                                                               */
2855 /****************************************************************************/
2856 static void
2857 bce_init_txp_cpu(struct bce_softc *sc)
2858 {
2859         struct cpu_reg cpu_reg;
2860         struct fw_info fw;
2861
2862         cpu_reg.mode = BCE_TXP_CPU_MODE;
2863         cpu_reg.mode_value_halt = BCE_TXP_CPU_MODE_SOFT_HALT;
2864         cpu_reg.mode_value_sstep = BCE_TXP_CPU_MODE_STEP_ENA;
2865         cpu_reg.state = BCE_TXP_CPU_STATE;
2866         cpu_reg.state_value_clear = 0xffffff;
2867         cpu_reg.gpr0 = BCE_TXP_CPU_REG_FILE;
2868         cpu_reg.evmask = BCE_TXP_CPU_EVENT_MASK;
2869         cpu_reg.pc = BCE_TXP_CPU_PROGRAM_COUNTER;
2870         cpu_reg.inst = BCE_TXP_CPU_INSTRUCTION;
2871         cpu_reg.bp = BCE_TXP_CPU_HW_BREAKPOINT;
2872         cpu_reg.spad_base = BCE_TXP_SCRATCH;
2873         cpu_reg.mips_view_base = 0x8000000;
2874
2875         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
2876             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
2877                 fw.ver_major = bce_TXP_b09FwReleaseMajor;
2878                 fw.ver_minor = bce_TXP_b09FwReleaseMinor;
2879                 fw.ver_fix = bce_TXP_b09FwReleaseFix;
2880                 fw.start_addr = bce_TXP_b09FwStartAddr;
2881
2882                 fw.text_addr = bce_TXP_b09FwTextAddr;
2883                 fw.text_len = bce_TXP_b09FwTextLen;
2884                 fw.text_index = 0;
2885                 fw.text = bce_TXP_b09FwText;
2886
2887                 fw.data_addr = bce_TXP_b09FwDataAddr;
2888                 fw.data_len = bce_TXP_b09FwDataLen;
2889                 fw.data_index = 0;
2890                 fw.data = bce_TXP_b09FwData;
2891
2892                 fw.sbss_addr = bce_TXP_b09FwSbssAddr;
2893                 fw.sbss_len = bce_TXP_b09FwSbssLen;
2894                 fw.sbss_index = 0;
2895                 fw.sbss = bce_TXP_b09FwSbss;
2896
2897                 fw.bss_addr = bce_TXP_b09FwBssAddr;
2898                 fw.bss_len = bce_TXP_b09FwBssLen;
2899                 fw.bss_index = 0;
2900                 fw.bss = bce_TXP_b09FwBss;
2901
2902                 fw.rodata_addr = bce_TXP_b09FwRodataAddr;
2903                 fw.rodata_len = bce_TXP_b09FwRodataLen;
2904                 fw.rodata_index = 0;
2905                 fw.rodata = bce_TXP_b09FwRodata;
2906         } else {
2907                 fw.ver_major = bce_TXP_b06FwReleaseMajor;
2908                 fw.ver_minor = bce_TXP_b06FwReleaseMinor;
2909                 fw.ver_fix = bce_TXP_b06FwReleaseFix;
2910                 fw.start_addr = bce_TXP_b06FwStartAddr;
2911
2912                 fw.text_addr = bce_TXP_b06FwTextAddr;
2913                 fw.text_len = bce_TXP_b06FwTextLen;
2914                 fw.text_index = 0;
2915                 fw.text = bce_TXP_b06FwText;
2916
2917                 fw.data_addr = bce_TXP_b06FwDataAddr;
2918                 fw.data_len = bce_TXP_b06FwDataLen;
2919                 fw.data_index = 0;
2920                 fw.data = bce_TXP_b06FwData;
2921
2922                 fw.sbss_addr = bce_TXP_b06FwSbssAddr;
2923                 fw.sbss_len = bce_TXP_b06FwSbssLen;
2924                 fw.sbss_index = 0;
2925                 fw.sbss = bce_TXP_b06FwSbss;
2926
2927                 fw.bss_addr = bce_TXP_b06FwBssAddr;
2928                 fw.bss_len = bce_TXP_b06FwBssLen;
2929                 fw.bss_index = 0;
2930                 fw.bss = bce_TXP_b06FwBss;
2931
2932                 fw.rodata_addr = bce_TXP_b06FwRodataAddr;
2933                 fw.rodata_len = bce_TXP_b06FwRodataLen;
2934                 fw.rodata_index = 0;
2935                 fw.rodata = bce_TXP_b06FwRodata;
2936         }
2937
2938         bce_load_cpu_fw(sc, &cpu_reg, &fw);
2939         bce_start_cpu(sc, &cpu_reg);
2940 }
2941
2942
2943 /****************************************************************************/
2944 /* Initialize the TPAT CPU.                                                 */
2945 /*                                                                          */
2946 /* Returns:                                                                 */
2947 /*   Nothing.                                                               */
2948 /****************************************************************************/
2949 static void
2950 bce_init_tpat_cpu(struct bce_softc *sc)
2951 {
2952         struct cpu_reg cpu_reg;
2953         struct fw_info fw;
2954
2955         cpu_reg.mode = BCE_TPAT_CPU_MODE;
2956         cpu_reg.mode_value_halt = BCE_TPAT_CPU_MODE_SOFT_HALT;
2957         cpu_reg.mode_value_sstep = BCE_TPAT_CPU_MODE_STEP_ENA;
2958         cpu_reg.state = BCE_TPAT_CPU_STATE;
2959         cpu_reg.state_value_clear = 0xffffff;
2960         cpu_reg.gpr0 = BCE_TPAT_CPU_REG_FILE;
2961         cpu_reg.evmask = BCE_TPAT_CPU_EVENT_MASK;
2962         cpu_reg.pc = BCE_TPAT_CPU_PROGRAM_COUNTER;
2963         cpu_reg.inst = BCE_TPAT_CPU_INSTRUCTION;
2964         cpu_reg.bp = BCE_TPAT_CPU_HW_BREAKPOINT;
2965         cpu_reg.spad_base = BCE_TPAT_SCRATCH;
2966         cpu_reg.mips_view_base = 0x8000000;
2967
2968         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
2969             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
2970                 fw.ver_major = bce_TPAT_b09FwReleaseMajor;
2971                 fw.ver_minor = bce_TPAT_b09FwReleaseMinor;
2972                 fw.ver_fix = bce_TPAT_b09FwReleaseFix;
2973                 fw.start_addr = bce_TPAT_b09FwStartAddr;
2974
2975                 fw.text_addr = bce_TPAT_b09FwTextAddr;
2976                 fw.text_len = bce_TPAT_b09FwTextLen;
2977                 fw.text_index = 0;
2978                 fw.text = bce_TPAT_b09FwText;
2979
2980                 fw.data_addr = bce_TPAT_b09FwDataAddr;
2981                 fw.data_len = bce_TPAT_b09FwDataLen;
2982                 fw.data_index = 0;
2983                 fw.data = bce_TPAT_b09FwData;
2984
2985                 fw.sbss_addr = bce_TPAT_b09FwSbssAddr;
2986                 fw.sbss_len = bce_TPAT_b09FwSbssLen;
2987                 fw.sbss_index = 0;
2988                 fw.sbss = bce_TPAT_b09FwSbss;
2989
2990                 fw.bss_addr = bce_TPAT_b09FwBssAddr;
2991                 fw.bss_len = bce_TPAT_b09FwBssLen;
2992                 fw.bss_index = 0;
2993                 fw.bss = bce_TPAT_b09FwBss;
2994
2995                 fw.rodata_addr = bce_TPAT_b09FwRodataAddr;
2996                 fw.rodata_len = bce_TPAT_b09FwRodataLen;
2997                 fw.rodata_index = 0;
2998                 fw.rodata = bce_TPAT_b09FwRodata;
2999         } else {
3000                 fw.ver_major = bce_TPAT_b06FwReleaseMajor;
3001                 fw.ver_minor = bce_TPAT_b06FwReleaseMinor;
3002                 fw.ver_fix = bce_TPAT_b06FwReleaseFix;
3003                 fw.start_addr = bce_TPAT_b06FwStartAddr;
3004
3005                 fw.text_addr = bce_TPAT_b06FwTextAddr;
3006                 fw.text_len = bce_TPAT_b06FwTextLen;
3007                 fw.text_index = 0;
3008                 fw.text = bce_TPAT_b06FwText;
3009
3010                 fw.data_addr = bce_TPAT_b06FwDataAddr;
3011                 fw.data_len = bce_TPAT_b06FwDataLen;
3012                 fw.data_index = 0;
3013                 fw.data = bce_TPAT_b06FwData;
3014
3015                 fw.sbss_addr = bce_TPAT_b06FwSbssAddr;
3016                 fw.sbss_len = bce_TPAT_b06FwSbssLen;
3017                 fw.sbss_index = 0;
3018                 fw.sbss = bce_TPAT_b06FwSbss;
3019
3020                 fw.bss_addr = bce_TPAT_b06FwBssAddr;
3021                 fw.bss_len = bce_TPAT_b06FwBssLen;
3022                 fw.bss_index = 0;
3023                 fw.bss = bce_TPAT_b06FwBss;
3024
3025                 fw.rodata_addr = bce_TPAT_b06FwRodataAddr;
3026                 fw.rodata_len = bce_TPAT_b06FwRodataLen;
3027                 fw.rodata_index = 0;
3028                 fw.rodata = bce_TPAT_b06FwRodata;
3029         }
3030
3031         bce_load_cpu_fw(sc, &cpu_reg, &fw);
3032         bce_start_cpu(sc, &cpu_reg);
3033 }
3034
3035
3036 /****************************************************************************/
3037 /* Initialize the CP CPU.                                                   */
3038 /*                                                                          */
3039 /* Returns:                                                                 */
3040 /*   Nothing.                                                               */
3041 /****************************************************************************/
3042 static void
3043 bce_init_cp_cpu(struct bce_softc *sc)
3044 {
3045         struct cpu_reg cpu_reg;
3046         struct fw_info fw;
3047
3048         cpu_reg.mode = BCE_CP_CPU_MODE;
3049         cpu_reg.mode_value_halt = BCE_CP_CPU_MODE_SOFT_HALT;
3050         cpu_reg.mode_value_sstep = BCE_CP_CPU_MODE_STEP_ENA;
3051         cpu_reg.state = BCE_CP_CPU_STATE;
3052         cpu_reg.state_value_clear = 0xffffff;
3053         cpu_reg.gpr0 = BCE_CP_CPU_REG_FILE;
3054         cpu_reg.evmask = BCE_CP_CPU_EVENT_MASK;
3055         cpu_reg.pc = BCE_CP_CPU_PROGRAM_COUNTER;
3056         cpu_reg.inst = BCE_CP_CPU_INSTRUCTION;
3057         cpu_reg.bp = BCE_CP_CPU_HW_BREAKPOINT;
3058         cpu_reg.spad_base = BCE_CP_SCRATCH;
3059         cpu_reg.mips_view_base = 0x8000000;
3060
3061         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3062             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3063                 fw.ver_major = bce_CP_b09FwReleaseMajor;
3064                 fw.ver_minor = bce_CP_b09FwReleaseMinor;
3065                 fw.ver_fix = bce_CP_b09FwReleaseFix;
3066                 fw.start_addr = bce_CP_b09FwStartAddr;
3067
3068                 fw.text_addr = bce_CP_b09FwTextAddr;
3069                 fw.text_len = bce_CP_b09FwTextLen;
3070                 fw.text_index = 0;
3071                 fw.text = bce_CP_b09FwText;
3072
3073                 fw.data_addr = bce_CP_b09FwDataAddr;
3074                 fw.data_len = bce_CP_b09FwDataLen;
3075                 fw.data_index = 0;
3076                 fw.data = bce_CP_b09FwData;
3077
3078                 fw.sbss_addr = bce_CP_b09FwSbssAddr;
3079                 fw.sbss_len = bce_CP_b09FwSbssLen;
3080                 fw.sbss_index = 0;
3081                 fw.sbss = bce_CP_b09FwSbss;
3082
3083                 fw.bss_addr = bce_CP_b09FwBssAddr;
3084                 fw.bss_len = bce_CP_b09FwBssLen;
3085                 fw.bss_index = 0;
3086                 fw.bss = bce_CP_b09FwBss;
3087
3088                 fw.rodata_addr = bce_CP_b09FwRodataAddr;
3089                 fw.rodata_len = bce_CP_b09FwRodataLen;
3090                 fw.rodata_index = 0;
3091                 fw.rodata = bce_CP_b09FwRodata;
3092         } else {
3093                 fw.ver_major = bce_CP_b06FwReleaseMajor;
3094                 fw.ver_minor = bce_CP_b06FwReleaseMinor;
3095                 fw.ver_fix = bce_CP_b06FwReleaseFix;
3096                 fw.start_addr = bce_CP_b06FwStartAddr;
3097
3098                 fw.text_addr = bce_CP_b06FwTextAddr;
3099                 fw.text_len = bce_CP_b06FwTextLen;
3100                 fw.text_index = 0;
3101                 fw.text = bce_CP_b06FwText;
3102
3103                 fw.data_addr = bce_CP_b06FwDataAddr;
3104                 fw.data_len = bce_CP_b06FwDataLen;
3105                 fw.data_index = 0;
3106                 fw.data = bce_CP_b06FwData;
3107
3108                 fw.sbss_addr = bce_CP_b06FwSbssAddr;
3109                 fw.sbss_len = bce_CP_b06FwSbssLen;
3110                 fw.sbss_index = 0;
3111                 fw.sbss = bce_CP_b06FwSbss;
3112
3113                 fw.bss_addr = bce_CP_b06FwBssAddr;
3114                 fw.bss_len = bce_CP_b06FwBssLen;
3115                 fw.bss_index = 0;
3116                 fw.bss = bce_CP_b06FwBss;
3117
3118                 fw.rodata_addr = bce_CP_b06FwRodataAddr;
3119                 fw.rodata_len = bce_CP_b06FwRodataLen;
3120                 fw.rodata_index = 0;
3121                 fw.rodata = bce_CP_b06FwRodata;
3122         }
3123
3124         bce_load_cpu_fw(sc, &cpu_reg, &fw);
3125         bce_start_cpu(sc, &cpu_reg);
3126 }
3127
3128
3129 /****************************************************************************/
3130 /* Initialize the COM CPU.                                                 */
3131 /*                                                                          */
3132 /* Returns:                                                                 */
3133 /*   Nothing.                                                               */
3134 /****************************************************************************/
3135 static void
3136 bce_init_com_cpu(struct bce_softc *sc)
3137 {
3138         struct cpu_reg cpu_reg;
3139         struct fw_info fw;
3140
3141         cpu_reg.mode = BCE_COM_CPU_MODE;
3142         cpu_reg.mode_value_halt = BCE_COM_CPU_MODE_SOFT_HALT;
3143         cpu_reg.mode_value_sstep = BCE_COM_CPU_MODE_STEP_ENA;
3144         cpu_reg.state = BCE_COM_CPU_STATE;
3145         cpu_reg.state_value_clear = 0xffffff;
3146         cpu_reg.gpr0 = BCE_COM_CPU_REG_FILE;
3147         cpu_reg.evmask = BCE_COM_CPU_EVENT_MASK;
3148         cpu_reg.pc = BCE_COM_CPU_PROGRAM_COUNTER;
3149         cpu_reg.inst = BCE_COM_CPU_INSTRUCTION;
3150         cpu_reg.bp = BCE_COM_CPU_HW_BREAKPOINT;
3151         cpu_reg.spad_base = BCE_COM_SCRATCH;
3152         cpu_reg.mips_view_base = 0x8000000;
3153
3154         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3155             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3156                 fw.ver_major = bce_COM_b09FwReleaseMajor;
3157                 fw.ver_minor = bce_COM_b09FwReleaseMinor;
3158                 fw.ver_fix = bce_COM_b09FwReleaseFix;
3159                 fw.start_addr = bce_COM_b09FwStartAddr;
3160
3161                 fw.text_addr = bce_COM_b09FwTextAddr;
3162                 fw.text_len = bce_COM_b09FwTextLen;
3163                 fw.text_index = 0;
3164                 fw.text = bce_COM_b09FwText;
3165
3166                 fw.data_addr = bce_COM_b09FwDataAddr;
3167                 fw.data_len = bce_COM_b09FwDataLen;
3168                 fw.data_index = 0;
3169                 fw.data = bce_COM_b09FwData;
3170
3171                 fw.sbss_addr = bce_COM_b09FwSbssAddr;
3172                 fw.sbss_len = bce_COM_b09FwSbssLen;
3173                 fw.sbss_index = 0;
3174                 fw.sbss = bce_COM_b09FwSbss;
3175
3176                 fw.bss_addr = bce_COM_b09FwBssAddr;
3177                 fw.bss_len = bce_COM_b09FwBssLen;
3178                 fw.bss_index = 0;
3179                 fw.bss = bce_COM_b09FwBss;
3180
3181                 fw.rodata_addr = bce_COM_b09FwRodataAddr;
3182                 fw.rodata_len = bce_COM_b09FwRodataLen;
3183                 fw.rodata_index = 0;
3184                 fw.rodata = bce_COM_b09FwRodata;
3185         } else {
3186                 fw.ver_major = bce_COM_b06FwReleaseMajor;
3187                 fw.ver_minor = bce_COM_b06FwReleaseMinor;
3188                 fw.ver_fix = bce_COM_b06FwReleaseFix;
3189                 fw.start_addr = bce_COM_b06FwStartAddr;
3190
3191                 fw.text_addr = bce_COM_b06FwTextAddr;
3192                 fw.text_len = bce_COM_b06FwTextLen;
3193                 fw.text_index = 0;
3194                 fw.text = bce_COM_b06FwText;
3195
3196                 fw.data_addr = bce_COM_b06FwDataAddr;
3197                 fw.data_len = bce_COM_b06FwDataLen;
3198                 fw.data_index = 0;
3199                 fw.data = bce_COM_b06FwData;
3200
3201                 fw.sbss_addr = bce_COM_b06FwSbssAddr;
3202                 fw.sbss_len = bce_COM_b06FwSbssLen;
3203                 fw.sbss_index = 0;
3204                 fw.sbss = bce_COM_b06FwSbss;
3205
3206                 fw.bss_addr = bce_COM_b06FwBssAddr;
3207                 fw.bss_len = bce_COM_b06FwBssLen;
3208                 fw.bss_index = 0;
3209                 fw.bss = bce_COM_b06FwBss;
3210
3211                 fw.rodata_addr = bce_COM_b06FwRodataAddr;
3212                 fw.rodata_len = bce_COM_b06FwRodataLen;
3213                 fw.rodata_index = 0;
3214                 fw.rodata = bce_COM_b06FwRodata;
3215         }
3216
3217         bce_load_cpu_fw(sc, &cpu_reg, &fw);
3218         bce_start_cpu(sc, &cpu_reg);
3219 }
3220
3221
3222 /****************************************************************************/
3223 /* Initialize the RV2P, RX, TX, TPAT, COM, and CP CPUs.                     */
3224 /*                                                                          */
3225 /* Loads the firmware for each CPU and starts the CPU.                      */
3226 /*                                                                          */
3227 /* Returns:                                                                 */
3228 /*   Nothing.                                                               */
3229 /****************************************************************************/
3230 static void
3231 bce_init_cpus(struct bce_softc *sc)
3232 {
3233         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3234             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3235                 if (BCE_CHIP_REV(sc) == BCE_CHIP_REV_Ax) {
3236                         bce_load_rv2p_fw(sc, bce_xi90_rv2p_proc1,
3237                             sizeof(bce_xi90_rv2p_proc1), RV2P_PROC1);
3238                         bce_load_rv2p_fw(sc, bce_xi90_rv2p_proc2,
3239                             sizeof(bce_xi90_rv2p_proc2), RV2P_PROC2);
3240                 } else {
3241                         bce_load_rv2p_fw(sc, bce_xi_rv2p_proc1,
3242                             sizeof(bce_xi_rv2p_proc1), RV2P_PROC1);
3243                         bce_load_rv2p_fw(sc, bce_xi_rv2p_proc2,
3244                             sizeof(bce_xi_rv2p_proc2), RV2P_PROC2);
3245                 }
3246         } else {
3247                 bce_load_rv2p_fw(sc, bce_rv2p_proc1,
3248                     sizeof(bce_rv2p_proc1), RV2P_PROC1);
3249                 bce_load_rv2p_fw(sc, bce_rv2p_proc2,
3250                     sizeof(bce_rv2p_proc2), RV2P_PROC2);
3251         }
3252
3253         bce_init_rxp_cpu(sc);
3254         bce_init_txp_cpu(sc);
3255         bce_init_tpat_cpu(sc);
3256         bce_init_com_cpu(sc);
3257         bce_init_cp_cpu(sc);
3258 }
3259
3260
3261 /****************************************************************************/
3262 /* Initialize context memory.                                               */
3263 /*                                                                          */
3264 /* Clears the memory associated with each Context ID (CID).                 */
3265 /*                                                                          */
3266 /* Returns:                                                                 */
3267 /*   Nothing.                                                               */
3268 /****************************************************************************/
3269 static int
3270 bce_init_ctx(struct bce_softc *sc)
3271 {
3272         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3273             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3274                 /* DRC: Replace this constant value with a #define. */
3275                 int i, retry_cnt = 10;
3276                 uint32_t val;
3277
3278                 /*
3279                  * BCM5709 context memory may be cached
3280                  * in host memory so prepare the host memory
3281                  * for access.
3282                  */
3283                 val = BCE_CTX_COMMAND_ENABLED | BCE_CTX_COMMAND_MEM_INIT |
3284                     (1 << 12);
3285                 val |= (BCM_PAGE_BITS - 8) << 16;
3286                 REG_WR(sc, BCE_CTX_COMMAND, val);
3287
3288                 /* Wait for mem init command to complete. */
3289                 for (i = 0; i < retry_cnt; i++) {
3290                         val = REG_RD(sc, BCE_CTX_COMMAND);
3291                         if (!(val & BCE_CTX_COMMAND_MEM_INIT))
3292                                 break;
3293                         DELAY(2);
3294                 }
3295                 if (i == retry_cnt) {
3296                         device_printf(sc->bce_dev,
3297                             "Context memory initialization failed!\n");
3298                         return ETIMEDOUT;
3299                 }
3300
3301                 for (i = 0; i < sc->ctx_pages; i++) {
3302                         int j;
3303
3304                         /*
3305                          * Set the physical address of the context
3306                          * memory cache.
3307                          */
3308                         REG_WR(sc, BCE_CTX_HOST_PAGE_TBL_DATA0,
3309                             BCE_ADDR_LO(sc->ctx_paddr[i] & 0xfffffff0) |
3310                             BCE_CTX_HOST_PAGE_TBL_DATA0_VALID);
3311                         REG_WR(sc, BCE_CTX_HOST_PAGE_TBL_DATA1,
3312                             BCE_ADDR_HI(sc->ctx_paddr[i]));
3313                         REG_WR(sc, BCE_CTX_HOST_PAGE_TBL_CTRL,
3314                             i | BCE_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ);
3315
3316                         /*
3317                          * Verify that the context memory write was successful.
3318                          */
3319                         for (j = 0; j < retry_cnt; j++) {
3320                                 val = REG_RD(sc, BCE_CTX_HOST_PAGE_TBL_CTRL);
3321                                 if ((val &
3322                                     BCE_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) == 0)
3323                                         break;
3324                                 DELAY(5);
3325                         }
3326                         if (j == retry_cnt) {
3327                                 device_printf(sc->bce_dev,
3328                                     "Failed to initialize context page!\n");
3329                                 return ETIMEDOUT;
3330                         }
3331                 }
3332         } else {
3333                 uint32_t vcid_addr, offset;
3334
3335                 /*
3336                  * For the 5706/5708, context memory is local to
3337                  * the controller, so initialize the controller
3338                  * context memory.
3339                  */
3340
3341                 vcid_addr = GET_CID_ADDR(96);
3342                 while (vcid_addr) {
3343                         vcid_addr -= PHY_CTX_SIZE;
3344
3345                         REG_WR(sc, BCE_CTX_VIRT_ADDR, 0);
3346                         REG_WR(sc, BCE_CTX_PAGE_TBL, vcid_addr);
3347
3348                         for (offset = 0; offset < PHY_CTX_SIZE; offset += 4)
3349                                 CTX_WR(sc, 0x00, offset, 0);
3350
3351                         REG_WR(sc, BCE_CTX_VIRT_ADDR, vcid_addr);
3352                         REG_WR(sc, BCE_CTX_PAGE_TBL, vcid_addr);
3353                 }
3354         }
3355         return 0;
3356 }
3357
3358
3359 /****************************************************************************/
3360 /* Fetch the permanent MAC address of the controller.                       */
3361 /*                                                                          */
3362 /* Returns:                                                                 */
3363 /*   Nothing.                                                               */
3364 /****************************************************************************/
3365 static void
3366 bce_get_mac_addr(struct bce_softc *sc)
3367 {
3368         uint32_t mac_lo = 0, mac_hi = 0;
3369
3370         /*
3371          * The NetXtreme II bootcode populates various NIC
3372          * power-on and runtime configuration items in a
3373          * shared memory area.  The factory configured MAC
3374          * address is available from both NVRAM and the
3375          * shared memory area so we'll read the value from
3376          * shared memory for speed.
3377          */
3378
3379         mac_hi = bce_shmem_rd(sc,  BCE_PORT_HW_CFG_MAC_UPPER);
3380         mac_lo = bce_shmem_rd(sc, BCE_PORT_HW_CFG_MAC_LOWER);
3381
3382         if (mac_lo == 0 && mac_hi == 0) {
3383                 if_printf(&sc->arpcom.ac_if, "Invalid Ethernet address!\n");
3384         } else {
3385                 sc->eaddr[0] = (u_char)(mac_hi >> 8);
3386                 sc->eaddr[1] = (u_char)(mac_hi >> 0);
3387                 sc->eaddr[2] = (u_char)(mac_lo >> 24);
3388                 sc->eaddr[3] = (u_char)(mac_lo >> 16);
3389                 sc->eaddr[4] = (u_char)(mac_lo >> 8);
3390                 sc->eaddr[5] = (u_char)(mac_lo >> 0);
3391         }
3392 }
3393
3394
3395 /****************************************************************************/
3396 /* Program the MAC address.                                                 */
3397 /*                                                                          */
3398 /* Returns:                                                                 */
3399 /*   Nothing.                                                               */
3400 /****************************************************************************/
3401 static void
3402 bce_set_mac_addr(struct bce_softc *sc)
3403 {
3404         const uint8_t *mac_addr = sc->eaddr;
3405         uint32_t val;
3406
3407         val = (mac_addr[0] << 8) | mac_addr[1];
3408         REG_WR(sc, BCE_EMAC_MAC_MATCH0, val);
3409
3410         val = (mac_addr[2] << 24) |
3411               (mac_addr[3] << 16) |
3412               (mac_addr[4] << 8) |
3413               mac_addr[5];
3414         REG_WR(sc, BCE_EMAC_MAC_MATCH1, val);
3415 }
3416
3417
3418 /****************************************************************************/
3419 /* Stop the controller.                                                     */
3420 /*                                                                          */
3421 /* Returns:                                                                 */
3422 /*   Nothing.                                                               */
3423 /****************************************************************************/
3424 static void
3425 bce_stop(struct bce_softc *sc)
3426 {
3427         struct ifnet *ifp = &sc->arpcom.ac_if;
3428         int i;
3429
3430         ASSERT_IFNET_SERIALIZED_ALL(ifp);
3431
3432         callout_stop(&sc->bce_tick_callout);
3433
3434         /* Disable the transmit/receive blocks. */
3435         REG_WR(sc, BCE_MISC_ENABLE_CLR_BITS, BCE_MISC_ENABLE_CLR_DEFAULT);
3436         REG_RD(sc, BCE_MISC_ENABLE_CLR_BITS);
3437         DELAY(20);
3438
3439         bce_disable_intr(sc);
3440
3441         ifp->if_flags &= ~IFF_RUNNING;
3442         for (i = 0; i < sc->ring_cnt; ++i) {
3443                 ifsq_clr_oactive(sc->tx_rings[i].ifsq);
3444                 ifsq_watchdog_stop(&sc->tx_rings[i].tx_watchdog);
3445         }
3446
3447         /* Free the RX lists. */
3448         for (i = 0; i < sc->ring_cnt; ++i)
3449                 bce_free_rx_chain(&sc->rx_rings[i]);
3450
3451         /* Free TX buffers. */
3452         for (i = 0; i < sc->ring_cnt; ++i)
3453                 bce_free_tx_chain(&sc->tx_rings[i]);
3454
3455         sc->bce_link = 0;
3456         sc->bce_coalchg_mask = 0;
3457 }
3458
3459
3460 static int
3461 bce_reset(struct bce_softc *sc, uint32_t reset_code)
3462 {
3463         uint32_t val;
3464         int i, rc = 0;
3465
3466         /* Wait for pending PCI transactions to complete. */
3467         REG_WR(sc, BCE_MISC_ENABLE_CLR_BITS,
3468                BCE_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE |
3469                BCE_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE |
3470                BCE_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE |
3471                BCE_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE);
3472         val = REG_RD(sc, BCE_MISC_ENABLE_CLR_BITS);
3473         DELAY(5);
3474
3475         /* Disable DMA */
3476         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3477             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3478                 val = REG_RD(sc, BCE_MISC_NEW_CORE_CTL);
3479                 val &= ~BCE_MISC_NEW_CORE_CTL_DMA_ENABLE;
3480                 REG_WR(sc, BCE_MISC_NEW_CORE_CTL, val);
3481         }
3482
3483         /* Assume bootcode is running. */
3484         sc->bce_fw_timed_out = 0;
3485         sc->bce_drv_cardiac_arrest = 0;
3486
3487         /* Give the firmware a chance to prepare for the reset. */
3488         rc = bce_fw_sync(sc, BCE_DRV_MSG_DATA_WAIT0 | reset_code);
3489         if (rc) {
3490                 if_printf(&sc->arpcom.ac_if,
3491                           "Firmware is not ready for reset\n");
3492                 return rc;
3493         }
3494
3495         /* Set a firmware reminder that this is a soft reset. */
3496         bce_shmem_wr(sc, BCE_DRV_RESET_SIGNATURE,
3497             BCE_DRV_RESET_SIGNATURE_MAGIC);
3498
3499         /* Dummy read to force the chip to complete all current transactions. */
3500         val = REG_RD(sc, BCE_MISC_ID);
3501
3502         /* Chip reset. */
3503         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3504             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3505                 REG_WR(sc, BCE_MISC_COMMAND, BCE_MISC_COMMAND_SW_RESET);
3506                 REG_RD(sc, BCE_MISC_COMMAND);
3507                 DELAY(5);
3508
3509                 val = BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
3510                     BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
3511
3512                 pci_write_config(sc->bce_dev, BCE_PCICFG_MISC_CONFIG, val, 4);
3513         } else {
3514                 val = BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ |
3515                     BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
3516                     BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
3517                 REG_WR(sc, BCE_PCICFG_MISC_CONFIG, val);
3518
3519                 /* Allow up to 30us for reset to complete. */
3520                 for (i = 0; i < 10; i++) {
3521                         val = REG_RD(sc, BCE_PCICFG_MISC_CONFIG);
3522                         if ((val & (BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ |
3523                             BCE_PCICFG_MISC_CONFIG_CORE_RST_BSY)) == 0)
3524                                 break;
3525                         DELAY(10);
3526                 }
3527
3528                 /* Check that reset completed successfully. */
3529                 if (val & (BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ |
3530                     BCE_PCICFG_MISC_CONFIG_CORE_RST_BSY)) {
3531                         if_printf(&sc->arpcom.ac_if, "Reset failed!\n");
3532                         return EBUSY;
3533                 }
3534         }
3535
3536         /* Make sure byte swapping is properly configured. */
3537         val = REG_RD(sc, BCE_PCI_SWAP_DIAG0);
3538         if (val != 0x01020304) {
3539                 if_printf(&sc->arpcom.ac_if, "Byte swap is incorrect!\n");
3540                 return ENODEV;
3541         }
3542
3543         /* Just completed a reset, assume that firmware is running again. */
3544         sc->bce_fw_timed_out = 0;
3545         sc->bce_drv_cardiac_arrest = 0;
3546
3547         /* Wait for the firmware to finish its initialization. */
3548         rc = bce_fw_sync(sc, BCE_DRV_MSG_DATA_WAIT1 | reset_code);
3549         if (rc) {
3550                 if_printf(&sc->arpcom.ac_if,
3551                           "Firmware did not complete initialization!\n");
3552         }
3553         return rc;
3554 }
3555
3556
3557 static int
3558 bce_chipinit(struct bce_softc *sc)
3559 {
3560         uint32_t val;
3561         int rc = 0;
3562
3563         /* Make sure the interrupt is not active. */
3564         REG_WR(sc, BCE_PCICFG_INT_ACK_CMD, BCE_PCICFG_INT_ACK_CMD_MASK_INT);
3565         REG_RD(sc, BCE_PCICFG_INT_ACK_CMD);
3566
3567         /*
3568          * Initialize DMA byte/word swapping, configure the number of DMA
3569          * channels and PCI clock compensation delay.
3570          */
3571         val = BCE_DMA_CONFIG_DATA_BYTE_SWAP |
3572               BCE_DMA_CONFIG_DATA_WORD_SWAP |
3573 #if BYTE_ORDER == BIG_ENDIAN
3574               BCE_DMA_CONFIG_CNTL_BYTE_SWAP |
3575 #endif
3576               BCE_DMA_CONFIG_CNTL_WORD_SWAP |
3577               DMA_READ_CHANS << 12 |
3578               DMA_WRITE_CHANS << 16;
3579
3580         val |= (0x2 << 20) | BCE_DMA_CONFIG_CNTL_PCI_COMP_DLY;
3581
3582         if ((sc->bce_flags & BCE_PCIX_FLAG) && sc->bus_speed_mhz == 133)
3583                 val |= BCE_DMA_CONFIG_PCI_FAST_CLK_CMP;
3584
3585         /*
3586          * This setting resolves a problem observed on certain Intel PCI
3587          * chipsets that cannot handle multiple outstanding DMA operations.
3588          * See errata E9_5706A1_65.
3589          */
3590         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5706 &&
3591             BCE_CHIP_ID(sc) != BCE_CHIP_ID_5706_A0 &&
3592             !(sc->bce_flags & BCE_PCIX_FLAG))
3593                 val |= BCE_DMA_CONFIG_CNTL_PING_PONG_DMA;
3594
3595         REG_WR(sc, BCE_DMA_CONFIG, val);
3596
3597         /* Enable the RX_V2P and Context state machines before access. */
3598         REG_WR(sc, BCE_MISC_ENABLE_SET_BITS,
3599                BCE_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE |
3600                BCE_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE |
3601                BCE_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE);
3602
3603         /* Initialize context mapping and zero out the quick contexts. */
3604         rc = bce_init_ctx(sc);
3605         if (rc != 0)
3606                 return rc;
3607
3608         /* Initialize the on-boards CPUs */
3609         bce_init_cpus(sc);
3610
3611         /* Enable management frames (NC-SI) to flow to the MCP. */
3612         if (sc->bce_flags & BCE_MFW_ENABLE_FLAG) {
3613                 val = REG_RD(sc, BCE_RPM_MGMT_PKT_CTRL) |
3614                     BCE_RPM_MGMT_PKT_CTRL_MGMT_EN;
3615                 REG_WR(sc, BCE_RPM_MGMT_PKT_CTRL, val);
3616         }
3617
3618         /* Prepare NVRAM for access. */
3619         rc = bce_init_nvram(sc);
3620         if (rc != 0)
3621                 return rc;
3622
3623         /* Set the kernel bypass block size */
3624         val = REG_RD(sc, BCE_MQ_CONFIG);
3625         val &= ~BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE;
3626         val |= BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE_256;
3627
3628         /* Enable bins used on the 5709/5716. */
3629         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3630             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3631                 val |= BCE_MQ_CONFIG_BIN_MQ_MODE;
3632                 if (BCE_CHIP_ID(sc) == BCE_CHIP_ID_5709_A1)
3633                         val |= BCE_MQ_CONFIG_HALT_DIS;
3634         }
3635
3636         REG_WR(sc, BCE_MQ_CONFIG, val);
3637
3638         val = 0x10000 + (MAX_CID_CNT * MB_KERNEL_CTX_SIZE);
3639         REG_WR(sc, BCE_MQ_KNL_BYP_WIND_START, val);
3640         REG_WR(sc, BCE_MQ_KNL_WIND_END, val);
3641
3642         /* Set the page size and clear the RV2P processor stall bits. */
3643         val = (BCM_PAGE_BITS - 8) << 24;
3644         REG_WR(sc, BCE_RV2P_CONFIG, val);
3645
3646         /* Configure page size. */
3647         val = REG_RD(sc, BCE_TBDR_CONFIG);
3648         val &= ~BCE_TBDR_CONFIG_PAGE_SIZE;
3649         val |= (BCM_PAGE_BITS - 8) << 24 | 0x40;
3650         REG_WR(sc, BCE_TBDR_CONFIG, val);
3651
3652         /* Set the perfect match control register to default. */
3653         REG_WR_IND(sc, BCE_RXP_PM_CTRL, 0);
3654
3655         return 0;
3656 }
3657
3658
3659 /****************************************************************************/
3660 /* Initialize the controller in preparation to send/receive traffic.        */
3661 /*                                                                          */
3662 /* Returns:                                                                 */
3663 /*   0 for success, positive value for failure.                             */
3664 /****************************************************************************/
3665 static int
3666 bce_blockinit(struct bce_softc *sc)
3667 {
3668         uint32_t reg, val;
3669
3670         /* Load the hardware default MAC address. */
3671         bce_set_mac_addr(sc);
3672
3673         /* Set the Ethernet backoff seed value */
3674         val = sc->eaddr[0] + (sc->eaddr[1] << 8) + (sc->eaddr[2] << 16) +
3675               sc->eaddr[3] + (sc->eaddr[4] << 8) + (sc->eaddr[5] << 16);
3676         REG_WR(sc, BCE_EMAC_BACKOFF_SEED, val);
3677
3678         sc->last_status_idx = 0;
3679         sc->rx_mode = BCE_EMAC_RX_MODE_SORT_MODE;
3680
3681         /* Set up link change interrupt generation. */
3682         REG_WR(sc, BCE_EMAC_ATTENTION_ENA, BCE_EMAC_ATTENTION_ENA_LINK);
3683
3684         /* Program the physical address of the status block. */
3685         REG_WR(sc, BCE_HC_STATUS_ADDR_L, BCE_ADDR_LO(sc->status_block_paddr));
3686         REG_WR(sc, BCE_HC_STATUS_ADDR_H, BCE_ADDR_HI(sc->status_block_paddr));
3687
3688         /* Program the physical address of the statistics block. */
3689         REG_WR(sc, BCE_HC_STATISTICS_ADDR_L,
3690                BCE_ADDR_LO(sc->stats_block_paddr));
3691         REG_WR(sc, BCE_HC_STATISTICS_ADDR_H,
3692                BCE_ADDR_HI(sc->stats_block_paddr));
3693
3694         /* Program various host coalescing parameters. */
3695         REG_WR(sc, BCE_HC_TX_QUICK_CONS_TRIP,
3696                (sc->bce_tx_quick_cons_trip_int << 16) |
3697                sc->bce_tx_quick_cons_trip);
3698         REG_WR(sc, BCE_HC_RX_QUICK_CONS_TRIP,
3699                (sc->bce_rx_quick_cons_trip_int << 16) |
3700                sc->bce_rx_quick_cons_trip);
3701         REG_WR(sc, BCE_HC_COMP_PROD_TRIP,
3702                (sc->bce_comp_prod_trip_int << 16) | sc->bce_comp_prod_trip);
3703         REG_WR(sc, BCE_HC_TX_TICKS,
3704                (sc->bce_tx_ticks_int << 16) | sc->bce_tx_ticks);
3705         REG_WR(sc, BCE_HC_RX_TICKS,
3706                (sc->bce_rx_ticks_int << 16) | sc->bce_rx_ticks);
3707         REG_WR(sc, BCE_HC_COM_TICKS,
3708                (sc->bce_com_ticks_int << 16) | sc->bce_com_ticks);
3709         REG_WR(sc, BCE_HC_CMD_TICKS,
3710                (sc->bce_cmd_ticks_int << 16) | sc->bce_cmd_ticks);
3711         REG_WR(sc, BCE_HC_STATS_TICKS, (sc->bce_stats_ticks & 0xffff00));
3712         REG_WR(sc, BCE_HC_STAT_COLLECT_TICKS, 0xbb8);   /* 3ms */
3713
3714         val = BCE_HC_CONFIG_TX_TMR_MODE | BCE_HC_CONFIG_COLLECT_STATS;
3715         if