2 * Copyright (c) 1995, David Greenman
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice unmodified, this list of conditions, and the following
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * $FreeBSD: src/sys/dev/ed/if_ed.c,v 1.173.2.13 2001/11/03 00:36:07 luigi Exp $
28 * $DragonFly: src/sys/dev/netif/ed/if_ed.c,v 1.3 2003/07/26 14:25:20 rob Exp $
32 * Device driver for National Semiconductor DS8390/WD83C690 based ethernet
33 * adapters. By David Greenman, 29-April-1993
35 * Currently supports the Western Digital/SMC 8003 and 8013 series,
36 * the SMC Elite Ultra (8216), the 3Com 3c503, the NE1000 and NE2000,
37 * and a variety of similar clones.
41 #include <sys/param.h>
42 #include <sys/systm.h>
43 #include <sys/sockio.h>
45 #include <sys/kernel.h>
46 #include <sys/socket.h>
47 #include <sys/syslog.h>
49 #include <sys/module.h>
52 #include <machine/bus.h>
54 #include <machine/resource.h>
56 #include <net/ethernet.h>
58 #include <net/if_arp.h>
59 #include <net/if_dl.h>
60 #include <net/if_mib.h>
61 #include <net/if_media.h>
63 #include <dev/mii/mii.h>
64 #include <dev/mii/miivar.h>
68 #include <net/bridge.h>
70 #include <machine/clock.h>
71 #include <machine/md_var.h>
73 #include <dev/ed/if_edreg.h>
74 #include <dev/ed/if_edvar.h>
76 static void ed_init __P((void *));
77 static int ed_ioctl __P((struct ifnet *, u_long, caddr_t));
78 static void ed_start __P((struct ifnet *));
79 static void ed_reset __P((struct ifnet *));
80 static void ed_watchdog __P((struct ifnet *));
81 static void ed_tick __P((void *));
83 static void ds_getmcaf __P((struct ed_softc *, u_int32_t *));
85 static void ed_get_packet __P((struct ed_softc *, char *, /* u_short */ int));
87 static __inline void ed_rint __P((struct ed_softc *));
88 static __inline void ed_xmit __P((struct ed_softc *));
89 static __inline char * ed_ring_copy __P((struct ed_softc *, char *, char *,
91 static void ed_hpp_set_physical_link __P((struct ed_softc *));
92 static void ed_hpp_readmem __P((struct ed_softc *, int, unsigned char *,
94 static void ed_hpp_writemem __P((struct ed_softc *, unsigned char *,
95 /* u_short */ int, /* u_short */ int));
96 static u_short ed_hpp_write_mbufs __P((struct ed_softc *, struct mbuf *,
99 static u_short ed_pio_write_mbufs __P((struct ed_softc *, struct mbuf *,
102 static void ed_setrcr __P((struct ed_softc *));
104 static u_int32_t ds_crc __P((u_char *ep));
107 * Interrupt conversion table for WD/SMC ASIC/83C584
109 static unsigned short ed_intr_val[] = {
121 * Interrupt conversion table for 83C790
123 static unsigned short ed_790_intr_val[] = {
135 * Interrupt conversion table for the HP PC LAN+
138 static unsigned short ed_hpp_intr_val[] = {
158 * Generic probe routine for testing for the existance of a DS8390.
159 * Must be called after the NIC has just been reset. This routine
160 * works by looking at certain register values that are guaranteed
161 * to be initialized a certain way after power-up or reset. Seems
162 * not to currently work on the 83C690.
166 * Register reset bits set bits
167 * Command Register (CR) TXP, STA RD2, STP
168 * Interrupt Status (ISR) RST
169 * Interrupt Mask (IMR) All bits
170 * Data Control (DCR) LAS
171 * Transmit Config. (TCR) LB1, LB0
173 * We only look at the CR and ISR registers, however, because looking at
174 * the others would require changing register pages (which would be
175 * intrusive if this isn't an 8390).
177 * Return 1 if 8390 was found, 0 if not.
181 ed_probe_generic8390(sc)
184 if ((ed_nic_inb(sc, ED_P0_CR) &
185 (ED_CR_RD2 | ED_CR_TXP | ED_CR_STA | ED_CR_STP)) !=
186 (ED_CR_RD2 | ED_CR_STP))
188 if ((ed_nic_inb(sc, ED_P0_ISR) & ED_ISR_RST) != ED_ISR_RST)
195 * Probe and vendor-specific initialization routine for SMC/WD80x3 boards
198 ed_probe_WD80x3_generic(dev, flags, intr_vals)
201 unsigned short *intr_vals[];
203 struct ed_softc *sc = device_get_softc(dev);
206 u_int memsize, maddr;
207 u_char iptr, isa16bit, sum, totalsum;
208 u_long conf_maddr, conf_msize, irq, junk;
210 sc->chip_type = ED_CHIP_TYPE_DP8390;
212 if (ED_FLAGS_GETTYPE(flags) == ED_FLAGS_TOSH_ETHER) {
213 totalsum = ED_WD_ROM_CHECKSUM_TOTAL_TOSH_ETHER;
214 ed_asic_outb(sc, ED_WD_MSR, ED_WD_MSR_POW);
218 totalsum = ED_WD_ROM_CHECKSUM_TOTAL;
221 * Attempt to do a checksum over the station address PROM. If it
222 * fails, it's probably not a SMC/WD board. There is a problem with
223 * this, though: some clone WD boards don't pass the checksum test.
224 * Danpex boards for one.
226 for (sum = 0, i = 0; i < 8; ++i)
227 sum += ed_asic_inb(sc, ED_WD_PROM + i);
229 if (sum != totalsum) {
232 * Checksum is invalid. This often happens with cheap WD8003E
233 * clones. In this case, the checksum byte (the eighth byte)
234 * seems to always be zero.
236 if (ed_asic_inb(sc, ED_WD_CARD_ID) != ED_TYPE_WD8003E ||
237 ed_asic_inb(sc, ED_WD_PROM + 7) != 0)
240 /* reset card to force it into a known state. */
241 if (ED_FLAGS_GETTYPE(flags) == ED_FLAGS_TOSH_ETHER)
242 ed_asic_outb(sc, ED_WD_MSR, ED_WD_MSR_RST | ED_WD_MSR_POW);
244 ed_asic_outb(sc, ED_WD_MSR, ED_WD_MSR_RST);
247 ed_asic_outb(sc, ED_WD_MSR, ed_asic_inb(sc, ED_WD_MSR) & ~ED_WD_MSR_RST);
248 /* wait in the case this card is reading its EEROM */
251 sc->vendor = ED_VENDOR_WD_SMC;
252 sc->type = ed_asic_inb(sc, ED_WD_CARD_ID);
255 * Set initial values for width/size.
260 case ED_TYPE_WD8003S:
261 sc->type_str = "WD8003S";
263 case ED_TYPE_WD8003E:
264 sc->type_str = "WD8003E";
266 case ED_TYPE_WD8003EB:
267 sc->type_str = "WD8003EB";
269 case ED_TYPE_WD8003W:
270 sc->type_str = "WD8003W";
272 case ED_TYPE_WD8013EBT:
273 sc->type_str = "WD8013EBT";
277 case ED_TYPE_WD8013W:
278 sc->type_str = "WD8013W";
282 case ED_TYPE_WD8013EP: /* also WD8003EP */
283 if (ed_asic_inb(sc, ED_WD_ICR) & ED_WD_ICR_16BIT) {
286 sc->type_str = "WD8013EP";
288 sc->type_str = "WD8003EP";
291 case ED_TYPE_WD8013WC:
292 sc->type_str = "WD8013WC";
296 case ED_TYPE_WD8013EBP:
297 sc->type_str = "WD8013EBP";
301 case ED_TYPE_WD8013EPC:
302 sc->type_str = "WD8013EPC";
306 case ED_TYPE_SMC8216C: /* 8216 has 16K shared mem -- 8416 has 8K */
307 case ED_TYPE_SMC8216T:
308 if (sc->type == ED_TYPE_SMC8216C) {
309 sc->type_str = "SMC8216/SMC8216C";
311 sc->type_str = "SMC8216T";
314 ed_asic_outb(sc, ED_WD790_HWR,
315 ed_asic_inb(sc, ED_WD790_HWR) | ED_WD790_HWR_SWH);
316 switch (ed_asic_inb(sc, ED_WD790_RAR) & ED_WD790_RAR_SZ64) {
317 case ED_WD790_RAR_SZ64:
320 case ED_WD790_RAR_SZ32:
323 case ED_WD790_RAR_SZ16:
326 case ED_WD790_RAR_SZ8:
327 /* 8216 has 16K shared mem -- 8416 has 8K */
328 if (sc->type == ED_TYPE_SMC8216C) {
329 sc->type_str = "SMC8416C/SMC8416BT";
331 sc->type_str = "SMC8416T";
336 ed_asic_outb(sc, ED_WD790_HWR,
337 ed_asic_inb(sc, ED_WD790_HWR) & ~ED_WD790_HWR_SWH);
340 sc->chip_type = ED_CHIP_TYPE_WD790;
342 case ED_TYPE_TOSHIBA1:
343 sc->type_str = "Toshiba1";
347 case ED_TYPE_TOSHIBA4:
348 sc->type_str = "Toshiba4";
358 * Make some adjustments to initial values depending on what is found
361 if (isa16bit && (sc->type != ED_TYPE_WD8013EBT)
362 && (sc->type != ED_TYPE_TOSHIBA1) && (sc->type != ED_TYPE_TOSHIBA4)
363 && ((ed_asic_inb(sc, ED_WD_ICR) & ED_WD_ICR_16BIT) == 0)) {
368 error = bus_get_resource(dev, SYS_RES_MEMORY, 0,
369 &conf_maddr, &conf_msize);
374 printf("type = %x type_str=%s isa16bit=%d memsize=%d id_msize=%d\n",
375 sc->type, sc->type_str, isa16bit, memsize, conf_msize);
376 for (i = 0; i < 8; i++)
377 printf("%x -> %x\n", i, ed_asic_inb(sc, i));
381 * Allow the user to override the autoconfiguration
384 memsize = conf_msize;
387 if (maddr < 0xa0000 || maddr + memsize > 0x1000000) {
388 device_printf(dev, "Invalid ISA memory address range configured: 0x%x - 0x%x\n",
389 maddr, maddr + memsize);
394 * (note that if the user specifies both of the following flags that
395 * '8bit' mode intentionally has precedence)
397 if (flags & ED_FLAGS_FORCE_16BIT_MODE)
399 if (flags & ED_FLAGS_FORCE_8BIT_MODE)
403 * If possible, get the assigned interrupt number from the card and
406 if ((sc->type & ED_WD_SOFTCONFIG) &&
407 (sc->chip_type != ED_CHIP_TYPE_WD790)) {
410 * Assemble together the encoded interrupt number.
412 iptr = (ed_asic_inb(sc, ED_WD_ICR) & ED_WD_ICR_IR2) |
413 ((ed_asic_inb(sc, ED_WD_IRR) &
414 (ED_WD_IRR_IR0 | ED_WD_IRR_IR1)) >> 5);
417 * If no interrupt specified (or "?"), use what the board tells us.
419 error = bus_get_resource(dev, SYS_RES_IRQ, 0,
421 if (error && intr_vals[0] != NULL) {
422 error = bus_set_resource(dev, SYS_RES_IRQ, 0,
423 intr_vals[0][iptr], 1);
429 * Enable the interrupt.
431 ed_asic_outb(sc, ED_WD_IRR,
432 ed_asic_inb(sc, ED_WD_IRR) | ED_WD_IRR_IEN);
434 if (sc->chip_type == ED_CHIP_TYPE_WD790) {
435 ed_asic_outb(sc, ED_WD790_HWR,
436 ed_asic_inb(sc, ED_WD790_HWR) | ED_WD790_HWR_SWH);
437 iptr = (((ed_asic_inb(sc, ED_WD790_GCR) & ED_WD790_GCR_IR2) >> 4) |
438 (ed_asic_inb(sc, ED_WD790_GCR) &
439 (ED_WD790_GCR_IR1 | ED_WD790_GCR_IR0)) >> 2);
440 ed_asic_outb(sc, ED_WD790_HWR,
441 ed_asic_inb(sc, ED_WD790_HWR) & ~ED_WD790_HWR_SWH);
444 * If no interrupt specified (or "?"), use what the board tells us.
446 error = bus_get_resource(dev, SYS_RES_IRQ, 0,
448 if (error && intr_vals[1] != NULL) {
449 error = bus_set_resource(dev, SYS_RES_IRQ, 0,
450 intr_vals[1][iptr], 1);
458 ed_asic_outb(sc, ED_WD790_ICR,
459 ed_asic_inb(sc, ED_WD790_ICR) | ED_WD790_ICR_EIL);
461 error = bus_get_resource(dev, SYS_RES_IRQ, 0,
464 device_printf(dev, "%s cards don't support auto-detected/assigned interrupts.\n",
468 sc->isa16bit = isa16bit;
471 error = ed_alloc_memory(dev, 0, memsize);
473 printf("*** ed_alloc_memory() failed! (%d)\n", error);
476 sc->mem_start = (caddr_t) rman_get_virtual(sc->mem_res);
479 * allocate one xmit buffer if < 16k, two buffers otherwise
481 if ((memsize < 16384) ||
482 (flags & ED_FLAGS_NO_MULTI_BUFFERING)) {
487 sc->tx_page_start = ED_WD_PAGE_OFFSET;
488 sc->rec_page_start = ED_WD_PAGE_OFFSET + ED_TXBUF_SIZE * sc->txb_cnt;
489 sc->rec_page_stop = ED_WD_PAGE_OFFSET + memsize / ED_PAGE_SIZE;
490 sc->mem_ring = sc->mem_start + (ED_PAGE_SIZE * sc->rec_page_start);
491 sc->mem_size = memsize;
492 sc->mem_end = sc->mem_start + memsize;
495 * Get station address from on-board ROM
497 for (i = 0; i < ETHER_ADDR_LEN; ++i)
498 sc->arpcom.ac_enaddr[i] = ed_asic_inb(sc, ED_WD_PROM + i);
501 * Set upper address bits and 8/16 bit access to shared memory.
504 if (sc->chip_type == ED_CHIP_TYPE_WD790) {
505 sc->wd_laar_proto = ed_asic_inb(sc, ED_WD_LAAR);
507 sc->wd_laar_proto = ED_WD_LAAR_L16EN |
508 ((kvtop(sc->mem_start) >> 19) & ED_WD_LAAR_ADDRHI);
511 * Enable 16bit access
513 ed_asic_outb(sc, ED_WD_LAAR, sc->wd_laar_proto |
516 if (((sc->type & ED_WD_SOFTCONFIG) ||
517 (sc->type == ED_TYPE_TOSHIBA1) ||
518 (sc->type == ED_TYPE_TOSHIBA4) ||
519 (sc->type == ED_TYPE_WD8013EBT)) &&
520 (sc->chip_type != ED_CHIP_TYPE_WD790)) {
521 sc->wd_laar_proto = (kvtop(sc->mem_start) >> 19) &
523 ed_asic_outb(sc, ED_WD_LAAR, sc->wd_laar_proto);
528 * Set address and enable interface shared memory.
530 if (sc->chip_type != ED_CHIP_TYPE_WD790) {
531 if (ED_FLAGS_GETTYPE(flags) == ED_FLAGS_TOSH_ETHER) {
532 ed_asic_outb(sc, ED_WD_MSR + 1,
533 ((kvtop(sc->mem_start) >> 8) & 0xe0) | 4);
534 ed_asic_outb(sc, ED_WD_MSR + 2,
535 ((kvtop(sc->mem_start) >> 16) & 0x0f));
536 ed_asic_outb(sc, ED_WD_MSR,
537 ED_WD_MSR_MENB | ED_WD_MSR_POW);
539 ed_asic_outb(sc, ED_WD_MSR,
540 ((kvtop(sc->mem_start) >> 13) &
541 ED_WD_MSR_ADDR) | ED_WD_MSR_MENB);
543 sc->cr_proto = ED_CR_RD2;
545 ed_asic_outb(sc, ED_WD_MSR, ED_WD_MSR_MENB);
546 ed_asic_outb(sc, ED_WD790_HWR, (ed_asic_inb(sc, ED_WD790_HWR) | ED_WD790_HWR_SWH));
547 ed_asic_outb(sc, ED_WD790_RAR, ((kvtop(sc->mem_start) >> 13) & 0x0f) |
548 ((kvtop(sc->mem_start) >> 11) & 0x40) |
549 (ed_asic_inb(sc, ED_WD790_RAR) & 0xb0));
550 ed_asic_outb(sc, ED_WD790_HWR, (ed_asic_inb(sc, ED_WD790_HWR) & ~ED_WD790_HWR_SWH));
555 printf("starting memory performance test at 0x%x, size %d...\n",
556 sc->mem_start, memsize*16384);
557 for (i = 0; i < 16384; i++)
558 bzero(sc->mem_start, memsize);
559 printf("***DONE***\n");
563 * Now zero memory and verify that it is clear
565 bzero(sc->mem_start, memsize);
567 for (i = 0; i < memsize; ++i) {
568 if (sc->mem_start[i]) {
569 device_printf(dev, "failed to clear shared memory at %lx - check configuration\n",
570 kvtop(sc->mem_start + i));
573 * Disable 16 bit access to shared memory
576 if (sc->chip_type == ED_CHIP_TYPE_WD790) {
577 ed_asic_outb(sc, ED_WD_MSR, 0x00);
579 ed_asic_outb(sc, ED_WD_LAAR, sc->wd_laar_proto &
587 * Disable 16bit access to shared memory - we leave it
588 * disabled so that 1) machines reboot properly when the board
589 * is set 16 bit mode and there are conflicting 8bit
590 * devices/ROMS in the same 128k address space as this boards
591 * shared memory. and 2) so that other 8 bit devices with
592 * shared memory can be used in this 128k region, too.
595 if (sc->chip_type == ED_CHIP_TYPE_WD790) {
596 ed_asic_outb(sc, ED_WD_MSR, 0x00);
598 ed_asic_outb(sc, ED_WD_LAAR, sc->wd_laar_proto &
605 ed_probe_WD80x3(dev, port_rid, flags)
610 struct ed_softc *sc = device_get_softc(dev);
612 static unsigned short *intr_vals[] = {ed_intr_val, ed_790_intr_val};
614 error = ed_alloc_port(dev, port_rid, ED_WD_IO_PORTS);
618 sc->asic_offset = ED_WD_ASIC_OFFSET;
619 sc->nic_offset = ED_WD_NIC_OFFSET;
621 return ed_probe_WD80x3_generic(dev, flags, intr_vals);
625 * Probe and vendor-specific initialization routine for 3Com 3c503 boards
628 ed_probe_3Com(dev, port_rid, flags)
633 struct ed_softc *sc = device_get_softc(dev);
638 u_long conf_maddr, conf_msize, irq, junk;
640 error = ed_alloc_port(dev, 0, ED_3COM_IO_PORTS);
644 sc->asic_offset = ED_3COM_ASIC_OFFSET;
645 sc->nic_offset = ED_3COM_NIC_OFFSET;
648 * Verify that the kernel configured I/O address matches the board
651 switch (ed_asic_inb(sc, ED_3COM_BCFR)) {
652 case ED_3COM_BCFR_300:
653 if (rman_get_start(sc->port_res) != 0x300)
656 case ED_3COM_BCFR_310:
657 if (rman_get_start(sc->port_res) != 0x310)
660 case ED_3COM_BCFR_330:
661 if (rman_get_start(sc->port_res) != 0x330)
664 case ED_3COM_BCFR_350:
665 if (rman_get_start(sc->port_res) != 0x350)
668 case ED_3COM_BCFR_250:
669 if (rman_get_start(sc->port_res) != 0x250)
672 case ED_3COM_BCFR_280:
673 if (rman_get_start(sc->port_res) != 0x280)
676 case ED_3COM_BCFR_2A0:
677 if (rman_get_start(sc->port_res) != 0x2a0)
680 case ED_3COM_BCFR_2E0:
681 if (rman_get_start(sc->port_res) != 0x2e0)
688 error = bus_get_resource(dev, SYS_RES_MEMORY, 0,
689 &conf_maddr, &conf_msize);
694 * Verify that the kernel shared memory address matches the board
695 * configured address.
697 switch (ed_asic_inb(sc, ED_3COM_PCFR)) {
698 case ED_3COM_PCFR_DC000:
699 if (conf_maddr != 0xdc000)
702 case ED_3COM_PCFR_D8000:
703 if (conf_maddr != 0xd8000)
706 case ED_3COM_PCFR_CC000:
707 if (conf_maddr != 0xcc000)
710 case ED_3COM_PCFR_C8000:
711 if (conf_maddr != 0xc8000)
720 * Reset NIC and ASIC. Enable on-board transceiver throughout reset
721 * sequence because it'll lock up if the cable isn't connected if we
724 ed_asic_outb(sc, ED_3COM_CR, ED_3COM_CR_RST | ED_3COM_CR_XSEL);
727 * Wait for a while, then un-reset it
732 * The 3Com ASIC defaults to rather strange settings for the CR after
733 * a reset - it's important to set it again after the following outb
734 * (this is done when we map the PROM below).
736 ed_asic_outb(sc, ED_3COM_CR, ED_3COM_CR_XSEL);
739 * Wait a bit for the NIC to recover from the reset
743 sc->vendor = ED_VENDOR_3COM;
744 sc->type_str = "3c503";
746 sc->cr_proto = ED_CR_RD2;
749 * Hmmm...a 16bit 3Com board has 16k of memory, but only an 8k window
755 * Get station address from on-board ROM
759 * First, map ethernet address PROM over the top of where the NIC
760 * registers normally appear.
762 ed_asic_outb(sc, ED_3COM_CR, ED_3COM_CR_EALO | ED_3COM_CR_XSEL);
764 for (i = 0; i < ETHER_ADDR_LEN; ++i)
765 sc->arpcom.ac_enaddr[i] = ed_nic_inb(sc, i);
768 * Unmap PROM - select NIC registers. The proper setting of the
769 * tranceiver is set in ed_init so that the attach code is given a
770 * chance to set the default based on a compile-time config option
772 ed_asic_outb(sc, ED_3COM_CR, ED_3COM_CR_XSEL);
775 * Determine if this is an 8bit or 16bit board
779 * select page 0 registers
781 ed_nic_outb(sc, ED_P0_CR, ED_CR_RD2 | ED_CR_STP);
784 * Attempt to clear WTS bit. If it doesn't clear, then this is a 16bit
787 ed_nic_outb(sc, ED_P0_DCR, 0);
790 * select page 2 registers
792 ed_nic_outb(sc, ED_P0_CR, ED_CR_PAGE_2 | ED_CR_RD2 | ED_CR_STP);
795 * The 3c503 forces the WTS bit to a one if this is a 16bit board
797 if (ed_nic_inb(sc, ED_P2_DCR) & ED_DCR_WTS)
803 * select page 0 registers
805 ed_nic_outb(sc, ED_P2_CR, ED_CR_RD2 | ED_CR_STP);
807 error = ed_alloc_memory(dev, 0, memsize);
811 sc->mem_start = (caddr_t) rman_get_virtual(sc->mem_res);
812 sc->mem_size = memsize;
813 sc->mem_end = sc->mem_start + memsize;
816 * We have an entire 8k window to put the transmit buffers on the
817 * 16bit boards. But since the 16bit 3c503's shared memory is only
818 * fast enough to overlap the loading of one full-size packet, trying
819 * to load more than 2 buffers can actually leave the transmitter idle
820 * during the load. So 2 seems the best value. (Although a mix of
821 * variable-sized packets might change this assumption. Nonetheless,
822 * we optimize for linear transfers of same-size packets.)
825 if (flags & ED_FLAGS_NO_MULTI_BUFFERING)
830 sc->tx_page_start = ED_3COM_TX_PAGE_OFFSET_16BIT;
831 sc->rec_page_start = ED_3COM_RX_PAGE_OFFSET_16BIT;
832 sc->rec_page_stop = memsize / ED_PAGE_SIZE +
833 ED_3COM_RX_PAGE_OFFSET_16BIT;
834 sc->mem_ring = sc->mem_start;
837 sc->tx_page_start = ED_3COM_TX_PAGE_OFFSET_8BIT;
838 sc->rec_page_start = ED_TXBUF_SIZE + ED_3COM_TX_PAGE_OFFSET_8BIT;
839 sc->rec_page_stop = memsize / ED_PAGE_SIZE +
840 ED_3COM_TX_PAGE_OFFSET_8BIT;
841 sc->mem_ring = sc->mem_start + (ED_PAGE_SIZE * ED_TXBUF_SIZE);
844 sc->isa16bit = isa16bit;
847 * Initialize GA page start/stop registers. Probably only needed if
848 * doing DMA, but what the hell.
850 ed_asic_outb(sc, ED_3COM_PSTR, sc->rec_page_start);
851 ed_asic_outb(sc, ED_3COM_PSPR, sc->rec_page_stop);
854 * Set IRQ. 3c503 only allows a choice of irq 2-5.
856 error = bus_get_resource(dev, SYS_RES_IRQ, 0, &irq, &junk);
863 ed_asic_outb(sc, ED_3COM_IDCFR, ED_3COM_IDCFR_IRQ2);
866 ed_asic_outb(sc, ED_3COM_IDCFR, ED_3COM_IDCFR_IRQ3);
869 ed_asic_outb(sc, ED_3COM_IDCFR, ED_3COM_IDCFR_IRQ4);
872 ed_asic_outb(sc, ED_3COM_IDCFR, ED_3COM_IDCFR_IRQ5);
875 device_printf(dev, "Invalid irq configuration (%ld) must be 3-5,9 for 3c503\n",
881 * Initialize GA configuration register. Set bank and enable shared
884 ed_asic_outb(sc, ED_3COM_GACFR, ED_3COM_GACFR_RSEL |
888 * Initialize "Vector Pointer" registers. These gawd-awful things are
889 * compared to 20 bits of the address on ISA, and if they match, the
890 * shared memory is disabled. We set them to 0xffff0...allegedly the
893 ed_asic_outb(sc, ED_3COM_VPTR2, 0xff);
894 ed_asic_outb(sc, ED_3COM_VPTR1, 0xff);
895 ed_asic_outb(sc, ED_3COM_VPTR0, 0x00);
898 * Zero memory and verify that it is clear
900 bzero(sc->mem_start, memsize);
902 for (i = 0; i < memsize; ++i)
903 if (sc->mem_start[i]) {
904 device_printf(dev, "failed to clear shared memory at %lx - check configuration\n",
905 kvtop(sc->mem_start + i));
912 * Probe and vendor-specific initialization routine for NE1000/2000 boards
915 ed_probe_Novell_generic(dev, flags)
919 struct ed_softc *sc = device_get_softc(dev);
921 u_char romdata[16], tmp;
922 static char test_pattern[32] = "THIS is A memory TEST pattern";
923 char test_buffer[32];
925 /* XXX - do Novell-specific probe here */
927 /* Reset the board */
928 if (ED_FLAGS_GETTYPE(flags) == ED_FLAGS_GWETHER) {
929 ed_asic_outb(sc, ED_NOVELL_RESET, 0);
932 tmp = ed_asic_inb(sc, ED_NOVELL_RESET);
935 * I don't know if this is necessary; probably cruft leftover from
936 * Clarkson packet driver code. Doesn't do a thing on the boards I've
937 * tested. -DG [note that a outb(0x84, 0) seems to work here, and is
938 * non-invasive...but some boards don't seem to reset and I don't have
939 * complete documentation on what the 'right' thing to do is...so we
940 * do the invasive thing for now. Yuck.]
942 ed_asic_outb(sc, ED_NOVELL_RESET, tmp);
946 * This is needed because some NE clones apparently don't reset the
947 * NIC properly (or the NIC chip doesn't reset fully on power-up) XXX
948 * - this makes the probe invasive! ...Done against my better
951 ed_nic_outb(sc, ED_P0_CR, ED_CR_RD2 | ED_CR_STP);
955 /* Make sure that we really have an 8390 based board */
956 if (!ed_probe_generic8390(sc))
959 sc->vendor = ED_VENDOR_NOVELL;
961 sc->cr_proto = ED_CR_RD2;
964 * Test the ability to read and write to the NIC memory. This has the
965 * side affect of determining if this is an NE1000 or an NE2000.
969 * This prevents packets from being stored in the NIC memory when the
970 * readmem routine turns on the start bit in the CR.
972 ed_nic_outb(sc, ED_P0_RCR, ED_RCR_MON);
974 /* Temporarily initialize DCR for byte operations */
975 ed_nic_outb(sc, ED_P0_DCR, ED_DCR_FT1 | ED_DCR_LS);
977 ed_nic_outb(sc, ED_P0_PSTART, 8192 / ED_PAGE_SIZE);
978 ed_nic_outb(sc, ED_P0_PSTOP, 16384 / ED_PAGE_SIZE);
983 * Write a test pattern in byte mode. If this fails, then there
984 * probably isn't any memory at 8k - which likely means that the board
987 ed_pio_writemem(sc, test_pattern, 8192, sizeof(test_pattern));
988 ed_pio_readmem(sc, 8192, test_buffer, sizeof(test_pattern));
990 if (bcmp(test_pattern, test_buffer, sizeof(test_pattern)) == 0) {
991 sc->type = ED_TYPE_NE1000;
992 sc->type_str = "NE1000";
995 /* neither an NE1000 nor a Linksys - try NE2000 */
996 ed_nic_outb(sc, ED_P0_DCR, ED_DCR_WTS | ED_DCR_FT1 | ED_DCR_LS);
997 ed_nic_outb(sc, ED_P0_PSTART, 16384 / ED_PAGE_SIZE);
998 ed_nic_outb(sc, ED_P0_PSTOP, 32768 / ED_PAGE_SIZE);
1003 * Write a test pattern in word mode. If this also fails, then
1004 * we don't know what this board is.
1006 ed_pio_writemem(sc, test_pattern, 16384, sizeof(test_pattern));
1007 ed_pio_readmem(sc, 16384, test_buffer, sizeof(test_pattern));
1008 if (bcmp(test_pattern, test_buffer, sizeof(test_pattern)) == 0) {
1009 sc->type = ED_TYPE_NE2000;
1010 sc->type_str = "NE2000";
1017 /* 8k of memory plus an additional 8k if 16bit */
1018 memsize = 8192 + sc->isa16bit * 8192;
1020 #if 0 /* probably not useful - NE boards only come two ways */
1021 /* allow kernel config file overrides */
1022 if (isa_dev->id_msize)
1023 memsize = isa_dev->id_msize;
1026 sc->mem_size = memsize;
1028 /* NIC memory doesn't start at zero on an NE board */
1029 /* The start address is tied to the bus width */
1030 sc->mem_start = (char *) 8192 + sc->isa16bit * 8192;
1031 sc->mem_end = sc->mem_start + memsize;
1032 sc->tx_page_start = memsize / ED_PAGE_SIZE;
1034 if (ED_FLAGS_GETTYPE(flags) == ED_FLAGS_GWETHER) {
1035 int x, i, mstart = 0, msize = 0;
1036 char pbuf0[ED_PAGE_SIZE], pbuf[ED_PAGE_SIZE], tbuf[ED_PAGE_SIZE];
1038 for (i = 0; i < ED_PAGE_SIZE; i++)
1041 /* Clear all the memory. */
1042 for (x = 1; x < 256; x++)
1043 ed_pio_writemem(sc, pbuf0, x * 256, ED_PAGE_SIZE);
1045 /* Search for the start of RAM. */
1046 for (x = 1; x < 256; x++) {
1047 ed_pio_readmem(sc, x * 256, tbuf, ED_PAGE_SIZE);
1048 if (bcmp(pbuf0, tbuf, ED_PAGE_SIZE) == 0) {
1049 for (i = 0; i < ED_PAGE_SIZE; i++)
1051 ed_pio_writemem(sc, pbuf, x * 256, ED_PAGE_SIZE);
1052 ed_pio_readmem(sc, x * 256, tbuf, ED_PAGE_SIZE);
1053 if (bcmp(pbuf, tbuf, ED_PAGE_SIZE) == 0) {
1054 mstart = x * ED_PAGE_SIZE;
1055 msize = ED_PAGE_SIZE;
1062 device_printf(dev, "Cannot find start of RAM.\n");
1065 /* Search for the start of RAM. */
1066 for (x = (mstart / ED_PAGE_SIZE) + 1; x < 256; x++) {
1067 ed_pio_readmem(sc, x * 256, tbuf, ED_PAGE_SIZE);
1068 if (bcmp(pbuf0, tbuf, ED_PAGE_SIZE) == 0) {
1069 for (i = 0; i < ED_PAGE_SIZE; i++)
1071 ed_pio_writemem(sc, pbuf, x * 256, ED_PAGE_SIZE);
1072 ed_pio_readmem(sc, x * 256, tbuf, ED_PAGE_SIZE);
1073 if (bcmp(pbuf, tbuf, ED_PAGE_SIZE) == 0)
1074 msize += ED_PAGE_SIZE;
1084 device_printf(dev, "Cannot find any RAM, start : %d, x = %d.\n", mstart, x);
1087 device_printf(dev, "RAM start at %d, size : %d.\n", mstart, msize);
1089 sc->mem_size = msize;
1090 sc->mem_start = (caddr_t) mstart;
1091 sc->mem_end = (caddr_t) (msize + mstart);
1092 sc->tx_page_start = mstart / ED_PAGE_SIZE;
1096 * Use one xmit buffer if < 16k, two buffers otherwise (if not told
1099 if ((memsize < 16384) || (flags & ED_FLAGS_NO_MULTI_BUFFERING))
1104 sc->rec_page_start = sc->tx_page_start + sc->txb_cnt * ED_TXBUF_SIZE;
1105 sc->rec_page_stop = sc->tx_page_start + memsize / ED_PAGE_SIZE;
1107 sc->mem_ring = sc->mem_start + sc->txb_cnt * ED_PAGE_SIZE * ED_TXBUF_SIZE;
1109 ed_pio_readmem(sc, 0, romdata, 16);
1110 for (n = 0; n < ETHER_ADDR_LEN; n++)
1111 sc->arpcom.ac_enaddr[n] = romdata[n * (sc->isa16bit + 1)];
1113 if ((ED_FLAGS_GETTYPE(flags) == ED_FLAGS_GWETHER) &&
1114 (sc->arpcom.ac_enaddr[2] == 0x86)) {
1115 sc->type_str = "Gateway AT";
1118 /* clear any pending interrupts that might have occurred above */
1119 ed_nic_outb(sc, ED_P0_ISR, 0xff);
1125 ed_probe_Novell(dev, port_rid, flags)
1130 struct ed_softc *sc = device_get_softc(dev);
1133 error = ed_alloc_port(dev, port_rid, ED_NOVELL_IO_PORTS);
1137 sc->asic_offset = ED_NOVELL_ASIC_OFFSET;
1138 sc->nic_offset = ED_NOVELL_NIC_OFFSET;
1140 return ed_probe_Novell_generic(dev, flags);
1143 #define ED_HPP_TEST_SIZE 16
1146 * Probe and vendor specific initialization for the HP PC Lan+ Cards.
1147 * (HP Part nos: 27247B and 27252A).
1149 * The card has an asic wrapper around a DS8390 core. The asic handles
1150 * host accesses and offers both standard register IO and memory mapped
1151 * IO. Memory mapped I/O allows better performance at the expense of greater
1152 * chance of an incompatibility with existing ISA cards.
1154 * The card has a few caveats: it isn't tolerant of byte wide accesses, only
1155 * short (16 bit) or word (32 bit) accesses are allowed. Some card revisions
1156 * don't allow 32 bit accesses; these are indicated by a bit in the software
1157 * ID register (see if_edreg.h).
1159 * Other caveats are: we should read the MAC address only when the card
1162 * For more information; please consult the CRYNWR packet driver.
1164 * The AUI port is turned on using the "link2" option on the ifconfig
1168 ed_probe_HP_pclanp(dev, port_rid, flags)
1173 struct ed_softc *sc = device_get_softc(dev);
1175 int n; /* temp var */
1176 int memsize; /* mem on board */
1177 u_char checksum; /* checksum of board address */
1178 u_char irq; /* board configured IRQ */
1179 char test_pattern[ED_HPP_TEST_SIZE]; /* read/write areas for */
1180 char test_buffer[ED_HPP_TEST_SIZE]; /* probing card */
1181 u_long conf_maddr, conf_msize, conf_irq, junk;
1183 error = ed_alloc_port(dev, 0, ED_HPP_IO_PORTS);
1187 /* Fill in basic information */
1188 sc->asic_offset = ED_HPP_ASIC_OFFSET;
1189 sc->nic_offset = ED_HPP_NIC_OFFSET;
1191 sc->chip_type = ED_CHIP_TYPE_DP8390;
1192 sc->isa16bit = 0; /* the 8390 core needs to be in byte mode */
1195 * Look for the HP PCLAN+ signature: "0x50,0x48,0x00,0x53"
1198 if ((ed_asic_inb(sc, ED_HPP_ID) != 0x50) ||
1199 (ed_asic_inb(sc, ED_HPP_ID + 1) != 0x48) ||
1200 ((ed_asic_inb(sc, ED_HPP_ID + 2) & 0xF0) != 0) ||
1201 (ed_asic_inb(sc, ED_HPP_ID + 3) != 0x53))
1205 * Read the MAC address and verify checksum on the address.
1208 ed_asic_outw(sc, ED_HPP_PAGING, ED_HPP_PAGE_MAC);
1209 for (n = 0, checksum = 0; n < ETHER_ADDR_LEN; n++)
1210 checksum += (sc->arpcom.ac_enaddr[n] =
1211 ed_asic_inb(sc, ED_HPP_MAC_ADDR + n));
1213 checksum += ed_asic_inb(sc, ED_HPP_MAC_ADDR + ETHER_ADDR_LEN);
1215 if (checksum != 0xFF)
1219 * Verify that the software model number is 0.
1222 ed_asic_outw(sc, ED_HPP_PAGING, ED_HPP_PAGE_ID);
1223 if (((sc->hpp_id = ed_asic_inw(sc, ED_HPP_PAGE_4)) &
1224 ED_HPP_ID_SOFT_MODEL_MASK) != 0x0000)
1228 * Read in and save the current options configured on card.
1231 sc->hpp_options = ed_asic_inw(sc, ED_HPP_OPTION);
1233 sc->hpp_options |= (ED_HPP_OPTION_NIC_RESET |
1234 ED_HPP_OPTION_CHIP_RESET |
1235 ED_HPP_OPTION_ENABLE_IRQ);
1238 * Reset the chip. This requires writing to the option register
1239 * so take care to preserve the other bits.
1242 ed_asic_outw(sc, ED_HPP_OPTION,
1243 (sc->hpp_options & ~(ED_HPP_OPTION_NIC_RESET |
1244 ED_HPP_OPTION_CHIP_RESET)));
1246 DELAY(5000); /* wait for chip reset to complete */
1248 ed_asic_outw(sc, ED_HPP_OPTION,
1249 (sc->hpp_options | (ED_HPP_OPTION_NIC_RESET |
1250 ED_HPP_OPTION_CHIP_RESET |
1251 ED_HPP_OPTION_ENABLE_IRQ)));
1255 if (!(ed_nic_inb(sc, ED_P0_ISR) & ED_ISR_RST))
1256 return ENXIO; /* reset did not complete */
1259 * Read out configuration information.
1262 ed_asic_outw(sc, ED_HPP_PAGING, ED_HPP_PAGE_HW);
1264 irq = ed_asic_inb(sc, ED_HPP_HW_IRQ);
1267 * Check for impossible IRQ.
1270 if (irq >= (sizeof(ed_hpp_intr_val) / sizeof(ed_hpp_intr_val[0])))
1274 * If the kernel IRQ was specified with a '?' use the cards idea
1275 * of the IRQ. If the kernel IRQ was explicitly specified, it
1276 * should match that of the hardware.
1278 error = bus_get_resource(dev, SYS_RES_IRQ, 0,
1281 bus_set_resource(dev, SYS_RES_IRQ, 0,
1282 ed_hpp_intr_val[irq], 1);
1284 if (conf_irq != ed_hpp_intr_val[irq])
1289 * Fill in softconfig info.
1292 sc->vendor = ED_VENDOR_HP;
1293 sc->type = ED_TYPE_HP_PCLANPLUS;
1294 sc->type_str = "HP-PCLAN+";
1296 sc->mem_shared = 0; /* we DON'T have dual ported RAM */
1297 sc->mem_start = 0; /* we use offsets inside the card RAM */
1299 sc->hpp_mem_start = NULL;/* no memory mapped I/O by default */
1302 * The board has 32KB of memory. Is there a way to determine
1303 * this programmatically?
1309 * Check if memory mapping of the I/O registers possible.
1312 if (sc->hpp_options & ED_HPP_OPTION_MEM_ENABLE)
1317 * determine the memory address from the board.
1320 ed_asic_outw(sc, ED_HPP_PAGING, ED_HPP_PAGE_HW);
1321 mem_addr = (ed_asic_inw(sc, ED_HPP_HW_MEM_MAP) << 8);
1324 * Check that the kernel specified start of memory and
1325 * hardware's idea of it match.
1327 error = bus_get_resource(dev, SYS_RES_MEMORY, 0,
1328 &conf_maddr, &conf_msize);
1332 if (mem_addr != conf_maddr)
1335 error = ed_alloc_memory(dev, 0, memsize);
1339 sc->hpp_mem_start = rman_get_virtual(sc->mem_res);
1343 * Fill in the rest of the soft config structure.
1347 * The transmit page index.
1350 sc->tx_page_start = ED_HPP_TX_PAGE_OFFSET;
1352 if (device_get_flags(dev) & ED_FLAGS_NO_MULTI_BUFFERING)
1358 * Memory description
1361 sc->mem_size = memsize;
1362 sc->mem_ring = sc->mem_start +
1363 (sc->txb_cnt * ED_PAGE_SIZE * ED_TXBUF_SIZE);
1364 sc->mem_end = sc->mem_start + sc->mem_size;
1367 * Receive area starts after the transmit area and
1368 * continues till the end of memory.
1371 sc->rec_page_start = sc->tx_page_start +
1372 (sc->txb_cnt * ED_TXBUF_SIZE);
1373 sc->rec_page_stop = (sc->mem_size / ED_PAGE_SIZE);
1376 sc->cr_proto = 0; /* value works */
1379 * Set the wrap registers for string I/O reads.
1382 ed_asic_outw(sc, ED_HPP_PAGING, ED_HPP_PAGE_HW);
1383 ed_asic_outw(sc, ED_HPP_HW_WRAP,
1384 ((sc->rec_page_start / ED_PAGE_SIZE) |
1385 (((sc->rec_page_stop / ED_PAGE_SIZE) - 1) << 8)));
1388 * Reset the register page to normal operation.
1391 ed_asic_outw(sc, ED_HPP_PAGING, ED_HPP_PAGE_PERF);
1394 * Verify that we can read/write from adapter memory.
1395 * Create test pattern.
1398 for (n = 0; n < ED_HPP_TEST_SIZE; n++)
1400 test_pattern[n] = (n*n) ^ ~n;
1403 #undef ED_HPP_TEST_SIZE
1406 * Check that the memory is accessible thru the I/O ports.
1407 * Write out the contents of "test_pattern", read back
1408 * into "test_buffer" and compare the two for any
1412 for (n = 0; n < (32768 / ED_PAGE_SIZE); n ++) {
1414 ed_hpp_writemem(sc, test_pattern, (n * ED_PAGE_SIZE),
1415 sizeof(test_pattern));
1416 ed_hpp_readmem(sc, (n * ED_PAGE_SIZE),
1417 test_buffer, sizeof(test_pattern));
1419 if (bcmp(test_pattern, test_buffer,
1420 sizeof(test_pattern)))
1429 * HP PC Lan+ : Set the physical link to use AUI or TP/TL.
1433 ed_hpp_set_physical_link(struct ed_softc *sc)
1435 struct ifnet *ifp = &sc->arpcom.ac_if;
1438 ed_asic_outw(sc, ED_HPP_PAGING, ED_HPP_PAGE_LAN);
1439 lan_page = ed_asic_inw(sc, ED_HPP_PAGE_0);
1441 if (ifp->if_flags & IFF_ALTPHYS) {
1447 lan_page |= ED_HPP_LAN_AUI;
1449 ed_asic_outw(sc, ED_HPP_PAGING, ED_HPP_PAGE_LAN);
1450 ed_asic_outw(sc, ED_HPP_PAGE_0, lan_page);
1456 * Use the ThinLan interface
1459 lan_page &= ~ED_HPP_LAN_AUI;
1461 ed_asic_outw(sc, ED_HPP_PAGING, ED_HPP_PAGE_LAN);
1462 ed_asic_outw(sc, ED_HPP_PAGE_0, lan_page);
1467 * Wait for the lan card to re-initialize itself
1470 DELAY(150000); /* wait 150 ms */
1473 * Restore normal pages.
1476 ed_asic_outw(sc, ED_HPP_PAGING, ED_HPP_PAGE_PERF);
1481 * Allocate a port resource with the given resource id.
1484 ed_alloc_port(dev, rid, size)
1489 struct ed_softc *sc = device_get_softc(dev);
1490 struct resource *res;
1492 res = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid,
1493 0ul, ~0ul, size, RF_ACTIVE);
1497 sc->port_used = size;
1505 * Allocate a memory resource with the given resource id.
1508 ed_alloc_memory(dev, rid, size)
1513 struct ed_softc *sc = device_get_softc(dev);
1514 struct resource *res;
1516 res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid,
1517 0ul, ~0ul, size, RF_ACTIVE);
1521 sc->mem_used = size;
1529 * Allocate an irq resource with the given resource id.
1532 ed_alloc_irq(dev, rid, flags)
1537 struct ed_softc *sc = device_get_softc(dev);
1538 struct resource *res;
1540 res = bus_alloc_resource(dev, SYS_RES_IRQ, &rid,
1541 0ul, ~0ul, 1, (RF_ACTIVE | flags));
1552 * Release all resources
1555 ed_release_resources(dev)
1558 struct ed_softc *sc = device_get_softc(dev);
1561 bus_release_resource(dev, SYS_RES_IOPORT,
1562 sc->port_rid, sc->port_res);
1566 bus_release_resource(dev, SYS_RES_MEMORY,
1567 sc->mem_rid, sc->mem_res);
1571 bus_release_resource(dev, SYS_RES_IRQ,
1572 sc->irq_rid, sc->irq_res);
1578 * Install interface into kernel networking data structures
1581 ed_attach(sc, unit, flags)
1582 struct ed_softc *sc;
1586 struct ifnet *ifp = &sc->arpcom.ac_if;
1588 callout_handle_init(&sc->tick_ch);
1590 * Set interface to stopped condition (reset)
1594 if (!ifp->if_name) {
1596 * Initialize ifnet structure
1599 ifp->if_unit = unit;
1600 ifp->if_name = "ed";
1601 ifp->if_output = ether_output;
1602 ifp->if_start = ed_start;
1603 ifp->if_ioctl = ed_ioctl;
1604 ifp->if_watchdog = ed_watchdog;
1605 ifp->if_init = ed_init;
1606 ifp->if_snd.ifq_maxlen = IFQ_MAXLEN;
1607 ifp->if_linkmib = &sc->mibdata;
1608 ifp->if_linkmiblen = sizeof sc->mibdata;
1610 * XXX - should do a better job.
1612 if (sc->chip_type == ED_CHIP_TYPE_WD790)
1613 sc->mibdata.dot3StatsEtherChipSet =
1614 DOT3CHIPSET(dot3VendorWesternDigital,
1615 dot3ChipSetWesternDigital83C790);
1617 sc->mibdata.dot3StatsEtherChipSet =
1618 DOT3CHIPSET(dot3VendorNational,
1619 dot3ChipSetNational8390);
1620 sc->mibdata.dot3Compliance = DOT3COMPLIANCE_COLLS;
1623 * Set default state for ALTPHYS flag (used to disable the
1624 * tranceiver for AUI operation), based on compile-time
1627 if (flags & ED_FLAGS_DISABLE_TRANCEIVER)
1628 ifp->if_flags = (IFF_BROADCAST | IFF_SIMPLEX |
1629 IFF_MULTICAST | IFF_ALTPHYS);
1631 ifp->if_flags = (IFF_BROADCAST | IFF_SIMPLEX |
1635 * Attach the interface
1637 ether_ifattach(ifp, ETHER_BPF_SUPPORTED);
1639 /* device attach does transition from UNCONFIGURED to IDLE state */
1642 * Print additional info when attached
1644 printf("%s%d: address %6D, ", ifp->if_name, ifp->if_unit,
1645 sc->arpcom.ac_enaddr, ":");
1647 if (sc->type_str && (*sc->type_str != 0))
1648 printf("type %s ", sc->type_str);
1650 printf("type unknown (0x%x) ", sc->type);
1652 if (sc->vendor == ED_VENDOR_HP)
1653 printf("(%s %s IO)", (sc->hpp_id & ED_HPP_ID_16_BIT_ACCESS) ?
1654 "16-bit" : "32-bit",
1655 sc->hpp_mem_start ? "memory mapped" : "regular");
1657 printf("%s ", sc->isa16bit ? "(16 bit)" : "(8 bit)");
1659 printf("%s\n", (((sc->vendor == ED_VENDOR_3COM) ||
1660 (sc->vendor == ED_VENDOR_HP)) &&
1661 (ifp->if_flags & IFF_ALTPHYS)) ? " tranceiver disabled" : "");
1673 struct ed_softc *sc = ifp->if_softc;
1681 * Stop interface and re-initialize.
1690 * Take interface offline.
1694 struct ed_softc *sc;
1698 untimeout(ed_tick, sc, sc->tick_ch);
1699 callout_handle_init(&sc->tick_ch);
1703 * Stop everything on the interface, and select page 0 registers.
1705 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STP);
1708 * Wait for interface to enter stopped state, but limit # of checks to
1709 * 'n' (about 5ms). It shouldn't even take 5us on modern DS8390's, but
1710 * just in case it's an old one.
1712 if (sc->chip_type != ED_CHIP_TYPE_AX88190)
1713 while (((ed_nic_inb(sc, ED_P0_ISR) & ED_ISR_RST) == 0) && --n);
1717 * Device timeout/watchdog routine. Entered if the device neglects to
1718 * generate an interrupt after a transmit has been started on it.
1724 struct ed_softc *sc = ifp->if_softc;
1728 log(LOG_ERR, "ed%d: device timeout\n", ifp->if_unit);
1738 struct ed_softc *sc = arg;
1739 struct mii_data *mii;
1743 callout_handle_init(&sc->tick_ch);
1747 if (sc->miibus != NULL) {
1748 mii = device_get_softc(sc->miibus);
1751 sc->tick_ch = timeout(ed_tick, sc, hz);
1756 * Initialize device.
1762 struct ed_softc *sc = xsc;
1763 struct ifnet *ifp = &sc->arpcom.ac_if;
1769 /* address not known */
1770 if (TAILQ_EMPTY(&ifp->if_addrhead)) /* unlikely? XXX */
1774 * Initialize the NIC in the exact order outlined in the NS manual.
1775 * This init procedure is "mandatory"...don't change what or when
1780 /* reset transmitter flags */
1786 sc->txb_next_tx = 0;
1788 /* This variable is used below - don't move this assignment */
1789 sc->next_packet = sc->rec_page_start + 1;
1792 * Set interface for page 0, Remote DMA complete, Stopped
1794 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STP);
1799 * Set FIFO threshold to 8, No auto-init Remote DMA, byte
1800 * order=80x86, word-wide DMA xfers,
1802 ed_nic_outb(sc, ED_P0_DCR, ED_DCR_FT1 | ED_DCR_WTS | ED_DCR_LS);
1806 * Same as above, but byte-wide DMA xfers
1808 ed_nic_outb(sc, ED_P0_DCR, ED_DCR_FT1 | ED_DCR_LS);
1812 * Clear Remote Byte Count Registers
1814 ed_nic_outb(sc, ED_P0_RBCR0, 0);
1815 ed_nic_outb(sc, ED_P0_RBCR1, 0);
1818 * For the moment, don't store incoming packets in memory.
1820 ed_nic_outb(sc, ED_P0_RCR, ED_RCR_MON);
1823 * Place NIC in internal loopback mode
1825 ed_nic_outb(sc, ED_P0_TCR, ED_TCR_LB0);
1828 * Initialize transmit/receive (ring-buffer) Page Start
1830 ed_nic_outb(sc, ED_P0_TPSR, sc->tx_page_start);
1831 ed_nic_outb(sc, ED_P0_PSTART, sc->rec_page_start);
1832 /* Set lower bits of byte addressable framing to 0 */
1833 if (sc->chip_type == ED_CHIP_TYPE_WD790)
1834 ed_nic_outb(sc, 0x09, 0);
1837 * Initialize Receiver (ring-buffer) Page Stop and Boundry
1839 ed_nic_outb(sc, ED_P0_PSTOP, sc->rec_page_stop);
1840 ed_nic_outb(sc, ED_P0_BNRY, sc->rec_page_start);
1843 * Clear all interrupts. A '1' in each bit position clears the
1844 * corresponding flag.
1846 ed_nic_outb(sc, ED_P0_ISR, 0xff);
1849 * Enable the following interrupts: receive/transmit complete,
1850 * receive/transmit error, and Receiver OverWrite.
1852 * Counter overflow and Remote DMA complete are *not* enabled.
1854 ed_nic_outb(sc, ED_P0_IMR,
1855 ED_IMR_PRXE | ED_IMR_PTXE | ED_IMR_RXEE | ED_IMR_TXEE | ED_IMR_OVWE);
1858 * Program Command Register for page 1
1860 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_PAGE_1 | ED_CR_STP);
1863 * Copy out our station address
1865 for (i = 0; i < ETHER_ADDR_LEN; ++i)
1866 ed_nic_outb(sc, ED_P1_PAR(i), sc->arpcom.ac_enaddr[i]);
1869 * Set Current Page pointer to next_packet (initialized above)
1871 ed_nic_outb(sc, ED_P1_CURR, sc->next_packet);
1874 * Program Receiver Configuration Register and multicast filter. CR is
1875 * set to page 0 on return.
1880 * Take interface out of loopback
1882 ed_nic_outb(sc, ED_P0_TCR, 0);
1885 * If this is a 3Com board, the tranceiver must be software enabled
1886 * (there is no settable hardware default).
1888 if (sc->vendor == ED_VENDOR_3COM) {
1889 if (ifp->if_flags & IFF_ALTPHYS) {
1890 ed_asic_outb(sc, ED_3COM_CR, 0);
1892 ed_asic_outb(sc, ED_3COM_CR, ED_3COM_CR_XSEL);
1896 if (sc->miibus != NULL) {
1897 struct mii_data *mii;
1898 mii = device_get_softc(sc->miibus);
1902 * Set 'running' flag, and clear output active flag.
1904 ifp->if_flags |= IFF_RUNNING;
1905 ifp->if_flags &= ~IFF_OACTIVE;
1908 * ...and attempt to start output
1912 untimeout(ed_tick, sc, sc->tick_ch);
1913 sc->tick_ch = timeout(ed_tick, sc, hz);
1918 * This routine actually starts the transmission on the interface
1920 static __inline void
1922 struct ed_softc *sc;
1924 struct ifnet *ifp = (struct ifnet *)sc;
1929 len = sc->txb_len[sc->txb_next_tx];
1932 * Set NIC for page 0 register access
1934 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STA);
1937 * Set TX buffer start page
1939 ed_nic_outb(sc, ED_P0_TPSR, sc->tx_page_start +
1940 sc->txb_next_tx * ED_TXBUF_SIZE);
1945 ed_nic_outb(sc, ED_P0_TBCR0, len);
1946 ed_nic_outb(sc, ED_P0_TBCR1, len >> 8);
1949 * Set page 0, Remote DMA complete, Transmit Packet, and *Start*
1951 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_TXP | ED_CR_STA);
1955 * Point to next transmit buffer slot and wrap if necessary.
1958 if (sc->txb_next_tx == sc->txb_cnt)
1959 sc->txb_next_tx = 0;
1962 * Set a timer just in case we never hear from the board again
1968 * Start output on interface.
1969 * We make two assumptions here:
1970 * 1) that the current priority is set to splimp _before_ this code
1971 * is called *and* is returned to the appropriate priority after
1973 * 2) that the IFF_OACTIVE flag is checked before this code is called
1974 * (i.e. that the output part of the interface is idle)
1980 struct ed_softc *sc = ifp->if_softc;
1981 struct mbuf *m0, *m;
1986 printf("ed_start(%p) GONE\n",ifp);
1992 * First, see if there are buffered packets and an idle transmitter -
1993 * should never happen at this point.
1995 if (sc->txb_inuse && (sc->xmit_busy == 0)) {
1996 printf("ed: packets buffered, but transmitter idle\n");
2001 * See if there is room to put another packet in the buffer.
2003 if (sc->txb_inuse == sc->txb_cnt) {
2006 * No room. Indicate this to the outside world and exit.
2008 ifp->if_flags |= IFF_OACTIVE;
2011 IF_DEQUEUE(&ifp->if_snd, m);
2015 * We are using the !OACTIVE flag to indicate to the outside
2016 * world that we can accept an additional packet rather than
2017 * that the transmitter is _actually_ active. Indeed, the
2018 * transmitter may be active, but if we haven't filled all the
2019 * buffers with data then we still want to accept more.
2021 ifp->if_flags &= ~IFF_OACTIVE;
2026 * Copy the mbuf chain into the transmit buffer
2031 /* txb_new points to next open buffer slot */
2032 buffer = sc->mem_start + (sc->txb_new * ED_TXBUF_SIZE * ED_PAGE_SIZE);
2034 if (sc->mem_shared) {
2037 * Special case setup for 16 bit boards...
2040 switch (sc->vendor) {
2043 * For 16bit 3Com boards (which have 16k of
2044 * memory), we have the xmit buffers in a
2045 * different page of memory ('page 0') - so
2048 case ED_VENDOR_3COM:
2049 ed_asic_outb(sc, ED_3COM_GACFR,
2050 ED_3COM_GACFR_RSEL);
2054 * Enable 16bit access to shared memory on
2057 case ED_VENDOR_WD_SMC:
2058 ed_asic_outb(sc, ED_WD_LAAR,
2059 sc->wd_laar_proto | ED_WD_LAAR_M16EN);
2060 if (sc->chip_type == ED_CHIP_TYPE_WD790) {
2061 ed_asic_outb(sc, ED_WD_MSR, ED_WD_MSR_MENB);
2066 for (len = 0; m != 0; m = m->m_next) {
2067 bcopy(mtod(m, caddr_t), buffer, m->m_len);
2073 * Restore previous shared memory access
2076 switch (sc->vendor) {
2077 case ED_VENDOR_3COM:
2078 ed_asic_outb(sc, ED_3COM_GACFR,
2079 ED_3COM_GACFR_RSEL | ED_3COM_GACFR_MBS0);
2081 case ED_VENDOR_WD_SMC:
2082 if (sc->chip_type == ED_CHIP_TYPE_WD790) {
2083 ed_asic_outb(sc, ED_WD_MSR, 0x00);
2085 ed_asic_outb(sc, ED_WD_LAAR,
2086 sc->wd_laar_proto & ~ED_WD_LAAR_M16EN);
2091 len = ed_pio_write_mbufs(sc, m, (int)buffer);
2096 sc->txb_len[sc->txb_new] = max(len, (ETHER_MIN_LEN-ETHER_CRC_LEN));
2101 * Point to next buffer slot and wrap if necessary.
2104 if (sc->txb_new == sc->txb_cnt)
2107 if (sc->xmit_busy == 0)
2111 * Tap off here if there is a bpf listener.
2120 * Loop back to the top to possibly buffer more packets
2126 * Ethernet interface receiver interrupt.
2128 static __inline void
2130 struct ed_softc *sc;
2132 struct ifnet *ifp = &sc->arpcom.ac_if;
2135 struct ed_ring packet_hdr;
2142 * Set NIC to page 1 registers to get 'current' pointer
2144 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_PAGE_1 | ED_CR_STA);
2147 * 'sc->next_packet' is the logical beginning of the ring-buffer -
2148 * i.e. it points to where new data has been buffered. The 'CURR'
2149 * (current) register points to the logical end of the ring-buffer -
2150 * i.e. it points to where additional new data will be added. We loop
2151 * here until the logical beginning equals the logical end (or in
2152 * other words, until the ring-buffer is empty).
2154 while (sc->next_packet != ed_nic_inb(sc, ED_P1_CURR)) {
2156 /* get pointer to this buffer's header structure */
2157 packet_ptr = sc->mem_ring +
2158 (sc->next_packet - sc->rec_page_start) * ED_PAGE_SIZE;
2161 * The byte count includes a 4 byte header that was added by
2165 packet_hdr = *(struct ed_ring *) packet_ptr;
2167 ed_pio_readmem(sc, (int)packet_ptr, (char *) &packet_hdr,
2168 sizeof(packet_hdr));
2169 len = packet_hdr.count;
2170 if (len > (ETHER_MAX_LEN - ETHER_CRC_LEN + sizeof(struct ed_ring)) ||
2171 len < (ETHER_MIN_LEN - ETHER_CRC_LEN + sizeof(struct ed_ring))) {
2173 * Length is a wild value. There's a good chance that
2174 * this was caused by the NIC being old and buggy.
2175 * The bug is that the length low byte is duplicated in
2176 * the high byte. Try to recalculate the length based on
2177 * the pointer to the next packet.
2180 * NOTE: sc->next_packet is pointing at the current packet.
2182 len &= ED_PAGE_SIZE - 1; /* preserve offset into page */
2183 if (packet_hdr.next_packet >= sc->next_packet) {
2184 len += (packet_hdr.next_packet - sc->next_packet) * ED_PAGE_SIZE;
2186 len += ((packet_hdr.next_packet - sc->rec_page_start) +
2187 (sc->rec_page_stop - sc->next_packet)) * ED_PAGE_SIZE;
2190 * because buffers are aligned on 256-byte boundary,
2191 * the length computed above is off by 256 in almost
2192 * all cases. Fix it...
2196 if (len > (ETHER_MAX_LEN - ETHER_CRC_LEN
2197 + sizeof(struct ed_ring)))
2198 sc->mibdata.dot3StatsFrameTooLongs++;
2201 * Be fairly liberal about what we allow as a "reasonable" length
2202 * so that a [crufty] packet will make it to BPF (and can thus
2203 * be analyzed). Note that all that is really important is that
2204 * we have a length that will fit into one mbuf cluster or less;
2205 * the upper layer protocols can then figure out the length from
2206 * their own length field(s).
2207 * But make sure that we have at least a full ethernet header
2208 * or we would be unable to call ether_input() later.
2210 if ((len >= sizeof(struct ed_ring) + ETHER_HDR_LEN) &&
2211 (len <= MCLBYTES) &&
2212 (packet_hdr.next_packet >= sc->rec_page_start) &&
2213 (packet_hdr.next_packet < sc->rec_page_stop)) {
2217 ed_get_packet(sc, packet_ptr + sizeof(struct ed_ring),
2218 len - sizeof(struct ed_ring));
2222 * Really BAD. The ring pointers are corrupted.
2225 "ed%d: NIC memory corrupt - invalid packet length %d\n",
2233 * Update next packet pointer
2235 sc->next_packet = packet_hdr.next_packet;
2238 * Update NIC boundry pointer - being careful to keep it one
2239 * buffer behind. (as recommended by NS databook)
2241 boundry = sc->next_packet - 1;
2242 if (boundry < sc->rec_page_start)
2243 boundry = sc->rec_page_stop - 1;
2246 * Set NIC to page 0 registers to update boundry register
2248 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STA);
2250 ed_nic_outb(sc, ED_P0_BNRY, boundry);
2253 * Set NIC to page 1 registers before looping to top (prepare
2254 * to get 'CURR' current pointer)
2256 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_PAGE_1 | ED_CR_STA);
2261 * Ethernet interface interrupt processor
2267 struct ed_softc *sc = (struct ed_softc*) arg;
2268 struct ifnet *ifp = (struct ifnet *)sc;
2274 * Set NIC to page 0 registers
2276 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STA);
2279 * loop until there are no more new interrupts
2281 while ((isr = ed_nic_inb(sc, ED_P0_ISR)) != 0) {
2284 * reset all the bits that we are 'acknowledging' by writing a
2285 * '1' to each bit position that was set (writing a '1'
2288 ed_nic_outb(sc, ED_P0_ISR, isr);
2290 /* XXX workaround for AX88190 */
2291 if (sc->chip_type == ED_CHIP_TYPE_AX88190) {
2292 while (ed_nic_inb(sc, ED_P0_ISR) & isr) {
2293 ed_nic_outb(sc, ED_P0_ISR,0);
2294 ed_nic_outb(sc, ED_P0_ISR,isr);
2299 * Handle transmitter interrupts. Handle these first because
2300 * the receiver will reset the board under some conditions.
2302 if (isr & (ED_ISR_PTX | ED_ISR_TXE)) {
2303 u_char collisions = ed_nic_inb(sc, ED_P0_NCR) & 0x0f;
2306 * Check for transmit error. If a TX completed with an
2307 * error, we end up throwing the packet away. Really
2308 * the only error that is possible is excessive
2309 * collisions, and in this case it is best to allow
2310 * the automatic mechanisms of TCP to backoff the
2311 * flow. Of course, with UDP we're screwed, but this
2312 * is expected when a network is heavily loaded.
2314 (void) ed_nic_inb(sc, ED_P0_TSR);
2315 if (isr & ED_ISR_TXE) {
2319 * Excessive collisions (16)
2321 tsr = ed_nic_inb(sc, ED_P0_TSR);
2322 if ((tsr & ED_TSR_ABT)
2323 && (collisions == 0)) {
2326 * When collisions total 16, the
2327 * P0_NCR will indicate 0, and the
2331 sc->mibdata.dot3StatsExcessiveCollisions++;
2332 sc->mibdata.dot3StatsCollFrequencies[15]++;
2334 if (tsr & ED_TSR_OWC)
2335 sc->mibdata.dot3StatsLateCollisions++;
2336 if (tsr & ED_TSR_CDH)
2337 sc->mibdata.dot3StatsSQETestErrors++;
2338 if (tsr & ED_TSR_CRS)
2339 sc->mibdata.dot3StatsCarrierSenseErrors++;
2340 if (tsr & ED_TSR_FU)
2341 sc->mibdata.dot3StatsInternalMacTransmitErrors++;
2344 * update output errors counter
2350 * Update total number of successfully
2351 * transmitted packets.
2357 * reset tx busy and output active flags
2360 ifp->if_flags &= ~IFF_OACTIVE;
2363 * clear watchdog timer
2368 * Add in total number of collisions on last
2371 ifp->if_collisions += collisions;
2372 switch(collisions) {
2377 sc->mibdata.dot3StatsSingleCollisionFrames++;
2378 sc->mibdata.dot3StatsCollFrequencies[0]++;
2381 sc->mibdata.dot3StatsMultipleCollisionFrames++;
2383 dot3StatsCollFrequencies[collisions-1]
2389 * Decrement buffer in-use count if not zero (can only
2390 * be zero if a transmitter interrupt occured while
2391 * not actually transmitting). If data is ready to
2392 * transmit, start it transmitting, otherwise defer
2393 * until after handling receiver
2395 if (sc->txb_inuse && --sc->txb_inuse)
2400 * Handle receiver interrupts
2402 if (isr & (ED_ISR_PRX | ED_ISR_RXE | ED_ISR_OVW)) {
2405 * Overwrite warning. In order to make sure that a
2406 * lockup of the local DMA hasn't occurred, we reset
2407 * and re-init the NIC. The NSC manual suggests only a
2408 * partial reset/re-init is necessary - but some chips
2409 * seem to want more. The DMA lockup has been seen
2410 * only with early rev chips - Methinks this bug was
2411 * fixed in later revs. -DG
2413 if (isr & ED_ISR_OVW) {
2417 "ed%d: warning - receiver ring buffer overrun\n",
2422 * Stop/reset/re-init NIC
2428 * Receiver Error. One or more of: CRC error,
2429 * frame alignment error FIFO overrun, or
2432 if (isr & ED_ISR_RXE) {
2434 rsr = ed_nic_inb(sc, ED_P0_RSR);
2435 if (rsr & ED_RSR_CRC)
2436 sc->mibdata.dot3StatsFCSErrors++;
2437 if (rsr & ED_RSR_FAE)
2438 sc->mibdata.dot3StatsAlignmentErrors++;
2439 if (rsr & ED_RSR_FO)
2440 sc->mibdata.dot3StatsInternalMacReceiveErrors++;
2443 printf("ed%d: receive error %x\n", ifp->if_unit,
2444 ed_nic_inb(sc, ED_P0_RSR));
2449 * Go get the packet(s) XXX - Doing this on an
2450 * error is dubious because there shouldn't be
2451 * any data to get (we've configured the
2452 * interface to not accept packets with
2457 * Enable 16bit access to shared memory first
2461 (sc->vendor == ED_VENDOR_WD_SMC)) {
2463 ed_asic_outb(sc, ED_WD_LAAR,
2464 sc->wd_laar_proto | ED_WD_LAAR_M16EN);
2465 if (sc->chip_type == ED_CHIP_TYPE_WD790) {
2466 ed_asic_outb(sc, ED_WD_MSR,
2472 /* disable 16bit access */
2474 (sc->vendor == ED_VENDOR_WD_SMC)) {
2476 if (sc->chip_type == ED_CHIP_TYPE_WD790) {
2477 ed_asic_outb(sc, ED_WD_MSR, 0x00);
2479 ed_asic_outb(sc, ED_WD_LAAR,
2480 sc->wd_laar_proto & ~ED_WD_LAAR_M16EN);
2486 * If it looks like the transmitter can take more data,
2487 * attempt to start output on the interface. This is done
2488 * after handling the receiver to give the receiver priority.
2490 if ((ifp->if_flags & IFF_OACTIVE) == 0)
2494 * return NIC CR to standard state: page 0, remote DMA
2495 * complete, start (toggling the TXP bit off, even if was just
2496 * set in the transmit routine, is *okay* - it is 'edge'
2497 * triggered from low to high)
2499 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STA);
2502 * If the Network Talley Counters overflow, read them to reset
2503 * them. It appears that old 8390's won't clear the ISR flag
2504 * otherwise - resulting in an infinite loop.
2506 if (isr & ED_ISR_CNT) {
2507 (void) ed_nic_inb(sc, ED_P0_CNTR0);
2508 (void) ed_nic_inb(sc, ED_P0_CNTR1);
2509 (void) ed_nic_inb(sc, ED_P0_CNTR2);
2515 * Process an ioctl request. This code needs some work - it looks
2519 ed_ioctl(ifp, command, data)
2524 struct ed_softc *sc = ifp->if_softc;
2525 struct ifreq *ifr = (struct ifreq *)data;
2526 struct mii_data *mii;
2529 if (sc == NULL || sc->gone) {
2530 ifp->if_flags &= ~IFF_RUNNING;
2540 error = ether_ioctl(ifp, command, data);
2546 * If the interface is marked up and stopped, then start it.
2547 * If it is marked down and running, then stop it.
2549 if (ifp->if_flags & IFF_UP) {
2550 if ((ifp->if_flags & IFF_RUNNING) == 0)
2553 if (ifp->if_flags & IFF_RUNNING) {
2555 ifp->if_flags &= ~IFF_RUNNING;
2560 * Promiscuous flag may have changed, so reprogram the RCR.
2565 * An unfortunate hack to provide the (required) software
2566 * control of the tranceiver for 3Com boards. The ALTPHYS flag
2567 * disables the tranceiver if set.
2569 if (sc->vendor == ED_VENDOR_3COM) {
2570 if (ifp->if_flags & IFF_ALTPHYS) {
2571 ed_asic_outb(sc, ED_3COM_CR, 0);
2573 ed_asic_outb(sc, ED_3COM_CR, ED_3COM_CR_XSEL);
2575 } else if (sc->vendor == ED_VENDOR_HP)
2576 ed_hpp_set_physical_link(sc);
2582 * Multicast list has changed; set the hardware filter
2591 if (sc->miibus == NULL) {
2595 mii = device_get_softc(sc->miibus);
2596 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
2607 * Given a source and destination address, copy 'amount' of a packet from
2608 * the ring buffer into a linear destination buffer. Takes into account
2611 static __inline char *
2612 ed_ring_copy(sc, src, dst, amount)
2613 struct ed_softc *sc;
2620 /* does copy wrap to lower addr in ring buffer? */
2621 if (src + amount > sc->mem_end) {
2622 tmp_amount = sc->mem_end - src;
2624 /* copy amount up to end of NIC memory */
2626 bcopy(src, dst, tmp_amount);
2628 ed_pio_readmem(sc, (int)src, dst, tmp_amount);
2630 amount -= tmp_amount;
2635 bcopy(src, dst, amount);
2637 ed_pio_readmem(sc, (int)src, dst, amount);
2639 return (src + amount);
2643 * Retreive packet from shared memory and send to the next level up via
2647 ed_get_packet(sc, buf, len)
2648 struct ed_softc *sc;
2652 struct ether_header *eh;
2655 /* Allocate a header mbuf */
2656 MGETHDR(m, M_DONTWAIT, MT_DATA);
2659 m->m_pkthdr.rcvif = &sc->arpcom.ac_if;
2660 m->m_pkthdr.len = m->m_len = len;
2663 * We always put the received packet in a single buffer -
2664 * either with just an mbuf header or in a cluster attached
2665 * to the header. The +2 is to compensate for the alignment
2668 if ((len + 2) > MHLEN) {
2669 /* Attach an mbuf cluster */
2670 MCLGET(m, M_DONTWAIT);
2672 /* Insist on getting a cluster */
2673 if ((m->m_flags & M_EXT) == 0) {
2680 * The +2 is to longword align the start of the real packet.
2681 * This is important for NFS.
2684 eh = mtod(m, struct ether_header *);
2687 * Don't read in the entire packet if we know we're going to drop it
2688 * and no bpf is active.
2690 if (!sc->arpcom.ac_if.if_bpf && BDG_ACTIVE( (&sc->arpcom.ac_if) ) ) {
2693 ed_ring_copy(sc, buf, (char *)eh, ETHER_HDR_LEN);
2694 bif = bridge_in_ptr(&sc->arpcom.ac_if, eh) ;
2695 if (bif == BDG_DROP) {
2699 if (len > ETHER_HDR_LEN)
2700 ed_ring_copy(sc, buf + ETHER_HDR_LEN,
2701 (char *)(eh + 1), len - ETHER_HDR_LEN);
2704 * Get packet, including link layer address, from interface.
2706 ed_ring_copy(sc, buf, (char *)eh, len);
2709 * Remove link layer address.
2711 m->m_pkthdr.len = m->m_len = len - sizeof(struct ether_header);
2712 m->m_data += sizeof(struct ether_header);
2714 ether_input(&sc->arpcom.ac_if, eh, m);
2718 * Supporting routines
2722 * Given a NIC memory source address and a host memory destination
2723 * address, copy 'amount' from NIC to host using Programmed I/O.
2724 * The 'amount' is rounded up to a word - okay as long as mbufs
2726 * This routine is currently Novell-specific.
2729 ed_pio_readmem(sc, src, dst, amount)
2730 struct ed_softc *sc;
2733 unsigned short amount;
2735 /* HP PC Lan+ cards need special handling */
2736 if (sc->vendor == ED_VENDOR_HP && sc->type == ED_TYPE_HP_PCLANPLUS) {
2737 ed_hpp_readmem(sc, src, dst, amount);
2741 /* Regular Novell cards */
2742 /* select page 0 registers */
2743 ed_nic_outb(sc, ED_P0_CR, ED_CR_RD2 | ED_CR_STA);
2745 /* round up to a word */
2749 /* set up DMA byte count */
2750 ed_nic_outb(sc, ED_P0_RBCR0, amount);
2751 ed_nic_outb(sc, ED_P0_RBCR1, amount >> 8);
2753 /* set up source address in NIC mem */
2754 ed_nic_outb(sc, ED_P0_RSAR0, src);
2755 ed_nic_outb(sc, ED_P0_RSAR1, src >> 8);
2757 ed_nic_outb(sc, ED_P0_CR, ED_CR_RD0 | ED_CR_STA);
2760 ed_asic_insw(sc, ED_NOVELL_DATA, dst, amount / 2);
2762 ed_asic_insb(sc, ED_NOVELL_DATA, dst, amount);
2767 * Stripped down routine for writing a linear buffer to NIC memory.
2768 * Only used in the probe routine to test the memory. 'len' must
2772 ed_pio_writemem(sc, src, dst, len)
2773 struct ed_softc *sc;
2778 int maxwait = 200; /* about 240us */
2780 /* select page 0 registers */
2781 ed_nic_outb(sc, ED_P0_CR, ED_CR_RD2 | ED_CR_STA);
2783 /* reset remote DMA complete flag */
2784 ed_nic_outb(sc, ED_P0_ISR, ED_ISR_RDC);
2786 /* set up DMA byte count */
2787 ed_nic_outb(sc, ED_P0_RBCR0, len);
2788 ed_nic_outb(sc, ED_P0_RBCR1, len >> 8);
2790 /* set up destination address in NIC mem */
2791 ed_nic_outb(sc, ED_P0_RSAR0, dst);
2792 ed_nic_outb(sc, ED_P0_RSAR1, dst >> 8);
2794 /* set remote DMA write */
2795 ed_nic_outb(sc, ED_P0_CR, ED_CR_RD1 | ED_CR_STA);
2798 ed_asic_outsw(sc, ED_NOVELL_DATA, src, len / 2);
2800 ed_asic_outsb(sc, ED_NOVELL_DATA, src, len);
2804 * Wait for remote DMA complete. This is necessary because on the
2805 * transmit side, data is handled internally by the NIC in bursts and
2806 * we can't start another remote DMA until this one completes. Not
2807 * waiting causes really bad things to happen - like the NIC
2808 * irrecoverably jamming the ISA bus.
2810 while (((ed_nic_inb(sc, ED_P0_ISR) & ED_ISR_RDC) != ED_ISR_RDC) && --maxwait);
2814 * Write an mbuf chain to the destination NIC memory address using
2818 ed_pio_write_mbufs(sc, m, dst)
2819 struct ed_softc *sc;
2823 struct ifnet *ifp = (struct ifnet *)sc;
2824 unsigned short total_len, dma_len;
2826 int maxwait = 200; /* about 240us */
2828 /* HP PC Lan+ cards need special handling */
2829 if (sc->vendor == ED_VENDOR_HP && sc->type == ED_TYPE_HP_PCLANPLUS) {
2830 return ed_hpp_write_mbufs(sc, m, dst);
2833 /* Regular Novell cards */
2834 /* First, count up the total number of bytes to copy */
2835 for (total_len = 0, mp = m; mp; mp = mp->m_next)
2836 total_len += mp->m_len;
2838 dma_len = total_len;
2839 if (sc->isa16bit && (dma_len & 1))
2842 /* select page 0 registers */
2843 ed_nic_outb(sc, ED_P0_CR, ED_CR_RD2 | ED_CR_STA);
2845 /* reset remote DMA complete flag */
2846 ed_nic_outb(sc, ED_P0_ISR, ED_ISR_RDC);
2848 /* set up DMA byte count */
2849 ed_nic_outb(sc, ED_P0_RBCR0, dma_len);
2850 ed_nic_outb(sc, ED_P0_RBCR1, dma_len >> 8);
2852 /* set up destination address in NIC mem */
2853 ed_nic_outb(sc, ED_P0_RSAR0, dst);
2854 ed_nic_outb(sc, ED_P0_RSAR1, dst >> 8);
2856 /* set remote DMA write */
2857 ed_nic_outb(sc, ED_P0_CR, ED_CR_RD1 | ED_CR_STA);
2860 * Transfer the mbuf chain to the NIC memory.
2861 * 16-bit cards require that data be transferred as words, and only words.
2862 * So that case requires some extra code to patch over odd-length mbufs.
2865 if (!sc->isa16bit) {
2866 /* NE1000s are easy */
2869 ed_asic_outsb(sc, ED_NOVELL_DATA,
2870 m->m_data, m->m_len);
2875 /* NE2000s are a pain */
2876 unsigned char *data;
2878 unsigned char savebyte[2];
2885 data = mtod(m, caddr_t);
2886 /* finish the last word */
2888 savebyte[1] = *data;
2889 ed_asic_outw(sc, ED_NOVELL_DATA,
2890 *(u_short *)savebyte);
2895 /* output contiguous words */
2897 ed_asic_outsw(sc, ED_NOVELL_DATA,
2902 /* save last byte, if necessary */
2904 savebyte[0] = *data;
2910 /* spit last byte */
2912 ed_asic_outw(sc, ED_NOVELL_DATA, *(u_short *)savebyte);
2917 * Wait for remote DMA complete. This is necessary because on the
2918 * transmit side, data is handled internally by the NIC in bursts and
2919 * we can't start another remote DMA until this one completes. Not
2920 * waiting causes really bad things to happen - like the NIC
2921 * irrecoverably jamming the ISA bus.
2923 while (((ed_nic_inb(sc, ED_P0_ISR) & ED_ISR_RDC) != ED_ISR_RDC) && --maxwait);
2926 log(LOG_WARNING, "ed%d: remote transmit DMA failed to complete\n",
2935 * Support routines to handle the HP PC Lan+ card.
2939 * HP PC Lan+: Read from NIC memory, using either PIO or memory mapped
2944 ed_hpp_readmem(sc, src, dst, amount)
2945 struct ed_softc *sc;
2948 unsigned short amount;
2951 int use_32bit_access = !(sc->hpp_id & ED_HPP_ID_16_BIT_ACCESS);
2954 /* Program the source address in RAM */
2955 ed_asic_outw(sc, ED_HPP_PAGE_2, src);
2958 * The HP PC Lan+ card supports word reads as well as
2959 * a memory mapped i/o port that is aliased to every
2960 * even address on the board.
2963 if (sc->hpp_mem_start) {
2965 /* Enable memory mapped access. */
2966 ed_asic_outw(sc, ED_HPP_OPTION, sc->hpp_options &
2967 ~(ED_HPP_OPTION_MEM_DISABLE |
2968 ED_HPP_OPTION_BOOT_ROM_ENB));
2970 if (use_32bit_access && (amount > 3)) {
2971 u_int32_t *dl = (u_int32_t *) dst;
2972 volatile u_int32_t *const sl =
2973 (u_int32_t *) sc->hpp_mem_start;
2974 u_int32_t *const fence = dl + (amount >> 2);
2976 /* Copy out NIC data. We could probably write this
2977 as a `movsl'. The currently generated code is lousy.
2983 dst += (amount & ~3);
2988 /* Finish off any words left, as a series of short reads */
2990 u_short *d = (u_short *) dst;
2991 volatile u_short *const s =
2992 (u_short *) sc->hpp_mem_start;
2993 u_short *const fence = d + (amount >> 1);
2995 /* Copy out NIC data. */
3000 dst += (amount & ~1);
3005 * read in a byte; however we need to always read 16 bits
3006 * at a time or the hardware gets into a funny state
3010 /* need to read in a short and copy LSB */
3011 volatile u_short *const s =
3012 (volatile u_short *) sc->hpp_mem_start;
3017 /* Restore Boot ROM access. */
3019 ed_asic_outw(sc, ED_HPP_OPTION, sc->hpp_options);
3023 /* Read in data using the I/O port */
3024 if (use_32bit_access && (amount > 3)) {
3025 ed_asic_insl(sc, ED_HPP_PAGE_4, dst, amount >> 2);
3026 dst += (amount & ~3);
3030 ed_asic_insw(sc, ED_HPP_PAGE_4, dst, amount >> 1);
3031 dst += (amount & ~1);
3034 if (amount == 1) { /* read in a short and keep the LSB */
3035 *dst = ed_asic_inw(sc, ED_HPP_PAGE_4) & 0xFF;
3041 * HP PC Lan+: Write to NIC memory, using either PIO or memory mapped
3043 * Only used in the probe routine to test the memory. 'len' must
3047 ed_hpp_writemem(sc, src, dst, len)
3048 struct ed_softc *sc;
3053 /* reset remote DMA complete flag */
3054 ed_nic_outb(sc, ED_P0_ISR, ED_ISR_RDC);
3056 /* program the write address in RAM */
3057 ed_asic_outw(sc, ED_HPP_PAGE_0, dst);
3059 if (sc->hpp_mem_start) {
3060 u_short *s = (u_short *) src;
3061 volatile u_short *d = (u_short *) sc->hpp_mem_start;
3062 u_short *const fence = s + (len >> 1);
3065 * Enable memory mapped access.
3068 ed_asic_outw(sc, ED_HPP_OPTION, sc->hpp_options &
3069 ~(ED_HPP_OPTION_MEM_DISABLE |
3070 ED_HPP_OPTION_BOOT_ROM_ENB));
3073 * Copy to NIC memory.
3080 * Restore Boot ROM access.
3083 ed_asic_outw(sc, ED_HPP_OPTION, sc->hpp_options);
3086 /* write data using I/O writes */
3087 ed_asic_outsw(sc, ED_HPP_PAGE_4, src, len / 2);
3092 * Write to HP PC Lan+ NIC memory. Access to the NIC can be by using
3093 * outsw() or via the memory mapped interface to the same register.
3094 * Writes have to be in word units; byte accesses won't work and may cause
3095 * the NIC to behave wierdly. Long word accesses are permitted if the ASIC
3100 ed_hpp_write_mbufs(struct ed_softc *sc, struct mbuf *m, int dst)
3103 unsigned short total_len;
3104 unsigned char savebyte[2];
3105 volatile u_short * const d =
3106 (volatile u_short *) sc->hpp_mem_start;
3107 int use_32bit_accesses = !(sc->hpp_id & ED_HPP_ID_16_BIT_ACCESS);
3109 /* select page 0 registers */
3110 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STA);
3112 /* reset remote DMA complete flag */
3113 ed_nic_outb(sc, ED_P0_ISR, ED_ISR_RDC);
3115 /* program the write address in RAM */
3116 ed_asic_outw(sc, ED_HPP_PAGE_0, dst);
3118 if (sc->hpp_mem_start) /* enable memory mapped I/O */
3119 ed_asic_outw(sc, ED_HPP_OPTION, sc->hpp_options &
3120 ~(ED_HPP_OPTION_MEM_DISABLE |
3121 ED_HPP_OPTION_BOOT_ROM_ENB));
3126 if (sc->hpp_mem_start) { /* Memory mapped I/O port */
3128 total_len += (len = m->m_len);
3130 caddr_t data = mtod(m, caddr_t);
3131 /* finish the last word of the previous mbuf */
3133 savebyte[1] = *data;
3134 *d = *((ushort *) savebyte);
3135 data++; len--; wantbyte = 0;
3137 /* output contiguous words */
3138 if ((len > 3) && (use_32bit_accesses)) {
3139 volatile u_int32_t *const dl =
3140 (volatile u_int32_t *) d;
3141 u_int32_t *sl = (u_int32_t *) data;
3142 u_int32_t *fence = sl + (len >> 2);
3150 /* finish off remain 16 bit writes */
3152 u_short *s = (u_short *) data;
3153 u_short *fence = s + (len >> 1);
3161 /* save last byte if needed */
3162 if ((wantbyte = (len == 1)) != 0)
3163 savebyte[0] = *data;
3165 m = m->m_next; /* to next mbuf */
3167 if (wantbyte) /* write last byte */
3168 *d = *((u_short *) savebyte);
3170 /* use programmed I/O */
3172 total_len += (len = m->m_len);
3174 caddr_t data = mtod(m, caddr_t);
3175 /* finish the last word of the previous mbuf */
3177 savebyte[1] = *data;
3178 ed_asic_outw(sc, ED_HPP_PAGE_4,
3179 *((u_short *)savebyte));
3184 /* output contiguous words */
3185 if ((len > 3) && use_32bit_accesses) {
3186 ed_asic_outsl(sc, ED_HPP_PAGE_4,
3191 /* finish off remaining 16 bit accesses */
3193 ed_asic_outsw(sc, ED_HPP_PAGE_4,
3198 if ((wantbyte = (len == 1)) != 0)
3199 savebyte[0] = *data;
3204 if (wantbyte) /* spit last byte */
3205 ed_asic_outw(sc, ED_HPP_PAGE_4, *(u_short *)savebyte);
3209 if (sc->hpp_mem_start) /* turn off memory mapped i/o */
3210 ed_asic_outw(sc, ED_HPP_OPTION, sc->hpp_options);
3216 * MII bus support routines.
3219 ed_miibus_readreg(dev, phy, reg)
3223 struct ed_softc *sc;
3227 sc = device_get_softc(dev);
3233 (*sc->mii_writebits)(sc, 0xffffffff, 32);
3234 (*sc->mii_writebits)(sc, ED_MII_STARTDELIM, ED_MII_STARTDELIM_BITS);
3235 (*sc->mii_writebits)(sc, ED_MII_READOP, ED_MII_OP_BITS);
3236 (*sc->mii_writebits)(sc, phy, ED_MII_PHY_BITS);
3237 (*sc->mii_writebits)(sc, reg, ED_MII_REG_BITS);
3239 failed = (*sc->mii_readbits)(sc, ED_MII_ACK_BITS);
3240 val = (*sc->mii_readbits)(sc, ED_MII_DATA_BITS);
3241 (*sc->mii_writebits)(sc, ED_MII_IDLE, ED_MII_IDLE_BITS);
3244 return (failed ? 0 : val);
3248 ed_miibus_writereg(dev, phy, reg, data)
3252 struct ed_softc *sc;
3256 sc = device_get_softc(dev);
3262 (*sc->mii_writebits)(sc, 0xffffffff, 32);
3263 (*sc->mii_writebits)(sc, ED_MII_STARTDELIM, ED_MII_STARTDELIM_BITS);
3264 (*sc->mii_writebits)(sc, ED_MII_WRITEOP, ED_MII_OP_BITS);
3265 (*sc->mii_writebits)(sc, phy, ED_MII_PHY_BITS);
3266 (*sc->mii_writebits)(sc, reg, ED_MII_REG_BITS);
3267 (*sc->mii_writebits)(sc, ED_MII_TURNAROUND, ED_MII_TURNAROUND_BITS);
3268 (*sc->mii_writebits)(sc, data, ED_MII_DATA_BITS);
3269 (*sc->mii_writebits)(sc, ED_MII_IDLE, ED_MII_IDLE_BITS);
3278 struct ed_softc *sc;
3279 struct mii_data *mii;
3282 if (sc->gone || sc->miibus == NULL)
3285 mii = device_get_softc(sc->miibus);
3286 return mii_mediachg(mii);
3290 ed_ifmedia_sts(ifp, ifmr)
3292 struct ifmediareq *ifmr;
3294 struct ed_softc *sc;
3295 struct mii_data *mii;
3298 if (sc->gone || sc->miibus == NULL)
3301 mii = device_get_softc(sc->miibus);
3303 ifmr->ifm_active = mii->mii_media_active;
3304 ifmr->ifm_status = mii->mii_media_status;
3308 ed_child_detached(dev, child)
3312 struct ed_softc *sc;
3314 sc = device_get_softc(dev);
3315 if (child == sc->miibus)
3321 struct ed_softc *sc;
3323 struct ifnet *ifp = (struct ifnet *)sc;
3327 /* Bit 6 in AX88190 RCR register must be set. */
3328 if (sc->chip_type == ED_CHIP_TYPE_AX88190)
3333 /* set page 1 registers */
3334 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_PAGE_1 | ED_CR_STP);
3336 if (ifp->if_flags & IFF_PROMISC) {
3339 * Reconfigure the multicast filter.
3341 for (i = 0; i < 8; i++)
3342 ed_nic_outb(sc, ED_P1_MAR(i), 0xff);
3345 * And turn on promiscuous mode. Also enable reception of
3346 * runts and packets with CRC & alignment errors.
3348 /* Set page 0 registers */
3349 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STP);
3351 ed_nic_outb(sc, ED_P0_RCR, ED_RCR_PRO | ED_RCR_AM |
3352 ED_RCR_AB | ED_RCR_AR | ED_RCR_SEP | reg1);
3354 /* set up multicast addresses and filter modes */
3355 if (ifp->if_flags & IFF_MULTICAST) {
3358 if (ifp->if_flags & IFF_ALLMULTI) {
3359 mcaf[0] = 0xffffffff;
3360 mcaf[1] = 0xffffffff;
3362 ds_getmcaf(sc, mcaf);
3365 * Set multicast filter on chip.
3367 for (i = 0; i < 8; i++)
3368 ed_nic_outb(sc, ED_P1_MAR(i), ((u_char *) mcaf)[i]);
3370 /* Set page 0 registers */
3371 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STP);
3373 ed_nic_outb(sc, ED_P0_RCR, ED_RCR_AM | ED_RCR_AB | reg1);
3377 * Initialize multicast address hashing registers to
3378 * not accept multicasts.
3380 for (i = 0; i < 8; ++i)
3381 ed_nic_outb(sc, ED_P1_MAR(i), 0x00);
3383 /* Set page 0 registers */
3384 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STP);
3386 ed_nic_outb(sc, ED_P0_RCR, ED_RCR_AB | reg1);
3393 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STA);
3397 * Compute crc for ethernet address
3403 #define POLYNOMIAL 0x04c11db6
3404 u_int32_t crc = 0xffffffff;
3408 for (i = 6; --i >= 0;) {
3410 for (j = 8; --j >= 0;) {
3411 carry = ((crc & 0x80000000) ? 1 : 0) ^ (b & 0x01);
3415 crc = (crc ^ POLYNOMIAL) | carry;
3423 * Compute the multicast address filter from the
3424 * list of multicast addresses we need to listen to.
3427 ds_getmcaf(sc, mcaf)
3428 struct ed_softc *sc;
3432 u_char *af = (u_char *) mcaf;
3433 struct ifmultiaddr *ifma;
3438 for (ifma = sc->arpcom.ac_if.if_multiaddrs.lh_first; ifma;
3439 ifma = ifma->ifma_link.le_next) {
3440 if (ifma->ifma_addr->sa_family != AF_LINK)
3442 index = ds_crc(LLADDR((struct sockaddr_dl *)ifma->ifma_addr))
3444 af[index >> 3] |= 1 << (index & 7);