sys/dev/drm/i915/intel_dsi_panel_vbt.c

   1 /*
   2  * Copyright © 2014 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Author: Shobhit Kumar <shobhit.kumar@intel.com>
  24  *
  25  */
  26
  27 #include <drm/drmP.h>
  28 #include <drm/drm_crtc.h>
  29 #include <drm/drm_edid.h>
  30 #include <drm/i915_drm.h>
  31 #include <drm/drm_panel.h>
  32 #include <linux/slab.h>
  33 #include <video/mipi_display.h>
  34 #include <video/mipi_display.h>
  35 #include "i915_drv.h"
  36 #include "intel_drv.h"
  37 #include "intel_dsi.h"
  38
  39 struct vbt_panel {
  40         struct drm_panel panel;
  41         struct intel_dsi *intel_dsi;
  42 };
  43
  44 static inline struct vbt_panel *to_vbt_panel(struct drm_panel *panel)
  45 {
  46         return container_of(panel, struct vbt_panel, panel);
  47 }
  48
  49 #define MIPI_TRANSFER_MODE_SHIFT        0
  50 #define MIPI_VIRTUAL_CHANNEL_SHIFT      1
  51 #define MIPI_PORT_SHIFT                 3
  52
  53 #define PREPARE_CNT_MAX         0x3F
  54 #define EXIT_ZERO_CNT_MAX       0x3F
  55 #define CLK_ZERO_CNT_MAX        0xFF
  56 #define TRAIL_CNT_MAX           0x1F
  57
  58 #define NS_KHZ_RATIO 1000000
  59
  60 #define GPI0_NC_0_HV_DDI0_HPD           0x4130
  61 #define GPIO_NC_0_HV_DDI0_PAD           0x4138
  62 #define GPIO_NC_1_HV_DDI0_DDC_SDA       0x4120
  63 #define GPIO_NC_1_HV_DDI0_DDC_SDA_PAD   0x4128
  64 #define GPIO_NC_2_HV_DDI0_DDC_SCL       0x4110
  65 #define GPIO_NC_2_HV_DDI0_DDC_SCL_PAD   0x4118
  66 #define GPIO_NC_3_PANEL0_VDDEN          0x4140
  67 #define GPIO_NC_3_PANEL0_VDDEN_PAD      0x4148
  68 #define GPIO_NC_4_PANEL0_BLKEN          0x4150
  69 #define GPIO_NC_4_PANEL0_BLKEN_PAD      0x4158
  70 #define GPIO_NC_5_PANEL0_BLKCTL         0x4160
  71 #define GPIO_NC_5_PANEL0_BLKCTL_PAD     0x4168
  72 #define GPIO_NC_6_PCONF0                0x4180
  73 #define GPIO_NC_6_PAD                   0x4188
  74 #define GPIO_NC_7_PCONF0                0x4190
  75 #define GPIO_NC_7_PAD                   0x4198
  76 #define GPIO_NC_8_PCONF0                0x4170
  77 #define GPIO_NC_8_PAD                   0x4178
  78 #define GPIO_NC_9_PCONF0                0x4100
  79 #define GPIO_NC_9_PAD                   0x4108
  80 #define GPIO_NC_10_PCONF0               0x40E0
  81 #define GPIO_NC_10_PAD                  0x40E8
  82 #define GPIO_NC_11_PCONF0               0x40F0
  83 #define GPIO_NC_11_PAD                  0x40F8
  84
  85 struct gpio_table {
  86         u16 function_reg;
  87         u16 pad_reg;
  88         u8 init;
  89 };
  90
  91 static struct gpio_table gtable[] = {
  92         { GPI0_NC_0_HV_DDI0_HPD, GPIO_NC_0_HV_DDI0_PAD, 0 },
  93         { GPIO_NC_1_HV_DDI0_DDC_SDA, GPIO_NC_1_HV_DDI0_DDC_SDA_PAD, 0 },
  94         { GPIO_NC_2_HV_DDI0_DDC_SCL, GPIO_NC_2_HV_DDI0_DDC_SCL_PAD, 0 },
  95         { GPIO_NC_3_PANEL0_VDDEN, GPIO_NC_3_PANEL0_VDDEN_PAD, 0 },
  96         { GPIO_NC_4_PANEL0_BLKEN, GPIO_NC_4_PANEL0_BLKEN_PAD, 0 },
  97         { GPIO_NC_5_PANEL0_BLKCTL, GPIO_NC_5_PANEL0_BLKCTL_PAD, 0 },
  98         { GPIO_NC_6_PCONF0, GPIO_NC_6_PAD, 0 },
  99         { GPIO_NC_7_PCONF0, GPIO_NC_7_PAD, 0 },
 100         { GPIO_NC_8_PCONF0, GPIO_NC_8_PAD, 0 },
 101         { GPIO_NC_9_PCONF0, GPIO_NC_9_PAD, 0 },
 102         { GPIO_NC_10_PCONF0, GPIO_NC_10_PAD, 0},
 103         { GPIO_NC_11_PCONF0, GPIO_NC_11_PAD, 0}
 104 };
 105
 106 static inline enum port intel_dsi_seq_port_to_port(u8 port)
 107 {
 108         return port ? PORT_C : PORT_A;
 109 }
 110
 111 static const u8 *mipi_exec_send_packet(struct intel_dsi *intel_dsi,
 112                                        const u8 *data)
 113 {
 114         struct mipi_dsi_device *dsi_device;
 115         u8 type, flags, seq_port;
 116         u16 len;
 117         enum port port;
 118
 119         flags = *data++;
 120         type = *data++;
 121
 122         len = *((const u16 *) data);
 123         data += 2;
 124
 125         seq_port = (flags >> MIPI_PORT_SHIFT) & 3;
 126
 127         /* For DSI single link on Port A & C, the seq_port value which is
 128          * parsed from Sequence Block#53 of VBT has been set to 0
 129          * Now, read/write of packets for the DSI single link on Port A and
 130          * Port C will based on the DVO port from VBT block 2.
 131          */
 132         if (intel_dsi->ports == (1 << PORT_C))
 133                 port = PORT_C;
 134         else
 135                 port = intel_dsi_seq_port_to_port(seq_port);
 136
 137         dsi_device = intel_dsi->dsi_hosts[port]->device;
 138         if (!dsi_device) {
 139                 DRM_DEBUG_KMS("no dsi device for port %c\n", port_name(port));
 140                 goto out;
 141         }
 142
 143         if ((flags >> MIPI_TRANSFER_MODE_SHIFT) & 1)
 144                 dsi_device->mode_flags &= ~MIPI_DSI_MODE_LPM;
 145         else
 146                 dsi_device->mode_flags |= MIPI_DSI_MODE_LPM;
 147
 148         dsi_device->channel = (flags >> MIPI_VIRTUAL_CHANNEL_SHIFT) & 3;
 149
 150         switch (type) {
 151         case MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM:
 152                 mipi_dsi_generic_write(dsi_device, NULL, 0);
 153                 break;
 154         case MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM:
 155                 mipi_dsi_generic_write(dsi_device, data, 1);
 156                 break;
 157         case MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM:
 158                 mipi_dsi_generic_write(dsi_device, data, 2);
 159                 break;
 160         case MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM:
 161         case MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM:
 162         case MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM:
 163                 DRM_DEBUG_DRIVER("Generic Read not yet implemented or used\n");
 164                 break;
 165         case MIPI_DSI_GENERIC_LONG_WRITE:
 166                 mipi_dsi_generic_write(dsi_device, data, len);
 167                 break;
 168         case MIPI_DSI_DCS_SHORT_WRITE:
 169                 mipi_dsi_dcs_write_buffer(dsi_device, data, 1);
 170                 break;
 171         case MIPI_DSI_DCS_SHORT_WRITE_PARAM:
 172                 mipi_dsi_dcs_write_buffer(dsi_device, data, 2);
 173                 break;
 174         case MIPI_DSI_DCS_READ:
 175                 DRM_DEBUG_DRIVER("DCS Read not yet implemented or used\n");
 176                 break;
 177         case MIPI_DSI_DCS_LONG_WRITE:
 178                 mipi_dsi_dcs_write_buffer(dsi_device, data, len);
 179                 break;
 180         }
 181
 182 out:
 183         data += len;
 184
 185         return data;
 186 }
 187
 188 static const u8 *mipi_exec_delay(struct intel_dsi *intel_dsi, const u8 *data)
 189 {
 190         u32 delay = *((const u32 *) data);
 191
 192         usleep_range(delay, delay + 10);
 193         data += 4;
 194
 195         return data;
 196 }
 197
 198 static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data)
 199 {
 200         u8 gpio, action;
 201         u16 function, pad;
 202         u32 val;
 203         struct drm_device *dev = intel_dsi->base.base.dev;
 204         struct drm_i915_private *dev_priv = dev->dev_private;
 205
 206         gpio = *data++;
 207
 208         /* pull up/down */
 209         action = *data++;
 210
 211         function = gtable[gpio].function_reg;
 212         pad = gtable[gpio].pad_reg;
 213
 214         mutex_lock(&dev_priv->dpio_lock);
 215         if (!gtable[gpio].init) {
 216                 /* program the function */
 217                 /* FIXME: remove constant below */
 218                 vlv_gpio_nc_write(dev_priv, function, 0x2000CC00);
 219                 gtable[gpio].init = 1;
 220         }
 221
 222         val = 0x4 | action;
 223
 224         /* pull up/down */
 225         vlv_gpio_nc_write(dev_priv, pad, val);
 226         mutex_unlock(&dev_priv->dpio_lock);
 227
 228         return data;
 229 }
 230
 231 typedef const u8 * (*fn_mipi_elem_exec)(struct intel_dsi *intel_dsi,
 232                                         const u8 *data);
 233 static const fn_mipi_elem_exec exec_elem[] = {
 234         NULL, /* reserved */
 235         mipi_exec_send_packet,
 236         mipi_exec_delay,
 237         mipi_exec_gpio,
 238         NULL, /* status read; later */
 239 };
 240
 241 /*
 242  * MIPI Sequence from VBT #53 parsing logic
 243  * We have already separated each seqence during bios parsing
 244  * Following is generic execution function for any sequence
 245  */
 246
 247 static const char * const seq_name[] = {
 248         "UNDEFINED",
 249         "MIPI_SEQ_ASSERT_RESET",
 250         "MIPI_SEQ_INIT_OTP",
 251         "MIPI_SEQ_DISPLAY_ON",
 252         "MIPI_SEQ_DISPLAY_OFF",
 253         "MIPI_SEQ_DEASSERT_RESET"
 254 };
 255
 256 static void generic_exec_sequence(struct intel_dsi *intel_dsi, const u8 *data)
 257 {
 258         fn_mipi_elem_exec mipi_elem_exec;
 259         int index;
 260
 261         if (!data)
 262                 return;
 263
 264         DRM_DEBUG_DRIVER("Starting MIPI sequence - %s\n", seq_name[*data]);
 265
 266         /* go to the first element of the sequence */
 267         data++;
 268
 269         /* parse each byte till we reach end of sequence byte - 0x00 */
 270         while (1) {
 271                 index = *data;
 272                 mipi_elem_exec = exec_elem[index];
 273                 if (!mipi_elem_exec) {
 274                         DRM_ERROR("Unsupported MIPI element, skipping sequence execution\n");
 275                         return;
 276                 }
 277
 278                 /* goto element payload */
 279                 data++;
 280
 281                 /* execute the element specific rotines */
 282                 data = mipi_elem_exec(intel_dsi, data);
 283
 284                 /*
 285                  * After processing the element, data should point to
 286                  * next element or end of sequence
 287                  * check if have we reached end of sequence
 288                  */
 289                 if (*data == 0x00)
 290                         break;
 291         }
 292 }
 293
 294 static int vbt_panel_prepare(struct drm_panel *panel)
 295 {
 296         struct vbt_panel *vbt_panel = to_vbt_panel(panel);
 297         struct intel_dsi *intel_dsi = vbt_panel->intel_dsi;
 298         struct drm_device *dev = intel_dsi->base.base.dev;
 299         struct drm_i915_private *dev_priv = dev->dev_private;
 300         const u8 *sequence;
 301
 302         sequence = dev_priv->vbt.dsi.sequence[MIPI_SEQ_ASSERT_RESET];
 303         generic_exec_sequence(intel_dsi, sequence);
 304
 305         sequence = dev_priv->vbt.dsi.sequence[MIPI_SEQ_INIT_OTP];
 306         generic_exec_sequence(intel_dsi, sequence);
 307
 308         return 0;
 309 }
 310
 311 static int vbt_panel_unprepare(struct drm_panel *panel)
 312 {
 313         struct vbt_panel *vbt_panel = to_vbt_panel(panel);
 314         struct intel_dsi *intel_dsi = vbt_panel->intel_dsi;
 315         struct drm_device *dev = intel_dsi->base.base.dev;
 316         struct drm_i915_private *dev_priv = dev->dev_private;
 317         const u8 *sequence;
 318
 319         sequence = dev_priv->vbt.dsi.sequence[MIPI_SEQ_DEASSERT_RESET];
 320         generic_exec_sequence(intel_dsi, sequence);
 321
 322         return 0;
 323 }
 324
 325 static int vbt_panel_enable(struct drm_panel *panel)
 326 {
 327         struct vbt_panel *vbt_panel = to_vbt_panel(panel);
 328         struct intel_dsi *intel_dsi = vbt_panel->intel_dsi;
 329         struct drm_device *dev = intel_dsi->base.base.dev;
 330         struct drm_i915_private *dev_priv = dev->dev_private;
 331         const u8 *sequence;
 332
 333         sequence = dev_priv->vbt.dsi.sequence[MIPI_SEQ_DISPLAY_ON];
 334         generic_exec_sequence(intel_dsi, sequence);
 335
 336         return 0;
 337 }
 338
 339 static int vbt_panel_disable(struct drm_panel *panel)
 340 {
 341         struct vbt_panel *vbt_panel = to_vbt_panel(panel);
 342         struct intel_dsi *intel_dsi = vbt_panel->intel_dsi;
 343         struct drm_device *dev = intel_dsi->base.base.dev;
 344         struct drm_i915_private *dev_priv = dev->dev_private;
 345         const u8 *sequence;
 346
 347         sequence = dev_priv->vbt.dsi.sequence[MIPI_SEQ_DISPLAY_OFF];
 348         generic_exec_sequence(intel_dsi, sequence);
 349
 350         return 0;
 351 }
 352
 353 static int vbt_panel_get_modes(struct drm_panel *panel)
 354 {
 355         struct vbt_panel *vbt_panel = to_vbt_panel(panel);
 356         struct intel_dsi *intel_dsi = vbt_panel->intel_dsi;
 357         struct drm_device *dev = intel_dsi->base.base.dev;
 358         struct drm_i915_private *dev_priv = dev->dev_private;
 359         struct drm_display_mode *mode;
 360
 361         if (!panel->connector)
 362                 return 0;
 363
 364         mode = drm_mode_duplicate(dev, dev_priv->vbt.lfp_lvds_vbt_mode);
 365         if (!mode)
 366                 return 0;
 367
 368         mode->type |= DRM_MODE_TYPE_PREFERRED;
 369
 370         drm_mode_probed_add(panel->connector, mode);
 371
 372         return 1;
 373 }
 374
 375 static const struct drm_panel_funcs vbt_panel_funcs = {
 376         .disable = vbt_panel_disable,
 377         .unprepare = vbt_panel_unprepare,
 378         .prepare = vbt_panel_prepare,
 379         .enable = vbt_panel_enable,
 380         .get_modes = vbt_panel_get_modes,
 381 };
 382
 383 struct drm_panel *vbt_panel_init(struct intel_dsi *intel_dsi, u16 panel_id)
 384 {
 385         struct drm_device *dev = intel_dsi->base.base.dev;
 386         struct drm_i915_private *dev_priv = dev->dev_private;
 387         struct mipi_config *mipi_config = dev_priv->vbt.dsi.config;
 388         struct mipi_pps_data *pps = dev_priv->vbt.dsi.pps;
 389         struct drm_display_mode *mode = dev_priv->vbt.lfp_lvds_vbt_mode;
 390         struct vbt_panel *vbt_panel;
 391         u32 bits_per_pixel = 24;
 392         u32 tlpx_ns, extra_byte_count, bitrate, tlpx_ui;
 393         u32 ui_num, ui_den;
 394         u32 prepare_cnt, exit_zero_cnt, clk_zero_cnt, trail_cnt;
 395         u32 ths_prepare_ns, tclk_trail_ns;
 396         u32 tclk_prepare_clkzero, ths_prepare_hszero;
 397         u32 lp_to_hs_switch, hs_to_lp_switch;
 398         u32 pclk, computed_ddr;
 399         u16 burst_mode_ratio;
 400         enum port port;
 401
 402         DRM_DEBUG_KMS("\n");
 403
 404         intel_dsi->eotp_pkt = mipi_config->eot_pkt_disabled ? 0 : 1;
 405         intel_dsi->clock_stop = mipi_config->enable_clk_stop ? 1 : 0;
 406         intel_dsi->lane_count = mipi_config->lane_cnt + 1;
 407         intel_dsi->pixel_format = mipi_config->videomode_color_format << 7;
 408         intel_dsi->dual_link = mipi_config->dual_link;
 409         intel_dsi->pixel_overlap = mipi_config->pixel_overlap;
 410
 411         if (intel_dsi->pixel_format == VID_MODE_FORMAT_RGB666)
 412                 bits_per_pixel = 18;
 413         else if (intel_dsi->pixel_format == VID_MODE_FORMAT_RGB565)
 414                 bits_per_pixel = 16;
 415
 416         intel_dsi->operation_mode = mipi_config->is_cmd_mode;
 417         intel_dsi->video_mode_format = mipi_config->video_transfer_mode;
 418         intel_dsi->escape_clk_div = mipi_config->byte_clk_sel;
 419         intel_dsi->lp_rx_timeout = mipi_config->lp_rx_timeout;
 420         intel_dsi->turn_arnd_val = mipi_config->turn_around_timeout;
 421         intel_dsi->rst_timer_val = mipi_config->device_reset_timer;
 422         intel_dsi->init_count = mipi_config->master_init_timer;
 423         intel_dsi->bw_timer = mipi_config->dbi_bw_timer;
 424         intel_dsi->video_frmt_cfg_bits =
 425                 mipi_config->bta_enabled ? DISABLE_VIDEO_BTA : 0;
 426
 427         pclk = mode->clock;
 428
 429         /* In dual link mode each port needs half of pixel clock */
 430         if (intel_dsi->dual_link) {
 431                 pclk = pclk / 2;
 432
 433                 /* we can enable pixel_overlap if needed by panel. In this
 434                  * case we need to increase the pixelclock for extra pixels
 435                  */
 436                 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) {
 437                         pclk += DIV_ROUND_UP(mode->vtotal *
 438                                                 intel_dsi->pixel_overlap *
 439                                                 60, 1000);
 440                 }
 441         }
 442
 443         /* Burst Mode Ratio
 444          * Target ddr frequency from VBT / non burst ddr freq
 445          * multiply by 100 to preserve remainder
 446          */
 447         if (intel_dsi->video_mode_format == VIDEO_MODE_BURST) {
 448                 if (mipi_config->target_burst_mode_freq) {
 449                         computed_ddr =
 450                                 (pclk * bits_per_pixel) / intel_dsi->lane_count;
 451
 452                         if (mipi_config->target_burst_mode_freq <
 453                                                                 computed_ddr) {
 454                                 DRM_ERROR("Burst mode freq is less than computed\n");
 455                                 return NULL;
 456                         }
 457
 458                         burst_mode_ratio = DIV_ROUND_UP(
 459                                 mipi_config->target_burst_mode_freq * 100,
 460                                 computed_ddr);
 461
 462                         pclk = DIV_ROUND_UP(pclk * burst_mode_ratio, 100);
 463                 } else {
 464                         DRM_ERROR("Burst mode target is not set\n");
 465                         return NULL;
 466                 }
 467         } else
 468                 burst_mode_ratio = 100;
 469
 470         intel_dsi->burst_mode_ratio = burst_mode_ratio;
 471         intel_dsi->pclk = pclk;
 472
 473         bitrate = (pclk * bits_per_pixel) / intel_dsi->lane_count;
 474
 475         switch (intel_dsi->escape_clk_div) {
 476         case 0:
 477                 tlpx_ns = 50;
 478                 break;
 479         case 1:
 480                 tlpx_ns = 100;
 481                 break;
 482
 483         case 2:
 484                 tlpx_ns = 200;
 485                 break;
 486         default:
 487                 tlpx_ns = 50;
 488                 break;
 489         }
 490
 491         switch (intel_dsi->lane_count) {
 492         case 1:
 493         case 2:
 494                 extra_byte_count = 2;
 495                 break;
 496         case 3:
 497                 extra_byte_count = 4;
 498                 break;
 499         case 4:
 500         default:
 501                 extra_byte_count = 3;
 502                 break;
 503         }
 504
 505         /*
 506          * ui(s) = 1/f [f in hz]
 507          * ui(ns) = 10^9 / (f*10^6) [f in Mhz] -> 10^3/f(Mhz)
 508          */
 509
 510         /* in Kbps */
 511         ui_num = NS_KHZ_RATIO;
 512         ui_den = bitrate;
 513
 514         tclk_prepare_clkzero = mipi_config->tclk_prepare_clkzero;
 515         ths_prepare_hszero = mipi_config->ths_prepare_hszero;
 516
 517         /*
 518          * B060
 519          * LP byte clock = TLPX/ (8UI)
 520          */
 521         intel_dsi->lp_byte_clk = DIV_ROUND_UP(tlpx_ns * ui_den, 8 * ui_num);
 522
 523         /* count values in UI = (ns value) * (bitrate / (2 * 10^6))
 524          *
 525          * Since txddrclkhs_i is 2xUI, all the count values programmed in
 526          * DPHY param register are divided by 2
 527          *
 528          * prepare count
 529          */
 530         ths_prepare_ns = max(mipi_config->ths_prepare,
 531                              mipi_config->tclk_prepare);
 532         prepare_cnt = DIV_ROUND_UP(ths_prepare_ns * ui_den, ui_num * 2);
 533
 534         /* exit zero count */
 535         exit_zero_cnt = DIV_ROUND_UP(
 536                                 (ths_prepare_hszero - ths_prepare_ns) * ui_den,
 537                                 ui_num * 2
 538                                 );
 539
 540         /*
 541          * Exit zero  is unified val ths_zero and ths_exit
 542          * minimum value for ths_exit = 110ns
 543          * min (exit_zero_cnt * 2) = 110/UI
 544          * exit_zero_cnt = 55/UI
 545          */
 546          if (exit_zero_cnt < (55 * ui_den / ui_num))
 547                 if ((55 * ui_den) % ui_num)
 548                         exit_zero_cnt += 1;
 549
 550         /* clk zero count */
 551         clk_zero_cnt = DIV_ROUND_UP(
 552                         (tclk_prepare_clkzero - ths_prepare_ns)
 553                         * ui_den, 2 * ui_num);
 554
 555         /* trail count */
 556         tclk_trail_ns = max(mipi_config->tclk_trail, mipi_config->ths_trail);
 557         trail_cnt = DIV_ROUND_UP(tclk_trail_ns * ui_den, 2 * ui_num);
 558
 559         if (prepare_cnt > PREPARE_CNT_MAX ||
 560                 exit_zero_cnt > EXIT_ZERO_CNT_MAX ||
 561                 clk_zero_cnt > CLK_ZERO_CNT_MAX ||
 562                 trail_cnt > TRAIL_CNT_MAX)
 563                 DRM_DEBUG_DRIVER("Values crossing maximum limits, restricting to max values\n");
 564
 565         if (prepare_cnt > PREPARE_CNT_MAX)
 566                 prepare_cnt = PREPARE_CNT_MAX;
 567
 568         if (exit_zero_cnt > EXIT_ZERO_CNT_MAX)
 569                 exit_zero_cnt = EXIT_ZERO_CNT_MAX;
 570
 571         if (clk_zero_cnt > CLK_ZERO_CNT_MAX)
 572                 clk_zero_cnt = CLK_ZERO_CNT_MAX;
 573
 574         if (trail_cnt > TRAIL_CNT_MAX)
 575                 trail_cnt = TRAIL_CNT_MAX;
 576
 577         /* B080 */
 578         intel_dsi->dphy_reg = exit_zero_cnt << 24 | trail_cnt << 16 |
 579                                                 clk_zero_cnt << 8 | prepare_cnt;
 580
 581         /*
 582          * LP to HS switch count = 4TLPX + PREP_COUNT * 2 + EXIT_ZERO_COUNT * 2
 583          *                                      + 10UI + Extra Byte Count
 584          *
 585          * HS to LP switch count = THS-TRAIL + 2TLPX + Extra Byte Count
 586          * Extra Byte Count is calculated according to number of lanes.
 587          * High Low Switch Count is the Max of LP to HS and
 588          * HS to LP switch count
 589          *
 590          */
 591         tlpx_ui = DIV_ROUND_UP(tlpx_ns * ui_den, ui_num);
 592
 593         /* B044 */
 594         /* FIXME:
 595          * The comment above does not match with the code */
 596         lp_to_hs_switch = DIV_ROUND_UP(4 * tlpx_ui + prepare_cnt * 2 +
 597                                                 exit_zero_cnt * 2 + 10, 8);
 598
 599         hs_to_lp_switch = DIV_ROUND_UP(mipi_config->ths_trail + 2 * tlpx_ui, 8);
 600
 601         intel_dsi->hs_to_lp_count = max(lp_to_hs_switch, hs_to_lp_switch);
 602         intel_dsi->hs_to_lp_count += extra_byte_count;
 603
 604         /* B088 */
 605         /* LP -> HS for clock lanes
 606          * LP clk sync + LP11 + LP01 + tclk_prepare + tclk_zero +
 607          *                                              extra byte count
 608          * 2TPLX + 1TLPX + 1 TPLX(in ns) + prepare_cnt * 2 + clk_zero_cnt *
 609          *                                      2(in UI) + extra byte count
 610          * In byteclks = (4TLPX + prepare_cnt * 2 + clk_zero_cnt *2 (in UI)) /
 611          *                                      8 + extra byte count
 612          */
 613         intel_dsi->clk_lp_to_hs_count =
 614                 DIV_ROUND_UP(
 615                         4 * tlpx_ui + prepare_cnt * 2 +
 616                         clk_zero_cnt * 2,
 617                         8);
 618
 619         intel_dsi->clk_lp_to_hs_count += extra_byte_count;
 620
 621         /* HS->LP for Clock Lanes
 622          * Low Power clock synchronisations + 1Tx byteclk + tclk_trail +
 623          *                                              Extra byte count
 624          * 2TLPX + 8UI + (trail_count*2)(in UI) + Extra byte count
 625          * In byteclks = (2*TLpx(in UI) + trail_count*2 +8)(in UI)/8 +
 626          *                                              Extra byte count
 627          */
 628         intel_dsi->clk_hs_to_lp_count =
 629                 DIV_ROUND_UP(2 * tlpx_ui + trail_cnt * 2 + 8,
 630                         8);
 631         intel_dsi->clk_hs_to_lp_count += extra_byte_count;
 632
 633         DRM_DEBUG_KMS("Eot %s\n", intel_dsi->eotp_pkt ? "enabled" : "disabled");
 634         DRM_DEBUG_KMS("Clockstop %s\n", intel_dsi->clock_stop ?
 635                                                 "disabled" : "enabled");
 636         DRM_DEBUG_KMS("Mode %s\n", intel_dsi->operation_mode ? "command" : "video");
 637         if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK)
 638                 DRM_DEBUG_KMS("Dual link: DSI_DUAL_LINK_FRONT_BACK\n");
 639         else if (intel_dsi->dual_link == DSI_DUAL_LINK_PIXEL_ALT)
 640                 DRM_DEBUG_KMS("Dual link: DSI_DUAL_LINK_PIXEL_ALT\n");
 641         else
 642                 DRM_DEBUG_KMS("Dual link: NONE\n");
 643         DRM_DEBUG_KMS("Pixel Format %d\n", intel_dsi->pixel_format);
 644         DRM_DEBUG_KMS("TLPX %d\n", intel_dsi->escape_clk_div);
 645         DRM_DEBUG_KMS("LP RX Timeout 0x%x\n", intel_dsi->lp_rx_timeout);
 646         DRM_DEBUG_KMS("Turnaround Timeout 0x%x\n", intel_dsi->turn_arnd_val);
 647         DRM_DEBUG_KMS("Init Count 0x%x\n", intel_dsi->init_count);
 648         DRM_DEBUG_KMS("HS to LP Count 0x%x\n", intel_dsi->hs_to_lp_count);
 649         DRM_DEBUG_KMS("LP Byte Clock %d\n", intel_dsi->lp_byte_clk);
 650         DRM_DEBUG_KMS("DBI BW Timer 0x%x\n", intel_dsi->bw_timer);
 651         DRM_DEBUG_KMS("LP to HS Clock Count 0x%x\n", intel_dsi->clk_lp_to_hs_count);
 652         DRM_DEBUG_KMS("HS to LP Clock Count 0x%x\n", intel_dsi->clk_hs_to_lp_count);
 653         DRM_DEBUG_KMS("BTA %s\n",
 654                         intel_dsi->video_frmt_cfg_bits & DISABLE_VIDEO_BTA ?
 655                         "disabled" : "enabled");
 656
 657         /* delays in VBT are in unit of 100us, so need to convert
 658          * here in ms
 659          * Delay (100us) * 100 /1000 = Delay / 10 (ms) */
 660         intel_dsi->backlight_off_delay = pps->bl_disable_delay / 10;
 661         intel_dsi->backlight_on_delay = pps->bl_enable_delay / 10;
 662         intel_dsi->panel_on_delay = pps->panel_on_delay / 10;
 663         intel_dsi->panel_off_delay = pps->panel_off_delay / 10;
 664         intel_dsi->panel_pwr_cycle_delay = pps->panel_power_cycle_delay / 10;
 665
 666         /* This is cheating a bit with the cleanup. */
 667         vbt_panel = kzalloc(sizeof(*vbt_panel), GFP_KERNEL);
 668
 669         vbt_panel->intel_dsi = intel_dsi;
 670         drm_panel_init(&vbt_panel->panel);
 671         vbt_panel->panel.funcs = &vbt_panel_funcs;
 672         drm_panel_add(&vbt_panel->panel);
 673
 674         /* a regular driver would get the device in probe */
 675         for_each_dsi_port(port, intel_dsi->ports) {
 676                 mipi_dsi_attach(intel_dsi->dsi_hosts[port]->device);
 677         }
 678
 679         return &vbt_panel->panel;
 680 }