2 * Copyright (c) 1996, by Steve Passe
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. The name of the developer may NOT be used to endorse or promote products
11 * derived from this software without specific prior written permission.
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * $FreeBSD: src/sys/i386/i386/mp_machdep.c,v 1.115.2.15 2003/03/14 21:22:35 jhb Exp $
26 * $DragonFly: src/sys/platform/pc32/i386/mp_machdep.c,v 1.60 2008/06/07 12:03:52 mneumann Exp $
31 #include <sys/param.h>
32 #include <sys/systm.h>
33 #include <sys/kernel.h>
34 #include <sys/sysctl.h>
35 #include <sys/malloc.h>
36 #include <sys/memrange.h>
37 #include <sys/cons.h> /* cngetc() */
38 #include <sys/machintr.h>
41 #include <vm/vm_param.h>
43 #include <vm/vm_kern.h>
44 #include <vm/vm_extern.h>
46 #include <vm/vm_map.h>
52 #include <machine/smp.h>
53 #include <machine_base/apic/apicreg.h>
54 #include <machine/atomic.h>
55 #include <machine/cpufunc.h>
56 #include <machine_base/apic/mpapic.h>
57 #include <machine/psl.h>
58 #include <machine/segments.h>
59 #include <machine/tss.h>
60 #include <machine/specialreg.h>
61 #include <machine/globaldata.h>
63 #include <machine/md_var.h> /* setidt() */
64 #include <machine_base/icu/icu.h> /* IPIs */
65 #include <machine_base/isa/intr_machdep.h> /* IPIs */
67 #define FIXUP_EXTRA_APIC_INTS 8 /* additional entries we may create */
69 #define WARMBOOT_TARGET 0
70 #define WARMBOOT_OFF (KERNBASE + 0x0467)
71 #define WARMBOOT_SEG (KERNBASE + 0x0469)
73 #define BIOS_BASE (0xf0000)
74 #define BIOS_SIZE (0x10000)
75 #define BIOS_COUNT (BIOS_SIZE/4)
77 #define CMOS_REG (0x70)
78 #define CMOS_DATA (0x71)
79 #define BIOS_RESET (0x0f)
80 #define BIOS_WARM (0x0a)
82 #define PROCENTRY_FLAG_EN 0x01
83 #define PROCENTRY_FLAG_BP 0x02
84 #define IOAPICENTRY_FLAG_EN 0x01
87 /* MP Floating Pointer Structure */
88 typedef struct MPFPS {
101 /* MP Configuration Table Header */
102 typedef struct MPCTH {
104 u_short base_table_length;
108 u_char product_id[12];
109 void *oem_table_pointer;
110 u_short oem_table_size;
113 u_short extended_table_length;
114 u_char extended_table_checksum;
119 typedef struct PROCENTRY {
124 u_long cpu_signature;
125 u_long feature_flags;
130 typedef struct BUSENTRY {
136 typedef struct IOAPICENTRY {
142 } *io_apic_entry_ptr;
144 typedef struct INTENTRY {
154 /* descriptions of MP basetable entries */
155 typedef struct BASETABLE_ENTRY {
164 vm_size_t mp_cth_mapsz;
167 typedef int (*mptable_iter_func)(void *, const void *, int);
170 * this code MUST be enabled here and in mpboot.s.
171 * it follows the very early stages of AP boot by placing values in CMOS ram.
172 * it NORMALLY will never be needed and thus the primitive method for enabling.
175 #if defined(CHECK_POINTS)
176 #define CHECK_READ(A) (outb(CMOS_REG, (A)), inb(CMOS_DATA))
177 #define CHECK_WRITE(A,D) (outb(CMOS_REG, (A)), outb(CMOS_DATA, (D)))
179 #define CHECK_INIT(D); \
180 CHECK_WRITE(0x34, (D)); \
181 CHECK_WRITE(0x35, (D)); \
182 CHECK_WRITE(0x36, (D)); \
183 CHECK_WRITE(0x37, (D)); \
184 CHECK_WRITE(0x38, (D)); \
185 CHECK_WRITE(0x39, (D));
187 #define CHECK_PRINT(S); \
188 kprintf("%s: %d, %d, %d, %d, %d, %d\n", \
197 #else /* CHECK_POINTS */
199 #define CHECK_INIT(D)
200 #define CHECK_PRINT(S)
202 #endif /* CHECK_POINTS */
205 * Values to send to the POST hardware.
207 #define MP_BOOTADDRESS_POST 0x10
208 #define MP_PROBE_POST 0x11
209 #define MPTABLE_PASS1_POST 0x12
211 #define MP_START_POST 0x13
212 #define MP_ENABLE_POST 0x14
213 #define MPTABLE_PASS2_POST 0x15
215 #define START_ALL_APS_POST 0x16
216 #define INSTALL_AP_TRAMP_POST 0x17
217 #define START_AP_POST 0x18
219 #define MP_ANNOUNCE_POST 0x19
221 static int need_hyperthreading_fixup;
222 static u_int logical_cpus;
223 u_int logical_cpus_mask;
225 static int madt_probe_test;
226 TUNABLE_INT("hw.madt_probe_test", &madt_probe_test);
228 /** XXX FIXME: where does this really belong, isa.h/isa.c perhaps? */
229 int current_postcode;
231 /** XXX FIXME: what system files declare these??? */
232 extern struct region_descriptor r_gdt, r_idt;
234 int mp_naps; /* # of Applications processors */
236 static int mp_nbusses; /* # of busses */
237 int mp_napics; /* # of IO APICs */
239 vm_offset_t cpu_apic_address;
241 vm_offset_t io_apic_address[NAPICID]; /* NAPICID is more than enough */
242 u_int32_t *io_apic_versions;
246 u_int32_t cpu_apic_versions[MAXCPU];
248 extern int64_t tsc_offsets[];
250 extern u_long ebda_addr;
253 struct apic_intmapinfo int_to_apicintpin[APIC_INTMAPSIZE];
257 * APIC ID logical/physical mapping structures.
258 * We oversize these to simplify boot-time config.
260 int cpu_num_to_apic_id[NAPICID];
262 int io_num_to_apic_id[NAPICID];
264 int apic_id_to_logical[NAPICID];
266 /* AP uses this during bootstrap. Do not staticize. */
270 /* Hotwire a 0->4MB V==P mapping */
271 extern pt_entry_t *KPTphys;
274 * SMP page table page. Setup by locore to point to a page table
275 * page from which we allocate per-cpu privatespace areas io_apics,
279 #define IO_MAPPING_START_INDEX \
280 (SMP_MAXCPU * sizeof(struct privatespace) / PAGE_SIZE)
282 extern pt_entry_t *SMPpt;
283 static int SMPpt_alloc_index = IO_MAPPING_START_INDEX;
285 struct pcb stoppcbs[MAXCPU];
287 static basetable_entry basetable_entry_types[] =
289 {0, 20, "Processor"},
297 * Local data and functions.
300 static u_int boot_address;
301 static u_int base_memory;
302 static int mp_finish;
304 static void mp_enable(u_int boot_addr);
306 static int mptable_iterate_entries(const mpcth_t,
307 mptable_iter_func, void *);
308 static int mptable_probe(void);
309 static int mptable_check(vm_paddr_t);
310 static int mptable_search_sig(u_int32_t target, int count);
311 static void mptable_hyperthread_fixup(u_int id_mask);
312 static void mptable_pass1(struct mptable_pos *);
313 static int mptable_pass2(struct mptable_pos *);
314 static void mptable_default(int type);
315 static void mptable_fix(void);
316 static int mptable_map(struct mptable_pos *, vm_paddr_t);
317 static void mptable_unmap(struct mptable_pos *);
320 static void setup_apic_irq_mapping(void);
321 static int apic_int_is_bus_type(int intr, int bus_type);
323 static int start_all_aps(u_int boot_addr);
324 static void install_ap_tramp(u_int boot_addr);
325 static int start_ap(struct mdglobaldata *gd, u_int boot_addr);
327 static cpumask_t smp_startup_mask = 1; /* which cpus have been started */
328 cpumask_t smp_active_mask = 1; /* which cpus are ready for IPIs etc? */
329 SYSCTL_INT(_machdep, OID_AUTO, smp_active, CTLFLAG_RD, &smp_active_mask, 0, "");
332 * Calculate usable address in base memory for AP trampoline code.
335 mp_bootaddress(u_int basemem)
337 POSTCODE(MP_BOOTADDRESS_POST);
339 base_memory = basemem;
341 boot_address = base_memory & ~0xfff; /* round down to 4k boundary */
342 if ((base_memory - boot_address) < bootMP_size)
343 boot_address -= 4096; /* not enough, lower by 4k */
350 * Look for an Intel MP spec table (ie, SMP capable hardware).
359 * Make sure our SMPpt[] page table is big enough to hold all the
362 KKASSERT(IO_MAPPING_START_INDEX < NPTEPG - 2);
364 POSTCODE(MP_PROBE_POST);
366 /* see if EBDA exists */
367 if (ebda_addr != 0) {
368 /* search first 1K of EBDA */
369 target = (u_int32_t)ebda_addr;
370 if ((x = mptable_search_sig(target, 1024 / 4)) > 0)
373 /* last 1K of base memory, effective 'top of base' passed in */
374 target = (u_int32_t)(base_memory - 0x400);
375 if ((x = mptable_search_sig(target, 1024 / 4)) > 0)
379 /* search the BIOS */
380 target = (u_int32_t)BIOS_BASE;
381 if ((x = mptable_search_sig(target, BIOS_COUNT)) > 0)
388 struct mptable_check_cbarg {
394 mptable_check_callback(void *xarg, const void *pos, int type)
396 const struct PROCENTRY *ent;
397 struct mptable_check_cbarg *arg = xarg;
403 if ((ent->cpu_flags & PROCENTRY_FLAG_EN) == 0)
407 if (ent->cpu_flags & PROCENTRY_FLAG_BP) {
408 if (arg->found_bsp) {
409 kprintf("more than one BSP in base MP table\n");
418 mptable_check(vm_paddr_t mpfps_paddr)
420 struct mptable_pos mpt;
421 struct mptable_check_cbarg arg;
425 if (mpfps_paddr == 0)
428 error = mptable_map(&mpt, mpfps_paddr);
432 if (mpt.mp_fps->mpfb1 != 0)
440 if (cth->apic_address == 0)
443 bzero(&arg, sizeof(arg));
444 error = mptable_iterate_entries(cth, mptable_check_callback, &arg);
446 if (arg.cpu_count == 0) {
447 kprintf("MP table contains no processor entries\n");
449 } else if (!arg.found_bsp) {
450 kprintf("MP table does not contains BSP entry\n");
460 mptable_iterate_entries(const mpcth_t cth, mptable_iter_func func, void *arg)
462 int count, total_size;
463 const void *position;
465 KKASSERT(cth->base_table_length >= sizeof(struct MPCTH));
466 total_size = cth->base_table_length - sizeof(struct MPCTH);
467 position = (const uint8_t *)cth + sizeof(struct MPCTH);
468 count = cth->entry_count;
473 KKASSERT(total_size >= 0);
474 if (total_size == 0) {
475 kprintf("invalid base MP table, "
476 "entry count and length mismatch\n");
480 type = *(const uint8_t *)position;
482 case 0: /* processor_entry */
483 case 1: /* bus_entry */
484 case 2: /* io_apic_entry */
485 case 3: /* int_entry */
486 case 4: /* int_entry */
489 kprintf("unknown base MP table entry type %d\n", type);
493 if (total_size < basetable_entry_types[type].length) {
494 kprintf("invalid base MP table length, "
495 "does not contain all entries\n");
498 total_size -= basetable_entry_types[type].length;
500 error = func(arg, position, type);
504 position = (const uint8_t *)position +
505 basetable_entry_types[type].length;
512 * Startup the SMP processors.
517 POSTCODE(MP_START_POST);
518 mp_enable(boot_address);
523 * Print various information about the SMP system hardware and setup.
530 POSTCODE(MP_ANNOUNCE_POST);
532 kprintf("DragonFly/MP: Multiprocessor motherboard\n");
533 kprintf(" cpu0 (BSP): apic id: %2d", CPU_TO_ID(0));
534 kprintf(", version: 0x%08x", cpu_apic_versions[0]);
535 kprintf(", at 0x%08x\n", cpu_apic_address);
536 for (x = 1; x <= mp_naps; ++x) {
537 kprintf(" cpu%d (AP): apic id: %2d", x, CPU_TO_ID(x));
538 kprintf(", version: 0x%08x", cpu_apic_versions[x]);
539 kprintf(", at 0x%08x\n", cpu_apic_address);
543 for (x = 0; x < mp_napics; ++x) {
544 kprintf(" io%d (APIC): apic id: %2d", x, IO_TO_ID(x));
545 kprintf(", version: 0x%08x", io_apic_versions[x]);
546 kprintf(", at 0x%08x\n", io_apic_address[x]);
549 kprintf(" Warning: APIC I/O disabled\n");
554 * AP cpu's call this to sync up protected mode.
556 * WARNING! We must ensure that the cpu is sufficiently initialized to
557 * be able to use to the FP for our optimized bzero/bcopy code before
558 * we enter more mainstream C code.
560 * WARNING! %fs is not set up on entry. This routine sets up %fs.
566 int x, myid = bootAP;
568 struct mdglobaldata *md;
569 struct privatespace *ps;
571 ps = &CPU_prvspace[myid];
573 gdt_segs[GPRIV_SEL].ssd_base = (int)ps;
574 gdt_segs[GPROC0_SEL].ssd_base =
575 (int) &ps->mdglobaldata.gd_common_tss;
576 ps->mdglobaldata.mi.gd_prvspace = ps;
578 for (x = 0; x < NGDT; x++) {
579 ssdtosd(&gdt_segs[x], &gdt[myid * NGDT + x].sd);
582 r_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1;
583 r_gdt.rd_base = (int) &gdt[myid * NGDT];
584 lgdt(&r_gdt); /* does magic intra-segment return */
589 mdcpu->gd_currentldt = _default_ldt;
591 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL);
592 gdt[myid * NGDT + GPROC0_SEL].sd.sd_type = SDT_SYS386TSS;
594 md = mdcpu; /* loaded through %fs:0 (mdglobaldata.mi.gd_prvspace)*/
596 md->gd_common_tss.tss_esp0 = 0; /* not used until after switch */
597 md->gd_common_tss.tss_ss0 = GSEL(GDATA_SEL, SEL_KPL);
598 md->gd_common_tss.tss_ioopt = (sizeof md->gd_common_tss) << 16;
599 md->gd_tss_gdt = &gdt[myid * NGDT + GPROC0_SEL].sd;
600 md->gd_common_tssd = *md->gd_tss_gdt;
604 * Set to a known state:
605 * Set by mpboot.s: CR0_PG, CR0_PE
606 * Set by cpu_setregs: CR0_NE, CR0_MP, CR0_TS, CR0_WP, CR0_AM
609 cr0 &= ~(CR0_CD | CR0_NW | CR0_EM);
611 pmap_set_opt(); /* PSE/4MB pages, etc */
613 /* set up CPU registers and state */
616 /* set up FPU state on the AP */
617 npxinit(__INITIAL_NPXCW__);
619 /* set up SSE registers */
623 /*******************************************************************
624 * local functions and data
628 * start the SMP system
631 mp_enable(u_int boot_addr)
638 vm_paddr_t mpfps_paddr;
640 POSTCODE(MP_ENABLE_POST);
642 if (madt_probe_test) {
645 mpfps_paddr = mptable_probe();
646 if (mptable_check(mpfps_paddr))
651 struct mptable_pos mpt;
653 mptable_map(&mpt, mpfps_paddr);
656 * We can safely map physical memory into SMPpt after
657 * mptable_pass1() completes.
661 if (cpu_apic_address == 0)
662 panic("mp_enable: no local apic (mptable)!\n");
665 * Examine the MP table for needed info
667 x = mptable_pass2(&mpt);
671 /* Local apic is mapped on last page */
672 SMPpt[NPTEPG - 1] = (pt_entry_t)(PG_V | PG_RW | PG_N |
673 pmap_get_pgeflag() | (cpu_apic_address & PG_FRAME));
676 * Can't process default configs till the
677 * CPU APIC is pmapped
682 /* Post scan cleanup */
685 vm_paddr_t madt_paddr;
688 madt_paddr = madt_probe();
690 panic("mp_enable: madt_probe failed\n");
692 cpu_apic_address = madt_pass1(madt_paddr);
693 if (cpu_apic_address == 0)
694 panic("mp_enable: no local apic (madt)!\n");
696 /* Local apic is mapped on last page */
697 SMPpt[NPTEPG - 1] = (pt_entry_t)(PG_V | PG_RW | PG_N |
698 pmap_get_pgeflag() | (cpu_apic_address & PG_FRAME));
700 bsp_apic_id = (lapic.id & 0xff000000) >> 24;
701 if (madt_pass2(madt_paddr, bsp_apic_id))
702 panic("mp_enable: madt_pass2 failed\n");
707 setup_apic_irq_mapping();
709 /* fill the LOGICAL io_apic_versions table */
710 for (apic = 0; apic < mp_napics; ++apic) {
711 ux = io_apic_read(apic, IOAPIC_VER);
712 io_apic_versions[apic] = ux;
713 io_apic_set_id(apic, IO_TO_ID(apic));
716 /* program each IO APIC in the system */
717 for (apic = 0; apic < mp_napics; ++apic)
718 if (io_apic_setup(apic) < 0)
719 panic("IO APIC setup failure");
724 * These are required for SMP operation
727 /* install a 'Spurious INTerrupt' vector */
728 setidt(XSPURIOUSINT_OFFSET, Xspuriousint,
729 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
731 /* install an inter-CPU IPI for TLB invalidation */
732 setidt(XINVLTLB_OFFSET, Xinvltlb,
733 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
735 /* install an inter-CPU IPI for IPIQ messaging */
736 setidt(XIPIQ_OFFSET, Xipiq,
737 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
739 /* install a timer vector */
740 setidt(XTIMER_OFFSET, Xtimer,
741 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
743 /* install an inter-CPU IPI for CPU stop/restart */
744 setidt(XCPUSTOP_OFFSET, Xcpustop,
745 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
747 /* start each Application Processor */
748 start_all_aps(boot_addr);
753 * look for the MP spec signature
756 /* string defined by the Intel MP Spec as identifying the MP table */
757 #define MP_SIG 0x5f504d5f /* _MP_ */
758 #define NEXT(X) ((X) += 4)
760 mptable_search_sig(u_int32_t target, int count)
766 KKASSERT(target != 0);
768 map_size = count * sizeof(u_int32_t);
769 addr = pmap_mapdev((vm_paddr_t)target, map_size);
772 for (x = 0; x < count; NEXT(x)) {
773 if (addr[x] == MP_SIG) {
774 /* make array index a byte index */
775 ret = target + (x * sizeof(u_int32_t));
780 pmap_unmapdev((vm_offset_t)addr, map_size);
785 typedef struct BUSDATA {
787 enum busTypes bus_type;
790 typedef struct INTDATA {
800 typedef struct BUSTYPENAME {
805 static bus_type_name bus_type_table[] =
811 {UNKNOWN_BUSTYPE, "---"},
814 {UNKNOWN_BUSTYPE, "---"},
815 {UNKNOWN_BUSTYPE, "---"},
816 {UNKNOWN_BUSTYPE, "---"},
817 {UNKNOWN_BUSTYPE, "---"},
818 {UNKNOWN_BUSTYPE, "---"},
820 {UNKNOWN_BUSTYPE, "---"},
821 {UNKNOWN_BUSTYPE, "---"},
822 {UNKNOWN_BUSTYPE, "---"},
823 {UNKNOWN_BUSTYPE, "---"},
825 {UNKNOWN_BUSTYPE, "---"}
827 /* from MP spec v1.4, table 5-1 */
828 static int default_data[7][5] =
830 /* nbus, id0, type0, id1, type1 */
831 {1, 0, ISA, 255, 255},
832 {1, 0, EISA, 255, 255},
833 {1, 0, EISA, 255, 255},
834 {1, 0, MCA, 255, 255},
836 {2, 0, EISA, 1, PCI},
844 static bus_datum *bus_data;
846 /* the IO INT data, one entry per possible APIC INTerrupt */
847 static io_int *io_apic_ints;
852 static int processor_entry (proc_entry_ptr entry, int cpu);
854 static int bus_entry (bus_entry_ptr entry, int bus);
855 static int io_apic_entry (io_apic_entry_ptr entry, int apic);
856 static int int_entry (int_entry_ptr entry, int intr);
858 static int lookup_bus_type (char *name);
862 * 1st pass on motherboard's Intel MP specification table.
865 * cpu_apic_address (common to all CPUs)
871 * need_hyperthreading_fixup
875 mptable_pass1(struct mptable_pos *mpt)
888 POSTCODE(MPTABLE_PASS1_POST);
891 KKASSERT(fps != NULL);
894 /* clear various tables */
895 for (x = 0; x < NAPICID; ++x) {
896 io_apic_address[x] = ~0; /* IO APIC address table */
900 /* init everything to empty */
909 /* check for use of 'default' configuration */
910 if (fps->mpfb1 != 0) {
911 /* use default addresses */
912 cpu_apic_address = DEFAULT_APIC_BASE;
914 io_apic_address[0] = DEFAULT_IO_APIC_BASE;
917 /* fill in with defaults */
918 mp_naps = 2; /* includes BSP */
920 mp_nbusses = default_data[fps->mpfb1 - 1][0];
928 panic("MP Configuration Table Header MISSING!");
930 cpu_apic_address = (vm_offset_t) cth->apic_address;
932 /* walk the table, recording info of interest */
933 totalSize = cth->base_table_length - sizeof(struct MPCTH);
934 position = (u_char *) cth + sizeof(struct MPCTH);
935 count = cth->entry_count;
938 switch (type = *(u_char *) position) {
939 case 0: /* processor_entry */
940 if (((proc_entry_ptr)position)->cpu_flags
941 & PROCENTRY_FLAG_EN) {
944 ((proc_entry_ptr)position)->apic_id;
947 case 1: /* bus_entry */
952 case 2: /* io_apic_entry */
954 if (((io_apic_entry_ptr)position)->apic_flags
955 & IOAPICENTRY_FLAG_EN)
956 io_apic_address[mp_napics++] =
957 (vm_offset_t)((io_apic_entry_ptr)
958 position)->apic_address;
961 case 3: /* int_entry */
966 case 4: /* int_entry */
969 panic("mpfps Base Table HOSED!");
973 totalSize -= basetable_entry_types[type].length;
974 position = (uint8_t *)position +
975 basetable_entry_types[type].length;
979 /* qualify the numbers */
980 if (mp_naps > MAXCPU) {
981 kprintf("Warning: only using %d of %d available CPUs!\n",
986 /* See if we need to fixup HT logical CPUs. */
987 mptable_hyperthread_fixup(id_mask);
989 --mp_naps; /* subtract the BSP */
994 * 2nd pass on motherboard's Intel MP specification table.
998 * ID_TO_IO(N), phy APIC ID to log CPU/IO table
999 * CPU_TO_ID(N), logical CPU to APIC ID table
1000 * IO_TO_ID(N), logical IO to APIC ID table
1005 mptable_pass2(struct mptable_pos *mpt)
1007 struct PROCENTRY proc;
1015 int apic, bus, cpu, intr;
1018 POSTCODE(MPTABLE_PASS2_POST);
1021 KKASSERT(fps != NULL);
1023 /* Initialize fake proc entry for use with HT fixup. */
1024 bzero(&proc, sizeof(proc));
1026 proc.cpu_flags = PROCENTRY_FLAG_EN;
1029 MALLOC(io_apic_versions, u_int32_t *, sizeof(u_int32_t) * mp_napics,
1030 M_DEVBUF, M_WAITOK);
1031 MALLOC(ioapic, volatile ioapic_t **, sizeof(ioapic_t *) * mp_napics,
1032 M_DEVBUF, M_WAITOK | M_ZERO);
1033 MALLOC(io_apic_ints, io_int *, sizeof(io_int) * (nintrs + FIXUP_EXTRA_APIC_INTS),
1034 M_DEVBUF, M_WAITOK);
1035 MALLOC(bus_data, bus_datum *, sizeof(bus_datum) * mp_nbusses,
1036 M_DEVBUF, M_WAITOK);
1040 for (i = 0; i < mp_napics; i++) {
1041 ioapic[i] = permanent_io_mapping(io_apic_address[i]);
1045 /* clear various tables */
1046 for (x = 0; x < NAPICID; ++x) {
1047 CPU_TO_ID(x) = -1; /* logical CPU to APIC ID table */
1049 ID_TO_IO(x) = -1; /* phy APIC ID to log CPU/IO table */
1050 IO_TO_ID(x) = -1; /* logical IO to APIC ID table */
1055 /* clear bus data table */
1056 for (x = 0; x < mp_nbusses; ++x)
1057 bus_data[x].bus_id = 0xff;
1059 /* clear IO APIC INT table */
1060 for (x = 0; x < (nintrs + 1); ++x) {
1061 io_apic_ints[x].int_type = 0xff;
1062 io_apic_ints[x].int_vector = 0xff;
1066 /* record whether PIC or virtual-wire mode */
1067 machintr_setvar_simple(MACHINTR_VAR_IMCR_PRESENT, fps->mpfb2 & 0x80);
1069 /* check for use of 'default' configuration */
1070 if (fps->mpfb1 != 0)
1071 return fps->mpfb1; /* return default configuration type */
1075 panic("MP Configuration Table Header MISSING!");
1077 /* walk the table, recording info of interest */
1078 totalSize = cth->base_table_length - sizeof(struct MPCTH);
1079 position = (u_char *) cth + sizeof(struct MPCTH);
1080 count = cth->entry_count;
1081 apic = bus = intr = 0;
1082 cpu = 1; /* pre-count the BSP */
1085 switch (type = *(u_char *) position) {
1087 if (processor_entry(position, cpu))
1090 if (need_hyperthreading_fixup) {
1092 * Create fake mptable processor entries
1093 * and feed them to processor_entry() to
1094 * enumerate the logical CPUs.
1096 proc.apic_id = ((proc_entry_ptr)position)->apic_id;
1097 for (i = 1; i < logical_cpus; i++) {
1099 processor_entry(&proc, cpu);
1100 logical_cpus_mask |= (1 << cpu);
1107 if (bus_entry(position, bus))
1113 if (io_apic_entry(position, apic))
1119 if (int_entry(position, intr))
1124 /* int_entry(position); */
1127 panic("mpfps Base Table HOSED!");
1131 totalSize -= basetable_entry_types[type].length;
1132 position = (uint8_t *)position + basetable_entry_types[type].length;
1135 if (CPU_TO_ID(0) < 0)
1136 panic("NO BSP found!");
1138 /* report fact that its NOT a default configuration */
1143 * Check if we should perform a hyperthreading "fix-up" to
1144 * enumerate any logical CPU's that aren't already listed
1147 * XXX: We assume that all of the physical CPUs in the
1148 * system have the same number of logical CPUs.
1150 * XXX: We assume that APIC ID's are allocated such that
1151 * the APIC ID's for a physical processor are aligned
1152 * with the number of logical CPU's in the processor.
1155 mptable_hyperthread_fixup(u_int id_mask)
1157 int i, id, lcpus_max;
1159 if ((cpu_feature & CPUID_HTT) == 0)
1162 lcpus_max = (cpu_procinfo & CPUID_HTT_CORES) >> 16;
1166 if (strcmp(cpu_vendor, "GenuineIntel") == 0) {
1168 * INSTRUCTION SET REFERENCE, A-M (#253666)
1169 * Page 3-181, Table 3-20
1170 * "The nearest power-of-2 integer that is not smaller
1171 * than EBX[23:16] is the number of unique initial APIC
1172 * IDs reserved for addressing different logical
1173 * processors in a physical package."
1175 for (i = 0; ; ++i) {
1176 if ((1 << i) >= lcpus_max) {
1183 if (mp_naps == lcpus_max) {
1184 /* We have nothing to fix */
1186 } else if (mp_naps == 1) {
1187 /* XXX this may be incorrect */
1188 logical_cpus = lcpus_max;
1190 int cur, prev, dist;
1193 * Calculate the distances between two nearest
1194 * APIC IDs. If all such distances are same,
1195 * then it is the number of missing cpus that
1196 * we are going to fill later.
1198 dist = cur = prev = -1;
1199 for (id = 0; id < MAXCPU; ++id) {
1200 if ((id_mask & 1 << id) == 0)
1205 int new_dist = cur - prev;
1211 * Make sure that all distances
1212 * between two nearest APIC IDs
1215 if (dist != new_dist)
1223 /* Must be power of 2 */
1224 if (dist & (dist - 1))
1227 /* Can't exceed CPU package capacity */
1228 if (dist > lcpus_max)
1229 logical_cpus = lcpus_max;
1231 logical_cpus = dist;
1235 * For each APIC ID of a CPU that is set in the mask,
1236 * scan the other candidate APIC ID's for this
1237 * physical processor. If any of those ID's are
1238 * already in the table, then kill the fixup.
1240 for (id = 0; id < MAXCPU; id++) {
1241 if ((id_mask & 1 << id) == 0)
1243 /* First, make sure we are on a logical_cpus boundary. */
1244 if (id % logical_cpus != 0)
1246 for (i = id + 1; i < id + logical_cpus; i++)
1247 if ((id_mask & 1 << i) != 0)
1252 * Ok, the ID's checked out, so enable the fixup. We have to fixup
1253 * mp_naps right now.
1255 need_hyperthreading_fixup = 1;
1256 mp_naps *= logical_cpus;
1260 mptable_map(struct mptable_pos *mpt, vm_paddr_t mpfps_paddr)
1264 vm_size_t cth_mapsz = 0;
1266 bzero(mpt, sizeof(*mpt));
1268 fps = pmap_mapdev(mpfps_paddr, sizeof(*fps));
1269 if (fps->pap != 0) {
1271 * Map configuration table header to get
1272 * the base table size
1274 cth = pmap_mapdev(fps->pap, sizeof(*cth));
1275 cth_mapsz = cth->base_table_length;
1276 pmap_unmapdev((vm_offset_t)cth, sizeof(*cth));
1278 if (cth_mapsz < sizeof(*cth)) {
1279 kprintf("invalid base MP table length %d\n",
1281 pmap_unmapdev((vm_offset_t)fps, sizeof(*fps));
1286 * Map the base table
1288 cth = pmap_mapdev(fps->pap, cth_mapsz);
1293 mpt->mp_cth_mapsz = cth_mapsz;
1299 mptable_unmap(struct mptable_pos *mpt)
1301 if (mpt->mp_cth != NULL) {
1302 pmap_unmapdev((vm_offset_t)mpt->mp_cth, mpt->mp_cth_mapsz);
1304 mpt->mp_cth_mapsz = 0;
1306 if (mpt->mp_fps != NULL) {
1307 pmap_unmapdev((vm_offset_t)mpt->mp_fps, sizeof(*mpt->mp_fps));
1315 assign_apic_irq(int apic, int intpin, int irq)
1319 if (int_to_apicintpin[irq].ioapic != -1)
1320 panic("assign_apic_irq: inconsistent table");
1322 int_to_apicintpin[irq].ioapic = apic;
1323 int_to_apicintpin[irq].int_pin = intpin;
1324 int_to_apicintpin[irq].apic_address = ioapic[apic];
1325 int_to_apicintpin[irq].redirindex = IOAPIC_REDTBL + 2 * intpin;
1327 for (x = 0; x < nintrs; x++) {
1328 if ((io_apic_ints[x].int_type == 0 ||
1329 io_apic_ints[x].int_type == 3) &&
1330 io_apic_ints[x].int_vector == 0xff &&
1331 io_apic_ints[x].dst_apic_id == IO_TO_ID(apic) &&
1332 io_apic_ints[x].dst_apic_int == intpin)
1333 io_apic_ints[x].int_vector = irq;
1338 revoke_apic_irq(int irq)
1344 if (int_to_apicintpin[irq].ioapic == -1)
1345 panic("revoke_apic_irq: inconsistent table");
1347 oldapic = int_to_apicintpin[irq].ioapic;
1348 oldintpin = int_to_apicintpin[irq].int_pin;
1350 int_to_apicintpin[irq].ioapic = -1;
1351 int_to_apicintpin[irq].int_pin = 0;
1352 int_to_apicintpin[irq].apic_address = NULL;
1353 int_to_apicintpin[irq].redirindex = 0;
1355 for (x = 0; x < nintrs; x++) {
1356 if ((io_apic_ints[x].int_type == 0 ||
1357 io_apic_ints[x].int_type == 3) &&
1358 io_apic_ints[x].int_vector != 0xff &&
1359 io_apic_ints[x].dst_apic_id == IO_TO_ID(oldapic) &&
1360 io_apic_ints[x].dst_apic_int == oldintpin)
1361 io_apic_ints[x].int_vector = 0xff;
1369 allocate_apic_irq(int intr)
1375 if (io_apic_ints[intr].int_vector != 0xff)
1376 return; /* Interrupt handler already assigned */
1378 if (io_apic_ints[intr].int_type != 0 &&
1379 (io_apic_ints[intr].int_type != 3 ||
1380 (io_apic_ints[intr].dst_apic_id == IO_TO_ID(0) &&
1381 io_apic_ints[intr].dst_apic_int == 0)))
1382 return; /* Not INT or ExtInt on != (0, 0) */
1385 while (irq < APIC_INTMAPSIZE &&
1386 int_to_apicintpin[irq].ioapic != -1)
1389 if (irq >= APIC_INTMAPSIZE)
1390 return; /* No free interrupt handlers */
1392 apic = ID_TO_IO(io_apic_ints[intr].dst_apic_id);
1393 intpin = io_apic_ints[intr].dst_apic_int;
1395 assign_apic_irq(apic, intpin, irq);
1396 io_apic_setup_intpin(apic, intpin);
1401 swap_apic_id(int apic, int oldid, int newid)
1408 return; /* Nothing to do */
1410 kprintf("Changing APIC ID for IO APIC #%d from %d to %d in MP table\n",
1411 apic, oldid, newid);
1413 /* Swap physical APIC IDs in interrupt entries */
1414 for (x = 0; x < nintrs; x++) {
1415 if (io_apic_ints[x].dst_apic_id == oldid)
1416 io_apic_ints[x].dst_apic_id = newid;
1417 else if (io_apic_ints[x].dst_apic_id == newid)
1418 io_apic_ints[x].dst_apic_id = oldid;
1421 /* Swap physical APIC IDs in IO_TO_ID mappings */
1422 for (oapic = 0; oapic < mp_napics; oapic++)
1423 if (IO_TO_ID(oapic) == newid)
1426 if (oapic < mp_napics) {
1427 kprintf("Changing APIC ID for IO APIC #%d from "
1428 "%d to %d in MP table\n",
1429 oapic, newid, oldid);
1430 IO_TO_ID(oapic) = oldid;
1432 IO_TO_ID(apic) = newid;
1437 fix_id_to_io_mapping(void)
1441 for (x = 0; x < NAPICID; x++)
1444 for (x = 0; x <= mp_naps; x++)
1445 if (CPU_TO_ID(x) < NAPICID)
1446 ID_TO_IO(CPU_TO_ID(x)) = x;
1448 for (x = 0; x < mp_napics; x++)
1449 if (IO_TO_ID(x) < NAPICID)
1450 ID_TO_IO(IO_TO_ID(x)) = x;
1455 first_free_apic_id(void)
1459 for (freeid = 0; freeid < NAPICID; freeid++) {
1460 for (x = 0; x <= mp_naps; x++)
1461 if (CPU_TO_ID(x) == freeid)
1465 for (x = 0; x < mp_napics; x++)
1466 if (IO_TO_ID(x) == freeid)
1477 io_apic_id_acceptable(int apic, int id)
1479 int cpu; /* Logical CPU number */
1480 int oapic; /* Logical IO APIC number for other IO APIC */
1483 return 0; /* Out of range */
1485 for (cpu = 0; cpu <= mp_naps; cpu++)
1486 if (CPU_TO_ID(cpu) == id)
1487 return 0; /* Conflict with CPU */
1489 for (oapic = 0; oapic < mp_napics && oapic < apic; oapic++)
1490 if (IO_TO_ID(oapic) == id)
1491 return 0; /* Conflict with other APIC */
1493 return 1; /* ID is acceptable for IO APIC */
1498 io_apic_find_int_entry(int apic, int pin)
1502 /* search each of the possible INTerrupt sources */
1503 for (x = 0; x < nintrs; ++x) {
1504 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1505 (pin == io_apic_ints[x].dst_apic_int))
1506 return (&io_apic_ints[x]);
1514 * parse an Intel MP specification table
1522 int apic; /* IO APIC unit number */
1523 int freeid; /* Free physical APIC ID */
1524 int physid; /* Current physical IO APIC ID */
1526 int bus_0 = 0; /* Stop GCC warning */
1527 int bus_pci = 0; /* Stop GCC warning */
1531 * Fix mis-numbering of the PCI bus and its INT entries if the BIOS
1532 * did it wrong. The MP spec says that when more than 1 PCI bus
1533 * exists the BIOS must begin with bus entries for the PCI bus and use
1534 * actual PCI bus numbering. This implies that when only 1 PCI bus
1535 * exists the BIOS can choose to ignore this ordering, and indeed many
1536 * MP motherboards do ignore it. This causes a problem when the PCI
1537 * sub-system makes requests of the MP sub-system based on PCI bus
1538 * numbers. So here we look for the situation and renumber the
1539 * busses and associated INTs in an effort to "make it right".
1542 /* find bus 0, PCI bus, count the number of PCI busses */
1543 for (num_pci_bus = 0, x = 0; x < mp_nbusses; ++x) {
1544 if (bus_data[x].bus_id == 0) {
1547 if (bus_data[x].bus_type == PCI) {
1553 * bus_0 == slot of bus with ID of 0
1554 * bus_pci == slot of last PCI bus encountered
1557 /* check the 1 PCI bus case for sanity */
1558 /* if it is number 0 all is well */
1559 if (num_pci_bus == 1 &&
1560 bus_data[bus_pci].bus_id != 0) {
1562 /* mis-numbered, swap with whichever bus uses slot 0 */
1564 /* swap the bus entry types */
1565 bus_data[bus_pci].bus_type = bus_data[bus_0].bus_type;
1566 bus_data[bus_0].bus_type = PCI;
1568 /* swap each relavant INTerrupt entry */
1569 id = bus_data[bus_pci].bus_id;
1570 for (x = 0; x < nintrs; ++x) {
1571 if (io_apic_ints[x].src_bus_id == id) {
1572 io_apic_ints[x].src_bus_id = 0;
1574 else if (io_apic_ints[x].src_bus_id == 0) {
1575 io_apic_ints[x].src_bus_id = id;
1580 /* Assign IO APIC IDs.
1582 * First try the existing ID. If a conflict is detected, try
1583 * the ID in the MP table. If a conflict is still detected, find
1586 * We cannot use the ID_TO_IO table before all conflicts has been
1587 * resolved and the table has been corrected.
1589 for (apic = 0; apic < mp_napics; ++apic) { /* For all IO APICs */
1591 /* First try to use the value set by the BIOS */
1592 physid = io_apic_get_id(apic);
1593 if (io_apic_id_acceptable(apic, physid)) {
1594 if (IO_TO_ID(apic) != physid)
1595 swap_apic_id(apic, IO_TO_ID(apic), physid);
1599 /* Then check if the value in the MP table is acceptable */
1600 if (io_apic_id_acceptable(apic, IO_TO_ID(apic)))
1603 /* Last resort, find a free APIC ID and use it */
1604 freeid = first_free_apic_id();
1605 if (freeid >= NAPICID)
1606 panic("No free physical APIC IDs found");
1608 if (io_apic_id_acceptable(apic, freeid)) {
1609 swap_apic_id(apic, IO_TO_ID(apic), freeid);
1612 panic("Free physical APIC ID not usable");
1614 fix_id_to_io_mapping();
1616 /* detect and fix broken Compaq MP table */
1617 if (apic_int_type(0, 0) == -1) {
1618 kprintf("APIC_IO: MP table broken: 8259->APIC entry missing!\n");
1619 io_apic_ints[nintrs].int_type = 3; /* ExtInt */
1620 io_apic_ints[nintrs].int_vector = 0xff; /* Unassigned */
1621 /* XXX fixme, set src bus id etc, but it doesn't seem to hurt */
1622 io_apic_ints[nintrs].dst_apic_id = IO_TO_ID(0);
1623 io_apic_ints[nintrs].dst_apic_int = 0; /* Pin 0 */
1625 } else if (apic_int_type(0, 0) == 0) {
1626 kprintf("APIC_IO: MP table broken: ExtINT entry corrupt!\n");
1627 for (x = 0; x < nintrs; ++x)
1628 if ((0 == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1629 (0 == io_apic_ints[x].dst_apic_int)) {
1630 io_apic_ints[x].int_type = 3;
1631 io_apic_ints[x].int_vector = 0xff;
1637 * Fix missing IRQ 15 when IRQ 14 is an ISA interrupt. IDE
1638 * controllers universally come in pairs. If IRQ 14 is specified
1639 * as an ISA interrupt, then IRQ 15 had better be too.
1641 * [ Shuttle XPC / AMD Athlon X2 ]
1642 * The MPTable is missing an entry for IRQ 15. Note that the
1643 * ACPI table has an entry for both 14 and 15.
1645 if (apic_int_type(0, 14) == 0 && apic_int_type(0, 15) == -1) {
1646 kprintf("APIC_IO: MP table broken: IRQ 15 not ISA when IRQ 14 is!\n");
1647 io14 = io_apic_find_int_entry(0, 14);
1648 io_apic_ints[nintrs] = *io14;
1649 io_apic_ints[nintrs].src_bus_irq = 15;
1650 io_apic_ints[nintrs].dst_apic_int = 15;
1658 /* Assign low level interrupt handlers */
1660 setup_apic_irq_mapping(void)
1666 for (x = 0; x < APIC_INTMAPSIZE; x++) {
1667 int_to_apicintpin[x].ioapic = -1;
1668 int_to_apicintpin[x].int_pin = 0;
1669 int_to_apicintpin[x].apic_address = NULL;
1670 int_to_apicintpin[x].redirindex = 0;
1673 /* First assign ISA/EISA interrupts */
1674 for (x = 0; x < nintrs; x++) {
1675 int_vector = io_apic_ints[x].src_bus_irq;
1676 if (int_vector < APIC_INTMAPSIZE &&
1677 io_apic_ints[x].int_vector == 0xff &&
1678 int_to_apicintpin[int_vector].ioapic == -1 &&
1679 (apic_int_is_bus_type(x, ISA) ||
1680 apic_int_is_bus_type(x, EISA)) &&
1681 io_apic_ints[x].int_type == 0) {
1682 assign_apic_irq(ID_TO_IO(io_apic_ints[x].dst_apic_id),
1683 io_apic_ints[x].dst_apic_int,
1688 /* Assign ExtInt entry if no ISA/EISA interrupt 0 entry */
1689 for (x = 0; x < nintrs; x++) {
1690 if (io_apic_ints[x].dst_apic_int == 0 &&
1691 io_apic_ints[x].dst_apic_id == IO_TO_ID(0) &&
1692 io_apic_ints[x].int_vector == 0xff &&
1693 int_to_apicintpin[0].ioapic == -1 &&
1694 io_apic_ints[x].int_type == 3) {
1695 assign_apic_irq(0, 0, 0);
1699 /* PCI interrupt assignment is deferred */
1705 mp_set_cpuids(int cpu_id, int apic_id)
1707 CPU_TO_ID(cpu_id) = apic_id;
1708 ID_TO_CPU(apic_id) = cpu_id;
1712 processor_entry(proc_entry_ptr entry, int cpu)
1716 /* check for usability */
1717 if (!(entry->cpu_flags & PROCENTRY_FLAG_EN))
1720 if(entry->apic_id >= NAPICID)
1721 panic("CPU APIC ID out of range (0..%d)", NAPICID - 1);
1722 /* check for BSP flag */
1723 if (entry->cpu_flags & PROCENTRY_FLAG_BP) {
1724 mp_set_cpuids(0, entry->apic_id);
1725 return 0; /* its already been counted */
1728 /* add another AP to list, if less than max number of CPUs */
1729 else if (cpu < MAXCPU) {
1730 mp_set_cpuids(cpu, entry->apic_id);
1740 bus_entry(bus_entry_ptr entry, int bus)
1745 /* encode the name into an index */
1746 for (x = 0; x < 6; ++x) {
1747 if ((c = entry->bus_type[x]) == ' ')
1753 if ((x = lookup_bus_type(name)) == UNKNOWN_BUSTYPE)
1754 panic("unknown bus type: '%s'", name);
1756 bus_data[bus].bus_id = entry->bus_id;
1757 bus_data[bus].bus_type = x;
1763 io_apic_entry(io_apic_entry_ptr entry, int apic)
1765 if (!(entry->apic_flags & IOAPICENTRY_FLAG_EN))
1768 IO_TO_ID(apic) = entry->apic_id;
1769 if (entry->apic_id < NAPICID)
1770 ID_TO_IO(entry->apic_id) = apic;
1778 lookup_bus_type(char *name)
1782 for (x = 0; x < MAX_BUSTYPE; ++x)
1783 if (strcmp(bus_type_table[x].name, name) == 0)
1784 return bus_type_table[x].type;
1786 return UNKNOWN_BUSTYPE;
1792 int_entry(int_entry_ptr entry, int intr)
1796 io_apic_ints[intr].int_type = entry->int_type;
1797 io_apic_ints[intr].int_flags = entry->int_flags;
1798 io_apic_ints[intr].src_bus_id = entry->src_bus_id;
1799 io_apic_ints[intr].src_bus_irq = entry->src_bus_irq;
1800 if (entry->dst_apic_id == 255) {
1801 /* This signal goes to all IO APICS. Select an IO APIC
1802 with sufficient number of interrupt pins */
1803 for (apic = 0; apic < mp_napics; apic++)
1804 if (((io_apic_read(apic, IOAPIC_VER) &
1805 IOART_VER_MAXREDIR) >> MAXREDIRSHIFT) >=
1806 entry->dst_apic_int)
1808 if (apic < mp_napics)
1809 io_apic_ints[intr].dst_apic_id = IO_TO_ID(apic);
1811 io_apic_ints[intr].dst_apic_id = entry->dst_apic_id;
1813 io_apic_ints[intr].dst_apic_id = entry->dst_apic_id;
1814 io_apic_ints[intr].dst_apic_int = entry->dst_apic_int;
1820 apic_int_is_bus_type(int intr, int bus_type)
1824 for (bus = 0; bus < mp_nbusses; ++bus)
1825 if ((bus_data[bus].bus_id == io_apic_ints[intr].src_bus_id)
1826 && ((int) bus_data[bus].bus_type == bus_type))
1833 * Given a traditional ISA INT mask, return an APIC mask.
1836 isa_apic_mask(u_int isa_mask)
1841 #if defined(SKIP_IRQ15_REDIRECT)
1842 if (isa_mask == (1 << 15)) {
1843 kprintf("skipping ISA IRQ15 redirect\n");
1846 #endif /* SKIP_IRQ15_REDIRECT */
1848 isa_irq = ffs(isa_mask); /* find its bit position */
1849 if (isa_irq == 0) /* doesn't exist */
1851 --isa_irq; /* make it zero based */
1853 apic_pin = isa_apic_irq(isa_irq); /* look for APIC connection */
1857 return (1 << apic_pin); /* convert pin# to a mask */
1861 * Determine which APIC pin an ISA/EISA INT is attached to.
1863 #define INTTYPE(I) (io_apic_ints[(I)].int_type)
1864 #define INTPIN(I) (io_apic_ints[(I)].dst_apic_int)
1865 #define INTIRQ(I) (io_apic_ints[(I)].int_vector)
1866 #define INTAPIC(I) (ID_TO_IO(io_apic_ints[(I)].dst_apic_id))
1868 #define SRCBUSIRQ(I) (io_apic_ints[(I)].src_bus_irq)
1870 isa_apic_irq(int isa_irq)
1874 for (intr = 0; intr < nintrs; ++intr) { /* check each record */
1875 if (INTTYPE(intr) == 0) { /* standard INT */
1876 if (SRCBUSIRQ(intr) == isa_irq) {
1877 if (apic_int_is_bus_type(intr, ISA) ||
1878 apic_int_is_bus_type(intr, EISA)) {
1879 if (INTIRQ(intr) == 0xff)
1880 return -1; /* unassigned */
1881 return INTIRQ(intr); /* found */
1886 return -1; /* NOT found */
1891 * Determine which APIC pin a PCI INT is attached to.
1893 #define SRCBUSID(I) (io_apic_ints[(I)].src_bus_id)
1894 #define SRCBUSDEVICE(I) ((io_apic_ints[(I)].src_bus_irq >> 2) & 0x1f)
1895 #define SRCBUSLINE(I) (io_apic_ints[(I)].src_bus_irq & 0x03)
1897 pci_apic_irq(int pciBus, int pciDevice, int pciInt)
1901 --pciInt; /* zero based */
1903 for (intr = 0; intr < nintrs; ++intr) { /* check each record */
1904 if ((INTTYPE(intr) == 0) /* standard INT */
1905 && (SRCBUSID(intr) == pciBus)
1906 && (SRCBUSDEVICE(intr) == pciDevice)
1907 && (SRCBUSLINE(intr) == pciInt)) { /* a candidate IRQ */
1908 if (apic_int_is_bus_type(intr, PCI)) {
1909 if (INTIRQ(intr) == 0xff)
1910 allocate_apic_irq(intr);
1911 if (INTIRQ(intr) == 0xff)
1912 return -1; /* unassigned */
1913 return INTIRQ(intr); /* exact match */
1918 return -1; /* NOT found */
1922 next_apic_irq(int irq)
1929 for (intr = 0; intr < nintrs; intr++) {
1930 if (INTIRQ(intr) != irq || INTTYPE(intr) != 0)
1932 bus = SRCBUSID(intr);
1933 bustype = apic_bus_type(bus);
1934 if (bustype != ISA &&
1940 if (intr >= nintrs) {
1943 for (ointr = intr + 1; ointr < nintrs; ointr++) {
1944 if (INTTYPE(ointr) != 0)
1946 if (bus != SRCBUSID(ointr))
1948 if (bustype == PCI) {
1949 if (SRCBUSDEVICE(intr) != SRCBUSDEVICE(ointr))
1951 if (SRCBUSLINE(intr) != SRCBUSLINE(ointr))
1954 if (bustype == ISA || bustype == EISA) {
1955 if (SRCBUSIRQ(intr) != SRCBUSIRQ(ointr))
1958 if (INTPIN(intr) == INTPIN(ointr))
1962 if (ointr >= nintrs) {
1965 return INTIRQ(ointr);
1980 * Reprogram the MB chipset to NOT redirect an ISA INTerrupt.
1983 * Exactly what this means is unclear at this point. It is a solution
1984 * for motherboards that redirect the MBIRQ0 pin. Generically a motherboard
1985 * could route any of the ISA INTs to upper (>15) IRQ values. But most would
1986 * NOT be redirected via MBIRQ0, thus "undirect()ing" them would NOT be an
1990 undirect_isa_irq(int rirq)
1994 kprintf("Freeing redirected ISA irq %d.\n", rirq);
1995 /** FIXME: tickle the MB redirector chip */
1999 kprintf("Freeing (NOT implemented) redirected ISA irq %d.\n", rirq);
2006 * Reprogram the MB chipset to NOT redirect a PCI INTerrupt
2009 undirect_pci_irq(int rirq)
2013 kprintf("Freeing redirected PCI irq %d.\n", rirq);
2015 /** FIXME: tickle the MB redirector chip */
2019 kprintf("Freeing (NOT implemented) redirected PCI irq %d.\n",
2029 * given a bus ID, return:
2030 * the bus type if found
2034 apic_bus_type(int id)
2038 for (x = 0; x < mp_nbusses; ++x)
2039 if (bus_data[x].bus_id == id)
2040 return bus_data[x].bus_type;
2046 * given a LOGICAL APIC# and pin#, return:
2047 * the associated src bus ID if found
2051 apic_src_bus_id(int apic, int pin)
2055 /* search each of the possible INTerrupt sources */
2056 for (x = 0; x < nintrs; ++x)
2057 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
2058 (pin == io_apic_ints[x].dst_apic_int))
2059 return (io_apic_ints[x].src_bus_id);
2061 return -1; /* NOT found */
2065 * given a LOGICAL APIC# and pin#, return:
2066 * the associated src bus IRQ if found
2070 apic_src_bus_irq(int apic, int pin)
2074 for (x = 0; x < nintrs; x++)
2075 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
2076 (pin == io_apic_ints[x].dst_apic_int))
2077 return (io_apic_ints[x].src_bus_irq);
2079 return -1; /* NOT found */
2084 * given a LOGICAL APIC# and pin#, return:
2085 * the associated INTerrupt type if found
2089 apic_int_type(int apic, int pin)
2093 /* search each of the possible INTerrupt sources */
2094 for (x = 0; x < nintrs; ++x) {
2095 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
2096 (pin == io_apic_ints[x].dst_apic_int))
2097 return (io_apic_ints[x].int_type);
2099 return -1; /* NOT found */
2103 * Return the IRQ associated with an APIC pin
2106 apic_irq(int apic, int pin)
2111 for (x = 0; x < nintrs; ++x) {
2112 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
2113 (pin == io_apic_ints[x].dst_apic_int)) {
2114 res = io_apic_ints[x].int_vector;
2117 if (apic != int_to_apicintpin[res].ioapic)
2118 panic("apic_irq: inconsistent table %d/%d", apic, int_to_apicintpin[res].ioapic);
2119 if (pin != int_to_apicintpin[res].int_pin)
2120 panic("apic_irq inconsistent table (2)");
2129 * given a LOGICAL APIC# and pin#, return:
2130 * the associated trigger mode if found
2134 apic_trigger(int apic, int pin)
2138 /* search each of the possible INTerrupt sources */
2139 for (x = 0; x < nintrs; ++x)
2140 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
2141 (pin == io_apic_ints[x].dst_apic_int))
2142 return ((io_apic_ints[x].int_flags >> 2) & 0x03);
2144 return -1; /* NOT found */
2149 * given a LOGICAL APIC# and pin#, return:
2150 * the associated 'active' level if found
2154 apic_polarity(int apic, int pin)
2158 /* search each of the possible INTerrupt sources */
2159 for (x = 0; x < nintrs; ++x)
2160 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
2161 (pin == io_apic_ints[x].dst_apic_int))
2162 return (io_apic_ints[x].int_flags & 0x03);
2164 return -1; /* NOT found */
2170 * set data according to MP defaults
2171 * FIXME: probably not complete yet...
2174 mptable_default(int type)
2176 int ap_cpu_id, boot_cpu_id;
2177 #if defined(APIC_IO)
2180 #endif /* APIC_IO */
2183 kprintf(" MP default config type: %d\n", type);
2186 kprintf(" bus: ISA, APIC: 82489DX\n");
2189 kprintf(" bus: EISA, APIC: 82489DX\n");
2192 kprintf(" bus: EISA, APIC: 82489DX\n");
2195 kprintf(" bus: MCA, APIC: 82489DX\n");
2198 kprintf(" bus: ISA+PCI, APIC: Integrated\n");
2201 kprintf(" bus: EISA+PCI, APIC: Integrated\n");
2204 kprintf(" bus: MCA+PCI, APIC: Integrated\n");
2207 kprintf(" future type\n");
2213 boot_cpu_id = (lapic.id & APIC_ID_MASK) >> 24;
2214 ap_cpu_id = (boot_cpu_id == 0) ? 1 : 0;
2217 CPU_TO_ID(0) = boot_cpu_id;
2218 ID_TO_CPU(boot_cpu_id) = 0;
2220 /* one and only AP */
2221 CPU_TO_ID(1) = ap_cpu_id;
2222 ID_TO_CPU(ap_cpu_id) = 1;
2224 #if defined(APIC_IO)
2225 /* one and only IO APIC */
2226 io_apic_id = (io_apic_read(0, IOAPIC_ID) & APIC_ID_MASK) >> 24;
2229 * sanity check, refer to MP spec section 3.6.6, last paragraph
2230 * necessary as some hardware isn't properly setting up the IO APIC
2232 #if defined(REALLY_ANAL_IOAPICID_VALUE)
2233 if (io_apic_id != 2) {
2235 if ((io_apic_id == 0) || (io_apic_id == 1) || (io_apic_id == 15)) {
2236 #endif /* REALLY_ANAL_IOAPICID_VALUE */
2237 io_apic_set_id(0, 2);
2240 IO_TO_ID(0) = io_apic_id;
2241 ID_TO_IO(io_apic_id) = 0;
2242 #endif /* APIC_IO */
2244 /* fill out bus entries */
2254 bus_data[0].bus_id = default_data[type - 1][1];
2255 bus_data[0].bus_type = default_data[type - 1][2];
2256 bus_data[1].bus_id = default_data[type - 1][3];
2257 bus_data[1].bus_type = default_data[type - 1][4];
2261 /* case 4: case 7: MCA NOT supported */
2262 default: /* illegal/reserved */
2263 panic("BAD default MP config: %d", type);
2267 #if defined(APIC_IO)
2268 /* general cases from MP v1.4, table 5-2 */
2269 for (pin = 0; pin < 16; ++pin) {
2270 io_apic_ints[pin].int_type = 0;
2271 io_apic_ints[pin].int_flags = 0x05; /* edge/active-hi */
2272 io_apic_ints[pin].src_bus_id = 0;
2273 io_apic_ints[pin].src_bus_irq = pin; /* IRQ2 caught below */
2274 io_apic_ints[pin].dst_apic_id = io_apic_id;
2275 io_apic_ints[pin].dst_apic_int = pin; /* 1-to-1 */
2278 /* special cases from MP v1.4, table 5-2 */
2280 io_apic_ints[2].int_type = 0xff; /* N/C */
2281 io_apic_ints[13].int_type = 0xff; /* N/C */
2282 #if !defined(APIC_MIXED_MODE)
2284 panic("sorry, can't support type 2 default yet");
2285 #endif /* APIC_MIXED_MODE */
2288 io_apic_ints[2].src_bus_irq = 0; /* ISA IRQ0 is on APIC INT 2 */
2291 io_apic_ints[0].int_type = 0xff; /* N/C */
2293 io_apic_ints[0].int_type = 3; /* vectored 8259 */
2294 #endif /* APIC_IO */
2298 * Map a physical memory address representing I/O into KVA. The I/O
2299 * block is assumed not to cross a page boundary.
2302 permanent_io_mapping(vm_paddr_t pa)
2308 KKASSERT(pa < 0x100000000LL);
2310 pgeflag = 0; /* not used for SMP yet */
2313 * If the requested physical address has already been incidently
2314 * mapped, just use the existing mapping. Otherwise create a new
2317 for (i = IO_MAPPING_START_INDEX; i < SMPpt_alloc_index; ++i) {
2318 if (((vm_offset_t)SMPpt[i] & PG_FRAME) ==
2319 ((vm_offset_t)pa & PG_FRAME)) {
2323 if (i == SMPpt_alloc_index) {
2324 if (i == NPTEPG - 2) {
2325 panic("permanent_io_mapping: We ran out of space"
2328 SMPpt[i] = (pt_entry_t)(PG_V | PG_RW | pgeflag |
2329 ((vm_offset_t)pa & PG_FRAME));
2330 ++SMPpt_alloc_index;
2332 vaddr = (vm_offset_t)CPU_prvspace + (i * PAGE_SIZE) +
2333 ((vm_offset_t)pa & PAGE_MASK);
2334 return ((void *)vaddr);
2338 * start each AP in our list
2341 start_all_aps(u_int boot_addr)
2345 u_char mpbiosreason;
2346 u_long mpbioswarmvec;
2347 struct mdglobaldata *gd;
2348 struct privatespace *ps;
2352 POSTCODE(START_ALL_APS_POST);
2354 /* Initialize BSP's local APIC */
2355 apic_initialize(TRUE);
2357 /* install the AP 1st level boot code */
2358 install_ap_tramp(boot_addr);
2361 /* save the current value of the warm-start vector */
2362 mpbioswarmvec = *((u_long *) WARMBOOT_OFF);
2363 outb(CMOS_REG, BIOS_RESET);
2364 mpbiosreason = inb(CMOS_DATA);
2366 /* set up temporary P==V mapping for AP boot */
2367 /* XXX this is a hack, we should boot the AP on its own stack/PTD */
2368 kptbase = (uintptr_t)(void *)KPTphys;
2369 for (x = 0; x < NKPT; x++) {
2370 PTD[x] = (pd_entry_t)(PG_V | PG_RW |
2371 ((kptbase + x * PAGE_SIZE) & PG_FRAME));
2376 for (x = 1; x <= mp_naps; ++x) {
2378 /* This is a bit verbose, it will go away soon. */
2380 /* first page of AP's private space */
2381 pg = x * i386_btop(sizeof(struct privatespace));
2383 /* allocate new private data page(s) */
2384 gd = (struct mdglobaldata *)kmem_alloc(&kernel_map,
2385 MDGLOBALDATA_BASEALLOC_SIZE);
2386 /* wire it into the private page table page */
2387 for (i = 0; i < MDGLOBALDATA_BASEALLOC_SIZE; i += PAGE_SIZE) {
2388 SMPpt[pg + i / PAGE_SIZE] = (pt_entry_t)
2389 (PG_V | PG_RW | vtophys_pte((char *)gd + i));
2391 pg += MDGLOBALDATA_BASEALLOC_PAGES;
2393 SMPpt[pg + 0] = 0; /* *gd_CMAP1 */
2394 SMPpt[pg + 1] = 0; /* *gd_CMAP2 */
2395 SMPpt[pg + 2] = 0; /* *gd_CMAP3 */
2396 SMPpt[pg + 3] = 0; /* *gd_PMAP1 */
2398 /* allocate and set up an idle stack data page */
2399 stack = (char *)kmem_alloc(&kernel_map, UPAGES*PAGE_SIZE);
2400 for (i = 0; i < UPAGES; i++) {
2401 SMPpt[pg + 4 + i] = (pt_entry_t)
2402 (PG_V | PG_RW | vtophys_pte(PAGE_SIZE * i + stack));
2405 gd = &CPU_prvspace[x].mdglobaldata; /* official location */
2406 bzero(gd, sizeof(*gd));
2407 gd->mi.gd_prvspace = ps = &CPU_prvspace[x];
2409 /* prime data page for it to use */
2410 mi_gdinit(&gd->mi, x);
2412 gd->gd_CMAP1 = &SMPpt[pg + 0];
2413 gd->gd_CMAP2 = &SMPpt[pg + 1];
2414 gd->gd_CMAP3 = &SMPpt[pg + 2];
2415 gd->gd_PMAP1 = &SMPpt[pg + 3];
2416 gd->gd_CADDR1 = ps->CPAGE1;
2417 gd->gd_CADDR2 = ps->CPAGE2;
2418 gd->gd_CADDR3 = ps->CPAGE3;
2419 gd->gd_PADDR1 = (unsigned *)ps->PPAGE1;
2420 gd->mi.gd_ipiq = (void *)kmem_alloc(&kernel_map, sizeof(lwkt_ipiq) * (mp_naps + 1));
2421 bzero(gd->mi.gd_ipiq, sizeof(lwkt_ipiq) * (mp_naps + 1));
2423 /* setup a vector to our boot code */
2424 *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET;
2425 *((volatile u_short *) WARMBOOT_SEG) = (boot_addr >> 4);
2426 outb(CMOS_REG, BIOS_RESET);
2427 outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */
2430 * Setup the AP boot stack
2432 bootSTK = &ps->idlestack[UPAGES*PAGE_SIZE/2];
2435 /* attempt to start the Application Processor */
2436 CHECK_INIT(99); /* setup checkpoints */
2437 if (!start_ap(gd, boot_addr)) {
2438 kprintf("AP #%d (PHY# %d) failed!\n", x, CPU_TO_ID(x));
2439 CHECK_PRINT("trace"); /* show checkpoints */
2440 /* better panic as the AP may be running loose */
2441 kprintf("panic y/n? [y] ");
2442 if (cngetc() != 'n')
2445 CHECK_PRINT("trace"); /* show checkpoints */
2447 /* record its version info */
2448 cpu_apic_versions[x] = cpu_apic_versions[0];
2451 /* set ncpus to 1 + highest logical cpu. Not all may have come up */
2454 /* ncpus2 -- ncpus rounded down to the nearest power of 2 */
2455 for (shift = 0; (1 << shift) <= ncpus; ++shift)
2458 ncpus2_shift = shift;
2459 ncpus2 = 1 << shift;
2460 ncpus2_mask = ncpus2 - 1;
2462 /* ncpus_fit -- ncpus rounded up to the nearest power of 2 */
2463 if ((1 << shift) < ncpus)
2465 ncpus_fit = 1 << shift;
2466 ncpus_fit_mask = ncpus_fit - 1;
2468 /* build our map of 'other' CPUs */
2469 mycpu->gd_other_cpus = smp_startup_mask & ~(1 << mycpu->gd_cpuid);
2470 mycpu->gd_ipiq = (void *)kmem_alloc(&kernel_map, sizeof(lwkt_ipiq) * ncpus);
2471 bzero(mycpu->gd_ipiq, sizeof(lwkt_ipiq) * ncpus);
2473 /* fill in our (BSP) APIC version */
2474 cpu_apic_versions[0] = lapic.version;
2476 /* restore the warmstart vector */
2477 *(u_long *) WARMBOOT_OFF = mpbioswarmvec;
2478 outb(CMOS_REG, BIOS_RESET);
2479 outb(CMOS_DATA, mpbiosreason);
2482 * NOTE! The idlestack for the BSP was setup by locore. Finish
2483 * up, clean out the P==V mapping we did earlier.
2485 for (x = 0; x < NKPT; x++)
2489 /* number of APs actually started */
2495 * load the 1st level AP boot code into base memory.
2498 /* targets for relocation */
2499 extern void bigJump(void);
2500 extern void bootCodeSeg(void);
2501 extern void bootDataSeg(void);
2502 extern void MPentry(void);
2503 extern u_int MP_GDT;
2504 extern u_int mp_gdtbase;
2507 install_ap_tramp(u_int boot_addr)
2510 int size = *(int *) ((u_long) & bootMP_size);
2511 u_char *src = (u_char *) ((u_long) bootMP);
2512 u_char *dst = (u_char *) boot_addr + KERNBASE;
2513 u_int boot_base = (u_int) bootMP;
2518 POSTCODE(INSTALL_AP_TRAMP_POST);
2520 for (x = 0; x < size; ++x)
2524 * modify addresses in code we just moved to basemem. unfortunately we
2525 * need fairly detailed info about mpboot.s for this to work. changes
2526 * to mpboot.s might require changes here.
2529 /* boot code is located in KERNEL space */
2530 dst = (u_char *) boot_addr + KERNBASE;
2532 /* modify the lgdt arg */
2533 dst32 = (u_int32_t *) (dst + ((u_int) & mp_gdtbase - boot_base));
2534 *dst32 = boot_addr + ((u_int) & MP_GDT - boot_base);
2536 /* modify the ljmp target for MPentry() */
2537 dst32 = (u_int32_t *) (dst + ((u_int) bigJump - boot_base) + 1);
2538 *dst32 = ((u_int) MPentry - KERNBASE);
2540 /* modify the target for boot code segment */
2541 dst16 = (u_int16_t *) (dst + ((u_int) bootCodeSeg - boot_base));
2542 dst8 = (u_int8_t *) (dst16 + 1);
2543 *dst16 = (u_int) boot_addr & 0xffff;
2544 *dst8 = ((u_int) boot_addr >> 16) & 0xff;
2546 /* modify the target for boot data segment */
2547 dst16 = (u_int16_t *) (dst + ((u_int) bootDataSeg - boot_base));
2548 dst8 = (u_int8_t *) (dst16 + 1);
2549 *dst16 = (u_int) boot_addr & 0xffff;
2550 *dst8 = ((u_int) boot_addr >> 16) & 0xff;
2555 * this function starts the AP (application processor) identified
2556 * by the APIC ID 'physicalCpu'. It does quite a "song and dance"
2557 * to accomplish this. This is necessary because of the nuances
2558 * of the different hardware we might encounter. It ain't pretty,
2559 * but it seems to work.
2561 * NOTE: eventually an AP gets to ap_init(), which is called just
2562 * before the AP goes into the LWKT scheduler's idle loop.
2565 start_ap(struct mdglobaldata *gd, u_int boot_addr)
2569 u_long icr_lo, icr_hi;
2571 POSTCODE(START_AP_POST);
2573 /* get the PHYSICAL APIC ID# */
2574 physical_cpu = CPU_TO_ID(gd->mi.gd_cpuid);
2576 /* calculate the vector */
2577 vector = (boot_addr >> 12) & 0xff;
2579 /* Make sure the target cpu sees everything */
2583 * first we do an INIT/RESET IPI this INIT IPI might be run, reseting
2584 * and running the target CPU. OR this INIT IPI might be latched (P5
2585 * bug), CPU waiting for STARTUP IPI. OR this INIT IPI might be
2589 /* setup the address for the target AP */
2590 icr_hi = lapic.icr_hi & ~APIC_ID_MASK;
2591 icr_hi |= (physical_cpu << 24);
2592 lapic.icr_hi = icr_hi;
2594 /* do an INIT IPI: assert RESET */
2595 icr_lo = lapic.icr_lo & 0xfff00000;
2596 lapic.icr_lo = icr_lo | 0x0000c500;
2598 /* wait for pending status end */
2599 while (lapic.icr_lo & APIC_DELSTAT_MASK)
2602 /* do an INIT IPI: deassert RESET */
2603 lapic.icr_lo = icr_lo | 0x00008500;
2605 /* wait for pending status end */
2606 u_sleep(10000); /* wait ~10mS */
2607 while (lapic.icr_lo & APIC_DELSTAT_MASK)
2611 * next we do a STARTUP IPI: the previous INIT IPI might still be
2612 * latched, (P5 bug) this 1st STARTUP would then terminate
2613 * immediately, and the previously started INIT IPI would continue. OR
2614 * the previous INIT IPI has already run. and this STARTUP IPI will
2615 * run. OR the previous INIT IPI was ignored. and this STARTUP IPI
2619 /* do a STARTUP IPI */
2620 lapic.icr_lo = icr_lo | 0x00000600 | vector;
2621 while (lapic.icr_lo & APIC_DELSTAT_MASK)
2623 u_sleep(200); /* wait ~200uS */
2626 * finally we do a 2nd STARTUP IPI: this 2nd STARTUP IPI should run IF
2627 * the previous STARTUP IPI was cancelled by a latched INIT IPI. OR
2628 * this STARTUP IPI will be ignored, as only ONE STARTUP IPI is
2629 * recognized after hardware RESET or INIT IPI.
2632 lapic.icr_lo = icr_lo | 0x00000600 | vector;
2633 while (lapic.icr_lo & APIC_DELSTAT_MASK)
2635 u_sleep(200); /* wait ~200uS */
2637 /* wait for it to start, see ap_init() */
2638 set_apic_timer(5000000);/* == 5 seconds */
2639 while (read_apic_timer()) {
2640 if (smp_startup_mask & (1 << gd->mi.gd_cpuid))
2641 return 1; /* return SUCCESS */
2643 return 0; /* return FAILURE */
2648 * Lazy flush the TLB on all other CPU's. DEPRECATED.
2650 * If for some reason we were unable to start all cpus we cannot safely
2651 * use broadcast IPIs.
2657 if (smp_startup_mask == smp_active_mask) {
2658 all_but_self_ipi(XINVLTLB_OFFSET);
2660 selected_apic_ipi(smp_active_mask, XINVLTLB_OFFSET,
2661 APIC_DELMODE_FIXED);
2667 * When called the executing CPU will send an IPI to all other CPUs
2668 * requesting that they halt execution.
2670 * Usually (but not necessarily) called with 'other_cpus' as its arg.
2672 * - Signals all CPUs in map to stop.
2673 * - Waits for each to stop.
2680 * XXX FIXME: this is not MP-safe, needs a lock to prevent multiple CPUs
2681 * from executing at same time.
2684 stop_cpus(u_int map)
2686 map &= smp_active_mask;
2688 /* send the Xcpustop IPI to all CPUs in map */
2689 selected_apic_ipi(map, XCPUSTOP_OFFSET, APIC_DELMODE_FIXED);
2691 while ((stopped_cpus & map) != map)
2699 * Called by a CPU to restart stopped CPUs.
2701 * Usually (but not necessarily) called with 'stopped_cpus' as its arg.
2703 * - Signals all CPUs in map to restart.
2704 * - Waits for each to restart.
2712 restart_cpus(u_int map)
2714 /* signal other cpus to restart */
2715 started_cpus = map & smp_active_mask;
2717 while ((stopped_cpus & map) != 0) /* wait for each to clear its bit */
2724 * This is called once the mpboot code has gotten us properly relocated
2725 * and the MMU turned on, etc. ap_init() is actually the idle thread,
2726 * and when it returns the scheduler will call the real cpu_idle() main
2727 * loop for the idlethread. Interrupts are disabled on entry and should
2728 * remain disabled at return.
2736 * Adjust smp_startup_mask to signal the BSP that we have started
2737 * up successfully. Note that we do not yet hold the BGL. The BSP
2738 * is waiting for our signal.
2740 * We can't set our bit in smp_active_mask yet because we are holding
2741 * interrupts physically disabled and remote cpus could deadlock
2742 * trying to send us an IPI.
2744 smp_startup_mask |= 1 << mycpu->gd_cpuid;
2748 * Interlock for finalization. Wait until mp_finish is non-zero,
2749 * then get the MP lock.
2751 * Note: We are in a critical section.
2753 * Note: We have to synchronize td_mpcount to our desired MP state
2754 * before calling cpu_try_mplock().
2756 * Note: we are the idle thread, we can only spin.
2758 * Note: The load fence is memory volatile and prevents the compiler
2759 * from improperly caching mp_finish, and the cpu from improperly
2762 while (mp_finish == 0)
2764 ++curthread->td_mpcount;
2765 while (cpu_try_mplock() == 0)
2768 if (cpu_feature & CPUID_TSC) {
2770 * The BSP is constantly updating tsc0_offset, figure out the
2771 * relative difference to synchronize ktrdump.
2773 tsc_offsets[mycpu->gd_cpuid] = rdtsc() - tsc0_offset;
2776 /* BSP may have changed PTD while we're waiting for the lock */
2779 #if defined(I586_CPU) && !defined(NO_F00F_HACK)
2783 /* Build our map of 'other' CPUs. */
2784 mycpu->gd_other_cpus = smp_startup_mask & ~(1 << mycpu->gd_cpuid);
2786 kprintf("SMP: AP CPU #%d Launched!\n", mycpu->gd_cpuid);
2788 /* A quick check from sanity claus */
2789 apic_id = (apic_id_to_logical[(lapic.id & 0x0f000000) >> 24]);
2790 if (mycpu->gd_cpuid != apic_id) {
2791 kprintf("SMP: cpuid = %d\n", mycpu->gd_cpuid);
2792 kprintf("SMP: apic_id = %d\n", apic_id);
2793 kprintf("PTD[MPPTDI] = %p\n", (void *)PTD[MPPTDI]);
2794 panic("cpuid mismatch! boom!!");
2797 /* Initialize AP's local APIC for irq's */
2798 apic_initialize(FALSE);
2800 /* Set memory range attributes for this CPU to match the BSP */
2801 mem_range_AP_init();
2804 * Once we go active we must process any IPIQ messages that may
2805 * have been queued, because no actual IPI will occur until we
2806 * set our bit in the smp_active_mask. If we don't the IPI
2807 * message interlock could be left set which would also prevent
2810 * The idle loop doesn't expect the BGL to be held and while
2811 * lwkt_switch() normally cleans things up this is a special case
2812 * because we returning almost directly into the idle loop.
2814 * The idle thread is never placed on the runq, make sure
2815 * nothing we've done put it there.
2817 KKASSERT(curthread->td_mpcount == 1);
2818 smp_active_mask |= 1 << mycpu->gd_cpuid;
2821 * Enable interrupts here. idle_restore will also do it, but
2822 * doing it here lets us clean up any strays that got posted to
2823 * the CPU during the AP boot while we are still in a critical
2826 __asm __volatile("sti; pause; pause"::);
2827 mdcpu->gd_fpending = 0;
2828 mdcpu->gd_ipending = 0;
2830 initclocks_pcpu(); /* clock interrupts (via IPIs) */
2831 lwkt_process_ipiq();
2834 * Releasing the mp lock lets the BSP finish up the SMP init
2837 KKASSERT((curthread->td_flags & TDF_RUNQ) == 0);
2841 * Get SMP fully working before we start initializing devices.
2849 kprintf("Finish MP startup\n");
2850 if (cpu_feature & CPUID_TSC)
2851 tsc0_offset = rdtsc();
2854 while (smp_active_mask != smp_startup_mask) {
2856 if (cpu_feature & CPUID_TSC)
2857 tsc0_offset = rdtsc();
2859 while (try_mplock() == 0)
2862 kprintf("Active CPU Mask: %08x\n", smp_active_mask);
2865 SYSINIT(finishsmp, SI_BOOT2_FINISH_SMP, SI_ORDER_FIRST, ap_finish, NULL)
2868 cpu_send_ipiq(int dcpu)
2870 if ((1 << dcpu) & smp_active_mask)
2871 single_apic_ipi(dcpu, XIPIQ_OFFSET, APIC_DELMODE_FIXED);
2874 #if 0 /* single_apic_ipi_passive() not working yet */
2876 * Returns 0 on failure, 1 on success
2879 cpu_send_ipiq_passive(int dcpu)
2882 if ((1 << dcpu) & smp_active_mask) {
2883 r = single_apic_ipi_passive(dcpu, XIPIQ_OFFSET,
2884 APIC_DELMODE_FIXED);