bnx: Pack TX mbuf and dmamap together; improve cache utilization
[dragonfly.git] / sys / dev / netif / bnx / if_bnx.c
1 /*
2  * Copyright (c) 2001 Wind River Systems
3  * Copyright (c) 1997, 1998, 1999, 2001
4  *      Bill Paul <wpaul@windriver.com>.  All rights reserved.
5  *
6  * Redistribution and use in source and binary forms, with or without
7  * modification, are permitted provided that the following conditions
8  * are met:
9  * 1. Redistributions of source code must retain the above copyright
10  *    notice, this list of conditions and the following disclaimer.
11  * 2. Redistributions in binary form must reproduce the above copyright
12  *    notice, this list of conditions and the following disclaimer in the
13  *    documentation and/or other materials provided with the distribution.
14  * 3. All advertising materials mentioning features or use of this software
15  *    must display the following acknowledgement:
16  *      This product includes software developed by Bill Paul.
17  * 4. Neither the name of the author nor the names of any co-contributors
18  *    may be used to endorse or promote products derived from this software
19  *    without specific prior written permission.
20  *
21  * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
22  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24  * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
25  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
31  * THE POSSIBILITY OF SUCH DAMAGE.
32  *
33  * $FreeBSD: src/sys/dev/bge/if_bge.c,v 1.3.2.39 2005/07/03 03:41:18 silby Exp $
34  */
35
36 #include "opt_bnx.h"
37 #include "opt_ifpoll.h"
38
39 #include <sys/param.h>
40 #include <sys/bus.h>
41 #include <sys/endian.h>
42 #include <sys/kernel.h>
43 #include <sys/interrupt.h>
44 #include <sys/mbuf.h>
45 #include <sys/malloc.h>
46 #include <sys/queue.h>
47 #include <sys/rman.h>
48 #include <sys/serialize.h>
49 #include <sys/socket.h>
50 #include <sys/sockio.h>
51 #include <sys/sysctl.h>
52
53 #include <netinet/ip.h>
54 #include <netinet/tcp.h>
55
56 #include <net/bpf.h>
57 #include <net/ethernet.h>
58 #include <net/if.h>
59 #include <net/if_arp.h>
60 #include <net/if_dl.h>
61 #include <net/if_media.h>
62 #include <net/if_poll.h>
63 #include <net/if_types.h>
64 #include <net/ifq_var.h>
65 #include <net/vlan/if_vlan_var.h>
66 #include <net/vlan/if_vlan_ether.h>
67
68 #include <dev/netif/mii_layer/mii.h>
69 #include <dev/netif/mii_layer/miivar.h>
70 #include <dev/netif/mii_layer/brgphyreg.h>
71
72 #include <bus/pci/pcidevs.h>
73 #include <bus/pci/pcireg.h>
74 #include <bus/pci/pcivar.h>
75
76 #include <dev/netif/bge/if_bgereg.h>
77 #include <dev/netif/bnx/if_bnxvar.h>
78
79 /* "device miibus" required.  See GENERIC if you get errors here. */
80 #include "miibus_if.h"
81
82 #define BNX_CSUM_FEATURES       (CSUM_IP | CSUM_TCP | CSUM_UDP)
83
84 #define BNX_INTR_CKINTVL        ((10 * hz) / 1000)      /* 10ms */
85
86 static const struct bnx_type {
87         uint16_t                bnx_vid;
88         uint16_t                bnx_did;
89         char                    *bnx_name;
90 } bnx_devs[] = {
91         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5717,
92                 "Broadcom BCM5717 Gigabit Ethernet" },
93         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5717C,
94                 "Broadcom BCM5717C Gigabit Ethernet" },
95         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5718,
96                 "Broadcom BCM5718 Gigabit Ethernet" },
97         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5719,
98                 "Broadcom BCM5719 Gigabit Ethernet" },
99         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5720_ALT,
100                 "Broadcom BCM5720 Gigabit Ethernet" },
101
102         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5725,
103                 "Broadcom BCM5725 Gigabit Ethernet" },
104         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5727,
105                 "Broadcom BCM5727 Gigabit Ethernet" },
106         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5762,
107                 "Broadcom BCM5762 Gigabit Ethernet" },
108
109         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57761,
110                 "Broadcom BCM57761 Gigabit Ethernet" },
111         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57762,
112                 "Broadcom BCM57762 Gigabit Ethernet" },
113         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57765,
114                 "Broadcom BCM57765 Gigabit Ethernet" },
115         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57766,
116                 "Broadcom BCM57766 Gigabit Ethernet" },
117         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57781,
118                 "Broadcom BCM57781 Gigabit Ethernet" },
119         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57782,
120                 "Broadcom BCM57782 Gigabit Ethernet" },
121         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57785,
122                 "Broadcom BCM57785 Gigabit Ethernet" },
123         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57786,
124                 "Broadcom BCM57786 Gigabit Ethernet" },
125         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57791,
126                 "Broadcom BCM57791 Fast Ethernet" },
127         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57795,
128                 "Broadcom BCM57795 Fast Ethernet" },
129
130         { 0, 0, NULL }
131 };
132
133 #define BNX_IS_JUMBO_CAPABLE(sc)        ((sc)->bnx_flags & BNX_FLAG_JUMBO)
134 #define BNX_IS_5717_PLUS(sc)            ((sc)->bnx_flags & BNX_FLAG_5717_PLUS)
135 #define BNX_IS_57765_PLUS(sc)           ((sc)->bnx_flags & BNX_FLAG_57765_PLUS)
136 #define BNX_IS_57765_FAMILY(sc)  \
137         ((sc)->bnx_flags & BNX_FLAG_57765_FAMILY)
138
139 typedef int     (*bnx_eaddr_fcn_t)(struct bnx_softc *, uint8_t[]);
140
141 static int      bnx_probe(device_t);
142 static int      bnx_attach(device_t);
143 static int      bnx_detach(device_t);
144 static void     bnx_shutdown(device_t);
145 static int      bnx_suspend(device_t);
146 static int      bnx_resume(device_t);
147 static int      bnx_miibus_readreg(device_t, int, int);
148 static int      bnx_miibus_writereg(device_t, int, int, int);
149 static void     bnx_miibus_statchg(device_t);
150
151 #ifdef IFPOLL_ENABLE
152 static void     bnx_npoll(struct ifnet *, struct ifpoll_info *);
153 static void     bnx_npoll_compat(struct ifnet *, void *, int);
154 #endif
155 static void     bnx_intr_legacy(void *);
156 static void     bnx_msi(void *);
157 static void     bnx_msi_oneshot(void *);
158 static void     bnx_intr(struct bnx_softc *);
159 static void     bnx_enable_intr(struct bnx_softc *);
160 static void     bnx_disable_intr(struct bnx_softc *);
161 static void     bnx_txeof(struct bnx_tx_ring *, uint16_t);
162 static void     bnx_rxeof(struct bnx_softc *, uint16_t, int);
163
164 static void     bnx_start(struct ifnet *, struct ifaltq_subque *);
165 static int      bnx_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
166 static void     bnx_init(void *);
167 static void     bnx_stop(struct bnx_softc *);
168 static void     bnx_watchdog(struct ifnet *);
169 static int      bnx_ifmedia_upd(struct ifnet *);
170 static void     bnx_ifmedia_sts(struct ifnet *, struct ifmediareq *);
171 static void     bnx_tick(void *);
172
173 static int      bnx_alloc_jumbo_mem(struct bnx_softc *);
174 static void     bnx_free_jumbo_mem(struct bnx_softc *);
175 static struct bnx_jslot
176                 *bnx_jalloc(struct bnx_softc *);
177 static void     bnx_jfree(void *);
178 static void     bnx_jref(void *);
179 static int      bnx_newbuf_std(struct bnx_softc *, int, int);
180 static int      bnx_newbuf_jumbo(struct bnx_softc *, int, int);
181 static void     bnx_setup_rxdesc_std(struct bnx_softc *, int);
182 static void     bnx_setup_rxdesc_jumbo(struct bnx_softc *, int);
183 static int      bnx_init_rx_ring_std(struct bnx_softc *);
184 static void     bnx_free_rx_ring_std(struct bnx_softc *);
185 static int      bnx_init_rx_ring_jumbo(struct bnx_softc *);
186 static void     bnx_free_rx_ring_jumbo(struct bnx_softc *);
187 static void     bnx_free_tx_ring(struct bnx_tx_ring *);
188 static int      bnx_init_tx_ring(struct bnx_tx_ring *);
189 static int      bnx_create_tx_ring(struct bnx_tx_ring *);
190 static void     bnx_destroy_tx_ring(struct bnx_tx_ring *);
191 static int      bnx_dma_alloc(struct bnx_softc *);
192 static void     bnx_dma_free(struct bnx_softc *);
193 static int      bnx_dma_block_alloc(struct bnx_softc *, bus_size_t,
194                     bus_dma_tag_t *, bus_dmamap_t *, void **, bus_addr_t *);
195 static void     bnx_dma_block_free(bus_dma_tag_t, bus_dmamap_t, void *);
196 static struct mbuf *
197                 bnx_defrag_shortdma(struct mbuf *);
198 static int      bnx_encap(struct bnx_tx_ring *, struct mbuf **,
199                     uint32_t *, int *);
200 static int      bnx_setup_tso(struct bnx_tx_ring *, struct mbuf **,
201                     uint16_t *, uint16_t *);
202
203 static void     bnx_reset(struct bnx_softc *);
204 static int      bnx_chipinit(struct bnx_softc *);
205 static int      bnx_blockinit(struct bnx_softc *);
206 static void     bnx_stop_block(struct bnx_softc *, bus_size_t, uint32_t);
207 static void     bnx_enable_msi(struct bnx_softc *sc);
208 static void     bnx_setmulti(struct bnx_softc *);
209 static void     bnx_setpromisc(struct bnx_softc *);
210 static void     bnx_stats_update_regs(struct bnx_softc *);
211 static uint32_t bnx_dma_swap_options(struct bnx_softc *);
212
213 static uint32_t bnx_readmem_ind(struct bnx_softc *, uint32_t);
214 static void     bnx_writemem_ind(struct bnx_softc *, uint32_t, uint32_t);
215 #ifdef notdef
216 static uint32_t bnx_readreg_ind(struct bnx_softc *, uint32_t);
217 #endif
218 static void     bnx_writemem_direct(struct bnx_softc *, uint32_t, uint32_t);
219 static void     bnx_writembx(struct bnx_softc *, int, int);
220 static int      bnx_read_nvram(struct bnx_softc *, caddr_t, int, int);
221 static uint8_t  bnx_eeprom_getbyte(struct bnx_softc *, uint32_t, uint8_t *);
222 static int      bnx_read_eeprom(struct bnx_softc *, caddr_t, uint32_t, size_t);
223
224 static void     bnx_tbi_link_upd(struct bnx_softc *, uint32_t);
225 static void     bnx_copper_link_upd(struct bnx_softc *, uint32_t);
226 static void     bnx_autopoll_link_upd(struct bnx_softc *, uint32_t);
227 static void     bnx_link_poll(struct bnx_softc *);
228
229 static int      bnx_get_eaddr_mem(struct bnx_softc *, uint8_t[]);
230 static int      bnx_get_eaddr_nvram(struct bnx_softc *, uint8_t[]);
231 static int      bnx_get_eaddr_eeprom(struct bnx_softc *, uint8_t[]);
232 static int      bnx_get_eaddr(struct bnx_softc *, uint8_t[]);
233
234 static void     bnx_coal_change(struct bnx_softc *);
235 static int      bnx_sysctl_force_defrag(SYSCTL_HANDLER_ARGS);
236 static int      bnx_sysctl_tx_wreg(SYSCTL_HANDLER_ARGS);
237 static int      bnx_sysctl_rx_coal_ticks(SYSCTL_HANDLER_ARGS);
238 static int      bnx_sysctl_tx_coal_ticks(SYSCTL_HANDLER_ARGS);
239 static int      bnx_sysctl_rx_coal_bds(SYSCTL_HANDLER_ARGS);
240 static int      bnx_sysctl_tx_coal_bds(SYSCTL_HANDLER_ARGS);
241 static int      bnx_sysctl_rx_coal_bds_int(SYSCTL_HANDLER_ARGS);
242 static int      bnx_sysctl_tx_coal_bds_int(SYSCTL_HANDLER_ARGS);
243 static int      bnx_sysctl_coal_chg(SYSCTL_HANDLER_ARGS, uint32_t *,
244                     int, int, uint32_t);
245
246 static int      bnx_msi_enable = 1;
247 TUNABLE_INT("hw.bnx.msi.enable", &bnx_msi_enable);
248
249 static device_method_t bnx_methods[] = {
250         /* Device interface */
251         DEVMETHOD(device_probe,         bnx_probe),
252         DEVMETHOD(device_attach,        bnx_attach),
253         DEVMETHOD(device_detach,        bnx_detach),
254         DEVMETHOD(device_shutdown,      bnx_shutdown),
255         DEVMETHOD(device_suspend,       bnx_suspend),
256         DEVMETHOD(device_resume,        bnx_resume),
257
258         /* bus interface */
259         DEVMETHOD(bus_print_child,      bus_generic_print_child),
260         DEVMETHOD(bus_driver_added,     bus_generic_driver_added),
261
262         /* MII interface */
263         DEVMETHOD(miibus_readreg,       bnx_miibus_readreg),
264         DEVMETHOD(miibus_writereg,      bnx_miibus_writereg),
265         DEVMETHOD(miibus_statchg,       bnx_miibus_statchg),
266
267         DEVMETHOD_END
268 };
269
270 static DEFINE_CLASS_0(bnx, bnx_driver, bnx_methods, sizeof(struct bnx_softc));
271 static devclass_t bnx_devclass;
272
273 DECLARE_DUMMY_MODULE(if_bnx);
274 DRIVER_MODULE(if_bnx, pci, bnx_driver, bnx_devclass, NULL, NULL);
275 DRIVER_MODULE(miibus, bnx, miibus_driver, miibus_devclass, NULL, NULL);
276
277 static uint32_t
278 bnx_readmem_ind(struct bnx_softc *sc, uint32_t off)
279 {
280         device_t dev = sc->bnx_dev;
281         uint32_t val;
282
283         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
284         val = pci_read_config(dev, BGE_PCI_MEMWIN_DATA, 4);
285         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4);
286         return (val);
287 }
288
289 static void
290 bnx_writemem_ind(struct bnx_softc *sc, uint32_t off, uint32_t val)
291 {
292         device_t dev = sc->bnx_dev;
293
294         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
295         pci_write_config(dev, BGE_PCI_MEMWIN_DATA, val, 4);
296         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4);
297 }
298
299 static void
300 bnx_writemem_direct(struct bnx_softc *sc, uint32_t off, uint32_t val)
301 {
302         CSR_WRITE_4(sc, off, val);
303 }
304
305 static void
306 bnx_writembx(struct bnx_softc *sc, int off, int val)
307 {
308         CSR_WRITE_4(sc, off, val);
309 }
310
311 /*
312  * Read a sequence of bytes from NVRAM.
313  */
314 static int
315 bnx_read_nvram(struct bnx_softc *sc, caddr_t dest, int off, int cnt)
316 {
317         return (1);
318 }
319
320 /*
321  * Read a byte of data stored in the EEPROM at address 'addr.' The
322  * BCM570x supports both the traditional bitbang interface and an
323  * auto access interface for reading the EEPROM. We use the auto
324  * access method.
325  */
326 static uint8_t
327 bnx_eeprom_getbyte(struct bnx_softc *sc, uint32_t addr, uint8_t *dest)
328 {
329         int i;
330         uint32_t byte = 0;
331
332         /*
333          * Enable use of auto EEPROM access so we can avoid
334          * having to use the bitbang method.
335          */
336         BNX_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM);
337
338         /* Reset the EEPROM, load the clock period. */
339         CSR_WRITE_4(sc, BGE_EE_ADDR,
340             BGE_EEADDR_RESET|BGE_EEHALFCLK(BGE_HALFCLK_384SCL));
341         DELAY(20);
342
343         /* Issue the read EEPROM command. */
344         CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr);
345
346         /* Wait for completion */
347         for(i = 0; i < BNX_TIMEOUT * 10; i++) {
348                 DELAY(10);
349                 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE)
350                         break;
351         }
352
353         if (i == BNX_TIMEOUT) {
354                 if_printf(&sc->arpcom.ac_if, "eeprom read timed out\n");
355                 return(1);
356         }
357
358         /* Get result. */
359         byte = CSR_READ_4(sc, BGE_EE_DATA);
360
361         *dest = (byte >> ((addr % 4) * 8)) & 0xFF;
362
363         return(0);
364 }
365
366 /*
367  * Read a sequence of bytes from the EEPROM.
368  */
369 static int
370 bnx_read_eeprom(struct bnx_softc *sc, caddr_t dest, uint32_t off, size_t len)
371 {
372         size_t i;
373         int err;
374         uint8_t byte;
375
376         for (byte = 0, err = 0, i = 0; i < len; i++) {
377                 err = bnx_eeprom_getbyte(sc, off + i, &byte);
378                 if (err)
379                         break;
380                 *(dest + i) = byte;
381         }
382
383         return(err ? 1 : 0);
384 }
385
386 static int
387 bnx_miibus_readreg(device_t dev, int phy, int reg)
388 {
389         struct bnx_softc *sc = device_get_softc(dev);
390         uint32_t val;
391         int i;
392
393         KASSERT(phy == sc->bnx_phyno,
394             ("invalid phyno %d, should be %d", phy, sc->bnx_phyno));
395
396         /* Clear the autopoll bit if set, otherwise may trigger PCI errors. */
397         if (sc->bnx_mi_mode & BGE_MIMODE_AUTOPOLL) {
398                 CSR_WRITE_4(sc, BGE_MI_MODE,
399                     sc->bnx_mi_mode & ~BGE_MIMODE_AUTOPOLL);
400                 DELAY(80);
401         }
402
403         CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ | BGE_MICOMM_BUSY |
404             BGE_MIPHY(phy) | BGE_MIREG(reg));
405
406         /* Poll for the PHY register access to complete. */
407         for (i = 0; i < BNX_TIMEOUT; i++) {
408                 DELAY(10);
409                 val = CSR_READ_4(sc, BGE_MI_COMM);
410                 if ((val & BGE_MICOMM_BUSY) == 0) {
411                         DELAY(5);
412                         val = CSR_READ_4(sc, BGE_MI_COMM);
413                         break;
414                 }
415         }
416         if (i == BNX_TIMEOUT) {
417                 if_printf(&sc->arpcom.ac_if, "PHY read timed out "
418                     "(phy %d, reg %d, val 0x%08x)\n", phy, reg, val);
419                 val = 0;
420         }
421
422         /* Restore the autopoll bit if necessary. */
423         if (sc->bnx_mi_mode & BGE_MIMODE_AUTOPOLL) {
424                 CSR_WRITE_4(sc, BGE_MI_MODE, sc->bnx_mi_mode);
425                 DELAY(80);
426         }
427
428         if (val & BGE_MICOMM_READFAIL)
429                 return 0;
430
431         return (val & 0xFFFF);
432 }
433
434 static int
435 bnx_miibus_writereg(device_t dev, int phy, int reg, int val)
436 {
437         struct bnx_softc *sc = device_get_softc(dev);
438         int i;
439
440         KASSERT(phy == sc->bnx_phyno,
441             ("invalid phyno %d, should be %d", phy, sc->bnx_phyno));
442
443         /* Clear the autopoll bit if set, otherwise may trigger PCI errors. */
444         if (sc->bnx_mi_mode & BGE_MIMODE_AUTOPOLL) {
445                 CSR_WRITE_4(sc, BGE_MI_MODE,
446                     sc->bnx_mi_mode & ~BGE_MIMODE_AUTOPOLL);
447                 DELAY(80);
448         }
449
450         CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE | BGE_MICOMM_BUSY |
451             BGE_MIPHY(phy) | BGE_MIREG(reg) | val);
452
453         for (i = 0; i < BNX_TIMEOUT; i++) {
454                 DELAY(10);
455                 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY)) {
456                         DELAY(5);
457                         CSR_READ_4(sc, BGE_MI_COMM); /* dummy read */
458                         break;
459                 }
460         }
461         if (i == BNX_TIMEOUT) {
462                 if_printf(&sc->arpcom.ac_if, "PHY write timed out "
463                     "(phy %d, reg %d, val %d)\n", phy, reg, val);
464         }
465
466         /* Restore the autopoll bit if necessary. */
467         if (sc->bnx_mi_mode & BGE_MIMODE_AUTOPOLL) {
468                 CSR_WRITE_4(sc, BGE_MI_MODE, sc->bnx_mi_mode);
469                 DELAY(80);
470         }
471
472         return 0;
473 }
474
475 static void
476 bnx_miibus_statchg(device_t dev)
477 {
478         struct bnx_softc *sc;
479         struct mii_data *mii;
480
481         sc = device_get_softc(dev);
482         mii = device_get_softc(sc->bnx_miibus);
483
484         if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
485             (IFM_ACTIVE | IFM_AVALID)) {
486                 switch (IFM_SUBTYPE(mii->mii_media_active)) {
487                 case IFM_10_T:
488                 case IFM_100_TX:
489                         sc->bnx_link = 1;
490                         break;
491                 case IFM_1000_T:
492                 case IFM_1000_SX:
493                 case IFM_2500_SX:
494                         sc->bnx_link = 1;
495                         break;
496                 default:
497                         sc->bnx_link = 0;
498                         break;
499                 }
500         } else {
501                 sc->bnx_link = 0;
502         }
503         if (sc->bnx_link == 0)
504                 return;
505
506         BNX_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_PORTMODE);
507         if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T ||
508             IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) {
509                 BNX_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_GMII);
510         } else {
511                 BNX_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_MII);
512         }
513
514         if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
515                 BNX_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX);
516         } else {
517                 BNX_SETBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX);
518         }
519 }
520
521 /*
522  * Memory management for jumbo frames.
523  */
524 static int
525 bnx_alloc_jumbo_mem(struct bnx_softc *sc)
526 {
527         struct ifnet *ifp = &sc->arpcom.ac_if;
528         struct bnx_jslot *entry;
529         uint8_t *ptr;
530         bus_addr_t paddr;
531         int i, error;
532
533         /*
534          * Create tag for jumbo mbufs.
535          * This is really a bit of a kludge. We allocate a special
536          * jumbo buffer pool which (thanks to the way our DMA
537          * memory allocation works) will consist of contiguous
538          * pages. This means that even though a jumbo buffer might
539          * be larger than a page size, we don't really need to
540          * map it into more than one DMA segment. However, the
541          * default mbuf tag will result in multi-segment mappings,
542          * so we have to create a special jumbo mbuf tag that
543          * lets us get away with mapping the jumbo buffers as
544          * a single segment. I think eventually the driver should
545          * be changed so that it uses ordinary mbufs and cluster
546          * buffers, i.e. jumbo frames can span multiple DMA
547          * descriptors. But that's a project for another day.
548          */
549
550         /*
551          * Create DMA stuffs for jumbo RX ring.
552          */
553         error = bnx_dma_block_alloc(sc, BGE_JUMBO_RX_RING_SZ,
554                                     &sc->bnx_cdata.bnx_rx_jumbo_ring_tag,
555                                     &sc->bnx_cdata.bnx_rx_jumbo_ring_map,
556                                     (void *)&sc->bnx_ldata.bnx_rx_jumbo_ring,
557                                     &sc->bnx_ldata.bnx_rx_jumbo_ring_paddr);
558         if (error) {
559                 if_printf(ifp, "could not create jumbo RX ring\n");
560                 return error;
561         }
562
563         /*
564          * Create DMA stuffs for jumbo buffer block.
565          */
566         error = bnx_dma_block_alloc(sc, BNX_JMEM,
567                                     &sc->bnx_cdata.bnx_jumbo_tag,
568                                     &sc->bnx_cdata.bnx_jumbo_map,
569                                     (void **)&sc->bnx_ldata.bnx_jumbo_buf,
570                                     &paddr);
571         if (error) {
572                 if_printf(ifp, "could not create jumbo buffer\n");
573                 return error;
574         }
575
576         SLIST_INIT(&sc->bnx_jfree_listhead);
577
578         /*
579          * Now divide it up into 9K pieces and save the addresses
580          * in an array. Note that we play an evil trick here by using
581          * the first few bytes in the buffer to hold the the address
582          * of the softc structure for this interface. This is because
583          * bnx_jfree() needs it, but it is called by the mbuf management
584          * code which will not pass it to us explicitly.
585          */
586         for (i = 0, ptr = sc->bnx_ldata.bnx_jumbo_buf; i < BNX_JSLOTS; i++) {
587                 entry = &sc->bnx_cdata.bnx_jslots[i];
588                 entry->bnx_sc = sc;
589                 entry->bnx_buf = ptr;
590                 entry->bnx_paddr = paddr;
591                 entry->bnx_inuse = 0;
592                 entry->bnx_slot = i;
593                 SLIST_INSERT_HEAD(&sc->bnx_jfree_listhead, entry, jslot_link);
594
595                 ptr += BNX_JLEN;
596                 paddr += BNX_JLEN;
597         }
598         return 0;
599 }
600
601 static void
602 bnx_free_jumbo_mem(struct bnx_softc *sc)
603 {
604         /* Destroy jumbo RX ring. */
605         bnx_dma_block_free(sc->bnx_cdata.bnx_rx_jumbo_ring_tag,
606                            sc->bnx_cdata.bnx_rx_jumbo_ring_map,
607                            sc->bnx_ldata.bnx_rx_jumbo_ring);
608
609         /* Destroy jumbo buffer block. */
610         bnx_dma_block_free(sc->bnx_cdata.bnx_jumbo_tag,
611                            sc->bnx_cdata.bnx_jumbo_map,
612                            sc->bnx_ldata.bnx_jumbo_buf);
613 }
614
615 /*
616  * Allocate a jumbo buffer.
617  */
618 static struct bnx_jslot *
619 bnx_jalloc(struct bnx_softc *sc)
620 {
621         struct bnx_jslot *entry;
622
623         lwkt_serialize_enter(&sc->bnx_jslot_serializer);
624         entry = SLIST_FIRST(&sc->bnx_jfree_listhead);
625         if (entry) {
626                 SLIST_REMOVE_HEAD(&sc->bnx_jfree_listhead, jslot_link);
627                 entry->bnx_inuse = 1;
628         } else {
629                 if_printf(&sc->arpcom.ac_if, "no free jumbo buffers\n");
630         }
631         lwkt_serialize_exit(&sc->bnx_jslot_serializer);
632         return(entry);
633 }
634
635 /*
636  * Adjust usage count on a jumbo buffer.
637  */
638 static void
639 bnx_jref(void *arg)
640 {
641         struct bnx_jslot *entry = (struct bnx_jslot *)arg;
642         struct bnx_softc *sc = entry->bnx_sc;
643
644         if (sc == NULL)
645                 panic("bnx_jref: can't find softc pointer!");
646
647         if (&sc->bnx_cdata.bnx_jslots[entry->bnx_slot] != entry) {
648                 panic("bnx_jref: asked to reference buffer "
649                     "that we don't manage!");
650         } else if (entry->bnx_inuse == 0) {
651                 panic("bnx_jref: buffer already free!");
652         } else {
653                 atomic_add_int(&entry->bnx_inuse, 1);
654         }
655 }
656
657 /*
658  * Release a jumbo buffer.
659  */
660 static void
661 bnx_jfree(void *arg)
662 {
663         struct bnx_jslot *entry = (struct bnx_jslot *)arg;
664         struct bnx_softc *sc = entry->bnx_sc;
665
666         if (sc == NULL)
667                 panic("bnx_jfree: can't find softc pointer!");
668
669         if (&sc->bnx_cdata.bnx_jslots[entry->bnx_slot] != entry) {
670                 panic("bnx_jfree: asked to free buffer that we don't manage!");
671         } else if (entry->bnx_inuse == 0) {
672                 panic("bnx_jfree: buffer already free!");
673         } else {
674                 /*
675                  * Possible MP race to 0, use the serializer.  The atomic insn
676                  * is still needed for races against bnx_jref().
677                  */
678                 lwkt_serialize_enter(&sc->bnx_jslot_serializer);
679                 atomic_subtract_int(&entry->bnx_inuse, 1);
680                 if (entry->bnx_inuse == 0) {
681                         SLIST_INSERT_HEAD(&sc->bnx_jfree_listhead, 
682                                           entry, jslot_link);
683                 }
684                 lwkt_serialize_exit(&sc->bnx_jslot_serializer);
685         }
686 }
687
688
689 /*
690  * Intialize a standard receive ring descriptor.
691  */
692 static int
693 bnx_newbuf_std(struct bnx_softc *sc, int i, int init)
694 {
695         struct mbuf *m_new = NULL;
696         bus_dma_segment_t seg;
697         bus_dmamap_t map;
698         int error, nsegs;
699
700         m_new = m_getcl(init ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR);
701         if (m_new == NULL)
702                 return ENOBUFS;
703         m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
704         m_adj(m_new, ETHER_ALIGN);
705
706         error = bus_dmamap_load_mbuf_segment(sc->bnx_cdata.bnx_rx_mtag,
707                         sc->bnx_cdata.bnx_rx_tmpmap, m_new,
708                         &seg, 1, &nsegs, BUS_DMA_NOWAIT);
709         if (error) {
710                 m_freem(m_new);
711                 return error;
712         }
713
714         if (!init) {
715                 bus_dmamap_sync(sc->bnx_cdata.bnx_rx_mtag,
716                                 sc->bnx_cdata.bnx_rx_std_dmamap[i],
717                                 BUS_DMASYNC_POSTREAD);
718                 bus_dmamap_unload(sc->bnx_cdata.bnx_rx_mtag,
719                         sc->bnx_cdata.bnx_rx_std_dmamap[i]);
720         }
721
722         map = sc->bnx_cdata.bnx_rx_tmpmap;
723         sc->bnx_cdata.bnx_rx_tmpmap = sc->bnx_cdata.bnx_rx_std_dmamap[i];
724         sc->bnx_cdata.bnx_rx_std_dmamap[i] = map;
725
726         sc->bnx_cdata.bnx_rx_std_chain[i].bnx_mbuf = m_new;
727         sc->bnx_cdata.bnx_rx_std_chain[i].bnx_paddr = seg.ds_addr;
728
729         bnx_setup_rxdesc_std(sc, i);
730         return 0;
731 }
732
733 static void
734 bnx_setup_rxdesc_std(struct bnx_softc *sc, int i)
735 {
736         struct bnx_rxchain *rc;
737         struct bge_rx_bd *r;
738
739         rc = &sc->bnx_cdata.bnx_rx_std_chain[i];
740         r = &sc->bnx_ldata.bnx_rx_std_ring[i];
741
742         r->bge_addr.bge_addr_lo = BGE_ADDR_LO(rc->bnx_paddr);
743         r->bge_addr.bge_addr_hi = BGE_ADDR_HI(rc->bnx_paddr);
744         r->bge_len = rc->bnx_mbuf->m_len;
745         r->bge_idx = i;
746         r->bge_flags = BGE_RXBDFLAG_END;
747 }
748
749 /*
750  * Initialize a jumbo receive ring descriptor. This allocates
751  * a jumbo buffer from the pool managed internally by the driver.
752  */
753 static int
754 bnx_newbuf_jumbo(struct bnx_softc *sc, int i, int init)
755 {
756         struct mbuf *m_new = NULL;
757         struct bnx_jslot *buf;
758         bus_addr_t paddr;
759
760         /* Allocate the mbuf. */
761         MGETHDR(m_new, init ? MB_WAIT : MB_DONTWAIT, MT_DATA);
762         if (m_new == NULL)
763                 return ENOBUFS;
764
765         /* Allocate the jumbo buffer */
766         buf = bnx_jalloc(sc);
767         if (buf == NULL) {
768                 m_freem(m_new);
769                 return ENOBUFS;
770         }
771
772         /* Attach the buffer to the mbuf. */
773         m_new->m_ext.ext_arg = buf;
774         m_new->m_ext.ext_buf = buf->bnx_buf;
775         m_new->m_ext.ext_free = bnx_jfree;
776         m_new->m_ext.ext_ref = bnx_jref;
777         m_new->m_ext.ext_size = BNX_JUMBO_FRAMELEN;
778
779         m_new->m_flags |= M_EXT;
780
781         m_new->m_data = m_new->m_ext.ext_buf;
782         m_new->m_len = m_new->m_pkthdr.len = m_new->m_ext.ext_size;
783
784         paddr = buf->bnx_paddr;
785         m_adj(m_new, ETHER_ALIGN);
786         paddr += ETHER_ALIGN;
787
788         /* Save necessary information */
789         sc->bnx_cdata.bnx_rx_jumbo_chain[i].bnx_mbuf = m_new;
790         sc->bnx_cdata.bnx_rx_jumbo_chain[i].bnx_paddr = paddr;
791
792         /* Set up the descriptor. */
793         bnx_setup_rxdesc_jumbo(sc, i);
794         return 0;
795 }
796
797 static void
798 bnx_setup_rxdesc_jumbo(struct bnx_softc *sc, int i)
799 {
800         struct bge_rx_bd *r;
801         struct bnx_rxchain *rc;
802
803         r = &sc->bnx_ldata.bnx_rx_jumbo_ring[i];
804         rc = &sc->bnx_cdata.bnx_rx_jumbo_chain[i];
805
806         r->bge_addr.bge_addr_lo = BGE_ADDR_LO(rc->bnx_paddr);
807         r->bge_addr.bge_addr_hi = BGE_ADDR_HI(rc->bnx_paddr);
808         r->bge_len = rc->bnx_mbuf->m_len;
809         r->bge_idx = i;
810         r->bge_flags = BGE_RXBDFLAG_END|BGE_RXBDFLAG_JUMBO_RING;
811 }
812
813 static int
814 bnx_init_rx_ring_std(struct bnx_softc *sc)
815 {
816         int i, error;
817
818         for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
819                 error = bnx_newbuf_std(sc, i, 1);
820                 if (error)
821                         return error;
822         }
823
824         sc->bnx_std = BGE_STD_RX_RING_CNT - 1;
825         bnx_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bnx_std);
826
827         return(0);
828 }
829
830 static void
831 bnx_free_rx_ring_std(struct bnx_softc *sc)
832 {
833         int i;
834
835         for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
836                 struct bnx_rxchain *rc = &sc->bnx_cdata.bnx_rx_std_chain[i];
837
838                 if (rc->bnx_mbuf != NULL) {
839                         bus_dmamap_unload(sc->bnx_cdata.bnx_rx_mtag,
840                                           sc->bnx_cdata.bnx_rx_std_dmamap[i]);
841                         m_freem(rc->bnx_mbuf);
842                         rc->bnx_mbuf = NULL;
843                 }
844                 bzero(&sc->bnx_ldata.bnx_rx_std_ring[i],
845                     sizeof(struct bge_rx_bd));
846         }
847 }
848
849 static int
850 bnx_init_rx_ring_jumbo(struct bnx_softc *sc)
851 {
852         struct bge_rcb *rcb;
853         int i, error;
854
855         for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
856                 error = bnx_newbuf_jumbo(sc, i, 1);
857                 if (error)
858                         return error;
859         }
860
861         sc->bnx_jumbo = BGE_JUMBO_RX_RING_CNT - 1;
862
863         rcb = &sc->bnx_ldata.bnx_info.bnx_jumbo_rx_rcb;
864         rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0, 0);
865         CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
866
867         bnx_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bnx_jumbo);
868
869         return(0);
870 }
871
872 static void
873 bnx_free_rx_ring_jumbo(struct bnx_softc *sc)
874 {
875         int i;
876
877         for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
878                 struct bnx_rxchain *rc = &sc->bnx_cdata.bnx_rx_jumbo_chain[i];
879
880                 if (rc->bnx_mbuf != NULL) {
881                         m_freem(rc->bnx_mbuf);
882                         rc->bnx_mbuf = NULL;
883                 }
884                 bzero(&sc->bnx_ldata.bnx_rx_jumbo_ring[i],
885                     sizeof(struct bge_rx_bd));
886         }
887 }
888
889 static void
890 bnx_free_tx_ring(struct bnx_tx_ring *txr)
891 {
892         int i;
893
894         for (i = 0; i < BGE_TX_RING_CNT; i++) {
895                 struct bnx_tx_buf *buf = &txr->bnx_tx_buf[i];
896
897                 if (buf->bnx_tx_mbuf != NULL) {
898                         bus_dmamap_unload(txr->bnx_tx_mtag,
899                             buf->bnx_tx_dmamap);
900                         m_freem(buf->bnx_tx_mbuf);
901                         buf->bnx_tx_mbuf = NULL;
902                 }
903                 bzero(&txr->bnx_tx_ring[i], sizeof(struct bge_tx_bd));
904         }
905         txr->bnx_tx_saved_considx = BNX_TXCONS_UNSET;
906 }
907
908 static int
909 bnx_init_tx_ring(struct bnx_tx_ring *txr)
910 {
911         txr->bnx_txcnt = 0;
912         txr->bnx_tx_saved_considx = 0;
913         txr->bnx_tx_prodidx = 0;
914
915         /* Initialize transmit producer index for host-memory send ring. */
916         bnx_writembx(txr->bnx_sc, txr->bnx_tx_mbx, txr->bnx_tx_prodidx);
917
918         return(0);
919 }
920
921 static void
922 bnx_setmulti(struct bnx_softc *sc)
923 {
924         struct ifnet *ifp;
925         struct ifmultiaddr *ifma;
926         uint32_t hashes[4] = { 0, 0, 0, 0 };
927         int h, i;
928
929         ifp = &sc->arpcom.ac_if;
930
931         if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
932                 for (i = 0; i < 4; i++)
933                         CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0xFFFFFFFF);
934                 return;
935         }
936
937         /* First, zot all the existing filters. */
938         for (i = 0; i < 4; i++)
939                 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0);
940
941         /* Now program new ones. */
942         TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
943                 if (ifma->ifma_addr->sa_family != AF_LINK)
944                         continue;
945                 h = ether_crc32_le(
946                     LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
947                     ETHER_ADDR_LEN) & 0x7f;
948                 hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F);
949         }
950
951         for (i = 0; i < 4; i++)
952                 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]);
953 }
954
955 /*
956  * Do endian, PCI and DMA initialization. Also check the on-board ROM
957  * self-test results.
958  */
959 static int
960 bnx_chipinit(struct bnx_softc *sc)
961 {
962         uint32_t dma_rw_ctl, mode_ctl;
963         int i;
964
965         /* Set endian type before we access any non-PCI registers. */
966         pci_write_config(sc->bnx_dev, BGE_PCI_MISC_CTL,
967             BGE_INIT | BGE_PCIMISCCTL_TAGGED_STATUS, 4);
968
969         /* Clear the MAC control register */
970         CSR_WRITE_4(sc, BGE_MAC_MODE, 0);
971
972         /*
973          * Clear the MAC statistics block in the NIC's
974          * internal memory.
975          */
976         for (i = BGE_STATS_BLOCK;
977             i < BGE_STATS_BLOCK_END + 1; i += sizeof(uint32_t))
978                 BNX_MEMWIN_WRITE(sc, i, 0);
979
980         for (i = BGE_STATUS_BLOCK;
981             i < BGE_STATUS_BLOCK_END + 1; i += sizeof(uint32_t))
982                 BNX_MEMWIN_WRITE(sc, i, 0);
983
984         if (BNX_IS_57765_FAMILY(sc)) {
985                 uint32_t val;
986
987                 if (sc->bnx_chipid == BGE_CHIPID_BCM57765_A0) {
988                         mode_ctl = CSR_READ_4(sc, BGE_MODE_CTL);
989                         val = mode_ctl & ~BGE_MODECTL_PCIE_PORTS;
990
991                         /* Access the lower 1K of PL PCI-E block registers. */
992                         CSR_WRITE_4(sc, BGE_MODE_CTL,
993                             val | BGE_MODECTL_PCIE_PL_SEL);
994
995                         val = CSR_READ_4(sc, BGE_PCIE_PL_LO_PHYCTL5);
996                         val |= BGE_PCIE_PL_LO_PHYCTL5_DIS_L2CLKREQ;
997                         CSR_WRITE_4(sc, BGE_PCIE_PL_LO_PHYCTL5, val);
998
999                         CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl);
1000                 }
1001                 if (sc->bnx_chiprev != BGE_CHIPREV_57765_AX) {
1002                         /* Fix transmit hangs */
1003                         val = CSR_READ_4(sc, BGE_CPMU_PADRNG_CTL);
1004                         val |= BGE_CPMU_PADRNG_CTL_RDIV2;
1005                         CSR_WRITE_4(sc, BGE_CPMU_PADRNG_CTL, val);
1006
1007                         mode_ctl = CSR_READ_4(sc, BGE_MODE_CTL);
1008                         val = mode_ctl & ~BGE_MODECTL_PCIE_PORTS;
1009
1010                         /* Access the lower 1K of DL PCI-E block registers. */
1011                         CSR_WRITE_4(sc, BGE_MODE_CTL,
1012                             val | BGE_MODECTL_PCIE_DL_SEL);
1013
1014                         val = CSR_READ_4(sc, BGE_PCIE_DL_LO_FTSMAX);
1015                         val &= ~BGE_PCIE_DL_LO_FTSMAX_MASK;
1016                         val |= BGE_PCIE_DL_LO_FTSMAX_VAL;
1017                         CSR_WRITE_4(sc, BGE_PCIE_DL_LO_FTSMAX, val);
1018
1019                         CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl);
1020                 }
1021
1022                 val = CSR_READ_4(sc, BGE_CPMU_LSPD_10MB_CLK);
1023                 val &= ~BGE_CPMU_LSPD_10MB_MACCLK_MASK;
1024                 val |= BGE_CPMU_LSPD_10MB_MACCLK_6_25;
1025                 CSR_WRITE_4(sc, BGE_CPMU_LSPD_10MB_CLK, val);
1026         }
1027
1028         /*
1029          * Set up the PCI DMA control register.
1030          */
1031         dma_rw_ctl = pci_read_config(sc->bnx_dev, BGE_PCI_DMA_RW_CTL, 4);
1032         /*
1033          * Disable 32bytes cache alignment for DMA write to host memory
1034          *
1035          * NOTE:
1036          * 64bytes cache alignment for DMA write to host memory is still
1037          * enabled.
1038          */
1039         dma_rw_ctl |= BGE_PCIDMARWCTL_DIS_CACHE_ALIGNMENT;
1040         if (sc->bnx_chipid == BGE_CHIPID_BCM57765_A0)
1041                 dma_rw_ctl &= ~BGE_PCIDMARWCTL_CRDRDR_RDMA_MRRS_MSK;
1042         /*
1043          * Enable HW workaround for controllers that misinterpret
1044          * a status tag update and leave interrupts permanently
1045          * disabled.
1046          */
1047         if (sc->bnx_asicrev != BGE_ASICREV_BCM5717 &&
1048             sc->bnx_asicrev != BGE_ASICREV_BCM5762 &&
1049             !BNX_IS_57765_FAMILY(sc))
1050                 dma_rw_ctl |= BGE_PCIDMARWCTL_TAGGED_STATUS_WA;
1051         if (bootverbose) {
1052                 if_printf(&sc->arpcom.ac_if, "DMA read/write %#x\n",
1053                     dma_rw_ctl);
1054         }
1055         pci_write_config(sc->bnx_dev, BGE_PCI_DMA_RW_CTL, dma_rw_ctl, 4);
1056
1057         /*
1058          * Set up general mode register.
1059          */
1060         mode_ctl = bnx_dma_swap_options(sc) | BGE_MODECTL_MAC_ATTN_INTR |
1061             BGE_MODECTL_HOST_SEND_BDS | BGE_MODECTL_TX_NO_PHDR_CSUM;
1062         CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl);
1063
1064         /*
1065          * Disable memory write invalidate.  Apparently it is not supported
1066          * properly by these devices.  Also ensure that INTx isn't disabled,
1067          * as these chips need it even when using MSI.
1068          */
1069         PCI_CLRBIT(sc->bnx_dev, BGE_PCI_CMD,
1070             (PCIM_CMD_MWRICEN | PCIM_CMD_INTxDIS), 4);
1071
1072         /* Set the timer prescaler (always 66Mhz) */
1073         CSR_WRITE_4(sc, BGE_MISC_CFG, 65 << 1/*BGE_32BITTIME_66MHZ*/);
1074
1075         return(0);
1076 }
1077
1078 static int
1079 bnx_blockinit(struct bnx_softc *sc)
1080 {
1081         struct bnx_tx_ring *txr = &sc->bnx_tx_ring[0];
1082         struct bge_rcb *rcb;
1083         bus_size_t vrcb;
1084         bge_hostaddr taddr;
1085         uint32_t val;
1086         int i, limit;
1087
1088         /*
1089          * Initialize the memory window pointer register so that
1090          * we can access the first 32K of internal NIC RAM. This will
1091          * allow us to set up the TX send ring RCBs and the RX return
1092          * ring RCBs, plus other things which live in NIC memory.
1093          */
1094         CSR_WRITE_4(sc, BGE_PCI_MEMWIN_BASEADDR, 0);
1095
1096         /* Configure mbuf pool watermarks */
1097         if (BNX_IS_57765_PLUS(sc)) {
1098                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
1099                 if (sc->arpcom.ac_if.if_mtu > ETHERMTU) {
1100                         CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x7e);
1101                         CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0xea);
1102                 } else {
1103                         CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x2a);
1104                         CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0xa0);
1105                 }
1106         } else {
1107                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
1108                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10);
1109                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60);
1110         }
1111
1112         /* Configure DMA resource watermarks */
1113         CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5);
1114         CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10);
1115
1116         /* Enable buffer manager */
1117         val = BGE_BMANMODE_ENABLE | BGE_BMANMODE_LOMBUF_ATTN;
1118         /*
1119          * Change the arbitration algorithm of TXMBUF read request to
1120          * round-robin instead of priority based for BCM5719.  When
1121          * TXFIFO is almost empty, RDMA will hold its request until
1122          * TXFIFO is not almost empty.
1123          */
1124         if (sc->bnx_asicrev == BGE_ASICREV_BCM5719)
1125                 val |= BGE_BMANMODE_NO_TX_UNDERRUN;
1126         if (sc->bnx_asicrev == BGE_ASICREV_BCM5717 ||
1127             sc->bnx_chipid == BGE_CHIPID_BCM5719_A0 ||
1128             sc->bnx_chipid == BGE_CHIPID_BCM5720_A0)
1129                 val |= BGE_BMANMODE_LOMBUF_ATTN;
1130         CSR_WRITE_4(sc, BGE_BMAN_MODE, val);
1131
1132         /* Poll for buffer manager start indication */
1133         for (i = 0; i < BNX_TIMEOUT; i++) {
1134                 if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE)
1135                         break;
1136                 DELAY(10);
1137         }
1138
1139         if (i == BNX_TIMEOUT) {
1140                 if_printf(&sc->arpcom.ac_if,
1141                           "buffer manager failed to start\n");
1142                 return(ENXIO);
1143         }
1144
1145         /* Enable flow-through queues */
1146         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
1147         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
1148
1149         /* Wait until queue initialization is complete */
1150         for (i = 0; i < BNX_TIMEOUT; i++) {
1151                 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0)
1152                         break;
1153                 DELAY(10);
1154         }
1155
1156         if (i == BNX_TIMEOUT) {
1157                 if_printf(&sc->arpcom.ac_if,
1158                           "flow-through queue init failed\n");
1159                 return(ENXIO);
1160         }
1161
1162         /*
1163          * Summary of rings supported by the controller:
1164          *
1165          * Standard Receive Producer Ring
1166          * - This ring is used to feed receive buffers for "standard"
1167          *   sized frames (typically 1536 bytes) to the controller.
1168          *
1169          * Jumbo Receive Producer Ring
1170          * - This ring is used to feed receive buffers for jumbo sized
1171          *   frames (i.e. anything bigger than the "standard" frames)
1172          *   to the controller.
1173          *
1174          * Mini Receive Producer Ring
1175          * - This ring is used to feed receive buffers for "mini"
1176          *   sized frames to the controller.
1177          * - This feature required external memory for the controller
1178          *   but was never used in a production system.  Should always
1179          *   be disabled.
1180          *
1181          * Receive Return Ring
1182          * - After the controller has placed an incoming frame into a
1183          *   receive buffer that buffer is moved into a receive return
1184          *   ring.  The driver is then responsible to passing the
1185          *   buffer up to the stack.  Many versions of the controller
1186          *   support multiple RR rings.
1187          *
1188          * Send Ring
1189          * - This ring is used for outgoing frames.  Many versions of
1190          *   the controller support multiple send rings.
1191          */
1192
1193         /* Initialize the standard receive producer ring control block. */
1194         rcb = &sc->bnx_ldata.bnx_info.bnx_std_rx_rcb;
1195         rcb->bge_hostaddr.bge_addr_lo =
1196             BGE_ADDR_LO(sc->bnx_ldata.bnx_rx_std_ring_paddr);
1197         rcb->bge_hostaddr.bge_addr_hi =
1198             BGE_ADDR_HI(sc->bnx_ldata.bnx_rx_std_ring_paddr);
1199         if (BNX_IS_57765_PLUS(sc)) {
1200                 /*
1201                  * Bits 31-16: Programmable ring size (2048, 1024, 512, .., 32)
1202                  * Bits 15-2 : Maximum RX frame size
1203                  * Bit 1     : 1 = Ring Disabled, 0 = Ring ENabled
1204                  * Bit 0     : Reserved
1205                  */
1206                 rcb->bge_maxlen_flags =
1207                     BGE_RCB_MAXLEN_FLAGS(512, BNX_MAX_FRAMELEN << 2);
1208         } else {
1209                 /*
1210                  * Bits 31-16: Programmable ring size (512, 256, 128, 64, 32)
1211                  * Bits 15-2 : Reserved (should be 0)
1212                  * Bit 1     : 1 = Ring Disabled, 0 = Ring Enabled
1213                  * Bit 0     : Reserved
1214                  */
1215                 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0);
1216         }
1217         if (BNX_IS_5717_PLUS(sc))
1218                 rcb->bge_nicaddr = BGE_STD_RX_RINGS_5717;
1219         else
1220                 rcb->bge_nicaddr = BGE_STD_RX_RINGS;
1221         /* Write the standard receive producer ring control block. */
1222         CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi);
1223         CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo);
1224         CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
1225         CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr);
1226         /* Reset the standard receive producer ring producer index. */
1227         bnx_writembx(sc, BGE_MBX_RX_STD_PROD_LO, 0);
1228
1229         /*
1230          * Initialize the jumbo RX producer ring control
1231          * block.  We set the 'ring disabled' bit in the
1232          * flags field until we're actually ready to start
1233          * using this ring (i.e. once we set the MTU
1234          * high enough to require it).
1235          */
1236         if (BNX_IS_JUMBO_CAPABLE(sc)) {
1237                 rcb = &sc->bnx_ldata.bnx_info.bnx_jumbo_rx_rcb;
1238                 /* Get the jumbo receive producer ring RCB parameters. */
1239                 rcb->bge_hostaddr.bge_addr_lo =
1240                     BGE_ADDR_LO(sc->bnx_ldata.bnx_rx_jumbo_ring_paddr);
1241                 rcb->bge_hostaddr.bge_addr_hi =
1242                     BGE_ADDR_HI(sc->bnx_ldata.bnx_rx_jumbo_ring_paddr);
1243                 rcb->bge_maxlen_flags =
1244                     BGE_RCB_MAXLEN_FLAGS(BNX_MAX_FRAMELEN,
1245                     BGE_RCB_FLAG_RING_DISABLED);
1246                 if (BNX_IS_5717_PLUS(sc))
1247                         rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS_5717;
1248                 else
1249                         rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS;
1250                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI,
1251                     rcb->bge_hostaddr.bge_addr_hi);
1252                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO,
1253                     rcb->bge_hostaddr.bge_addr_lo);
1254                 /* Program the jumbo receive producer ring RCB parameters. */
1255                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS,
1256                     rcb->bge_maxlen_flags);
1257                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr);
1258                 /* Reset the jumbo receive producer ring producer index. */
1259                 bnx_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0);
1260         }
1261
1262         /*
1263          * The BD ring replenish thresholds control how often the
1264          * hardware fetches new BD's from the producer rings in host
1265          * memory.  Setting the value too low on a busy system can
1266          * starve the hardware and recue the throughpout.
1267          *
1268          * Set the BD ring replentish thresholds. The recommended
1269          * values are 1/8th the number of descriptors allocated to
1270          * each ring.
1271          */
1272         val = 8;
1273         CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, val);
1274         if (BNX_IS_JUMBO_CAPABLE(sc)) {
1275                 CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH,
1276                     BGE_JUMBO_RX_RING_CNT/8);
1277         }
1278         if (BNX_IS_57765_PLUS(sc)) {
1279                 CSR_WRITE_4(sc, BGE_STD_REPLENISH_LWM, 32);
1280                 CSR_WRITE_4(sc, BGE_JMB_REPLENISH_LWM, 16);
1281         }
1282
1283         /*
1284          * Disable all send rings by setting the 'ring disabled' bit
1285          * in the flags field of all the TX send ring control blocks,
1286          * located in NIC memory.
1287          */
1288         if (BNX_IS_5717_PLUS(sc))
1289                 limit = 4;
1290         else if (BNX_IS_57765_FAMILY(sc) ||
1291             sc->bnx_asicrev == BGE_ASICREV_BCM5762)
1292                 limit = 2;
1293         else
1294                 limit = 1;
1295         vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB;
1296         for (i = 0; i < limit; i++) {
1297                 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1298                     BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED));
1299                 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
1300                 vrcb += sizeof(struct bge_rcb);
1301         }
1302
1303         /* Configure send ring RCB 0 (we use only the first ring) */
1304         vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB;
1305         BGE_HOSTADDR(taddr, txr->bnx_tx_ring_paddr);
1306         RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi);
1307         RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo);
1308         if (BNX_IS_5717_PLUS(sc)) {
1309                 RCB_WRITE_4(sc, vrcb, bge_nicaddr, BGE_SEND_RING_5717);
1310         } else {
1311                 RCB_WRITE_4(sc, vrcb, bge_nicaddr,
1312                     BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT));
1313         }
1314         RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1315             BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0));
1316
1317         /*
1318          * Disable all receive return rings by setting the
1319          * 'ring disabled' bit in the flags field of all the receive
1320          * return ring control blocks, located in NIC memory.
1321          */
1322         if (BNX_IS_5717_PLUS(sc)) {
1323                 /* Should be 17, use 16 until we get an SRAM map. */
1324                 limit = 16;
1325         } else if (BNX_IS_57765_FAMILY(sc) ||
1326             sc->bnx_asicrev == BGE_ASICREV_BCM5762) {
1327                 limit = 4;
1328         } else {
1329                 limit = 1;
1330         }
1331         /* Disable all receive return rings. */
1332         vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB;
1333         for (i = 0; i < limit; i++) {
1334                 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, 0);
1335                 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, 0);
1336                 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1337                     BGE_RCB_FLAG_RING_DISABLED);
1338                 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
1339                 bnx_writembx(sc, BGE_MBX_RX_CONS0_LO +
1340                     (i * (sizeof(uint64_t))), 0);
1341                 vrcb += sizeof(struct bge_rcb);
1342         }
1343
1344         /*
1345          * Set up receive return ring 0.  Note that the NIC address
1346          * for RX return rings is 0x0.  The return rings live entirely
1347          * within the host, so the nicaddr field in the RCB isn't used.
1348          */
1349         vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB;
1350         BGE_HOSTADDR(taddr, sc->bnx_ldata.bnx_rx_return_ring_paddr);
1351         RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi);
1352         RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo);
1353         RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
1354         RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1355             BGE_RCB_MAXLEN_FLAGS(BNX_RETURN_RING_CNT, 0));
1356
1357         /* Set random backoff seed for TX */
1358         CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF,
1359             sc->arpcom.ac_enaddr[0] + sc->arpcom.ac_enaddr[1] +
1360             sc->arpcom.ac_enaddr[2] + sc->arpcom.ac_enaddr[3] +
1361             sc->arpcom.ac_enaddr[4] + sc->arpcom.ac_enaddr[5] +
1362             BGE_TX_BACKOFF_SEED_MASK);
1363
1364         /* Set inter-packet gap */
1365         val = 0x2620;
1366         if (sc->bnx_asicrev == BGE_ASICREV_BCM5720 ||
1367             sc->bnx_asicrev == BGE_ASICREV_BCM5762) {
1368                 val |= CSR_READ_4(sc, BGE_TX_LENGTHS) &
1369                     (BGE_TXLEN_JMB_FRM_LEN_MSK | BGE_TXLEN_CNT_DN_VAL_MSK);
1370         }
1371         CSR_WRITE_4(sc, BGE_TX_LENGTHS, val);
1372
1373         /*
1374          * Specify which ring to use for packets that don't match
1375          * any RX rules.
1376          */
1377         CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08);
1378
1379         /*
1380          * Configure number of RX lists. One interrupt distribution
1381          * list, sixteen active lists, one bad frames class.
1382          */
1383         CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181);
1384
1385         /* Inialize RX list placement stats mask. */
1386         CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF);
1387         CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1);
1388
1389         /* Disable host coalescing until we get it set up */
1390         CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000);
1391
1392         /* Poll to make sure it's shut down. */
1393         for (i = 0; i < BNX_TIMEOUT; i++) {
1394                 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE))
1395                         break;
1396                 DELAY(10);
1397         }
1398
1399         if (i == BNX_TIMEOUT) {
1400                 if_printf(&sc->arpcom.ac_if,
1401                           "host coalescing engine failed to idle\n");
1402                 return(ENXIO);
1403         }
1404
1405         /* Set up host coalescing defaults */
1406         CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bnx_rx_coal_ticks);
1407         CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bnx_tx_coal_ticks);
1408         CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bnx_rx_coal_bds);
1409         CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bnx_tx_coal_bds);
1410         CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, sc->bnx_rx_coal_bds_int);
1411         CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, sc->bnx_tx_coal_bds_int);
1412
1413         /* Set up address of status block */
1414         bzero(sc->bnx_ldata.bnx_status_block, BGE_STATUS_BLK_SZ);
1415         CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI,
1416             BGE_ADDR_HI(sc->bnx_ldata.bnx_status_block_paddr));
1417         CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO,
1418             BGE_ADDR_LO(sc->bnx_ldata.bnx_status_block_paddr));
1419
1420         /* Set up status block partail update size. */
1421         val = BGE_STATBLKSZ_32BYTE;
1422 #if 0
1423         /*
1424          * Does not seem to have visible effect in both
1425          * bulk data (1472B UDP datagram) and tiny data
1426          * (18B UDP datagram) TX tests.
1427          */
1428         val |= BGE_HCCMODE_CLRTICK_TX;
1429 #endif
1430         /* Turn on host coalescing state machine */
1431         CSR_WRITE_4(sc, BGE_HCC_MODE, val | BGE_HCCMODE_ENABLE);
1432
1433         /* Turn on RX BD completion state machine and enable attentions */
1434         CSR_WRITE_4(sc, BGE_RBDC_MODE,
1435             BGE_RBDCMODE_ENABLE|BGE_RBDCMODE_ATTN);
1436
1437         /* Turn on RX list placement state machine */
1438         CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
1439
1440         val = BGE_MACMODE_TXDMA_ENB | BGE_MACMODE_RXDMA_ENB |
1441             BGE_MACMODE_RX_STATS_CLEAR | BGE_MACMODE_TX_STATS_CLEAR |
1442             BGE_MACMODE_RX_STATS_ENB | BGE_MACMODE_TX_STATS_ENB |
1443             BGE_MACMODE_FRMHDR_DMA_ENB;
1444
1445         if (sc->bnx_flags & BNX_FLAG_TBI)
1446                 val |= BGE_PORTMODE_TBI;
1447         else if (sc->bnx_flags & BNX_FLAG_MII_SERDES)
1448                 val |= BGE_PORTMODE_GMII;
1449         else
1450                 val |= BGE_PORTMODE_MII;
1451
1452         /* Turn on DMA, clear stats */
1453         CSR_WRITE_4(sc, BGE_MAC_MODE, val);
1454
1455         /* Set misc. local control, enable interrupts on attentions */
1456         CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN);
1457
1458 #ifdef notdef
1459         /* Assert GPIO pins for PHY reset */
1460         BNX_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0|
1461             BGE_MLC_MISCIO_OUT1|BGE_MLC_MISCIO_OUT2);
1462         BNX_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0|
1463             BGE_MLC_MISCIO_OUTEN1|BGE_MLC_MISCIO_OUTEN2);
1464 #endif
1465
1466         /* Turn on write DMA state machine */
1467         val = BGE_WDMAMODE_ENABLE|BGE_WDMAMODE_ALL_ATTNS;
1468         /* Enable host coalescing bug fix. */
1469         val |= BGE_WDMAMODE_STATUS_TAG_FIX;
1470         if (sc->bnx_asicrev == BGE_ASICREV_BCM5785) {
1471                 /* Request larger DMA burst size to get better performance. */
1472                 val |= BGE_WDMAMODE_BURST_ALL_DATA;
1473         }
1474         CSR_WRITE_4(sc, BGE_WDMA_MODE, val);
1475         DELAY(40);
1476
1477         if (BNX_IS_57765_PLUS(sc)) {
1478                 uint32_t dmactl, dmactl_reg;
1479
1480                 if (sc->bnx_asicrev == BGE_ASICREV_BCM5762)
1481                         dmactl_reg = BGE_RDMA_RSRVCTRL2;
1482                 else
1483                         dmactl_reg = BGE_RDMA_RSRVCTRL;
1484
1485                 dmactl = CSR_READ_4(sc, dmactl_reg);
1486                 /*
1487                  * Adjust tx margin to prevent TX data corruption and
1488                  * fix internal FIFO overflow.
1489                  */
1490                 if (sc->bnx_asicrev == BGE_ASICREV_BCM5719 ||
1491                     sc->bnx_asicrev == BGE_ASICREV_BCM5720 ||
1492                     sc->bnx_asicrev == BGE_ASICREV_BCM5762) {
1493                         dmactl &= ~(BGE_RDMA_RSRVCTRL_FIFO_LWM_MASK |
1494                             BGE_RDMA_RSRVCTRL_FIFO_HWM_MASK |
1495                             BGE_RDMA_RSRVCTRL_TXMRGN_MASK);
1496                         dmactl |= BGE_RDMA_RSRVCTRL_FIFO_LWM_1_5K |
1497                             BGE_RDMA_RSRVCTRL_FIFO_HWM_1_5K |
1498                             BGE_RDMA_RSRVCTRL_TXMRGN_320B;
1499                 }
1500                 /*
1501                  * Enable fix for read DMA FIFO overruns.
1502                  * The fix is to limit the number of RX BDs
1503                  * the hardware would fetch at a fime.
1504                  */
1505                 CSR_WRITE_4(sc, dmactl_reg,
1506                     dmactl | BGE_RDMA_RSRVCTRL_FIFO_OFLW_FIX);
1507         }
1508
1509         if (sc->bnx_asicrev == BGE_ASICREV_BCM5719) {
1510                 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL,
1511                     CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL) |
1512                     BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_4K |
1513                     BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K);
1514         } else if (sc->bnx_asicrev == BGE_ASICREV_BCM5720 ||
1515             sc->bnx_asicrev == BGE_ASICREV_BCM5762) {
1516                 uint32_t ctrl_reg;
1517
1518                 if (sc->bnx_asicrev == BGE_ASICREV_BCM5762)
1519                         ctrl_reg = BGE_RDMA_LSO_CRPTEN_CTRL2;
1520                 else
1521                         ctrl_reg = BGE_RDMA_LSO_CRPTEN_CTRL;
1522
1523                 /*
1524                  * Allow 4KB burst length reads for non-LSO frames.
1525                  * Enable 512B burst length reads for buffer descriptors.
1526                  */
1527                 CSR_WRITE_4(sc, ctrl_reg,
1528                     CSR_READ_4(sc, ctrl_reg) |
1529                     BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_512 |
1530                     BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K);
1531         }
1532
1533         /* Turn on read DMA state machine */
1534         val = BGE_RDMAMODE_ENABLE | BGE_RDMAMODE_ALL_ATTNS;
1535         if (sc->bnx_asicrev == BGE_ASICREV_BCM5717)
1536                 val |= BGE_RDMAMODE_MULT_DMA_RD_DIS;
1537         if (sc->bnx_asicrev == BGE_ASICREV_BCM5784 ||
1538             sc->bnx_asicrev == BGE_ASICREV_BCM5785 ||
1539             sc->bnx_asicrev == BGE_ASICREV_BCM57780) {
1540                 val |= BGE_RDMAMODE_BD_SBD_CRPT_ATTN |
1541                     BGE_RDMAMODE_MBUF_RBD_CRPT_ATTN |
1542                     BGE_RDMAMODE_MBUF_SBD_CRPT_ATTN;
1543         }
1544         if (sc->bnx_asicrev == BGE_ASICREV_BCM5720 ||
1545             sc->bnx_asicrev == BGE_ASICREV_BCM5762) {
1546                 val |= CSR_READ_4(sc, BGE_RDMA_MODE) &
1547                     BGE_RDMAMODE_H2BNC_VLAN_DET;
1548                 /*
1549                  * Allow multiple outstanding read requests from
1550                  * non-LSO read DMA engine.
1551                  */
1552                 val &= ~BGE_RDMAMODE_MULT_DMA_RD_DIS;
1553         }
1554         if (sc->bnx_asicrev == BGE_ASICREV_BCM57766)
1555                 val |= BGE_RDMAMODE_JMB_2K_MMRR;
1556         if (sc->bnx_flags & BNX_FLAG_TSO)
1557                 val |= BGE_RDMAMODE_TSO4_ENABLE;
1558         val |= BGE_RDMAMODE_FIFO_LONG_BURST;
1559         CSR_WRITE_4(sc, BGE_RDMA_MODE, val);
1560         DELAY(40);
1561
1562         /* Turn on RX data completion state machine */
1563         CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
1564
1565         /* Turn on RX BD initiator state machine */
1566         CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
1567
1568         /* Turn on RX data and RX BD initiator state machine */
1569         CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE);
1570
1571         /* Turn on send BD completion state machine */
1572         CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
1573
1574         /* Turn on send data completion state machine */
1575         val = BGE_SDCMODE_ENABLE;
1576         if (sc->bnx_asicrev == BGE_ASICREV_BCM5761)
1577                 val |= BGE_SDCMODE_CDELAY; 
1578         CSR_WRITE_4(sc, BGE_SDC_MODE, val);
1579
1580         /* Turn on send data initiator state machine */
1581         if (sc->bnx_flags & BNX_FLAG_TSO) {
1582                 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE |
1583                     BGE_SDIMODE_HW_LSO_PRE_DMA);
1584         } else {
1585                 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
1586         }
1587
1588         /* Turn on send BD initiator state machine */
1589         CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
1590
1591         /* Turn on send BD selector state machine */
1592         CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
1593
1594         CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF);
1595         CSR_WRITE_4(sc, BGE_SDI_STATS_CTL,
1596             BGE_SDISTATSCTL_ENABLE|BGE_SDISTATSCTL_FASTER);
1597
1598         /* ack/clear link change events */
1599         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED|
1600             BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE|
1601             BGE_MACSTAT_LINK_CHANGED);
1602         CSR_WRITE_4(sc, BGE_MI_STS, 0);
1603
1604         /*
1605          * Enable attention when the link has changed state for
1606          * devices that use auto polling.
1607          */
1608         if (sc->bnx_flags & BNX_FLAG_TBI) {
1609                 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK);
1610         } else {
1611                 if (sc->bnx_mi_mode & BGE_MIMODE_AUTOPOLL) {
1612                         CSR_WRITE_4(sc, BGE_MI_MODE, sc->bnx_mi_mode);
1613                         DELAY(80);
1614                 }
1615         }
1616
1617         /*
1618          * Clear any pending link state attention.
1619          * Otherwise some link state change events may be lost until attention
1620          * is cleared by bnx_intr() -> bnx_softc.bnx_link_upd() sequence.
1621          * It's not necessary on newer BCM chips - perhaps enabling link
1622          * state change attentions implies clearing pending attention.
1623          */
1624         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED|
1625             BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE|
1626             BGE_MACSTAT_LINK_CHANGED);
1627
1628         /* Enable link state change attentions. */
1629         BNX_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED);
1630
1631         return(0);
1632 }
1633
1634 /*
1635  * Probe for a Broadcom chip. Check the PCI vendor and device IDs
1636  * against our list and return its name if we find a match. Note
1637  * that since the Broadcom controller contains VPD support, we
1638  * can get the device name string from the controller itself instead
1639  * of the compiled-in string. This is a little slow, but it guarantees
1640  * we'll always announce the right product name.
1641  */
1642 static int
1643 bnx_probe(device_t dev)
1644 {
1645         const struct bnx_type *t;
1646         uint16_t product, vendor;
1647
1648         if (!pci_is_pcie(dev))
1649                 return ENXIO;
1650
1651         product = pci_get_device(dev);
1652         vendor = pci_get_vendor(dev);
1653
1654         for (t = bnx_devs; t->bnx_name != NULL; t++) {
1655                 if (vendor == t->bnx_vid && product == t->bnx_did)
1656                         break;
1657         }
1658         if (t->bnx_name == NULL)
1659                 return ENXIO;
1660
1661         device_set_desc(dev, t->bnx_name);
1662         return 0;
1663 }
1664
1665 static int
1666 bnx_attach(device_t dev)
1667 {
1668         struct ifnet *ifp;
1669         struct bnx_softc *sc;
1670         uint32_t hwcfg = 0;
1671         int error = 0, rid, capmask;
1672         uint8_t ether_addr[ETHER_ADDR_LEN];
1673         uint16_t product;
1674         driver_intr_t *intr_func;
1675         uintptr_t mii_priv = 0;
1676         u_int intr_flags;
1677 #ifdef BNX_TSO_DEBUG
1678         char desc[32];
1679         int i;
1680 #endif
1681
1682         sc = device_get_softc(dev);
1683         sc->bnx_dev = dev;
1684         callout_init_mp(&sc->bnx_stat_timer);
1685         callout_init_mp(&sc->bnx_intr_timer);
1686         lwkt_serialize_init(&sc->bnx_jslot_serializer);
1687
1688         product = pci_get_device(dev);
1689
1690 #ifndef BURN_BRIDGES
1691         if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
1692                 uint32_t irq, mem;
1693
1694                 irq = pci_read_config(dev, PCIR_INTLINE, 4);
1695                 mem = pci_read_config(dev, BGE_PCI_BAR0, 4);
1696
1697                 device_printf(dev, "chip is in D%d power mode "
1698                     "-- setting to D0\n", pci_get_powerstate(dev));
1699
1700                 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
1701
1702                 pci_write_config(dev, PCIR_INTLINE, irq, 4);
1703                 pci_write_config(dev, BGE_PCI_BAR0, mem, 4);
1704         }
1705 #endif  /* !BURN_BRIDGE */
1706
1707         /*
1708          * Map control/status registers.
1709          */
1710         pci_enable_busmaster(dev);
1711
1712         rid = BGE_PCI_BAR0;
1713         sc->bnx_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
1714             RF_ACTIVE);
1715
1716         if (sc->bnx_res == NULL) {
1717                 device_printf(dev, "couldn't map memory\n");
1718                 return ENXIO;
1719         }
1720
1721         sc->bnx_btag = rman_get_bustag(sc->bnx_res);
1722         sc->bnx_bhandle = rman_get_bushandle(sc->bnx_res);
1723
1724         /* Save various chip information */
1725         sc->bnx_chipid =
1726             pci_read_config(dev, BGE_PCI_MISC_CTL, 4) >>
1727             BGE_PCIMISCCTL_ASICREV_SHIFT;
1728         if (BGE_ASICREV(sc->bnx_chipid) == BGE_ASICREV_USE_PRODID_REG) {
1729                 /* All chips having dedicated ASICREV register have CPMU */
1730                 sc->bnx_flags |= BNX_FLAG_CPMU;
1731
1732                 switch (product) {
1733                 case PCI_PRODUCT_BROADCOM_BCM5717:
1734                 case PCI_PRODUCT_BROADCOM_BCM5717C:
1735                 case PCI_PRODUCT_BROADCOM_BCM5718:
1736                 case PCI_PRODUCT_BROADCOM_BCM5719:
1737                 case PCI_PRODUCT_BROADCOM_BCM5720_ALT:
1738                 case PCI_PRODUCT_BROADCOM_BCM5725:
1739                 case PCI_PRODUCT_BROADCOM_BCM5727:
1740                 case PCI_PRODUCT_BROADCOM_BCM5762:
1741                         sc->bnx_chipid = pci_read_config(dev,
1742                             BGE_PCI_GEN2_PRODID_ASICREV, 4);
1743                         break;
1744
1745                 case PCI_PRODUCT_BROADCOM_BCM57761:
1746                 case PCI_PRODUCT_BROADCOM_BCM57762:
1747                 case PCI_PRODUCT_BROADCOM_BCM57765:
1748                 case PCI_PRODUCT_BROADCOM_BCM57766:
1749                 case PCI_PRODUCT_BROADCOM_BCM57781:
1750                 case PCI_PRODUCT_BROADCOM_BCM57782:
1751                 case PCI_PRODUCT_BROADCOM_BCM57785:
1752                 case PCI_PRODUCT_BROADCOM_BCM57786:
1753                 case PCI_PRODUCT_BROADCOM_BCM57791:
1754                 case PCI_PRODUCT_BROADCOM_BCM57795:
1755                         sc->bnx_chipid = pci_read_config(dev,
1756                             BGE_PCI_GEN15_PRODID_ASICREV, 4);
1757                         break;
1758
1759                 default:
1760                         sc->bnx_chipid = pci_read_config(dev,
1761                             BGE_PCI_PRODID_ASICREV, 4);
1762                         break;
1763                 }
1764         }
1765         if (sc->bnx_chipid == BGE_CHIPID_BCM5717_C0)
1766                 sc->bnx_chipid = BGE_CHIPID_BCM5720_A0;
1767
1768         sc->bnx_asicrev = BGE_ASICREV(sc->bnx_chipid);
1769         sc->bnx_chiprev = BGE_CHIPREV(sc->bnx_chipid);
1770
1771         switch (sc->bnx_asicrev) {
1772         case BGE_ASICREV_BCM5717:
1773         case BGE_ASICREV_BCM5719:
1774         case BGE_ASICREV_BCM5720:
1775                 sc->bnx_flags |= BNX_FLAG_5717_PLUS | BNX_FLAG_57765_PLUS;
1776                 break;
1777
1778         case BGE_ASICREV_BCM5762:
1779                 sc->bnx_flags |= BNX_FLAG_57765_PLUS;
1780                 break;
1781
1782         case BGE_ASICREV_BCM57765:
1783         case BGE_ASICREV_BCM57766:
1784                 sc->bnx_flags |= BNX_FLAG_57765_FAMILY | BNX_FLAG_57765_PLUS;
1785                 break;
1786         }
1787
1788         sc->bnx_flags |= BNX_FLAG_TSO;
1789         if (sc->bnx_asicrev == BGE_ASICREV_BCM5719 &&
1790             sc->bnx_chipid == BGE_CHIPID_BCM5719_A0)
1791                 sc->bnx_flags &= ~BNX_FLAG_TSO;
1792
1793         if (sc->bnx_asicrev == BGE_ASICREV_BCM5717 ||
1794             BNX_IS_57765_FAMILY(sc)) {
1795                 /*
1796                  * All BCM57785 and BCM5718 families chips have a bug that
1797                  * under certain situation interrupt will not be enabled
1798                  * even if status tag is written to BGE_MBX_IRQ0_LO mailbox.
1799                  *
1800                  * While BCM5719 and BCM5720 have a hardware workaround
1801                  * which could fix the above bug.
1802                  * See the comment near BGE_PCIDMARWCTL_TAGGED_STATUS_WA in
1803                  * bnx_chipinit().
1804                  *
1805                  * For the rest of the chips in these two families, we will
1806                  * have to poll the status block at high rate (10ms currently)
1807                  * to check whether the interrupt is hosed or not.
1808                  * See bnx_intr_check() for details.
1809                  */
1810                 sc->bnx_flags |= BNX_FLAG_STATUSTAG_BUG;
1811         }
1812
1813         sc->bnx_pciecap = pci_get_pciecap_ptr(sc->bnx_dev);
1814         if (sc->bnx_asicrev == BGE_ASICREV_BCM5719 ||
1815             sc->bnx_asicrev == BGE_ASICREV_BCM5720)
1816                 pcie_set_max_readrq(dev, PCIEM_DEVCTL_MAX_READRQ_2048);
1817         else
1818                 pcie_set_max_readrq(dev, PCIEM_DEVCTL_MAX_READRQ_4096);
1819         device_printf(dev, "CHIP ID 0x%08x; "
1820                       "ASIC REV 0x%02x; CHIP REV 0x%02x\n",
1821                       sc->bnx_chipid, sc->bnx_asicrev, sc->bnx_chiprev);
1822
1823         /*
1824          * Set various PHY quirk flags.
1825          */
1826
1827         capmask = MII_CAPMASK_DEFAULT;
1828         if (product == PCI_PRODUCT_BROADCOM_BCM57791 ||
1829             product == PCI_PRODUCT_BROADCOM_BCM57795) {
1830                 /* 10/100 only */
1831                 capmask &= ~BMSR_EXTSTAT;
1832         }
1833
1834         mii_priv |= BRGPHY_FLAG_WIRESPEED;
1835         if (sc->bnx_chipid == BGE_CHIPID_BCM5762_A0)
1836                 mii_priv |= BRGPHY_FLAG_5762_A0;
1837
1838         /* Initialize if_name earlier, so if_printf could be used */
1839         ifp = &sc->arpcom.ac_if;
1840         if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1841
1842         /* Try to reset the chip. */
1843         bnx_reset(sc);
1844
1845         if (bnx_chipinit(sc)) {
1846                 device_printf(dev, "chip initialization failed\n");
1847                 error = ENXIO;
1848                 goto fail;
1849         }
1850
1851         /*
1852          * Get station address
1853          */
1854         error = bnx_get_eaddr(sc, ether_addr);
1855         if (error) {
1856                 device_printf(dev, "failed to read station address\n");
1857                 goto fail;
1858         }
1859
1860         /* XXX */
1861         sc->bnx_tx_ringcnt = 1;
1862
1863         error = bnx_dma_alloc(sc);
1864         if (error)
1865                 goto fail;
1866
1867         /*
1868          * Allocate interrupt
1869          */
1870         sc->bnx_irq_type = pci_alloc_1intr(dev, bnx_msi_enable, &sc->bnx_irq_rid,
1871             &intr_flags);
1872
1873         sc->bnx_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->bnx_irq_rid,
1874             intr_flags);
1875         if (sc->bnx_irq == NULL) {
1876                 device_printf(dev, "couldn't map interrupt\n");
1877                 error = ENXIO;
1878                 goto fail;
1879         }
1880
1881         if (sc->bnx_irq_type == PCI_INTR_TYPE_MSI) {
1882                 sc->bnx_flags |= BNX_FLAG_ONESHOT_MSI;
1883                 bnx_enable_msi(sc);
1884         }
1885
1886         /* Set default tuneable values. */
1887         sc->bnx_rx_coal_ticks = BNX_RX_COAL_TICKS_DEF;
1888         sc->bnx_tx_coal_ticks = BNX_TX_COAL_TICKS_DEF;
1889         sc->bnx_rx_coal_bds = BNX_RX_COAL_BDS_DEF;
1890         sc->bnx_tx_coal_bds = BNX_TX_COAL_BDS_DEF;
1891         sc->bnx_rx_coal_bds_int = BNX_RX_COAL_BDS_INT_DEF;
1892         sc->bnx_tx_coal_bds_int = BNX_TX_COAL_BDS_INT_DEF;
1893
1894         /* Set up ifnet structure */
1895         ifp->if_softc = sc;
1896         ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1897         ifp->if_ioctl = bnx_ioctl;
1898         ifp->if_start = bnx_start;
1899 #ifdef IFPOLL_ENABLE
1900         ifp->if_npoll = bnx_npoll;
1901 #endif
1902         ifp->if_watchdog = bnx_watchdog;
1903         ifp->if_init = bnx_init;
1904         ifp->if_mtu = ETHERMTU;
1905         ifp->if_capabilities = IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU;
1906         ifq_set_maxlen(&ifp->if_snd, BGE_TX_RING_CNT - 1);
1907         ifq_set_ready(&ifp->if_snd);
1908
1909         ifp->if_capabilities |= IFCAP_HWCSUM;
1910         ifp->if_hwassist = BNX_CSUM_FEATURES;
1911         if (sc->bnx_flags & BNX_FLAG_TSO) {
1912                 ifp->if_capabilities |= IFCAP_TSO;
1913                 ifp->if_hwassist |= CSUM_TSO;
1914         }
1915         ifp->if_capenable = ifp->if_capabilities;
1916
1917         /*
1918          * Figure out what sort of media we have by checking the
1919          * hardware config word in the first 32k of NIC internal memory,
1920          * or fall back to examining the EEPROM if necessary.
1921          * Note: on some BCM5700 cards, this value appears to be unset.
1922          * If that's the case, we have to rely on identifying the NIC
1923          * by its PCI subsystem ID, as we do below for the SysKonnect
1924          * SK-9D41.
1925          */
1926         if (bnx_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_SIG) == BGE_MAGIC_NUMBER) {
1927                 hwcfg = bnx_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_NICCFG);
1928         } else {
1929                 if (bnx_read_eeprom(sc, (caddr_t)&hwcfg, BGE_EE_HWCFG_OFFSET,
1930                                     sizeof(hwcfg))) {
1931                         device_printf(dev, "failed to read EEPROM\n");
1932                         error = ENXIO;
1933                         goto fail;
1934                 }
1935                 hwcfg = ntohl(hwcfg);
1936         }
1937
1938         /* The SysKonnect SK-9D41 is a 1000baseSX card. */
1939         if (pci_get_subvendor(dev) == PCI_PRODUCT_SCHNEIDERKOCH_SK_9D41 ||
1940             (hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER)
1941                 sc->bnx_flags |= BNX_FLAG_TBI;
1942
1943         /* Setup MI MODE */
1944         if (sc->bnx_flags & BNX_FLAG_CPMU)
1945                 sc->bnx_mi_mode = BGE_MIMODE_500KHZ_CONST;
1946         else
1947                 sc->bnx_mi_mode = BGE_MIMODE_BASE;
1948
1949         /* Setup link status update stuffs */
1950         if (sc->bnx_flags & BNX_FLAG_TBI) {
1951                 sc->bnx_link_upd = bnx_tbi_link_upd;
1952                 sc->bnx_link_chg = BGE_MACSTAT_LINK_CHANGED;
1953         } else if (sc->bnx_mi_mode & BGE_MIMODE_AUTOPOLL) {
1954                 sc->bnx_link_upd = bnx_autopoll_link_upd;
1955                 sc->bnx_link_chg = BGE_MACSTAT_LINK_CHANGED;
1956         } else {
1957                 sc->bnx_link_upd = bnx_copper_link_upd;
1958                 sc->bnx_link_chg = BGE_MACSTAT_LINK_CHANGED;
1959         }
1960
1961         /* Set default PHY address */
1962         sc->bnx_phyno = 1;
1963
1964         /*
1965          * PHY address mapping for various devices.
1966          *
1967          *          | F0 Cu | F0 Sr | F1 Cu | F1 Sr |
1968          * ---------+-------+-------+-------+-------+
1969          * BCM57XX  |   1   |   X   |   X   |   X   |
1970          * BCM5704  |   1   |   X   |   1   |   X   |
1971          * BCM5717  |   1   |   8   |   2   |   9   |
1972          * BCM5719  |   1   |   8   |   2   |   9   |
1973          * BCM5720  |   1   |   8   |   2   |   9   |
1974          *
1975          * Other addresses may respond but they are not
1976          * IEEE compliant PHYs and should be ignored.
1977          */
1978         if (BNX_IS_5717_PLUS(sc)) {
1979                 int f;
1980
1981                 f = pci_get_function(dev);
1982                 if (sc->bnx_chipid == BGE_CHIPID_BCM5717_A0) {
1983                         if (CSR_READ_4(sc, BGE_SGDIG_STS) &
1984                             BGE_SGDIGSTS_IS_SERDES)
1985                                 sc->bnx_phyno = f + 8;
1986                         else
1987                                 sc->bnx_phyno = f + 1;
1988                 } else {
1989                         if (CSR_READ_4(sc, BGE_CPMU_PHY_STRAP) &
1990                             BGE_CPMU_PHY_STRAP_IS_SERDES)
1991                                 sc->bnx_phyno = f + 8;
1992                         else
1993                                 sc->bnx_phyno = f + 1;
1994                 }
1995         }
1996
1997         if (sc->bnx_flags & BNX_FLAG_TBI) {
1998                 ifmedia_init(&sc->bnx_ifmedia, IFM_IMASK,
1999                     bnx_ifmedia_upd, bnx_ifmedia_sts);
2000                 ifmedia_add(&sc->bnx_ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL);
2001                 ifmedia_add(&sc->bnx_ifmedia,
2002                     IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL);
2003                 ifmedia_add(&sc->bnx_ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL);
2004                 ifmedia_set(&sc->bnx_ifmedia, IFM_ETHER|IFM_AUTO);
2005                 sc->bnx_ifmedia.ifm_media = sc->bnx_ifmedia.ifm_cur->ifm_media;
2006         } else {
2007                 struct mii_probe_args mii_args;
2008
2009                 mii_probe_args_init(&mii_args, bnx_ifmedia_upd, bnx_ifmedia_sts);
2010                 mii_args.mii_probemask = 1 << sc->bnx_phyno;
2011                 mii_args.mii_capmask = capmask;
2012                 mii_args.mii_privtag = MII_PRIVTAG_BRGPHY;
2013                 mii_args.mii_priv = mii_priv;
2014
2015                 error = mii_probe(dev, &sc->bnx_miibus, &mii_args);
2016                 if (error) {
2017                         device_printf(dev, "MII without any PHY!\n");
2018                         goto fail;
2019                 }
2020         }
2021
2022         /*
2023          * Create sysctl nodes.
2024          */
2025         sysctl_ctx_init(&sc->bnx_sysctl_ctx);
2026         sc->bnx_sysctl_tree = SYSCTL_ADD_NODE(&sc->bnx_sysctl_ctx,
2027                                               SYSCTL_STATIC_CHILDREN(_hw),
2028                                               OID_AUTO,
2029                                               device_get_nameunit(dev),
2030                                               CTLFLAG_RD, 0, "");
2031         if (sc->bnx_sysctl_tree == NULL) {
2032                 device_printf(dev, "can't add sysctl node\n");
2033                 error = ENXIO;
2034                 goto fail;
2035         }
2036
2037         SYSCTL_ADD_PROC(&sc->bnx_sysctl_ctx,
2038                         SYSCTL_CHILDREN(sc->bnx_sysctl_tree),
2039                         OID_AUTO, "rx_coal_ticks",
2040                         CTLTYPE_INT | CTLFLAG_RW,
2041                         sc, 0, bnx_sysctl_rx_coal_ticks, "I",
2042                         "Receive coalescing ticks (usec).");
2043         SYSCTL_ADD_PROC(&sc->bnx_sysctl_ctx,
2044                         SYSCTL_CHILDREN(sc->bnx_sysctl_tree),
2045                         OID_AUTO, "tx_coal_ticks",
2046                         CTLTYPE_INT | CTLFLAG_RW,
2047                         sc, 0, bnx_sysctl_tx_coal_ticks, "I",
2048                         "Transmit coalescing ticks (usec).");
2049         SYSCTL_ADD_PROC(&sc->bnx_sysctl_ctx,
2050                         SYSCTL_CHILDREN(sc->bnx_sysctl_tree),
2051                         OID_AUTO, "rx_coal_bds",
2052                         CTLTYPE_INT | CTLFLAG_RW,
2053                         sc, 0, bnx_sysctl_rx_coal_bds, "I",
2054                         "Receive max coalesced BD count.");
2055         SYSCTL_ADD_PROC(&sc->bnx_sysctl_ctx,
2056                         SYSCTL_CHILDREN(sc->bnx_sysctl_tree),
2057                         OID_AUTO, "tx_coal_bds",
2058                         CTLTYPE_INT | CTLFLAG_RW,
2059                         sc, 0, bnx_sysctl_tx_coal_bds, "I",
2060                         "Transmit max coalesced BD count.");
2061         /*
2062          * A common design characteristic for many Broadcom
2063          * client controllers is that they only support a
2064          * single outstanding DMA read operation on the PCIe
2065          * bus. This means that it will take twice as long to
2066          * fetch a TX frame that is split into header and
2067          * payload buffers as it does to fetch a single,
2068          * contiguous TX frame (2 reads vs. 1 read). For these
2069          * controllers, coalescing buffers to reduce the number
2070          * of memory reads is effective way to get maximum
2071          * performance(about 940Mbps).  Without collapsing TX
2072          * buffers the maximum TCP bulk transfer performance
2073          * is about 850Mbps. However forcing coalescing mbufs
2074          * consumes a lot of CPU cycles, so leave it off by
2075          * default.
2076          */
2077         SYSCTL_ADD_PROC(&sc->bnx_sysctl_ctx,
2078             SYSCTL_CHILDREN(sc->bnx_sysctl_tree), OID_AUTO,
2079             "force_defrag", CTLTYPE_INT | CTLFLAG_RW,
2080             sc, 0, bnx_sysctl_force_defrag, "I",
2081             "Force defragment on TX path");
2082
2083         SYSCTL_ADD_PROC(&sc->bnx_sysctl_ctx,
2084             SYSCTL_CHILDREN(sc->bnx_sysctl_tree), OID_AUTO,
2085             "tx_wreg", CTLTYPE_INT | CTLFLAG_RW,
2086             sc, 0, bnx_sysctl_tx_wreg, "I",
2087             "# of segments before writing to hardware register");
2088
2089         SYSCTL_ADD_PROC(&sc->bnx_sysctl_ctx,
2090             SYSCTL_CHILDREN(sc->bnx_sysctl_tree), OID_AUTO,
2091             "rx_coal_bds_int", CTLTYPE_INT | CTLFLAG_RW,
2092             sc, 0, bnx_sysctl_rx_coal_bds_int, "I",
2093             "Receive max coalesced BD count during interrupt.");
2094         SYSCTL_ADD_PROC(&sc->bnx_sysctl_ctx,
2095             SYSCTL_CHILDREN(sc->bnx_sysctl_tree), OID_AUTO,
2096             "tx_coal_bds_int", CTLTYPE_INT | CTLFLAG_RW,
2097             sc, 0, bnx_sysctl_tx_coal_bds_int, "I",
2098             "Transmit max coalesced BD count during interrupt.");
2099
2100 #ifdef BNX_TSO_DEBUG
2101         for (i = 0; i < BNX_TSO_NSTATS; ++i) {
2102                 ksnprintf(desc, sizeof(desc), "tso%d", i + 1);
2103                 SYSCTL_ADD_ULONG(&sc->bnx_sysctl_ctx,
2104                     SYSCTL_CHILDREN(sc->bnx_sysctl_tree), OID_AUTO,
2105                     desc, CTLFLAG_RW, &sc->bnx_tsosegs[i], "");
2106         }
2107 #endif
2108
2109         /*
2110          * Call MI attach routine.
2111          */
2112         ether_ifattach(ifp, ether_addr, NULL);
2113
2114         ifq_set_cpuid(&ifp->if_snd, sc->bnx_intr_cpuid);
2115
2116 #ifdef IFPOLL_ENABLE
2117         ifpoll_compat_setup(&sc->bnx_npoll,
2118             &sc->bnx_sysctl_ctx, sc->bnx_sysctl_tree,
2119             device_get_unit(dev), ifp->if_serializer);
2120 #endif
2121
2122         if (sc->bnx_irq_type == PCI_INTR_TYPE_MSI) {
2123                 if (sc->bnx_flags & BNX_FLAG_ONESHOT_MSI) {
2124                         intr_func = bnx_msi_oneshot;
2125                         if (bootverbose)
2126                                 device_printf(dev, "oneshot MSI\n");
2127                 } else {
2128                         intr_func = bnx_msi;
2129                 }
2130         } else {
2131                 intr_func = bnx_intr_legacy;
2132         }
2133         error = bus_setup_intr(dev, sc->bnx_irq, INTR_MPSAFE, intr_func, sc,
2134             &sc->bnx_intrhand, ifp->if_serializer);
2135         if (error) {
2136                 ether_ifdetach(ifp);
2137                 device_printf(dev, "couldn't set up irq\n");
2138                 goto fail;
2139         }
2140
2141         sc->bnx_intr_cpuid = rman_get_cpuid(sc->bnx_irq);
2142         sc->bnx_stat_cpuid = sc->bnx_intr_cpuid;
2143
2144         return(0);
2145 fail:
2146         bnx_detach(dev);
2147         return(error);
2148 }
2149
2150 static int
2151 bnx_detach(device_t dev)
2152 {
2153         struct bnx_softc *sc = device_get_softc(dev);
2154
2155         if (device_is_attached(dev)) {
2156                 struct ifnet *ifp = &sc->arpcom.ac_if;
2157
2158                 lwkt_serialize_enter(ifp->if_serializer);
2159                 bnx_stop(sc);
2160                 bnx_reset(sc);
2161                 bus_teardown_intr(dev, sc->bnx_irq, sc->bnx_intrhand);
2162                 lwkt_serialize_exit(ifp->if_serializer);
2163
2164                 ether_ifdetach(ifp);
2165         }
2166
2167         if (sc->bnx_flags & BNX_FLAG_TBI)
2168                 ifmedia_removeall(&sc->bnx_ifmedia);
2169         if (sc->bnx_miibus)
2170                 device_delete_child(dev, sc->bnx_miibus);
2171         bus_generic_detach(dev);
2172
2173         if (sc->bnx_irq != NULL) {
2174                 bus_release_resource(dev, SYS_RES_IRQ, sc->bnx_irq_rid,
2175                     sc->bnx_irq);
2176         }
2177         if (sc->bnx_irq_type == PCI_INTR_TYPE_MSI)
2178                 pci_release_msi(dev);
2179
2180         if (sc->bnx_res != NULL) {
2181                 bus_release_resource(dev, SYS_RES_MEMORY,
2182                     BGE_PCI_BAR0, sc->bnx_res);
2183         }
2184
2185         if (sc->bnx_sysctl_tree != NULL)
2186                 sysctl_ctx_free(&sc->bnx_sysctl_ctx);
2187
2188         bnx_dma_free(sc);
2189
2190         return 0;
2191 }
2192
2193 static void
2194 bnx_reset(struct bnx_softc *sc)
2195 {
2196         device_t dev;
2197         uint32_t cachesize, command, pcistate, reset;
2198         void (*write_op)(struct bnx_softc *, uint32_t, uint32_t);
2199         int i, val = 0;
2200         uint16_t devctl;
2201
2202         dev = sc->bnx_dev;
2203
2204         write_op = bnx_writemem_direct;
2205
2206         /* Save some important PCI state. */
2207         cachesize = pci_read_config(dev, BGE_PCI_CACHESZ, 4);
2208         command = pci_read_config(dev, BGE_PCI_CMD, 4);
2209         pcistate = pci_read_config(dev, BGE_PCI_PCISTATE, 4);
2210
2211         pci_write_config(dev, BGE_PCI_MISC_CTL,
2212             BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR|
2213             BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_PCISTATE_RW|
2214             BGE_PCIMISCCTL_TAGGED_STATUS, 4);
2215
2216         /* Disable fastboot on controllers that support it. */
2217         if (bootverbose)
2218                 if_printf(&sc->arpcom.ac_if, "Disabling fastboot\n");
2219         CSR_WRITE_4(sc, BGE_FASTBOOT_PC, 0x0);
2220
2221         /*
2222          * Write the magic number to SRAM at offset 0xB50.
2223          * When firmware finishes its initialization it will
2224          * write ~BGE_MAGIC_NUMBER to the same location.
2225          */
2226         bnx_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER);
2227
2228         reset = BGE_MISCCFG_RESET_CORE_CLOCKS|(65<<1);
2229
2230         /* XXX: Broadcom Linux driver. */
2231         /* Force PCI-E 1.0a mode */
2232         if (!BNX_IS_57765_PLUS(sc) &&
2233             CSR_READ_4(sc, BGE_PCIE_PHY_TSTCTL) ==
2234             (BGE_PCIE_PHY_TSTCTL_PSCRAM |
2235              BGE_PCIE_PHY_TSTCTL_PCIE10)) {
2236                 CSR_WRITE_4(sc, BGE_PCIE_PHY_TSTCTL,
2237                     BGE_PCIE_PHY_TSTCTL_PSCRAM);
2238         }
2239         if (sc->bnx_chipid != BGE_CHIPID_BCM5750_A0) {
2240                 /* Prevent PCIE link training during global reset */
2241                 CSR_WRITE_4(sc, BGE_MISC_CFG, (1<<29));
2242                 reset |= (1<<29);
2243         }
2244
2245         /* 
2246          * Set GPHY Power Down Override to leave GPHY
2247          * powered up in D0 uninitialized.
2248          */
2249         if ((sc->bnx_flags & BNX_FLAG_CPMU) == 0)
2250                 reset |= BGE_MISCCFG_GPHY_PD_OVERRIDE;
2251
2252         /* Issue global reset */
2253         write_op(sc, BGE_MISC_CFG, reset);
2254
2255         DELAY(1000);
2256
2257         /* XXX: Broadcom Linux driver. */
2258         if (sc->bnx_chipid == BGE_CHIPID_BCM5750_A0) {
2259                 uint32_t v;
2260
2261                 DELAY(500000); /* wait for link training to complete */
2262                 v = pci_read_config(dev, 0xc4, 4);
2263                 pci_write_config(dev, 0xc4, v | (1<<15), 4);
2264         }
2265
2266         devctl = pci_read_config(dev, sc->bnx_pciecap + PCIER_DEVCTRL, 2);
2267
2268         /* Disable no snoop and disable relaxed ordering. */
2269         devctl &= ~(PCIEM_DEVCTL_RELAX_ORDER | PCIEM_DEVCTL_NOSNOOP);
2270
2271         /* Old PCI-E chips only support 128 bytes Max PayLoad Size. */
2272         if ((sc->bnx_flags & BNX_FLAG_CPMU) == 0) {
2273                 devctl &= ~PCIEM_DEVCTL_MAX_PAYLOAD_MASK;
2274                 devctl |= PCIEM_DEVCTL_MAX_PAYLOAD_128;
2275         }
2276
2277         pci_write_config(dev, sc->bnx_pciecap + PCIER_DEVCTRL,
2278             devctl, 2);
2279
2280         /* Clear error status. */
2281         pci_write_config(dev, sc->bnx_pciecap + PCIER_DEVSTS,
2282             PCIEM_DEVSTS_CORR_ERR |
2283             PCIEM_DEVSTS_NFATAL_ERR |
2284             PCIEM_DEVSTS_FATAL_ERR |
2285             PCIEM_DEVSTS_UNSUPP_REQ, 2);
2286
2287         /* Reset some of the PCI state that got zapped by reset */
2288         pci_write_config(dev, BGE_PCI_MISC_CTL,
2289             BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR|
2290             BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_PCISTATE_RW|
2291             BGE_PCIMISCCTL_TAGGED_STATUS, 4);
2292         pci_write_config(dev, BGE_PCI_CACHESZ, cachesize, 4);
2293         pci_write_config(dev, BGE_PCI_CMD, command, 4);
2294         write_op(sc, BGE_MISC_CFG, (65 << 1));
2295
2296         /* Enable memory arbiter */
2297         CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
2298
2299         /*
2300          * Poll until we see the 1's complement of the magic number.
2301          * This indicates that the firmware initialization is complete.
2302          */
2303         for (i = 0; i < BNX_FIRMWARE_TIMEOUT; i++) {
2304                 val = bnx_readmem_ind(sc, BGE_SOFTWARE_GENCOMM);
2305                 if (val == ~BGE_MAGIC_NUMBER)
2306                         break;
2307                 DELAY(10);
2308         }
2309         if (i == BNX_FIRMWARE_TIMEOUT) {
2310                 if_printf(&sc->arpcom.ac_if, "firmware handshake "
2311                           "timed out, found 0x%08x\n", val);
2312         }
2313
2314         /* BCM57765 A0 needs additional time before accessing. */
2315         if (sc->bnx_chipid == BGE_CHIPID_BCM57765_A0)
2316                 DELAY(10 * 1000);
2317
2318         /*
2319          * XXX Wait for the value of the PCISTATE register to
2320          * return to its original pre-reset state. This is a
2321          * fairly good indicator of reset completion. If we don't
2322          * wait for the reset to fully complete, trying to read
2323          * from the device's non-PCI registers may yield garbage
2324          * results.
2325          */
2326         for (i = 0; i < BNX_TIMEOUT; i++) {
2327                 if (pci_read_config(dev, BGE_PCI_PCISTATE, 4) == pcistate)
2328                         break;
2329                 DELAY(10);
2330         }
2331
2332         /* Fix up byte swapping */
2333         CSR_WRITE_4(sc, BGE_MODE_CTL, bnx_dma_swap_options(sc));
2334
2335         CSR_WRITE_4(sc, BGE_MAC_MODE, 0);
2336
2337         /*
2338          * The 5704 in TBI mode apparently needs some special
2339          * adjustment to insure the SERDES drive level is set
2340          * to 1.2V.
2341          */
2342         if (sc->bnx_asicrev == BGE_ASICREV_BCM5704 &&
2343             (sc->bnx_flags & BNX_FLAG_TBI)) {
2344                 uint32_t serdescfg;
2345
2346                 serdescfg = CSR_READ_4(sc, BGE_SERDES_CFG);
2347                 serdescfg = (serdescfg & ~0xFFF) | 0x880;
2348                 CSR_WRITE_4(sc, BGE_SERDES_CFG, serdescfg);
2349         }
2350
2351         CSR_WRITE_4(sc, BGE_MI_MODE,
2352             sc->bnx_mi_mode & ~BGE_MIMODE_AUTOPOLL);
2353         DELAY(80);
2354
2355         /* XXX: Broadcom Linux driver. */
2356         if (!BNX_IS_57765_PLUS(sc)) {
2357                 uint32_t v;
2358
2359                 /* Enable Data FIFO protection. */
2360                 v = CSR_READ_4(sc, BGE_PCIE_TLDLPL_PORT);
2361                 CSR_WRITE_4(sc, BGE_PCIE_TLDLPL_PORT, v | (1 << 25));
2362         }
2363
2364         DELAY(10000);
2365
2366         if (sc->bnx_asicrev == BGE_ASICREV_BCM5720) {
2367                 BNX_CLRBIT(sc, BGE_CPMU_CLCK_ORIDE,
2368                     CPMU_CLCK_ORIDE_MAC_ORIDE_EN);
2369         }
2370 }
2371
2372 /*
2373  * Frame reception handling. This is called if there's a frame
2374  * on the receive return list.
2375  *
2376  * Note: we have to be able to handle two possibilities here:
2377  * 1) the frame is from the jumbo recieve ring
2378  * 2) the frame is from the standard receive ring
2379  */
2380
2381 static void
2382 bnx_rxeof(struct bnx_softc *sc, uint16_t rx_prod, int count)
2383 {
2384         struct ifnet *ifp;
2385         int stdcnt = 0, jumbocnt = 0;
2386
2387         ifp = &sc->arpcom.ac_if;
2388
2389         while (sc->bnx_rx_saved_considx != rx_prod && count != 0) {
2390                 struct bge_rx_bd        *cur_rx;
2391                 uint32_t                rxidx;
2392                 struct mbuf             *m = NULL;
2393                 uint16_t                vlan_tag = 0;
2394                 int                     have_tag = 0;
2395
2396                 --count;
2397
2398                 cur_rx =
2399             &sc->bnx_ldata.bnx_rx_return_ring[sc->bnx_rx_saved_considx];
2400
2401                 rxidx = cur_rx->bge_idx;
2402                 BNX_INC(sc->bnx_rx_saved_considx, BNX_RETURN_RING_CNT);
2403
2404                 if (cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) {
2405                         have_tag = 1;
2406                         vlan_tag = cur_rx->bge_vlan_tag;
2407                 }
2408
2409                 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) {
2410                         BNX_INC(sc->bnx_jumbo, BGE_JUMBO_RX_RING_CNT);
2411                         jumbocnt++;
2412
2413                         if (rxidx != sc->bnx_jumbo) {
2414                                 IFNET_STAT_INC(ifp, ierrors, 1);
2415                                 if_printf(ifp, "sw jumbo index(%d) "
2416                                     "and hw jumbo index(%d) mismatch, drop!\n",
2417                                     sc->bnx_jumbo, rxidx);
2418                                 bnx_setup_rxdesc_jumbo(sc, rxidx);
2419                                 continue;
2420                         }
2421
2422                         m = sc->bnx_cdata.bnx_rx_jumbo_chain[rxidx].bnx_mbuf;
2423                         if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
2424                                 IFNET_STAT_INC(ifp, ierrors, 1);
2425                                 bnx_setup_rxdesc_jumbo(sc, sc->bnx_jumbo);
2426                                 continue;
2427                         }
2428                         if (bnx_newbuf_jumbo(sc, sc->bnx_jumbo, 0)) {
2429                                 IFNET_STAT_INC(ifp, ierrors, 1);
2430                                 bnx_setup_rxdesc_jumbo(sc, sc->bnx_jumbo);
2431                                 continue;
2432                         }
2433                 } else {
2434                         BNX_INC(sc->bnx_std, BGE_STD_RX_RING_CNT);
2435                         stdcnt++;
2436
2437                         if (rxidx != sc->bnx_std) {
2438                                 IFNET_STAT_INC(ifp, ierrors, 1);
2439                                 if_printf(ifp, "sw std index(%d) "
2440                                     "and hw std index(%d) mismatch, drop!\n",
2441                                     sc->bnx_std, rxidx);
2442                                 bnx_setup_rxdesc_std(sc, rxidx);
2443                                 continue;
2444                         }
2445
2446                         m = sc->bnx_cdata.bnx_rx_std_chain[rxidx].bnx_mbuf;
2447                         if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
2448                                 IFNET_STAT_INC(ifp, ierrors, 1);
2449                                 bnx_setup_rxdesc_std(sc, sc->bnx_std);
2450                                 continue;
2451                         }
2452                         if (bnx_newbuf_std(sc, sc->bnx_std, 0)) {
2453                                 IFNET_STAT_INC(ifp, ierrors, 1);
2454                                 bnx_setup_rxdesc_std(sc, sc->bnx_std);
2455                                 continue;
2456                         }
2457                 }
2458
2459                 IFNET_STAT_INC(ifp, ipackets, 1);
2460                 m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN;
2461                 m->m_pkthdr.rcvif = ifp;
2462
2463                 if ((ifp->if_capenable & IFCAP_RXCSUM) &&
2464                     (cur_rx->bge_flags & BGE_RXBDFLAG_IPV6) == 0) {
2465                         if (cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) {
2466                                 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
2467                                 if ((cur_rx->bge_error_flag &
2468                                     BGE_RXERRFLAG_IP_CSUM_NOK) == 0)
2469                                         m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
2470                         }
2471                         if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM) {
2472                                 m->m_pkthdr.csum_data =
2473                                     cur_rx->bge_tcp_udp_csum;
2474                                 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID |
2475                                     CSUM_PSEUDO_HDR;
2476                         }
2477                 }
2478
2479                 /*
2480                  * If we received a packet with a vlan tag, pass it
2481                  * to vlan_input() instead of ether_input().
2482                  */
2483                 if (have_tag) {
2484                         m->m_flags |= M_VLANTAG;
2485                         m->m_pkthdr.ether_vlantag = vlan_tag;
2486                 }
2487                 ifp->if_input(ifp, m);
2488         }
2489
2490         bnx_writembx(sc, BGE_MBX_RX_CONS0_LO, sc->bnx_rx_saved_considx);
2491         if (stdcnt)
2492                 bnx_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bnx_std);
2493         if (jumbocnt)
2494                 bnx_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bnx_jumbo);
2495 }
2496
2497 static void
2498 bnx_txeof(struct bnx_tx_ring *txr, uint16_t tx_cons)
2499 {
2500         struct ifnet *ifp = &txr->bnx_sc->arpcom.ac_if;
2501
2502         /*
2503          * Go through our tx ring and free mbufs for those
2504          * frames that have been sent.
2505          */
2506         while (txr->bnx_tx_saved_considx != tx_cons) {
2507                 struct bnx_tx_buf *buf;
2508                 uint32_t idx = 0;
2509
2510                 idx = txr->bnx_tx_saved_considx;
2511                 buf = &txr->bnx_tx_buf[idx];
2512                 if (buf->bnx_tx_mbuf != NULL) {
2513                         IFNET_STAT_INC(ifp, opackets, 1);
2514                         bus_dmamap_unload(txr->bnx_tx_mtag,
2515                             buf->bnx_tx_dmamap);
2516                         m_freem(buf->bnx_tx_mbuf);
2517                         buf->bnx_tx_mbuf = NULL;
2518                 }
2519                 txr->bnx_txcnt--;
2520                 BNX_INC(txr->bnx_tx_saved_considx, BGE_TX_RING_CNT);
2521         }
2522
2523         if ((BGE_TX_RING_CNT - txr->bnx_txcnt) >=
2524             (BNX_NSEG_RSVD + BNX_NSEG_SPARE))
2525                 ifq_clr_oactive(&ifp->if_snd);
2526
2527         if (txr->bnx_txcnt == 0)
2528                 ifp->if_timer = 0;
2529
2530         if (!ifq_is_empty(&ifp->if_snd))
2531                 if_devstart(ifp);
2532 }
2533
2534 #ifdef IFPOLL_ENABLE
2535
2536 static void
2537 bnx_npoll(struct ifnet *ifp, struct ifpoll_info *info)
2538 {
2539         struct bnx_softc *sc = ifp->if_softc;
2540
2541         ASSERT_SERIALIZED(ifp->if_serializer);
2542
2543         if (info != NULL) {
2544                 int cpuid = sc->bnx_npoll.ifpc_cpuid;
2545
2546                 info->ifpi_rx[cpuid].poll_func = bnx_npoll_compat;
2547                 info->ifpi_rx[cpuid].arg = NULL;
2548                 info->ifpi_rx[cpuid].serializer = ifp->if_serializer;
2549
2550                 if (ifp->if_flags & IFF_RUNNING)
2551                         bnx_disable_intr(sc);
2552                 ifq_set_cpuid(&ifp->if_snd, cpuid);
2553         } else {
2554                 if (ifp->if_flags & IFF_RUNNING)
2555                         bnx_enable_intr(sc);
2556                 ifq_set_cpuid(&ifp->if_snd, sc->bnx_intr_cpuid);
2557         }
2558 }
2559
2560 static void
2561 bnx_npoll_compat(struct ifnet *ifp, void *arg __unused, int cycle)
2562 {
2563         struct bnx_softc *sc = ifp->if_softc;
2564         struct bnx_tx_ring *txr = &sc->bnx_tx_ring[0]; /* XXX */
2565         struct bge_status_block *sblk = sc->bnx_ldata.bnx_status_block;
2566         uint16_t rx_prod, tx_cons;
2567
2568         ASSERT_SERIALIZED(ifp->if_serializer);
2569
2570         if (sc->bnx_npoll.ifpc_stcount-- == 0) {
2571                 sc->bnx_npoll.ifpc_stcount = sc->bnx_npoll.ifpc_stfrac;
2572                 /*
2573                  * Process link state changes.
2574                  */
2575                 bnx_link_poll(sc);
2576         }
2577
2578         sc->bnx_status_tag = sblk->bge_status_tag;
2579
2580         /*
2581          * Use a load fence to ensure that status_tag is saved
2582          * before rx_prod and tx_cons.
2583          */
2584         cpu_lfence();
2585
2586         rx_prod = sblk->bge_idx[0].bge_rx_prod_idx;
2587         tx_cons = sblk->bge_idx[0].bge_tx_cons_idx;
2588
2589         if (sc->bnx_rx_saved_considx != rx_prod)
2590                 bnx_rxeof(sc, rx_prod, cycle);
2591
2592         if (txr->bnx_tx_saved_considx != tx_cons)
2593                 bnx_txeof(txr, tx_cons);
2594
2595         if (sc->bnx_coal_chg)
2596                 bnx_coal_change(sc);
2597 }
2598
2599 #endif  /* IFPOLL_ENABLE */
2600
2601 static void
2602 bnx_intr_legacy(void *xsc)
2603 {
2604         struct bnx_softc *sc = xsc;
2605         struct bge_status_block *sblk = sc->bnx_ldata.bnx_status_block;
2606
2607         if (sc->bnx_status_tag == sblk->bge_status_tag) {
2608                 uint32_t val;
2609
2610                 val = pci_read_config(sc->bnx_dev, BGE_PCI_PCISTATE, 4);
2611                 if (val & BGE_PCISTAT_INTR_NOTACT)
2612                         return;
2613         }
2614
2615         /*
2616          * NOTE:
2617          * Interrupt will have to be disabled if tagged status
2618          * is used, else interrupt will always be asserted on
2619          * certain chips (at least on BCM5750 AX/BX).
2620          */
2621         bnx_writembx(sc, BGE_MBX_IRQ0_LO, 1);
2622
2623         bnx_intr(sc);
2624 }
2625
2626 static void
2627 bnx_msi(void *xsc)
2628 {
2629         struct bnx_softc *sc = xsc;
2630
2631         /* Disable interrupt first */
2632         bnx_writembx(sc, BGE_MBX_IRQ0_LO, 1);
2633         bnx_intr(sc);
2634 }
2635
2636 static void
2637 bnx_msi_oneshot(void *xsc)
2638 {
2639         bnx_intr(xsc);
2640 }
2641
2642 static void
2643 bnx_intr(struct bnx_softc *sc)
2644 {
2645         struct ifnet *ifp = &sc->arpcom.ac_if;
2646         struct bge_status_block *sblk = sc->bnx_ldata.bnx_status_block;
2647         uint16_t rx_prod, tx_cons;
2648         uint32_t status;
2649
2650         sc->bnx_status_tag = sblk->bge_status_tag;
2651         /*
2652          * Use a load fence to ensure that status_tag is saved 
2653          * before rx_prod, tx_cons and status.
2654          */
2655         cpu_lfence();
2656
2657         rx_prod = sblk->bge_idx[0].bge_rx_prod_idx;
2658         tx_cons = sblk->bge_idx[0].bge_tx_cons_idx;
2659         status = sblk->bge_status;
2660
2661         if ((status & BGE_STATFLAG_LINKSTATE_CHANGED) || sc->bnx_link_evt)
2662                 bnx_link_poll(sc);
2663
2664         if (ifp->if_flags & IFF_RUNNING) {
2665                 struct bnx_tx_ring *txr = &sc->bnx_tx_ring[0]; /* XXX */
2666
2667                 if (sc->bnx_rx_saved_considx != rx_prod)
2668                         bnx_rxeof(sc, rx_prod, -1);
2669
2670                 if (txr->bnx_tx_saved_considx != tx_cons)
2671                         bnx_txeof(txr, tx_cons);
2672         }
2673
2674         bnx_writembx(sc, BGE_MBX_IRQ0_LO, sc->bnx_status_tag << 24);
2675
2676         if (sc->bnx_coal_chg)
2677                 bnx_coal_change(sc);
2678 }
2679
2680 static void
2681 bnx_tick(void *xsc)
2682 {
2683         struct bnx_softc *sc = xsc;
2684         struct ifnet *ifp = &sc->arpcom.ac_if;
2685
2686         lwkt_serialize_enter(ifp->if_serializer);
2687
2688         KKASSERT(mycpuid == sc->bnx_stat_cpuid);
2689
2690         bnx_stats_update_regs(sc);
2691
2692         if (sc->bnx_flags & BNX_FLAG_TBI) {
2693                 /*
2694                  * Since in TBI mode auto-polling can't be used we should poll
2695                  * link status manually. Here we register pending link event
2696                  * and trigger interrupt.
2697                  */
2698                 sc->bnx_link_evt++;
2699                 BNX_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW);
2700         } else if (!sc->bnx_link) {
2701                 mii_tick(device_get_softc(sc->bnx_miibus));
2702         }
2703
2704         callout_reset(&sc->bnx_stat_timer, hz, bnx_tick, sc);
2705
2706         lwkt_serialize_exit(ifp->if_serializer);
2707 }
2708
2709 static void
2710 bnx_stats_update_regs(struct bnx_softc *sc)
2711 {
2712         struct ifnet *ifp = &sc->arpcom.ac_if;
2713         struct bge_mac_stats_regs stats;
2714         uint32_t *s;
2715         int i;
2716
2717         s = (uint32_t *)&stats;
2718         for (i = 0; i < sizeof(struct bge_mac_stats_regs); i += 4) {
2719                 *s = CSR_READ_4(sc, BGE_RX_STATS + i);
2720                 s++;
2721         }
2722
2723         IFNET_STAT_SET(ifp, collisions,
2724            (stats.dot3StatsSingleCollisionFrames +
2725            stats.dot3StatsMultipleCollisionFrames +
2726            stats.dot3StatsExcessiveCollisions +
2727            stats.dot3StatsLateCollisions));
2728 }
2729
2730 /*
2731  * Encapsulate an mbuf chain in the tx ring  by coupling the mbuf data
2732  * pointers to descriptors.
2733  */
2734 static int
2735 bnx_encap(struct bnx_tx_ring *txr, struct mbuf **m_head0, uint32_t *txidx,
2736     int *segs_used)
2737 {
2738         struct bge_tx_bd *d = NULL;
2739         uint16_t csum_flags = 0, vlan_tag = 0, mss = 0;
2740         bus_dma_segment_t segs[BNX_NSEG_NEW];
2741         bus_dmamap_t map;
2742         int error, maxsegs, nsegs, idx, i;
2743         struct mbuf *m_head = *m_head0, *m_new;
2744
2745         if (m_head->m_pkthdr.csum_flags & CSUM_TSO) {
2746 #ifdef BNX_TSO_DEBUG
2747                 int tso_nsegs;
2748 #endif
2749
2750                 error = bnx_setup_tso(txr, m_head0, &mss, &csum_flags);
2751                 if (error)
2752                         return error;
2753                 m_head = *m_head0;
2754
2755 #ifdef BNX_TSO_DEBUG
2756                 tso_nsegs = (m_head->m_pkthdr.len /
2757                     m_head->m_pkthdr.tso_segsz) - 1;
2758                 if (tso_nsegs > (BNX_TSO_NSTATS - 1))
2759                         tso_nsegs = BNX_TSO_NSTATS - 1;
2760                 else if (tso_nsegs < 0)
2761                         tso_nsegs = 0;
2762                 txr->bnx_sc->bnx_tsosegs[tso_nsegs]++;
2763 #endif
2764         } else if (m_head->m_pkthdr.csum_flags & BNX_CSUM_FEATURES) {
2765                 if (m_head->m_pkthdr.csum_flags & CSUM_IP)
2766                         csum_flags |= BGE_TXBDFLAG_IP_CSUM;
2767                 if (m_head->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP))
2768                         csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM;
2769                 if (m_head->m_flags & M_LASTFRAG)
2770                         csum_flags |= BGE_TXBDFLAG_IP_FRAG_END;
2771                 else if (m_head->m_flags & M_FRAG)
2772                         csum_flags |= BGE_TXBDFLAG_IP_FRAG;
2773         }
2774         if (m_head->m_flags & M_VLANTAG) {
2775                 csum_flags |= BGE_TXBDFLAG_VLAN_TAG;
2776                 vlan_tag = m_head->m_pkthdr.ether_vlantag;
2777         }
2778
2779         idx = *txidx;
2780         map = txr->bnx_tx_buf[idx].bnx_tx_dmamap;
2781
2782         maxsegs = (BGE_TX_RING_CNT - txr->bnx_txcnt) - BNX_NSEG_RSVD;
2783         KASSERT(maxsegs >= BNX_NSEG_SPARE,
2784                 ("not enough segments %d", maxsegs));
2785
2786         if (maxsegs > BNX_NSEG_NEW)
2787                 maxsegs = BNX_NSEG_NEW;
2788
2789         /*
2790          * Pad outbound frame to BGE_MIN_FRAMELEN for an unusual reason.
2791          * The bge hardware will pad out Tx runts to BGE_MIN_FRAMELEN,
2792          * but when such padded frames employ the bge IP/TCP checksum
2793          * offload, the hardware checksum assist gives incorrect results
2794          * (possibly from incorporating its own padding into the UDP/TCP
2795          * checksum; who knows).  If we pad such runts with zeros, the
2796          * onboard checksum comes out correct.
2797          */
2798         if ((csum_flags & BGE_TXBDFLAG_TCP_UDP_CSUM) &&
2799             m_head->m_pkthdr.len < BNX_MIN_FRAMELEN) {
2800                 error = m_devpad(m_head, BNX_MIN_FRAMELEN);
2801                 if (error)
2802                         goto back;
2803         }
2804
2805         if ((txr->bnx_tx_flags & BNX_TX_FLAG_SHORTDMA) &&
2806             m_head->m_next != NULL) {
2807                 m_new = bnx_defrag_shortdma(m_head);
2808                 if (m_new == NULL) {
2809                         error = ENOBUFS;
2810                         goto back;
2811                 }
2812                 *m_head0 = m_head = m_new;
2813         }
2814         if ((m_head->m_pkthdr.csum_flags & CSUM_TSO) == 0 &&
2815             (txr->bnx_tx_flags & BNX_TX_FLAG_FORCE_DEFRAG) &&
2816             m_head->m_next != NULL) {
2817                 /*
2818                  * Forcefully defragment mbuf chain to overcome hardware
2819                  * limitation which only support a single outstanding
2820                  * DMA read operation.  If it fails, keep moving on using
2821                  * the original mbuf chain.
2822                  */
2823                 m_new = m_defrag(m_head, MB_DONTWAIT);
2824                 if (m_new != NULL)
2825                         *m_head0 = m_head = m_new;
2826         }
2827
2828         error = bus_dmamap_load_mbuf_defrag(txr->bnx_tx_mtag, map,
2829             m_head0, segs, maxsegs, &nsegs, BUS_DMA_NOWAIT);
2830         if (error)
2831                 goto back;
2832         *segs_used += nsegs;
2833
2834         m_head = *m_head0;
2835         bus_dmamap_sync(txr->bnx_tx_mtag, map, BUS_DMASYNC_PREWRITE);
2836
2837         for (i = 0; ; i++) {
2838                 d = &txr->bnx_tx_ring[idx];
2839
2840                 d->bge_addr.bge_addr_lo = BGE_ADDR_LO(segs[i].ds_addr);
2841                 d->bge_addr.bge_addr_hi = BGE_ADDR_HI(segs[i].ds_addr);
2842                 d->bge_len = segs[i].ds_len;
2843                 d->bge_flags = csum_flags;
2844                 d->bge_vlan_tag = vlan_tag;
2845                 d->bge_mss = mss;
2846
2847                 if (i == nsegs - 1)
2848                         break;
2849                 BNX_INC(idx, BGE_TX_RING_CNT);
2850         }
2851         /* Mark the last segment as end of packet... */
2852         d->bge_flags |= BGE_TXBDFLAG_END;
2853
2854         /*
2855          * Insure that the map for this transmission is placed at
2856          * the array index of the last descriptor in this chain.
2857          */
2858         txr->bnx_tx_buf[*txidx].bnx_tx_dmamap = txr->bnx_tx_buf[idx].bnx_tx_dmamap;
2859         txr->bnx_tx_buf[idx].bnx_tx_dmamap = map;
2860         txr->bnx_tx_buf[idx].bnx_tx_mbuf = m_head;
2861         txr->bnx_txcnt += nsegs;
2862
2863         BNX_INC(idx, BGE_TX_RING_CNT);
2864         *txidx = idx;
2865 back:
2866         if (error) {
2867                 m_freem(*m_head0);
2868                 *m_head0 = NULL;
2869         }
2870         return error;
2871 }
2872
2873 /*
2874  * Main transmit routine. To avoid having to do mbuf copies, we put pointers
2875  * to the mbuf data regions directly in the transmit descriptors.
2876  */
2877 static void
2878 bnx_start(struct ifnet *ifp, struct ifaltq_subque *ifsq)
2879 {
2880         struct bnx_softc *sc = ifp->if_softc;
2881         struct bnx_tx_ring *txr = &sc->bnx_tx_ring[0]; /* XXX */
2882         struct mbuf *m_head = NULL;
2883         uint32_t prodidx;
2884         int nsegs = 0;
2885
2886         ASSERT_ALTQ_SQ_DEFAULT(ifp, ifsq);
2887
2888         if ((ifp->if_flags & IFF_RUNNING) == 0 || ifq_is_oactive(&ifp->if_snd))
2889                 return;
2890
2891         prodidx = txr->bnx_tx_prodidx;
2892
2893         while (txr->bnx_tx_buf[prodidx].bnx_tx_mbuf == NULL) {
2894                 /*
2895                  * Sanity check: avoid coming within BGE_NSEG_RSVD
2896                  * descriptors of the end of the ring.  Also make
2897                  * sure there are BGE_NSEG_SPARE descriptors for
2898                  * jumbo buffers' or TSO segments' defragmentation.
2899                  */
2900                 if ((BGE_TX_RING_CNT - txr->bnx_txcnt) <
2901                     (BNX_NSEG_RSVD + BNX_NSEG_SPARE)) {
2902                         ifq_set_oactive(&ifp->if_snd);
2903                         break;
2904                 }
2905
2906                 m_head = ifq_dequeue(&ifp->if_snd, NULL);
2907                 if (m_head == NULL)
2908                         break;
2909
2910                 /*
2911                  * Pack the data into the transmit ring. If we
2912                  * don't have room, set the OACTIVE flag and wait
2913                  * for the NIC to drain the ring.
2914                  */
2915                 if (bnx_encap(txr, &m_head, &prodidx, &nsegs)) {
2916                         ifq_set_oactive(&ifp->if_snd);
2917                         IFNET_STAT_INC(ifp, oerrors, 1);
2918                         break;
2919                 }
2920
2921                 if (nsegs >= txr->bnx_tx_wreg) {
2922                         /* Transmit */
2923                         bnx_writembx(txr->bnx_sc, txr->bnx_tx_mbx, prodidx);
2924                         nsegs = 0;
2925                 }
2926
2927                 ETHER_BPF_MTAP(ifp, m_head);
2928
2929                 /*
2930                  * Set a timeout in case the chip goes out to lunch.
2931                  */
2932                 ifp->if_timer = 5;
2933         }
2934
2935         if (nsegs > 0) {
2936                 /* Transmit */
2937                 bnx_writembx(txr->bnx_sc, txr->bnx_tx_mbx, prodidx);
2938         }
2939         txr->bnx_tx_prodidx = prodidx;
2940 }
2941
2942 static void
2943 bnx_init(void *xsc)
2944 {
2945         struct bnx_softc *sc = xsc;
2946         struct ifnet *ifp = &sc->arpcom.ac_if;
2947         uint16_t *m;
2948         uint32_t mode;
2949         int i;
2950
2951         ASSERT_SERIALIZED(ifp->if_serializer);
2952
2953         /* Cancel pending I/O and flush buffers. */
2954         bnx_stop(sc);
2955         bnx_reset(sc);
2956         bnx_chipinit(sc);
2957
2958         /*
2959          * Init the various state machines, ring
2960          * control blocks and firmware.
2961          */
2962         if (bnx_blockinit(sc)) {
2963                 if_printf(ifp, "initialization failure\n");
2964                 bnx_stop(sc);
2965                 return;
2966         }
2967
2968         /* Specify MTU. */
2969         CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu +
2970             ETHER_HDR_LEN + ETHER_CRC_LEN + EVL_ENCAPLEN);
2971
2972         /* Load our MAC address. */
2973         m = (uint16_t *)&sc->arpcom.ac_enaddr[0];
2974         CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0]));
2975         CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2]));
2976
2977         /* Enable or disable promiscuous mode as needed. */
2978         bnx_setpromisc(sc);
2979
2980         /* Program multicast filter. */
2981         bnx_setmulti(sc);
2982
2983         /* Init RX ring. */
2984         if (bnx_init_rx_ring_std(sc)) {
2985                 if_printf(ifp, "RX ring initialization failed\n");
2986                 bnx_stop(sc);
2987                 return;
2988         }
2989
2990         /* Init jumbo RX ring. */
2991         if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) {
2992                 if (bnx_init_rx_ring_jumbo(sc)) {
2993                         if_printf(ifp, "Jumbo RX ring initialization failed\n");
2994                         bnx_stop(sc);
2995                         return;
2996                 }
2997         }
2998
2999         /* Init our RX return ring index */
3000         sc->bnx_rx_saved_considx = 0;
3001
3002         /* Init TX ring. */
3003         for (i = 0; i < sc->bnx_tx_ringcnt; ++i)
3004                 bnx_init_tx_ring(&sc->bnx_tx_ring[i]);
3005
3006         /* Enable TX MAC state machine lockup fix. */
3007         mode = CSR_READ_4(sc, BGE_TX_MODE);
3008         mode |= BGE_TXMODE_MBUF_LOCKUP_FIX;
3009         if (sc->bnx_asicrev == BGE_ASICREV_BCM5720 ||
3010             sc->bnx_asicrev == BGE_ASICREV_BCM5762) {
3011                 mode &= ~(BGE_TXMODE_JMB_FRM_LEN | BGE_TXMODE_CNT_DN_MODE);
3012                 mode |= CSR_READ_4(sc, BGE_TX_MODE) &
3013                     (BGE_TXMODE_JMB_FRM_LEN | BGE_TXMODE_CNT_DN_MODE);
3014         }
3015         /* Turn on transmitter */
3016         CSR_WRITE_4(sc, BGE_TX_MODE, mode | BGE_TXMODE_ENABLE);
3017
3018         /* Turn on receiver */
3019         BNX_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);
3020
3021         /*
3022          * Set the number of good frames to receive after RX MBUF
3023          * Low Watermark has been reached.  After the RX MAC receives
3024          * this number of frames, it will drop subsequent incoming
3025          * frames until the MBUF High Watermark is reached.
3026          */
3027         if (BNX_IS_57765_FAMILY(sc))
3028                 CSR_WRITE_4(sc, BGE_MAX_RX_FRAME_LOWAT, 1);
3029         else
3030                 CSR_WRITE_4(sc, BGE_MAX_RX_FRAME_LOWAT, 2);
3031
3032         if (sc->bnx_irq_type == PCI_INTR_TYPE_MSI) {
3033                 if (bootverbose) {
3034                         if_printf(ifp, "MSI_MODE: %#x\n",
3035                             CSR_READ_4(sc, BGE_MSI_MODE));
3036                 }
3037         }
3038
3039         /* Tell firmware we're alive. */
3040         BNX_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
3041
3042         /* Enable host interrupts if polling(4) is not enabled. */
3043         PCI_SETBIT(sc->bnx_dev, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA, 4);
3044 #ifdef IFPOLL_ENABLE
3045         if (ifp->if_flags & IFF_NPOLLING)
3046                 bnx_disable_intr(sc);
3047         else
3048 #endif
3049         bnx_enable_intr(sc);
3050
3051         bnx_ifmedia_upd(ifp);
3052
3053         ifp->if_flags |= IFF_RUNNING;
3054         ifq_clr_oactive(&ifp->if_snd);
3055
3056         callout_reset_bycpu(&sc->bnx_stat_timer, hz, bnx_tick, sc,
3057             sc->bnx_stat_cpuid);
3058 }
3059
3060 /*
3061  * Set media options.
3062  */
3063 static int
3064 bnx_ifmedia_upd(struct ifnet *ifp)
3065 {
3066         struct bnx_softc *sc = ifp->if_softc;
3067
3068         /* If this is a 1000baseX NIC, enable the TBI port. */
3069         if (sc->bnx_flags & BNX_FLAG_TBI) {
3070                 struct ifmedia *ifm = &sc->bnx_ifmedia;
3071
3072                 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
3073                         return(EINVAL);
3074
3075                 switch(IFM_SUBTYPE(ifm->ifm_media)) {
3076                 case IFM_AUTO:
3077                         break;
3078
3079                 case IFM_1000_SX:
3080                         if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) {
3081                                 BNX_CLRBIT(sc, BGE_MAC_MODE,
3082                                     BGE_MACMODE_HALF_DUPLEX);
3083                         } else {
3084                                 BNX_SETBIT(sc, BGE_MAC_MODE,
3085                                     BGE_MACMODE_HALF_DUPLEX);
3086                         }
3087                         break;
3088                 default:
3089                         return(EINVAL);
3090                 }
3091         } else {
3092                 struct mii_data *mii = device_get_softc(sc->bnx_miibus);
3093
3094                 sc->bnx_link_evt++;
3095                 sc->bnx_link = 0;
3096                 if (mii->mii_instance) {
3097                         struct mii_softc *miisc;
3098
3099                         LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
3100                                 mii_phy_reset(miisc);
3101                 }
3102                 mii_mediachg(mii);
3103
3104                 /*
3105                  * Force an interrupt so that we will call bnx_link_upd
3106                  * if needed and clear any pending link state attention.
3107                  * Without this we are not getting any further interrupts
3108                  * for link state changes and thus will not UP the link and
3109                  * not be able to send in bnx_start.  The only way to get
3110                  * things working was to receive a packet and get an RX
3111                  * intr.
3112                  *
3113                  * bnx_tick should help for fiber cards and we might not
3114                  * need to do this here if BNX_FLAG_TBI is set but as
3115                  * we poll for fiber anyway it should not harm.
3116                  */
3117                 BNX_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW);
3118         }
3119         return(0);
3120 }
3121
3122 /*
3123  * Report current media status.
3124  */
3125 static void
3126 bnx_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
3127 {
3128         struct bnx_softc *sc = ifp->if_softc;
3129
3130         if (sc->bnx_flags & BNX_FLAG_TBI) {
3131                 ifmr->ifm_status = IFM_AVALID;
3132                 ifmr->ifm_active = IFM_ETHER;
3133                 if (CSR_READ_4(sc, BGE_MAC_STS) &
3134                     BGE_MACSTAT_TBI_PCS_SYNCHED) {
3135                         ifmr->ifm_status |= IFM_ACTIVE;
3136                 } else {
3137                         ifmr->ifm_active |= IFM_NONE;
3138                         return;
3139                 }
3140
3141                 ifmr->ifm_active |= IFM_1000_SX;
3142                 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX)
3143                         ifmr->ifm_active |= IFM_HDX;    
3144                 else
3145                         ifmr->ifm_active |= IFM_FDX;
3146         } else {
3147                 struct mii_data *mii = device_get_softc(sc->bnx_miibus);
3148
3149                 mii_pollstat(mii);
3150                 ifmr->ifm_active = mii->mii_media_active;
3151                 ifmr->ifm_status = mii->mii_media_status;
3152         }
3153 }
3154
3155 static int
3156 bnx_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
3157 {
3158         struct bnx_softc *sc = ifp->if_softc;
3159         struct ifreq *ifr = (struct ifreq *)data;
3160         int mask, error = 0;
3161
3162         ASSERT_SERIALIZED(ifp->if_serializer);
3163
3164         switch (command) {
3165         case SIOCSIFMTU:
3166                 if ((!BNX_IS_JUMBO_CAPABLE(sc) && ifr->ifr_mtu > ETHERMTU) ||
3167                     (BNX_IS_JUMBO_CAPABLE(sc) &&
3168                      ifr->ifr_mtu > BNX_JUMBO_MTU)) {
3169                         error = EINVAL;
3170                 } else if (ifp->if_mtu != ifr->ifr_mtu) {
3171                         ifp->if_mtu = ifr->ifr_mtu;
3172                         if (ifp->if_flags & IFF_RUNNING)
3173                                 bnx_init(sc);
3174                 }
3175                 break;
3176         case SIOCSIFFLAGS:
3177                 if (ifp->if_flags & IFF_UP) {
3178                         if (ifp->if_flags & IFF_RUNNING) {
3179                                 mask = ifp->if_flags ^ sc->bnx_if_flags;
3180
3181                                 /*
3182                                  * If only the state of the PROMISC flag
3183                                  * changed, then just use the 'set promisc
3184                                  * mode' command instead of reinitializing
3185                                  * the entire NIC. Doing a full re-init
3186                                  * means reloading the firmware and waiting
3187                                  * for it to start up, which may take a
3188                                  * second or two.  Similarly for ALLMULTI.
3189                                  */
3190                                 if (mask & IFF_PROMISC)
3191                                         bnx_setpromisc(sc);
3192                                 if (mask & IFF_ALLMULTI)
3193                                         bnx_setmulti(sc);
3194                         } else {
3195                                 bnx_init(sc);
3196                         }
3197                 } else if (ifp->if_flags & IFF_RUNNING) {
3198                         bnx_stop(sc);
3199                 }
3200                 sc->bnx_if_flags = ifp->if_flags;
3201                 break;
3202         case SIOCADDMULTI:
3203         case SIOCDELMULTI:
3204                 if (ifp->if_flags & IFF_RUNNING)
3205                         bnx_setmulti(sc);
3206                 break;
3207         case SIOCSIFMEDIA:
3208         case SIOCGIFMEDIA:
3209                 if (sc->bnx_flags & BNX_FLAG_TBI) {
3210                         error = ifmedia_ioctl(ifp, ifr,
3211                             &sc->bnx_ifmedia, command);
3212                 } else {
3213                         struct mii_data *mii;
3214
3215                         mii = device_get_softc(sc->bnx_miibus);
3216                         error = ifmedia_ioctl(ifp, ifr,
3217                                               &mii->mii_media, command);
3218                 }
3219                 break;
3220         case SIOCSIFCAP:
3221                 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
3222                 if (mask & IFCAP_HWCSUM) {
3223                         ifp->if_capenable ^= (mask & IFCAP_HWCSUM);
3224                         if (ifp->if_capenable & IFCAP_TXCSUM)
3225                                 ifp->if_hwassist |= BNX_CSUM_FEATURES;
3226                         else
3227                                 ifp->if_hwassist &= ~BNX_CSUM_FEATURES;
3228                 }
3229                 if (mask & IFCAP_TSO) {
3230                         ifp->if_capenable ^= (mask & IFCAP_TSO);
3231                         if (ifp->if_capenable & IFCAP_TSO)
3232                                 ifp->if_hwassist |= CSUM_TSO;
3233                         else
3234                                 ifp->if_hwassist &= ~CSUM_TSO;
3235                 }
3236                 break;
3237         default:
3238                 error = ether_ioctl(ifp, command, data);
3239                 break;
3240         }
3241         return error;
3242 }
3243
3244 static void
3245 bnx_watchdog(struct ifnet *ifp)
3246 {
3247         struct bnx_softc *sc = ifp->if_softc;
3248
3249         if_printf(ifp, "watchdog timeout -- resetting\n");
3250
3251         bnx_init(sc);
3252
3253         IFNET_STAT_INC(ifp, oerrors, 1);
3254
3255         if (!ifq_is_empty(&ifp->if_snd))
3256                 if_devstart(ifp);
3257 }
3258
3259 /*
3260  * Stop the adapter and free any mbufs allocated to the
3261  * RX and TX lists.
3262  */
3263 static void
3264 bnx_stop(struct bnx_softc *sc)
3265 {
3266         struct ifnet *ifp = &sc->arpcom.ac_if;
3267         int i;
3268
3269         ASSERT_SERIALIZED(ifp->if_serializer);
3270
3271         callout_stop(&sc->bnx_stat_timer);
3272
3273         /*
3274          * Disable all of the receiver blocks
3275          */
3276         bnx_stop_block(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);
3277         bnx_stop_block(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
3278         bnx_stop_block(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
3279         bnx_stop_block(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE);
3280         bnx_stop_block(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
3281         bnx_stop_block(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE);
3282
3283         /*
3284          * Disable all of the transmit blocks
3285          */
3286         bnx_stop_block(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
3287         bnx_stop_block(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
3288         bnx_stop_block(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
3289         bnx_stop_block(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE);
3290         bnx_stop_block(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE);
3291         bnx_stop_block(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
3292
3293         /*
3294          * Shut down all of the memory managers and related
3295          * state machines.
3296          */
3297         bnx_stop_block(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE);
3298         bnx_stop_block(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE);
3299         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
3300         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
3301
3302         /* Disable host interrupts. */
3303         bnx_disable_intr(sc);
3304
3305         /*
3306          * Tell firmware we're shutting down.
3307          */
3308         BNX_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
3309
3310         /* Free the RX lists. */
3311         bnx_free_rx_ring_std(sc);
3312
3313         /* Free jumbo RX list. */
3314         if (BNX_IS_JUMBO_CAPABLE(sc))
3315                 bnx_free_rx_ring_jumbo(sc);
3316
3317         /* Free TX buffers. */
3318         for (i = 0; i < sc->bnx_tx_ringcnt; ++i)
3319                 bnx_free_tx_ring(&sc->bnx_tx_ring[i]);
3320
3321         sc->bnx_status_tag = 0;
3322         sc->bnx_link = 0;
3323         sc->bnx_coal_chg = 0;
3324
3325         ifp->if_flags &= ~IFF_RUNNING;
3326         ifq_clr_oactive(&ifp->if_snd);
3327         ifp->if_timer = 0;
3328 }
3329
3330 /*
3331  * Stop all chip I/O so that the kernel's probe routines don't
3332  * get confused by errant DMAs when rebooting.
3333  */
3334 static void
3335 bnx_shutdown(device_t dev)
3336 {
3337         struct bnx_softc *sc = device_get_softc(dev);
3338         struct ifnet *ifp = &sc->arpcom.ac_if;
3339
3340         lwkt_serialize_enter(ifp->if_serializer);
3341         bnx_stop(sc);
3342         bnx_reset(sc);
3343         lwkt_serialize_exit(ifp->if_serializer);
3344 }
3345
3346 static int
3347 bnx_suspend(device_t dev)
3348 {
3349         struct bnx_softc *sc = device_get_softc(dev);
3350         struct ifnet *ifp = &sc->arpcom.ac_if;
3351
3352         lwkt_serialize_enter(ifp->if_serializer);
3353         bnx_stop(sc);
3354         lwkt_serialize_exit(ifp->if_serializer);
3355
3356         return 0;
3357 }
3358
3359 static int
3360 bnx_resume(device_t dev)
3361 {
3362         struct bnx_softc *sc = device_get_softc(dev);
3363         struct ifnet *ifp = &sc->arpcom.ac_if;
3364
3365         lwkt_serialize_enter(ifp->if_serializer);
3366
3367         if (ifp->if_flags & IFF_UP) {
3368                 bnx_init(sc);
3369
3370                 if (!ifq_is_empty(&ifp->if_snd))
3371                         if_devstart(ifp);
3372         }
3373
3374         lwkt_serialize_exit(ifp->if_serializer);
3375
3376         return 0;
3377 }
3378
3379 static void
3380 bnx_setpromisc(struct bnx_softc *sc)
3381 {
3382         struct ifnet *ifp = &sc->arpcom.ac_if;
3383
3384         if (ifp->if_flags & IFF_PROMISC)
3385                 BNX_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
3386         else
3387                 BNX_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
3388 }
3389
3390 static void
3391 bnx_dma_free(struct bnx_softc *sc)
3392 {
3393         int i;
3394
3395         /* Destroy RX mbuf DMA stuffs. */
3396         if (sc->bnx_cdata.bnx_rx_mtag != NULL) {
3397                 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
3398                         bus_dmamap_destroy(sc->bnx_cdata.bnx_rx_mtag,
3399                             sc->bnx_cdata.bnx_rx_std_dmamap[i]);
3400                 }
3401                 bus_dmamap_destroy(sc->bnx_cdata.bnx_rx_mtag,
3402                                    sc->bnx_cdata.bnx_rx_tmpmap);
3403                 bus_dma_tag_destroy(sc->bnx_cdata.bnx_rx_mtag);
3404         }
3405
3406         /* Destroy TX rings */
3407         if (sc->bnx_tx_ring != NULL) {
3408                 for (i = 0; i < sc->bnx_tx_ringcnt; ++i)
3409                         bnx_destroy_tx_ring(&sc->bnx_tx_ring[i]);
3410                 kfree(sc->bnx_tx_ring, M_DEVBUF);
3411         }
3412
3413         /* Destroy standard RX ring */
3414         bnx_dma_block_free(sc->bnx_cdata.bnx_rx_std_ring_tag,
3415                            sc->bnx_cdata.bnx_rx_std_ring_map,
3416                            sc->bnx_ldata.bnx_rx_std_ring);
3417
3418         if (BNX_IS_JUMBO_CAPABLE(sc))
3419                 bnx_free_jumbo_mem(sc);
3420
3421         /* Destroy RX return ring */
3422         bnx_dma_block_free(sc->bnx_cdata.bnx_rx_return_ring_tag,
3423                            sc->bnx_cdata.bnx_rx_return_ring_map,
3424                            sc->bnx_ldata.bnx_rx_return_ring);
3425
3426         /* Destroy status block */
3427         bnx_dma_block_free(sc->bnx_cdata.bnx_status_tag,
3428                            sc->bnx_cdata.bnx_status_map,
3429                            sc->bnx_ldata.bnx_status_block);
3430
3431         /* Destroy the parent tag */
3432         if (sc->bnx_cdata.bnx_parent_tag != NULL)
3433                 bus_dma_tag_destroy(sc->bnx_cdata.bnx_parent_tag);
3434 }
3435
3436 static int
3437 bnx_dma_alloc(struct bnx_softc *sc)
3438 {
3439         struct ifnet *ifp = &sc->arpcom.ac_if;
3440         int i, error, mbx;
3441
3442         /*
3443          * Allocate the parent bus DMA tag appropriate for PCI.
3444          *
3445          * All of the NetExtreme/NetLink controllers have 4GB boundary
3446          * DMA bug.
3447          * Whenever an address crosses a multiple of the 4GB boundary
3448          * (including 4GB, 8Gb, 12Gb, etc.) and makes the transition
3449          * from 0xX_FFFF_FFFF to 0x(X+1)_0000_0000 an internal DMA
3450          * state machine will lockup and cause the device to hang.
3451          */
3452         error = bus_dma_tag_create(NULL, 1, BGE_DMA_BOUNDARY_4G,
3453                                    BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
3454                                    NULL, NULL,
3455                                    BUS_SPACE_MAXSIZE_32BIT, 0,
3456                                    BUS_SPACE_MAXSIZE_32BIT,
3457                                    0, &sc->bnx_cdata.bnx_parent_tag);
3458         if (error) {
3459                 if_printf(ifp, "could not allocate parent dma tag\n");
3460                 return error;
3461         }
3462
3463         /*
3464          * Create DMA tag and maps for RX mbufs.
3465          */
3466         error = bus_dma_tag_create(sc->bnx_cdata.bnx_parent_tag, 1, 0,
3467                                    BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
3468                                    NULL, NULL, MCLBYTES, 1, MCLBYTES,
3469                                    BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK,
3470                                    &sc->bnx_cdata.bnx_rx_mtag);
3471         if (error) {
3472                 if_printf(ifp, "could not allocate RX mbuf dma tag\n");
3473                 return error;
3474         }
3475
3476         error = bus_dmamap_create(sc->bnx_cdata.bnx_rx_mtag,
3477                                   BUS_DMA_WAITOK, &sc->bnx_cdata.bnx_rx_tmpmap);
3478         if (error) {
3479                 bus_dma_tag_destroy(sc->bnx_cdata.bnx_rx_mtag);
3480                 sc->bnx_cdata.bnx_rx_mtag = NULL;
3481                 return error;
3482         }
3483
3484         for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
3485                 error = bus_dmamap_create(sc->bnx_cdata.bnx_rx_mtag,
3486                                           BUS_DMA_WAITOK,
3487                                           &sc->bnx_cdata.bnx_rx_std_dmamap[i]);
3488                 if (error) {
3489                         int j;
3490
3491                         for (j = 0; j < i; ++j) {
3492                                 bus_dmamap_destroy(sc->bnx_cdata.bnx_rx_mtag,
3493                                         sc->bnx_cdata.bnx_rx_std_dmamap[j]);
3494                         }
3495                         bus_dma_tag_destroy(sc->bnx_cdata.bnx_rx_mtag);
3496                         sc->bnx_cdata.bnx_rx_mtag = NULL;
3497
3498                         if_printf(ifp, "could not create DMA map for RX\n");
3499                         return error;
3500                 }
3501         }
3502
3503         /*
3504          * Create DMA stuffs for standard RX ring.
3505          */
3506         error = bnx_dma_block_alloc(sc, BGE_STD_RX_RING_SZ,
3507                                     &sc->bnx_cdata.bnx_rx_std_ring_tag,
3508                                     &sc->bnx_cdata.bnx_rx_std_ring_map,
3509                                     (void *)&sc->bnx_ldata.bnx_rx_std_ring,
3510                                     &sc->bnx_ldata.bnx_rx_std_ring_paddr);
3511         if (error) {
3512                 if_printf(ifp, "could not create std RX ring\n");
3513                 return error;
3514         }
3515
3516         /*
3517          * Create jumbo buffer pool.
3518          */
3519         if (BNX_IS_JUMBO_CAPABLE(sc)) {
3520                 error = bnx_alloc_jumbo_mem(sc);
3521                 if (error) {
3522                         if_printf(ifp, "could not create jumbo buffer pool\n");
3523                         return error;
3524                 }
3525         }
3526
3527         /*
3528          * Create DMA stuffs for RX return ring.
3529          */
3530         error = bnx_dma_block_alloc(sc,
3531             BGE_RX_RTN_RING_SZ(BNX_RETURN_RING_CNT),
3532             &sc->bnx_cdata.bnx_rx_return_ring_tag,
3533             &sc->bnx_cdata.bnx_rx_return_ring_map,
3534             (void *)&sc->bnx_ldata.bnx_rx_return_ring,
3535             &sc->bnx_ldata.bnx_rx_return_ring_paddr);
3536         if (error) {
3537                 if_printf(ifp, "could not create RX ret ring\n");
3538                 return error;
3539         }
3540
3541         /*
3542          * Create DMA stuffs for status block.
3543          */
3544         error = bnx_dma_block_alloc(sc, BGE_STATUS_BLK_SZ,
3545                                     &sc->bnx_cdata.bnx_status_tag,
3546                                     &sc->bnx_cdata.bnx_status_map,
3547                                     (void *)&sc->bnx_ldata.bnx_status_block,
3548                                     &sc->bnx_ldata.bnx_status_block_paddr);
3549         if (error) {
3550                 if_printf(ifp, "could not create status block\n");
3551                 return error;
3552         }
3553
3554         mbx = BGE_MBX_TX_HOST_PROD0_LO;
3555         sc->bnx_tx_ring = kmalloc_cachealign(
3556             sizeof(struct bnx_tx_ring) * sc->bnx_tx_ringcnt, M_DEVBUF,
3557             M_WAITOK | M_ZERO);
3558         for (i = 0; i < sc->bnx_tx_ringcnt; ++i) {
3559                 struct bnx_tx_ring *txr = &sc->bnx_tx_ring[i];
3560
3561                 txr->bnx_sc = sc;
3562                 txr->bnx_tx_mbx = mbx;
3563
3564                 if (mbx & 0x4)
3565                         mbx -= 0x4;
3566                 else
3567                         mbx += 0xc;
3568
3569                 error = bnx_create_tx_ring(txr);
3570                 if (error) {
3571                         device_printf(sc->bnx_dev,
3572                             "can't create %dth tx ring\n", i);
3573                         return error;
3574                 }
3575         }
3576
3577         return 0;
3578 }
3579
3580 static int
3581 bnx_dma_block_alloc(struct bnx_softc *sc, bus_size_t size, bus_dma_tag_t *tag,
3582                     bus_dmamap_t *map, void **addr, bus_addr_t *paddr)
3583 {
3584         bus_dmamem_t dmem;
3585         int error;
3586
3587         error = bus_dmamem_coherent(sc->bnx_cdata.bnx_parent_tag, PAGE_SIZE, 0,
3588                                     BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
3589                                     size, BUS_DMA_WAITOK | BUS_DMA_ZERO, &dmem);
3590         if (error)
3591                 return error;
3592
3593         *tag = dmem.dmem_tag;
3594         *map = dmem.dmem_map;
3595         *addr = dmem.dmem_addr;
3596         *paddr = dmem.dmem_busaddr;
3597
3598         return 0;
3599 }
3600
3601 static void
3602 bnx_dma_block_free(bus_dma_tag_t tag, bus_dmamap_t map, void *addr)
3603 {
3604         if (tag != NULL) {
3605                 bus_dmamap_unload(tag, map);
3606                 bus_dmamem_free(tag, addr, map);
3607                 bus_dma_tag_destroy(tag);
3608         }
3609 }
3610
3611 static void
3612 bnx_tbi_link_upd(struct bnx_softc *sc, uint32_t status)
3613 {
3614         struct ifnet *ifp = &sc->arpcom.ac_if;
3615
3616 #define PCS_ENCODE_ERR  (BGE_MACSTAT_PORT_DECODE_ERROR|BGE_MACSTAT_MI_COMPLETE)
3617
3618         /*
3619          * Sometimes PCS encoding errors are detected in
3620          * TBI mode (on fiber NICs), and for some reason
3621          * the chip will signal them as link changes.
3622          * If we get a link change event, but the 'PCS
3623          * encoding error' bit in the MAC status register
3624          * is set, don't bother doing a link check.
3625          * This avoids spurious "gigabit link up" messages
3626          * that sometimes appear on fiber NICs during
3627          * periods of heavy traffic.
3628          */
3629         if (status & BGE_MACSTAT_TBI_PCS_SYNCHED) {
3630                 if (!sc->bnx_link) {
3631                         sc->bnx_link++;
3632                         if (sc->bnx_asicrev == BGE_ASICREV_BCM5704) {
3633                                 BNX_CLRBIT(sc, BGE_MAC_MODE,
3634                                     BGE_MACMODE_TBI_SEND_CFGS);
3635                         }
3636                         CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF);
3637
3638                         if (bootverbose)
3639                                 if_printf(ifp, "link UP\n");
3640
3641                         ifp->if_link_state = LINK_STATE_UP;
3642                         if_link_state_change(ifp);
3643                 }
3644         } else if ((status & PCS_ENCODE_ERR) != PCS_ENCODE_ERR) {
3645                 if (sc->bnx_link) {
3646                         sc->bnx_link = 0;
3647
3648                         if (bootverbose)
3649                                 if_printf(ifp, "link DOWN\n");
3650
3651                         ifp->if_link_state = LINK_STATE_DOWN;
3652                         if_link_state_change(ifp);
3653                 }
3654         }
3655
3656 #undef PCS_ENCODE_ERR
3657
3658         /* Clear the attention. */
3659         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
3660             BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
3661             BGE_MACSTAT_LINK_CHANGED);
3662 }
3663
3664 static void
3665 bnx_copper_link_upd(struct bnx_softc *sc, uint32_t status __unused)
3666 {
3667         struct ifnet *ifp = &sc->arpcom.ac_if;
3668         struct mii_data *mii = device_get_softc(sc->bnx_miibus);
3669
3670         mii_pollstat(mii);
3671         bnx_miibus_statchg(sc->bnx_dev);
3672
3673         if (bootverbose) {
3674                 if (sc->bnx_link)
3675                         if_printf(ifp, "link UP\n");
3676                 else
3677                         if_printf(ifp, "link DOWN\n");
3678         }
3679
3680         /* Clear the attention. */
3681         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
3682             BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
3683             BGE_MACSTAT_LINK_CHANGED);
3684 }
3685
3686 static void
3687 bnx_autopoll_link_upd(struct bnx_softc *sc, uint32_t status __unused)
3688 {
3689         struct ifnet *ifp = &sc->arpcom.ac_if;
3690         struct mii_data *mii = device_get_softc(sc->bnx_miibus);
3691
3692         mii_pollstat(mii);
3693
3694         if (!sc->bnx_link &&
3695             (mii->mii_media_status & IFM_ACTIVE) &&
3696             IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
3697                 sc->bnx_link++;
3698                 if (bootverbose)
3699                         if_printf(ifp, "link UP\n");
3700         } else if (sc->bnx_link &&
3701             (!(mii->mii_media_status & IFM_ACTIVE) ||
3702             IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) {
3703                 sc->bnx_link = 0;
3704                 if (bootverbose)
3705                         if_printf(ifp, "link DOWN\n");
3706         }
3707
3708         /* Clear the attention. */
3709         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
3710             BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
3711             BGE_MACSTAT_LINK_CHANGED);
3712 }
3713
3714 static int
3715 bnx_sysctl_rx_coal_ticks(SYSCTL_HANDLER_ARGS)
3716 {
3717         struct bnx_softc *sc = arg1;
3718
3719         return bnx_sysctl_coal_chg(oidp, arg1, arg2, req,
3720             &sc->bnx_rx_coal_ticks,
3721             BNX_RX_COAL_TICKS_MIN, BNX_RX_COAL_TICKS_MAX,
3722             BNX_RX_COAL_TICKS_CHG);
3723 }
3724
3725 static int
3726 bnx_sysctl_tx_coal_ticks(SYSCTL_HANDLER_ARGS)
3727 {
3728         struct bnx_softc *sc = arg1;
3729
3730         return bnx_sysctl_coal_chg(oidp, arg1, arg2, req,
3731             &sc->bnx_tx_coal_ticks,
3732             BNX_TX_COAL_TICKS_MIN, BNX_TX_COAL_TICKS_MAX,
3733             BNX_TX_COAL_TICKS_CHG);
3734 }
3735
3736 static int
3737 bnx_sysctl_rx_coal_bds(SYSCTL_HANDLER_ARGS)
3738 {
3739         struct bnx_softc *sc = arg1;
3740
3741         return bnx_sysctl_coal_chg(oidp, arg1, arg2, req,
3742             &sc->bnx_rx_coal_bds,
3743             BNX_RX_COAL_BDS_MIN, BNX_RX_COAL_BDS_MAX,
3744             BNX_RX_COAL_BDS_CHG);
3745 }
3746
3747 static int
3748 bnx_sysctl_tx_coal_bds(SYSCTL_HANDLER_ARGS)
3749 {
3750         struct bnx_softc *sc = arg1;
3751
3752         return bnx_sysctl_coal_chg(oidp, arg1, arg2, req,
3753             &sc->bnx_tx_coal_bds,
3754             BNX_TX_COAL_BDS_MIN, BNX_TX_COAL_BDS_MAX,
3755             BNX_TX_COAL_BDS_CHG);
3756 }
3757
3758 static int
3759 bnx_sysctl_rx_coal_bds_int(SYSCTL_HANDLER_ARGS)
3760 {
3761         struct bnx_softc *sc = arg1;
3762
3763         return bnx_sysctl_coal_chg(oidp, arg1, arg2, req,
3764             &sc->bnx_rx_coal_bds_int,
3765             BNX_RX_COAL_BDS_MIN, BNX_RX_COAL_BDS_MAX,
3766             BNX_RX_COAL_BDS_INT_CHG);
3767 }
3768
3769 static int
3770 bnx_sysctl_tx_coal_bds_int(SYSCTL_HANDLER_ARGS)
3771 {
3772         struct bnx_softc *sc = arg1;
3773
3774         return bnx_sysctl_coal_chg(oidp, arg1, arg2, req,
3775             &sc->bnx_tx_coal_bds_int,
3776             BNX_TX_COAL_BDS_MIN, BNX_TX_COAL_BDS_MAX,
3777             BNX_TX_COAL_BDS_INT_CHG);
3778 }
3779
3780 static int
3781 bnx_sysctl_coal_chg(SYSCTL_HANDLER_ARGS, uint32_t *coal,
3782     int coal_min, int coal_max, uint32_t coal_chg_mask)
3783 {
3784         struct bnx_softc *sc = arg1;
3785         struct ifnet *ifp = &sc->arpcom.ac_if;
3786         int error = 0, v;
3787
3788         lwkt_serialize_enter(ifp->if_serializer);
3789
3790         v = *coal;
3791         error = sysctl_handle_int(oidp, &v, 0, req);
3792         if (!error && req->newptr != NULL) {
3793                 if (v < coal_min || v > coal_max) {
3794                         error = EINVAL;
3795                 } else {
3796                         *coal = v;
3797                         sc->bnx_coal_chg |= coal_chg_mask;
3798                 }
3799         }
3800
3801         lwkt_serialize_exit(ifp->if_serializer);
3802         return error;
3803 }
3804
3805 static void
3806 bnx_coal_change(struct bnx_softc *sc)
3807 {
3808         struct ifnet *ifp = &sc->arpcom.ac_if;
3809
3810         ASSERT_SERIALIZED(ifp->if_serializer);
3811
3812         if (sc->bnx_coal_chg & BNX_RX_COAL_TICKS_CHG) {
3813                 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS,
3814                             sc->bnx_rx_coal_ticks);
3815                 DELAY(10);
3816                 CSR_READ_4(sc, BGE_HCC_RX_COAL_TICKS);
3817
3818                 if (bootverbose) {
3819                         if_printf(ifp, "rx_coal_ticks -> %u\n",
3820                                   sc->bnx_rx_coal_ticks);
3821                 }
3822         }
3823
3824         if (sc->bnx_coal_chg & BNX_TX_COAL_TICKS_CHG) {
3825                 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS,
3826                             sc->bnx_tx_coal_ticks);
3827                 DELAY(10);
3828                 CSR_READ_4(sc, BGE_HCC_TX_COAL_TICKS);
3829
3830                 if (bootverbose) {
3831                         if_printf(ifp, "tx_coal_ticks -> %u\n",
3832                                   sc->bnx_tx_coal_ticks);
3833                 }
3834         }
3835
3836         if (sc->bnx_coal_chg & BNX_RX_COAL_BDS_CHG) {
3837                 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS,
3838                             sc->bnx_rx_coal_bds);
3839                 DELAY(10);
3840                 CSR_READ_4(sc, BGE_HCC_RX_MAX_COAL_BDS);
3841
3842                 if (bootverbose) {
3843                         if_printf(ifp, "rx_coal_bds -> %u\n",
3844                                   sc->bnx_rx_coal_bds);
3845                 }
3846         }
3847
3848         if (sc->bnx_coal_chg & BNX_TX_COAL_BDS_CHG) {
3849                 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS,
3850                             sc->bnx_tx_coal_bds);
3851                 DELAY(10);
3852                 CSR_READ_4(sc, BGE_HCC_TX_MAX_COAL_BDS);
3853
3854                 if (bootverbose) {
3855                         if_printf(ifp, "tx_coal_bds -> %u\n",
3856                                   sc->bnx_tx_coal_bds);
3857                 }
3858         }
3859
3860         if (sc->bnx_coal_chg & BNX_RX_COAL_BDS_INT_CHG) {
3861                 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT,
3862                     sc->bnx_rx_coal_bds_int);
3863                 DELAY(10);
3864                 CSR_READ_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT);
3865
3866                 if (bootverbose) {
3867                         if_printf(ifp, "rx_coal_bds_int -> %u\n",
3868                             sc->bnx_rx_coal_bds_int);
3869                 }
3870         }
3871
3872         if (sc->bnx_coal_chg & BNX_TX_COAL_BDS_INT_CHG) {
3873                 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT,
3874                     sc->bnx_tx_coal_bds_int);
3875                 DELAY(10);
3876                 CSR_READ_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT);
3877
3878                 if (bootverbose) {
3879                         if_printf(ifp, "tx_coal_bds_int -> %u\n",
3880                             sc->bnx_tx_coal_bds_int);
3881                 }
3882         }
3883
3884         sc->bnx_coal_chg = 0;
3885 }
3886
3887 static void
3888 bnx_intr_check(void *xsc)
3889 {
3890         struct bnx_softc *sc = xsc;
3891         struct bnx_tx_ring *txr = &sc->bnx_tx_ring[0]; /* XXX */
3892         struct ifnet *ifp = &sc->arpcom.ac_if;
3893         struct bge_status_block *sblk = sc->bnx_ldata.bnx_status_block;
3894
3895         lwkt_serialize_enter(ifp->if_serializer);
3896
3897         KKASSERT(mycpuid == sc->bnx_intr_cpuid);
3898
3899         if ((ifp->if_flags & (IFF_RUNNING | IFF_NPOLLING)) != IFF_RUNNING) {
3900                 lwkt_serialize_exit(ifp->if_serializer);
3901                 return;
3902         }
3903
3904         if (sblk->bge_idx[0].bge_rx_prod_idx != sc->bnx_rx_saved_considx ||
3905             sblk->bge_idx[0].bge_tx_cons_idx != txr->bnx_tx_saved_considx) {
3906                 if (sc->bnx_rx_check_considx == sc->bnx_rx_saved_considx &&
3907                     sc->bnx_tx_check_considx == txr->bnx_tx_saved_considx) {
3908                         if (!sc->bnx_intr_maylose) {
3909                                 sc->bnx_intr_maylose = TRUE;
3910                                 goto done;
3911                         }
3912                         if (bootverbose)
3913                                 if_printf(ifp, "lost interrupt\n");
3914                         bnx_msi(sc);
3915                 }
3916         }
3917         sc->bnx_intr_maylose = FALSE;
3918         sc->bnx_rx_check_considx = sc->bnx_rx_saved_considx;
3919         sc->bnx_tx_check_considx = txr->bnx_tx_saved_considx;
3920
3921 done:
3922         callout_reset(&sc->bnx_intr_timer, BNX_INTR_CKINTVL,
3923             bnx_intr_check, sc);
3924         lwkt_serialize_exit(ifp->if_serializer);
3925 }
3926
3927 static void
3928 bnx_enable_intr(struct bnx_softc *sc)
3929 {
3930         struct ifnet *ifp = &sc->arpcom.ac_if;
3931
3932         lwkt_serialize_handler_enable(ifp->if_serializer);
3933
3934         /*
3935          * Enable interrupt.
3936          */
3937         bnx_writembx(sc, BGE_MBX_IRQ0_LO, sc->bnx_status_tag << 24);
3938         if (sc->bnx_flags & BNX_FLAG_ONESHOT_MSI) {
3939                 /* XXX Linux driver */
3940                 bnx_writembx(sc, BGE_MBX_IRQ0_LO, sc->bnx_status_tag << 24);
3941         }
3942
3943         /*
3944          * Unmask the interrupt when we stop polling.
3945          */
3946         PCI_CLRBIT(sc->bnx_dev, BGE_PCI_MISC_CTL,
3947             BGE_PCIMISCCTL_MASK_PCI_INTR, 4);
3948
3949         /*
3950          * Trigger another interrupt, since above writing
3951          * to interrupt mailbox0 may acknowledge pending
3952          * interrupt.
3953          */
3954         BNX_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET);
3955
3956         if (sc->bnx_flags & BNX_FLAG_STATUSTAG_BUG) {
3957                 sc->bnx_intr_maylose = FALSE;
3958                 sc->bnx_rx_check_considx = 0;
3959                 sc->bnx_tx_check_considx = 0;
3960
3961                 if (bootverbose)
3962                         if_printf(ifp, "status tag bug workaround\n");
3963
3964                 /* 10ms check interval */
3965                 callout_reset_bycpu(&sc->bnx_intr_timer, BNX_INTR_CKINTVL,
3966                     bnx_intr_check, sc, sc->bnx_intr_cpuid);
3967         }
3968 }
3969
3970 static void
3971 bnx_disable_intr(struct bnx_softc *sc)
3972 {
3973         struct ifnet *ifp = &sc->arpcom.ac_if;
3974
3975         /*
3976          * Mask the interrupt when we start polling.
3977          */
3978         PCI_SETBIT(sc->bnx_dev, BGE_PCI_MISC_CTL,
3979             BGE_PCIMISCCTL_MASK_PCI_INTR, 4);
3980
3981         /*
3982          * Acknowledge possible asserted interrupt.
3983          */
3984         bnx_writembx(sc, BGE_MBX_IRQ0_LO, 1);
3985
3986         callout_stop(&sc->bnx_intr_timer);
3987         sc->bnx_intr_maylose = FALSE;
3988         sc->bnx_rx_check_considx = 0;
3989         sc->bnx_tx_check_considx = 0;
3990
3991         sc->bnx_npoll.ifpc_stcount = 0;
3992
3993         lwkt_serialize_handler_disable(ifp->if_serializer);
3994 }
3995
3996 static int
3997 bnx_get_eaddr_mem(struct bnx_softc *sc, uint8_t ether_addr[])
3998 {
3999         uint32_t mac_addr;
4000         int ret = 1;
4001
4002         mac_addr = bnx_readmem_ind(sc, 0x0c14);
4003         if ((mac_addr >> 16) == 0x484b) {
4004                 ether_addr[0] = (uint8_t)(mac_addr >> 8);
4005                 ether_addr[1] = (uint8_t)mac_addr;
4006                 mac_addr = bnx_readmem_ind(sc, 0x0c18);
4007                 ether_addr[2] = (uint8_t)(mac_addr >> 24);
4008                 ether_addr[3] = (uint8_t)(mac_addr >> 16);
4009                 ether_addr[4] = (uint8_t)(mac_addr >> 8);
4010                 ether_addr[5] = (uint8_t)mac_addr;
4011                 ret = 0;
4012         }
4013         return ret;
4014 }
4015
4016 static int
4017 bnx_get_eaddr_nvram(struct bnx_softc *sc, uint8_t ether_addr[])
4018 {
4019         int mac_offset = BGE_EE_MAC_OFFSET;
4020
4021         if (BNX_IS_5717_PLUS(sc)) {
4022       &nbs