1 /******************************************************************************
3 Copyright (c) 2001-2017, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
32 ******************************************************************************/
35 #include "ixgbe_common.h"
36 #include "ixgbe_phy.h"
37 #include "ixgbe_dcb.h"
38 #include "ixgbe_dcb_82599.h"
39 #include "ixgbe_api.h"
41 static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw);
42 static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw);
43 static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw);
44 static s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw);
45 static void ixgbe_standby_eeprom(struct ixgbe_hw *hw);
46 static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data,
48 static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count);
49 static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec);
50 static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec);
51 static void ixgbe_release_eeprom(struct ixgbe_hw *hw);
53 static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr);
54 static s32 ixgbe_get_san_mac_addr_offset(struct ixgbe_hw *hw,
56 static s32 ixgbe_read_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
57 u16 words, u16 *data);
58 static s32 ixgbe_write_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
59 u16 words, u16 *data);
60 static s32 ixgbe_detect_eeprom_page_size_generic(struct ixgbe_hw *hw,
64 * ixgbe_init_ops_generic - Inits function ptrs
65 * @hw: pointer to the hardware structure
67 * Initialize the function pointers.
69 s32 ixgbe_init_ops_generic(struct ixgbe_hw *hw)
71 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
72 struct ixgbe_mac_info *mac = &hw->mac;
73 u32 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
75 DEBUGFUNC("ixgbe_init_ops_generic");
78 eeprom->ops.init_params = ixgbe_init_eeprom_params_generic;
79 /* If EEPROM is valid (bit 8 = 1), use EERD otherwise use bit bang */
80 if (eec & IXGBE_EEC_PRES) {
81 eeprom->ops.read = ixgbe_read_eerd_generic;
82 eeprom->ops.read_buffer = ixgbe_read_eerd_buffer_generic;
84 eeprom->ops.read = ixgbe_read_eeprom_bit_bang_generic;
85 eeprom->ops.read_buffer =
86 ixgbe_read_eeprom_buffer_bit_bang_generic;
88 eeprom->ops.write = ixgbe_write_eeprom_generic;
89 eeprom->ops.write_buffer = ixgbe_write_eeprom_buffer_bit_bang_generic;
90 eeprom->ops.validate_checksum =
91 ixgbe_validate_eeprom_checksum_generic;
92 eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_generic;
93 eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_generic;
96 mac->ops.init_hw = ixgbe_init_hw_generic;
97 mac->ops.reset_hw = NULL;
98 mac->ops.start_hw = ixgbe_start_hw_generic;
99 mac->ops.clear_hw_cntrs = ixgbe_clear_hw_cntrs_generic;
100 mac->ops.get_media_type = NULL;
101 mac->ops.get_supported_physical_layer = NULL;
102 mac->ops.enable_rx_dma = ixgbe_enable_rx_dma_generic;
103 mac->ops.get_mac_addr = ixgbe_get_mac_addr_generic;
104 mac->ops.stop_adapter = ixgbe_stop_adapter_generic;
105 mac->ops.get_bus_info = ixgbe_get_bus_info_generic;
106 mac->ops.set_lan_id = ixgbe_set_lan_id_multi_port_pcie;
107 mac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync;
108 mac->ops.release_swfw_sync = ixgbe_release_swfw_sync;
109 mac->ops.prot_autoc_read = prot_autoc_read_generic;
110 mac->ops.prot_autoc_write = prot_autoc_write_generic;
113 mac->ops.led_on = ixgbe_led_on_generic;
114 mac->ops.led_off = ixgbe_led_off_generic;
115 mac->ops.blink_led_start = ixgbe_blink_led_start_generic;
116 mac->ops.blink_led_stop = ixgbe_blink_led_stop_generic;
117 mac->ops.init_led_link_act = ixgbe_init_led_link_act_generic;
119 /* RAR, Multicast, VLAN */
120 mac->ops.set_rar = ixgbe_set_rar_generic;
121 mac->ops.clear_rar = ixgbe_clear_rar_generic;
122 mac->ops.insert_mac_addr = NULL;
123 mac->ops.set_vmdq = NULL;
124 mac->ops.clear_vmdq = NULL;
125 mac->ops.init_rx_addrs = ixgbe_init_rx_addrs_generic;
126 mac->ops.update_uc_addr_list = ixgbe_update_uc_addr_list_generic;
127 mac->ops.update_mc_addr_list = ixgbe_update_mc_addr_list_generic;
128 mac->ops.enable_mc = ixgbe_enable_mc_generic;
129 mac->ops.disable_mc = ixgbe_disable_mc_generic;
130 mac->ops.clear_vfta = NULL;
131 mac->ops.set_vfta = NULL;
132 mac->ops.set_vlvf = NULL;
133 mac->ops.init_uta_tables = NULL;
134 mac->ops.enable_rx = ixgbe_enable_rx_generic;
135 mac->ops.disable_rx = ixgbe_disable_rx_generic;
138 mac->ops.fc_enable = ixgbe_fc_enable_generic;
139 mac->ops.setup_fc = ixgbe_setup_fc_generic;
140 mac->ops.fc_autoneg = ixgbe_fc_autoneg;
143 mac->ops.get_link_capabilities = NULL;
144 mac->ops.setup_link = NULL;
145 mac->ops.check_link = NULL;
146 mac->ops.dmac_config = NULL;
147 mac->ops.dmac_update_tcs = NULL;
148 mac->ops.dmac_config_tcs = NULL;
150 return IXGBE_SUCCESS;
154 * ixgbe_device_supports_autoneg_fc - Check if device supports autonegotiation
156 * @hw: pointer to hardware structure
158 * This function returns TRUE if the device supports flow control
159 * autonegotiation, and FALSE if it does not.
162 bool ixgbe_device_supports_autoneg_fc(struct ixgbe_hw *hw)
164 bool supported = FALSE;
165 ixgbe_link_speed speed;
168 DEBUGFUNC("ixgbe_device_supports_autoneg_fc");
170 switch (hw->phy.media_type) {
171 case ixgbe_media_type_fiber_fixed:
172 case ixgbe_media_type_fiber_qsfp:
173 case ixgbe_media_type_fiber:
174 /* flow control autoneg black list */
175 switch (hw->device_id) {
176 case IXGBE_DEV_ID_X550EM_A_SFP:
177 case IXGBE_DEV_ID_X550EM_A_SFP_N:
178 case IXGBE_DEV_ID_X550EM_A_QSFP:
179 case IXGBE_DEV_ID_X550EM_A_QSFP_N:
183 hw->mac.ops.check_link(hw, &speed, &link_up, FALSE);
184 /* if link is down, assume supported */
186 supported = speed == IXGBE_LINK_SPEED_1GB_FULL ?
193 case ixgbe_media_type_backplane:
194 if (hw->device_id == IXGBE_DEV_ID_X550EM_X_XFI)
199 case ixgbe_media_type_copper:
200 /* only some copper devices support flow control autoneg */
201 switch (hw->device_id) {
202 case IXGBE_DEV_ID_82599_T3_LOM:
203 case IXGBE_DEV_ID_X540T:
204 case IXGBE_DEV_ID_X540T1:
205 case IXGBE_DEV_ID_X540_BYPASS:
206 case IXGBE_DEV_ID_X550T:
207 case IXGBE_DEV_ID_X550T1:
208 case IXGBE_DEV_ID_X550EM_X_10G_T:
209 case IXGBE_DEV_ID_X550EM_A_10G_T:
210 case IXGBE_DEV_ID_X550EM_A_1G_T:
211 case IXGBE_DEV_ID_X550EM_A_1G_T_L:
222 ERROR_REPORT2(IXGBE_ERROR_UNSUPPORTED,
223 "Device %x does not support flow control autoneg",
229 * ixgbe_setup_fc_generic - Set up flow control
230 * @hw: pointer to hardware structure
232 * Called at init time to set up flow control.
234 s32 ixgbe_setup_fc_generic(struct ixgbe_hw *hw)
236 s32 ret_val = IXGBE_SUCCESS;
237 u32 reg = 0, reg_bp = 0;
241 DEBUGFUNC("ixgbe_setup_fc_generic");
243 /* Validate the requested mode */
244 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
245 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
246 "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
247 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
252 * 10gig parts do not have a word in the EEPROM to determine the
253 * default flow control setting, so we explicitly set it to full.
255 if (hw->fc.requested_mode == ixgbe_fc_default)
256 hw->fc.requested_mode = ixgbe_fc_full;
259 * Set up the 1G and 10G flow control advertisement registers so the
260 * HW will be able to do fc autoneg once the cable is plugged in. If
261 * we link at 10G, the 1G advertisement is harmless and vice versa.
263 switch (hw->phy.media_type) {
264 case ixgbe_media_type_backplane:
265 /* some MAC's need RMW protection on AUTOC */
266 ret_val = hw->mac.ops.prot_autoc_read(hw, &locked, ®_bp);
267 if (ret_val != IXGBE_SUCCESS)
270 /* fall through - only backplane uses autoc */
271 case ixgbe_media_type_fiber_fixed:
272 case ixgbe_media_type_fiber_qsfp:
273 case ixgbe_media_type_fiber:
274 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
277 case ixgbe_media_type_copper:
278 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_ADVT,
279 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, ®_cu);
286 * The possible values of fc.requested_mode are:
287 * 0: Flow control is completely disabled
288 * 1: Rx flow control is enabled (we can receive pause frames,
289 * but not send pause frames).
290 * 2: Tx flow control is enabled (we can send pause frames but
291 * we do not support receiving pause frames).
292 * 3: Both Rx and Tx flow control (symmetric) are enabled.
295 switch (hw->fc.requested_mode) {
297 /* Flow control completely disabled by software override. */
298 reg &= ~(IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE);
299 if (hw->phy.media_type == ixgbe_media_type_backplane)
300 reg_bp &= ~(IXGBE_AUTOC_SYM_PAUSE |
301 IXGBE_AUTOC_ASM_PAUSE);
302 else if (hw->phy.media_type == ixgbe_media_type_copper)
303 reg_cu &= ~(IXGBE_TAF_SYM_PAUSE | IXGBE_TAF_ASM_PAUSE);
305 case ixgbe_fc_tx_pause:
307 * Tx Flow control is enabled, and Rx Flow control is
308 * disabled by software override.
310 reg |= IXGBE_PCS1GANA_ASM_PAUSE;
311 reg &= ~IXGBE_PCS1GANA_SYM_PAUSE;
312 if (hw->phy.media_type == ixgbe_media_type_backplane) {
313 reg_bp |= IXGBE_AUTOC_ASM_PAUSE;
314 reg_bp &= ~IXGBE_AUTOC_SYM_PAUSE;
315 } else if (hw->phy.media_type == ixgbe_media_type_copper) {
316 reg_cu |= IXGBE_TAF_ASM_PAUSE;
317 reg_cu &= ~IXGBE_TAF_SYM_PAUSE;
320 case ixgbe_fc_rx_pause:
322 * Rx Flow control is enabled and Tx Flow control is
323 * disabled by software override. Since there really
324 * isn't a way to advertise that we are capable of RX
325 * Pause ONLY, we will advertise that we support both
326 * symmetric and asymmetric Rx PAUSE, as such we fall
327 * through to the fc_full statement. Later, we will
328 * disable the adapter's ability to send PAUSE frames.
331 /* Flow control (both Rx and Tx) is enabled by SW override. */
332 reg |= IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE;
333 if (hw->phy.media_type == ixgbe_media_type_backplane)
334 reg_bp |= IXGBE_AUTOC_SYM_PAUSE |
335 IXGBE_AUTOC_ASM_PAUSE;
336 else if (hw->phy.media_type == ixgbe_media_type_copper)
337 reg_cu |= IXGBE_TAF_SYM_PAUSE | IXGBE_TAF_ASM_PAUSE;
340 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT,
341 "Flow control param set incorrectly\n");
342 ret_val = IXGBE_ERR_CONFIG;
347 if (hw->mac.type < ixgbe_mac_X540) {
349 * Enable auto-negotiation between the MAC & PHY;
350 * the MAC will advertise clause 37 flow control.
352 IXGBE_WRITE_REG(hw, IXGBE_PCS1GANA, reg);
353 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GLCTL);
355 /* Disable AN timeout */
356 if (hw->fc.strict_ieee)
357 reg &= ~IXGBE_PCS1GLCTL_AN_1G_TIMEOUT_EN;
359 IXGBE_WRITE_REG(hw, IXGBE_PCS1GLCTL, reg);
360 DEBUGOUT1("Set up FC; PCS1GLCTL = 0x%08X\n", reg);
364 * AUTOC restart handles negotiation of 1G and 10G on backplane
365 * and copper. There is no need to set the PCS1GCTL register.
368 if (hw->phy.media_type == ixgbe_media_type_backplane) {
369 reg_bp |= IXGBE_AUTOC_AN_RESTART;
370 ret_val = hw->mac.ops.prot_autoc_write(hw, reg_bp, locked);
373 } else if ((hw->phy.media_type == ixgbe_media_type_copper) &&
374 (ixgbe_device_supports_autoneg_fc(hw))) {
375 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_ADVT,
376 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, reg_cu);
379 DEBUGOUT1("Set up FC; PCS1GLCTL = 0x%08X\n", reg);
385 * ixgbe_start_hw_generic - Prepare hardware for Tx/Rx
386 * @hw: pointer to hardware structure
388 * Starts the hardware by filling the bus info structure and media type, clears
389 * all on chip counters, initializes receive address registers, multicast
390 * table, VLAN filter table, calls routine to set up link and flow control
391 * settings, and leaves transmit and receive units disabled and uninitialized
393 s32 ixgbe_start_hw_generic(struct ixgbe_hw *hw)
399 DEBUGFUNC("ixgbe_start_hw_generic");
401 /* Set the media type */
402 hw->phy.media_type = hw->mac.ops.get_media_type(hw);
404 /* PHY ops initialization must be done in reset_hw() */
406 /* Clear the VLAN filter table */
407 hw->mac.ops.clear_vfta(hw);
409 /* Clear statistics registers */
410 hw->mac.ops.clear_hw_cntrs(hw);
412 /* Set No Snoop Disable */
413 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
414 ctrl_ext |= IXGBE_CTRL_EXT_NS_DIS;
415 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
416 IXGBE_WRITE_FLUSH(hw);
418 /* Setup flow control */
419 ret_val = ixgbe_setup_fc(hw);
420 if (ret_val != IXGBE_SUCCESS && ret_val != IXGBE_NOT_IMPLEMENTED) {
421 DEBUGOUT1("Flow control setup failed, returning %d\n", ret_val);
425 /* Cache bit indicating need for crosstalk fix */
426 switch (hw->mac.type) {
427 case ixgbe_mac_82599EB:
428 case ixgbe_mac_X550EM_x:
429 case ixgbe_mac_X550EM_a:
430 hw->mac.ops.get_device_caps(hw, &device_caps);
431 if (device_caps & IXGBE_DEVICE_CAPS_NO_CROSSTALK_WR)
432 hw->need_crosstalk_fix = FALSE;
434 hw->need_crosstalk_fix = TRUE;
437 hw->need_crosstalk_fix = FALSE;
441 /* Clear adapter stopped flag */
442 hw->adapter_stopped = FALSE;
444 return IXGBE_SUCCESS;
448 * ixgbe_start_hw_gen2 - Init sequence for common device family
449 * @hw: pointer to hw structure
451 * Performs the init sequence common to the second generation
453 * Devices in the second generation:
457 s32 ixgbe_start_hw_gen2(struct ixgbe_hw *hw)
462 /* Clear the rate limiters */
463 for (i = 0; i < hw->mac.max_tx_queues; i++) {
464 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, i);
465 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, 0);
467 IXGBE_WRITE_FLUSH(hw);
469 /* Disable relaxed ordering */
470 for (i = 0; i < hw->mac.max_tx_queues; i++) {
471 regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(i));
472 regval &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN;
473 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(i), regval);
476 for (i = 0; i < hw->mac.max_rx_queues; i++) {
477 regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
478 regval &= ~(IXGBE_DCA_RXCTRL_DATA_WRO_EN |
479 IXGBE_DCA_RXCTRL_HEAD_WRO_EN);
480 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval);
483 return IXGBE_SUCCESS;
487 * ixgbe_init_hw_generic - Generic hardware initialization
488 * @hw: pointer to hardware structure
490 * Initialize the hardware by resetting the hardware, filling the bus info
491 * structure and media type, clears all on chip counters, initializes receive
492 * address registers, multicast table, VLAN filter table, calls routine to set
493 * up link and flow control settings, and leaves transmit and receive units
494 * disabled and uninitialized
496 s32 ixgbe_init_hw_generic(struct ixgbe_hw *hw)
500 DEBUGFUNC("ixgbe_init_hw_generic");
502 /* Reset the hardware */
503 status = hw->mac.ops.reset_hw(hw);
505 if (status == IXGBE_SUCCESS || status == IXGBE_ERR_SFP_NOT_PRESENT) {
507 status = hw->mac.ops.start_hw(hw);
510 /* Initialize the LED link active for LED blink support */
511 if (hw->mac.ops.init_led_link_act)
512 hw->mac.ops.init_led_link_act(hw);
514 if (status != IXGBE_SUCCESS)
515 DEBUGOUT1("Failed to initialize HW, STATUS = %d\n", status);
521 * ixgbe_clear_hw_cntrs_generic - Generic clear hardware counters
522 * @hw: pointer to hardware structure
524 * Clears all hardware statistics counters by reading them from the hardware
525 * Statistics counters are clear on read.
527 s32 ixgbe_clear_hw_cntrs_generic(struct ixgbe_hw *hw)
531 DEBUGFUNC("ixgbe_clear_hw_cntrs_generic");
533 IXGBE_READ_REG(hw, IXGBE_CRCERRS);
534 IXGBE_READ_REG(hw, IXGBE_ILLERRC);
535 IXGBE_READ_REG(hw, IXGBE_ERRBC);
536 IXGBE_READ_REG(hw, IXGBE_MSPDC);
537 for (i = 0; i < 8; i++)
538 IXGBE_READ_REG(hw, IXGBE_MPC(i));
540 IXGBE_READ_REG(hw, IXGBE_MLFC);
541 IXGBE_READ_REG(hw, IXGBE_MRFC);
542 IXGBE_READ_REG(hw, IXGBE_RLEC);
543 IXGBE_READ_REG(hw, IXGBE_LXONTXC);
544 IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
545 if (hw->mac.type >= ixgbe_mac_82599EB) {
546 IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
547 IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
549 IXGBE_READ_REG(hw, IXGBE_LXONRXC);
550 IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
553 for (i = 0; i < 8; i++) {
554 IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
555 IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
556 if (hw->mac.type >= ixgbe_mac_82599EB) {
557 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
558 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
560 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
561 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
564 if (hw->mac.type >= ixgbe_mac_82599EB)
565 for (i = 0; i < 8; i++)
566 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
567 IXGBE_READ_REG(hw, IXGBE_PRC64);
568 IXGBE_READ_REG(hw, IXGBE_PRC127);
569 IXGBE_READ_REG(hw, IXGBE_PRC255);
570 IXGBE_READ_REG(hw, IXGBE_PRC511);
571 IXGBE_READ_REG(hw, IXGBE_PRC1023);
572 IXGBE_READ_REG(hw, IXGBE_PRC1522);
573 IXGBE_READ_REG(hw, IXGBE_GPRC);
574 IXGBE_READ_REG(hw, IXGBE_BPRC);
575 IXGBE_READ_REG(hw, IXGBE_MPRC);
576 IXGBE_READ_REG(hw, IXGBE_GPTC);
577 IXGBE_READ_REG(hw, IXGBE_GORCL);
578 IXGBE_READ_REG(hw, IXGBE_GORCH);
579 IXGBE_READ_REG(hw, IXGBE_GOTCL);
580 IXGBE_READ_REG(hw, IXGBE_GOTCH);
581 if (hw->mac.type == ixgbe_mac_82598EB)
582 for (i = 0; i < 8; i++)
583 IXGBE_READ_REG(hw, IXGBE_RNBC(i));
584 IXGBE_READ_REG(hw, IXGBE_RUC);
585 IXGBE_READ_REG(hw, IXGBE_RFC);
586 IXGBE_READ_REG(hw, IXGBE_ROC);
587 IXGBE_READ_REG(hw, IXGBE_RJC);
588 IXGBE_READ_REG(hw, IXGBE_MNGPRC);
589 IXGBE_READ_REG(hw, IXGBE_MNGPDC);
590 IXGBE_READ_REG(hw, IXGBE_MNGPTC);
591 IXGBE_READ_REG(hw, IXGBE_TORL);
592 IXGBE_READ_REG(hw, IXGBE_TORH);
593 IXGBE_READ_REG(hw, IXGBE_TPR);
594 IXGBE_READ_REG(hw, IXGBE_TPT);
595 IXGBE_READ_REG(hw, IXGBE_PTC64);
596 IXGBE_READ_REG(hw, IXGBE_PTC127);
597 IXGBE_READ_REG(hw, IXGBE_PTC255);
598 IXGBE_READ_REG(hw, IXGBE_PTC511);
599 IXGBE_READ_REG(hw, IXGBE_PTC1023);
600 IXGBE_READ_REG(hw, IXGBE_PTC1522);
601 IXGBE_READ_REG(hw, IXGBE_MPTC);
602 IXGBE_READ_REG(hw, IXGBE_BPTC);
603 for (i = 0; i < 16; i++) {
604 IXGBE_READ_REG(hw, IXGBE_QPRC(i));
605 IXGBE_READ_REG(hw, IXGBE_QPTC(i));
606 if (hw->mac.type >= ixgbe_mac_82599EB) {
607 IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
608 IXGBE_READ_REG(hw, IXGBE_QBRC_H(i));
609 IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
610 IXGBE_READ_REG(hw, IXGBE_QBTC_H(i));
611 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
613 IXGBE_READ_REG(hw, IXGBE_QBRC(i));
614 IXGBE_READ_REG(hw, IXGBE_QBTC(i));
618 if (hw->mac.type == ixgbe_mac_X550 || hw->mac.type == ixgbe_mac_X540) {
620 ixgbe_identify_phy(hw);
621 hw->phy.ops.read_reg(hw, IXGBE_PCRC8ECL,
622 IXGBE_MDIO_PCS_DEV_TYPE, &i);
623 hw->phy.ops.read_reg(hw, IXGBE_PCRC8ECH,
624 IXGBE_MDIO_PCS_DEV_TYPE, &i);
625 hw->phy.ops.read_reg(hw, IXGBE_LDPCECL,
626 IXGBE_MDIO_PCS_DEV_TYPE, &i);
627 hw->phy.ops.read_reg(hw, IXGBE_LDPCECH,
628 IXGBE_MDIO_PCS_DEV_TYPE, &i);
631 return IXGBE_SUCCESS;
635 * ixgbe_read_pba_string_generic - Reads part number string from EEPROM
636 * @hw: pointer to hardware structure
637 * @pba_num: stores the part number string from the EEPROM
638 * @pba_num_size: part number string buffer length
640 * Reads the part number string from the EEPROM.
642 s32 ixgbe_read_pba_string_generic(struct ixgbe_hw *hw, u8 *pba_num,
651 DEBUGFUNC("ixgbe_read_pba_string_generic");
653 if (pba_num == NULL) {
654 DEBUGOUT("PBA string buffer was null\n");
655 return IXGBE_ERR_INVALID_ARGUMENT;
658 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM0_PTR, &data);
660 DEBUGOUT("NVM Read Error\n");
664 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM1_PTR, &pba_ptr);
666 DEBUGOUT("NVM Read Error\n");
671 * if data is not ptr guard the PBA must be in legacy format which
672 * means pba_ptr is actually our second data word for the PBA number
673 * and we can decode it into an ascii string
675 if (data != IXGBE_PBANUM_PTR_GUARD) {
676 DEBUGOUT("NVM PBA number is not stored as string\n");
678 /* we will need 11 characters to store the PBA */
679 if (pba_num_size < 11) {
680 DEBUGOUT("PBA string buffer too small\n");
681 return IXGBE_ERR_NO_SPACE;
684 /* extract hex string from data and pba_ptr */
685 pba_num[0] = (data >> 12) & 0xF;
686 pba_num[1] = (data >> 8) & 0xF;
687 pba_num[2] = (data >> 4) & 0xF;
688 pba_num[3] = data & 0xF;
689 pba_num[4] = (pba_ptr >> 12) & 0xF;
690 pba_num[5] = (pba_ptr >> 8) & 0xF;
693 pba_num[8] = (pba_ptr >> 4) & 0xF;
694 pba_num[9] = pba_ptr & 0xF;
696 /* put a null character on the end of our string */
699 /* switch all the data but the '-' to hex char */
700 for (offset = 0; offset < 10; offset++) {
701 if (pba_num[offset] < 0xA)
702 pba_num[offset] += '0';
703 else if (pba_num[offset] < 0x10)
704 pba_num[offset] += 'A' - 0xA;
707 return IXGBE_SUCCESS;
710 ret_val = hw->eeprom.ops.read(hw, pba_ptr, &length);
712 DEBUGOUT("NVM Read Error\n");
716 if (length == 0xFFFF || length == 0) {
717 DEBUGOUT("NVM PBA number section invalid length\n");
718 return IXGBE_ERR_PBA_SECTION;
721 /* check if pba_num buffer is big enough */
722 if (pba_num_size < (((u32)length * 2) - 1)) {
723 DEBUGOUT("PBA string buffer too small\n");
724 return IXGBE_ERR_NO_SPACE;
727 /* trim pba length from start of string */
731 for (offset = 0; offset < length; offset++) {
732 ret_val = hw->eeprom.ops.read(hw, pba_ptr + offset, &data);
734 DEBUGOUT("NVM Read Error\n");
737 pba_num[offset * 2] = (u8)(data >> 8);
738 pba_num[(offset * 2) + 1] = (u8)(data & 0xFF);
740 pba_num[offset * 2] = '\0';
742 return IXGBE_SUCCESS;
746 * ixgbe_read_pba_num_generic - Reads part number from EEPROM
747 * @hw: pointer to hardware structure
748 * @pba_num: stores the part number from the EEPROM
750 * Reads the part number from the EEPROM.
752 s32 ixgbe_read_pba_num_generic(struct ixgbe_hw *hw, u32 *pba_num)
757 DEBUGFUNC("ixgbe_read_pba_num_generic");
759 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM0_PTR, &data);
761 DEBUGOUT("NVM Read Error\n");
763 } else if (data == IXGBE_PBANUM_PTR_GUARD) {
764 DEBUGOUT("NVM Not supported\n");
765 return IXGBE_NOT_IMPLEMENTED;
767 *pba_num = (u32)(data << 16);
769 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM1_PTR, &data);
771 DEBUGOUT("NVM Read Error\n");
776 return IXGBE_SUCCESS;
781 * @hw: pointer to the HW structure
782 * @eeprom_buf: optional pointer to EEPROM image
783 * @eeprom_buf_size: size of EEPROM image in words
784 * @max_pba_block_size: PBA block size limit
785 * @pba: pointer to output PBA structure
787 * Reads PBA from EEPROM image when eeprom_buf is not NULL.
788 * Reads PBA from physical EEPROM device when eeprom_buf is NULL.
791 s32 ixgbe_read_pba_raw(struct ixgbe_hw *hw, u16 *eeprom_buf,
792 u32 eeprom_buf_size, u16 max_pba_block_size,
793 struct ixgbe_pba *pba)
799 return IXGBE_ERR_PARAM;
801 if (eeprom_buf == NULL) {
802 ret_val = hw->eeprom.ops.read_buffer(hw, IXGBE_PBANUM0_PTR, 2,
807 if (eeprom_buf_size > IXGBE_PBANUM1_PTR) {
808 pba->word[0] = eeprom_buf[IXGBE_PBANUM0_PTR];
809 pba->word[1] = eeprom_buf[IXGBE_PBANUM1_PTR];
811 return IXGBE_ERR_PARAM;
815 if (pba->word[0] == IXGBE_PBANUM_PTR_GUARD) {
816 if (pba->pba_block == NULL)
817 return IXGBE_ERR_PARAM;
819 ret_val = ixgbe_get_pba_block_size(hw, eeprom_buf,
825 if (pba_block_size > max_pba_block_size)
826 return IXGBE_ERR_PARAM;
828 if (eeprom_buf == NULL) {
829 ret_val = hw->eeprom.ops.read_buffer(hw, pba->word[1],
835 if (eeprom_buf_size > (u32)(pba->word[1] +
837 memcpy(pba->pba_block,
838 &eeprom_buf[pba->word[1]],
839 pba_block_size * sizeof(u16));
841 return IXGBE_ERR_PARAM;
846 return IXGBE_SUCCESS;
850 * ixgbe_write_pba_raw
851 * @hw: pointer to the HW structure
852 * @eeprom_buf: optional pointer to EEPROM image
853 * @eeprom_buf_size: size of EEPROM image in words
854 * @pba: pointer to PBA structure
856 * Writes PBA to EEPROM image when eeprom_buf is not NULL.
857 * Writes PBA to physical EEPROM device when eeprom_buf is NULL.
860 s32 ixgbe_write_pba_raw(struct ixgbe_hw *hw, u16 *eeprom_buf,
861 u32 eeprom_buf_size, struct ixgbe_pba *pba)
866 return IXGBE_ERR_PARAM;
868 if (eeprom_buf == NULL) {
869 ret_val = hw->eeprom.ops.write_buffer(hw, IXGBE_PBANUM0_PTR, 2,
874 if (eeprom_buf_size > IXGBE_PBANUM1_PTR) {
875 eeprom_buf[IXGBE_PBANUM0_PTR] = pba->word[0];
876 eeprom_buf[IXGBE_PBANUM1_PTR] = pba->word[1];
878 return IXGBE_ERR_PARAM;
882 if (pba->word[0] == IXGBE_PBANUM_PTR_GUARD) {
883 if (pba->pba_block == NULL)
884 return IXGBE_ERR_PARAM;
886 if (eeprom_buf == NULL) {
887 ret_val = hw->eeprom.ops.write_buffer(hw, pba->word[1],
893 if (eeprom_buf_size > (u32)(pba->word[1] +
894 pba->pba_block[0])) {
895 memcpy(&eeprom_buf[pba->word[1]],
897 pba->pba_block[0] * sizeof(u16));
899 return IXGBE_ERR_PARAM;
904 return IXGBE_SUCCESS;
908 * ixgbe_get_pba_block_size
909 * @hw: pointer to the HW structure
910 * @eeprom_buf: optional pointer to EEPROM image
911 * @eeprom_buf_size: size of EEPROM image in words
912 * @pba_data_size: pointer to output variable
914 * Returns the size of the PBA block in words. Function operates on EEPROM
915 * image if the eeprom_buf pointer is not NULL otherwise it accesses physical
919 s32 ixgbe_get_pba_block_size(struct ixgbe_hw *hw, u16 *eeprom_buf,
920 u32 eeprom_buf_size, u16 *pba_block_size)
926 DEBUGFUNC("ixgbe_get_pba_block_size");
928 if (eeprom_buf == NULL) {
929 ret_val = hw->eeprom.ops.read_buffer(hw, IXGBE_PBANUM0_PTR, 2,
934 if (eeprom_buf_size > IXGBE_PBANUM1_PTR) {
935 pba_word[0] = eeprom_buf[IXGBE_PBANUM0_PTR];
936 pba_word[1] = eeprom_buf[IXGBE_PBANUM1_PTR];
938 return IXGBE_ERR_PARAM;
942 if (pba_word[0] == IXGBE_PBANUM_PTR_GUARD) {
943 if (eeprom_buf == NULL) {
944 ret_val = hw->eeprom.ops.read(hw, pba_word[1] + 0,
949 if (eeprom_buf_size > pba_word[1])
950 length = eeprom_buf[pba_word[1] + 0];
952 return IXGBE_ERR_PARAM;
955 if (length == 0xFFFF || length == 0)
956 return IXGBE_ERR_PBA_SECTION;
958 /* PBA number in legacy format, there is no PBA Block. */
962 if (pba_block_size != NULL)
963 *pba_block_size = length;
965 return IXGBE_SUCCESS;
969 * ixgbe_get_mac_addr_generic - Generic get MAC address
970 * @hw: pointer to hardware structure
971 * @mac_addr: Adapter MAC address
973 * Reads the adapter's MAC address from first Receive Address Register (RAR0)
974 * A reset of the adapter must be performed prior to calling this function
975 * in order for the MAC address to have been loaded from the EEPROM into RAR0
977 s32 ixgbe_get_mac_addr_generic(struct ixgbe_hw *hw, u8 *mac_addr)
983 DEBUGFUNC("ixgbe_get_mac_addr_generic");
985 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(0));
986 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(0));
988 for (i = 0; i < 4; i++)
989 mac_addr[i] = (u8)(rar_low >> (i*8));
991 for (i = 0; i < 2; i++)
992 mac_addr[i+4] = (u8)(rar_high >> (i*8));
994 return IXGBE_SUCCESS;
998 * ixgbe_set_pci_config_data_generic - Generic store PCI bus info
999 * @hw: pointer to hardware structure
1000 * @link_status: the link status returned by the PCI config space
1002 * Stores the PCI bus info (speed, width, type) within the ixgbe_hw structure
1004 void ixgbe_set_pci_config_data_generic(struct ixgbe_hw *hw, u16 link_status)
1006 struct ixgbe_mac_info *mac = &hw->mac;
1008 if (hw->bus.type == ixgbe_bus_type_unknown)
1009 hw->bus.type = ixgbe_bus_type_pci_express;
1011 switch (link_status & IXGBE_PCI_LINK_WIDTH) {
1012 case IXGBE_PCI_LINK_WIDTH_1:
1013 hw->bus.width = ixgbe_bus_width_pcie_x1;
1015 case IXGBE_PCI_LINK_WIDTH_2:
1016 hw->bus.width = ixgbe_bus_width_pcie_x2;
1018 case IXGBE_PCI_LINK_WIDTH_4:
1019 hw->bus.width = ixgbe_bus_width_pcie_x4;
1021 case IXGBE_PCI_LINK_WIDTH_8:
1022 hw->bus.width = ixgbe_bus_width_pcie_x8;
1025 hw->bus.width = ixgbe_bus_width_unknown;
1029 switch (link_status & IXGBE_PCI_LINK_SPEED) {
1030 case IXGBE_PCI_LINK_SPEED_2500:
1031 hw->bus.speed = ixgbe_bus_speed_2500;
1033 case IXGBE_PCI_LINK_SPEED_5000:
1034 hw->bus.speed = ixgbe_bus_speed_5000;
1036 case IXGBE_PCI_LINK_SPEED_8000:
1037 hw->bus.speed = ixgbe_bus_speed_8000;
1040 hw->bus.speed = ixgbe_bus_speed_unknown;
1044 mac->ops.set_lan_id(hw);
1048 * ixgbe_get_bus_info_generic - Generic set PCI bus info
1049 * @hw: pointer to hardware structure
1051 * Gets the PCI bus info (speed, width, type) then calls helper function to
1052 * store this data within the ixgbe_hw structure.
1054 s32 ixgbe_get_bus_info_generic(struct ixgbe_hw *hw)
1058 DEBUGFUNC("ixgbe_get_bus_info_generic");
1060 /* Get the negotiated link width and speed from PCI config space */
1061 link_status = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_LINK_STATUS);
1063 ixgbe_set_pci_config_data_generic(hw, link_status);
1065 return IXGBE_SUCCESS;
1069 * ixgbe_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port devices
1070 * @hw: pointer to the HW structure
1072 * Determines the LAN function id by reading memory-mapped registers and swaps
1073 * the port value if requested, and set MAC instance for devices that share
1076 void ixgbe_set_lan_id_multi_port_pcie(struct ixgbe_hw *hw)
1078 struct ixgbe_bus_info *bus = &hw->bus;
1082 DEBUGFUNC("ixgbe_set_lan_id_multi_port_pcie");
1084 reg = IXGBE_READ_REG(hw, IXGBE_STATUS);
1085 bus->func = (reg & IXGBE_STATUS_LAN_ID) >> IXGBE_STATUS_LAN_ID_SHIFT;
1086 bus->lan_id = (u8)bus->func;
1088 /* check for a port swap */
1089 reg = IXGBE_READ_REG(hw, IXGBE_FACTPS_BY_MAC(hw));
1090 if (reg & IXGBE_FACTPS_LFS)
1093 /* Get MAC instance from EEPROM for configuring CS4227 */
1094 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP) {
1095 hw->eeprom.ops.read(hw, IXGBE_EEPROM_CTRL_4, &ee_ctrl_4);
1096 bus->instance_id = (ee_ctrl_4 & IXGBE_EE_CTRL_4_INST_ID) >>
1097 IXGBE_EE_CTRL_4_INST_ID_SHIFT;
1102 * ixgbe_stop_adapter_generic - Generic stop Tx/Rx units
1103 * @hw: pointer to hardware structure
1105 * Sets the adapter_stopped flag within ixgbe_hw struct. Clears interrupts,
1106 * disables transmit and receive units. The adapter_stopped flag is used by
1107 * the shared code and drivers to determine if the adapter is in a stopped
1108 * state and should not touch the hardware.
1110 s32 ixgbe_stop_adapter_generic(struct ixgbe_hw *hw)
1115 DEBUGFUNC("ixgbe_stop_adapter_generic");
1118 * Set the adapter_stopped flag so other driver functions stop touching
1121 hw->adapter_stopped = TRUE;
1123 /* Disable the receive unit */
1124 ixgbe_disable_rx(hw);
1126 /* Clear interrupt mask to stop interrupts from being generated */
1127 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
1129 /* Clear any pending interrupts, flush previous writes */
1130 IXGBE_READ_REG(hw, IXGBE_EICR);
1132 /* Disable the transmit unit. Each queue must be disabled. */
1133 for (i = 0; i < hw->mac.max_tx_queues; i++)
1134 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(i), IXGBE_TXDCTL_SWFLSH);
1136 /* Disable the receive unit by stopping each queue */
1137 for (i = 0; i < hw->mac.max_rx_queues; i++) {
1138 reg_val = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1139 reg_val &= ~IXGBE_RXDCTL_ENABLE;
1140 reg_val |= IXGBE_RXDCTL_SWFLSH;
1141 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), reg_val);
1144 /* flush all queues disables */
1145 IXGBE_WRITE_FLUSH(hw);
1149 * Prevent the PCI-E bus from hanging by disabling PCI-E master
1150 * access and verify no pending requests
1152 return ixgbe_disable_pcie_master(hw);
1156 * ixgbe_init_led_link_act_generic - Store the LED index link/activity.
1157 * @hw: pointer to hardware structure
1159 * Store the index for the link active LED. This will be used to support
1162 s32 ixgbe_init_led_link_act_generic(struct ixgbe_hw *hw)
1164 struct ixgbe_mac_info *mac = &hw->mac;
1165 u32 led_reg, led_mode;
1168 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
1170 /* Get LED link active from the LEDCTL register */
1171 for (i = 0; i < 4; i++) {
1172 led_mode = led_reg >> IXGBE_LED_MODE_SHIFT(i);
1174 if ((led_mode & IXGBE_LED_MODE_MASK_BASE) ==
1175 IXGBE_LED_LINK_ACTIVE) {
1176 mac->led_link_act = i;
1177 return IXGBE_SUCCESS;
1182 * If LEDCTL register does not have the LED link active set, then use
1183 * known MAC defaults.
1185 switch (hw->mac.type) {
1186 case ixgbe_mac_X550EM_a:
1187 case ixgbe_mac_X550EM_x:
1188 mac->led_link_act = 1;
1191 mac->led_link_act = 2;
1193 return IXGBE_SUCCESS;
1197 * ixgbe_led_on_generic - Turns on the software controllable LEDs.
1198 * @hw: pointer to hardware structure
1199 * @index: led number to turn on
1201 s32 ixgbe_led_on_generic(struct ixgbe_hw *hw, u32 index)
1203 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
1205 DEBUGFUNC("ixgbe_led_on_generic");
1208 return IXGBE_ERR_PARAM;
1210 /* To turn on the LED, set mode to ON. */
1211 led_reg &= ~IXGBE_LED_MODE_MASK(index);
1212 led_reg |= IXGBE_LED_ON << IXGBE_LED_MODE_SHIFT(index);
1213 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
1214 IXGBE_WRITE_FLUSH(hw);
1216 return IXGBE_SUCCESS;
1220 * ixgbe_led_off_generic - Turns off the software controllable LEDs.
1221 * @hw: pointer to hardware structure
1222 * @index: led number to turn off
1224 s32 ixgbe_led_off_generic(struct ixgbe_hw *hw, u32 index)
1226 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
1228 DEBUGFUNC("ixgbe_led_off_generic");
1231 return IXGBE_ERR_PARAM;
1233 /* To turn off the LED, set mode to OFF. */
1234 led_reg &= ~IXGBE_LED_MODE_MASK(index);
1235 led_reg |= IXGBE_LED_OFF << IXGBE_LED_MODE_SHIFT(index);
1236 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
1237 IXGBE_WRITE_FLUSH(hw);
1239 return IXGBE_SUCCESS;
1243 * ixgbe_init_eeprom_params_generic - Initialize EEPROM params
1244 * @hw: pointer to hardware structure
1246 * Initializes the EEPROM parameters ixgbe_eeprom_info within the
1247 * ixgbe_hw struct in order to set up EEPROM access.
1249 s32 ixgbe_init_eeprom_params_generic(struct ixgbe_hw *hw)
1251 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
1255 DEBUGFUNC("ixgbe_init_eeprom_params_generic");
1257 if (eeprom->type == ixgbe_eeprom_uninitialized) {
1258 eeprom->type = ixgbe_eeprom_none;
1259 /* Set default semaphore delay to 10ms which is a well
1261 eeprom->semaphore_delay = 10;
1262 /* Clear EEPROM page size, it will be initialized as needed */
1263 eeprom->word_page_size = 0;
1266 * Check for EEPROM present first.
1267 * If not present leave as none
1269 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
1270 if (eec & IXGBE_EEC_PRES) {
1271 eeprom->type = ixgbe_eeprom_spi;
1274 * SPI EEPROM is assumed here. This code would need to
1275 * change if a future EEPROM is not SPI.
1277 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
1278 IXGBE_EEC_SIZE_SHIFT);
1279 eeprom->word_size = 1 << (eeprom_size +
1280 IXGBE_EEPROM_WORD_SIZE_SHIFT);
1283 if (eec & IXGBE_EEC_ADDR_SIZE)
1284 eeprom->address_bits = 16;
1286 eeprom->address_bits = 8;
1287 DEBUGOUT3("Eeprom params: type = %d, size = %d, address bits: "
1288 "%d\n", eeprom->type, eeprom->word_size,
1289 eeprom->address_bits);
1292 return IXGBE_SUCCESS;
1296 * ixgbe_write_eeprom_buffer_bit_bang_generic - Write EEPROM using bit-bang
1297 * @hw: pointer to hardware structure
1298 * @offset: offset within the EEPROM to write
1299 * @words: number of word(s)
1300 * @data: 16 bit word(s) to write to EEPROM
1302 * Reads 16 bit word(s) from EEPROM through bit-bang method
1304 s32 ixgbe_write_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
1305 u16 words, u16 *data)
1307 s32 status = IXGBE_SUCCESS;
1310 DEBUGFUNC("ixgbe_write_eeprom_buffer_bit_bang_generic");
1312 hw->eeprom.ops.init_params(hw);
1315 status = IXGBE_ERR_INVALID_ARGUMENT;
1319 if (offset + words > hw->eeprom.word_size) {
1320 status = IXGBE_ERR_EEPROM;
1325 * The EEPROM page size cannot be queried from the chip. We do lazy
1326 * initialization. It is worth to do that when we write large buffer.
1328 if ((hw->eeprom.word_page_size == 0) &&
1329 (words > IXGBE_EEPROM_PAGE_SIZE_MAX))
1330 ixgbe_detect_eeprom_page_size_generic(hw, offset);
1333 * We cannot hold synchronization semaphores for too long
1334 * to avoid other entity starvation. However it is more efficient
1335 * to read in bursts than synchronizing access for each word.
1337 for (i = 0; i < words; i += IXGBE_EEPROM_RD_BUFFER_MAX_COUNT) {
1338 count = (words - i) / IXGBE_EEPROM_RD_BUFFER_MAX_COUNT > 0 ?
1339 IXGBE_EEPROM_RD_BUFFER_MAX_COUNT : (words - i);
1340 status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset + i,
1343 if (status != IXGBE_SUCCESS)
1352 * ixgbe_write_eeprom_buffer_bit_bang - Writes 16 bit word(s) to EEPROM
1353 * @hw: pointer to hardware structure
1354 * @offset: offset within the EEPROM to be written to
1355 * @words: number of word(s)
1356 * @data: 16 bit word(s) to be written to the EEPROM
1358 * If ixgbe_eeprom_update_checksum is not called after this function, the
1359 * EEPROM will most likely contain an invalid checksum.
1361 static s32 ixgbe_write_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
1362 u16 words, u16 *data)
1368 u8 write_opcode = IXGBE_EEPROM_WRITE_OPCODE_SPI;
1370 DEBUGFUNC("ixgbe_write_eeprom_buffer_bit_bang");
1372 /* Prepare the EEPROM for writing */
1373 status = ixgbe_acquire_eeprom(hw);
1375 if (status == IXGBE_SUCCESS) {
1376 if (ixgbe_ready_eeprom(hw) != IXGBE_SUCCESS) {
1377 ixgbe_release_eeprom(hw);
1378 status = IXGBE_ERR_EEPROM;
1382 if (status == IXGBE_SUCCESS) {
1383 for (i = 0; i < words; i++) {
1384 ixgbe_standby_eeprom(hw);
1386 /* Send the WRITE ENABLE command (8 bit opcode ) */
1387 ixgbe_shift_out_eeprom_bits(hw,
1388 IXGBE_EEPROM_WREN_OPCODE_SPI,
1389 IXGBE_EEPROM_OPCODE_BITS);
1391 ixgbe_standby_eeprom(hw);
1394 * Some SPI eeproms use the 8th address bit embedded
1397 if ((hw->eeprom.address_bits == 8) &&
1398 ((offset + i) >= 128))
1399 write_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI;
1401 /* Send the Write command (8-bit opcode + addr) */
1402 ixgbe_shift_out_eeprom_bits(hw, write_opcode,
1403 IXGBE_EEPROM_OPCODE_BITS);
1404 ixgbe_shift_out_eeprom_bits(hw, (u16)((offset + i) * 2),
1405 hw->eeprom.address_bits);
1407 page_size = hw->eeprom.word_page_size;
1409 /* Send the data in burst via SPI*/
1412 word = (word >> 8) | (word << 8);
1413 ixgbe_shift_out_eeprom_bits(hw, word, 16);
1418 /* do not wrap around page */
1419 if (((offset + i) & (page_size - 1)) ==
1422 } while (++i < words);
1424 ixgbe_standby_eeprom(hw);
1427 /* Done with writing - release the EEPROM */
1428 ixgbe_release_eeprom(hw);
1435 * ixgbe_write_eeprom_generic - Writes 16 bit value to EEPROM
1436 * @hw: pointer to hardware structure
1437 * @offset: offset within the EEPROM to be written to
1438 * @data: 16 bit word to be written to the EEPROM
1440 * If ixgbe_eeprom_update_checksum is not called after this function, the
1441 * EEPROM will most likely contain an invalid checksum.
1443 s32 ixgbe_write_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 data)
1447 DEBUGFUNC("ixgbe_write_eeprom_generic");
1449 hw->eeprom.ops.init_params(hw);
1451 if (offset >= hw->eeprom.word_size) {
1452 status = IXGBE_ERR_EEPROM;
1456 status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset, 1, &data);
1463 * ixgbe_read_eeprom_buffer_bit_bang_generic - Read EEPROM using bit-bang
1464 * @hw: pointer to hardware structure
1465 * @offset: offset within the EEPROM to be read
1466 * @data: read 16 bit words(s) from EEPROM
1467 * @words: number of word(s)
1469 * Reads 16 bit word(s) from EEPROM through bit-bang method
1471 s32 ixgbe_read_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
1472 u16 words, u16 *data)
1474 s32 status = IXGBE_SUCCESS;
1477 DEBUGFUNC("ixgbe_read_eeprom_buffer_bit_bang_generic");
1479 hw->eeprom.ops.init_params(hw);
1482 status = IXGBE_ERR_INVALID_ARGUMENT;
1486 if (offset + words > hw->eeprom.word_size) {
1487 status = IXGBE_ERR_EEPROM;
1492 * We cannot hold synchronization semaphores for too long
1493 * to avoid other entity starvation. However it is more efficient
1494 * to read in bursts than synchronizing access for each word.
1496 for (i = 0; i < words; i += IXGBE_EEPROM_RD_BUFFER_MAX_COUNT) {
1497 count = (words - i) / IXGBE_EEPROM_RD_BUFFER_MAX_COUNT > 0 ?
1498 IXGBE_EEPROM_RD_BUFFER_MAX_COUNT : (words - i);
1500 status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset + i,
1503 if (status != IXGBE_SUCCESS)
1512 * ixgbe_read_eeprom_buffer_bit_bang - Read EEPROM using bit-bang
1513 * @hw: pointer to hardware structure
1514 * @offset: offset within the EEPROM to be read
1515 * @words: number of word(s)
1516 * @data: read 16 bit word(s) from EEPROM
1518 * Reads 16 bit word(s) from EEPROM through bit-bang method
1520 static s32 ixgbe_read_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
1521 u16 words, u16 *data)
1525 u8 read_opcode = IXGBE_EEPROM_READ_OPCODE_SPI;
1528 DEBUGFUNC("ixgbe_read_eeprom_buffer_bit_bang");
1530 /* Prepare the EEPROM for reading */
1531 status = ixgbe_acquire_eeprom(hw);
1533 if (status == IXGBE_SUCCESS) {
1534 if (ixgbe_ready_eeprom(hw) != IXGBE_SUCCESS) {
1535 ixgbe_release_eeprom(hw);
1536 status = IXGBE_ERR_EEPROM;
1540 if (status == IXGBE_SUCCESS) {
1541 for (i = 0; i < words; i++) {
1542 ixgbe_standby_eeprom(hw);
1544 * Some SPI eeproms use the 8th address bit embedded
1547 if ((hw->eeprom.address_bits == 8) &&
1548 ((offset + i) >= 128))
1549 read_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI;
1551 /* Send the READ command (opcode + addr) */
1552 ixgbe_shift_out_eeprom_bits(hw, read_opcode,
1553 IXGBE_EEPROM_OPCODE_BITS);
1554 ixgbe_shift_out_eeprom_bits(hw, (u16)((offset + i) * 2),
1555 hw->eeprom.address_bits);
1557 /* Read the data. */
1558 word_in = ixgbe_shift_in_eeprom_bits(hw, 16);
1559 data[i] = (word_in >> 8) | (word_in << 8);
1562 /* End this read operation */
1563 ixgbe_release_eeprom(hw);
1570 * ixgbe_read_eeprom_bit_bang_generic - Read EEPROM word using bit-bang
1571 * @hw: pointer to hardware structure
1572 * @offset: offset within the EEPROM to be read
1573 * @data: read 16 bit value from EEPROM
1575 * Reads 16 bit value from EEPROM through bit-bang method
1577 s32 ixgbe_read_eeprom_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
1582 DEBUGFUNC("ixgbe_read_eeprom_bit_bang_generic");
1584 hw->eeprom.ops.init_params(hw);
1586 if (offset >= hw->eeprom.word_size) {
1587 status = IXGBE_ERR_EEPROM;
1591 status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset, 1, data);
1598 * ixgbe_read_eerd_buffer_generic - Read EEPROM word(s) using EERD
1599 * @hw: pointer to hardware structure
1600 * @offset: offset of word in the EEPROM to read
1601 * @words: number of word(s)
1602 * @data: 16 bit word(s) from the EEPROM
1604 * Reads a 16 bit word(s) from the EEPROM using the EERD register.
1606 s32 ixgbe_read_eerd_buffer_generic(struct ixgbe_hw *hw, u16 offset,
1607 u16 words, u16 *data)
1610 s32 status = IXGBE_SUCCESS;
1613 DEBUGFUNC("ixgbe_read_eerd_buffer_generic");
1615 hw->eeprom.ops.init_params(hw);
1618 status = IXGBE_ERR_INVALID_ARGUMENT;
1619 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT, "Invalid EEPROM words");
1623 if (offset >= hw->eeprom.word_size) {
1624 status = IXGBE_ERR_EEPROM;
1625 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT, "Invalid EEPROM offset");
1629 for (i = 0; i < words; i++) {
1630 eerd = ((offset + i) << IXGBE_EEPROM_RW_ADDR_SHIFT) |
1631 IXGBE_EEPROM_RW_REG_START;
1633 IXGBE_WRITE_REG(hw, IXGBE_EERD, eerd);
1634 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_READ);
1636 if (status == IXGBE_SUCCESS) {
1637 data[i] = (IXGBE_READ_REG(hw, IXGBE_EERD) >>
1638 IXGBE_EEPROM_RW_REG_DATA);
1640 DEBUGOUT("Eeprom read timed out\n");
1649 * ixgbe_detect_eeprom_page_size_generic - Detect EEPROM page size
1650 * @hw: pointer to hardware structure
1651 * @offset: offset within the EEPROM to be used as a scratch pad
1653 * Discover EEPROM page size by writing marching data at given offset.
1654 * This function is called only when we are writing a new large buffer
1655 * at given offset so the data would be overwritten anyway.
1657 static s32 ixgbe_detect_eeprom_page_size_generic(struct ixgbe_hw *hw,
1660 u16 data[IXGBE_EEPROM_PAGE_SIZE_MAX];
1661 s32 status = IXGBE_SUCCESS;
1664 DEBUGFUNC("ixgbe_detect_eeprom_page_size_generic");
1666 for (i = 0; i < IXGBE_EEPROM_PAGE_SIZE_MAX; i++)
1669 hw->eeprom.word_page_size = IXGBE_EEPROM_PAGE_SIZE_MAX;
1670 status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset,
1671 IXGBE_EEPROM_PAGE_SIZE_MAX, data);
1672 hw->eeprom.word_page_size = 0;
1673 if (status != IXGBE_SUCCESS)
1676 status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset, 1, data);
1677 if (status != IXGBE_SUCCESS)
1681 * When writing in burst more than the actual page size
1682 * EEPROM address wraps around current page.
1684 hw->eeprom.word_page_size = IXGBE_EEPROM_PAGE_SIZE_MAX - data[0];
1686 DEBUGOUT1("Detected EEPROM page size = %d words.",
1687 hw->eeprom.word_page_size);
1693 * ixgbe_read_eerd_generic - Read EEPROM word using EERD
1694 * @hw: pointer to hardware structure
1695 * @offset: offset of word in the EEPROM to read
1696 * @data: word read from the EEPROM
1698 * Reads a 16 bit word from the EEPROM using the EERD register.
1700 s32 ixgbe_read_eerd_generic(struct ixgbe_hw *hw, u16 offset, u16 *data)
1702 return ixgbe_read_eerd_buffer_generic(hw, offset, 1, data);
1706 * ixgbe_write_eewr_buffer_generic - Write EEPROM word(s) using EEWR
1707 * @hw: pointer to hardware structure
1708 * @offset: offset of word in the EEPROM to write
1709 * @words: number of word(s)
1710 * @data: word(s) write to the EEPROM
1712 * Write a 16 bit word(s) to the EEPROM using the EEWR register.
1714 s32 ixgbe_write_eewr_buffer_generic(struct ixgbe_hw *hw, u16 offset,
1715 u16 words, u16 *data)
1718 s32 status = IXGBE_SUCCESS;
1721 DEBUGFUNC("ixgbe_write_eewr_generic");
1723 hw->eeprom.ops.init_params(hw);
1726 status = IXGBE_ERR_INVALID_ARGUMENT;
1727 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT, "Invalid EEPROM words");
1731 if (offset >= hw->eeprom.word_size) {
1732 status = IXGBE_ERR_EEPROM;
1733 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT, "Invalid EEPROM offset");
1737 for (i = 0; i < words; i++) {
1738 eewr = ((offset + i) << IXGBE_EEPROM_RW_ADDR_SHIFT) |
1739 (data[i] << IXGBE_EEPROM_RW_REG_DATA) |
1740 IXGBE_EEPROM_RW_REG_START;
1742 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_WRITE);
1743 if (status != IXGBE_SUCCESS) {
1744 DEBUGOUT("Eeprom write EEWR timed out\n");
1748 IXGBE_WRITE_REG(hw, IXGBE_EEWR, eewr);
1750 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_WRITE);
1751 if (status != IXGBE_SUCCESS) {
1752 DEBUGOUT("Eeprom write EEWR timed out\n");
1762 * ixgbe_write_eewr_generic - Write EEPROM word using EEWR
1763 * @hw: pointer to hardware structure
1764 * @offset: offset of word in the EEPROM to write
1765 * @data: word write to the EEPROM
1767 * Write a 16 bit word to the EEPROM using the EEWR register.
1769 s32 ixgbe_write_eewr_generic(struct ixgbe_hw *hw, u16 offset, u16 data)
1771 return ixgbe_write_eewr_buffer_generic(hw, offset, 1, &data);
1775 * ixgbe_poll_eerd_eewr_done - Poll EERD read or EEWR write status
1776 * @hw: pointer to hardware structure
1777 * @ee_reg: EEPROM flag for polling
1779 * Polls the status bit (bit 1) of the EERD or EEWR to determine when the
1780 * read or write is done respectively.
1782 s32 ixgbe_poll_eerd_eewr_done(struct ixgbe_hw *hw, u32 ee_reg)
1786 s32 status = IXGBE_ERR_EEPROM;
1788 DEBUGFUNC("ixgbe_poll_eerd_eewr_done");
1790 for (i = 0; i < IXGBE_EERD_EEWR_ATTEMPTS; i++) {
1791 if (ee_reg == IXGBE_NVM_POLL_READ)
1792 reg = IXGBE_READ_REG(hw, IXGBE_EERD);
1794 reg = IXGBE_READ_REG(hw, IXGBE_EEWR);
1796 if (reg & IXGBE_EEPROM_RW_REG_DONE) {
1797 status = IXGBE_SUCCESS;
1803 if (i == IXGBE_EERD_EEWR_ATTEMPTS)
1804 ERROR_REPORT1(IXGBE_ERROR_POLLING,
1805 "EEPROM read/write done polling timed out");
1811 * ixgbe_acquire_eeprom - Acquire EEPROM using bit-bang
1812 * @hw: pointer to hardware structure
1814 * Prepares EEPROM for access using bit-bang method. This function should
1815 * be called before issuing a command to the EEPROM.
1817 static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw)
1819 s32 status = IXGBE_SUCCESS;
1823 DEBUGFUNC("ixgbe_acquire_eeprom");
1825 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM)
1827 status = IXGBE_ERR_SWFW_SYNC;
1829 if (status == IXGBE_SUCCESS) {
1830 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
1832 /* Request EEPROM Access */
1833 eec |= IXGBE_EEC_REQ;
1834 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec);
1836 for (i = 0; i < IXGBE_EEPROM_GRANT_ATTEMPTS; i++) {
1837 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
1838 if (eec & IXGBE_EEC_GNT)
1843 /* Release if grant not acquired */
1844 if (!(eec & IXGBE_EEC_GNT)) {
1845 eec &= ~IXGBE_EEC_REQ;
1846 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec);
1847 DEBUGOUT("Could not acquire EEPROM grant\n");
1849 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1850 status = IXGBE_ERR_EEPROM;
1853 /* Setup EEPROM for Read/Write */
1854 if (status == IXGBE_SUCCESS) {
1855 /* Clear CS and SK */
1856 eec &= ~(IXGBE_EEC_CS | IXGBE_EEC_SK);
1857 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec);
1858 IXGBE_WRITE_FLUSH(hw);
1866 * ixgbe_get_eeprom_semaphore - Get hardware semaphore
1867 * @hw: pointer to hardware structure
1869 * Sets the hardware semaphores so EEPROM access can occur for bit-bang method
1871 static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw)
1873 s32 status = IXGBE_ERR_EEPROM;
1878 DEBUGFUNC("ixgbe_get_eeprom_semaphore");
1881 /* Get SMBI software semaphore between device drivers first */
1882 for (i = 0; i < timeout; i++) {
1884 * If the SMBI bit is 0 when we read it, then the bit will be
1885 * set and we have the semaphore
1887 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM_BY_MAC(hw));
1888 if (!(swsm & IXGBE_SWSM_SMBI)) {
1889 status = IXGBE_SUCCESS;
1896 DEBUGOUT("Driver can't access the Eeprom - SMBI Semaphore "
1899 * this release is particularly important because our attempts
1900 * above to get the semaphore may have succeeded, and if there
1901 * was a timeout, we should unconditionally clear the semaphore
1902 * bits to free the driver to make progress
1904 ixgbe_release_eeprom_semaphore(hw);
1909 * If the SMBI bit is 0 when we read it, then the bit will be
1910 * set and we have the semaphore
1912 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM_BY_MAC(hw));
1913 if (!(swsm & IXGBE_SWSM_SMBI))
1914 status = IXGBE_SUCCESS;
1917 /* Now get the semaphore between SW/FW through the SWESMBI bit */
1918 if (status == IXGBE_SUCCESS) {
1919 for (i = 0; i < timeout; i++) {
1920 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM_BY_MAC(hw));
1922 /* Set the SW EEPROM semaphore bit to request access */
1923 swsm |= IXGBE_SWSM_SWESMBI;
1924 IXGBE_WRITE_REG(hw, IXGBE_SWSM_BY_MAC(hw), swsm);
1927 * If we set the bit successfully then we got the
1930 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM_BY_MAC(hw));
1931 if (swsm & IXGBE_SWSM_SWESMBI)
1938 * Release semaphores and return error if SW EEPROM semaphore
1939 * was not granted because we don't have access to the EEPROM
1942 ERROR_REPORT1(IXGBE_ERROR_POLLING,
1943 "SWESMBI Software EEPROM semaphore not granted.\n");
1944 ixgbe_release_eeprom_semaphore(hw);
1945 status = IXGBE_ERR_EEPROM;
1948 ERROR_REPORT1(IXGBE_ERROR_POLLING,
1949 "Software semaphore SMBI between device drivers "
1957 * ixgbe_release_eeprom_semaphore - Release hardware semaphore
1958 * @hw: pointer to hardware structure
1960 * This function clears hardware semaphore bits.
1962 static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw)
1966 DEBUGFUNC("ixgbe_release_eeprom_semaphore");
1968 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
1970 /* Release both semaphores by writing 0 to the bits SWESMBI and SMBI */
1971 swsm &= ~(IXGBE_SWSM_SWESMBI | IXGBE_SWSM_SMBI);
1972 IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm);
1973 IXGBE_WRITE_FLUSH(hw);
1977 * ixgbe_ready_eeprom - Polls for EEPROM ready
1978 * @hw: pointer to hardware structure
1980 static s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw)
1982 s32 status = IXGBE_SUCCESS;
1986 DEBUGFUNC("ixgbe_ready_eeprom");
1989 * Read "Status Register" repeatedly until the LSB is cleared. The
1990 * EEPROM will signal that the command has been completed by clearing
1991 * bit 0 of the internal status register. If it's not cleared within
1992 * 5 milliseconds, then error out.
1994 for (i = 0; i < IXGBE_EEPROM_MAX_RETRY_SPI; i += 5) {
1995 ixgbe_shift_out_eeprom_bits(hw, IXGBE_EEPROM_RDSR_OPCODE_SPI,
1996 IXGBE_EEPROM_OPCODE_BITS);
1997 spi_stat_reg = (u8)ixgbe_shift_in_eeprom_bits(hw, 8);
1998 if (!(spi_stat_reg & IXGBE_EEPROM_STATUS_RDY_SPI))
2002 ixgbe_standby_eeprom(hw);
2006 * On some parts, SPI write time could vary from 0-20mSec on 3.3V
2007 * devices (and only 0-5mSec on 5V devices)
2009 if (i >= IXGBE_EEPROM_MAX_RETRY_SPI) {
2010 DEBUGOUT("SPI EEPROM Status error\n");
2011 status = IXGBE_ERR_EEPROM;
2018 * ixgbe_standby_eeprom - Returns EEPROM to a "standby" state
2019 * @hw: pointer to hardware structure
2021 static void ixgbe_standby_eeprom(struct ixgbe_hw *hw)
2025 DEBUGFUNC("ixgbe_standby_eeprom");
2027 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
2029 /* Toggle CS to flush commands */
2030 eec |= IXGBE_EEC_CS;
2031 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec);
2032 IXGBE_WRITE_FLUSH(hw);
2034 eec &= ~IXGBE_EEC_CS;
2035 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec);
2036 IXGBE_WRITE_FLUSH(hw);
2041 * ixgbe_shift_out_eeprom_bits - Shift data bits out to the EEPROM.
2042 * @hw: pointer to hardware structure
2043 * @data: data to send to the EEPROM
2044 * @count: number of bits to shift out
2046 static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data,
2053 DEBUGFUNC("ixgbe_shift_out_eeprom_bits");
2055 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
2058 * Mask is used to shift "count" bits of "data" out to the EEPROM
2059 * one bit at a time. Determine the starting bit based on count
2061 mask = 0x01 << (count - 1);
2063 for (i = 0; i < count; i++) {
2065 * A "1" is shifted out to the EEPROM by setting bit "DI" to a
2066 * "1", and then raising and then lowering the clock (the SK
2067 * bit controls the clock input to the EEPROM). A "0" is
2068 * shifted out to the EEPROM by setting "DI" to "0" and then
2069 * raising and then lowering the clock.
2072 eec |= IXGBE_EEC_DI;
2074 eec &= ~IXGBE_EEC_DI;
2076 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec);
2077 IXGBE_WRITE_FLUSH(hw);
2081 ixgbe_raise_eeprom_clk(hw, &eec);
2082 ixgbe_lower_eeprom_clk(hw, &eec);
2085 * Shift mask to signify next bit of data to shift in to the
2091 /* We leave the "DI" bit set to "0" when we leave this routine. */
2092 eec &= ~IXGBE_EEC_DI;
2093 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec);
2094 IXGBE_WRITE_FLUSH(hw);
2098 * ixgbe_shift_in_eeprom_bits - Shift data bits in from the EEPROM
2099 * @hw: pointer to hardware structure
2100 * @count: number of bits to shift
2102 static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count)
2108 DEBUGFUNC("ixgbe_shift_in_eeprom_bits");
2111 * In order to read a register from the EEPROM, we need to shift
2112 * 'count' bits in from the EEPROM. Bits are "shifted in" by raising
2113 * the clock input to the EEPROM (setting the SK bit), and then reading
2114 * the value of the "DO" bit. During this "shifting in" process the
2115 * "DI" bit should always be clear.
2117 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
2119 eec &= ~(IXGBE_EEC_DO | IXGBE_EEC_DI);
2121 for (i = 0; i < count; i++) {
2123 ixgbe_raise_eeprom_clk(hw, &eec);
2125 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
2127 eec &= ~(IXGBE_EEC_DI);
2128 if (eec & IXGBE_EEC_DO)
2131 ixgbe_lower_eeprom_clk(hw, &eec);
2138 * ixgbe_raise_eeprom_clk - Raises the EEPROM's clock input.
2139 * @hw: pointer to hardware structure
2140 * @eec: EEC register's current value
2142 static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec)
2144 DEBUGFUNC("ixgbe_raise_eeprom_clk");
2147 * Raise the clock input to the EEPROM
2148 * (setting the SK bit), then delay
2150 *eec = *eec | IXGBE_EEC_SK;
2151 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), *eec);
2152 IXGBE_WRITE_FLUSH(hw);
2157 * ixgbe_lower_eeprom_clk - Lowers the EEPROM's clock input.
2158 * @hw: pointer to hardware structure
2159 * @eec: EEC's current value
2161 static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec)
2163 DEBUGFUNC("ixgbe_lower_eeprom_clk");
2166 * Lower the clock input to the EEPROM (clearing the SK bit), then
2169 *eec = *eec & ~IXGBE_EEC_SK;
2170 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), *eec);
2171 IXGBE_WRITE_FLUSH(hw);
2176 * ixgbe_release_eeprom - Release EEPROM, release semaphores
2177 * @hw: pointer to hardware structure
2179 static void ixgbe_release_eeprom(struct ixgbe_hw *hw)
2183 DEBUGFUNC("ixgbe_release_eeprom");
2185 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
2187 eec |= IXGBE_EEC_CS; /* Pull CS high */
2188 eec &= ~IXGBE_EEC_SK; /* Lower SCK */
2190 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec);
2191 IXGBE_WRITE_FLUSH(hw);
2195 /* Stop requesting EEPROM access */
2196 eec &= ~IXGBE_EEC_REQ;
2197 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec);
2199 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2201 /* Delay before attempt to obtain semaphore again to allow FW access */
2202 msec_delay(hw->eeprom.semaphore_delay);
2206 * ixgbe_calc_eeprom_checksum_generic - Calculates and returns the checksum
2207 * @hw: pointer to hardware structure
2209 * Returns a negative error code on error, or the 16-bit checksum
2211 s32 ixgbe_calc_eeprom_checksum_generic(struct ixgbe_hw *hw)
2220 DEBUGFUNC("ixgbe_calc_eeprom_checksum_generic");
2222 /* Include 0x0-0x3F in the checksum */
2223 for (i = 0; i < IXGBE_EEPROM_CHECKSUM; i++) {
2224 if (hw->eeprom.ops.read(hw, i, &word)) {
2225 DEBUGOUT("EEPROM read failed\n");
2226 return IXGBE_ERR_EEPROM;
2231 /* Include all data from pointers except for the fw pointer */
2232 for (i = IXGBE_PCIE_ANALOG_PTR; i < IXGBE_FW_PTR; i++) {
2233 if (hw->eeprom.ops.read(hw, i, &pointer)) {
2234 DEBUGOUT("EEPROM read failed\n");
2235 return IXGBE_ERR_EEPROM;
2238 /* If the pointer seems invalid */
2239 if (pointer == 0xFFFF || pointer == 0)
2242 if (hw->eeprom.ops.read(hw, pointer, &length)) {
2243 DEBUGOUT("EEPROM read failed\n");
2244 return IXGBE_ERR_EEPROM;
2247 if (length == 0xFFFF || length == 0)
2250 for (j = pointer + 1; j <= pointer + length; j++) {
2251 if (hw->eeprom.ops.read(hw, j, &word)) {
2252 DEBUGOUT("EEPROM read failed\n");
2253 return IXGBE_ERR_EEPROM;
2259 checksum = (u16)IXGBE_EEPROM_SUM - checksum;
2261 return (s32)checksum;
2265 * ixgbe_validate_eeprom_checksum_generic - Validate EEPROM checksum
2266 * @hw: pointer to hardware structure
2267 * @checksum_val: calculated checksum
2269 * Performs checksum calculation and validates the EEPROM checksum. If the
2270 * caller does not need checksum_val, the value can be NULL.
2272 s32 ixgbe_validate_eeprom_checksum_generic(struct ixgbe_hw *hw,
2277 u16 read_checksum = 0;
2279 DEBUGFUNC("ixgbe_validate_eeprom_checksum_generic");
2281 /* Read the first word from the EEPROM. If this times out or fails, do
2282 * not continue or we could be in for a very long wait while every
2285 status = hw->eeprom.ops.read(hw, 0, &checksum);
2287 DEBUGOUT("EEPROM read failed\n");
2291 status = hw->eeprom.ops.calc_checksum(hw);
2295 checksum = (u16)(status & 0xffff);
2297 status = hw->eeprom.ops.read(hw, IXGBE_EEPROM_CHECKSUM, &read_checksum);
2299 DEBUGOUT("EEPROM read failed\n");
2303 /* Verify read checksum from EEPROM is the same as
2304 * calculated checksum
2306 if (read_checksum != checksum)
2307 status = IXGBE_ERR_EEPROM_CHECKSUM;
2309 /* If the user cares, return the calculated checksum */
2311 *checksum_val = checksum;
2317 * ixgbe_update_eeprom_checksum_generic - Updates the EEPROM checksum
2318 * @hw: pointer to hardware structure
2320 s32 ixgbe_update_eeprom_checksum_generic(struct ixgbe_hw *hw)
2325 DEBUGFUNC("ixgbe_update_eeprom_checksum_generic");
2327 /* Read the first word from the EEPROM. If this times out or fails, do
2328 * not continue or we could be in for a very long wait while every
2331 status = hw->eeprom.ops.read(hw, 0, &checksum);
2333 DEBUGOUT("EEPROM read failed\n");
2337 status = hw->eeprom.ops.calc_checksum(hw);
2341 checksum = (u16)(status & 0xffff);
2343 status = hw->eeprom.ops.write(hw, IXGBE_EEPROM_CHECKSUM, checksum);
2349 * ixgbe_validate_mac_addr - Validate MAC address
2350 * @mac_addr: pointer to MAC address.
2352 * Tests a MAC address to ensure it is a valid Individual Address.
2354 s32 ixgbe_validate_mac_addr(u8 *mac_addr)
2356 s32 status = IXGBE_SUCCESS;
2358 DEBUGFUNC("ixgbe_validate_mac_addr");
2360 /* Make sure it is not a multicast address */
2361 if (IXGBE_IS_MULTICAST(mac_addr)) {
2362 status = IXGBE_ERR_INVALID_MAC_ADDR;
2363 /* Not a broadcast address */
2364 } else if (IXGBE_IS_BROADCAST(mac_addr)) {
2365 status = IXGBE_ERR_INVALID_MAC_ADDR;
2366 /* Reject the zero address */
2367 } else if (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 &&
2368 mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0) {
2369 status = IXGBE_ERR_INVALID_MAC_ADDR;
2375 * ixgbe_set_rar_generic - Set Rx address register
2376 * @hw: pointer to hardware structure
2377 * @index: Receive address register to write
2378 * @addr: Address to put into receive address register
2379 * @vmdq: VMDq "set" or "pool" index
2380 * @enable_addr: set flag that address is active
2382 * Puts an ethernet address into a receive address register.
2384 s32 ixgbe_set_rar_generic(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq,
2387 u32 rar_low, rar_high;
2388 u32 rar_entries = hw->mac.num_rar_entries;
2390 DEBUGFUNC("ixgbe_set_rar_generic");
2392 /* Make sure we are using a valid rar index range */
2393 if (index >= rar_entries) {
2394 ERROR_REPORT2(IXGBE_ERROR_ARGUMENT,
2395 "RAR index %d is out of range.\n", index);
2396 return IXGBE_ERR_INVALID_ARGUMENT;
2399 /* setup VMDq pool selection before this RAR gets enabled */
2400 hw->mac.ops.set_vmdq(hw, index, vmdq);
2403 * HW expects these in little endian so we reverse the byte
2404 * order from network order (big endian) to little endian
2406 rar_low = ((u32)addr[0] |
2407 ((u32)addr[1] << 8) |
2408 ((u32)addr[2] << 16) |
2409 ((u32)addr[3] << 24));
2411 * Some parts put the VMDq setting in the extra RAH bits,
2412 * so save everything except the lower 16 bits that hold part
2413 * of the address and the address valid bit.
2415 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index));
2416 rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV);
2417 rar_high |= ((u32)addr[4] | ((u32)addr[5] << 8));
2419 if (enable_addr != 0)
2420 rar_high |= IXGBE_RAH_AV;
2422 IXGBE_WRITE_REG(hw, IXGBE_RAL(index), rar_low);
2423 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high);
2425 return IXGBE_SUCCESS;
2429 * ixgbe_clear_rar_generic - Remove Rx address register
2430 * @hw: pointer to hardware structure
2431 * @index: Receive address register to write
2433 * Clears an ethernet address from a receive address register.
2435 s32 ixgbe_clear_rar_generic(struct ixgbe_hw *hw, u32 index)
2438 u32 rar_entries = hw->mac.num_rar_entries;
2440 DEBUGFUNC("ixgbe_clear_rar_generic");
2442 /* Make sure we are using a valid rar index range */
2443 if (index >= rar_entries) {
2444 ERROR_REPORT2(IXGBE_ERROR_ARGUMENT,
2445 "RAR index %d is out of range.\n", index);
2446 return IXGBE_ERR_INVALID_ARGUMENT;
2450 * Some parts put the VMDq setting in the extra RAH bits,
2451 * so save everything except the lower 16 bits that hold part
2452 * of the address and the address valid bit.
2454 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index));
2455 rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV);
2457 IXGBE_WRITE_REG(hw, IXGBE_RAL(index), 0);
2458 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high);
2460 /* clear VMDq pool/queue selection for this RAR */
2461 hw->mac.ops.clear_vmdq(hw, index, IXGBE_CLEAR_VMDQ_ALL);
2463 return IXGBE_SUCCESS;
2467 * ixgbe_init_rx_addrs_generic - Initializes receive address filters.
2468 * @hw: pointer to hardware structure
2470 * Places the MAC address in receive address register 0 and clears the rest
2471 * of the receive address registers. Clears the multicast table. Assumes
2472 * the receiver is in reset when the routine is called.
2474 s32 ixgbe_init_rx_addrs_generic(struct ixgbe_hw *hw)
2477 u32 rar_entries = hw->mac.num_rar_entries;
2479 DEBUGFUNC("ixgbe_init_rx_addrs_generic");
2482 * If the current mac address is valid, assume it is a software override
2483 * to the permanent address.
2484 * Otherwise, use the permanent address from the eeprom.
2486 if (ixgbe_validate_mac_addr(hw->mac.addr) ==
2487 IXGBE_ERR_INVALID_MAC_ADDR) {
2488 /* Get the MAC address from the RAR0 for later reference */
2489 hw->mac.ops.get_mac_addr(hw, hw->mac.addr);
2491 DEBUGOUT3(" Keeping Current RAR0 Addr =%.2X %.2X %.2X ",
2492 hw->mac.addr[0], hw->mac.addr[1],
2494 DEBUGOUT3("%.2X %.2X %.2X\n", hw->mac.addr[3],
2495 hw->mac.addr[4], hw->mac.addr[5]);
2497 /* Setup the receive address. */
2498 DEBUGOUT("Overriding MAC Address in RAR[0]\n");
2499 DEBUGOUT3(" New MAC Addr =%.2X %.2X %.2X ",
2500 hw->mac.addr[0], hw->mac.addr[1],
2502 DEBUGOUT3("%.2X %.2X %.2X\n", hw->mac.addr[3],
2503 hw->mac.addr[4], hw->mac.addr[5]);
2505 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2508 /* clear VMDq pool/queue selection for RAR 0 */
2509 hw->mac.ops.clear_vmdq(hw, 0, IXGBE_CLEAR_VMDQ_ALL);
2511 hw->addr_ctrl.overflow_promisc = 0;
2513 hw->addr_ctrl.rar_used_count = 1;
2515 /* Zero out the other receive addresses. */
2516 DEBUGOUT1("Clearing RAR[1-%d]\n", rar_entries - 1);
2517 for (i = 1; i < rar_entries; i++) {
2518 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
2519 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
2523 hw->addr_ctrl.mta_in_use = 0;
2524 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
2526 DEBUGOUT(" Clearing MTA\n");
2527 for (i = 0; i < hw->mac.mcft_size; i++)
2528 IXGBE_WRITE_REG(hw, IXGBE_MTA(i), 0);
2530 ixgbe_init_uta_tables(hw);
2532 return IXGBE_SUCCESS;
2536 * ixgbe_add_uc_addr - Adds a secondary unicast address.
2537 * @hw: pointer to hardware structure
2538 * @addr: new address
2539 * @vmdq: VMDq "set" or "pool" index
2541 * Adds it to unused receive address register or goes into promiscuous mode.
2543 void ixgbe_add_uc_addr(struct ixgbe_hw *hw, u8 *addr, u32 vmdq)
2545 u32 rar_entries = hw->mac.num_rar_entries;
2548 DEBUGFUNC("ixgbe_add_uc_addr");
2550 DEBUGOUT6(" UC Addr = %.2X %.2X %.2X %.2X %.2X %.2X\n",
2551 addr[0], addr[1], addr[2], addr[3], addr[4], addr[5]);
2554 * Place this address in the RAR if there is room,
2555 * else put the controller into promiscuous mode
2557 if (hw->addr_ctrl.rar_used_count < rar_entries) {
2558 rar = hw->addr_ctrl.rar_used_count;
2559 hw->mac.ops.set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV);
2560 DEBUGOUT1("Added a secondary address to RAR[%d]\n", rar);
2561 hw->addr_ctrl.rar_used_count++;
2563 hw->addr_ctrl.overflow_promisc++;
2566 DEBUGOUT("ixgbe_add_uc_addr Complete\n");
2570 * ixgbe_update_uc_addr_list_generic - Updates MAC list of secondary addresses
2571 * @hw: pointer to hardware structure
2572 * @addr_list: the list of new addresses
2573 * @addr_count: number of addresses
2574 * @next: iterator function to walk the address list
2576 * The given list replaces any existing list. Clears the secondary addrs from
2577 * receive address registers. Uses unused receive address registers for the
2578 * first secondary addresses, and falls back to promiscuous mode as needed.
2580 * Drivers using secondary unicast addresses must set user_set_promisc when
2581 * manually putting the device into promiscuous mode.
2583 s32 ixgbe_update_uc_addr_list_generic(struct ixgbe_hw *hw, u8 *addr_list,
2584 u32 addr_count, ixgbe_mc_addr_itr next)
2588 u32 old_promisc_setting = hw->addr_ctrl.overflow_promisc;
2593 DEBUGFUNC("ixgbe_update_uc_addr_list_generic");
2596 * Clear accounting of old secondary address list,
2597 * don't count RAR[0]
2599 uc_addr_in_use = hw->addr_ctrl.rar_used_count - 1;
2600 hw->addr_ctrl.rar_used_count -= uc_addr_in_use;
2601 hw->addr_ctrl.overflow_promisc = 0;
2603 /* Zero out the other receive addresses */
2604 DEBUGOUT1("Clearing RAR[1-%d]\n", uc_addr_in_use+1);
2605 for (i = 0; i < uc_addr_in_use; i++) {
2606 IXGBE_WRITE_REG(hw, IXGBE_RAL(1+i), 0);
2607 IXGBE_WRITE_REG(hw, IXGBE_RAH(1+i), 0);
2610 /* Add the new addresses */
2611 for (i = 0; i < addr_count; i++) {
2612 DEBUGOUT(" Adding the secondary addresses:\n");
2613 addr = next(hw, &addr_list, &vmdq);
2614 ixgbe_add_uc_addr(hw, addr, vmdq);
2617 if (hw->addr_ctrl.overflow_promisc) {
2618 /* enable promisc if not already in overflow or set by user */
2619 if (!old_promisc_setting && !hw->addr_ctrl.user_set_promisc) {
2620 DEBUGOUT(" Entering address overflow promisc mode\n");
2621 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2622 fctrl |= IXGBE_FCTRL_UPE;
2623 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2626 /* only disable if set by overflow, not by user */
2627 if (old_promisc_setting && !hw->addr_ctrl.user_set_promisc) {
2628 DEBUGOUT(" Leaving address overflow promisc mode\n");
2629 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2630 fctrl &= ~IXGBE_FCTRL_UPE;
2631 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2635 DEBUGOUT("ixgbe_update_uc_addr_list_generic Complete\n");
2636 return IXGBE_SUCCESS;
2640 * ixgbe_mta_vector - Determines bit-vector in multicast table to set
2641 * @hw: pointer to hardware structure
2642 * @mc_addr: the multicast address
2644 * Extracts the 12 bits, from a multicast address, to determine which
2645 * bit-vector to set in the multicast table. The hardware uses 12 bits, from
2646 * incoming rx multicast addresses, to determine the bit-vector to check in
2647 * the MTA. Which of the 4 combination, of 12-bits, the hardware uses is set
2648 * by the MO field of the MCSTCTRL. The MO field is set during initialization
2649 * to mc_filter_type.
2651 static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr)
2655 DEBUGFUNC("ixgbe_mta_vector");
2657 switch (hw->mac.mc_filter_type) {
2658 case 0: /* use bits [47:36] of the address */
2659 vector = ((mc_addr[4] >> 4) | (((u16)mc_addr[5]) << 4));
2661 case 1: /* use bits [46:35] of the address */
2662 vector = ((mc_addr[4] >> 3) | (((u16)mc_addr[5]) << 5));
2664 case 2: /* use bits [45:34] of the address */
2665 vector = ((mc_addr[4] >> 2) | (((u16)mc_addr[5]) << 6));
2667 case 3: /* use bits [43:32] of the address */
2668 vector = ((mc_addr[4]) | (((u16)mc_addr[5]) << 8));
2670 default: /* Invalid mc_filter_type */
2671 DEBUGOUT("MC filter type param set incorrectly\n");
2676 /* vector can only be 12-bits or boundary will be exceeded */
2682 * ixgbe_set_mta - Set bit-vector in multicast table
2683 * @hw: pointer to hardware structure
2684 * @mc_addr: Multicast address
2686 * Sets the bit-vector in the multicast table.
2688 void ixgbe_set_mta(struct ixgbe_hw *hw, u8 *mc_addr)
2694 DEBUGFUNC("ixgbe_set_mta");
2696 hw->addr_ctrl.mta_in_use++;
2698 vector = ixgbe_mta_vector(hw, mc_addr);
2699 DEBUGOUT1(" bit-vector = 0x%03X\n", vector);
2702 * The MTA is a register array of 128 32-bit registers. It is treated
2703 * like an array of 4096 bits. We want to set bit
2704 * BitArray[vector_value]. So we figure out what register the bit is
2705 * in, read it, OR in the new bit, then write back the new value. The
2706 * register is determined by the upper 7 bits of the vector value and
2707 * the bit within that register are determined by the lower 5 bits of
2710 vector_reg = (vector >> 5) & 0x7F;
2711 vector_bit = vector & 0x1F;
2712 hw->mac.mta_shadow[vector_reg] |= (1 << vector_bit);
2716 * ixgbe_update_mc_addr_list_generic - Updates MAC list of multicast addresses
2717 * @hw: pointer to hardware structure
2718 * @mc_addr_list: the list of new multicast addresses
2719 * @mc_addr_count: number of addresses
2720 * @next: iterator function to walk the multicast address list
2721 * @clear: flag, when set clears the table beforehand
2723 * When the clear flag is set, the given list replaces any existing list.
2724 * Hashes the given addresses into the multicast table.
2726 s32 ixgbe_update_mc_addr_list_generic(struct ixgbe_hw *hw, u8 *mc_addr_list,
2727 u32 mc_addr_count, ixgbe_mc_addr_itr next,
2733 DEBUGFUNC("ixgbe_update_mc_addr_list_generic");
2736 * Set the new number of MC addresses that we are being requested to
2739 hw->addr_ctrl.num_mc_addrs = mc_addr_count;
2740 hw->addr_ctrl.mta_in_use = 0;
2742 /* Clear mta_shadow */
2744 DEBUGOUT(" Clearing MTA\n");
2745 memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow));
2748 /* Update mta_shadow */
2749 for (i = 0; i < mc_addr_count; i++) {
2750 DEBUGOUT(" Adding the multicast addresses:\n");
2751 ixgbe_set_mta(hw, next(hw, &mc_addr_list, &vmdq));
2755 for (i = 0; i < hw->mac.mcft_size; i++)
2756 IXGBE_WRITE_REG_ARRAY(hw, IXGBE_MTA(0), i,
2757 hw->mac.mta_shadow[i]);
2759 if (hw->addr_ctrl.mta_in_use > 0)
2760 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
2761 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
2763 DEBUGOUT("ixgbe_update_mc_addr_list_generic Complete\n");
2764 return IXGBE_SUCCESS;
2768 * ixgbe_enable_mc_generic - Enable multicast address in RAR
2769 * @hw: pointer to hardware structure
2771 * Enables multicast address in RAR and the use of the multicast hash table.
2773 s32 ixgbe_enable_mc_generic(struct ixgbe_hw *hw)
2775 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl;
2777 DEBUGFUNC("ixgbe_enable_mc_generic");
2779 if (a->mta_in_use > 0)
2780 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, IXGBE_MCSTCTRL_MFE |
2781 hw->mac.mc_filter_type);
2783 return IXGBE_SUCCESS;
2787 * ixgbe_disable_mc_generic - Disable multicast address in RAR
2788 * @hw: pointer to hardware structure
2790 * Disables multicast address in RAR and the use of the multicast hash table.
2792 s32 ixgbe_disable_mc_generic(struct ixgbe_hw *hw)
2794 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl;
2796 DEBUGFUNC("ixgbe_disable_mc_generic");
2798 if (a->mta_in_use > 0)
2799 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
2801 return IXGBE_SUCCESS;
2805 * ixgbe_fc_enable_generic - Enable flow control
2806 * @hw: pointer to hardware structure
2808 * Enable flow control according to the current settings.
2810 s32 ixgbe_fc_enable_generic(struct ixgbe_hw *hw)
2812 s32 ret_val = IXGBE_SUCCESS;
2813 u32 mflcn_reg, fccfg_reg;
2818 DEBUGFUNC("ixgbe_fc_enable_generic");
2820 /* Validate the water mark configuration */
2821 if (!hw->fc.pause_time) {
2822 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2826 /* Low water mark of zero causes XOFF floods */
2827 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
2828 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
2829 hw->fc.high_water[i]) {
2830 if (!hw->fc.low_water[i] ||
2831 hw->fc.low_water[i] >= hw->fc.high_water[i]) {
2832 DEBUGOUT("Invalid water mark configuration\n");
2833 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2839 /* Negotiate the fc mode to use */
2840 hw->mac.ops.fc_autoneg(hw);
2842 /* Disable any previous flow control settings */
2843 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
2844 mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_MASK | IXGBE_MFLCN_RFCE);
2846 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
2847 fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
2850 * The possible values of fc.current_mode are:
2851 * 0: Flow control is completely disabled
2852 * 1: Rx flow control is enabled (we can receive pause frames,
2853 * but not send pause frames).
2854 * 2: Tx flow control is enabled (we can send pause frames but
2855 * we do not support receiving pause frames).
2856 * 3: Both Rx and Tx flow control (symmetric) are enabled.
2859 switch (hw->fc.current_mode) {
2862 * Flow control is disabled by software override or autoneg.
2863 * The code below will actually disable it in the HW.
2866 case ixgbe_fc_rx_pause:
2868 * Rx Flow control is enabled and Tx Flow control is
2869 * disabled by software override. Since there really
2870 * isn't a way to advertise that we are capable of RX
2871 * Pause ONLY, we will advertise that we support both
2872 * symmetric and asymmetric Rx PAUSE. Later, we will
2873 * disable the adapter's ability to send PAUSE frames.
2875 mflcn_reg |= IXGBE_MFLCN_RFCE;
2877 case ixgbe_fc_tx_pause:
2879 * Tx Flow control is enabled, and Rx Flow control is
2880 * disabled by software override.
2882 fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X;
2885 /* Flow control (both Rx and Tx) is enabled by SW override. */
2886 mflcn_reg |= IXGBE_MFLCN_RFCE;
2887 fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X;
2890 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT,
2891 "Flow control param set incorrectly\n");
2892 ret_val = IXGBE_ERR_CONFIG;
2897 /* Set 802.3x based flow control settings. */
2898 mflcn_reg |= IXGBE_MFLCN_DPF;
2899 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
2900 IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
2903 /* Set up and enable Rx high/low water mark thresholds, enable XON. */
2904 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
2905 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
2906 hw->fc.high_water[i]) {
2907 fcrtl = (hw->fc.low_water[i] << 10) | IXGBE_FCRTL_XONE;
2908 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), fcrtl);
2909 fcrth = (hw->fc.high_water[i] << 10) | IXGBE_FCRTH_FCEN;
2911 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), 0);
2913 * In order to prevent Tx hangs when the internal Tx
2914 * switch is enabled we must set the high water mark
2915 * to the Rx packet buffer size - 24KB. This allows
2916 * the Tx switch to function even under heavy Rx
2919 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i)) - 24576;
2922 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(i), fcrth);
2925 /* Configure pause time (2 TCs per register) */
2926 reg = hw->fc.pause_time * 0x00010001;
2927 for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
2928 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
2930 /* Configure flow control refresh threshold value */
2931 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
2938 * ixgbe_negotiate_fc - Negotiate flow control
2939 * @hw: pointer to hardware structure
2940 * @adv_reg: flow control advertised settings
2941 * @lp_reg: link partner's flow control settings
2942 * @adv_sym: symmetric pause bit in advertisement
2943 * @adv_asm: asymmetric pause bit in advertisement
2944 * @lp_sym: symmetric pause bit in link partner advertisement
2945 * @lp_asm: asymmetric pause bit in link partner advertisement
2947 * Find the intersection between advertised settings and link partner's
2948 * advertised settings
2950 s32 ixgbe_negotiate_fc(struct ixgbe_hw *hw, u32 adv_reg, u32 lp_reg,
2951 u32 adv_sym, u32 adv_asm, u32 lp_sym, u32 lp_asm)
2953 if ((!(adv_reg)) || (!(lp_reg))) {
2954 ERROR_REPORT3(IXGBE_ERROR_UNSUPPORTED,
2955 "Local or link partner's advertised flow control "
2956 "settings are NULL. Local: %x, link partner: %x\n",
2958 return IXGBE_ERR_FC_NOT_NEGOTIATED;
2961 if ((adv_reg & adv_sym) && (lp_reg & lp_sym)) {
2963 * Now we need to check if the user selected Rx ONLY
2964 * of pause frames. In this case, we had to advertise
2965 * FULL flow control because we could not advertise RX
2966 * ONLY. Hence, we must now check to see if we need to
2967 * turn OFF the TRANSMISSION of PAUSE frames.
2969 if (hw->fc.requested_mode == ixgbe_fc_full) {
2970 hw->fc.current_mode = ixgbe_fc_full;
2971 DEBUGOUT("Flow Control = FULL.\n");
2973 hw->fc.current_mode = ixgbe_fc_rx_pause;
2974 DEBUGOUT("Flow Control=RX PAUSE frames only\n");
2976 } else if (!(adv_reg & adv_sym) && (adv_reg & adv_asm) &&
2977 (lp_reg & lp_sym) && (lp_reg & lp_asm)) {
2978 hw->fc.current_mode = ixgbe_fc_tx_pause;
2979 DEBUGOUT("Flow Control = TX PAUSE frames only.\n");
2980 } else if ((adv_reg & adv_sym) && (adv_reg & adv_asm) &&
2981 !(lp_reg & lp_sym) && (lp_reg & lp_asm)) {
2982 hw->fc.current_mode = ixgbe_fc_rx_pause;
2983 DEBUGOUT("Flow Control = RX PAUSE frames only.\n");
2985 hw->fc.current_mode = ixgbe_fc_none;
2986 DEBUGOUT("Flow Control = NONE.\n");
2988 return IXGBE_SUCCESS;
2992 * ixgbe_fc_autoneg_fiber - Enable flow control on 1 gig fiber
2993 * @hw: pointer to hardware structure
2995 * Enable flow control according on 1 gig fiber.
2997 static s32 ixgbe_fc_autoneg_fiber(struct ixgbe_hw *hw)
2999 u32 pcs_anadv_reg, pcs_lpab_reg, linkstat;
3000 s32 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED;
3003 * On multispeed fiber at 1g, bail out if
3004 * - link is up but AN did not complete, or if
3005 * - link is up and AN completed but timed out
3008 linkstat = IXGBE_READ_REG(hw, IXGBE_PCS1GLSTA);
3009 if ((!!(linkstat & IXGBE_PCS1GLSTA_AN_COMPLETE) == 0) ||
3010 (!!(linkstat & IXGBE_PCS1GLSTA_AN_TIMED_OUT) == 1)) {
3011 DEBUGOUT("Auto-Negotiation did not complete or timed out\n");
3015 pcs_anadv_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
3016 pcs_lpab_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANLP);
3018 ret_val = ixgbe_negotiate_fc(hw, pcs_anadv_reg,
3019 pcs_lpab_reg, IXGBE_PCS1GANA_SYM_PAUSE,
3020 IXGBE_PCS1GANA_ASM_PAUSE,
3021 IXGBE_PCS1GANA_SYM_PAUSE,
3022 IXGBE_PCS1GANA_ASM_PAUSE);
3029 * ixgbe_fc_autoneg_backplane - Enable flow control IEEE clause 37
3030 * @hw: pointer to hardware structure
3032 * Enable flow control according to IEEE clause 37.
3034 static s32 ixgbe_fc_autoneg_backplane(struct ixgbe_hw *hw)
3036 u32 links2, anlp1_reg, autoc_reg, links;
3037 s32 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED;
3040 * On backplane, bail out if
3041 * - backplane autoneg was not completed, or if
3042 * - we are 82599 and link partner is not AN enabled
3044 links = IXGBE_READ_REG(hw, IXGBE_LINKS);
3045 if ((links & IXGBE_LINKS_KX_AN_COMP) == 0) {
3046 DEBUGOUT("Auto-Negotiation did not complete\n");
3050 if (hw->mac.type == ixgbe_mac_82599EB) {
3051 links2 = IXGBE_READ_REG(hw, IXGBE_LINKS2);
3052 if ((links2 & IXGBE_LINKS2_AN_SUPPORTED) == 0) {
3053 DEBUGOUT("Link partner is not AN enabled\n");
3058 * Read the 10g AN autoc and LP ability registers and resolve
3059 * local flow control settings accordingly
3061 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
3062 anlp1_reg = IXGBE_READ_REG(hw, IXGBE_ANLP1);
3064 ret_val = ixgbe_negotiate_fc(hw, autoc_reg,
3065 anlp1_reg, IXGBE_AUTOC_SYM_PAUSE, IXGBE_AUTOC_ASM_PAUSE,
3066 IXGBE_ANLP1_SYM_PAUSE, IXGBE_ANLP1_ASM_PAUSE);
3073 * ixgbe_fc_autoneg_copper - Enable flow control IEEE clause 37
3074 * @hw: pointer to hardware structure
3076 * Enable flow control according to IEEE clause 37.
3078 static s32 ixgbe_fc_autoneg_copper(struct ixgbe_hw *hw)
3080 u16 technology_ability_reg = 0;
3081 u16 lp_technology_ability_reg = 0;
3083 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_ADVT,
3084 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3085 &technology_ability_reg);
3086 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_LP,
3087 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
3088 &lp_technology_ability_reg);
3090 return ixgbe_negotiate_fc(hw, (u32)technology_ability_reg,
3091 (u32)lp_technology_ability_reg,
3092 IXGBE_TAF_SYM_PAUSE, IXGBE_TAF_ASM_PAUSE,
3093 IXGBE_TAF_SYM_PAUSE, IXGBE_TAF_ASM_PAUSE);
3097 * ixgbe_fc_autoneg - Configure flow control
3098 * @hw: pointer to hardware structure
3100 * Compares our advertised flow control capabilities to those advertised by
3101 * our link partner, and determines the proper flow control mode to use.
3103 void ixgbe_fc_autoneg(struct ixgbe_hw *hw)
3105 s32 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED;
3106 ixgbe_link_speed speed;
3109 DEBUGFUNC("ixgbe_fc_autoneg");
3112 * AN should have completed when the cable was plugged in.
3113 * Look for reasons to bail out. Bail out if:
3114 * - FC autoneg is disabled, or if
3117 if (hw->fc.disable_fc_autoneg) {
3118 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
3119 "Flow control autoneg is disabled");
3123 hw->mac.ops.check_link(hw, &speed, &link_up, FALSE);
3125 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE, "The link is down");
3129 switch (hw->phy.media_type) {
3130 /* Autoneg flow control on fiber adapters */
3131 case ixgbe_media_type_fiber_fixed:
3132 case ixgbe_media_type_fiber_qsfp:
3133 case ixgbe_media_type_fiber:
3134 if (speed == IXGBE_LINK_SPEED_1GB_FULL)
3135 ret_val = ixgbe_fc_autoneg_fiber(hw);
3138 /* Autoneg flow control on backplane adapters */
3139 case ixgbe_media_type_backplane:
3140 ret_val = ixgbe_fc_autoneg_backplane(hw);
3143 /* Autoneg flow control on copper adapters */
3144 case ixgbe_media_type_copper:
3145 if (ixgbe_device_supports_autoneg_fc(hw))
3146 ret_val = ixgbe_fc_autoneg_copper(hw);
3154 if (ret_val == IXGBE_SUCCESS) {
3155 hw->fc.fc_was_autonegged = TRUE;
3157 hw->fc.fc_was_autonegged = FALSE;
3158 hw->fc.current_mode = hw->fc.requested_mode;
3163 * ixgbe_pcie_timeout_poll - Return number of times to poll for completion
3164 * @hw: pointer to hardware structure
3166 * System-wide timeout range is encoded in PCIe Device Control2 register.
3168 * Add 10% to specified maximum and return the number of times to poll for
3169 * completion timeout, in units of 100 microsec. Never return less than
3170 * 800 = 80 millisec.
3172 static u32 ixgbe_pcie_timeout_poll(struct ixgbe_hw *hw)
3177 devctl2 = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_DEVICE_CONTROL2);
3178 devctl2 &= IXGBE_PCIDEVCTRL2_TIMEO_MASK;
3181 case IXGBE_PCIDEVCTRL2_65_130ms:
3182 pollcnt = 1300; /* 130 millisec */
3184 case IXGBE_PCIDEVCTRL2_260_520ms:
3185 pollcnt = 5200; /* 520 millisec */
3187 case IXGBE_PCIDEVCTRL2_1_2s:
3188 pollcnt = 20000; /* 2 sec */
3190 case IXGBE_PCIDEVCTRL2_4_8s:
3191 pollcnt = 80000; /* 8 sec */
3193 case IXGBE_PCIDEVCTRL2_17_34s:
3194 pollcnt = 34000; /* 34 sec */
3196 case IXGBE_PCIDEVCTRL2_50_100us: /* 100 microsecs */
3197 case IXGBE_PCIDEVCTRL2_1_2ms: /* 2 millisecs */
3198 case IXGBE_PCIDEVCTRL2_16_32ms: /* 32 millisec */
3199 case IXGBE_PCIDEVCTRL2_16_32ms_def: /* 32 millisec default */
3201 pollcnt = 800; /* 80 millisec minimum */
3205 /* add 10% to spec maximum */
3206 return (pollcnt * 11) / 10;
3210 * ixgbe_disable_pcie_master - Disable PCI-express master access
3211 * @hw: pointer to hardware structure
3213 * Disables PCI-Express master access and verifies there are no pending
3214 * requests. IXGBE_ERR_MASTER_REQUESTS_PENDING is returned if master disable
3215 * bit hasn't caused the master requests to be disabled, else IXGBE_SUCCESS
3216 * is returned signifying master requests disabled.
3218 s32 ixgbe_disable_pcie_master(struct ixgbe_hw *hw)
3220 s32 status = IXGBE_SUCCESS;
3224 DEBUGFUNC("ixgbe_disable_pcie_master");
3226 /* Always set this bit to ensure any future transactions are blocked */
3227 IXGBE_WRITE_REG(hw, IXGBE_CTRL, IXGBE_CTRL_GIO_DIS);
3229 /* Exit if master requests are blocked */
3230 if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO) ||
3231 IXGBE_REMOVED(hw->hw_addr))
3234 /* Poll for master request bit to clear */
3235 for (i = 0; i < IXGBE_PCI_MASTER_DISABLE_TIMEOUT; i++) {
3237 if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO))
3242 * Two consecutive resets are required via CTRL.RST per datasheet
3243 * 5.2.5.3.2 Master Disable. We set a flag to inform the reset routine
3244 * of this need. The first reset prevents new master requests from
3245 * being issued by our device. We then must wait 1usec or more for any
3246 * remaining completions from the PCIe bus to trickle in, and then reset
3247 * again to clear out any effects they may have had on our device.
3249 DEBUGOUT("GIO Master Disable bit didn't clear - requesting resets\n");
3250 hw->mac.flags |= IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
3252 if (hw->mac.type >= ixgbe_mac_X550)
3256 * Before proceeding, make sure that the PCIe block does not have
3257 * transactions pending.
3259 poll = ixgbe_pcie_timeout_poll(hw);
3260 for (i = 0; i < poll; i++) {
3262 value = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_DEVICE_STATUS);
3263 if (IXGBE_REMOVED(hw->hw_addr))
3265 if (!(value & IXGBE_PCI_DEVICE_STATUS_TRANSACTION_PENDING))
3269 ERROR_REPORT1(IXGBE_ERROR_POLLING,
3270 "PCIe transaction pending bit also did not clear.\n");
3271 status = IXGBE_ERR_MASTER_REQUESTS_PENDING;
3278 * ixgbe_acquire_swfw_sync - Acquire SWFW semaphore
3279 * @hw: pointer to hardware structure
3280 * @mask: Mask to specify which semaphore to acquire
3282 * Acquires the SWFW semaphore through the GSSR register for the specified
3283 * function (CSR, PHY0, PHY1, EEPROM, Flash)
3285 s32 ixgbe_acquire_swfw_sync(struct ixgbe_hw *hw, u32 mask)
3289 u32 fwmask = mask << 5;
3293 DEBUGFUNC("ixgbe_acquire_swfw_sync");
3295 for (i = 0; i < timeout; i++) {
3297 * SW NVM semaphore bit is used for access to all
3298 * SW_FW_SYNC bits (not just NVM)
3300 if (ixgbe_get_eeprom_semaphore(hw))
3301 return IXGBE_ERR_SWFW_SYNC;
3303 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR);
3304 if (!(gssr & (fwmask | swmask))) {
3306 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr);
3307 ixgbe_release_eeprom_semaphore(hw);
3308 return IXGBE_SUCCESS;
3310 /* Resource is currently in use by FW or SW */
3311 ixgbe_release_eeprom_semaphore(hw);
3316 /* If time expired clear the bits holding the lock and retry */
3317 if (gssr & (fwmask | swmask))
3318 ixgbe_release_swfw_sync(hw, gssr & (fwmask | swmask));
3321 return IXGBE_ERR_SWFW_SYNC;
3325 * ixgbe_release_swfw_sync - Release SWFW semaphore
3326 * @hw: pointer to hardware structure
3327 * @mask: Mask to specify which semaphore to release
3329 * Releases the SWFW semaphore through the GSSR register for the specified
3330 * function (CSR, PHY0, PHY1, EEPROM, Flash)
3332 void ixgbe_release_swfw_sync(struct ixgbe_hw *hw, u32 mask)
3337 DEBUGFUNC("ixgbe_release_swfw_sync");
3339 ixgbe_get_eeprom_semaphore(hw);
3341 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR);
3343 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr);
3345 ixgbe_release_eeprom_semaphore(hw);
3349 * ixgbe_disable_sec_rx_path_generic - Stops the receive data path
3350 * @hw: pointer to hardware structure
3352 * Stops the receive data path and waits for the HW to internally empty
3353 * the Rx security block
3355 s32 ixgbe_disable_sec_rx_path_generic(struct ixgbe_hw *hw)
3357 #define IXGBE_MAX_SECRX_POLL 4000
3362 DEBUGFUNC("ixgbe_disable_sec_rx_path_generic");
3365 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
3366 secrxreg |= IXGBE_SECRXCTRL_RX_DIS;
3367 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg);
3368 for (i = 0; i < IXGBE_MAX_SECRX_POLL; i++) {
3369 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXSTAT);
3370 if (secrxreg & IXGBE_SECRXSTAT_SECRX_RDY)
3373 /* Use interrupt-safe sleep just in case */
3377 /* For informational purposes only */
3378 if (i >= IXGBE_MAX_SECRX_POLL)
3379 DEBUGOUT("Rx unit being enabled before security "
3380 "path fully disabled. Continuing with init.\n");
3382 return IXGBE_SUCCESS;
3386 * prot_autoc_read_generic - Hides MAC differences needed for AUTOC read
3387 * @hw: pointer to hardware structure
3388 * @locked: bool to indicate whether the SW/FW lock was taken
3389 * @reg_val: Value we read from AUTOC
3391 * The default case requires no protection so just to the register read.
3393 s32 prot_autoc_read_generic(struct ixgbe_hw *hw, bool *locked, u32 *reg_val)
3396 *reg_val = IXGBE_READ_REG(hw, IXGBE_AUTOC);
3397 return IXGBE_SUCCESS;
3401 * prot_autoc_write_generic - Hides MAC differences needed for AUTOC write
3402 * @hw: pointer to hardware structure
3403 * @reg_val: value to write to AUTOC
3404 * @locked: bool to indicate whether the SW/FW lock was already taken by
3407 * The default case requires no protection so just to the register write.
3409 s32 prot_autoc_write_generic(struct ixgbe_hw *hw, u32 reg_val, bool locked)
3411 UNREFERENCED_1PARAMETER(locked);
3413 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, reg_val);
3414 return IXGBE_SUCCESS;
3418 * ixgbe_enable_sec_rx_path_generic - Enables the receive data path
3419 * @hw: pointer to hardware structure
3421 * Enables the receive data path.
3423 s32 ixgbe_enable_sec_rx_path_generic(struct ixgbe_hw *hw)
3427 DEBUGFUNC("ixgbe_enable_sec_rx_path_generic");
3429 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
3430 secrxreg &= ~IXGBE_SECRXCTRL_RX_DIS;
3431 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg);
3432 IXGBE_WRITE_FLUSH(hw);
3434 return IXGBE_SUCCESS;
3438 * ixgbe_enable_rx_dma_generic - Enable the Rx DMA unit
3439 * @hw: pointer to hardware structure
3440 * @regval: register value to write to RXCTRL
3442 * Enables the Rx DMA unit
3444 s32 ixgbe_enable_rx_dma_generic(struct ixgbe_hw *hw, u32 regval)
3446 DEBUGFUNC("ixgbe_enable_rx_dma_generic");
3448 if (regval & IXGBE_RXCTRL_RXEN)
3449 ixgbe_enable_rx(hw);
3451 ixgbe_disable_rx(hw);
3453 return IXGBE_SUCCESS;
3457 * ixgbe_blink_led_start_generic - Blink LED based on index.
3458 * @hw: pointer to hardware structure
3459 * @index: led number to blink
3461 s32 ixgbe_blink_led_start_generic(struct ixgbe_hw *hw, u32 index)
3463 ixgbe_link_speed speed = 0;
3466 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
3467 s32 ret_val = IXGBE_SUCCESS;
3468 bool locked = FALSE;
3470 DEBUGFUNC("ixgbe_blink_led_start_generic");
3473 return IXGBE_ERR_PARAM;
3476 * Link must be up to auto-blink the LEDs;
3477 * Force it if link is down.
3479 hw->mac.ops.check_link(hw, &speed, &link_up, FALSE);
3482 ret_val = hw->mac.ops.prot_autoc_read(hw, &locked, &autoc_reg);
3483 if (ret_val != IXGBE_SUCCESS)
3486 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
3487 autoc_reg |= IXGBE_AUTOC_FLU;
3489 ret_val = hw->mac.ops.prot_autoc_write(hw, autoc_reg, locked);
3490 if (ret_val != IXGBE_SUCCESS)
3493 IXGBE_WRITE_FLUSH(hw);
3497 led_reg &= ~IXGBE_LED_MODE_MASK(index);
3498 led_reg |= IXGBE_LED_BLINK(index);
3499 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
3500 IXGBE_WRITE_FLUSH(hw);
3507 * ixgbe_blink_led_stop_generic - Stop blinking LED based on index.
3508 * @hw: pointer to hardware structure
3509 * @index: led number to stop blinking
3511 s32 ixgbe_blink_led_stop_generic(struct ixgbe_hw *hw, u32 index)
3514 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
3515 s32 ret_val = IXGBE_SUCCESS;
3516 bool locked = FALSE;
3518 DEBUGFUNC("ixgbe_blink_led_stop_generic");
3521 return IXGBE_ERR_PARAM;
3524 ret_val = hw->mac.ops.prot_autoc_read(hw, &locked, &autoc_reg);
3525 if (ret_val != IXGBE_SUCCESS)
3528 autoc_reg &= ~IXGBE_AUTOC_FLU;
3529 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
3531 ret_val = hw->mac.ops.prot_autoc_write(hw, autoc_reg, locked);
3532 if (ret_val != IXGBE_SUCCESS)
3535 led_reg &= ~IXGBE_LED_MODE_MASK(index);
3536 led_reg &= ~IXGBE_LED_BLINK(index);
3537 led_reg |= IXGBE_LED_LINK_ACTIVE << IXGBE_LED_MODE_SHIFT(index);
3538 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
3539 IXGBE_WRITE_FLUSH(hw);
3546 * ixgbe_get_san_mac_addr_offset - Get SAN MAC address offset from the EEPROM
3547 * @hw: pointer to hardware structure
3548 * @san_mac_offset: SAN MAC address offset
3550 * This function will read the EEPROM location for the SAN MAC address
3551 * pointer, and returns the value at that location. This is used in both
3552 * get and set mac_addr routines.
3554 static s32 ixgbe_get_san_mac_addr_offset(struct ixgbe_hw *hw,
3555 u16 *san_mac_offset)
3559 DEBUGFUNC("ixgbe_get_san_mac_addr_offset");
3562 * First read the EEPROM pointer to see if the MAC addresses are
3565 ret_val = hw->eeprom.ops.read(hw, IXGBE_SAN_MAC_ADDR_PTR,
3568 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
3569 "eeprom at offset %d failed",
3570 IXGBE_SAN_MAC_ADDR_PTR);
3577 * ixgbe_get_san_mac_addr_generic - SAN MAC address retrieval from the EEPROM
3578 * @hw: pointer to hardware structure
3579 * @san_mac_addr: SAN MAC address
3581 * Reads the SAN MAC address from the EEPROM, if it's available. This is
3582 * per-port, so set_lan_id() must be called before reading the addresses.
3583 * set_lan_id() is called by identify_sfp(), but this cannot be relied
3584 * upon for non-SFP connections, so we must call it here.
3586 s32 ixgbe_get_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr)
3588 u16 san_mac_data, san_mac_offset;
3592 DEBUGFUNC("ixgbe_get_san_mac_addr_generic");
3595 * First read the EEPROM pointer to see if the MAC addresses are
3596 * available. If they're not, no point in calling set_lan_id() here.
3598 ret_val = ixgbe_get_san_mac_addr_offset(hw, &san_mac_offset);
3599 if (ret_val || san_mac_offset == 0 || san_mac_offset == 0xFFFF)
3600 goto san_mac_addr_out;
3602 /* make sure we know which port we need to program */
3603 hw->mac.ops.set_lan_id(hw);
3604 /* apply the port offset to the address offset */
3605 (hw->bus.func) ? (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT1_OFFSET) :
3606 (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT0_OFFSET);
3607 for (i = 0; i < 3; i++) {
3608 ret_val = hw->eeprom.ops.read(hw, san_mac_offset,
3611 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
3612 "eeprom read at offset %d failed",
3614 goto san_mac_addr_out;
3616 san_mac_addr[i * 2] = (u8)(san_mac_data);
3617 san_mac_addr[i * 2 + 1] = (u8)(san_mac_data >> 8);
3620 return IXGBE_SUCCESS;
3624 * No addresses available in this EEPROM. It's not an
3625 * error though, so just wipe the local address and return.
3627 for (i = 0; i < 6; i++)
3628 san_mac_addr[i] = 0xFF;
3629 return IXGBE_SUCCESS;
3633 * ixgbe_set_san_mac_addr_generic - Write the SAN MAC address to the EEPROM
3634 * @hw: pointer to hardware structure
3635 * @san_mac_addr: SAN MAC address
3637 * Write a SAN MAC address to the EEPROM.
3639 s32 ixgbe_set_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr)
3642 u16 san_mac_data, san_mac_offset;
3645 DEBUGFUNC("ixgbe_set_san_mac_addr_generic");
3647 /* Look for SAN mac address pointer. If not defined, return */
3648 ret_val = ixgbe_get_san_mac_addr_offset(hw, &san_mac_offset);
3649 if (ret_val || san_mac_offset == 0 || san_mac_offset == 0xFFFF)
3650 return IXGBE_ERR_NO_SAN_ADDR_PTR;
3652 /* Make sure we know which port we need to write */
3653 hw->mac.ops.set_lan_id(hw);
3654 /* Apply the port offset to the address offset */
3655 (hw->bus.func) ? (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT1_OFFSET) :
3656 (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT0_OFFSET);
3658 for (i = 0; i < 3; i++) {
3659 san_mac_data = (u16)((u16)(san_mac_addr[i * 2 + 1]) << 8);
3660 san_mac_data |= (u16)(san_mac_addr[i * 2]);
3661 hw->eeprom.ops.write(hw, san_mac_offset, san_mac_data);
3665 return IXGBE_SUCCESS;
3669 * ixgbe_get_pcie_msix_count_generic - Gets MSI-X vector count
3670 * @hw: pointer to hardware structure
3672 * Read PCIe configuration space, and get the MSI-X vector count from
3673 * the capabilities table.
3675 u16 ixgbe_get_pcie_msix_count_generic(struct ixgbe_hw *hw)
3681 switch (hw->mac.type) {
3682 case ixgbe_mac_82598EB:
3683 pcie_offset = IXGBE_PCIE_MSIX_82598_CAPS;
3684 max_msix_count = IXGBE_MAX_MSIX_VECTORS_82598;
3686 case ixgbe_mac_82599EB:
3687 case ixgbe_mac_X540:
3688 case ixgbe_mac_X550:
3689 case ixgbe_mac_X550EM_x:
3690 case ixgbe_mac_X550EM_a:
3691 pcie_offset = IXGBE_PCIE_MSIX_82599_CAPS;
3692 max_msix_count = IXGBE_MAX_MSIX_VECTORS_82599;
3698 DEBUGFUNC("ixgbe_get_pcie_msix_count_generic");
3699 msix_count = IXGBE_READ_PCIE_WORD(hw, pcie_offset);
3700 if (IXGBE_REMOVED(hw->hw_addr))
3702 msix_count &= IXGBE_PCIE_MSIX_TBL_SZ_MASK;
3704 /* MSI-X count is zero-based in HW */
3707 if (msix_count > max_msix_count)
3708 msix_count = max_msix_count;
3714 * ixgbe_insert_mac_addr_generic - Find a RAR for this mac address
3715 * @hw: pointer to hardware structure
3716 * @addr: Address to put into receive address register
3717 * @vmdq: VMDq pool to assign
3719 * Puts an ethernet address into a receive address register, or
3720 * finds the rar that it is aleady in; adds to the pool list
3722 s32 ixgbe_insert_mac_addr_generic(struct ixgbe_hw *hw, u8 *addr, u32 vmdq)
3724 static const u32 NO_EMPTY_RAR_FOUND = 0xFFFFFFFF;
3725 u32 first_empty_rar = NO_EMPTY_RAR_FOUND;
3727 u32 rar_low, rar_high;
3728 u32 addr_low, addr_high;
3730 DEBUGFUNC("ixgbe_insert_mac_addr_generic");
3732 /* swap bytes for HW little endian */
3733 addr_low = addr[0] | (addr[1] << 8)
3736 addr_high = addr[4] | (addr[5] << 8);
3739 * Either find the mac_id in rar or find the first empty space.
3740 * rar_highwater points to just after the highest currently used
3741 * rar in order to shorten the search. It grows when we add a new
3744 for (rar = 0; rar < hw->mac.rar_highwater; rar++) {
3745 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar));
3747 if (((IXGBE_RAH_AV & rar_high) == 0)
3748 && first_empty_rar == NO_EMPTY_RAR_FOUND) {
3749 first_empty_rar = rar;
3750 } else if ((rar_high & 0xFFFF) == addr_high) {
3751 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(rar));
3752 if (rar_low == addr_low)
3753 break; /* found it already in the rars */
3757 if (rar < hw->mac.rar_highwater) {
3758 /* already there so just add to the pool bits */
3759 ixgbe_set_vmdq(hw, rar, vmdq);
3760 } else if (first_empty_rar != NO_EMPTY_RAR_FOUND) {
3761 /* stick it into first empty RAR slot we found */
3762 rar = first_empty_rar;
3763 ixgbe_set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV);
3764 } else if (rar == hw->mac.rar_highwater) {
3765 /* add it to the top of the list and inc the highwater mark */
3766 ixgbe_set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV);
3767 hw->mac.rar_highwater++;
3768 } else if (rar >= hw->mac.num_rar_entries) {
3769 return IXGBE_ERR_INVALID_MAC_ADDR;
3773 * If we found rar[0], make sure the default pool bit (we use pool 0)
3774 * remains cleared to be sure default pool packets will get delivered
3777 ixgbe_clear_vmdq(hw, rar, 0);
3783 * ixgbe_clear_vmdq_generic - Disassociate a VMDq pool index from a rx address
3784 * @hw: pointer to hardware struct
3785 * @rar: receive address register index to disassociate
3786 * @vmdq: VMDq pool index to remove from the rar
3788 s32 ixgbe_clear_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
3790 u32 mpsar_lo, mpsar_hi;
3791 u32 rar_entries = hw->mac.num_rar_entries;
3793 DEBUGFUNC("ixgbe_clear_vmdq_generic");
3795 /* Make sure we are using a valid rar index range */
3796 if (rar >= rar_entries) {
3797 ERROR_REPORT2(IXGBE_ERROR_ARGUMENT,
3798 "RAR index %d is out of range.\n", rar);
3799 return IXGBE_ERR_INVALID_ARGUMENT;
3802 mpsar_lo = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
3803 mpsar_hi = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
3805 if (IXGBE_REMOVED(hw->hw_addr))
3808 if (!mpsar_lo && !mpsar_hi)
3811 if (vmdq == IXGBE_CLEAR_VMDQ_ALL) {
3813 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0);
3817 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0);
3820 } else if (vmdq < 32) {
3821 mpsar_lo &= ~(1 << vmdq);
3822 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar_lo);
3824 mpsar_hi &= ~(1 << (vmdq - 32));
3825 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar_hi);
3828 /* was that the last pool using this rar? */
3829 if (mpsar_lo == 0 && mpsar_hi == 0 &&
3830 rar != 0 && rar != hw->mac.san_mac_rar_index)
3831 hw->mac.ops.clear_rar(hw, rar);
3833 return IXGBE_SUCCESS;
3837 * ixgbe_set_vmdq_generic - Associate a VMDq pool index with a rx address
3838 * @hw: pointer to hardware struct
3839 * @rar: receive address register index to associate with a VMDq index
3840 * @vmdq: VMDq pool index
3842 s32 ixgbe_set_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
3845 u32 rar_entries = hw->mac.num_rar_entries;
3847 DEBUGFUNC("ixgbe_set_vmdq_generic");
3849 /* Make sure we are using a valid rar index range */
3850 if (rar >= rar_entries) {
3851 ERROR_REPORT2(IXGBE_ERROR_ARGUMENT,
3852 "RAR index %d is out of range.\n", rar);
3853 return IXGBE_ERR_INVALID_ARGUMENT;
3857 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
3859 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar);
3861 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
3862 mpsar |= 1 << (vmdq - 32);
3863 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar);
3865 return IXGBE_SUCCESS;
3869 * This function should only be involved in the IOV mode.
3870 * In IOV mode, Default pool is next pool after the number of
3871 * VFs advertized and not 0.
3872 * MPSAR table needs to be updated for SAN_MAC RAR [hw->mac.san_mac_rar_index]
3874 * ixgbe_set_vmdq_san_mac - Associate default VMDq pool index with a rx address
3875 * @hw: pointer to hardware struct
3876 * @vmdq: VMDq pool index
3878 s32 ixgbe_set_vmdq_san_mac_generic(struct ixgbe_hw *hw, u32 vmdq)
3880 u32 rar = hw->mac.san_mac_rar_index;
3882 DEBUGFUNC("ixgbe_set_vmdq_san_mac");
3885 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 1 << vmdq);
3886 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0);
3888 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0);
3889 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 1 << (vmdq - 32));
3892 return IXGBE_SUCCESS;
3896 * ixgbe_init_uta_tables_generic - Initialize the Unicast Table Array
3897 * @hw: pointer to hardware structure
3899 s32 ixgbe_init_uta_tables_generic(struct ixgbe_hw *hw)
3903 DEBUGFUNC("ixgbe_init_uta_tables_generic");
3904 DEBUGOUT(" Clearing UTA\n");
3906 for (i = 0; i < 128; i++)
3907 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
3909 return IXGBE_SUCCESS;
3913 * ixgbe_find_vlvf_slot - find the vlanid or the first empty slot
3914 * @hw: pointer to hardware structure
3915 * @vlan: VLAN id to write to VLAN filter
3916 * @vlvf_bypass: TRUE to find vlanid only, FALSE returns first empty slot if
3920 * return the VLVF index where this VLAN id should be placed
3923 s32 ixgbe_find_vlvf_slot(struct ixgbe_hw *hw, u32 vlan, bool vlvf_bypass)
3925 s32 regindex, first_empty_slot;
3928 /* short cut the special case */
3932 /* if vlvf_bypass is set we don't want to use an empty slot, we
3933 * will simply bypass the VLVF if there are no entries present in the
3934 * VLVF that contain our VLAN
3936 first_empty_slot = vlvf_bypass ? IXGBE_ERR_NO_SPACE : 0;
3938 /* add VLAN enable bit for comparison */
3939 vlan |= IXGBE_VLVF_VIEN;
3941 /* Search for the vlan id in the VLVF entries. Save off the first empty
3942 * slot found along the way.
3944 * pre-decrement loop covering (IXGBE_VLVF_ENTRIES - 1) .. 1
3946 for (regindex = IXGBE_VLVF_ENTRIES; --regindex;) {
3947 bits = IXGBE_READ_REG(hw, IXGBE_VLVF(regindex));
3950 if (!first_empty_slot && !bits)
3951 first_empty_slot = regindex;
3954 /* If we are here then we didn't find the VLAN. Return first empty
3955 * slot we found during our search, else error.
3957 if (!first_empty_slot)
3958 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE, "No space in VLVF.\n");
3960 return first_empty_slot ? first_empty_slot : IXGBE_ERR_NO_SPACE;
3964 * ixgbe_set_vfta_generic - Set VLAN filter table
3965 * @hw: pointer to hardware structure
3966 * @vlan: VLAN id to write to VLAN filter
3967 * @vind: VMDq output index that maps queue to VLAN id in VLVFB
3968 * @vlan_on: boolean flag to turn on/off VLAN
3969 * @vlvf_bypass: boolean flag indicating updating default pool is okay
3971 * Turn on/off specified VLAN in the VLAN filter table.
3973 s32 ixgbe_set_vfta_generic(struct ixgbe_hw *hw, u32 vlan, u32 vind,
3974 bool vlan_on, bool vlvf_bypass)
3976 u32 regidx, vfta_delta, vfta;
3979 DEBUGFUNC("ixgbe_set_vfta_generic");
3981 if (vlan > 4095 || vind > 63)
3982 return IXGBE_ERR_PARAM;
3985 * this is a 2 part operation - first the VFTA, then the
3986 * VLVF and VLVFB if VT Mode is set
3987 * We don't write the VFTA until we know the VLVF part succeeded.
3991 * The VFTA is a bitstring made up of 128 32-bit registers
3992 * that enable the particular VLAN id, much like the MTA:
3993 * bits[11-5]: which register
3994 * bits[4-0]: which bit in the register
3997 vfta_delta = 1 << (vlan % 32);
3998 vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(regidx));
4001 * vfta_delta represents the difference between the current value
4002 * of vfta and the value we want in the register. Since the diff
4003 * is an XOR mask we can just update the vfta using an XOR
4005 vfta_delta &= vlan_on ? ~vfta : vfta;
4009 * Call ixgbe_set_vlvf_generic to set VLVFB and VLVF
4011 ret_val = ixgbe_set_vlvf_generic(hw, vlan, vind, vlan_on, &vfta_delta,
4013 if (ret_val != IXGBE_SUCCESS) {
4020 /* Update VFTA now that we are ready for traffic */
4022 IXGBE_WRITE_REG(hw, IXGBE_VFTA(regidx), vfta);
4024 return IXGBE_SUCCESS;
4028 * ixgbe_set_vlvf_generic - Set VLAN Pool Filter
4029 * @hw: pointer to hardware structure
4030 * @vlan: VLAN id to write to VLAN filter
4031 * @vind: VMDq output index that maps queue to VLAN id in VLVFB
4032 * @vlan_on: boolean flag to turn on/off VLAN in VLVF
4033 * @vfta_delta: pointer to the difference between the current value of VFTA
4034 * and the desired value
4035 * @vfta: the desired value of the VFTA
4036 * @vlvf_bypass: boolean flag indicating updating default pool is okay
4038 * Turn on/off specified bit in VLVF table.
4040 s32 ixgbe_set_vlvf_generic(struct ixgbe_hw *hw, u32 vlan, u32 vind,
4041 bool vlan_on, u32 *vfta_delta, u32 vfta,
4047 DEBUGFUNC("ixgbe_set_vlvf_generic");
4049 if (vlan > 4095 || vind > 63)
4050 return IXGBE_ERR_PARAM;
4052 /* If VT Mode is set
4054 * make sure the vlan is in VLVF
4055 * set the vind bit in the matching VLVFB
4057 * clear the pool bit and possibly the vind
4059 if (!(IXGBE_READ_REG(hw, IXGBE_VT_CTL) & IXGBE_VT_CTL_VT_ENABLE))
4060 return IXGBE_SUCCESS;
4062 vlvf_index = ixgbe_find_vlvf_slot(hw, vlan, vlvf_bypass);
4066 bits = IXGBE_READ_REG(hw, IXGBE_VLVFB(vlvf_index * 2 + vind / 32));
4068 /* set the pool bit */
4069 bits |= 1 << (vind % 32);
4073 /* clear the pool bit */
4074 bits ^= 1 << (vind % 32);
4077 !IXGBE_READ_REG(hw, IXGBE_VLVFB(vlvf_index * 2 + 1 - vind / 32))) {
4078 /* Clear VFTA first, then disable VLVF. Otherwise
4079 * we run the risk of stray packets leaking into
4080 * the PF via the default pool
4083 IXGBE_WRITE_REG(hw, IXGBE_VFTA(vlan / 32), vfta);
4085 /* disable VLVF and clear remaining bit from pool */
4086 IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index), 0);
4087 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(vlvf_index * 2 + vind / 32), 0);
4089 return IXGBE_SUCCESS;
4092 /* If there are still bits set in the VLVFB registers
4093 * for the VLAN ID indicated we need to see if the
4094 * caller is requesting that we clear the VFTA entry bit.
4095 * If the caller has requested that we clear the VFTA
4096 * entry bit but there are still pools/VFs using this VLAN
4097 * ID entry then ignore the request. We're not worried
4098 * about the case where we're turning the VFTA VLAN ID
4099 * entry bit on, only when requested to turn it off as
4100 * there may be multiple pools and/or VFs using the
4101 * VLAN ID entry. In that case we cannot clear the
4102 * VFTA bit until all pools/VFs using that VLAN ID have also
4103 * been cleared. This will be indicated by "bits" being
4109 /* record pool change and enable VLAN ID if not already enabled */
4110 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(vlvf_index * 2 + vind / 32), bits);
4111 IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index), IXGBE_VLVF_VIEN | vlan);
4113 return IXGBE_SUCCESS;
4117 * ixgbe_clear_vfta_generic - Clear VLAN filter table
4118 * @hw: pointer to hardware structure
4120 * Clears the VLAN filer table, and the VMDq index associated with the filter
4122 s32 ixgbe_clear_vfta_generic(struct ixgbe_hw *hw)
4126 DEBUGFUNC("ixgbe_clear_vfta_generic");
4128 for (offset = 0; offset < hw->mac.vft_size; offset++)
4129 IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0);
4131 for (offset = 0; offset < IXGBE_VLVF_ENTRIES; offset++) {
4132 IXGBE_WRITE_REG(hw, IXGBE_VLVF(offset), 0);
4133 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(offset * 2), 0);
4134 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(offset * 2 + 1), 0);
4137 return IXGBE_SUCCESS;
4141 * ixgbe_need_crosstalk_fix - Determine if we need to do cross talk fix
4142 * @hw: pointer to hardware structure
4144 * Contains the logic to identify if we need to verify link for the
4147 static bool ixgbe_need_crosstalk_fix(struct ixgbe_hw *hw)
4150 /* Does FW say we need the fix */
4151 if (!hw->need_crosstalk_fix)
4154 /* Only consider SFP+ PHYs i.e. media type fiber */
4155 switch (hw->mac.ops.get_media_type(hw)) {
4156 case ixgbe_media_type_fiber:
4157 case ixgbe_media_type_fiber_qsfp:
4167 * ixgbe_check_mac_link_generic - Determine link and speed status
4168 * @hw: pointer to hardware structure
4169 * @speed: pointer to link speed
4170 * @link_up: TRUE when link is up
4171 * @link_up_wait_to_complete: bool used to wait for link up or not
4173 * Reads the links register to determine if link is up and the current speed
4175 s32 ixgbe_check_mac_link_generic(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
4176 bool *link_up, bool link_up_wait_to_complete)
4178 u32 links_reg, links_orig;
4181 DEBUGFUNC("ixgbe_check_mac_link_generic");
4183 /* If Crosstalk fix enabled do the sanity check of making sure
4184 * the SFP+ cage is full.
4186 if (ixgbe_need_crosstalk_fix(hw)) {
4189 switch (hw->mac.type) {
4190 case ixgbe_mac_82599EB:
4191 sfp_cage_full = IXGBE_READ_REG(hw, IXGBE_ESDP) &
4194 case ixgbe_mac_X550EM_x:
4195 case ixgbe_mac_X550EM_a:
4196 sfp_cage_full = IXGBE_READ_REG(hw, IXGBE_ESDP) &
4200 /* sanity check - No SFP+ devices here */
4201 sfp_cage_full = FALSE;
4205 if (!sfp_cage_full) {
4207 *speed = IXGBE_LINK_SPEED_UNKNOWN;
4208 return IXGBE_SUCCESS;
4212 /* clear the old state */
4213 links_orig = IXGBE_READ_REG(hw, IXGBE_LINKS);
4215 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
4217 if (links_orig != links_reg) {
4218 DEBUGOUT2("LINKS changed from %08X to %08X\n",
4219 links_orig, links_reg);
4222 if (link_up_wait_to_complete) {
4223 for (i = 0; i < hw->mac.max_link_up_time; i++) {
4224 if (links_reg & IXGBE_LINKS_UP) {
4231 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
4234 if (links_reg & IXGBE_LINKS_UP)
4240 switch (links_reg & IXGBE_LINKS_SPEED_82599) {
4241 case IXGBE_LINKS_SPEED_10G_82599:
4242 *speed = IXGBE_LINK_SPEED_10GB_FULL;
4243 if (hw->mac.type >= ixgbe_mac_X550) {
4244 if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
4245 *speed = IXGBE_LINK_SPEED_2_5GB_FULL;
4248 case IXGBE_LINKS_SPEED_1G_82599:
4249 *speed = IXGBE_LINK_SPEED_1GB_FULL;
4251 case IXGBE_LINKS_SPEED_100_82599:
4252 *speed = IXGBE_LINK_SPEED_100_FULL;
4253 if (hw->mac.type == ixgbe_mac_X550) {
4254 if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
4255 *speed = IXGBE_LINK_SPEED_5GB_FULL;
4258 case IXGBE_LINKS_SPEED_10_X550EM_A:
4259 *speed = IXGBE_LINK_SPEED_UNKNOWN;
4260 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T ||
4261 hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L)
4262 *speed = IXGBE_LINK_SPEED_10_FULL;
4265 *speed = IXGBE_LINK_SPEED_UNKNOWN;
4268 return IXGBE_SUCCESS;
4272 * ixgbe_get_wwn_prefix_generic - Get alternative WWNN/WWPN prefix from
4274 * @hw: pointer to hardware structure
4275 * @wwnn_prefix: the alternative WWNN prefix
4276 * @wwpn_prefix: the alternative WWPN prefix
4278 * This function will read the EEPROM from the alternative SAN MAC address
4279 * block to check the support for the alternative WWNN/WWPN prefix support.
4281 s32 ixgbe_get_wwn_prefix_generic(struct ixgbe_hw *hw, u16 *wwnn_prefix,
4285 u16 alt_san_mac_blk_offset;
4287 DEBUGFUNC("ixgbe_get_wwn_prefix_generic");
4289 /* clear output first */
4290 *wwnn_prefix = 0xFFFF;
4291 *wwpn_prefix = 0xFFFF;
4293 /* check if alternative SAN MAC is supported */
4294 offset = IXGBE_ALT_SAN_MAC_ADDR_BLK_PTR;
4295 if (hw->eeprom.ops.read(hw, offset, &alt_san_mac_blk_offset))
4296 goto wwn_prefix_err;
4298 if ((alt_san_mac_blk_offset == 0) ||
4299 (alt_san_mac_blk_offset == 0xFFFF))
4300 goto wwn_prefix_out;
4302 /* check capability in alternative san mac address block */
4303 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_CAPS_OFFSET;
4304 if (hw->eeprom.ops.read(hw, offset, &caps))
4305 goto wwn_prefix_err;
4306 if (!(caps & IXGBE_ALT_SAN_MAC_ADDR_CAPS_ALTWWN))
4307 goto wwn_prefix_out;
4309 /* get the corresponding prefix for WWNN/WWPN */
4310 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWNN_OFFSET;
4311 if (hw->eeprom.ops.read(hw, offset, wwnn_prefix)) {
4312 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
4313 "eeprom read at offset %d failed", offset);
4316 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWPN_OFFSET;
4317 if (hw->eeprom.ops.read(hw, offset, wwpn_prefix))
4318 goto wwn_prefix_err;
4321 return IXGBE_SUCCESS;
4324 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
4325 "eeprom read at offset %d failed", offset);
4326 return IXGBE_SUCCESS;
4330 * ixgbe_get_fcoe_boot_status_generic - Get FCOE boot status from EEPROM
4331 * @hw: pointer to hardware structure
4332 * @bs: the fcoe boot status
4334 * This function will read the FCOE boot status from the iSCSI FCOE block
4336 s32 ixgbe_get_fcoe_boot_status_generic(struct ixgbe_hw *hw, u16 *bs)
4338 u16 offset, caps, flags;
4341 DEBUGFUNC("ixgbe_get_fcoe_boot_status_generic");
4343 /* clear output first */
4344 *bs = ixgbe_fcoe_bootstatus_unavailable;
4346 /* check if FCOE IBA block is present */
4347 offset = IXGBE_FCOE_IBA_CAPS_BLK_PTR;
4348 status = hw->eeprom.ops.read(hw, offset, &caps);
4349 if (status != IXGBE_SUCCESS)
4352 if (!(caps & IXGBE_FCOE_IBA_CAPS_FCOE))
4355 /* check if iSCSI FCOE block is populated */
4356 status = hw->eeprom.ops.read(hw, IXGBE_ISCSI_FCOE_BLK_PTR, &offset);
4357 if (status != IXGBE_SUCCESS)
4360 if ((offset == 0) || (offset == 0xFFFF))
4363 /* read fcoe flags in iSCSI FCOE block */
4364 offset = offset + IXGBE_ISCSI_FCOE_FLAGS_OFFSET;
4365 status = hw->eeprom.ops.read(hw, offset, &flags);
4366 if (status != IXGBE_SUCCESS)
4369 if (flags & IXGBE_ISCSI_FCOE_FLAGS_ENABLE)
4370 *bs = ixgbe_fcoe_bootstatus_enabled;
4372 *bs = ixgbe_fcoe_bootstatus_disabled;
4379 * ixgbe_set_mac_anti_spoofing - Enable/Disable MAC anti-spoofing
4380 * @hw: pointer to hardware structure
4381 * @enable: enable or disable switch for MAC anti-spoofing
4382 * @vf: Virtual Function pool - VF Pool to set for MAC anti-spoofing
4385 void ixgbe_set_mac_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf)
4387 int vf_target_reg = vf >> 3;
4388 int vf_target_shift = vf % 8;
4391 if (hw->mac.type == ixgbe_mac_82598EB)
4394 pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg));
4396 pfvfspoof |= (1 << vf_target_shift);
4398 pfvfspoof &= ~(1 << vf_target_shift);
4399 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof);
4403 * ixgbe_set_vlan_anti_spoofing - Enable/Disable VLAN anti-spoofing
4404 * @hw: pointer to hardware structure
4405 * @enable: enable or disable switch for VLAN anti-spoofing
4406 * @vf: Virtual Function pool - VF Pool to set for VLAN anti-spoofing
4409 void ixgbe_set_vlan_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf)
4411 int vf_target_reg = vf >> 3;
4412 int vf_target_shift = vf % 8 + IXGBE_SPOOF_VLANAS_SHIFT;
4415 if (hw->mac.type == ixgbe_mac_82598EB)
4418 pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg));
4420 pfvfspoof |= (1 << vf_target_shift);
4422 pfvfspoof &= ~(1 << vf_target_shift);
4423 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof);
4427 * ixgbe_get_device_caps_generic - Get additional device capabilities
4428 * @hw: pointer to hardware structure
4429 * @device_caps: the EEPROM word with the extra device capabilities
4431 * This function will read the EEPROM location for the device capabilities,
4432 * and return the word through device_caps.
4434 s32 ixgbe_get_device_caps_generic(struct ixgbe_hw *hw, u16 *device_caps)
4436 DEBUGFUNC("ixgbe_get_device_caps_generic");
4438 hw->eeprom.ops.read(hw, IXGBE_DEVICE_CAPS, device_caps);
4440 return IXGBE_SUCCESS;
4444 * ixgbe_enable_relaxed_ordering_gen2 - Enable relaxed ordering
4445 * @hw: pointer to hardware structure
4448 void ixgbe_enable_relaxed_ordering_gen2(struct ixgbe_hw *hw)
4453 DEBUGFUNC("ixgbe_enable_relaxed_ordering_gen2");
4455 /* Enable relaxed ordering */
4456 for (i = 0; i < hw->mac.max_tx_queues; i++) {
4457 regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(i));
4458 regval |= IXGBE_DCA_TXCTRL_DESC_WRO_EN;
4459 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(i), regval);
4462 for (i = 0; i < hw->mac.max_rx_queues; i++) {
4463 regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
4464 regval |= IXGBE_DCA_RXCTRL_DATA_WRO_EN |
4465 IXGBE_DCA_RXCTRL_HEAD_WRO_EN;
4466 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval);
4472 * ixgbe_calculate_checksum - Calculate checksum for buffer
4473 * @buffer: pointer to EEPROM
4474 * @length: size of EEPROM to calculate a checksum for
4475 * Calculates the checksum for some buffer on a specified length. The
4476 * checksum calculated is returned.
4478 u8 ixgbe_calculate_checksum(u8 *buffer, u32 length)
4483 DEBUGFUNC("ixgbe_calculate_checksum");
4488 for (i = 0; i < length; i++)
4491 return (u8) (0 - sum);
4495 * ixgbe_hic_unlocked - Issue command to manageability block unlocked
4496 * @hw: pointer to the HW structure
4497 * @buffer: command to write and where the return status will be placed
4498 * @length: length of buffer, must be multiple of 4 bytes
4499 * @timeout: time in ms to wait for command completion
4501 * Communicates with the manageability block. On success return IXGBE_SUCCESS
4502 * else returns semaphore error when encountering an error acquiring
4503 * semaphore or IXGBE_ERR_HOST_INTERFACE_COMMAND when command fails.
4505 * This function assumes that the IXGBE_GSSR_SW_MNG_SM semaphore is held
4508 s32 ixgbe_hic_unlocked(struct ixgbe_hw *hw, u32 *buffer, u32 length,
4514 DEBUGFUNC("ixgbe_hic_unlocked");
4516 if (!length || length > IXGBE_HI_MAX_BLOCK_BYTE_LENGTH) {
4517 DEBUGOUT1("Buffer length failure buffersize=%d.\n", length);
4518 return IXGBE_ERR_HOST_INTERFACE_COMMAND;
4521 /* Set bit 9 of FWSTS clearing FW reset indication */
4522 fwsts = IXGBE_READ_REG(hw, IXGBE_FWSTS);
4523 IXGBE_WRITE_REG(hw, IXGBE_FWSTS, fwsts | IXGBE_FWSTS_FWRI);
4525 /* Check that the host interface is enabled. */
4526 hicr = IXGBE_READ_REG(hw, IXGBE_HICR);
4527 if (!(hicr & IXGBE_HICR_EN)) {
4528 DEBUGOUT("IXGBE_HOST_EN bit disabled.\n");
4529 return IXGBE_ERR_HOST_INTERFACE_COMMAND;
4532 /* Calculate length in DWORDs. We must be DWORD aligned */
4533 if (length % sizeof(u32)) {
4534 DEBUGOUT("Buffer length failure, not aligned to dword");
4535 return IXGBE_ERR_INVALID_ARGUMENT;
4538 dword_len = length >> 2;
4540 /* The device driver writes the relevant command block
4541 * into the ram area.
4543 for (i = 0; i < dword_len; i++)
4544 IXGBE_WRITE_REG_ARRAY(hw, IXGBE_FLEX_MNG,
4545 i, IXGBE_CPU_TO_LE32(buffer[i]));
4547 /* Setting this bit tells the ARC that a new command is pending. */
4548 IXGBE_WRITE_REG(hw, IXGBE_HICR, hicr | IXGBE_HICR_C);
4550 for (i = 0; i < timeout; i++) {
4551 hicr = IXGBE_READ_REG(hw, IXGBE_HICR);
4552 if (!(hicr & IXGBE_HICR_C))
4557 /* Check command completion */
4558 if ((timeout && i == timeout) ||
4559 !(IXGBE_READ_REG(hw, IXGBE_HICR) & IXGBE_HICR_SV)) {
4560 ERROR_REPORT1(IXGBE_ERROR_CAUTION,
4561 "Command has failed with no status valid.\n");
4562 return IXGBE_ERR_HOST_INTERFACE_COMMAND;
4565 return IXGBE_SUCCESS;
4569 * ixgbe_host_interface_command - Issue command to manageability block
4570 * @hw: pointer to the HW structure
4571 * @buffer: contains the command to write and where the return status will
4573 * @length: length of buffer, must be multiple of 4 bytes
4574 * @timeout: time in ms to wait for command completion
4575 * @return_data: read and return data from the buffer (TRUE) or not (FALSE)
4576 * Needed because FW structures are big endian and decoding of
4577 * these fields can be 8 bit or 16 bit based on command. Decoding
4578 * is not easily understood without making a table of commands.
4579 * So we will leave this up to the caller to read back the data
4582 * Communicates with the manageability block. On success return IXGBE_SUCCESS
4583 * else returns semaphore error when encountering an error acquiring
4584 * semaphore or IXGBE_ERR_HOST_INTERFACE_COMMAND when command fails.
4586 s32 ixgbe_host_interface_command(struct ixgbe_hw *hw, u32 *buffer,
4587 u32 length, u32 timeout, bool return_data)
4589 u32 hdr_size = sizeof(struct ixgbe_hic_hdr);
4590 struct ixgbe_hic_hdr *resp = (struct ixgbe_hic_hdr *)buffer;
4596 DEBUGFUNC("ixgbe_host_interface_command");
4598 if (length == 0 || length > IXGBE_HI_MAX_BLOCK_BYTE_LENGTH) {
4599 DEBUGOUT1("Buffer length failure buffersize=%d.\n", length);
4600 return IXGBE_ERR_HOST_INTERFACE_COMMAND;
4603 /* Take management host interface semaphore */
4604 status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_SW_MNG_SM);
4608 status = ixgbe_hic_unlocked(hw, buffer, length, timeout);
4615 /* Calculate length in DWORDs */
4616 dword_len = hdr_size >> 2;
4618 /* first pull in the header so we know the buffer length */
4619 for (bi = 0; bi < dword_len; bi++) {
4620 buffer[bi] = IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, bi);
4621 IXGBE_LE32_TO_CPUS(&buffer[bi]);
4625 * If there is any thing in data position pull it in
4626 * Read Flash command requires reading buffer length from
4627 * two byes instead of one byte
4629 if (resp->cmd == 0x30) {
4630 for (; bi < dword_len + 2; bi++) {
4631 buffer[bi] = IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG,
4633 IXGBE_LE32_TO_CPUS(&buffer[bi]);
4635 buf_len = (((u16)(resp->cmd_or_resp.ret_status) << 3)
4636 & 0xF00) | resp->buf_len;
4637 hdr_size += (2 << 2);
4639 buf_len = resp->buf_len;
4644 if (length < buf_len + hdr_size) {
4645 DEBUGOUT("Buffer not large enough for reply message.\n");
4646 status = IXGBE_ERR_HOST_INTERFACE_COMMAND;
4650 /* Calculate length in DWORDs, add 3 for odd lengths */
4651 dword_len = (buf_len + 3) >> 2;
4653 /* Pull in the rest of the buffer (bi is where we left off) */
4654 for (; bi <= dword_len; bi++) {
4655 buffer[bi] = IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, bi);
4656 IXGBE_LE32_TO_CPUS(&buffer[bi]);
4660 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_SW_MNG_SM);
4666 * ixgbe_set_fw_drv_ver_generic - Sends driver version to firmware
4667 * @hw: pointer to the HW structure
4668 * @maj: driver version major number
4669 * @min: driver version minor number
4670 * @build: driver version build number
4671 * @sub: driver version sub build number
4673 * @driver_ver: unused
4675 * Sends driver version number to firmware through the manageability
4676 * block. On success return IXGBE_SUCCESS
4677 * else returns IXGBE_ERR_SWFW_SYNC when encountering an error acquiring
4678 * semaphore or IXGBE_ERR_HOST_INTERFACE_COMMAND when command fails.
4680 s32 ixgbe_set_fw_drv_ver_generic(struct ixgbe_hw *hw, u8 maj, u8 min,
4681 u8 build, u8 sub, u16 len,
4682 const char *driver_ver)
4684 struct ixgbe_hic_drv_info fw_cmd;
4686 s32 ret_val = IXGBE_SUCCESS;
4688 DEBUGFUNC("ixgbe_set_fw_drv_ver_generic");
4689 UNREFERENCED_2PARAMETER(len, driver_ver);
4691 fw_cmd.hdr.cmd = FW_CEM_CMD_DRIVER_INFO;
4692 fw_cmd.hdr.buf_len = FW_CEM_CMD_DRIVER_INFO_LEN;
4693 fw_cmd.hdr.cmd_or_resp.cmd_resv = FW_CEM_CMD_RESERVED;
4694 fw_cmd.port_num = (u8)hw->bus.func;
4695 fw_cmd.ver_maj = maj;
4696 fw_cmd.ver_min = min;
4697 fw_cmd.ver_build = build;
4698 fw_cmd.ver_sub = sub;
4699 fw_cmd.hdr.checksum = 0;
4702 fw_cmd.hdr.checksum = ixgbe_calculate_checksum((u8 *)&fw_cmd,
4703 (FW_CEM_HDR_LEN + fw_cmd.hdr.buf_len));
4705 for (i = 0; i <= FW_CEM_MAX_RETRIES; i++) {
4706 ret_val = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,
4708 IXGBE_HI_COMMAND_TIMEOUT,
4710 if (ret_val != IXGBE_SUCCESS)
4713 if (fw_cmd.hdr.cmd_or_resp.ret_status ==
4714 FW_CEM_RESP_STATUS_SUCCESS)
4715 ret_val = IXGBE_SUCCESS;
4717 ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND;
4726 * ixgbe_set_rxpba_generic - Initialize Rx packet buffer
4727 * @hw: pointer to hardware structure
4728 * @num_pb: number of packet buffers to allocate
4729 * @headroom: reserve n KB of headroom
4730 * @strategy: packet buffer allocation strategy
4732 void ixgbe_set_rxpba_generic(struct ixgbe_hw *hw, int num_pb, u32 headroom,
4735 u32 pbsize = hw->mac.rx_pb_size;
4737 u32 rxpktsize, txpktsize, txpbthresh;
4739 /* Reserve headroom */
4745 /* Divide remaining packet buffer space amongst the number of packet
4746 * buffers requested using supplied strategy.
4749 case PBA_STRATEGY_WEIGHTED:
4750 /* ixgbe_dcb_pba_80_48 strategy weight first half of packet
4751 * buffer with 5/8 of the packet buffer space.
4753 rxpktsize = (pbsize * 5) / (num_pb * 4);
4754 pbsize -= rxpktsize * (num_pb / 2);
4755 rxpktsize <<= IXGBE_RXPBSIZE_SHIFT;
4756 for (; i < (num_pb / 2); i++)
4757 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize);
4758 /* fall through - configure remaining packet buffers */
4759 case PBA_STRATEGY_EQUAL:
4760 rxpktsize = (pbsize / (num_pb - i)) << IXGBE_RXPBSIZE_SHIFT;
4761 for (; i < num_pb; i++)
4762 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize);
4768 /* Only support an equally distributed Tx packet buffer strategy. */
4769 txpktsize = IXGBE_TXPBSIZE_MAX / num_pb;
4770 txpbthresh = (txpktsize / 1024) - IXGBE_TXPKT_SIZE_MAX;
4771 for (i = 0; i < num_pb; i++) {
4772 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), txpktsize);
4773 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), txpbthresh);
4776 /* Clear unused TCs, if any, to zero buffer size*/
4777 for (; i < IXGBE_MAX_PB; i++) {
4778 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0);
4779 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), 0);
4780 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), 0);
4785 * ixgbe_clear_tx_pending - Clear pending TX work from the PCIe fifo
4786 * @hw: pointer to the hardware structure
4788 * The 82599 and x540 MACs can experience issues if TX work is still pending
4789 * when a reset occurs. This function prevents this by flushing the PCIe
4790 * buffers on the system.
4792 void ixgbe_clear_tx_pending(struct ixgbe_hw *hw)
4794 u32 gcr_ext, hlreg0, i, poll;
4798 * If double reset is not requested then all transactions should
4799 * already be clear and as such there is no work to do
4801 if (!(hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED))
4805 * Set loopback enable to prevent any transmits from being sent
4806 * should the link come up. This assumes that the RXCTRL.RXEN bit
4807 * has already been cleared.
4809 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
4810 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0 | IXGBE_HLREG0_LPBK);
4812 /* Wait for a last completion before clearing buffers */
4813 IXGBE_WRITE_FLUSH(hw);
4817 * Before proceeding, make sure that the PCIe block does not have
4818 * transactions pending.
4820 poll = ixgbe_pcie_timeout_poll(hw);
4821 for (i = 0; i < poll; i++) {
4823 value = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_DEVICE_STATUS);
4824 if (IXGBE_REMOVED(hw->hw_addr))
4826 if (!(value & IXGBE_PCI_DEVICE_STATUS_TRANSACTION_PENDING))
4831 /* initiate cleaning flow for buffers in the PCIe transaction layer */
4832 gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
4833 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT,
4834 gcr_ext | IXGBE_GCR_EXT_BUFFERS_CLEAR);
4836 /* Flush all writes and allow 20usec for all transactions to clear */
4837 IXGBE_WRITE_FLUSH(hw);
4840 /* restore previous register values */
4841 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
4842 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
4846 * ixgbe_bypass_rw_generic - Bit bang data into by_pass FW
4848 * @hw: pointer to hardware structure
4849 * @cmd: Command we send to the FW
4850 * @status: The reply from the FW
4852 * Bit-bangs the cmd to the by_pass FW status points to what is returned.
4854 #define IXGBE_BYPASS_BB_WAIT 1
4855 s32 ixgbe_bypass_rw_generic(struct ixgbe_hw *hw, u32 cmd, u32 *status)
4858 u32 sck, sdi, sdo, dir_sck, dir_sdi, dir_sdo;
4862 return IXGBE_ERR_PARAM;
4866 /* SDP vary by MAC type */
4867 switch (hw->mac.type) {
4868 case ixgbe_mac_82599EB:
4869 sck = IXGBE_ESDP_SDP7;
4870 sdi = IXGBE_ESDP_SDP0;
4871 sdo = IXGBE_ESDP_SDP6;
4872 dir_sck = IXGBE_ESDP_SDP7_DIR;
4873 dir_sdi = IXGBE_ESDP_SDP0_DIR;
4874 dir_sdo = IXGBE_ESDP_SDP6_DIR;
4876 case ixgbe_mac_X540:
4877 sck = IXGBE_ESDP_SDP2;
4878 sdi = IXGBE_ESDP_SDP0;
4879 sdo = IXGBE_ESDP_SDP1;
4880 dir_sck = IXGBE_ESDP_SDP2_DIR;
4881 dir_sdi = IXGBE_ESDP_SDP0_DIR;
4882 dir_sdo = IXGBE_ESDP_SDP1_DIR;
4885 return IXGBE_ERR_DEVICE_NOT_SUPPORTED;
4888 /* Set SDP pins direction */
4889 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
4890 esdp |= dir_sck; /* SCK as output */
4891 esdp |= dir_sdi; /* SDI as output */
4892 esdp &= ~dir_sdo; /* SDO as input */
4895 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
4896 IXGBE_WRITE_FLUSH(hw);
4897 msec_delay(IXGBE_BYPASS_BB_WAIT);
4899 /* Generate start condition */
4901 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
4902 IXGBE_WRITE_FLUSH(hw);
4903 msec_delay(IXGBE_BYPASS_BB_WAIT);
4906 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
4907 IXGBE_WRITE_FLUSH(hw);
4908 msec_delay(IXGBE_BYPASS_BB_WAIT);
4910 /* Clock out the new control word and clock in the status */
4911 for (i = 0; i < 32; i++) {
4912 if ((cmd >> (31 - i)) & 0x01) {
4914 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
4917 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
4919 IXGBE_WRITE_FLUSH(hw);
4920 msec_delay(IXGBE_BYPASS_BB_WAIT);
4923 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
4924 IXGBE_WRITE_FLUSH(hw);
4925 msec_delay(IXGBE_BYPASS_BB_WAIT);
4928 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
4929 IXGBE_WRITE_FLUSH(hw);
4930 msec_delay(IXGBE_BYPASS_BB_WAIT);
4932 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
4934 *status = (*status << 1) | 0x01;
4936 *status = (*status << 1) | 0x00;
4937 msec_delay(IXGBE_BYPASS_BB_WAIT);
4940 /* stop condition */
4943 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
4944 IXGBE_WRITE_FLUSH(hw);
4945 msec_delay(IXGBE_BYPASS_BB_WAIT);
4948 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
4949 IXGBE_WRITE_FLUSH(hw);
4951 /* set the page bits to match the cmd that the status it belongs to */
4952 *status = (*status & 0x3fffffff) | (cmd & 0xc0000000);
4954 return IXGBE_SUCCESS;
4958 * ixgbe_bypass_valid_rd_generic - Verify valid return from bit-bang.
4960 * If we send a write we can't be sure it took until we can read back
4961 * that same register. It can be a problem as some of the feilds may
4962 * for valid reasons change inbetween the time wrote the register and
4963 * we read it again to verify. So this function check everything we
4964 * can check and then assumes it worked.
4966 * @u32 in_reg - The register cmd for the bit-bang read.
4967 * @u32 out_reg - The register returned from a bit-bang read.
4969 bool ixgbe_bypass_valid_rd_generic(u32 in_reg, u32 out_reg)
4973 /* Page must match for all control pages */
4974 if ((in_reg & BYPASS_PAGE_M) != (out_reg & BYPASS_PAGE_M))
4977 switch (in_reg & BYPASS_PAGE_M) {
4978 case BYPASS_PAGE_CTL0:
4979 /* All the following can't change since the last write
4980 * - All the event actions
4981 * - The timeout value
4983 mask = BYPASS_AUX_ON_M | BYPASS_MAIN_ON_M |
4984 BYPASS_MAIN_OFF_M | BYPASS_AUX_OFF_M |
4985 BYPASS_WDTIMEOUT_M |
4987 if ((out_reg & mask) != (in_reg & mask))
4990 /* 0x0 is never a valid value for bypass status */
4991 if (!(out_reg & BYPASS_STATUS_OFF_M))
4994 case BYPASS_PAGE_CTL1:
4995 /* All the following can't change since the last write
4997 * - time we last sent
4999 mask = BYPASS_CTL1_VALID_M | BYPASS_CTL1_TIME_M;
5000 if ((out_reg & mask) != (in_reg & mask))
5003 case BYPASS_PAGE_CTL2:
5004 /* All we can check in this page is control number
5005 * which is already done above.
5010 /* We are as sure as we can be return TRUE */
5015 * ixgbe_bypass_set_generic - Set a bypass field in the FW CTRL Regiter.
5017 * @hw: pointer to hardware structure
5018 * @cmd: The control word we are setting.
5019 * @event: The event we are setting in the FW. This also happens to
5020 * be the mask for the event we are setting (handy)
5021 * @action: The action we set the event to in the FW. This is in a
5022 * bit field that happens to be what we want to put in
5023 * the event spot (also handy)
5025 s32 ixgbe_bypass_set_generic(struct ixgbe_hw *hw, u32 ctrl, u32 event,
5032 /* Get current values */
5033 cmd = ctrl; /* just reading only need control number */
5034 if (ixgbe_bypass_rw_generic(hw, cmd, &by_ctl))
5035 return IXGBE_ERR_INVALID_ARGUMENT;
5037 /* Set to new action */
5038 cmd = (by_ctl & ~event) | BYPASS_WE | action;
5039 if (ixgbe_bypass_rw_generic(hw, cmd, &by_ctl))
5040 return IXGBE_ERR_INVALID_ARGUMENT;
5042 /* Page 0 force a FW eeprom write which is slow so verify */
5043 if ((cmd & BYPASS_PAGE_M) == BYPASS_PAGE_CTL0) {
5044 verify = BYPASS_PAGE_CTL0;
5047 return IXGBE_BYPASS_FW_WRITE_FAILURE;
5049 if (ixgbe_bypass_rw_generic(hw, verify, &by_ctl))
5050 return IXGBE_ERR_INVALID_ARGUMENT;
5051 } while (!ixgbe_bypass_valid_rd_generic(cmd, by_ctl));
5053 /* We have give the FW time for the write to stick */
5057 return IXGBE_SUCCESS;
5061 * ixgbe_bypass_rd_eep_generic - Read the bypass FW eeprom addres.
5063 * @hw: pointer to hardware structure
5064 * @addr: The bypass eeprom address to read.
5065 * @value: The 8b of data at the address above.
5067 s32 ixgbe_bypass_rd_eep_generic(struct ixgbe_hw *hw, u32 addr, u8 *value)
5073 /* send the request */
5074 cmd = BYPASS_PAGE_CTL2 | BYPASS_WE;
5075 cmd |= (addr << BYPASS_CTL2_OFFSET_SHIFT) & BYPASS_CTL2_OFFSET_M;
5076 if (ixgbe_bypass_rw_generic(hw, cmd, &status))
5077 return IXGBE_ERR_INVALID_ARGUMENT;
5079 /* We have give the FW time for the write to stick */
5082 /* now read the results */
5084 if (ixgbe_bypass_rw_generic(hw, cmd, &status))
5085 return IXGBE_ERR_INVALID_ARGUMENT;
5087 *value = status & BYPASS_CTL2_DATA_M;
5089 return IXGBE_SUCCESS;
5093 * ixgbe_get_orom_version - Return option ROM from EEPROM
5095 * @hw: pointer to hardware structure
5096 * @nvm_ver: pointer to output structure
5098 * if valid option ROM version, nvm_ver->or_valid set to TRUE
5099 * else nvm_ver->or_valid is FALSE.
5101 void ixgbe_get_orom_version(struct ixgbe_hw *hw,
5102 struct ixgbe_nvm_version *nvm_ver)
5104 u16 offset, eeprom_cfg_blkh, eeprom_cfg_blkl;
5106 nvm_ver->or_valid = FALSE;
5107 /* Option Rom may or may not be present. Start with pointer */
5108 hw->eeprom.ops.read(hw, NVM_OROM_OFFSET, &offset);
5110 /* make sure offset is valid */
5111 if ((offset == 0x0) || (offset == NVM_INVALID_PTR))
5114 hw->eeprom.ops.read(hw, offset + NVM_OROM_BLK_HI, &eeprom_cfg_blkh);
5115 hw->eeprom.ops.read(hw, offset + NVM_OROM_BLK_LOW, &eeprom_cfg_blkl);
5117 /* option rom exists and is valid */
5118 if ((eeprom_cfg_blkl | eeprom_cfg_blkh) == 0x0 ||
5119 eeprom_cfg_blkl == NVM_VER_INVALID ||
5120 eeprom_cfg_blkh == NVM_VER_INVALID)
5123 nvm_ver->or_valid = TRUE;
5124 nvm_ver->or_major = eeprom_cfg_blkl >> NVM_OROM_SHIFT;
5125 nvm_ver->or_build = (eeprom_cfg_blkl << NVM_OROM_SHIFT) |
5126 (eeprom_cfg_blkh >> NVM_OROM_SHIFT);
5127 nvm_ver->or_patch = eeprom_cfg_blkh & NVM_OROM_PATCH_MASK;
5131 * ixgbe_get_oem_prod_version - Return OEM Product version
5133 * @hw: pointer to hardware structure
5134 * @nvm_ver: pointer to output structure
5136 * if valid OEM product version, nvm_ver->oem_valid set to TRUE
5137 * else nvm_ver->oem_valid is FALSE.
5139 void ixgbe_get_oem_prod_version(struct ixgbe_hw *hw,
5140 struct ixgbe_nvm_version *nvm_ver)
5142 u16 rel_num, prod_ver, mod_len, cap, offset;
5144 nvm_ver->oem_valid = FALSE;
5145 hw->eeprom.ops.read(hw, NVM_OEM_PROD_VER_PTR, &offset);
5147 /* Return is offset to OEM Product Version block is invalid */
5148 if (offset == 0x0 && offset == NVM_INVALID_PTR)
5151 /* Read product version block */
5152 hw->eeprom.ops.read(hw, offset, &mod_len);
5153 hw->eeprom.ops.read(hw, offset + NVM_OEM_PROD_VER_CAP_OFF, &cap);
5155 /* Return if OEM product version block is invalid */
5156 if (mod_len != NVM_OEM_PROD_VER_MOD_LEN ||
5157 (cap & NVM_OEM_PROD_VER_CAP_MASK) != 0x0)
5160 hw->eeprom.ops.read(hw, offset + NVM_OEM_PROD_VER_OFF_L, &prod_ver);
5161 hw->eeprom.ops.read(hw, offset + NVM_OEM_PROD_VER_OFF_H, &rel_num);
5163 /* Return if version is invalid */
5164 if ((rel_num | prod_ver) == 0x0 ||
5165 rel_num == NVM_VER_INVALID || prod_ver == NVM_VER_INVALID)
5168 nvm_ver->oem_major = prod_ver >> NVM_VER_SHIFT;
5169 nvm_ver->oem_minor = prod_ver & NVM_VER_MASK;
5170 nvm_ver->oem_release = rel_num;
5171 nvm_ver->oem_valid = TRUE;
5175 * ixgbe_get_etk_id - Return Etrack ID from EEPROM
5177 * @hw: pointer to hardware structure
5178 * @nvm_ver: pointer to output structure
5180 * word read errors will return 0xFFFF
5182 void ixgbe_get_etk_id(struct ixgbe_hw *hw, struct ixgbe_nvm_version *nvm_ver)
5184 u16 etk_id_l, etk_id_h;
5186 if (hw->eeprom.ops.read(hw, NVM_ETK_OFF_LOW, &etk_id_l))
5187 etk_id_l = NVM_VER_INVALID;
5188 if (hw->eeprom.ops.read(hw, NVM_ETK_OFF_HI, &etk_id_h))
5189 etk_id_h = NVM_VER_INVALID;
5191 /* The word order for the version format is determined by high order
5194 if ((etk_id_h & NVM_ETK_VALID) == 0) {
5195 nvm_ver->etk_id = etk_id_h;
5196 nvm_ver->etk_id |= (etk_id_l << NVM_ETK_SHIFT);
5198 nvm_ver->etk_id = etk_id_l;
5199 nvm_ver->etk_id |= (etk_id_h << NVM_ETK_SHIFT);
5205 * ixgbe_dcb_get_rtrup2tc_generic - read rtrup2tc reg
5206 * @hw: pointer to hardware structure
5207 * @map: pointer to u8 arr for returning map
5209 * Read the rtrup2tc HW register and resolve its content into map
5211 void ixgbe_dcb_get_rtrup2tc_generic(struct ixgbe_hw *hw, u8 *map)
5215 reg = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC);
5216 for (i = 0; i < IXGBE_DCB_MAX_USER_PRIORITY; i++)
5217 map[i] = IXGBE_RTRUP2TC_UP_MASK &
5218 (reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT));
5222 void ixgbe_disable_rx_generic(struct ixgbe_hw *hw)
5227 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
5228 if (rxctrl & IXGBE_RXCTRL_RXEN) {
5229 if (hw->mac.type != ixgbe_mac_82598EB) {
5230 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
5231 if (pfdtxgswc & IXGBE_PFDTXGSWC_VT_LBEN) {
5232 pfdtxgswc &= ~IXGBE_PFDTXGSWC_VT_LBEN;
5233 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc);
5234 hw->mac.set_lben = TRUE;
5236 hw->mac.set_lben = FALSE;
5239 rxctrl &= ~IXGBE_RXCTRL_RXEN;
5240 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl);
5244 void ixgbe_enable_rx_generic(struct ixgbe_hw *hw)
5249 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
5250 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, (rxctrl | IXGBE_RXCTRL_RXEN));
5252 if (hw->mac.type != ixgbe_mac_82598EB) {
5253 if (hw->mac.set_lben) {
5254 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
5255 pfdtxgswc |= IXGBE_PFDTXGSWC_VT_LBEN;
5256 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc);
5257 hw->mac.set_lben = FALSE;
5263 * ixgbe_mng_present - returns TRUE when management capability is present
5264 * @hw: pointer to hardware structure
5266 bool ixgbe_mng_present(struct ixgbe_hw *hw)
5270 if (hw->mac.type < ixgbe_mac_82599EB)
5273 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM_BY_MAC(hw));
5275 return !!(fwsm & IXGBE_FWSM_FW_MODE_PT);
5279 * ixgbe_mng_enabled - Is the manageability engine enabled?
5280 * @hw: pointer to hardware structure
5282 * Returns TRUE if the manageability engine is enabled.
5284 bool ixgbe_mng_enabled(struct ixgbe_hw *hw)
5286 u32 fwsm, manc, factps;
5288 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM_BY_MAC(hw));
5289 if ((fwsm & IXGBE_FWSM_MODE_MASK) != IXGBE_FWSM_FW_MODE_PT)
5292 manc = IXGBE_READ_REG(hw, IXGBE_MANC);
5293 if (!(manc & IXGBE_MANC_RCV_TCO_EN))
5296 if (hw->mac.type <= ixgbe_mac_X540) {
5297 factps = IXGBE_READ_REG(hw, IXGBE_FACTPS_BY_MAC(hw));
5298 if (factps & IXGBE_FACTPS_MNGCG)
5306 * ixgbe_setup_mac_link_multispeed_fiber - Set MAC link speed
5307 * @hw: pointer to hardware structure
5308 * @speed: new link speed
5309 * @autoneg_wait_to_complete: TRUE when waiting for completion is needed
5311 * Set the link speed in the MAC and/or PHY register and restarts link.
5313 s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw,
5314 ixgbe_link_speed speed,
5315 bool autoneg_wait_to_complete)
5317 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
5318 ixgbe_link_speed highest_link_speed = IXGBE_LINK_SPEED_UNKNOWN;
5319 s32 status = IXGBE_SUCCESS;
5322 bool autoneg, link_up = FALSE;
5324 DEBUGFUNC("ixgbe_setup_mac_link_multispeed_fiber");
5326 /* Mask off requested but non-supported speeds */
5327 status = ixgbe_get_link_capabilities(hw, &link_speed, &autoneg);
5328 if (status != IXGBE_SUCCESS)
5331 speed &= link_speed;
5333 /* Try each speed one by one, highest priority first. We do this in
5334 * software because 10Gb fiber doesn't support speed autonegotiation.
5336 if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
5338 highest_link_speed = IXGBE_LINK_SPEED_10GB_FULL;
5340 /* Set the module link speed */
5341 switch (hw->phy.media_type) {
5342 case ixgbe_media_type_fiber_fixed:
5343 case ixgbe_media_type_fiber:
5344 ixgbe_set_rate_select_speed(hw,
5345 IXGBE_LINK_SPEED_10GB_FULL);
5347 case ixgbe_media_type_fiber_qsfp:
5348 /* QSFP module automatically detects MAC link speed */
5351 DEBUGOUT("Unexpected media type.\n");
5355 /* Allow module to change analog characteristics (1G->10G) */
5358 status = ixgbe_setup_mac_link(hw,
5359 IXGBE_LINK_SPEED_10GB_FULL,
5360 autoneg_wait_to_complete);
5361 if (status != IXGBE_SUCCESS)
5364 /* Flap the Tx laser if it has not already been done */
5365 ixgbe_flap_tx_laser(hw);
5367 /* Wait for the controller to acquire link. Per IEEE 802.3ap,
5368 * Section 73.10.2, we may have to wait up to 500ms if KR is
5369 * attempted. 82599 uses the same timing for 10g SFI.
5371 for (i = 0; i < 5; i++) {
5372 /* Wait for the link partner to also set speed */
5375 /* If we have link, just jump out */
5376 status = ixgbe_check_link(hw, &link_speed,
5378 if (status != IXGBE_SUCCESS)
5386 if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
5388 if (highest_link_speed == IXGBE_LINK_SPEED_UNKNOWN)
5389 highest_link_speed = IXGBE_LINK_SPEED_1GB_FULL;
5391 /* Set the module link speed */
5392 switch (hw->phy.media_type) {
5393 case ixgbe_media_type_fiber_fixed:
5394 case ixgbe_media_type_fiber:
5395 ixgbe_set_rate_select_speed(hw,
5396 IXGBE_LINK_SPEED_1GB_FULL);
5398 case ixgbe_media_type_fiber_qsfp:
5399 /* QSFP module automatically detects link speed */
5402 DEBUGOUT("Unexpected media type.\n");
5406 /* Allow module to change analog characteristics (10G->1G) */
5409 status = ixgbe_setup_mac_link(hw,
5410 IXGBE_LINK_SPEED_1GB_FULL,
5411 autoneg_wait_to_complete);
5412 if (status != IXGBE_SUCCESS)
5415 /* Flap the Tx laser if it has not already been done */
5416 ixgbe_flap_tx_laser(hw);
5418 /* Wait for the link partner to also set speed */
5421 /* If we have link, just jump out */
5422 status = ixgbe_check_link(hw, &link_speed, &link_up, FALSE);
5423 if (status != IXGBE_SUCCESS)
5430 /* We didn't get link. Configure back to the highest speed we tried,
5431 * (if there was more than one). We call ourselves back with just the
5432 * single highest speed that the user requested.
5435 status = ixgbe_setup_mac_link_multispeed_fiber(hw,
5437 autoneg_wait_to_complete);
5440 /* Set autoneg_advertised value based on input link speed */
5441 hw->phy.autoneg_advertised = 0;
5443 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
5444 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
5446 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
5447 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
5453 * ixgbe_set_soft_rate_select_speed - Set module link speed
5454 * @hw: pointer to hardware structure
5455 * @speed: link speed to set
5457 * Set module link speed via the soft rate select.
5459 void ixgbe_set_soft_rate_select_speed(struct ixgbe_hw *hw,
5460 ixgbe_link_speed speed)
5466 case IXGBE_LINK_SPEED_10GB_FULL:
5467 /* one bit mask same as setting on */
5468 rs = IXGBE_SFF_SOFT_RS_SELECT_10G;
5470 case IXGBE_LINK_SPEED_1GB_FULL:
5471 rs = IXGBE_SFF_SOFT_RS_SELECT_1G;
5474 DEBUGOUT("Invalid fixed module speed\n");
5479 status = hw->phy.ops.read_i2c_byte(hw, IXGBE_SFF_SFF_8472_OSCB,
5480 IXGBE_I2C_EEPROM_DEV_ADDR2,
5483 DEBUGOUT("Failed to read Rx Rate Select RS0\n");
5487 eeprom_data = (eeprom_data & ~IXGBE_SFF_SOFT_RS_SELECT_MASK) | rs;
5489 status = hw->phy.ops.write_i2c_byte(hw, IXGBE_SFF_SFF_8472_OSCB,
5490 IXGBE_I2C_EEPROM_DEV_ADDR2,
5493 DEBUGOUT("Failed to write Rx Rate Select RS0\n");
5498 status = hw->phy.ops.read_i2c_byte(hw, IXGBE_SFF_SFF_8472_ESCB,
5499 IXGBE_I2C_EEPROM_DEV_ADDR2,
5502 DEBUGOUT("Failed to read Rx Rate Select RS1\n");
5506 eeprom_data = (eeprom_data & ~IXGBE_SFF_SOFT_RS_SELECT_MASK) | rs;
5508 status = hw->phy.ops.write_i2c_byte(hw, IXGBE_SFF_SFF_8472_ESCB,
5509 IXGBE_I2C_EEPROM_DEV_ADDR2,
5512 DEBUGOUT("Failed to write Rx Rate Select RS1\n");