Use a globaldata_t instead of a cpuid in the lwkt_token structure. The
[dragonfly.git] / sys / dev / misc / pcic / i82365reg.h
1 /*      $NetBSD: i82365reg.h,v 1.3 1998/12/20 17:53:28 nathanw Exp $    */
2 /* $FreeBSD: src/sys/dev/pcic/i82365reg.h,v 1.3.2.4 2001/07/09 07:19:58 imp Exp $ */
3 /* $DragonFly: src/sys/dev/misc/pcic/Attic/i82365reg.h,v 1.2 2003/06/17 04:28:29 dillon Exp $ */
4
5 /*
6  * Copyright (c) 1997 Marc Horowitz.  All rights reserved.
7  *
8  * Redistribution and use in source and binary forms, with or without
9  * modification, are permitted provided that the following conditions
10  * are met:
11  * 1. Redistributions of source code must retain the above copyright
12  *    notice, this list of conditions and the following disclaimer.
13  * 2. Redistributions in binary form must reproduce the above copyright
14  *    notice, this list of conditions and the following disclaimer in the
15  *    documentation and/or other materials provided with the distribution.
16  * 3. All advertising materials mentioning features or use of this software
17  *    must display the following acknowledgement:
18  *      This product includes software developed by Marc Horowitz.
19  * 4. The name of the author may not be used to endorse or promote products
20  *    derived from this software without specific prior written permission.
21  *
22  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
23  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
24  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
25  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
26  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
27  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
31  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32  */
33
34 /*
35  * All information is from the intel 82365sl PC Card Interface Controller
36  * (PCIC) data sheet, marked "preliminary".  Order number 290423-002, January
37  * 1993.
38  */
39
40 #define PCIC_IOSIZE             2
41
42 #define PCIC_REG_INDEX          0
43 #define PCIC_REG_DATA           1
44
45 /*
46  * I/o ports
47  */
48 #define PCIC_INDEX0             0x3e0
49
50 /*
51  * The PCIC allows two chips to share the same address.  In order not to run
52  * afoul of the netbsd device model, this driver will treat those chips as
53  * the same device.
54  */
55
56 #define PCIC_CHIP0_BASE         0x00
57 #define PCIC_CHIP1_BASE         0x80
58
59 /* Each PCIC chip can drive two sockets */
60
61 #define PCIC_SOCKETA_INDEX      0x00
62 #define PCIC_SOCKETB_INDEX      0x40
63
64 /* general setup registers */
65
66 #define PCIC_IDENT                              0x00    /* RO */
67 #define PCIC_IDENT_IFTYPE_MASK                  0xC0
68 #define PCIC_IDENT_IFTYPE_IO_ONLY               0x00
69 #define PCIC_IDENT_IFTYPE_MEM_ONLY              0x40
70 #define PCIC_IDENT_IFTYPE_MEM_AND_IO            0x80
71 #define PCIC_IDENT_IFTYPE_RESERVED              0xC0
72 #define PCIC_IDENT_ZERO                         0x30
73 #define PCIC_IDENT_REV_MASK                     0x0F
74 #define PCIC_IDENT_REV_I82365SLR0               0x02
75 #define PCIC_IDENT_REV_I82365SLR1               0x03
76
77 #define PCIC_IF_STATUS                          0x01    /* RO */
78 #define PCIC_IF_STATUS_GPI                      0x80 /* General Purpose Input */
79 #define PCIC_IF_STATUS_POWERACTIVE              0x40
80 #define PCIC_IF_STATUS_READY                    0x20 /* really READY/!BUSY */
81 #define PCIC_IF_STATUS_MEM_WP                   0x10
82 #define PCIC_IF_STATUS_CARDDETECT_MASK          0x0C
83 #define PCIC_IF_STATUS_CARDDETECT_PRESENT       0x0C
84 #define PCIC_IF_STATUS_BATTERY_MASK             0x03
85 #define PCIC_IF_STATUS_BATTERY_DEAD1            0x00
86 #define PCIC_IF_STATUS_BATTERY_DEAD2            0x01
87 #define PCIC_IF_STATUS_BATTERY_WARNING          0x02
88 #define PCIC_IF_STATUS_BATTERY_GOOD             0x03
89
90 #define PCIC_PWRCTL                             0x02    /* RW */
91 #define PCIC_PWRCTL_OE                          0x80    /* output enable */
92 #define PCIC_PWRCTL_DISABLE_RESETDRV            0x40
93 #define PCIC_PWRCTL_AUTOSWITCH_ENABLE           0x20
94 #define PCIC_PWRCTL_PWR_ENABLE                  0x10
95 #define PCIC_PWRCTL_VPP2_MASK                   0x0C
96 /* XXX these are a little unclear from the data sheet */
97 #define PCIC_PWRCTL_VPP2_RESERVED               0x0C
98 #define PCIC_PWRCTL_VPP2_EN1                    0x08
99 #define PCIC_PWRCTL_VPP2_EN0                    0x04
100 #define PCIC_PWRCTL_VPP2_ENX                    0x00
101 #define PCIC_PWRCTL_VPP1_MASK                   0x03
102 /* XXX these are a little unclear from the data sheet */
103 #define PCIC_PWRCTL_VPP1_RESERVED               0x03
104 #define PCIC_PWRCTL_VPP1_EN1                    0x02
105 #define PCIC_PWRCTL_VPP1_EN0                    0x01
106 #define PCIC_PWRCTL_VPP1_ENX                    0x00
107
108 #define PCIC_CSC                                0x04    /* RW */
109 #define PCIC_CSC_ZERO                           0xE0
110 #define PCIC_CSC_GPI                            0x10
111 #define PCIC_CSC_CD                             0x08 /* Card Detect Change */
112 #define PCIC_CSC_READY                          0x04
113 #define PCIC_CSC_BATTWARN                       0x02
114 #define PCIC_CSC_BATTDEAD                       0x01    /* for memory cards */
115 #define PCIC_CSC_RI                             0x01    /* for i/o cards */
116
117 #define PCIC_ADDRWIN_ENABLE                     0x06    /* RW */
118 #define PCIC_ADDRWIN_ENABLE_IO1                 0x80
119 #define PCIC_ADDRWIN_ENABLE_IO0                 0x40
120 #define PCIC_ADDRWIN_ENABLE_MEMCS16             0x20    /* rtfds if you care */
121 #define PCIC_ADDRWIN_ENABLE_MEM4                0x10
122 #define PCIC_ADDRWIN_ENABLE_MEM3                0x08
123 #define PCIC_ADDRWIN_ENABLE_MEM2                0x04
124 #define PCIC_ADDRWIN_ENABLE_MEM1                0x02
125 #define PCIC_ADDRWIN_ENABLE_MEM0                0x01
126
127 #define PCIC_CARD_DETECT                        0x16    /* RW */
128 #define PCIC_CARD_DETECT_RESERVED               0xC0
129 #define PCIC_CARD_DETECT_SW_INTR                0x20
130 #define PCIC_CARD_DETECT_RESUME_ENABLE          0x10
131 #define PCIC_CARD_DETECT_GPI_TRANSCTL           0x08
132 #define PCIC_CARD_DETECT_GPI_ENABLE             0x04
133 #define PCIC_CARD_DETECT_CFGRST_ENABLE          0x02
134 #define PCIC_CARD_DETECT_MEMDLY_INHIBIT         0x01
135
136 /* interrupt registers */
137
138 #define PCIC_INTR                               0x03    /* RW */
139 #define PCIC_INTR_RI_ENABLE                     0x80
140 #define PCIC_INTR_RESET                         0x40    /* active low (zero) */
141 #define PCIC_INTR_CARDTYPE_MASK                 0x20
142 #define PCIC_INTR_CARDTYPE_IO                   0x20
143 #define PCIC_INTR_CARDTYPE_MEM                  0x00
144 #define PCIC_INTR_ENABLE                        0x10
145 #define PCIC_INTR_IRQ_MASK                      0x0F
146 #define PCIC_INTR_IRQ_SHIFT                     0
147 #define PCIC_INTR_IRQ_NONE                      0x00
148 #define PCIC_INTR_IRQ_RESERVED1                 0x01
149 #define PCIC_INTR_IRQ_RESERVED2                 0x02
150 #define PCIC_INTR_IRQ3                          0x03
151 #define PCIC_INTR_IRQ4                          0x04
152 #define PCIC_INTR_IRQ5                          0x05
153 #define PCIC_INTR_IRQ_RESERVED6                 0x06
154 #define PCIC_INTR_IRQ7                          0x07
155 #define PCIC_INTR_IRQ_RESERVED8                 0x08
156 #define PCIC_INTR_IRQ9                          0x09
157 #define PCIC_INTR_IRQ10                         0x0A
158 #define PCIC_INTR_IRQ11                         0x0B
159 #define PCIC_INTR_IRQ12                         0x0C
160 #define PCIC_INTR_IRQ_RESERVED13                0x0D
161 #define PCIC_INTR_IRQ14                         0x0E
162 #define PCIC_INTR_IRQ15                         0x0F
163
164 #define PCIC_INTR_IRQ_VALIDMASK                 0xDEB8 /* 1101 1110 1011 1000 */
165
166 #define PCIC_CSC_INTR                           0x05    /* RW */
167 #define PCIC_CSC_INTR_IRQ_MASK                  0xF0
168 #define PCIC_CSC_INTR_IRQ_SHIFT                 4
169 #define PCIC_CSC_INTR_IRQ_NONE                  0x00
170 #define PCIC_CSC_INTR_IRQ_RESERVED1             0x10
171 #define PCIC_CSC_INTR_IRQ_RESERVED2             0x20
172 #define PCIC_CSC_INTR_IRQ3                      0x30
173 #define PCIC_CSC_INTR_IRQ4                      0x40
174 #define PCIC_CSC_INTR_IRQ5                      0x50
175 #define PCIC_CSC_INTR_IRQ_RESERVED6             0x60
176 #define PCIC_CSC_INTR_IRQ7                      0x70
177 #define PCIC_CSC_INTR_IRQ_RESERVED8             0x80
178 #define PCIC_CSC_INTR_IRQ9                      0x90
179 #define PCIC_CSC_INTR_IRQ10                     0xA0
180 #define PCIC_CSC_INTR_IRQ11                     0xB0
181 #define PCIC_CSC_INTR_IRQ12                     0xC0
182 #define PCIC_CSC_INTR_IRQ_RESERVED13            0xD0
183 #define PCIC_CSC_INTR_IRQ14                     0xE0
184 #define PCIC_CSC_INTR_IRQ15                     0xF0
185 #define PCIC_CSC_INTR_CD_ENABLE                 0x08
186 #define PCIC_CSC_INTR_READY_ENABLE              0x04
187 #define PCIC_CSC_INTR_BATTWARN_ENABLE           0x02
188 #define PCIC_CSC_INTR_BATTDEAD_ENABLE           0x01    /* for memory cards */
189 #define PCIC_CSC_INTR_RI_ENABLE                 0x01    /* for I/O cards */
190
191 #define PCIC_CSC_INTR_IRQ_VALIDMASK             0xDEB8 /* 1101 1110 1011 1000 */
192
193 /* I/O registers */
194
195 #define PCIC_IO_WINS                            2
196
197 #define PCIC_IOCTL                              0x07    /* RW */
198 #define PCIC_IOCTL_IO1_WAITSTATE                0x80
199 #define PCIC_IOCTL_IO1_ZEROWAIT                 0x40
200 #define PCIC_IOCTL_IO1_IOCS16SRC_MASK           0x20
201 #define PCIC_IOCTL_IO1_IOCS16SRC_CARD           0x20
202 #define PCIC_IOCTL_IO1_IOCS16SRC_DATASIZE       0x00
203 #define PCIC_IOCTL_IO1_DATASIZE_MASK            0x10
204 #define PCIC_IOCTL_IO1_DATASIZE_16BIT           0x10
205 #define PCIC_IOCTL_IO1_DATASIZE_8BIT            0x00
206 #define PCIC_IOCTL_IO0_WAITSTATE                0x08
207 #define PCIC_IOCTL_IO0_ZEROWAIT                 0x04
208 #define PCIC_IOCTL_IO0_IOCS16SRC_MASK           0x02
209 #define PCIC_IOCTL_IO0_IOCS16SRC_CARD           0x02
210 #define PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE       0x00
211 #define PCIC_IOCTL_IO0_DATASIZE_MASK            0x01
212 #define PCIC_IOCTL_IO0_DATASIZE_16BIT           0x01
213 #define PCIC_IOCTL_IO0_DATASIZE_8BIT            0x00
214
215 #define PCIC_IOADDR0_START_LSB                  0x08
216 #define PCIC_IOADDR0_START_MSB                  0x09
217 #define PCIC_IOADDR0_STOP_LSB                   0x0A
218 #define PCIC_IOADDR0_STOP_MSB                   0x0B
219 #define PCIC_IOADDR1_START_LSB                  0x0C
220 #define PCIC_IOADDR1_START_MSB                  0x0D
221 #define PCIC_IOADDR1_STOP_LSB                   0x0E
222 #define PCIC_IOADDR1_STOP_MSB                   0x0F
223
224 /* memory registers */
225
226 /*
227  * memory window addresses refer to bits A23-A12 of the ISA system memory
228  * address.  This is a shift of 12 bits.  The LSB contains A19-A12, and the
229  * MSB contains A23-A20, plus some other bits.
230  */
231
232 #define PCIC_MEM_WINS                           5
233
234 #define PCIC_MEM_SHIFT                          12
235 #define PCIC_MEM_PAGESIZE                       (1<<PCIC_MEM_SHIFT)
236
237 #define PCIC_SYSMEM_ADDRX_SHIFT                         PCIC_MEM_SHIFT
238 #define PCIC_SYSMEM_ADDRX_START_MSB_DATASIZE_MASK       0x80
239 #define PCIC_SYSMEM_ADDRX_START_MSB_DATASIZE_16BIT      0x80
240 #define PCIC_SYSMEM_ADDRX_START_MSB_DATASIZE_8BIT       0x00
241 #define PCIC_SYSMEM_ADDRX_START_MSB_ZEROWAIT            0x40
242 #define PCIC_SYSMEM_ADDRX_START_MSB_SCRATCH_MASK        0x30
243 #define PCIC_SYSMEM_ADDRX_START_MSB_ADDR_MASK           0x0F
244
245 #define PCIC_SYSMEM_ADDRX_STOP_MSB_WAIT_MASK            0xC0
246 #define PCIC_SYSMEM_ADDRX_STOP_MSB_WAIT0                0x00
247 #define PCIC_SYSMEM_ADDRX_STOP_MSB_WAIT1                0x40
248 #define PCIC_SYSMEM_ADDRX_STOP_MSB_WAIT2                0x80
249 #define PCIC_SYSMEM_ADDRX_STOP_MSB_WAIT3                0xC0
250 #define PCIC_SYSMEM_ADDRX_STOP_MSB_ADDR_MASK            0x0F
251
252 /*
253  * The card side of a memory mapping consists of bits A19-A12 of the card
254  * memory address in the LSB, and A25-A20 plus some other bits in the MSB.
255  * Again, the shift is 12 bits.
256  */
257
258 #define PCIC_CARDMEM_ADDRX_SHIFT                PCIC_MEM_SHIFT
259 #define PCIC_CARDMEM_ADDRX_MSB_WP               0x80
260 #define PCIC_CARDMEM_ADDRX_MSB_REGACTIVE_MASK   0x40
261 #define PCIC_CARDMEM_ADDRX_MSB_REGACTIVE_ATTR   0x40
262 #define PCIC_CARDMEM_ADDRX_MSB_REGACTIVE_COMMON 0x00
263 #define PCIC_CARDMEM_ADDRX_MSB_ADDR_MASK        0x3F
264
265 #define PCIC_SYSMEM_ADDR0_START_LSB             0x10
266 #define PCIC_SYSMEM_ADDR0_START_MSB             0x11
267 #define PCIC_SYSMEM_ADDR0_STOP_LSB              0x12
268 #define PCIC_SYSMEM_ADDR0_STOP_MSB              0x13
269
270 #define PCIC_CARDMEM_ADDR0_LSB                  0x14
271 #define PCIC_CARDMEM_ADDR0_MSB                  0x15
272
273 /* #define      PCIC_RESERVED                   0x17 */
274
275 #define PCIC_SYSMEM_ADDR1_START_LSB             0x18
276 #define PCIC_SYSMEM_ADDR1_START_MSB             0x19
277 #define PCIC_SYSMEM_ADDR1_STOP_LSB              0x1A
278 #define PCIC_SYSMEM_ADDR1_STOP_MSB              0x1B
279
280 #define PCIC_CARDMEM_ADDR1_LSB                  0x1C
281 #define PCIC_CARDMEM_ADDR1_MSB                  0x1D
282
283 #define PCIC_SYSMEM_ADDR2_START_LSB             0x20
284 #define PCIC_SYSMEM_ADDR2_START_MSB             0x21
285 #define PCIC_SYSMEM_ADDR2_STOP_LSB              0x22
286 #define PCIC_SYSMEM_ADDR2_STOP_MSB              0x23
287
288 #define PCIC_CARDMEM_ADDR2_LSB                  0x24
289 #define PCIC_CARDMEM_ADDR2_MSB                  0x25
290
291 /* #define      PCIC_RESERVED                   0x26 */
292 /* #define      PCIC_RESERVED                   0x27 */
293
294 #define PCIC_SYSMEM_ADDR3_START_LSB             0x28
295 #define PCIC_SYSMEM_ADDR3_START_MSB             0x29
296 #define PCIC_SYSMEM_ADDR3_STOP_LSB              0x2A
297 #define PCIC_SYSMEM_ADDR3_STOP_MSB              0x2B
298
299 #define PCIC_CARDMEM_ADDR3_LSB                  0x2C
300 #define PCIC_CARDMEM_ADDR3_MSB                  0x2D
301
302 /* #define      PCIC_RESERVED                   0x2E */
303 /* #define      PCIC_RESERVED                   0x2F */
304
305 #define PCIC_SYSMEM_ADDR4_START_LSB             0x30
306 #define PCIC_SYSMEM_ADDR4_START_MSB             0x31
307 #define PCIC_SYSMEM_ADDR4_STOP_LSB              0x32
308 #define PCIC_SYSMEM_ADDR4_STOP_MSB              0x33
309
310 #define PCIC_CARDMEM_ADDR4_LSB                  0x34
311 #define PCIC_CARDMEM_ADDR4_MSB                  0x35
312
313 /* #define      PCIC_RESERVED                   0x36 */
314 /* #define      PCIC_RESERVED                   0x37 */
315 /* #define      PCIC_RESERVED                   0x38 */
316 /* #define      PCIC_RESERVED                   0x39 */
317 /* #define      PCIC_RESERVED                   0x3A */
318 /* #define      PCIC_RESERVED                   0x3B */
319 /* #define      PCIC_RESERVED                   0x3C */
320 /* #define      PCIC_RESERVED                   0x3D */
321 /* #define      PCIC_RESERVED                   0x3E */
322 /* #define      PCIC_RESERVED                   0x3F */
323
324 /* cardbus extensions - memory window page registers */
325
326 #define PCIC_MEMREG_WIN_SHIFT                   24
327 #define PCIC_SYSMEM_ADDR0_WIN                   0x40
328 #define PCIC_SYSMEM_ADDR1_WIN                   0x41
329 #define PCIC_SYSMEM_ADDR2_WIN                   0x42
330 #define PCIC_SYSMEM_ADDR3_WIN                   0x43
331 #define PCIC_SYSMEM_ADDR4_WIN                   0x44
332
333 /* vendor-specific registers */
334
335 #define PCIC_INTEL_GLOBAL_CTL                   0x1E    /* RW */
336 #define PCIC_INTEL_GLOBAL_CTL_RESERVED          0xF0
337 #define PCIC_INTEL_GLOBAL_CTL_IRQ14PULSE_ENABLE 0x08
338 #define PCIC_INTEL_GLOBAL_CTL_EXPLICIT_CSC_ACK  0x04
339 #define PCIC_INTEL_GLOBAL_CTL_IRQLEVEL_ENABLE   0x02
340 #define PCIC_INTEL_GLOBAL_CTL_POWERDOWN         0x01
341
342 #define PCIC_CIRRUS_MISC_CTL_2                  0x1E
343 #define PCIC_CIRRUS_MISC_CTL_2_SUSPEND          0x04
344
345 #define PCIC_CIRRUS_CHIP_INFO                   0x1F
346 #define PCIC_CIRRUS_CHIP_INFO_CHIP_ID           0xC0
347 #define PCIC_CIRRUS_CHIP_INFO_SLOTS             0x20
348 #define PCIC_CIRRUS_CHIP_INFO_REV               0x1F
349
350 #define PCIC_CIRRUS_EXTENDED_INDEX              0x2E
351 #define PCIC_CIRRUS_EXTENDED_DATA               0x2F
352 #define PCIC_CIRRUS_EXT_CONTROL_1               0x03
353 #define PCIC_CIRRUS_EXT_CONTROL_1_PCI_INTR_MASK 0x18
354
355 /* Plug and play */
356 #define PCIC_PNP_ACTIONTEC      0x1802A904      /* AEI0218 */
357 #define PCIC_PNP_IBM3765        0x65374d24      /* IBM3765 */
358 #define PCIC_PNP_82365          0x000ED041      /* PNP0E00 */
359 #define PCIC_PNP_CL_PD6720      0x010ED041      /* PNP0E01 */
360 #define PCIC_PNP_VLSI_82C146    0x020ED041      /* PNP0E02 */
361 #define PCIC_PNP_82365_CARDBUS  0x030ED041      /* PNP0E03 */
362 #define PCIC_PNP_SCM_SWAPBOX    0x69046d4c      /* SMC0469 */
363
364 /* C-Bus PnP Definitions */
365 #define PCIC_NEC_PC9801_102     0x9180a3b8      /* NEC8091 PC-9801-102 */
366 #define PCIC_NEC_PC9821RA_E01   0x2181a3b8      /* NEC8121 PC-9821RA-E01 */