sys/dev/drm/i915/i915_dma.c

   1 /* i915_dma.c -- DMA support for the I915 -*- linux-c -*-
   2  */
   3 /*
   4  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   5  * All Rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the
   9  * "Software"), to deal in the Software without restriction, including
  10  * without limitation the rights to use, copy, modify, merge, publish,
  11  * distribute, sub license, and/or sell copies of the Software, and to
  12  * permit persons to whom the Software is furnished to do so, subject to
  13  * the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the
  16  * next paragraph) shall be included in all copies or substantial portions
  17  * of the Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  20  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  21  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  22  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  23  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  24  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  25  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  26  *
  27  */
  28
  29 #include <linux/async.h>
  30 #include <drm/drmP.h>
  31 #include "intel_drv.h"
  32 #include <drm/i915_drm.h>
  33 #include <drm/drm_legacy.h>
  34 #include "i915_drv.h"
  35 #include "i915_vgpu.h"
  36 #include "intel_ringbuffer.h"
  37 #include <linux/workqueue.h>
  38
  39
  40 static int i915_getparam(struct drm_device *dev, void *data,
  41                          struct drm_file *file_priv)
  42 {
  43         struct drm_i915_private *dev_priv = dev->dev_private;
  44         drm_i915_getparam_t *param = data;
  45         int value;
  46
  47         switch (param->param) {
  48         case I915_PARAM_IRQ_ACTIVE:
  49         case I915_PARAM_ALLOW_BATCHBUFFER:
  50         case I915_PARAM_LAST_DISPATCH:
  51                 /* Reject all old ums/dri params. */
  52                 return -ENODEV;
  53         case I915_PARAM_CHIPSET_ID:
  54                 value = dev->pdev->device;
  55                 break;
  56         case I915_PARAM_REVISION:
  57                 value = dev->pdev->revision;
  58                 break;
  59         case I915_PARAM_HAS_GEM:
  60                 value = 1;
  61                 break;
  62         case I915_PARAM_NUM_FENCES_AVAIL:
  63                 value = dev_priv->num_fence_regs - dev_priv->fence_reg_start;
  64                 break;
  65         case I915_PARAM_HAS_OVERLAY:
  66                 value = dev_priv->overlay ? 1 : 0;
  67                 break;
  68         case I915_PARAM_HAS_PAGEFLIPPING:
  69                 value = 1;
  70                 break;
  71         case I915_PARAM_HAS_EXECBUF2:
  72                 /* depends on GEM */
  73                 value = 1;
  74                 break;
  75         case I915_PARAM_HAS_BSD:
  76                 value = intel_ring_initialized(&dev_priv->ring[VCS]);
  77                 break;
  78         case I915_PARAM_HAS_BLT:
  79                 value = intel_ring_initialized(&dev_priv->ring[BCS]);
  80                 break;
  81         case I915_PARAM_HAS_VEBOX:
  82                 value = intel_ring_initialized(&dev_priv->ring[VECS]);
  83                 break;
  84         case I915_PARAM_HAS_BSD2:
  85                 value = intel_ring_initialized(&dev_priv->ring[VCS2]);
  86                 break;
  87         case I915_PARAM_HAS_RELAXED_FENCING:
  88                 value = 1;
  89                 break;
  90         case I915_PARAM_HAS_COHERENT_RINGS:
  91                 value = 1;
  92                 break;
  93         case I915_PARAM_HAS_EXEC_CONSTANTS:
  94                 value = INTEL_INFO(dev)->gen >= 4;
  95                 break;
  96         case I915_PARAM_HAS_RELAXED_DELTA:
  97                 value = 1;
  98                 break;
  99         case I915_PARAM_HAS_GEN7_SOL_RESET:
 100                 value = 1;
 101                 break;
 102         case I915_PARAM_HAS_LLC:
 103                 value = HAS_LLC(dev);
 104                 break;
 105         case I915_PARAM_HAS_WT:
 106                 value = HAS_WT(dev);
 107                 break;
 108         case I915_PARAM_HAS_ALIASING_PPGTT:
 109                 value = USES_PPGTT(dev);
 110                 break;
 111         case I915_PARAM_HAS_WAIT_TIMEOUT:
 112                 value = 1;
 113                 break;
 114         case I915_PARAM_HAS_SEMAPHORES:
 115                 value = i915_semaphore_is_enabled(dev);
 116                 break;
 117         case I915_PARAM_HAS_PINNED_BATCHES:
 118                 value = 1;
 119                 break;
 120         case I915_PARAM_HAS_EXEC_NO_RELOC:
 121                 value = 1;
 122                 break;
 123         case I915_PARAM_HAS_EXEC_HANDLE_LUT:
 124                 value = 1;
 125                 break;
 126         case I915_PARAM_CMD_PARSER_VERSION:
 127                 value = i915_cmd_parser_get_version();
 128                 break;
 129         case I915_PARAM_HAS_COHERENT_PHYS_GTT:
 130                 value = 1;
 131                 break;
 132         case I915_PARAM_SUBSLICE_TOTAL:
 133                 value = INTEL_INFO(dev)->subslice_total;
 134                 if (!value)
 135                         return -ENODEV;
 136                 break;
 137         case I915_PARAM_EU_TOTAL:
 138                 value = INTEL_INFO(dev)->eu_total;
 139                 if (!value)
 140                         return -ENODEV;
 141                 break;
 142         case I915_PARAM_HAS_GPU_RESET:
 143                 value = i915.enable_hangcheck &&
 144                         intel_has_gpu_reset(dev);
 145                 break;
 146         case I915_PARAM_HAS_RESOURCE_STREAMER:
 147                 value = HAS_RESOURCE_STREAMER(dev);
 148                 break;
 149         default:
 150                 DRM_DEBUG("Unknown parameter %d\n", param->param);
 151                 return -EINVAL;
 152         }
 153
 154         if (copy_to_user(param->value, &value, sizeof(int))) {
 155                 DRM_ERROR("copy_to_user failed\n");
 156                 return -EFAULT;
 157         }
 158
 159         return 0;
 160 }
 161
 162 static int i915_setparam(struct drm_device *dev, void *data,
 163                          struct drm_file *file_priv)
 164 {
 165         struct drm_i915_private *dev_priv = dev->dev_private;
 166         drm_i915_setparam_t *param = data;
 167
 168         switch (param->param) {
 169         case I915_SETPARAM_USE_MI_BATCHBUFFER_START:
 170         case I915_SETPARAM_TEX_LRU_LOG_GRANULARITY:
 171         case I915_SETPARAM_ALLOW_BATCHBUFFER:
 172                 /* Reject all old ums/dri params. */
 173                 return -ENODEV;
 174
 175         case I915_SETPARAM_NUM_USED_FENCES:
 176                 if (param->value > dev_priv->num_fence_regs ||
 177                     param->value < 0)
 178                         return -EINVAL;
 179                 /* Userspace can use first N regs */
 180                 dev_priv->fence_reg_start = param->value;
 181                 break;
 182         default:
 183                 DRM_DEBUG_DRIVER("unknown parameter %d\n",
 184                                         param->param);
 185                 return -EINVAL;
 186         }
 187
 188         return 0;
 189 }
 190
 191 static int i915_get_bridge_dev(struct drm_device *dev)
 192 {
 193         struct drm_i915_private *dev_priv = dev->dev_private;
 194         static struct pci_dev i915_bridge_dev;
 195
 196         i915_bridge_dev.dev = pci_find_dbsf(0, 0, 0, 0);
 197         if (!i915_bridge_dev.dev) {
 198                 DRM_ERROR("bridge device not found\n");
 199                 return -1;
 200         }
 201
 202         dev_priv->bridge_dev = &i915_bridge_dev;
 203         return 0;
 204 }
 205
 206 #define MCHBAR_I915 0x44
 207 #define MCHBAR_I965 0x48
 208 #define MCHBAR_SIZE (4*4096)
 209
 210 #define DEVEN_REG 0x54
 211 #define   DEVEN_MCHBAR_EN (1 << 28)
 212
 213 /* Allocate space for the MCH regs if needed, return nonzero on error */
 214 static int
 215 intel_alloc_mchbar_resource(struct drm_device *dev)
 216 {
 217         struct drm_i915_private *dev_priv = dev->dev_private;
 218         int reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 219         device_t vga;
 220         u32 temp_lo, temp_hi = 0;
 221         u64 mchbar_addr;
 222
 223         if (INTEL_INFO(dev)->gen >= 4)
 224                 pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);
 225         pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo);
 226         mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
 227
 228         /* If ACPI doesn't have it, assume we need to allocate it ourselves */
 229 #ifdef CONFIG_PNP
 230         if (mchbar_addr &&
 231             pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE))
 232                 return 0;
 233 #endif
 234
 235         /* Get some space for it */
 236         vga = device_get_parent(dev->dev);
 237         dev_priv->mch_res_rid = 0x100;
 238         dev_priv->mch_res = BUS_ALLOC_RESOURCE(device_get_parent(vga),
 239             dev->dev, SYS_RES_MEMORY, &dev_priv->mch_res_rid, 0, ~0UL,
 240             MCHBAR_SIZE, RF_ACTIVE | RF_SHAREABLE, -1);
 241         if (dev_priv->mch_res == NULL) {
 242                 DRM_ERROR("failed mchbar resource alloc\n");
 243                 return (-ENOMEM);
 244         }
 245
 246         if (INTEL_INFO(dev)->gen >= 4)
 247                 pci_write_config_dword(dev_priv->bridge_dev, reg + 4,
 248                                        upper_32_bits(rman_get_start(dev_priv->mch_res)));
 249
 250         pci_write_config_dword(dev_priv->bridge_dev, reg,
 251                                lower_32_bits(rman_get_start(dev_priv->mch_res)));
 252         return 0;
 253 }
 254
 255 /* Setup MCHBAR if possible, return true if we should disable it again */
 256 static void
 257 intel_setup_mchbar(struct drm_device *dev)
 258 {
 259         struct drm_i915_private *dev_priv = dev->dev_private;
 260         int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 261         u32 temp;
 262         bool enabled;
 263
 264         if (IS_VALLEYVIEW(dev))
 265                 return;
 266
 267         dev_priv->mchbar_need_disable = false;
 268
 269         if (IS_I915G(dev) || IS_I915GM(dev)) {
 270                 pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp);
 271                 enabled = !!(temp & DEVEN_MCHBAR_EN);
 272         } else {
 273                 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
 274                 enabled = temp & 1;
 275         }
 276
 277         /* If it's already enabled, don't have to do anything */
 278         if (enabled)
 279                 return;
 280
 281         if (intel_alloc_mchbar_resource(dev))
 282                 return;
 283
 284         dev_priv->mchbar_need_disable = true;
 285
 286         /* Space is allocated or reserved, so enable it. */
 287         if (IS_I915G(dev) || IS_I915GM(dev)) {
 288                 pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG,
 289                                        temp | DEVEN_MCHBAR_EN);
 290         } else {
 291                 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
 292                 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1);
 293         }
 294 }
 295
 296 static void
 297 intel_teardown_mchbar(struct drm_device *dev)
 298 {
 299         struct drm_i915_private *dev_priv = dev->dev_private;
 300         int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 301         device_t vga;
 302         u32 temp;
 303
 304         if (dev_priv->mchbar_need_disable) {
 305                 if (IS_I915G(dev) || IS_I915GM(dev)) {
 306                         pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp);
 307                         temp &= ~DEVEN_MCHBAR_EN;
 308                         pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG, temp);
 309                 } else {
 310                         pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
 311                         temp &= ~1;
 312                         pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp);
 313                 }
 314         }
 315
 316         if (dev_priv->mch_res != NULL) {
 317                 vga = device_get_parent(dev->dev);
 318                 BUS_DEACTIVATE_RESOURCE(device_get_parent(vga), dev->dev,
 319                     SYS_RES_MEMORY, dev_priv->mch_res_rid, dev_priv->mch_res);
 320                 BUS_RELEASE_RESOURCE(device_get_parent(vga), dev->dev,
 321                     SYS_RES_MEMORY, dev_priv->mch_res_rid, dev_priv->mch_res);
 322                 dev_priv->mch_res = NULL;
 323         }
 324 }
 325
 326 #if 0
 327 /* true = enable decode, false = disable decoder */
 328 static unsigned int i915_vga_set_decode(void *cookie, bool state)
 329 {
 330         struct drm_device *dev = cookie;
 331
 332         intel_modeset_vga_set_state(dev, state);
 333         if (state)
 334                 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
 335                        VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 336         else
 337                 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 338 }
 339
 340 static void i915_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
 341 {
 342         struct drm_device *dev = pci_get_drvdata(pdev);
 343         pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
 344
 345         if (state == VGA_SWITCHEROO_ON) {
 346                 pr_info("switched on\n");
 347                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
 348                 /* i915 resume handler doesn't set to D0 */
 349                 pci_set_power_state(dev->pdev, PCI_D0);
 350                 i915_resume_legacy(dev);
 351                 dev->switch_power_state = DRM_SWITCH_POWER_ON;
 352         } else {
 353                 pr_err("switched off\n");
 354                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
 355                 i915_suspend_legacy(dev, pmm);
 356                 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
 357         }
 358 }
 359
 360 static bool i915_switcheroo_can_switch(struct pci_dev *pdev)
 361 {
 362         struct drm_device *dev = pci_get_drvdata(pdev);
 363
 364         /*
 365          * FIXME: open_count is protected by drm_global_mutex but that would lead to
 366          * locking inversion with the driver load path. And the access here is
 367          * completely racy anyway. So don't bother with locking for now.
 368          */
 369         return dev->open_count == 0;
 370 }
 371
 372 static const struct vga_switcheroo_client_ops i915_switcheroo_ops = {
 373         .set_gpu_state = i915_switcheroo_set_state,
 374         .reprobe = NULL,
 375         .can_switch = i915_switcheroo_can_switch,
 376 };
 377 #endif
 378
 379 static int i915_load_modeset_init(struct drm_device *dev)
 380 {
 381         struct drm_i915_private *dev_priv = dev->dev_private;
 382         int ret;
 383
 384         ret = intel_parse_bios(dev);
 385         if (ret)
 386                 DRM_INFO("failed to find VBIOS tables\n");
 387
 388 #if 0
 389         /* If we have > 1 VGA cards, then we need to arbitrate access
 390          * to the common VGA resources.
 391          *
 392          * If we are a secondary display controller (!PCI_DISPLAY_CLASS_VGA),
 393          * then we do not take part in VGA arbitration and the
 394          * vga_client_register() fails with -ENODEV.
 395          */
 396         ret = vga_client_register(dev->pdev, dev, NULL, i915_vga_set_decode);
 397         if (ret && ret != -ENODEV)
 398                 goto out;
 399
 400         intel_register_dsm_handler();
 401
 402         ret = vga_switcheroo_register_client(dev->pdev, &i915_switcheroo_ops, false);
 403         if (ret)
 404                 goto cleanup_vga_client;
 405
 406         /* Initialise stolen first so that we may reserve preallocated
 407          * objects for the BIOS to KMS transition.
 408          */
 409         ret = i915_gem_init_stolen(dev);
 410         if (ret)
 411                 goto cleanup_vga_switcheroo;
 412 #endif
 413
 414         intel_power_domains_init_hw(dev_priv);
 415
 416         ret = intel_irq_install(dev_priv);
 417         if (ret)
 418                 goto cleanup_gem_stolen;
 419
 420         /* Important: The output setup functions called by modeset_init need
 421          * working irqs for e.g. gmbus and dp aux transfers. */
 422         intel_modeset_init(dev);
 423
 424         ret = i915_gem_init(dev);
 425         if (ret)
 426                 goto cleanup_irq;
 427
 428         intel_modeset_gem_init(dev);
 429
 430         /* Always safe in the mode setting case. */
 431         /* FIXME: do pre/post-mode set stuff in core KMS code */
 432         dev->vblank_disable_allowed = 1;
 433         if (INTEL_INFO(dev)->num_pipes == 0)
 434                 return 0;
 435
 436         ret = intel_fbdev_init(dev);
 437         if (ret)
 438                 goto cleanup_gem;
 439
 440         /* Only enable hotplug handling once the fbdev is fully set up. */
 441         intel_hpd_init(dev_priv);
 442
 443         /*
 444          * Some ports require correctly set-up hpd registers for detection to
 445          * work properly (leading to ghost connected connector status), e.g. VGA
 446          * on gm45.  Hence we can only set up the initial fbdev config after hpd
 447          * irqs are fully enabled. Now we should scan for the initial config
 448          * only once hotplug handling is enabled, but due to screwed-up locking
 449          * around kms/fbdev init we can't protect the fdbev initial config
 450          * scanning against hotplug events. Hence do this first and ignore the
 451          * tiny window where we will loose hotplug notifactions.
 452          */
 453         async_schedule(intel_fbdev_initial_config, dev_priv);
 454
 455         drm_kms_helper_poll_init(dev);
 456
 457         return 0;
 458
 459 cleanup_gem:
 460         mutex_lock(&dev->struct_mutex);
 461         i915_gem_cleanup_ringbuffer(dev);
 462         i915_gem_context_fini(dev);
 463         mutex_unlock(&dev->struct_mutex);
 464 cleanup_irq:
 465         drm_irq_uninstall(dev);
 466 cleanup_gem_stolen:
 467         i915_gem_cleanup_stolen(dev);
 468 #if 0
 469 cleanup_vga_switcheroo:
 470         vga_switcheroo_unregister_client(dev->pdev);
 471 cleanup_vga_client:
 472         vga_client_register(dev->pdev, NULL, NULL, NULL);
 473 out:
 474 #endif
 475         return ret;
 476 }
 477
 478 #if IS_ENABLED(CONFIG_FB)
 479 static int i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv)
 480 {
 481         struct apertures_struct *ap;
 482         struct pci_dev *pdev = dev_priv->dev->pdev;
 483         bool primary;
 484         int ret;
 485
 486         ap = alloc_apertures(1);
 487         if (!ap)
 488                 return -ENOMEM;
 489
 490         ap->ranges[0].base = dev_priv->gtt.mappable_base;
 491         ap->ranges[0].size = dev_priv->gtt.mappable_end;
 492
 493         primary =
 494                 pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
 495
 496         ret = remove_conflicting_framebuffers(ap, "inteldrmfb", primary);
 497
 498         kfree(ap);
 499
 500         return ret;
 501 }
 502 #else
 503 static int i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv)
 504 {
 505         return 0;
 506 }
 507 #endif
 508
 509 #if !defined(CONFIG_VGA_CONSOLE)
 510 static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
 511 {
 512         return 0;
 513 }
 514 #elif !defined(CONFIG_DUMMY_CONSOLE)
 515 static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
 516 {
 517         return -ENODEV;
 518 }
 519 #else
 520 static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
 521 {
 522         int ret = 0;
 523
 524         DRM_INFO("Replacing VGA console driver\n");
 525
 526         console_lock();
 527         if (con_is_bound(&vga_con))
 528                 ret = do_take_over_console(&dummy_con, 0, MAX_NR_CONSOLES - 1, 1);
 529         if (ret == 0) {
 530                 ret = do_unregister_con_driver(&vga_con);
 531
 532                 /* Ignore "already unregistered". */
 533                 if (ret == -ENODEV)
 534                         ret = 0;
 535         }
 536         console_unlock();
 537
 538         return ret;
 539 }
 540 #endif
 541
 542 static void i915_dump_device_info(struct drm_i915_private *dev_priv)
 543 {
 544 #if 0
 545         const struct intel_device_info *info = &dev_priv->info;
 546
 547 #define PRINT_S(name) "%s"
 548 #define SEP_EMPTY
 549 #define PRINT_FLAG(name) info->name ? #name "," : ""
 550 #define SEP_COMMA ,
 551         DRM_DEBUG_DRIVER("i915 device info: gen=%i, pciid=0x%04x rev=0x%02x flags="
 552                          DEV_INFO_FOR_EACH_FLAG(PRINT_S, SEP_EMPTY),
 553                          info->gen,
 554                          dev_priv->dev->pdev->device,
 555                          dev_priv->dev->pdev->revision,
 556                          DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_COMMA));
 557 #undef PRINT_S
 558 #undef SEP_EMPTY
 559 #undef PRINT_FLAG
 560 #undef SEP_COMMA
 561 #endif
 562 }
 563
 564 static void cherryview_sseu_info_init(struct drm_device *dev)
 565 {
 566         struct drm_i915_private *dev_priv = dev->dev_private;
 567         struct intel_device_info *info;
 568         u32 fuse, eu_dis;
 569
 570         info = (struct intel_device_info *)&dev_priv->info;
 571         fuse = I915_READ(CHV_FUSE_GT);
 572
 573         info->slice_total = 1;
 574
 575         if (!(fuse & CHV_FGT_DISABLE_SS0)) {
 576                 info->subslice_per_slice++;
 577                 eu_dis = fuse & (CHV_FGT_EU_DIS_SS0_R0_MASK |
 578                                  CHV_FGT_EU_DIS_SS0_R1_MASK);
 579                 info->eu_total += 8 - hweight32(eu_dis);
 580         }
 581
 582         if (!(fuse & CHV_FGT_DISABLE_SS1)) {
 583                 info->subslice_per_slice++;
 584                 eu_dis = fuse & (CHV_FGT_EU_DIS_SS1_R0_MASK |
 585                                  CHV_FGT_EU_DIS_SS1_R1_MASK);
 586                 info->eu_total += 8 - hweight32(eu_dis);
 587         }
 588
 589         info->subslice_total = info->subslice_per_slice;
 590         /*
 591          * CHV expected to always have a uniform distribution of EU
 592          * across subslices.
 593         */
 594         info->eu_per_subslice = info->subslice_total ?
 595                                 info->eu_total / info->subslice_total :
 596                                 0;
 597         /*
 598          * CHV supports subslice power gating on devices with more than
 599          * one subslice, and supports EU power gating on devices with
 600          * more than one EU pair per subslice.
 601         */
 602         info->has_slice_pg = 0;
 603         info->has_subslice_pg = (info->subslice_total > 1);
 604         info->has_eu_pg = (info->eu_per_subslice > 2);
 605 }
 606
 607 static void gen9_sseu_info_init(struct drm_device *dev)
 608 {
 609         struct drm_i915_private *dev_priv = dev->dev_private;
 610         struct intel_device_info *info;
 611         int s_max = 3, ss_max = 4, eu_max = 8;
 612         int s, ss;
 613         u32 fuse2, s_enable, ss_disable, eu_disable;
 614         u8 eu_mask = 0xff;
 615
 616         /*
 617          * BXT has a single slice. BXT also has at most 6 EU per subslice,
 618          * and therefore only the lowest 6 bits of the 8-bit EU disable
 619          * fields are valid.
 620         */
 621         if (IS_BROXTON(dev)) {
 622                 s_max = 1;
 623                 eu_max = 6;
 624                 eu_mask = 0x3f;
 625         }
 626
 627         info = (struct intel_device_info *)&dev_priv->info;
 628         fuse2 = I915_READ(GEN8_FUSE2);
 629         s_enable = (fuse2 & GEN8_F2_S_ENA_MASK) >>
 630                    GEN8_F2_S_ENA_SHIFT;
 631         ss_disable = (fuse2 & GEN9_F2_SS_DIS_MASK) >>
 632                      GEN9_F2_SS_DIS_SHIFT;
 633
 634         info->slice_total = hweight32(s_enable);
 635         /*
 636          * The subslice disable field is global, i.e. it applies
 637          * to each of the enabled slices.
 638         */
 639         info->subslice_per_slice = ss_max - hweight32(ss_disable);
 640         info->subslice_total = info->slice_total *
 641                                info->subslice_per_slice;
 642
 643         /*
 644          * Iterate through enabled slices and subslices to
 645          * count the total enabled EU.
 646         */
 647         for (s = 0; s < s_max; s++) {
 648                 if (!(s_enable & (0x1 << s)))
 649                         /* skip disabled slice */
 650                         continue;
 651
 652                 eu_disable = I915_READ(GEN9_EU_DISABLE(s));
 653                 for (ss = 0; ss < ss_max; ss++) {
 654                         int eu_per_ss;
 655
 656                         if (ss_disable & (0x1 << ss))
 657                                 /* skip disabled subslice */
 658                                 continue;
 659
 660                         eu_per_ss = eu_max - hweight8((eu_disable >> (ss*8)) &
 661                                                       eu_mask);
 662
 663                         /*
 664                          * Record which subslice(s) has(have) 7 EUs. we
 665                          * can tune the hash used to spread work among
 666                          * subslices if they are unbalanced.
 667                          */
 668                         if (eu_per_ss == 7)
 669                                 info->subslice_7eu[s] |= 1 << ss;
 670
 671                         info->eu_total += eu_per_ss;
 672                 }
 673         }
 674
 675         /*
 676          * SKL is expected to always have a uniform distribution
 677          * of EU across subslices with the exception that any one
 678          * EU in any one subslice may be fused off for die
 679          * recovery. BXT is expected to be perfectly uniform in EU
 680          * distribution.
 681         */
 682         info->eu_per_subslice = info->subslice_total ?
 683                                 DIV_ROUND_UP(info->eu_total,
 684                                              info->subslice_total) : 0;
 685         /*
 686          * SKL supports slice power gating on devices with more than
 687          * one slice, and supports EU power gating on devices with
 688          * more than one EU pair per subslice. BXT supports subslice
 689          * power gating on devices with more than one subslice, and
 690          * supports EU power gating on devices with more than one EU
 691          * pair per subslice.
 692         */
 693         info->has_slice_pg = (IS_SKYLAKE(dev) && (info->slice_total > 1));
 694         info->has_subslice_pg = (IS_BROXTON(dev) && (info->subslice_total > 1));
 695         info->has_eu_pg = (info->eu_per_subslice > 2);
 696 }
 697
 698 /*
 699  * Determine various intel_device_info fields at runtime.
 700  *
 701  * Use it when either:
 702  *   - it's judged too laborious to fill n static structures with the limit
 703  *     when a simple if statement does the job,
 704  *   - run-time checks (eg read fuse/strap registers) are needed.
 705  *
 706  * This function needs to be called:
 707  *   - after the MMIO has been setup as we are reading registers,
 708  *   - after the PCH has been detected,
 709  *   - before the first usage of the fields it can tweak.
 710  */
 711 static void intel_device_info_runtime_init(struct drm_device *dev)
 712 {
 713         struct drm_i915_private *dev_priv = dev->dev_private;
 714         struct intel_device_info *info;
 715         enum i915_pipe pipe;
 716
 717         info = (struct intel_device_info *)&dev_priv->info;
 718
 719         /*
 720          * Skylake and Broxton currently don't expose the topmost plane as its
 721          * use is exclusive with the legacy cursor and we only want to expose
 722          * one of those, not both. Until we can safely expose the topmost plane
 723          * as a DRM_PLANE_TYPE_CURSOR with all the features exposed/supported,
 724          * we don't expose the topmost plane at all to prevent ABI breakage
 725          * down the line.
 726          */
 727         if (IS_BROXTON(dev)) {
 728                 info->num_sprites[PIPE_A] = 2;
 729                 info->num_sprites[PIPE_B] = 2;
 730                 info->num_sprites[PIPE_C] = 1;
 731         } else if (IS_VALLEYVIEW(dev))
 732                 for_each_pipe(dev_priv, pipe)
 733                         info->num_sprites[pipe] = 2;
 734         else
 735                 for_each_pipe(dev_priv, pipe)
 736                         info->num_sprites[pipe] = 1;
 737
 738         if (i915.disable_display) {
 739                 DRM_INFO("Display disabled (module parameter)\n");
 740                 info->num_pipes = 0;
 741         } else if (info->num_pipes > 0 &&
 742                    (INTEL_INFO(dev)->gen == 7 || INTEL_INFO(dev)->gen == 8) &&
 743                    !IS_VALLEYVIEW(dev)) {
 744                 u32 fuse_strap = I915_READ(FUSE_STRAP);
 745                 u32 sfuse_strap = I915_READ(SFUSE_STRAP);
 746
 747                 /*
 748                  * SFUSE_STRAP is supposed to have a bit signalling the display
 749                  * is fused off. Unfortunately it seems that, at least in
 750                  * certain cases, fused off display means that PCH display
 751                  * reads don't land anywhere. In that case, we read 0s.
 752                  *
 753                  * On CPT/PPT, we can detect this case as SFUSE_STRAP_FUSE_LOCK
 754                  * should be set when taking over after the firmware.
 755                  */
 756                 if (fuse_strap & ILK_INTERNAL_DISPLAY_DISABLE ||
 757                     sfuse_strap & SFUSE_STRAP_DISPLAY_DISABLED ||
 758                     (dev_priv->pch_type == PCH_CPT &&
 759                      !(sfuse_strap & SFUSE_STRAP_FUSE_LOCK))) {
 760                         DRM_INFO("Display fused off, disabling\n");
 761                         info->num_pipes = 0;
 762                 }
 763         }
 764
 765         /* Initialize slice/subslice/EU info */
 766         if (IS_CHERRYVIEW(dev))
 767                 cherryview_sseu_info_init(dev);
 768         else if (INTEL_INFO(dev)->gen >= 9)
 769                 gen9_sseu_info_init(dev);
 770
 771         DRM_DEBUG_DRIVER("slice total: %u\n", info->slice_total);
 772         DRM_DEBUG_DRIVER("subslice total: %u\n", info->subslice_total);
 773         DRM_DEBUG_DRIVER("subslice per slice: %u\n", info->subslice_per_slice);
 774         DRM_DEBUG_DRIVER("EU total: %u\n", info->eu_total);
 775         DRM_DEBUG_DRIVER("EU per subslice: %u\n", info->eu_per_subslice);
 776         DRM_DEBUG_DRIVER("has slice power gating: %s\n",
 777                          info->has_slice_pg ? "y" : "n");
 778         DRM_DEBUG_DRIVER("has subslice power gating: %s\n",
 779                          info->has_subslice_pg ? "y" : "n");
 780         DRM_DEBUG_DRIVER("has EU power gating: %s\n",
 781                          info->has_eu_pg ? "y" : "n");
 782 }
 783
 784 /**
 785  * i915_driver_load - setup chip and create an initial config
 786  * @dev: DRM device
 787  * @flags: startup flags
 788  *
 789  * The driver load routine has to do several things:
 790  *   - drive output discovery via intel_modeset_init()
 791  *   - initialize the memory manager
 792  *   - allocate initial config memory
 793  *   - setup the DRM framebuffer with the allocated memory
 794  */
 795 int i915_driver_load(struct drm_device *dev, unsigned long flags)
 796 {
 797         struct drm_i915_private *dev_priv = dev->dev_private;
 798         struct intel_device_info *info, *device_info;
 799         unsigned long base, size;
 800         int ret = 0, mmio_bar, mmio_size;
 801         uint32_t aperture_size;
 802
 803         /* XXX: struct pci_dev */
 804         info = i915_get_device_id(dev->pdev->device);
 805
 806         dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL);
 807         if (dev_priv == NULL)
 808                 return -ENOMEM;
 809
 810         dev->dev_private = dev_priv;
 811         dev_priv->dev = dev;
 812
 813         /* Setup the write-once "constant" device info */
 814         device_info = (struct intel_device_info *)&dev_priv->info;
 815         memcpy(device_info, info, sizeof(dev_priv->info));
 816         device_info->device_id = dev->pdev->device;
 817
 818         lockinit(&dev_priv->irq_lock, "userirq", 0, LK_CANRECURSE);
 819         lockinit(&dev_priv->gpu_error.lock, "915err", 0, LK_CANRECURSE);
 820         lockinit(&dev_priv->backlight_lock, "i915bl", 0, LK_CANRECURSE);
 821         lockinit(&dev_priv->uncore.lock, "915gt", 0, LK_CANRECURSE);
 822         spin_init(&dev_priv->mm.object_stat_lock, "i915osl");
 823         spin_init(&dev_priv->mmio_flip_lock, "i915mfl");
 824         lockinit(&dev_priv->sb_lock, "i915sbl", 0, LK_CANRECURSE);
 825         lockinit(&dev_priv->modeset_restore_lock, "i915mrl", 0, LK_CANRECURSE);
 826         lockinit(&dev_priv->csr_lock, "i915csr", 0, LK_CANRECURSE);
 827
 828         intel_pm_setup(dev);
 829
 830         intel_display_crc_init(dev);
 831
 832         i915_dump_device_info(dev_priv);
 833
 834         /* Not all pre-production machines fall into this category, only the
 835          * very first ones. Almost everything should work, except for maybe
 836          * suspend/resume. And we don't implement workarounds that affect only
 837          * pre-production machines. */
 838         if (IS_HSW_EARLY_SDV(dev))
 839                 DRM_INFO("This is an early pre-production Haswell machine. "
 840                          "It may not be fully functional.\n");
 841
 842         if (i915_get_bridge_dev(dev)) {
 843                 ret = -EIO;
 844                 goto free_priv;
 845         }
 846
 847         mmio_bar = IS_GEN2(dev) ? 1 : 0;
 848         /* Before gen4, the registers and the GTT are behind different BARs.
 849          * However, from gen4 onwards, the registers and the GTT are shared
 850          * in the same BAR, so we want to restrict this ioremap from
 851          * clobbering the GTT which we want ioremap_wc instead. Fortunately,
 852          * the register BAR remains the same size for all the earlier
 853          * generations up to Ironlake.
 854          */
 855         if (info->gen < 5)
 856                 mmio_size = 512*1024;
 857         else
 858                 mmio_size = 2*1024*1024;
 859
 860         dev_priv->regs = pci_iomap(dev->pdev, mmio_bar, mmio_size);
 861         if (!dev_priv->regs) {
 862                 DRM_ERROR("failed to map registers\n");
 863                 ret = -EIO;
 864                 goto put_bridge;
 865         }
 866 #ifdef __DragonFly__
 867         base = drm_get_resource_start(dev, mmio_bar);
 868         size = drm_get_resource_len(dev, mmio_bar);
 869
 870         ret = drm_legacy_addmap(dev, base, size, _DRM_REGISTERS,
 871             _DRM_KERNEL | _DRM_DRIVER, &dev_priv->mmio_map);
 872 #endif
 873
 874         /* This must be called before any calls to HAS_PCH_* */
 875         intel_detect_pch(dev);
 876
 877         intel_uncore_init(dev);
 878
 879         /* Load CSR Firmware for SKL */
 880         intel_csr_ucode_init(dev);
 881
 882         ret = i915_gem_gtt_init(dev);
 883         if (ret)
 884                 goto out_freecsr;
 885
 886         /* WARNING: Apparently we must kick fbdev drivers before vgacon,
 887          * otherwise the vga fbdev driver falls over. */
 888         ret = i915_kick_out_firmware_fb(dev_priv);
 889         if (ret) {
 890                 DRM_ERROR("failed to remove conflicting framebuffer drivers\n");
 891                 goto out_gtt;
 892         }
 893
 894         ret = i915_kick_out_vgacon(dev_priv);
 895         if (ret) {
 896                 DRM_ERROR("failed to remove conflicting VGA console\n");
 897                 goto out_gtt;
 898         }
 899
 900 #if 0
 901         pci_set_master(dev->pdev);
 902
 903         /* overlay on gen2 is broken and can't address above 1G */
 904         if (IS_GEN2(dev))
 905                 dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(30));
 906
 907         /* 965GM sometimes incorrectly writes to hardware status page (HWS)
 908          * using 32bit addressing, overwriting memory if HWS is located
 909          * above 4GB.
 910          *
 911          * The documentation also mentions an issue with undefined
 912          * behaviour if any general state is accessed within a page above 4GB,
 913          * which also needs to be handled carefully.
 914          */
 915         if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
 916                 dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(32));
 917 #endif
 918
 919         aperture_size = dev_priv->gtt.mappable_end;
 920
 921         dev_priv->gtt.mappable =
 922                 io_mapping_create_wc(dev_priv->gtt.mappable_base,
 923                                      aperture_size);
 924         if (dev_priv->gtt.mappable == NULL) {
 925                 ret = -EIO;
 926                 goto out_gtt;
 927         }
 928
 929         dev_priv->gtt.mtrr = arch_phys_wc_add(dev_priv->gtt.mappable_base,
 930                                               aperture_size);
 931
 932         /* The i915 workqueue is primarily used for batched retirement of
 933          * requests (and thus managing bo) once the task has been completed
 934          * by the GPU. i915_gem_retire_requests() is called directly when we
 935          * need high-priority retirement, such as waiting for an explicit
 936          * bo.
 937          *
 938          * It is also used for periodic low-priority events, such as
 939          * idle-timers and recording error state.
 940          *
 941          * All tasks on the workqueue are expected to acquire the dev mutex
 942          * so there is no point in running more than one instance of the
 943          * workqueue at any time.  Use an ordered one.
 944          */
 945         dev_priv->wq = alloc_ordered_workqueue("i915", 0);
 946         if (dev_priv->wq == NULL) {
 947                 DRM_ERROR("Failed to create our workqueue.\n");
 948                 ret = -ENOMEM;
 949                 goto out_mtrrfree;
 950         }
 951
 952         dev_priv->hotplug.dp_wq = alloc_ordered_workqueue("i915-dp", 0);
 953         if (dev_priv->hotplug.dp_wq == NULL) {
 954                 DRM_ERROR("Failed to create our dp workqueue.\n");
 955                 ret = -ENOMEM;
 956                 goto out_freewq;
 957         }
 958
 959         dev_priv->gpu_error.hangcheck_wq =
 960                 alloc_ordered_workqueue("i915-hangcheck", 0);
 961         if (dev_priv->gpu_error.hangcheck_wq == NULL) {
 962                 DRM_ERROR("Failed to create our hangcheck workqueue.\n");
 963                 ret = -ENOMEM;
 964                 goto out_freedpwq;
 965         }
 966
 967         intel_irq_init(dev_priv);
 968         intel_uncore_sanitize(dev);
 969
 970         /* Try to make sure MCHBAR is enabled before poking at it */
 971         intel_setup_mchbar(dev);
 972         intel_setup_gmbus(dev);
 973         intel_opregion_setup(dev);
 974
 975         intel_setup_bios(dev);
 976
 977         i915_gem_load(dev);
 978
 979         /* On the 945G/GM, the chipset reports the MSI capability on the
 980          * integrated graphics even though the support isn't actually there
 981          * according to the published specs.  It doesn't appear to function
 982          * correctly in testing on 945G.
 983          * This may be a side effect of MSI having been made available for PEG
 984          * and the registers being closely associated.
 985          *
 986          * According to chipset errata, on the 965GM, MSI interrupts may
 987          * be lost or delayed, but we use them anyways to avoid
 988          * stuck interrupts on some machines.
 989          */
 990 #if 0
 991         if (!IS_I945G(dev) && !IS_I945GM(dev))
 992                 pci_enable_msi(dev->pdev);
 993 #endif
 994
 995         intel_device_info_runtime_init(dev);
 996
 997         if (INTEL_INFO(dev)->num_pipes) {
 998                 ret = drm_vblank_init(dev, INTEL_INFO(dev)->num_pipes);
 999                 if (ret)
1000                         goto out_gem_unload;
1001         }
1002
1003         intel_power_domains_init(dev_priv);
1004
1005         ret = i915_load_modeset_init(dev);
1006         if (ret < 0) {
1007                 DRM_ERROR("failed to init modeset\n");
1008                 goto out_power_well;
1009         }
1010
1011         /*
1012          * Notify a valid surface after modesetting,
1013          * when running inside a VM.
1014          */
1015         if (intel_vgpu_active(dev))
1016                 I915_WRITE(vgtif_reg(display_ready), VGT_DRV_DISPLAY_READY);
1017
1018         i915_setup_sysfs(dev);
1019
1020         if (INTEL_INFO(dev)->num_pipes) {
1021                 /* Must be done after probing outputs */
1022                 intel_opregion_init(dev);
1023 #if 0
1024                 acpi_video_register();
1025 #endif
1026         }
1027
1028         if (IS_GEN5(dev))
1029                 intel_gpu_ips_init(dev_priv);
1030
1031         intel_runtime_pm_enable(dev_priv);
1032
1033         i915_audio_component_init(dev_priv);
1034
1035         return 0;
1036
1037 out_power_well:
1038         intel_power_domains_fini(dev_priv);
1039         drm_vblank_cleanup(dev);
1040 out_gem_unload:
1041
1042         intel_teardown_gmbus(dev);
1043         intel_teardown_mchbar(dev);
1044         pm_qos_remove_request(&dev_priv->pm_qos);
1045         destroy_workqueue(dev_priv->gpu_error.hangcheck_wq);
1046 out_freedpwq:
1047         destroy_workqueue(dev_priv->hotplug.dp_wq);
1048 out_freewq:
1049         destroy_workqueue(dev_priv->wq);
1050 out_mtrrfree:
1051         arch_phys_wc_del(dev_priv->gtt.mtrr);
1052 #if 0
1053         io_mapping_free(dev_priv->gtt.mappable);
1054 #endif
1055 out_gtt:
1056         i915_global_gtt_cleanup(dev);
1057 out_freecsr:
1058         intel_csr_ucode_fini(dev);
1059         intel_uncore_fini(dev);
1060 #if 0
1061         pci_iounmap(dev->pdev, dev_priv->regs);
1062 #endif
1063 put_bridge:
1064         pci_dev_put(dev_priv->bridge_dev);
1065 free_priv:
1066         kfree(dev_priv);
1067         return ret;
1068 }
1069
1070 int i915_driver_unload(struct drm_device *dev)
1071 {
1072         struct drm_i915_private *dev_priv = dev->dev_private;
1073         int ret;
1074
1075         i915_audio_component_cleanup(dev_priv);
1076
1077         ret = i915_gem_suspend(dev);
1078         if (ret) {
1079                 DRM_ERROR("failed to idle hardware: %d\n", ret);
1080                 return ret;
1081         }
1082
1083         intel_power_domains_fini(dev_priv);
1084
1085         intel_gpu_ips_teardown();
1086
1087         i915_teardown_sysfs(dev);
1088
1089 #if 0
1090         WARN_ON(unregister_oom_notifier(&dev_priv->mm.oom_notifier));
1091         unregister_shrinker(&dev_priv->mm.shrinker);
1092
1093         io_mapping_free(dev_priv->gtt.mappable);
1094 #endif
1095         arch_phys_wc_del(dev_priv->gtt.mtrr);
1096
1097 #if 0
1098         acpi_video_unregister();
1099 #endif
1100
1101         intel_fbdev_fini(dev);
1102
1103         drm_vblank_cleanup(dev);
1104
1105         intel_modeset_cleanup(dev);
1106
1107         /*
1108          * free the memory space allocated for the child device
1109          * config parsed from VBT
1110          */
1111         if (dev_priv->vbt.child_dev && dev_priv->vbt.child_dev_num) {
1112                 kfree(dev_priv->vbt.child_dev);
1113                 dev_priv->vbt.child_dev = NULL;
1114                 dev_priv->vbt.child_dev_num = 0;
1115         }
1116
1117 #if 0
1118         vga_switcheroo_unregister_client(dev->pdev);
1119         vga_client_register(dev->pdev, NULL, NULL, NULL);
1120 #endif
1121
1122         /* Free error state after interrupts are fully disabled. */
1123         cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work);
1124 #if 0
1125         i915_destroy_error_state(dev);
1126
1127         if (dev->pdev->msi_enabled)
1128                 pci_disable_msi(dev->pdev);
1129 #endif
1130
1131         intel_opregion_fini(dev);
1132
1133         /* Flush any outstanding unpin_work. */
1134         flush_workqueue(dev_priv->wq);
1135
1136         mutex_lock(&dev->struct_mutex);
1137         i915_gem_cleanup_ringbuffer(dev);
1138         i915_gem_context_fini(dev);
1139         mutex_unlock(&dev->struct_mutex);
1140         intel_fbc_cleanup_cfb(dev_priv);
1141         i915_gem_cleanup_stolen(dev);
1142
1143         intel_csr_ucode_fini(dev);
1144
1145         intel_teardown_gmbus(dev);
1146         intel_teardown_mchbar(dev);
1147
1148         destroy_workqueue(dev_priv->hotplug.dp_wq);
1149         destroy_workqueue(dev_priv->wq);
1150         destroy_workqueue(dev_priv->gpu_error.hangcheck_wq);
1151         pm_qos_remove_request(&dev_priv->pm_qos);
1152
1153         i915_global_gtt_cleanup(dev);
1154
1155         intel_uncore_fini(dev);
1156 #if 0
1157         if (dev_priv->regs != NULL)
1158                 pci_iounmap(dev->pdev, dev_priv->regs);
1159
1160         if (dev_priv->slab)
1161                 kmem_cache_destroy(dev_priv->slab);
1162 #endif
1163
1164         pci_dev_put(dev_priv->bridge_dev);
1165         kfree(dev_priv);
1166
1167         return 0;
1168 }
1169
1170 int i915_driver_open(struct drm_device *dev, struct drm_file *file)
1171 {
1172         int ret;
1173
1174         ret = i915_gem_open(dev, file);
1175         if (ret)
1176                 return ret;
1177
1178         return 0;
1179 }
1180
1181 /**
1182  * i915_driver_lastclose - clean up after all DRM clients have exited
1183  * @dev: DRM device
1184  *
1185  * Take care of cleaning up after all DRM clients have exited.  In the
1186  * mode setting case, we want to restore the kernel's initial mode (just
1187  * in case the last client left us in a bad state).
1188  *
1189  * Additionally, in the non-mode setting case, we'll tear down the GTT
1190  * and DMA structures, since the kernel won't be using them, and clea
1191  * up any GEM state.
1192  */
1193 void i915_driver_lastclose(struct drm_device *dev)
1194 {
1195         intel_fbdev_restore_mode(dev);
1196 #if 0
1197         vga_switcheroo_process_delayed_switch();
1198 #endif
1199 }
1200
1201 void i915_driver_preclose(struct drm_device *dev, struct drm_file *file)
1202 {
1203         mutex_lock(&dev->struct_mutex);
1204         i915_gem_context_close(dev, file);
1205         i915_gem_release(dev, file);
1206         mutex_unlock(&dev->struct_mutex);
1207
1208         intel_modeset_preclose(dev, file);
1209 }
1210
1211 void i915_driver_postclose(struct drm_device *dev, struct drm_file *file)
1212 {
1213         struct drm_i915_file_private *file_priv = file->driver_priv;
1214
1215         if (file_priv && file_priv->bsd_ring)
1216                 file_priv->bsd_ring = NULL;
1217         kfree(file_priv);
1218 }
1219
1220 static int
1221 i915_gem_reject_pin_ioctl(struct drm_device *dev, void *data,
1222                           struct drm_file *file)
1223 {
1224         return -ENODEV;
1225 }
1226
1227 const struct drm_ioctl_desc i915_ioctls[] = {
1228         DRM_IOCTL_DEF_DRV(I915_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1229         DRM_IOCTL_DEF_DRV(I915_FLUSH, drm_noop, DRM_AUTH),
1230         DRM_IOCTL_DEF_DRV(I915_FLIP, drm_noop, DRM_AUTH),
1231         DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, drm_noop, DRM_AUTH),
1232         DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, drm_noop, DRM_AUTH),
1233         DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, drm_noop, DRM_AUTH),
1234         DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam, DRM_AUTH|DRM_RENDER_ALLOW),
1235         DRM_IOCTL_DEF_DRV(I915_SETPARAM, i915_setparam, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1236         DRM_IOCTL_DEF_DRV(I915_ALLOC, drm_noop, DRM_AUTH),
1237         DRM_IOCTL_DEF_DRV(I915_FREE, drm_noop, DRM_AUTH),
1238         DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1239         DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, drm_noop, DRM_AUTH),
1240         DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP,  drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1241         DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE,  drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1242         DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE,  drm_noop, DRM_AUTH),
1243         DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, drm_noop, DRM_AUTH),
1244         DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1245         DRM_IOCTL_DEF_DRV(I915_GEM_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
1246         DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH|DRM_UNLOCKED),
1247         DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2, i915_gem_execbuffer2, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
1248         DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED),
1249         DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED),
1250         DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
1251         DRM_IOCTL_DEF_DRV(I915_GEM_SET_CACHING, i915_gem_set_caching_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1252         DRM_IOCTL_DEF_DRV(I915_GEM_GET_CACHING, i915_gem_get_caching_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1253         DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
1254         DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
1255         DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
1256         DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1257         DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1258         DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1259         DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1260         DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1261         DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1262         DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1263         DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1264         DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1265         DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1266         DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id, DRM_UNLOCKED),
1267         DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1268         DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
1269         DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
1270         DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
1271         DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, drm_noop, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
1272         DRM_IOCTL_DEF_DRV(I915_GEM_WAIT, i915_gem_wait_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
1273         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE, i915_gem_context_create_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1274         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY, i915_gem_context_destroy_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1275         DRM_IOCTL_DEF_DRV(I915_REG_READ, i915_reg_read_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1276         DRM_IOCTL_DEF_DRV(I915_GET_RESET_STATS, i915_get_reset_stats_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1277 #if 0
1278         DRM_IOCTL_DEF_DRV(I915_GEM_USERPTR, i915_gem_userptr_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1279 #endif
1280         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_GETPARAM, i915_gem_context_getparam_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1281         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_SETPARAM, i915_gem_context_setparam_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1282 };
1283
1284 int i915_max_ioctl = ARRAY_SIZE(i915_ioctls);