2 * Copyright (c) 1997, 1998, 1999
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
32 * $FreeBSD: src/sys/pci/if_sf.c,v 1.18.2.8 2001/12/16 15:46:07 luigi Exp $
36 * Adaptec AIC-6915 "Starfire" PCI fast ethernet driver for FreeBSD.
37 * Programming manual is available from:
38 * ftp.adaptec.com:/pub/BBS/userguides/aic6915_pg.pdf.
40 * Written by Bill Paul <wpaul@ctr.columbia.edu>
41 * Department of Electical Engineering
42 * Columbia University, New York City
46 * The Adaptec AIC-6915 "Starfire" is a 64-bit 10/100 PCI ethernet
47 * controller designed with flexibility and reducing CPU load in mind.
48 * The Starfire offers high and low priority buffer queues, a
49 * producer/consumer index mechanism and several different buffer
50 * queue and completion queue descriptor types. Any one of a number
51 * of different driver designs can be used, depending on system and
52 * OS requirements. This driver makes use of type0 transmit frame
53 * descriptors (since BSD fragments packets across an mbuf chain)
54 * and two RX buffer queues prioritized on size (one queue for small
55 * frames that will fit into a single mbuf, another with full size
56 * mbuf clusters for everything else). The producer/consumer indexes
57 * and completion queues are also used.
59 * One downside to the Starfire has to do with alignment: buffer
60 * queues must be aligned on 256-byte boundaries, and receive buffers
61 * must be aligned on longword boundaries. The receive buffer alignment
62 * causes problems on the Alpha platform, where the packet payload
63 * should be longword aligned. There is no simple way around this.
65 * For receive filtering, the Starfire offers 16 perfect filter slots
66 * and a 512-bit hash table.
68 * The Starfire has no internal transceiver, relying instead on an
69 * external MII-based transceiver. Accessing registers on external
70 * PHYs is done through a special register map rather than with the
71 * usual bitbang MDIO method.
73 * Acesssing the registers on the Starfire is a little tricky. The
74 * Starfire has a 512K internal register space. When programmed for
75 * PCI memory mapped mode, the entire register space can be accessed
76 * directly. However in I/O space mode, only 256 bytes are directly
77 * mapped into PCI I/O space. The other registers can be accessed
78 * indirectly using the SF_INDIRECTIO_ADDR and SF_INDIRECTIO_DATA
79 * registers inside the 256-byte I/O window.
82 #include <sys/param.h>
83 #include <sys/systm.h>
84 #include <sys/sockio.h>
86 #include <sys/malloc.h>
87 #include <sys/kernel.h>
88 #include <sys/interrupt.h>
89 #include <sys/socket.h>
90 #include <sys/serialize.h>
95 #include <net/ifq_var.h>
96 #include <net/if_arp.h>
97 #include <net/ethernet.h>
98 #include <net/if_dl.h>
99 #include <net/if_media.h>
103 #include <vm/vm.h> /* for vtophys */
104 #include <vm/pmap.h> /* for vtophys */
106 #include <machine/clock.h> /* for DELAY */
108 #include "../mii_layer/mii.h"
109 #include "../mii_layer/miivar.h"
111 /* "controller miibus0" required. See GENERIC if you get errors here. */
112 #include "miibus_if.h"
115 #include <bus/pci/pcireg.h>
116 #include <bus/pci/pcivar.h>
118 #define SF_USEIOSPACE
120 #include "if_sfreg.h"
122 static struct sf_type sf_devs[] = {
123 { PCI_VENDOR_ADP, PCI_PRODUCT_ADP_AIC6915,
124 "Adaptec AIC-6915 10/100BaseTX" },
128 static int sf_probe (device_t);
129 static int sf_attach (device_t);
130 static int sf_detach (device_t);
131 static void sf_intr (void *);
132 static void sf_stats_update (void *);
133 static void sf_rxeof (struct sf_softc *);
134 static void sf_txeof (struct sf_softc *);
135 static int sf_encap (struct sf_softc *,
136 struct sf_tx_bufdesc_type0 *,
138 static void sf_start (struct ifnet *, struct ifaltq_subque *);
139 static int sf_ioctl (struct ifnet *, u_long, caddr_t,
141 static void sf_init (void *);
142 static void sf_stop (struct sf_softc *);
143 static void sf_watchdog (struct ifnet *);
144 static void sf_shutdown (device_t);
145 static int sf_ifmedia_upd (struct ifnet *);
146 static void sf_ifmedia_sts (struct ifnet *, struct ifmediareq *);
147 static void sf_reset (struct sf_softc *);
148 static int sf_init_rx_ring (struct sf_softc *);
149 static void sf_init_tx_ring (struct sf_softc *);
150 static int sf_newbuf (struct sf_softc *,
151 struct sf_rx_bufdesc_type0 *,
153 static void sf_setmulti (struct sf_softc *);
154 static int sf_setperf (struct sf_softc *, int, caddr_t);
155 static int sf_sethash (struct sf_softc *, caddr_t, int);
157 static int sf_setvlan (struct sf_softc *, int, u_int32_t);
160 static u_int8_t sf_read_eeprom (struct sf_softc *, int);
161 static u_int32_t sf_calchash (caddr_t);
163 static int sf_miibus_readreg (device_t, int, int);
164 static int sf_miibus_writereg (device_t, int, int, int);
165 static void sf_miibus_statchg (device_t);
167 static u_int32_t csr_read_4 (struct sf_softc *, int);
168 static void csr_write_4 (struct sf_softc *, int, u_int32_t);
169 static void sf_txthresh_adjust (struct sf_softc *);
172 #define SF_RES SYS_RES_IOPORT
173 #define SF_RID SF_PCI_LOIO
175 #define SF_RES SYS_RES_MEMORY
176 #define SF_RID SF_PCI_LOMEM
179 static device_method_t sf_methods[] = {
180 /* Device interface */
181 DEVMETHOD(device_probe, sf_probe),
182 DEVMETHOD(device_attach, sf_attach),
183 DEVMETHOD(device_detach, sf_detach),
184 DEVMETHOD(device_shutdown, sf_shutdown),
187 DEVMETHOD(bus_print_child, bus_generic_print_child),
188 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
191 DEVMETHOD(miibus_readreg, sf_miibus_readreg),
192 DEVMETHOD(miibus_writereg, sf_miibus_writereg),
193 DEVMETHOD(miibus_statchg, sf_miibus_statchg),
198 static driver_t sf_driver = {
201 sizeof(struct sf_softc),
204 static devclass_t sf_devclass;
206 DECLARE_DUMMY_MODULE(if_sf);
207 DRIVER_MODULE(if_sf, pci, sf_driver, sf_devclass, NULL, NULL);
208 DRIVER_MODULE(miibus, sf, miibus_driver, miibus_devclass, NULL, NULL);
210 #define SF_SETBIT(sc, reg, x) \
211 csr_write_4(sc, reg, csr_read_4(sc, reg) | x)
213 #define SF_CLRBIT(sc, reg, x) \
214 csr_write_4(sc, reg, csr_read_4(sc, reg) & ~x)
217 csr_read_4(struct sf_softc *sc, int reg)
222 CSR_WRITE_4(sc, SF_INDIRECTIO_ADDR, reg + SF_RMAP_INTREG_BASE);
223 val = CSR_READ_4(sc, SF_INDIRECTIO_DATA);
225 val = CSR_READ_4(sc, (reg + SF_RMAP_INTREG_BASE));
232 sf_read_eeprom(struct sf_softc *sc, int reg)
236 val = (csr_read_4(sc, SF_EEADDR_BASE +
237 (reg & 0xFFFFFFFC)) >> (8 * (reg & 3))) & 0xFF;
243 csr_write_4(struct sf_softc *sc, int reg, u_int32_t val)
246 CSR_WRITE_4(sc, SF_INDIRECTIO_ADDR, reg + SF_RMAP_INTREG_BASE);
247 CSR_WRITE_4(sc, SF_INDIRECTIO_DATA, val);
249 CSR_WRITE_4(sc, (reg + SF_RMAP_INTREG_BASE), val);
255 sf_calchash(caddr_t addr)
257 u_int32_t crc, carry;
261 /* Compute CRC for the address value. */
262 crc = 0xFFFFFFFF; /* initial value */
264 for (i = 0; i < 6; i++) {
266 for (j = 0; j < 8; j++) {
267 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01);
271 crc = (crc ^ 0x04c11db6) | carry;
275 /* return the filter bit position */
276 return(crc >> 23 & 0x1FF);
280 * Copy the address 'mac' into the perfect RX filter entry at
281 * offset 'idx.' The perfect filter only has 16 entries so do
285 sf_setperf(struct sf_softc *sc, int idx, caddr_t mac)
289 if (idx < 0 || idx > SF_RXFILT_PERFECT_CNT)
295 p = (u_int16_t *)mac;
297 csr_write_4(sc, SF_RXFILT_PERFECT_BASE +
298 (idx * SF_RXFILT_PERFECT_SKIP), htons(p[2]));
299 csr_write_4(sc, SF_RXFILT_PERFECT_BASE +
300 (idx * SF_RXFILT_PERFECT_SKIP) + 4, htons(p[1]));
301 csr_write_4(sc, SF_RXFILT_PERFECT_BASE +
302 (idx * SF_RXFILT_PERFECT_SKIP) + 8, htons(p[0]));
308 * Set the bit in the 512-bit hash table that corresponds to the
309 * specified mac address 'mac.' If 'prio' is nonzero, update the
310 * priority hash table instead of the filter hash table.
313 sf_sethash(struct sf_softc *sc, caddr_t mac, int prio)
320 h = sf_calchash(mac);
323 SF_SETBIT(sc, SF_RXFILT_HASH_BASE + SF_RXFILT_HASH_PRIOOFF +
324 (SF_RXFILT_HASH_SKIP * (h >> 4)), (1 << (h & 0xF)));
326 SF_SETBIT(sc, SF_RXFILT_HASH_BASE + SF_RXFILT_HASH_ADDROFF +
327 (SF_RXFILT_HASH_SKIP * (h >> 4)), (1 << (h & 0xF)));
335 * Set a VLAN tag in the receive filter.
338 sf_setvlan(struct sf_softc *sc, int idx, u_int32_t vlan)
340 if (idx < 0 || idx >> SF_RXFILT_HASH_CNT)
343 csr_write_4(sc, SF_RXFILT_HASH_BASE +
344 (idx * SF_RXFILT_HASH_SKIP) + SF_RXFILT_HASH_VLANOFF, vlan);
351 sf_miibus_readreg(device_t dev, int phy, int reg)
357 sc = device_get_softc(dev);
359 for (i = 0; i < SF_TIMEOUT; i++) {
360 val = csr_read_4(sc, SF_PHY_REG(phy, reg));
361 if (val & SF_MII_DATAVALID)
368 if ((val & 0x0000FFFF) == 0xFFFF)
371 return(val & 0x0000FFFF);
375 sf_miibus_writereg(device_t dev, int phy, int reg, int val)
381 sc = device_get_softc(dev);
383 csr_write_4(sc, SF_PHY_REG(phy, reg), val);
385 for (i = 0; i < SF_TIMEOUT; i++) {
386 busy = csr_read_4(sc, SF_PHY_REG(phy, reg));
387 if (!(busy & SF_MII_BUSY))
395 sf_miibus_statchg(device_t dev)
398 struct mii_data *mii;
400 sc = device_get_softc(dev);
401 mii = device_get_softc(sc->sf_miibus);
403 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
404 SF_SETBIT(sc, SF_MACCFG_1, SF_MACCFG1_FULLDUPLEX);
405 csr_write_4(sc, SF_BKTOBKIPG, SF_IPGT_FDX);
407 SF_CLRBIT(sc, SF_MACCFG_1, SF_MACCFG1_FULLDUPLEX);
408 csr_write_4(sc, SF_BKTOBKIPG, SF_IPGT_HDX);
415 sf_setmulti(struct sf_softc *sc)
419 struct ifmultiaddr *ifma;
420 u_int8_t dummy[] = { 0, 0, 0, 0, 0, 0 };
422 ifp = &sc->arpcom.ac_if;
424 /* First zot all the existing filters. */
425 for (i = 1; i < SF_RXFILT_PERFECT_CNT; i++)
426 sf_setperf(sc, i, (char *)&dummy);
427 for (i = SF_RXFILT_HASH_BASE;
428 i < (SF_RXFILT_HASH_MAX + 1); i += 4)
429 csr_write_4(sc, i, 0);
430 SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_ALLMULTI);
432 /* Now program new ones. */
433 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
434 SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_ALLMULTI);
437 TAILQ_FOREACH_REVERSE(ifma, &ifp->if_multiaddrs, ifmultihead, ifma_link) {
438 if (ifma->ifma_addr->sa_family != AF_LINK)
441 * Program the first 15 multicast groups
442 * into the perfect filter. For all others,
443 * use the hash table.
445 if (i < SF_RXFILT_PERFECT_CNT) {
447 LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
453 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 0);
464 sf_ifmedia_upd(struct ifnet *ifp)
467 struct mii_data *mii;
470 mii = device_get_softc(sc->sf_miibus);
472 if (mii->mii_instance) {
473 struct mii_softc *miisc;
474 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL;
475 miisc = LIST_NEXT(miisc, mii_list))
476 mii_phy_reset(miisc);
484 * Report current media status.
487 sf_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
490 struct mii_data *mii;
493 mii = device_get_softc(sc->sf_miibus);
496 ifmr->ifm_active = mii->mii_media_active;
497 ifmr->ifm_status = mii->mii_media_status;
503 sf_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
505 struct sf_softc *sc = ifp->if_softc;
506 struct ifreq *ifr = (struct ifreq *) data;
507 struct mii_data *mii;
512 if (ifp->if_flags & IFF_UP) {
513 if (ifp->if_flags & IFF_RUNNING &&
514 ifp->if_flags & IFF_PROMISC &&
515 !(sc->sf_if_flags & IFF_PROMISC)) {
516 SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_PROMISC);
517 } else if (ifp->if_flags & IFF_RUNNING &&
518 !(ifp->if_flags & IFF_PROMISC) &&
519 sc->sf_if_flags & IFF_PROMISC) {
520 SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_PROMISC);
521 } else if (!(ifp->if_flags & IFF_RUNNING))
524 if (ifp->if_flags & IFF_RUNNING)
527 sc->sf_if_flags = ifp->if_flags;
537 mii = device_get_softc(sc->sf_miibus);
538 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
541 error = ether_ioctl(ifp, command, data);
549 sf_reset(struct sf_softc *sc)
553 csr_write_4(sc, SF_GEN_ETH_CTL, 0);
554 SF_SETBIT(sc, SF_MACCFG_1, SF_MACCFG1_SOFTRESET);
556 SF_CLRBIT(sc, SF_MACCFG_1, SF_MACCFG1_SOFTRESET);
558 SF_SETBIT(sc, SF_PCI_DEVCFG, SF_PCIDEVCFG_RESET);
560 for (i = 0; i < SF_TIMEOUT; i++) {
562 if (!(csr_read_4(sc, SF_PCI_DEVCFG) & SF_PCIDEVCFG_RESET))
567 kprintf("sf%d: reset never completed!\n", sc->sf_unit);
569 /* Wait a little while for the chip to get its brains in order. */
575 * Probe for an Adaptec AIC-6915 chip. Check the PCI vendor and device
576 * IDs against our list and return a device name if we find a match.
577 * We also check the subsystem ID so that we can identify exactly which
578 * NIC has been found, if possible.
581 sf_probe(device_t dev)
587 while(t->sf_name != NULL) {
588 if ((pci_get_vendor(dev) == t->sf_vid) &&
589 (pci_get_device(dev) == t->sf_did)) {
590 switch((pci_read_config(dev,
591 SF_PCI_SUBVEN_ID, 4) >> 16) & 0xFFFF) {
592 case AD_SUBSYSID_62011_REV0:
593 case AD_SUBSYSID_62011_REV1:
595 "Adaptec ANA-62011 10/100BaseTX");
598 case AD_SUBSYSID_62022:
600 "Adaptec ANA-62022 10/100BaseTX");
603 case AD_SUBSYSID_62044_REV0:
604 case AD_SUBSYSID_62044_REV1:
606 "Adaptec ANA-62044 10/100BaseTX");
609 case AD_SUBSYSID_62020:
611 "Adaptec ANA-62020 10/100BaseFX");
614 case AD_SUBSYSID_69011:
616 "Adaptec ANA-69011 10/100BaseTX");
620 device_set_desc(dev, t->sf_name);
632 * Attach the interface. Allocate softc structures, do ifmedia
633 * setup and ethernet/BPF attach.
636 sf_attach(device_t dev)
642 int unit, rid, error = 0;
644 sc = device_get_softc(dev);
645 unit = device_get_unit(dev);
648 * Handle power management nonsense.
650 command = pci_read_config(dev, SF_PCI_CAPID, 4) & 0x000000FF;
651 if (command == 0x01) {
653 command = pci_read_config(dev, SF_PCI_PWRMGMTCTRL, 4);
654 if (command & SF_PSTATE_MASK) {
655 u_int32_t iobase, membase, irq;
657 /* Save important PCI config data. */
658 iobase = pci_read_config(dev, SF_PCI_LOIO, 4);
659 membase = pci_read_config(dev, SF_PCI_LOMEM, 4);
660 irq = pci_read_config(dev, SF_PCI_INTLINE, 4);
662 /* Reset the power state. */
663 kprintf("sf%d: chip is in D%d power mode "
664 "-- setting to D0\n", unit, command & SF_PSTATE_MASK);
665 command &= 0xFFFFFFFC;
666 pci_write_config(dev, SF_PCI_PWRMGMTCTRL, command, 4);
668 /* Restore PCI config data. */
669 pci_write_config(dev, SF_PCI_LOIO, iobase, 4);
670 pci_write_config(dev, SF_PCI_LOMEM, membase, 4);
671 pci_write_config(dev, SF_PCI_INTLINE, irq, 4);
676 * Map control/status registers.
678 command = pci_read_config(dev, PCIR_COMMAND, 4);
679 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN);
680 pci_write_config(dev, PCIR_COMMAND, command, 4);
681 command = pci_read_config(dev, PCIR_COMMAND, 4);
684 if (!(command & PCIM_CMD_PORTEN)) {
685 kprintf("sf%d: failed to enable I/O ports!\n", unit);
690 if (!(command & PCIM_CMD_MEMEN)) {
691 kprintf("sf%d: failed to enable memory mapping!\n", unit);
698 sc->sf_res = bus_alloc_resource_any(dev, SF_RES, &rid, RF_ACTIVE);
700 if (sc->sf_res == NULL) {
701 kprintf ("sf%d: couldn't map ports\n", unit);
706 sc->sf_btag = rman_get_bustag(sc->sf_res);
707 sc->sf_bhandle = rman_get_bushandle(sc->sf_res);
709 /* Allocate interrupt */
711 sc->sf_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
712 RF_SHAREABLE | RF_ACTIVE);
714 if (sc->sf_irq == NULL) {
715 kprintf("sf%d: couldn't map interrupt\n", unit);
720 callout_init(&sc->sf_stat_timer);
722 /* Reset the adapter. */
726 * Get station address from the EEPROM.
728 for (i = 0; i < ETHER_ADDR_LEN; i++)
729 sc->arpcom.ac_enaddr[i] =
730 sf_read_eeprom(sc, SF_EE_NODEADDR + ETHER_ADDR_LEN - i);
734 /* Allocate the descriptor queues. */
735 sc->sf_ldata = contigmalloc(sizeof(struct sf_list_data), M_DEVBUF,
736 M_WAITOK | M_ZERO, 0, 0xffffffff, PAGE_SIZE, 0);
738 if (sc->sf_ldata == NULL) {
739 kprintf("sf%d: no memory for list buffers!\n", unit);
745 if (mii_phy_probe(dev, &sc->sf_miibus,
746 sf_ifmedia_upd, sf_ifmedia_sts)) {
747 kprintf("sf%d: MII without any phy!\n", sc->sf_unit);
752 ifp = &sc->arpcom.ac_if;
754 if_initname(ifp, "sf", unit);
755 ifp->if_mtu = ETHERMTU;
756 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
757 ifp->if_ioctl = sf_ioctl;
758 ifp->if_start = sf_start;
759 ifp->if_watchdog = sf_watchdog;
760 ifp->if_init = sf_init;
761 ifp->if_baudrate = 10000000;
762 ifq_set_maxlen(&ifp->if_snd, SF_TX_DLIST_CNT - 1);
763 ifq_set_ready(&ifp->if_snd);
766 * Call MI attach routine.
768 ether_ifattach(ifp, sc->arpcom.ac_enaddr, NULL);
770 ifq_set_cpuid(&ifp->if_snd, rman_get_cpuid(sc->sf_irq));
772 error = bus_setup_intr(dev, sc->sf_irq, INTR_MPSAFE,
773 sf_intr, sc, &sc->sf_intrhand,
778 device_printf(dev, "couldn't set up irq\n");
790 sf_detach(device_t dev)
792 struct sf_softc *sc = device_get_softc(dev);
793 struct ifnet *ifp = &sc->arpcom.ac_if;
795 if (device_is_attached(dev)) {
796 lwkt_serialize_enter(ifp->if_serializer);
798 bus_teardown_intr(dev, sc->sf_irq, sc->sf_intrhand);
799 lwkt_serialize_exit(ifp->if_serializer);
805 device_delete_child(dev, sc->sf_miibus);
806 bus_generic_detach(dev);
809 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sf_irq);
811 bus_release_resource(dev, SF_RES, SF_RID, sc->sf_res);
814 contigfree(sc->sf_ldata, sizeof(struct sf_list_data),
822 sf_init_rx_ring(struct sf_softc *sc)
824 struct sf_list_data *ld;
829 bzero((char *)ld->sf_rx_dlist_big,
830 sizeof(struct sf_rx_bufdesc_type0) * SF_RX_DLIST_CNT);
831 bzero((char *)ld->sf_rx_clist,
832 sizeof(struct sf_rx_cmpdesc_type3) * SF_RX_CLIST_CNT);
834 for (i = 0; i < SF_RX_DLIST_CNT; i++) {
835 if (sf_newbuf(sc, &ld->sf_rx_dlist_big[i], NULL) == ENOBUFS)
843 sf_init_tx_ring(struct sf_softc *sc)
845 struct sf_list_data *ld;
850 bzero((char *)ld->sf_tx_dlist,
851 sizeof(struct sf_tx_bufdesc_type0) * SF_TX_DLIST_CNT);
852 bzero((char *)ld->sf_tx_clist,
853 sizeof(struct sf_tx_cmpdesc_type0) * SF_TX_CLIST_CNT);
855 for (i = 0; i < SF_TX_DLIST_CNT; i++)
856 ld->sf_tx_dlist[i].sf_id = SF_TX_BUFDESC_ID;
857 for (i = 0; i < SF_TX_CLIST_CNT; i++)
858 ld->sf_tx_clist[i].sf_type = SF_TXCMPTYPE_TX;
860 ld->sf_tx_dlist[SF_TX_DLIST_CNT - 1].sf_end = 1;
867 sf_newbuf(struct sf_softc *sc, struct sf_rx_bufdesc_type0 *c,
870 struct mbuf *m_new = NULL;
873 MGETHDR(m_new, M_NOWAIT, MT_DATA);
877 MCLGET(m_new, M_NOWAIT);
878 if (!(m_new->m_flags & M_EXT)) {
882 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
885 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
886 m_new->m_data = m_new->m_ext.ext_buf;
889 m_adj(m_new, sizeof(u_int64_t));
892 c->sf_addrlo = SF_RX_HOSTADDR(vtophys(mtod(m_new, caddr_t)));
899 * The starfire is programmed to use 'normal' mode for packet reception,
900 * which means we use the consumer/producer model for both the buffer
901 * descriptor queue and the completion descriptor queue. The only problem
902 * with this is that it involves a lot of register accesses: we have to
903 * read the RX completion consumer and producer indexes and the RX buffer
904 * producer index, plus the RX completion consumer and RX buffer producer
905 * indexes have to be updated. It would have been easier if Adaptec had
906 * put each index in a separate register, especially given that the damn
907 * NIC has a 512K register space.
909 * In spite of all the lovely features that Adaptec crammed into the 6915,
910 * it is marred by one truly stupid design flaw, which is that receive
911 * buffer addresses must be aligned on a longword boundary. This forces
912 * the packet payload to be unaligned, which is suboptimal on the x86 and
913 * completely unuseable on the Alpha. Our only recourse is to copy received
914 * packets into properly aligned buffers before handing them off.
918 sf_rxeof(struct sf_softc *sc)
922 struct sf_rx_bufdesc_type0 *desc;
923 struct sf_rx_cmpdesc_type3 *cur_rx;
924 u_int32_t rxcons, rxprod;
925 int cmpprodidx, cmpconsidx, bufprodidx;
927 ifp = &sc->arpcom.ac_if;
929 rxcons = csr_read_4(sc, SF_CQ_CONSIDX);
930 rxprod = csr_read_4(sc, SF_RXDQ_PTR_Q1);
931 cmpprodidx = SF_IDX_LO(csr_read_4(sc, SF_CQ_PRODIDX));
932 cmpconsidx = SF_IDX_LO(rxcons);
933 bufprodidx = SF_IDX_LO(rxprod);
935 while (cmpconsidx != cmpprodidx) {
938 cur_rx = &sc->sf_ldata->sf_rx_clist[cmpconsidx];
939 desc = &sc->sf_ldata->sf_rx_dlist_big[cur_rx->sf_endidx];
941 SF_INC(cmpconsidx, SF_RX_CLIST_CNT);
942 SF_INC(bufprodidx, SF_RX_DLIST_CNT);
944 if (!(cur_rx->sf_status1 & SF_RXSTAT1_OK)) {
945 IFNET_STAT_INC(ifp, ierrors, 1);
946 sf_newbuf(sc, desc, m);
950 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN,
951 cur_rx->sf_len + ETHER_ALIGN, 0, ifp);
952 sf_newbuf(sc, desc, m);
954 IFNET_STAT_INC(ifp, ierrors, 1);
957 m_adj(m0, ETHER_ALIGN);
960 IFNET_STAT_INC(ifp, ipackets, 1);
962 ifp->if_input(ifp, m, NULL, -1);
965 csr_write_4(sc, SF_CQ_CONSIDX,
966 (rxcons & ~SF_CQ_CONSIDX_RXQ1) | cmpconsidx);
967 csr_write_4(sc, SF_RXDQ_PTR_Q1,
968 (rxprod & ~SF_RXDQ_PRODIDX) | bufprodidx);
974 * Read the transmit status from the completion queue and release
975 * mbufs. Note that the buffer descriptor index in the completion
976 * descriptor is an offset from the start of the transmit buffer
977 * descriptor list in bytes. This is important because the manual
978 * gives the impression that it should match the producer/consumer
979 * index, which is the offset in 8 byte blocks.
982 sf_txeof(struct sf_softc *sc)
984 int txcons, cmpprodidx, cmpconsidx;
985 struct sf_tx_cmpdesc_type1 *cur_cmp;
986 struct sf_tx_bufdesc_type0 *cur_tx;
989 ifp = &sc->arpcom.ac_if;
991 txcons = csr_read_4(sc, SF_CQ_CONSIDX);
992 cmpprodidx = SF_IDX_HI(csr_read_4(sc, SF_CQ_PRODIDX));
993 cmpconsidx = SF_IDX_HI(txcons);
995 while (cmpconsidx != cmpprodidx) {
996 cur_cmp = &sc->sf_ldata->sf_tx_clist[cmpconsidx];
997 cur_tx = &sc->sf_ldata->sf_tx_dlist[cur_cmp->sf_index >> 7];
999 if (cur_cmp->sf_txstat & SF_TXSTAT_TX_OK)
1000 IFNET_STAT_INC(ifp, opackets, 1);
1002 if (cur_cmp->sf_txstat & SF_TXSTAT_TX_UNDERRUN)
1003 sf_txthresh_adjust(sc);
1004 IFNET_STAT_INC(ifp, oerrors, 1);
1008 if (cur_tx->sf_mbuf != NULL) {
1009 m_freem(cur_tx->sf_mbuf);
1010 cur_tx->sf_mbuf = NULL;
1013 SF_INC(cmpconsidx, SF_TX_CLIST_CNT);
1017 ifq_clr_oactive(&ifp->if_snd);
1019 csr_write_4(sc, SF_CQ_CONSIDX,
1020 (txcons & ~SF_CQ_CONSIDX_TXQ) |
1021 ((cmpconsidx << 16) & 0xFFFF0000));
1027 sf_txthresh_adjust(struct sf_softc *sc)
1032 txfctl = csr_read_4(sc, SF_TX_FRAMCTL);
1033 txthresh = txfctl & SF_TXFRMCTL_TXTHRESH;
1034 if (txthresh < 0xFF) {
1036 txfctl &= ~SF_TXFRMCTL_TXTHRESH;
1039 kprintf("sf%d: tx underrun, increasing "
1040 "tx threshold to %d bytes\n",
1041 sc->sf_unit, txthresh * 4);
1043 csr_write_4(sc, SF_TX_FRAMCTL, txfctl);
1052 struct sf_softc *sc;
1057 ifp = &sc->arpcom.ac_if;
1059 if (!(csr_read_4(sc, SF_ISR_SHADOW) & SF_ISR_PCIINT_ASSERTED))
1062 /* Disable interrupts. */
1063 csr_write_4(sc, SF_IMR, 0x00000000);
1066 status = csr_read_4(sc, SF_ISR);
1068 csr_write_4(sc, SF_ISR, status);
1070 if (!(status & SF_INTRS))
1073 if (status & SF_ISR_RXDQ1_DMADONE)
1076 if (status & SF_ISR_TX_TXDONE ||
1077 status & SF_ISR_TX_DMADONE ||
1078 status & SF_ISR_TX_QUEUEDONE)
1081 if (status & SF_ISR_TX_LOFIFO)
1082 sf_txthresh_adjust(sc);
1084 if (status & SF_ISR_ABNORMALINTR) {
1085 if (status & SF_ISR_STATSOFLOW) {
1086 callout_stop(&sc->sf_stat_timer);
1087 sf_stats_update(sc);
1093 /* Re-enable interrupts. */
1094 csr_write_4(sc, SF_IMR, SF_INTRS);
1096 if (!ifq_is_empty(&ifp->if_snd))
1103 struct sf_softc *sc = xsc;
1104 struct ifnet *ifp = &sc->arpcom.ac_if;
1110 /* Init all the receive filter registers */
1111 for (i = SF_RXFILT_PERFECT_BASE;
1112 i < (SF_RXFILT_HASH_MAX + 1); i += 4)
1113 csr_write_4(sc, i, 0);
1115 /* Empty stats counter registers. */
1116 for (i = 0; i < sizeof(struct sf_stats)/sizeof(u_int32_t); i++)
1117 csr_write_4(sc, SF_STATS_BASE +
1118 (i + sizeof(u_int32_t)), 0);
1120 /* Init our MAC address */
1121 csr_write_4(sc, SF_PAR0, *(u_int32_t *)(&sc->arpcom.ac_enaddr[0]));
1122 csr_write_4(sc, SF_PAR1, *(u_int32_t *)(&sc->arpcom.ac_enaddr[4]));
1123 sf_setperf(sc, 0, (caddr_t)&sc->arpcom.ac_enaddr);
1125 if (sf_init_rx_ring(sc) == ENOBUFS) {
1126 kprintf("sf%d: initialization failed: no "
1127 "memory for rx buffers\n", sc->sf_unit);
1131 sf_init_tx_ring(sc);
1133 csr_write_4(sc, SF_RXFILT, SF_PERFMODE_NORMAL|SF_HASHMODE_WITHVLAN);
1135 /* If we want promiscuous mode, set the allframes bit. */
1136 if (ifp->if_flags & IFF_PROMISC) {
1137 SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_PROMISC);
1139 SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_PROMISC);
1142 if (ifp->if_flags & IFF_BROADCAST) {
1143 SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_BROAD);
1145 SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_BROAD);
1149 * Load the multicast filter.
1153 /* Init the completion queue indexes */
1154 csr_write_4(sc, SF_CQ_CONSIDX, 0);
1155 csr_write_4(sc, SF_CQ_PRODIDX, 0);
1157 /* Init the RX completion queue */
1158 csr_write_4(sc, SF_RXCQ_CTL_1,
1159 vtophys(sc->sf_ldata->sf_rx_clist) & SF_RXCQ_ADDR);
1160 SF_SETBIT(sc, SF_RXCQ_CTL_1, SF_RXCQTYPE_3);
1162 /* Init RX DMA control. */
1163 SF_SETBIT(sc, SF_RXDMA_CTL, SF_RXDMA_REPORTBADPKTS);
1165 /* Init the RX buffer descriptor queue. */
1166 csr_write_4(sc, SF_RXDQ_ADDR_Q1,
1167 vtophys(sc->sf_ldata->sf_rx_dlist_big));
1168 csr_write_4(sc, SF_RXDQ_CTL_1, (MCLBYTES << 16) | SF_DESCSPACE_16BYTES);
1169 csr_write_4(sc, SF_RXDQ_PTR_Q1, SF_RX_DLIST_CNT - 1);
1171 /* Init the TX completion queue */
1172 csr_write_4(sc, SF_TXCQ_CTL,
1173 vtophys(sc->sf_ldata->sf_tx_clist) & SF_RXCQ_ADDR);
1175 /* Init the TX buffer descriptor queue. */
1176 csr_write_4(sc, SF_TXDQ_ADDR_HIPRIO,
1177 vtophys(sc->sf_ldata->sf_tx_dlist));
1178 SF_SETBIT(sc, SF_TX_FRAMCTL, SF_TXFRMCTL_CPLAFTERTX);
1179 csr_write_4(sc, SF_TXDQ_CTL,
1180 SF_TXBUFDESC_TYPE0|SF_TXMINSPACE_128BYTES|SF_TXSKIPLEN_8BYTES);
1181 SF_SETBIT(sc, SF_TXDQ_CTL, SF_TXDQCTL_NODMACMP);
1183 /* Enable autopadding of short TX frames. */
1184 SF_SETBIT(sc, SF_MACCFG_1, SF_MACCFG1_AUTOPAD);
1186 /* Enable interrupts. */
1187 csr_write_4(sc, SF_IMR, SF_INTRS);
1188 SF_SETBIT(sc, SF_PCI_DEVCFG, SF_PCIDEVCFG_INTR_ENB);
1190 /* Enable the RX and TX engines. */
1191 SF_SETBIT(sc, SF_GEN_ETH_CTL, SF_ETHCTL_RX_ENB|SF_ETHCTL_RXDMA_ENB);
1192 SF_SETBIT(sc, SF_GEN_ETH_CTL, SF_ETHCTL_TX_ENB|SF_ETHCTL_TXDMA_ENB);
1194 /*mii_mediachg(mii);*/
1195 sf_ifmedia_upd(ifp);
1197 ifp->if_flags |= IFF_RUNNING;
1198 ifq_clr_oactive(&ifp->if_snd);
1200 callout_reset(&sc->sf_stat_timer, hz, sf_stats_update, sc);
1204 sf_encap(struct sf_softc *sc, struct sf_tx_bufdesc_type0 *c,
1205 struct mbuf *m_head)
1208 struct sf_frag *f = NULL;
1211 for (m = m_head; m != NULL; m = m->m_next) {
1212 if (m->m_len != 0) {
1213 if (frag == SF_MAXFRAGS)
1215 f = &c->sf_frags[frag];
1217 f->sf_pktlen = m_head->m_pkthdr.len;
1218 f->sf_fraglen = m->m_len;
1219 f->sf_addr = vtophys(mtod(m, vm_offset_t));
1223 /* Caller should make sure that 'm_head' is not excessive fragmented */
1224 KASSERT(m == NULL, ("too many fragments"));
1226 c->sf_mbuf = m_head;
1227 c->sf_id = SF_TX_BUFDESC_ID;
1228 c->sf_fragcnt = frag;
1237 sf_start(struct ifnet *ifp, struct ifaltq_subque *ifsq)
1239 struct sf_softc *sc;
1240 struct sf_tx_bufdesc_type0 *cur_tx = NULL;
1241 struct mbuf *m_head = NULL, *m_defragged;
1242 int i, txprod, need_trans = 0;
1244 ASSERT_ALTQ_SQ_DEFAULT(ifp, ifsq);
1249 ifq_purge(&ifp->if_snd);
1253 if ((ifp->if_flags & IFF_RUNNING) == 0 || ifq_is_oactive(&ifp->if_snd))
1256 txprod = csr_read_4(sc, SF_TXDQ_PRODIDX);
1257 i = SF_IDX_HI(txprod) >> 4;
1259 if (sc->sf_ldata->sf_tx_dlist[i].sf_mbuf != NULL) {
1260 kprintf("sf%d: TX ring full, resetting\n", sc->sf_unit);
1262 txprod = csr_read_4(sc, SF_TXDQ_PRODIDX);
1263 i = SF_IDX_HI(txprod) >> 4;
1266 while (sc->sf_ldata->sf_tx_dlist[i].sf_mbuf == NULL) {
1271 * Don't get the TX DMA queue get too full.
1273 if (sc->sf_tx_cnt > 64) {
1274 ifq_set_oactive(&ifp->if_snd);
1278 if (sc->sf_tx_cnt >= (SF_TX_DLIST_CNT - 5)) {
1279 ifq_set_oactive(&ifp->if_snd);
1285 m_head = ifq_dequeue(&ifp->if_snd);
1291 for (m = m_head; m != NULL; m = m->m_next)
1293 if (frag > SF_MAXFRAGS) {
1294 if (m_defragged != NULL) {
1296 * Even after defragmentation, there
1297 * are still too many fragments, so
1304 m_defragged = m_defrag(m_head, M_NOWAIT);
1305 if (m_defragged == NULL) {
1309 m_head = m_defragged;
1311 /* Recount # of fragments */
1315 cur_tx = &sc->sf_ldata->sf_tx_dlist[i];
1316 sf_encap(sc, cur_tx, m_head);
1317 BPF_MTAP(ifp, cur_tx->sf_mbuf);
1319 SF_INC(i, SF_TX_DLIST_CNT);
1328 csr_write_4(sc, SF_TXDQ_PRODIDX,
1329 (txprod & ~SF_TXDQ_PRODIDX_HIPRIO) |
1330 ((i << 20) & 0xFFFF0000));
1336 sf_stop(struct sf_softc *sc)
1341 ifp = &sc->arpcom.ac_if;
1343 callout_stop(&sc->sf_stat_timer);
1345 csr_write_4(sc, SF_GEN_ETH_CTL, 0);
1346 csr_write_4(sc, SF_CQ_CONSIDX, 0);
1347 csr_write_4(sc, SF_CQ_PRODIDX, 0);
1348 csr_write_4(sc, SF_RXDQ_ADDR_Q1, 0);
1349 csr_write_4(sc, SF_RXDQ_CTL_1, 0);
1350 csr_write_4(sc, SF_RXDQ_PTR_Q1, 0);
1351 csr_write_4(sc, SF_TXCQ_CTL, 0);
1352 csr_write_4(sc, SF_TXDQ_ADDR_HIPRIO, 0);
1353 csr_write_4(sc, SF_TXDQ_CTL, 0);
1358 for (i = 0; i < SF_RX_DLIST_CNT; i++) {
1359 if (sc->sf_ldata->sf_rx_dlist_big[i].sf_mbuf != NULL) {
1360 m_freem(sc->sf_ldata->sf_rx_dlist_big[i].sf_mbuf);
1361 sc->sf_ldata->sf_rx_dlist_big[i].sf_mbuf = NULL;
1365 for (i = 0; i < SF_TX_DLIST_CNT; i++) {
1366 if (sc->sf_ldata->sf_tx_dlist[i].sf_mbuf != NULL) {
1367 m_freem(sc->sf_ldata->sf_tx_dlist[i].sf_mbuf);
1368 sc->sf_ldata->sf_tx_dlist[i].sf_mbuf = NULL;
1372 ifp->if_flags &= ~IFF_RUNNING;
1373 ifq_clr_oactive(&ifp->if_snd);
1379 * Note: it is important that this function not be interrupted. We
1380 * use a two-stage register access scheme: if we are interrupted in
1381 * between setting the indirect address register and reading from the
1382 * indirect data register, the contents of the address register could
1383 * be changed out from under us.
1386 sf_stats_update(void *xsc)
1388 struct sf_softc *sc = xsc;
1389 struct ifnet *ifp = &sc->arpcom.ac_if;
1390 struct mii_data *mii = device_get_softc(sc->sf_miibus);
1391 struct sf_stats stats;
1395 lwkt_serialize_enter(ifp->if_serializer);
1397 ptr = (u_int32_t *)&stats;
1398 for (i = 0; i < sizeof(stats)/sizeof(u_int32_t); i++)
1399 ptr[i] = csr_read_4(sc, SF_STATS_BASE +
1400 (i + sizeof(u_int32_t)));
1402 for (i = 0; i < sizeof(stats)/sizeof(u_int32_t); i++)
1403 csr_write_4(sc, SF_STATS_BASE +
1404 (i + sizeof(u_int32_t)), 0);
1406 IFNET_STAT_INC(ifp, collisions, stats.sf_tx_single_colls +
1407 stats.sf_tx_multi_colls + stats.sf_tx_excess_colls);
1412 if (mii->mii_media_status & IFM_ACTIVE &&
1413 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
1415 if (!ifq_is_empty(&ifp->if_snd))
1420 callout_reset(&sc->sf_stat_timer, hz, sf_stats_update, sc);
1422 lwkt_serialize_exit(ifp->if_serializer);
1426 sf_watchdog(struct ifnet *ifp)
1428 struct sf_softc *sc;
1432 IFNET_STAT_INC(ifp, oerrors, 1);
1433 kprintf("sf%d: watchdog timeout\n", sc->sf_unit);
1439 if (!ifq_is_empty(&ifp->if_snd))
1444 sf_shutdown(device_t dev)
1446 struct sf_softc *sc;
1449 sc = device_get_softc(dev);
1450 ifp = &sc->arpcom.ac_if;
1451 lwkt_serialize_enter(ifp->if_serializer);
1453 lwkt_serialize_exit(ifp->if_serializer);