2 * Copyright (c) 1997, 1998, 1999
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
32 * $FreeBSD: src/sys/pci/if_sis.c,v 1.13.4.24 2003/03/05 18:42:33 njl Exp $
36 * SiS 900/SiS 7016 fast ethernet PCI NIC driver. Datasheets are
37 * available from http://www.sis.com.tw.
39 * This driver also supports the NatSemi DP83815. Datasheets are
40 * available from http://www.national.com.
42 * Written by Bill Paul <wpaul@ee.columbia.edu>
43 * Electrical Engineering Department
44 * Columbia University, New York City
48 * The SiS 900 is a fairly simple chip. It uses bus master DMA with
49 * simple TX and RX descriptors of 3 longwords in size. The receiver
50 * has a single perfect filter entry for the station address and a
51 * 128-bit multicast hash table. The SiS 900 has a built-in MII-based
52 * transceiver while the 7016 requires an external transceiver chip.
53 * Both chips offer the standard bit-bang MII interface as well as
54 * an enchanced PHY interface which simplifies accessing MII registers.
56 * The only downside to this chipset is that RX descriptors must be
60 #include "opt_ifpoll.h"
62 #include <sys/param.h>
63 #include <sys/systm.h>
64 #include <sys/sockio.h>
66 #include <sys/malloc.h>
67 #include <sys/kernel.h>
68 #include <sys/socket.h>
69 #include <sys/sysctl.h>
70 #include <sys/serialize.h>
73 #include <sys/interrupt.h>
76 #include <net/ifq_var.h>
77 #include <net/if_arp.h>
78 #include <net/ethernet.h>
79 #include <net/if_dl.h>
80 #include <net/if_media.h>
81 #include <net/if_poll.h>
82 #include <net/if_types.h>
83 #include <net/vlan/if_vlan_var.h>
87 #include <dev/netif/mii_layer/mii.h>
88 #include <dev/netif/mii_layer/miivar.h>
91 #include <bus/pci/pcireg.h>
92 #include <bus/pci/pcivar.h>
94 #define SIS_USEIOSPACE
96 #include "if_sisreg.h"
98 /* "controller miibus0" required. See GENERIC if you get errors here. */
99 #include "miibus_if.h"
102 * Various supported device vendors/types and their names.
104 static struct sis_type sis_devs[] = {
105 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_900, "SiS 900 10/100BaseTX" },
106 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_7016, "SiS 7016 10/100BaseTX" },
107 { PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815, "NatSemi DP8381[56] 10/100BaseTX" },
111 static int sis_probe(device_t);
112 static int sis_attach(device_t);
113 static int sis_detach(device_t);
115 static int sis_newbuf(struct sis_softc *, int, int);
116 static void sis_setup_rxdesc(struct sis_softc *, int);
117 static int sis_encap(struct sis_softc *, struct mbuf **, uint32_t *);
118 static void sis_rxeof(struct sis_softc *);
119 static void sis_rxeoc(struct sis_softc *);
120 static void sis_txeof(struct sis_softc *);
121 static void sis_intr(void *);
122 static void sis_tick(void *);
123 static void sis_start(struct ifnet *, struct ifaltq_subque *);
124 static int sis_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
125 static void sis_init(void *);
126 static void sis_stop(struct sis_softc *);
127 static void sis_watchdog(struct ifnet *);
128 static void sis_shutdown(device_t);
129 static int sis_ifmedia_upd(struct ifnet *);
130 static void sis_ifmedia_sts(struct ifnet *, struct ifmediareq *);
132 static uint16_t sis_reverse(uint16_t);
133 static void sis_delay(struct sis_softc *);
134 static void sis_eeprom_idle(struct sis_softc *);
135 static void sis_eeprom_putbyte(struct sis_softc *, int);
136 static void sis_eeprom_getword(struct sis_softc *, int, uint16_t *);
137 static void sis_read_eeprom(struct sis_softc *, caddr_t, int, int, int);
139 static void sis_read_cmos(struct sis_softc *, device_t, caddr_t, int, int);
140 static void sis_read_mac(struct sis_softc *, device_t, caddr_t);
141 static device_t sis_find_bridge(device_t);
144 static void sis_mii_sync(struct sis_softc *);
145 static void sis_mii_send(struct sis_softc *, uint32_t, int);
146 static int sis_mii_readreg(struct sis_softc *, struct sis_mii_frame *);
147 static int sis_mii_writereg(struct sis_softc *, struct sis_mii_frame *);
148 static int sis_miibus_readreg(device_t, int, int);
149 static int sis_miibus_writereg(device_t, int, int, int);
150 static void sis_miibus_statchg(device_t);
152 static void sis_setmulti_sis(struct sis_softc *);
153 static void sis_setmulti_ns(struct sis_softc *);
154 static uint32_t sis_mchash(struct sis_softc *, const uint8_t *);
155 static void sis_reset(struct sis_softc *);
156 static int sis_list_rx_init(struct sis_softc *);
157 static int sis_list_tx_init(struct sis_softc *);
159 static int sis_dma_alloc(device_t dev);
160 static void sis_dma_free(device_t dev);
162 static void sis_npoll(struct ifnet *, struct ifpoll_info *);
163 static void sis_npoll_compat(struct ifnet *, void *, int);
165 #ifdef SIS_USEIOSPACE
166 #define SIS_RES SYS_RES_IOPORT
167 #define SIS_RID SIS_PCI_LOIO
169 #define SIS_RES SYS_RES_MEMORY
170 #define SIS_RID SIS_PCI_LOMEM
173 static device_method_t sis_methods[] = {
174 /* Device interface */
175 DEVMETHOD(device_probe, sis_probe),
176 DEVMETHOD(device_attach, sis_attach),
177 DEVMETHOD(device_detach, sis_detach),
178 DEVMETHOD(device_shutdown, sis_shutdown),
181 DEVMETHOD(bus_print_child, bus_generic_print_child),
182 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
185 DEVMETHOD(miibus_readreg, sis_miibus_readreg),
186 DEVMETHOD(miibus_writereg, sis_miibus_writereg),
187 DEVMETHOD(miibus_statchg, sis_miibus_statchg),
192 static driver_t sis_driver = {
195 sizeof(struct sis_softc)
198 static devclass_t sis_devclass;
200 DECLARE_DUMMY_MODULE(if_sis);
201 DRIVER_MODULE(if_sis, pci, sis_driver, sis_devclass, NULL, NULL);
202 DRIVER_MODULE(miibus, sis, miibus_driver, miibus_devclass, NULL, NULL);
204 #define SIS_SETBIT(sc, reg, x) \
205 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x))
207 #define SIS_CLRBIT(sc, reg, x) \
208 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x))
211 CSR_WRITE_4(sc, SIS_EECTL, CSR_READ_4(sc, SIS_EECTL) | x)
214 CSR_WRITE_4(sc, SIS_EECTL, CSR_READ_4(sc, SIS_EECTL) & ~x)
217 * Routine to reverse the bits in a word. Stolen almost
218 * verbatim from /usr/games/fortune.
221 sis_reverse(uint16_t n)
223 n = ((n >> 1) & 0x5555) | ((n << 1) & 0xaaaa);
224 n = ((n >> 2) & 0x3333) | ((n << 2) & 0xcccc);
225 n = ((n >> 4) & 0x0f0f) | ((n << 4) & 0xf0f0);
226 n = ((n >> 8) & 0x00ff) | ((n << 8) & 0xff00);
232 sis_delay(struct sis_softc *sc)
236 for (idx = (300 / 33) + 1; idx > 0; idx--)
237 CSR_READ_4(sc, SIS_CSR);
241 sis_eeprom_idle(struct sis_softc *sc)
245 SIO_SET(SIS_EECTL_CSEL);
247 SIO_SET(SIS_EECTL_CLK);
250 for (i = 0; i < 25; i++) {
251 SIO_CLR(SIS_EECTL_CLK);
253 SIO_SET(SIS_EECTL_CLK);
257 SIO_CLR(SIS_EECTL_CLK);
259 SIO_CLR(SIS_EECTL_CSEL);
261 CSR_WRITE_4(sc, SIS_EECTL, 0x00000000);
265 * Send a read command and address to the EEPROM, check for ACK.
268 sis_eeprom_putbyte(struct sis_softc *sc, int addr)
272 d = addr | SIS_EECMD_READ;
275 * Feed in each bit and stobe the clock.
277 for (i = 0x400; i; i >>= 1) {
279 SIO_SET(SIS_EECTL_DIN);
281 SIO_CLR(SIS_EECTL_DIN);
283 SIO_SET(SIS_EECTL_CLK);
285 SIO_CLR(SIS_EECTL_CLK);
291 * Read a word of data stored in the EEPROM at address 'addr.'
294 sis_eeprom_getword(struct sis_softc *sc, int addr, uint16_t *dest)
299 /* Force EEPROM to idle state. */
302 /* Enter EEPROM access mode. */
304 SIO_CLR(SIS_EECTL_CLK);
306 SIO_SET(SIS_EECTL_CSEL);
310 * Send address of word we want to read.
312 sis_eeprom_putbyte(sc, addr);
315 * Start reading bits from EEPROM.
317 for (i = 0x8000; i; i >>= 1) {
318 SIO_SET(SIS_EECTL_CLK);
320 if (CSR_READ_4(sc, SIS_EECTL) & SIS_EECTL_DOUT)
323 SIO_CLR(SIS_EECTL_CLK);
327 /* Turn off EEPROM access mode. */
334 * Read a sequence of words from the EEPROM.
337 sis_read_eeprom(struct sis_softc *sc, caddr_t dest, int off, int cnt, int swap)
340 uint16_t word = 0, *ptr;
342 for (i = 0; i < cnt; i++) {
343 sis_eeprom_getword(sc, off + i, &word);
344 ptr = (uint16_t *)(dest + (i * 2));
354 sis_find_bridge(device_t dev)
356 devclass_t pci_devclass;
357 device_t *pci_devices;
359 device_t *pci_children;
360 int pci_childcount = 0;
361 device_t *busp, *childp;
362 device_t child = NULL;
365 if ((pci_devclass = devclass_find("pci")) == NULL)
368 devclass_get_devices(pci_devclass, &pci_devices, &pci_count);
370 for (i = 0, busp = pci_devices; i < pci_count; i++, busp++) {
372 device_get_children(*busp, &pci_children, &pci_childcount);
373 for (j = 0, childp = pci_children; j < pci_childcount;
375 if (pci_get_vendor(*childp) == PCI_VENDOR_SIS &&
376 pci_get_device(*childp) == 0x0008) {
384 kfree(pci_devices, M_TEMP);
385 kfree(pci_children, M_TEMP);
390 sis_read_cmos(struct sis_softc *sc, device_t dev, caddr_t dest, int off,
396 bus_space_tag_t btag;
398 bridge = sis_find_bridge(dev);
401 reg = pci_read_config(bridge, 0x48, 1);
402 pci_write_config(bridge, 0x48, reg|0x40, 1);
405 btag = X86_64_BUS_SPACE_IO;
407 for (i = 0; i < cnt; i++) {
408 bus_space_write_1(btag, 0x0, 0x70, i + off);
409 *(dest + i) = bus_space_read_1(btag, 0x0, 0x71);
412 pci_write_config(bridge, 0x48, reg & ~0x40, 1);
416 sis_read_mac(struct sis_softc *sc, device_t dev, caddr_t dest)
418 uint32_t filtsave, csrsave;
420 filtsave = CSR_READ_4(sc, SIS_RXFILT_CTL);
421 csrsave = CSR_READ_4(sc, SIS_CSR);
423 CSR_WRITE_4(sc, SIS_CSR, SIS_CSR_RELOAD | filtsave);
424 CSR_WRITE_4(sc, SIS_CSR, 0);
426 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave & ~SIS_RXFILTCTL_ENABLE);
428 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR0);
429 ((uint16_t *)dest)[0] = CSR_READ_2(sc, SIS_RXFILT_DATA);
430 CSR_WRITE_4(sc, SIS_RXFILT_CTL,SIS_FILTADDR_PAR1);
431 ((uint16_t *)dest)[1] = CSR_READ_2(sc, SIS_RXFILT_DATA);
432 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR2);
433 ((uint16_t *)dest)[2] = CSR_READ_2(sc, SIS_RXFILT_DATA);
435 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave);
436 CSR_WRITE_4(sc, SIS_CSR, csrsave);
441 * Sync the PHYs by setting data bit and strobing the clock 32 times.
444 sis_mii_sync(struct sis_softc *sc)
448 SIO_SET(SIS_MII_DIR|SIS_MII_DATA);
450 for (i = 0; i < 32; i++) {
451 SIO_SET(SIS_MII_CLK);
453 SIO_CLR(SIS_MII_CLK);
459 * Clock a series of bits through the MII.
462 sis_mii_send(struct sis_softc *sc, uint32_t bits, int cnt)
466 SIO_CLR(SIS_MII_CLK);
468 for (i = (0x1 << (cnt - 1)); i; i >>= 1) {
470 SIO_SET(SIS_MII_DATA);
472 SIO_CLR(SIS_MII_DATA);
474 SIO_CLR(SIS_MII_CLK);
476 SIO_SET(SIS_MII_CLK);
481 * Read an PHY register through the MII.
484 sis_mii_readreg(struct sis_softc *sc, struct sis_mii_frame *frame)
489 * Set up frame for RX.
491 frame->mii_stdelim = SIS_MII_STARTDELIM;
492 frame->mii_opcode = SIS_MII_READOP;
493 frame->mii_turnaround = 0;
499 SIO_SET(SIS_MII_DIR);
504 * Send command/address info.
506 sis_mii_send(sc, frame->mii_stdelim, 2);
507 sis_mii_send(sc, frame->mii_opcode, 2);
508 sis_mii_send(sc, frame->mii_phyaddr, 5);
509 sis_mii_send(sc, frame->mii_regaddr, 5);
512 SIO_CLR((SIS_MII_CLK|SIS_MII_DATA));
514 SIO_SET(SIS_MII_CLK);
518 SIO_CLR(SIS_MII_DIR);
521 SIO_CLR(SIS_MII_CLK);
523 ack = CSR_READ_4(sc, SIS_EECTL) & SIS_MII_DATA;
524 SIO_SET(SIS_MII_CLK);
528 * Now try reading data bits. If the ack failed, we still
529 * need to clock through 16 cycles to keep the PHY(s) in sync.
532 for(i = 0; i < 16; i++) {
533 SIO_CLR(SIS_MII_CLK);
535 SIO_SET(SIS_MII_CLK);
541 for (i = 0x8000; i; i >>= 1) {
542 SIO_CLR(SIS_MII_CLK);
545 if (CSR_READ_4(sc, SIS_EECTL) & SIS_MII_DATA)
546 frame->mii_data |= i;
549 SIO_SET(SIS_MII_CLK);
555 SIO_CLR(SIS_MII_CLK);
557 SIO_SET(SIS_MII_CLK);
566 * Write to a PHY register through the MII.
569 sis_mii_writereg(struct sis_softc *sc, struct sis_mii_frame *frame)
572 * Set up frame for TX.
575 frame->mii_stdelim = SIS_MII_STARTDELIM;
576 frame->mii_opcode = SIS_MII_WRITEOP;
577 frame->mii_turnaround = SIS_MII_TURNAROUND;
580 * Turn on data output.
582 SIO_SET(SIS_MII_DIR);
586 sis_mii_send(sc, frame->mii_stdelim, 2);
587 sis_mii_send(sc, frame->mii_opcode, 2);
588 sis_mii_send(sc, frame->mii_phyaddr, 5);
589 sis_mii_send(sc, frame->mii_regaddr, 5);
590 sis_mii_send(sc, frame->mii_turnaround, 2);
591 sis_mii_send(sc, frame->mii_data, 16);
594 SIO_SET(SIS_MII_CLK);
596 SIO_CLR(SIS_MII_CLK);
602 SIO_CLR(SIS_MII_DIR);
608 sis_miibus_readreg(device_t dev, int phy, int reg)
610 struct sis_softc *sc;
611 struct sis_mii_frame frame;
613 sc = device_get_softc(dev);
615 if (sc->sis_type == SIS_TYPE_83815) {
619 * The NatSemi chip can take a while after
620 * a reset to come ready, during which the BMSR
621 * returns a value of 0. This is *never* supposed
622 * to happen: some of the BMSR bits are meant to
623 * be hardwired in the on position, and this can
624 * confuse the miibus code a bit during the probe
625 * and attach phase. So we make an effort to check
626 * for this condition and wait for it to clear.
628 if (!CSR_READ_4(sc, NS_BMSR))
630 return CSR_READ_4(sc, NS_BMCR + (reg * 4));
633 * Chipsets < SIS_635 seem not to be able to read/write
634 * through mdio. Use the enhanced PHY access register
637 if (sc->sis_type == SIS_TYPE_900 &&
638 sc->sis_rev < SIS_REV_635) {
644 CSR_WRITE_4(sc, SIS_PHYCTL,
645 (phy << 11) | (reg << 6) | SIS_PHYOP_READ);
646 SIS_SETBIT(sc, SIS_PHYCTL, SIS_PHYCTL_ACCESS);
648 for (i = 0; i < SIS_TIMEOUT; i++) {
649 if (!(CSR_READ_4(sc, SIS_PHYCTL) & SIS_PHYCTL_ACCESS))
653 if (i == SIS_TIMEOUT) {
654 device_printf(dev, "PHY failed to come ready\n");
658 val = (CSR_READ_4(sc, SIS_PHYCTL) >> 16) & 0xFFFF;
665 bzero((char *)&frame, sizeof(frame));
667 frame.mii_phyaddr = phy;
668 frame.mii_regaddr = reg;
669 sis_mii_readreg(sc, &frame);
671 return(frame.mii_data);
676 sis_miibus_writereg(device_t dev, int phy, int reg, int data)
678 struct sis_softc *sc;
679 struct sis_mii_frame frame;
681 sc = device_get_softc(dev);
683 if (sc->sis_type == SIS_TYPE_83815) {
686 CSR_WRITE_4(sc, NS_BMCR + (reg * 4), data);
690 if (sc->sis_type == SIS_TYPE_900 &&
691 sc->sis_rev < SIS_REV_635) {
697 CSR_WRITE_4(sc, SIS_PHYCTL, (data << 16) | (phy << 11) |
698 (reg << 6) | SIS_PHYOP_WRITE);
699 SIS_SETBIT(sc, SIS_PHYCTL, SIS_PHYCTL_ACCESS);
701 for (i = 0; i < SIS_TIMEOUT; i++) {
702 if (!(CSR_READ_4(sc, SIS_PHYCTL) & SIS_PHYCTL_ACCESS))
706 if (i == SIS_TIMEOUT)
707 device_printf(dev, "PHY failed to come ready\n");
709 bzero((char *)&frame, sizeof(frame));
711 frame.mii_phyaddr = phy;
712 frame.mii_regaddr = reg;
713 frame.mii_data = data;
714 sis_mii_writereg(sc, &frame);
720 sis_miibus_statchg(device_t dev)
722 struct sis_softc *sc;
724 sc = device_get_softc(dev);
729 sis_mchash(struct sis_softc *sc, const uint8_t *addr)
735 /* Compute CRC for the address value. */
736 crc = 0xFFFFFFFF; /* initial value */
738 for (i = 0; i < 6; i++) {
740 for (j = 0; j < 8; j++) {
741 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01);
745 crc = (crc ^ 0x04c11db6) | carry;
750 * return the filter bit position
752 * The NatSemi chip has a 512-bit filter, which is
753 * different than the SiS, so we special-case it.
755 if (sc->sis_type == SIS_TYPE_83815)
757 else if (sc->sis_rev >= SIS_REV_635 || sc->sis_rev == SIS_REV_900B)
764 sis_setmulti_ns(struct sis_softc *sc)
767 struct ifmultiaddr *ifma;
768 uint32_t h = 0, i, filtsave;
771 ifp = &sc->arpcom.ac_if;
773 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
774 SIS_CLRBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_MCHASH);
775 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLMULTI);
780 * We have to explicitly enable the multicast hash table
781 * on the NatSemi chip if we want to use it, which we do.
783 SIS_SETBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_MCHASH);
784 SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLMULTI);
786 filtsave = CSR_READ_4(sc, SIS_RXFILT_CTL);
788 /* first, zot all the existing hash bits */
789 for (i = 0; i < 32; i++) {
790 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_FMEM_LO + (i*2));
791 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 0);
794 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
795 if (ifma->ifma_addr->sa_family != AF_LINK)
798 LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
801 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_FMEM_LO + index);
804 SIS_SETBIT(sc, SIS_RXFILT_DATA, (1 << bit));
807 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave);
811 sis_setmulti_sis(struct sis_softc *sc)
814 struct ifmultiaddr *ifma;
815 uint32_t h, i, n, ctl;
818 ifp = &sc->arpcom.ac_if;
820 /* hash table size */
821 if (sc->sis_rev >= SIS_REV_635 || sc->sis_rev == SIS_REV_900B)
826 ctl = CSR_READ_4(sc, SIS_RXFILT_CTL) & SIS_RXFILTCTL_ENABLE;
828 if (ifp->if_flags & IFF_BROADCAST)
829 ctl |= SIS_RXFILTCTL_BROAD;
831 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
832 ctl |= SIS_RXFILTCTL_ALLMULTI;
833 if (ifp->if_flags & IFF_PROMISC)
834 ctl |= SIS_RXFILTCTL_BROAD|SIS_RXFILTCTL_ALLPHYS;
835 for (i = 0; i < n; i++)
838 for (i = 0; i < n; i++)
841 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
842 if (ifma->ifma_addr->sa_family != AF_LINK)
845 LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
846 hashes[h >> 4] |= 1 << (h & 0xf);
850 ctl |= SIS_RXFILTCTL_ALLMULTI;
851 for (i = 0; i < n; i++)
856 for (i = 0; i < n; i++) {
857 CSR_WRITE_4(sc, SIS_RXFILT_CTL, (4 + i) << 16);
858 CSR_WRITE_4(sc, SIS_RXFILT_DATA, hashes[i]);
861 CSR_WRITE_4(sc, SIS_RXFILT_CTL, ctl);
865 sis_reset(struct sis_softc *sc)
867 struct ifnet *ifp = &sc->arpcom.ac_if;
870 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RESET);
872 for (i = 0; i < SIS_TIMEOUT; i++) {
873 if (!(CSR_READ_4(sc, SIS_CSR) & SIS_CSR_RESET))
877 if (i == SIS_TIMEOUT)
878 if_printf(ifp, "reset never completed\n");
880 /* Wait a little while for the chip to get its brains in order. */
884 * If this is a NetSemi chip, make sure to clear
887 if (sc->sis_type == SIS_TYPE_83815) {
888 CSR_WRITE_4(sc, NS_CLKRUN, NS_CLKRUN_PMESTS);
889 CSR_WRITE_4(sc, NS_CLKRUN, 0);
894 * Probe for an SiS chip. Check the PCI vendor and device
895 * IDs against our list and return a device name if we find a match.
898 sis_probe(device_t dev)
904 while(t->sis_name != NULL) {
905 if ((pci_get_vendor(dev) == t->sis_vid) &&
906 (pci_get_device(dev) == t->sis_did)) {
907 device_set_desc(dev, t->sis_name);
917 * Attach the interface. Allocate softc structures, do ifmedia
918 * setup and ethernet/BPF attach.
921 sis_attach(device_t dev)
923 uint8_t eaddr[ETHER_ADDR_LEN];
925 struct sis_softc *sc;
927 int error, rid, waittime;
929 error = waittime = 0;
930 sc = device_get_softc(dev);
932 if (pci_get_device(dev) == PCI_PRODUCT_SIS_900)
933 sc->sis_type = SIS_TYPE_900;
934 if (pci_get_device(dev) == PCI_PRODUCT_SIS_7016)
935 sc->sis_type = SIS_TYPE_7016;
936 if (pci_get_vendor(dev) == PCI_VENDOR_NS)
937 sc->sis_type = SIS_TYPE_83815;
939 sc->sis_rev = pci_read_config(dev, PCIR_REVID, 1);
942 * Handle power management nonsense.
945 command = pci_read_config(dev, SIS_PCI_CAPID, 4) & 0x000000FF;
946 if (command == 0x01) {
948 command = pci_read_config(dev, SIS_PCI_PWRMGMTCTRL, 4);
949 if (command & SIS_PSTATE_MASK) {
950 uint32_t iobase, membase, irq;
952 /* Save important PCI config data. */
953 iobase = pci_read_config(dev, SIS_PCI_LOIO, 4);
954 membase = pci_read_config(dev, SIS_PCI_LOMEM, 4);
955 irq = pci_read_config(dev, SIS_PCI_INTLINE, 4);
957 /* Reset the power state. */
958 device_printf(dev, "chip is in D%d power mode "
959 "-- setting to D0\n", command & SIS_PSTATE_MASK);
960 command &= 0xFFFFFFFC;
961 pci_write_config(dev, SIS_PCI_PWRMGMTCTRL, command, 4);
963 /* Restore PCI config data. */
964 pci_write_config(dev, SIS_PCI_LOIO, iobase, 4);
965 pci_write_config(dev, SIS_PCI_LOMEM, membase, 4);
966 pci_write_config(dev, SIS_PCI_INTLINE, irq, 4);
971 * Map control/status registers.
973 command = pci_read_config(dev, PCIR_COMMAND, 4);
974 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN);
975 pci_write_config(dev, PCIR_COMMAND, command, 4);
976 command = pci_read_config(dev, PCIR_COMMAND, 4);
978 #ifdef SIS_USEIOSPACE
979 if (!(command & PCIM_CMD_PORTEN)) {
980 device_printf(dev, "failed to enable I/O ports!\n");
985 if (!(command & PCIM_CMD_MEMEN)) {
986 device_printf(dev, "failed to enable memory mapping!\n");
993 sc->sis_res = bus_alloc_resource_any(dev, SIS_RES, &rid, RF_ACTIVE);
995 if (sc->sis_res == NULL) {
996 device_printf(dev, "couldn't map ports/memory\n");
1001 sc->sis_btag = rman_get_bustag(sc->sis_res);
1002 sc->sis_bhandle = rman_get_bushandle(sc->sis_res);
1004 /* Allocate interrupt */
1006 sc->sis_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
1007 RF_SHAREABLE | RF_ACTIVE);
1009 if (sc->sis_irq == NULL) {
1010 device_printf(dev, "couldn't map interrupt\n");
1015 /* Reset the adapter. */
1018 if (sc->sis_type == SIS_TYPE_900 &&
1019 (sc->sis_rev == SIS_REV_635 ||
1020 sc->sis_rev == SIS_REV_900B)) {
1021 SIO_SET(SIS_CFG_RND_CNT);
1022 SIO_SET(SIS_CFG_PERR_DETECT);
1026 * Get station address from the EEPROM.
1028 switch (pci_get_vendor(dev)) {
1031 * Reading the MAC address out of the EEPROM on
1032 * the NatSemi chip takes a bit more work than
1033 * you'd expect. The address spans 4 16-bit words,
1034 * with the first word containing only a single bit.
1035 * You have to shift everything over one bit to
1036 * get it aligned properly. Also, the bits are
1037 * stored backwards (the LSB is really the MSB,
1038 * and so on) so you have to reverse them in order
1039 * to get the MAC address into the form we want.
1040 * Why? Who the hell knows.
1045 sis_read_eeprom(sc, (caddr_t)&tmp,
1046 NS_EE_NODEADDR, 4, 0);
1048 /* Shift everything over one bit. */
1049 tmp[3] = tmp[3] >> 1;
1050 tmp[3] |= tmp[2] << 15;
1051 tmp[2] = tmp[2] >> 1;
1052 tmp[2] |= tmp[1] << 15;
1053 tmp[1] = tmp[1] >> 1;
1054 tmp[1] |= tmp[0] << 15;
1056 /* Now reverse all the bits. */
1057 tmp[3] = sis_reverse(tmp[3]);
1058 tmp[2] = sis_reverse(tmp[2]);
1059 tmp[1] = sis_reverse(tmp[1]);
1061 bcopy((char *)&tmp[1], eaddr, ETHER_ADDR_LEN);
1064 case PCI_VENDOR_SIS:
1068 * If this is a SiS 630E chipset with an embedded
1069 * SiS 900 controller, we have to read the MAC address
1070 * from the APC CMOS RAM. Our method for doing this
1071 * is very ugly since we have to reach out and grab
1072 * ahold of hardware for which we cannot properly
1073 * allocate resources. This code is only compiled on
1074 * the x86_64 architecture since the SiS 630E chipset
1075 * is for x86 motherboards only. Note that there are
1076 * a lot of magic numbers in this hack. These are
1077 * taken from SiS's Linux driver. I'd like to replace
1078 * them with proper symbolic definitions, but that
1079 * requires some datasheets that I don't have access
1082 if (sc->sis_rev == SIS_REV_630S ||
1083 sc->sis_rev == SIS_REV_630E ||
1084 sc->sis_rev == SIS_REV_630EA1)
1085 sis_read_cmos(sc, dev, (caddr_t)&eaddr, 0x9, 6);
1087 else if (sc->sis_rev == SIS_REV_635 ||
1088 sc->sis_rev == SIS_REV_630ET)
1089 sis_read_mac(sc, dev, (caddr_t)&eaddr);
1090 else if (sc->sis_rev == SIS_REV_96x) {
1092 * Allow to read EEPROM from LAN. It is shared
1093 * between a 1394 controller and the NIC and each
1094 * time we access it, we need to set SIS_EECMD_REQ.
1096 SIO_SET(SIS_EECMD_REQ);
1097 for (waittime = 0; waittime < SIS_TIMEOUT;
1099 /* Force EEPROM to idle state. */
1100 sis_eeprom_idle(sc);
1101 if (CSR_READ_4(sc, SIS_EECTL) & SIS_EECMD_GNT) {
1102 sis_read_eeprom(sc, (caddr_t)&eaddr,
1103 SIS_EE_NODEADDR, 3, 0);
1109 * Set SIS_EECTL_CLK to high, so a other master
1110 * can operate on the i2c bus.
1112 SIO_SET(SIS_EECTL_CLK);
1113 /* Refuse EEPROM access by LAN */
1114 SIO_SET(SIS_EECMD_DONE);
1117 sis_read_eeprom(sc, (caddr_t)&eaddr,
1118 SIS_EE_NODEADDR, 3, 0);
1122 callout_init(&sc->sis_timer);
1124 error = sis_dma_alloc(dev);
1128 ifp = &sc->arpcom.ac_if;
1130 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1131 ifp->if_mtu = ETHERMTU;
1132 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1133 ifp->if_ioctl = sis_ioctl;
1134 ifp->if_start = sis_start;
1135 ifp->if_watchdog = sis_watchdog;
1136 ifp->if_init = sis_init;
1137 ifp->if_baudrate = 10000000;
1138 ifq_set_maxlen(&ifp->if_snd, SIS_TX_LIST_CNT - 1);
1139 ifq_set_ready(&ifp->if_snd);
1140 #ifdef IFPOLL_ENABLE
1141 ifp->if_npoll = sis_npoll;
1143 ifp->if_capenable = ifp->if_capabilities;
1148 if (mii_phy_probe(dev, &sc->sis_miibus,
1149 sis_ifmedia_upd, sis_ifmedia_sts)) {
1150 device_printf(dev, "MII without any PHY!\n");
1156 * Call MI attach routine.
1158 ether_ifattach(ifp, eaddr, NULL);
1160 #ifdef IFPOLL_ENABLE
1161 ifpoll_compat_setup(&sc->sis_npoll, NULL, NULL, device_get_unit(dev),
1162 ifp->if_serializer);
1166 * Tell the upper layer(s) we support long frames.
1168 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
1170 ifq_set_cpuid(&ifp->if_snd, rman_get_cpuid(sc->sis_irq));
1172 error = bus_setup_intr(dev, sc->sis_irq, INTR_MPSAFE,
1175 ifp->if_serializer);
1178 device_printf(dev, "couldn't set up irq\n");
1179 ether_ifdetach(ifp);
1191 * Shutdown hardware and free up resources. It is called in both the error case
1192 * and the normal detach case so it needs to be careful about only freeing
1193 * resources that have actually been allocated.
1196 sis_detach(device_t dev)
1198 struct sis_softc *sc = device_get_softc(dev);
1199 struct ifnet *ifp = &sc->arpcom.ac_if;
1202 if (device_is_attached(dev)) {
1203 lwkt_serialize_enter(ifp->if_serializer);
1206 bus_teardown_intr(dev, sc->sis_irq, sc->sis_intrhand);
1207 lwkt_serialize_exit(ifp->if_serializer);
1209 ether_ifdetach(ifp);
1212 device_delete_child(dev, sc->sis_miibus);
1213 bus_generic_detach(dev);
1216 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sis_irq);
1218 bus_release_resource(dev, SIS_RES, SIS_RID, sc->sis_res);
1226 * Initialize the transmit descriptors.
1229 sis_list_tx_init(struct sis_softc *sc)
1231 struct sis_list_data *ld = &sc->sis_ldata;
1232 struct sis_chain_data *cd = &sc->sis_cdata;
1235 for (i = 0; i < SIS_TX_LIST_CNT; i++) {
1239 * Link the TX desc together
1241 nexti = (i == (SIS_TX_LIST_CNT - 1)) ? 0 : i+1;
1242 paddr = ld->sis_tx_paddr + (nexti * sizeof(struct sis_desc));
1243 ld->sis_tx_list[i].sis_next = paddr;
1245 cd->sis_tx_prod = cd->sis_tx_cons = cd->sis_tx_cnt = 0;
1251 * Initialize the RX descriptors and allocate mbufs for them. Note that
1252 * we arrange the descriptors in a closed ring, so that the last descriptor
1253 * points back to the first.
1256 sis_list_rx_init(struct sis_softc *sc)
1258 struct sis_list_data *ld = &sc->sis_ldata;
1259 struct sis_chain_data *cd = &sc->sis_cdata;
1262 for (i = 0; i < SIS_RX_LIST_CNT; i++) {
1266 error = sis_newbuf(sc, i, 1);
1271 * Link the RX desc together
1273 nexti = (i == (SIS_RX_LIST_CNT - 1)) ? 0 : i+1;
1274 paddr = ld->sis_rx_paddr + (nexti * sizeof(struct sis_desc));
1275 ld->sis_rx_list[i].sis_next = paddr;
1277 cd->sis_rx_prod = 0;
1283 * Initialize an RX descriptor and attach an MBUF cluster.
1286 sis_newbuf(struct sis_softc *sc, int idx, int init)
1288 struct sis_chain_data *cd = &sc->sis_cdata;
1289 struct sis_rx_data *rd = &cd->sis_rx_data[idx];
1290 bus_dma_segment_t seg;
1295 m = m_getcl(init ? M_WAITOK : M_NOWAIT, MT_DATA, M_PKTHDR);
1298 if_printf(&sc->arpcom.ac_if, "can't alloc RX mbuf\n");
1301 m->m_len = m->m_pkthdr.len = MCLBYTES;
1303 /* Try loading the mbuf into tmp DMA map */
1304 error = bus_dmamap_load_mbuf_segment(cd->sis_rxbuf_tag,
1305 cd->sis_rx_tmpmap, m, &seg, 1, &nseg, BUS_DMA_NOWAIT);
1309 if_printf(&sc->arpcom.ac_if, "can't load RX mbuf\n");
1313 /* Unload the currently loaded mbuf */
1314 if (rd->sis_mbuf != NULL) {
1315 bus_dmamap_sync(cd->sis_rxbuf_tag, rd->sis_map,
1316 BUS_DMASYNC_POSTREAD);
1317 bus_dmamap_unload(cd->sis_rxbuf_tag, rd->sis_map);
1321 map = cd->sis_rx_tmpmap;
1322 cd->sis_rx_tmpmap = rd->sis_map;
1325 /* Save necessary information */
1327 rd->sis_paddr = seg.ds_addr;
1329 sis_setup_rxdesc(sc, idx);
1334 sis_setup_rxdesc(struct sis_softc *sc, int idx)
1336 struct sis_desc *c = &sc->sis_ldata.sis_rx_list[idx];
1338 /* Setup the RX desc */
1339 c->sis_ctl = SIS_RXLEN;
1340 c->sis_ptr = sc->sis_cdata.sis_rx_data[idx].sis_paddr;
1344 * A frame has been uploaded: pass the resulting mbuf chain up to
1345 * the higher level protocols.
1348 sis_rxeof(struct sis_softc *sc)
1350 struct ifnet *ifp = &sc->arpcom.ac_if;
1351 int i, total_len = 0;
1354 i = sc->sis_cdata.sis_rx_prod;
1355 while (SIS_OWNDESC(&sc->sis_ldata.sis_rx_list[i])) {
1356 struct sis_desc *cur_rx;
1357 struct sis_rx_data *rd;
1361 #ifdef IFPOLL_ENABLE
1362 if (ifp->if_flags & IFF_NPOLLING) {
1363 if (sc->rxcycles <= 0)
1367 #endif /* IFPOLL_ENABLE */
1369 cur_rx = &sc->sis_ldata.sis_rx_list[idx];
1370 rd = &sc->sis_cdata.sis_rx_data[idx];
1372 rxstat = cur_rx->sis_rxstat;
1373 total_len = SIS_RXBYTES(cur_rx);
1377 SIS_INC(i, SIS_RX_LIST_CNT);
1380 * If an error occurs, update stats, clear the
1381 * status word and leave the mbuf cluster in place:
1382 * it should simply get re-used next time this descriptor
1383 * comes up in the ring.
1385 if (!(rxstat & SIS_CMDSTS_PKT_OK)) {
1386 IFNET_STAT_INC(ifp, ierrors, 1);
1387 if (rxstat & SIS_RXSTAT_COLL)
1388 IFNET_STAT_INC(ifp, collisions, 1);
1389 sis_setup_rxdesc(sc, idx);
1393 /* No errors; receive the packet. */
1394 if (sis_newbuf(sc, idx, 0) == 0) {
1395 m->m_pkthdr.len = m->m_len = total_len;
1396 m->m_pkthdr.rcvif = ifp;
1398 IFNET_STAT_INC(ifp, ierrors, 1);
1399 sis_setup_rxdesc(sc, idx);
1403 IFNET_STAT_INC(ifp, ipackets, 1);
1404 ifp->if_input(ifp, m, NULL, -1);
1406 sc->sis_cdata.sis_rx_prod = i;
1410 sis_rxeoc(struct sis_softc *sc)
1417 * A frame was downloaded to the chip. It's safe for us to clean up
1422 sis_txeof(struct sis_softc *sc)
1424 struct ifnet *ifp = &sc->arpcom.ac_if;
1425 struct sis_chain_data *cd = &sc->sis_cdata;
1429 * Go through our tx list and free mbufs for those
1430 * frames that have been transmitted.
1432 for (idx = sc->sis_cdata.sis_tx_cons; sc->sis_cdata.sis_tx_cnt > 0;
1433 sc->sis_cdata.sis_tx_cnt--, SIS_INC(idx, SIS_TX_LIST_CNT) ) {
1434 struct sis_desc *cur_tx;
1435 struct sis_tx_data *td;
1437 cur_tx = &sc->sis_ldata.sis_tx_list[idx];
1438 td = &cd->sis_tx_data[idx];
1440 if (SIS_OWNDESC(cur_tx))
1443 if (cur_tx->sis_ctl & SIS_CMDSTS_MORE)
1446 if (!(cur_tx->sis_ctl & SIS_CMDSTS_PKT_OK)) {
1447 IFNET_STAT_INC(ifp, oerrors, 1);
1448 if (cur_tx->sis_txstat & SIS_TXSTAT_EXCESSCOLLS)
1449 IFNET_STAT_INC(ifp, collisions, 1);
1450 if (cur_tx->sis_txstat & SIS_TXSTAT_OUTOFWINCOLL)
1451 IFNET_STAT_INC(ifp, collisions, 1);
1454 IFNET_STAT_INC(ifp, collisions,
1455 (cur_tx->sis_txstat & SIS_TXSTAT_COLLCNT) >> 16);
1457 IFNET_STAT_INC(ifp, opackets, 1);
1458 if (td->sis_mbuf != NULL) {
1459 bus_dmamap_unload(cd->sis_txbuf_tag, td->sis_map);
1460 m_freem(td->sis_mbuf);
1461 td->sis_mbuf = NULL;
1465 if (idx != sc->sis_cdata.sis_tx_cons) {
1466 /* we freed up some buffers */
1467 sc->sis_cdata.sis_tx_cons = idx;
1470 if (cd->sis_tx_cnt == 0)
1472 if (!SIS_IS_OACTIVE(sc))
1473 ifq_clr_oactive(&ifp->if_snd);
1479 struct sis_softc *sc = xsc;
1480 struct mii_data *mii;
1481 struct ifnet *ifp = &sc->arpcom.ac_if;
1483 lwkt_serialize_enter(ifp->if_serializer);
1485 mii = device_get_softc(sc->sis_miibus);
1488 if (!sc->sis_link) {
1490 if (mii->mii_media_status & IFM_ACTIVE &&
1491 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE)
1493 if (!ifq_is_empty(&ifp->if_snd))
1497 callout_reset(&sc->sis_timer, hz, sis_tick, sc);
1498 lwkt_serialize_exit(ifp->if_serializer);
1501 #ifdef IFPOLL_ENABLE
1504 sis_npoll_compat(struct ifnet *ifp, void *arg __unused, int count)
1506 struct sis_softc *sc = ifp->if_softc;
1508 ASSERT_SERIALIZED(ifp->if_serializer);
1511 * On the sis, reading the status register also clears it.
1512 * So before returning to intr mode we must make sure that all
1513 * possible pending sources of interrupts have been served.
1514 * In practice this means run to completion the *eof routines,
1515 * and then call the interrupt routine
1517 sc->rxcycles = count;
1520 if (!ifq_is_empty(&ifp->if_snd))
1523 if (sc->sis_npoll.ifpc_stcount-- == 0) {
1526 sc->sis_npoll.ifpc_stcount = sc->sis_npoll.ifpc_stfrac;
1528 /* Reading the ISR register clears all interrupts. */
1529 status = CSR_READ_4(sc, SIS_ISR);
1531 if (status & (SIS_ISR_RX_ERR|SIS_ISR_RX_OFLOW))
1534 if (status & (SIS_ISR_RX_IDLE))
1535 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE);
1537 if (status & SIS_ISR_SYSERR) {
1545 sis_npoll(struct ifnet *ifp, struct ifpoll_info *info)
1547 struct sis_softc *sc = ifp->if_softc;
1549 ASSERT_SERIALIZED(ifp->if_serializer);
1552 int cpuid = sc->sis_npoll.ifpc_cpuid;
1554 info->ifpi_rx[cpuid].poll_func = sis_npoll_compat;
1555 info->ifpi_rx[cpuid].arg = NULL;
1556 info->ifpi_rx[cpuid].serializer = ifp->if_serializer;
1558 if (ifp->if_flags & IFF_RUNNING) {
1559 /* disable interrupts */
1560 CSR_WRITE_4(sc, SIS_IER, 0);
1561 sc->sis_npoll.ifpc_stcount = 0;
1563 ifq_set_cpuid(&ifp->if_snd, cpuid);
1565 if (ifp->if_flags & IFF_RUNNING) {
1566 /* enable interrupts */
1567 CSR_WRITE_4(sc, SIS_IER, 1);
1569 ifq_set_cpuid(&ifp->if_snd, rman_get_cpuid(sc->sis_irq));
1573 #endif /* IFPOLL_ENABLE */
1578 struct sis_softc *sc;
1583 ifp = &sc->arpcom.ac_if;
1585 /* Supress unwanted interrupts */
1586 if (!(ifp->if_flags & IFF_UP)) {
1591 /* Disable interrupts. */
1592 CSR_WRITE_4(sc, SIS_IER, 0);
1595 /* Reading the ISR register clears all interrupts. */
1596 status = CSR_READ_4(sc, SIS_ISR);
1598 if ((status & SIS_INTRS) == 0)
1602 (SIS_ISR_TX_DESC_OK | SIS_ISR_TX_ERR | SIS_ISR_TX_OK |
1607 (SIS_ISR_RX_DESC_OK | SIS_ISR_RX_OK | SIS_ISR_RX_IDLE))
1610 if (status & (SIS_ISR_RX_ERR | SIS_ISR_RX_OFLOW))
1613 if (status & (SIS_ISR_RX_IDLE))
1614 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE);
1616 if (status & SIS_ISR_SYSERR) {
1622 /* Re-enable interrupts. */
1623 CSR_WRITE_4(sc, SIS_IER, 1);
1625 if (!ifq_is_empty(&ifp->if_snd))
1630 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
1631 * pointers to the fragment pointers.
1634 sis_encap(struct sis_softc *sc, struct mbuf **m_head, uint32_t *txidx)
1636 struct sis_chain_data *cd = &sc->sis_cdata;
1637 struct sis_list_data *ld = &sc->sis_ldata;
1638 bus_dma_segment_t segs[SIS_NSEGS];
1640 int frag, cur, maxsegs, nsegs, error, i;
1642 maxsegs = SIS_TX_LIST_CNT - SIS_NSEGS_RESERVED - cd->sis_tx_cnt;
1643 KASSERT(maxsegs >= 1, ("not enough TX descs"));
1644 if (maxsegs > SIS_NSEGS)
1645 maxsegs = SIS_NSEGS;
1647 map = cd->sis_tx_data[*txidx].sis_map;
1648 error = bus_dmamap_load_mbuf_defrag(cd->sis_txbuf_tag, map, m_head,
1649 segs, maxsegs, &nsegs, BUS_DMA_NOWAIT);
1655 bus_dmamap_sync(cd->sis_txbuf_tag, map, BUS_DMASYNC_PREWRITE);
1657 cur = frag = *txidx;
1658 for (i = 0; i < nsegs; ++i) {
1659 struct sis_desc *f = &ld->sis_tx_list[frag];
1661 f->sis_ctl = SIS_CMDSTS_MORE | segs[i].ds_len;
1662 f->sis_ptr = segs[i].ds_addr;
1664 f->sis_ctl |= SIS_CMDSTS_OWN;
1667 SIS_INC(frag, SIS_TX_LIST_CNT);
1669 ld->sis_tx_list[cur].sis_ctl &= ~SIS_CMDSTS_MORE;
1670 ld->sis_tx_list[*txidx].sis_ctl |= SIS_CMDSTS_OWN;
1673 cd->sis_tx_data[*txidx].sis_map = cd->sis_tx_data[cur].sis_map;
1674 cd->sis_tx_data[cur].sis_map = map;
1676 cd->sis_tx_data[cur].sis_mbuf = *m_head;
1678 cd->sis_tx_cnt += nsegs;
1685 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
1686 * to the mbuf data regions directly in the transmit lists. We also save a
1687 * copy of the pointers since the transmit list fragment pointers are
1688 * physical addresses.
1692 sis_start(struct ifnet *ifp, struct ifaltq_subque *ifsq)
1694 struct sis_softc *sc = ifp->if_softc;
1695 int need_trans, error;
1698 ASSERT_ALTQ_SQ_DEFAULT(ifp, ifsq);
1700 if (!sc->sis_link) {
1701 ifq_purge(&ifp->if_snd);
1705 if ((ifp->if_flags & IFF_RUNNING) == 0 || ifq_is_oactive(&ifp->if_snd))
1708 idx = sc->sis_cdata.sis_tx_prod;
1711 while (sc->sis_cdata.sis_tx_data[idx].sis_mbuf == NULL) {
1712 struct mbuf *m_head;
1715 * If there's no way we can send any packets, return now.
1717 if (SIS_IS_OACTIVE(sc)) {
1718 ifq_set_oactive(&ifp->if_snd);
1722 m_head = ifq_dequeue(&ifp->if_snd);
1726 error = sis_encap(sc, &m_head, &idx);
1728 IFNET_STAT_INC(ifp, oerrors, 1);
1729 if (sc->sis_cdata.sis_tx_cnt == 0) {
1732 ifq_set_oactive(&ifp->if_snd);
1739 * If there's a BPF listener, bounce a copy of this frame
1742 BPF_MTAP(ifp, m_head);
1749 sc->sis_cdata.sis_tx_prod = idx;
1750 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_TX_ENABLE);
1753 * Set a timeout in case the chip goes out to lunch.
1761 struct sis_softc *sc = xsc;
1762 struct ifnet *ifp = &sc->arpcom.ac_if;
1763 struct mii_data *mii;
1766 * Cancel pending I/O and free all RX/TX buffers.
1770 mii = device_get_softc(sc->sis_miibus);
1772 /* Set MAC address */
1773 if (sc->sis_type == SIS_TYPE_83815) {
1774 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR0);
1775 CSR_WRITE_4(sc, SIS_RXFILT_DATA,
1776 ((uint16_t *)sc->arpcom.ac_enaddr)[0]);
1777 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR1);
1778 CSR_WRITE_4(sc, SIS_RXFILT_DATA,
1779 ((uint16_t *)sc->arpcom.ac_enaddr)[1]);
1780 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR2);
1781 CSR_WRITE_4(sc, SIS_RXFILT_DATA,
1782 ((uint16_t *)sc->arpcom.ac_enaddr)[2]);
1784 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR0);
1785 CSR_WRITE_4(sc, SIS_RXFILT_DATA,
1786 ((uint16_t *)sc->arpcom.ac_enaddr)[0]);
1787 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR1);
1788 CSR_WRITE_4(sc, SIS_RXFILT_DATA,
1789 ((uint16_t *)sc->arpcom.ac_enaddr)[1]);
1790 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR2);
1791 CSR_WRITE_4(sc, SIS_RXFILT_DATA,
1792 ((uint16_t *)sc->arpcom.ac_enaddr)[2]);
1795 /* Init circular RX list. */
1796 if (sis_list_rx_init(sc)) {
1797 if_printf(ifp, "initialization failed: "
1798 "no memory for rx buffers\n");
1804 * Init tx descriptors.
1806 sis_list_tx_init(sc);
1809 * For the NatSemi chip, we have to explicitly enable the
1810 * reception of ARP frames, as well as turn on the 'perfect
1811 * match' filter where we store the station address, otherwise
1812 * we won't receive unicasts meant for this host.
1814 if (sc->sis_type == SIS_TYPE_83815) {
1815 SIS_SETBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_ARP);
1816 SIS_SETBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_PERFECT);
1819 /* If we want promiscuous mode, set the allframes bit. */
1820 if (ifp->if_flags & IFF_PROMISC)
1821 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLPHYS);
1823 SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLPHYS);
1826 * Set the capture broadcast bit to capture broadcast frames.
1828 if (ifp->if_flags & IFF_BROADCAST)
1829 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_BROAD);
1831 SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_BROAD);
1834 * Load the multicast filter.
1836 if (sc->sis_type == SIS_TYPE_83815)
1837 sis_setmulti_ns(sc);
1839 sis_setmulti_sis(sc);
1841 /* Turn the receive filter on */
1842 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ENABLE);
1845 * Load the address of the RX and TX lists.
1847 CSR_WRITE_4(sc, SIS_RX_LISTPTR, sc->sis_ldata.sis_rx_paddr);
1848 CSR_WRITE_4(sc, SIS_TX_LISTPTR, sc->sis_ldata.sis_tx_paddr);
1850 /* SIS_CFG_EDB_MASTER_EN indicates the EDB bus is used instead of
1851 * the PCI bus. When this bit is set, the Max DMA Burst Size
1852 * for TX/RX DMA should be no larger than 16 double words.
1854 if (CSR_READ_4(sc, SIS_CFG) & SIS_CFG_EDB_MASTER_EN)
1855 CSR_WRITE_4(sc, SIS_RX_CFG, SIS_RXCFG64);
1857 CSR_WRITE_4(sc, SIS_RX_CFG, SIS_RXCFG256);
1859 /* Accept Long Packets for VLAN support */
1860 SIS_SETBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_JABBER);
1862 /* Set TX configuration */
1863 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_10_T)
1864 CSR_WRITE_4(sc, SIS_TX_CFG, SIS_TXCFG_10);
1866 CSR_WRITE_4(sc, SIS_TX_CFG, SIS_TXCFG_100);
1868 /* Set full/half duplex mode. */
1869 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
1870 SIS_SETBIT(sc, SIS_TX_CFG,
1871 (SIS_TXCFG_IGN_HBEAT|SIS_TXCFG_IGN_CARR));
1872 SIS_SETBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_TXPKTS);
1874 SIS_CLRBIT(sc, SIS_TX_CFG,
1875 (SIS_TXCFG_IGN_HBEAT|SIS_TXCFG_IGN_CARR));
1876 SIS_CLRBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_TXPKTS);
1880 * Enable interrupts.
1882 CSR_WRITE_4(sc, SIS_IMR, SIS_INTRS);
1883 #ifdef IFPOLL_ENABLE
1885 * ... only enable interrupts if we are not polling, make sure
1886 * they are off otherwise.
1888 if (ifp->if_flags & IFF_NPOLLING) {
1889 CSR_WRITE_4(sc, SIS_IER, 0);
1890 sc->sis_npoll.ifpc_stcount = 0;
1892 #endif /* IFPOLL_ENABLE */
1893 CSR_WRITE_4(sc, SIS_IER, 1);
1895 /* Enable receiver and transmitter. */
1896 SIS_CLRBIT(sc, SIS_CSR, SIS_CSR_TX_DISABLE|SIS_CSR_RX_DISABLE);
1897 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE);
1904 * Page 75 of the DP83815 manual recommends the
1905 * following register settings "for optimum
1906 * performance." Note however that at least three
1907 * of the registers are listed as "reserved" in
1908 * the register map, so who knows what they do.
1910 if (sc->sis_type == SIS_TYPE_83815) {
1911 CSR_WRITE_4(sc, NS_PHY_PAGE, 0x0001);
1912 CSR_WRITE_4(sc, NS_PHY_CR, 0x189C);
1913 CSR_WRITE_4(sc, NS_PHY_TDATA, 0x0000);
1914 CSR_WRITE_4(sc, NS_PHY_DSPCFG, 0x5040);
1915 CSR_WRITE_4(sc, NS_PHY_SDCFG, 0x008C);
1918 ifp->if_flags |= IFF_RUNNING;
1919 ifq_clr_oactive(&ifp->if_snd);
1921 callout_reset(&sc->sis_timer, hz, sis_tick, sc);
1925 * Set media options.
1928 sis_ifmedia_upd(struct ifnet *ifp)
1930 struct sis_softc *sc;
1931 struct mii_data *mii;
1935 mii = device_get_softc(sc->sis_miibus);
1937 if (mii->mii_instance) {
1938 struct mii_softc *miisc;
1939 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
1940 mii_phy_reset(miisc);
1948 * Report current media status.
1951 sis_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
1953 struct sis_softc *sc;
1954 struct mii_data *mii;
1958 mii = device_get_softc(sc->sis_miibus);
1960 ifmr->ifm_active = mii->mii_media_active;
1961 ifmr->ifm_status = mii->mii_media_status;
1965 sis_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
1967 struct sis_softc *sc = ifp->if_softc;
1968 struct ifreq *ifr = (struct ifreq *) data;
1969 struct mii_data *mii;
1974 if (ifp->if_flags & IFF_UP) {
1977 if (ifp->if_flags & IFF_RUNNING)
1984 if (sc->sis_type == SIS_TYPE_83815)
1985 sis_setmulti_ns(sc);
1987 sis_setmulti_sis(sc);
1992 mii = device_get_softc(sc->sis_miibus);
1993 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
1996 error = ether_ioctl(ifp, command, data);
2003 sis_watchdog(struct ifnet *ifp)
2005 struct sis_softc *sc;
2009 IFNET_STAT_INC(ifp, oerrors, 1);
2010 if_printf(ifp, "watchdog timeout\n");
2016 if (!ifq_is_empty(&ifp->if_snd))
2021 * Stop the adapter and free any mbufs allocated to the
2025 sis_stop(struct sis_softc *sc)
2027 struct ifnet *ifp = &sc->arpcom.ac_if;
2028 struct sis_list_data *ld = &sc->sis_ldata;
2029 struct sis_chain_data *cd = &sc->sis_cdata;
2032 callout_stop(&sc->sis_timer);
2034 ifp->if_flags &= ~IFF_RUNNING;
2035 ifq_clr_oactive(&ifp->if_snd);
2038 CSR_WRITE_4(sc, SIS_IER, 0);
2039 CSR_WRITE_4(sc, SIS_IMR, 0);
2040 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_TX_DISABLE|SIS_CSR_RX_DISABLE);
2042 CSR_WRITE_4(sc, SIS_TX_LISTPTR, 0);
2043 CSR_WRITE_4(sc, SIS_RX_LISTPTR, 0);
2048 * Free data in the RX lists.
2050 for (i = 0; i < SIS_RX_LIST_CNT; i++) {
2051 struct sis_rx_data *rd = &cd->sis_rx_data[i];
2053 if (rd->sis_mbuf != NULL) {
2054 bus_dmamap_unload(cd->sis_rxbuf_tag, rd->sis_map);
2055 m_freem(rd->sis_mbuf);
2056 rd->sis_mbuf = NULL;
2059 bzero(ld->sis_rx_list, SIS_RX_LIST_SZ);
2062 * Free the TX list buffers.
2064 for (i = 0; i < SIS_TX_LIST_CNT; i++) {
2065 struct sis_tx_data *td = &cd->sis_tx_data[i];
2067 if (td->sis_mbuf != NULL) {
2068 bus_dmamap_unload(cd->sis_txbuf_tag, td->sis_map);
2069 m_freem(td->sis_mbuf);
2070 td->sis_mbuf = NULL;
2073 bzero(ld->sis_tx_list, SIS_TX_LIST_SZ);
2077 * Stop all chip I/O so that the kernel's probe routines don't
2078 * get confused by errant DMAs when rebooting.
2081 sis_shutdown(device_t dev)
2083 struct sis_softc *sc;
2086 sc = device_get_softc(dev);
2087 ifp = &sc->arpcom.ac_if;
2088 lwkt_serialize_enter(ifp->if_serializer);
2091 lwkt_serialize_exit(ifp->if_serializer);
2095 sis_dma_alloc(device_t dev)
2097 struct sis_softc *sc = device_get_softc(dev);
2098 struct sis_chain_data *cd = &sc->sis_cdata;
2099 struct sis_list_data *ld = &sc->sis_ldata;
2102 /* Create top level DMA tag */
2103 error = bus_dma_tag_create(NULL, /* parent */
2104 1, 0, /* alignment, boundary */
2105 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */
2106 BUS_SPACE_MAXADDR, /* highaddr */
2107 NULL, NULL, /* filter, filterarg */
2108 BUS_SPACE_MAXSIZE_32BIT,/* maxsize */
2110 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */
2112 &sc->sis_parent_tag);
2114 device_printf(dev, "could not create parent DMA tag\n");
2118 /* Allocate RX ring */
2119 ld->sis_rx_list = bus_dmamem_coherent_any(sc->sis_parent_tag,
2120 SIS_RING_ALIGN, SIS_RX_LIST_SZ,
2121 BUS_DMA_WAITOK | BUS_DMA_ZERO,
2122 &ld->sis_rx_tag, &ld->sis_rx_dmamap,
2124 if (ld->sis_rx_list == NULL) {
2125 device_printf(dev, "could not allocate RX ring\n");
2129 /* Allocate TX ring */
2130 ld->sis_tx_list = bus_dmamem_coherent_any(sc->sis_parent_tag,
2131 SIS_RING_ALIGN, SIS_TX_LIST_SZ,
2132 BUS_DMA_WAITOK | BUS_DMA_ZERO,
2133 &ld->sis_tx_tag, &ld->sis_tx_dmamap,
2135 if (ld->sis_tx_list == NULL) {
2136 device_printf(dev, "could not allocate TX ring\n");
2140 /* Create DMA tag for TX mbuf */
2141 error = bus_dma_tag_create(sc->sis_parent_tag,/* parent */
2142 1, 0, /* alignment, boundary */
2143 BUS_SPACE_MAXADDR, /* lowaddr */
2144 BUS_SPACE_MAXADDR, /* highaddr */
2145 NULL, NULL, /* filter, filterarg */
2146 MCLBYTES, /* maxsize */
2147 SIS_NSEGS, /* nsegments */
2148 MCLBYTES, /* maxsegsize */
2149 BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK,/* flags */
2150 &cd->sis_txbuf_tag);
2152 device_printf(dev, "could not create TX buf DMA tag\n");
2156 /* Create DMA maps for TX mbufs */
2157 for (i = 0; i < SIS_TX_LIST_CNT; ++i) {
2158 error = bus_dmamap_create(cd->sis_txbuf_tag, BUS_DMA_WAITOK,
2159 &cd->sis_tx_data[i].sis_map);
2163 for (j = 0; j < i; ++j) {
2164 bus_dmamap_destroy(cd->sis_txbuf_tag,
2165 cd->sis_tx_data[j].sis_map);
2167 bus_dma_tag_destroy(cd->sis_txbuf_tag);
2168 cd->sis_txbuf_tag = NULL;
2170 device_printf(dev, "could not create %dth "
2171 "TX buf DMA map\n", i);
2176 /* Create DMA tag for RX mbuf */
2177 error = bus_dma_tag_create(sc->sis_parent_tag,/* parent */
2178 SIS_RXBUF_ALIGN, 0, /* alignment, boundary */
2179 BUS_SPACE_MAXADDR, /* lowaddr */
2180 BUS_SPACE_MAXADDR, /* highaddr */
2181 NULL, NULL, /* filter, filterarg */
2182 MCLBYTES, /* maxsize */
2184 MCLBYTES, /* maxsegsize */
2185 BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK |
2186 BUS_DMA_ALIGNED, /* flags */
2187 &cd->sis_rxbuf_tag);
2189 device_printf(dev, "could not create RX buf DMA tag\n");
2193 /* Create tmp DMA map for loading RX mbuf */
2194 error = bus_dmamap_create(cd->sis_rxbuf_tag, BUS_DMA_WAITOK,
2195 &cd->sis_rx_tmpmap);
2197 device_printf(dev, "could not create RX buf tmp DMA map\n");
2198 bus_dma_tag_destroy(cd->sis_rxbuf_tag);
2199 cd->sis_rxbuf_tag = NULL;
2203 /* Create DMA maps for RX mbufs */
2204 for (i = 0; i < SIS_RX_LIST_CNT; ++i) {
2205 error = bus_dmamap_create(cd->sis_rxbuf_tag, BUS_DMA_WAITOK,
2206 &cd->sis_rx_data[i].sis_map);
2210 for (j = 0; j < i; ++j) {
2211 bus_dmamap_destroy(cd->sis_rxbuf_tag,
2212 cd->sis_rx_data[j].sis_map);
2214 bus_dmamap_destroy(cd->sis_rxbuf_tag,
2216 bus_dma_tag_destroy(cd->sis_rxbuf_tag);
2217 cd->sis_rxbuf_tag = NULL;
2219 device_printf(dev, "could not create %dth "
2220 "RX buf DMA map\n", i);
2228 sis_dma_free(device_t dev)
2230 struct sis_softc *sc = device_get_softc(dev);
2231 struct sis_list_data *ld = &sc->sis_ldata;
2232 struct sis_chain_data *cd = &sc->sis_cdata;
2236 if (ld->sis_tx_list != NULL) {
2237 bus_dmamap_unload(ld->sis_tx_tag, ld->sis_tx_dmamap);
2238 bus_dmamem_free(ld->sis_tx_tag, ld->sis_tx_list,
2240 bus_dma_tag_destroy(ld->sis_tx_tag);
2244 if (ld->sis_rx_list != NULL) {
2245 bus_dmamap_unload(ld->sis_rx_tag, ld->sis_rx_dmamap);
2246 bus_dmamem_free(ld->sis_rx_tag, ld->sis_rx_list,
2248 bus_dma_tag_destroy(ld->sis_rx_tag);
2251 /* Destroy DMA stuffs for TX mbufs */
2252 if (cd->sis_txbuf_tag != NULL) {
2253 for (i = 0; i < SIS_TX_LIST_CNT; ++i) {
2254 KKASSERT(cd->sis_tx_data[i].sis_mbuf == NULL);
2255 bus_dmamap_destroy(cd->sis_txbuf_tag,
2256 cd->sis_tx_data[i].sis_map);
2258 bus_dma_tag_destroy(cd->sis_txbuf_tag);
2261 /* Destroy DMA stuffs for RX mbufs */
2262 if (cd->sis_rxbuf_tag != NULL) {
2263 for (i = 0; i < SIS_RX_LIST_CNT; ++i) {
2264 KKASSERT(cd->sis_rx_data[i].sis_mbuf == NULL);
2265 bus_dmamap_destroy(cd->sis_rxbuf_tag,
2266 cd->sis_rx_data[i].sis_map);
2268 bus_dmamap_destroy(cd->sis_rxbuf_tag, cd->sis_rx_tmpmap);
2269 bus_dma_tag_destroy(cd->sis_rxbuf_tag);