sys/net/i4b/layer1/itjc/i4b_itjc_pci.c

   1 /*
   2  *   Copyright (c) 2000, 2001 Sergio Prallon. All rights reserved.
   3  *
   4  *   Redistribution and use in source and binary forms, with or without
   5  *   modification, are permitted provided that the following conditions
   6  *   are met:
   7  *
   8  *   1. Redistributions of source code must retain the above copyright
   9  *      notice, this list of conditions and the following disclaimer.
  10  *   2. Redistributions in binary form must reproduce the above copyright
  11  *      notice, this list of conditions and the following disclaimer in the
  12  *      documentation and/or other materials provided with the distribution.
  13  *   3. Neither the name of the author nor the names of any co-contributors
  14  *      may be used to endorse or promote products derived from this software
  15  *      without specific prior written permission.
  16  *   4. Altered versions must be plainly marked as such, and must not be
  17  *      misrepresented as being the original software and/or documentation.
  18  *
  19  *   THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  20  *   ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  21  *   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  22  *   ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  23  *   FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  24  *   DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  25  *   OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  26  *   HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  27  *   LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  28  *   OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  29  *   SUCH DAMAGE.
  30  *
  31  *---------------------------------------------------------------------------
  32  *
  33  *      i4b_itjc_pci.c: NetJet-S hardware driver
  34  *      ----------------------------------------
  35  *
  36  * $FreeBSD: src/sys/i4b/layer1/itjc/i4b_itjc_pci.c,v 1.1.2.1 2001/08/10 14:08:39 obrien Exp $
  37  * $DragonFly: src/sys/net/i4b/layer1/itjc/i4b_itjc_pci.c,v 1.13 2005/06/14 21:19:19 joerg Exp $
  38  *
  39  *      last edit-date: [Thu Jan 11 11:29:38 2001]
  40  *
  41  *---------------------------------------------------------------------------*/
  42
  43 #include "use_itjc.h"
  44 #include "use_pci.h"
  45 #include "opt_i4b.h"
  46
  47 #if (NITJC > 0)
  48
  49 #include <sys/param.h>
  50 #include <sys/kernel.h>
  51 #include <sys/systm.h>
  52 #include <sys/mbuf.h>
  53
  54 #include <machine/clock.h>
  55 #include <machine/bus_pio.h>
  56 #include <machine/bus.h>
  57 #include <machine/resource.h>
  58 #include <sys/bus.h>
  59 #include <sys/rman.h>
  60
  61 #include <bus/pci/pcireg.h>
  62 #include <bus/pci/pcivar.h>
  63
  64 #include <sys/socket.h>
  65 #include <sys/thread2.h>
  66 #include <net/if.h>
  67
  68 #include <net/i4b/include/machine/i4b_debug.h>
  69 #include <net/i4b/include/machine/i4b_ioctl.h>
  70 #include <net/i4b/include/machine/i4b_trace.h>
  71
  72 #include "../../include/i4b_global.h"
  73 #include "../../include/i4b_mbuf.h"
  74
  75 #include "../i4b_l1.h"
  76
  77 #include "i4b_hdlc.h"   /* XXXXXXXXXXXXXXXXXXXXXXXX */
  78
  79 #include "../isic/i4b_isic.h"
  80 #include "../isic/i4b_isac.h"
  81
  82 #include "i4b_itjc_ext.h"
  83
  84 #define PCI_TJNET_VID (0xe159)
  85 #define PCI_TJ300_DID (0x0001)
  86
  87
  88 /*
  89  * Function prototypes
  90  */
  91
  92 static int  itjc_probe(device_t dev);
  93 static int  itjc_attach(device_t dev);
  94 static void itjc_shutdown(device_t dev);
  95 static void itjc_intr(void *xsc);
  96 static int  itjc_dma_start(struct l1_softc *sc);
  97 static void itjc_dma_stop(struct l1_softc *sc);
  98 static void itjc_isac_intr(struct l1_softc *sc);
  99 static void itjc_init_linktab(struct l1_softc *sc);
 100 static void itjc_bchannel_setup(int unit, int h_chan, int bprot,
 101         int activate);
 102 static void itjc_bchannel_stat(int unit, int h_chan, bchan_statistics_t *bsp);
 103
 104
 105 /*
 106  * Shorter names to bus resource manager routines.
 107  */
 108
 109 #define itjc_bus_setup(sc)                                              \
 110         bus_space_handle_t h =                                          \
 111                 rman_get_bushandle((sc)->sc_resources.io_base[0]);      \
 112         bus_space_tag_t    t =                                          \
 113                 rman_get_bustag((sc)->sc_resources.io_base[0]);
 114
 115 #define itjc_read_1(port)       (bus_space_read_1(t, h, (port)))
 116 #define itjc_read_4(port)       (bus_space_read_4(t, h, (port)))
 117 #define itjc_write_1(port, data) (bus_space_write_1(t, h, (port), (data)))
 118 #define itjc_write_4(port, data) (bus_space_write_4(t, h, (port), (data)))
 119 #define itjc_read_multi_1(port, buf, size)                              \
 120         (bus_space_read_multi_1(t, h, (port), (buf), (size)))
 121 #define itjc_write_multi_1(port, buf, size)                             \
 122         (bus_space_write_multi_1(t, h, (port), (buf), (size)))
 123
 124
 125 /*---------------------------------------------------------------------------*
 126  *      Glue data to register ourselves as a PCI device driver.
 127  *---------------------------------------------------------------------------*/
 128
 129 static device_method_t itjc_pci_methods[] =
 130 {
 131         /* Device interface */
 132         DEVMETHOD(device_probe,         itjc_probe),
 133         DEVMETHOD(device_attach,        itjc_attach),
 134         DEVMETHOD(device_shutdown,      itjc_shutdown),
 135
 136         /* bus interface */
 137         DEVMETHOD(bus_print_child,      bus_generic_print_child),
 138         DEVMETHOD(bus_driver_added,     bus_generic_driver_added),
 139
 140         { 0, 0 }
 141 };
 142
 143 static driver_t itjc_pci_driver =
 144 {
 145         "itjc",
 146         itjc_pci_methods,
 147         sizeof(struct l1_softc)
 148 };
 149
 150 static devclass_t itjc_pci_devclass;
 151
 152 DRIVER_MODULE(netjet, pci, itjc_pci_driver, itjc_pci_devclass, 0, 0);
 153
 154 /*
 155  * Jump table for multiplex routines.
 156  */
 157
 158 struct i4b_l1mux_func itjc_l1mux_func =
 159 {
 160         itjc_ret_linktab,
 161         itjc_set_linktab,
 162         itjc_mph_command_req,
 163         itjc_ph_data_req,
 164         itjc_ph_activate_req,
 165 };
 166
 167 struct l1_softc *itjc_scp[ITJC_MAXUNIT];
 168
 169
 170 /*---------------------------------------------------------------------------*
 171  *      Tiger300/320 PCI ASIC registers.
 172  *---------------------------------------------------------------------------*/
 173
 174 /*
 175  *      Register offsets from i/o base.
 176  */
 177 enum tiger_regs
 178 {
 179         TIGER_RESET_PIB_CL_TIME = 0x00,
 180         TIGER_DMA_OPER          = 0x01,
 181         TIGER_AUX_PORT_CNTL     = 0x02,
 182         TIGER_AUX_PORT_DATA     = 0x03,
 183         TIGER_INT0_MASK         = 0x04,
 184         TIGER_INT1_MASK         = 0x05,
 185         TIGER_INT0_STATUS       = 0x06,
 186         TIGER_INT1_STATUS       = 0x07,
 187         TIGER_DMA_WR_START_ADDR = 0x08,
 188         TIGER_DMA_WR_INT_ADDR   = 0x0C,
 189         TIGER_DMA_WR_END_ADDR   = 0x10,
 190         TIGER_DMA_WR_CURR_ADDR  = 0x14,
 191         TIGER_DMA_RD_START_ADDR = 0x18,
 192         TIGER_DMA_RD_INT_ADDR   = 0x1C,
 193         TIGER_DMA_RD_END_ADDR   = 0x20,
 194         TIGER_DMA_RD_CURR_ADDR  = 0x24,
 195         TIGER_PULSE_COUNTER     = 0x28,
 196 };
 197
 198 /*
 199  * Bits on the above registers.
 200  */
 201
 202 enum tiger_reg_bits
 203 {
 204 /* Reset and PIB Cycle Timing */
 205
 206         TIGER_DMA_OP_MODE_MASK          = 0x80,
 207                 TIGER_SELF_ADDR_DMA     = 0x00, /* Wrap around ending addr */
 208                 TIGER_NORMAL_DMA        = 0x80, /* Stop at ending addr */
 209
 210         TIGER_DMA_INT_MODE_MASK         = 0x40,
 211                 TIGER_DONT_LATCH_DMA_INT= 0x00, /* Bits on int0 status will be
 212                                                    set only while curr addr
 213                                                    equals int or end addr */
 214                 TIGER_LATCH_DMA_INT     = 0x40, /* Bits on int0 status remain
 215                                                    set until cleared by CPU */
 216
 217         TIGER_PIB_CYCLE_TIMING_MASK     = 0x30,
 218                 TIGER_PIB_3_CYCLES      = 0x00,
 219                 TIGER_PIB_5_CYCLES      = 0x01,
 220                 TIGER_PIB_12_CYCLES     = 0x10,
 221
 222         TIGER_RESET_MASK                = 0x0F,
 223                 TIGER_RESET_PULSE_COUNT = 0x08,
 224                 TIGER_RESET_SERIAL_PORT = 0x04,
 225                 TIGER_RESET_DMA_LOGIC   = 0x02,
 226                 TIGER_RESET_EXTERNAL    = 0x01,
 227                 TIGER_RESET_ALL         = 0x0F,
 228
 229 /* DMA Operation */
 230         TIGER_DMA_RESTART_MASK          = 0x02,
 231                 TIGER_HOLD_DMA          = 0x00,
 232                 TIGER_RESTART_DMA       = 0x00,
 233
 234         TIGER_DMA_ENABLE_MASK           = 0x01,
 235                 TIGER_ENABLE_DMA        = 0x01,
 236                 TIGER_DISABLE_DMA       = 0x00,
 237
 238 /* AUX Port Control & Data plus Interrupt 1 Mask & Status  */
 239         TIGER_AUX_7_MASK                = 0x80,
 240         TIGER_AUX_6_MASK                = 0x40,
 241         TIGER_AUX_5_MASK                = 0x20,
 242         TIGER_AUX_4_MASK                = 0x10,
 243         TIGER_ISAC_INT_MASK             = 0x10,
 244         TIGER_AUX_3_MASK                = 0x08,
 245         TIGER_AUX_2_MASK                = 0x04,
 246         TIGER_AUX_1_MASK                = 0x02,
 247         TIGER_AUX_0_MASK                = 0x01,
 248
 249 /* AUX Port Control */
 250                 TIGER_AUX_7_IS_INPUT    = 0x00,
 251                 TIGER_AUX_7_IS_OUTPUT   = 0x80,
 252                 TIGER_AUX_6_IS_INPUT    = 0x00,
 253                 TIGER_AUX_6_IS_OUTPUT   = 0x40,
 254                 TIGER_AUX_5_IS_INPUT    = 0x00,
 255                 TIGER_AUX_5_IS_OUTPUT   = 0x20,
 256                 TIGER_AUX_4_IS_INPUT    = 0x00,
 257                 TIGER_AUX_4_IS_OUTPUT   = 0x10,
 258                 TIGER_AUX_3_IS_INPUT    = 0x00,
 259                 TIGER_AUX_3_IS_OUTPUT   = 0x80,
 260                 TIGER_AUX_2_IS_INPUT    = 0x00,
 261                 TIGER_AUX_2_IS_OUTPUT   = 0x40,
 262                 TIGER_AUX_1_IS_INPUT    = 0x00,
 263                 TIGER_AUX_1_IS_OUTPUT   = 0x20,
 264                 TIGER_AUX_0_IS_INPUT    = 0x00,
 265                 TIGER_AUX_0_IS_OUTPUT   = 0x10,
 266                 TIGER_AUX_NJ_DEFAULT    = 0xEF, /* All but ISAC int is output */
 267
 268 /* Interrupt 0 Mask & Status */
 269         TIGER_PCI_TARGET_ABORT_INT_MASK = 0x20,
 270                 TIGER_NO_TGT_ABORT_INT  = 0x00,
 271                 TIGER_TARGET_ABORT_INT  = 0x20,
 272         TIGER_PCI_MASTER_ABORT_INT_MASK = 0x10,
 273                 TIGER_NO_MST_ABORT_INT  = 0x00,
 274                 TIGER_MASTER_ABORT_INT  = 0x10,
 275         TIGER_DMA_RD_END_INT_MASK       = 0x08,
 276                 TIGER_NO_RD_END_INT     = 0x00,
 277                 TIGER_RD_END_INT        = 0x08,
 278         TIGER_DMA_RD_INT_INT_MASK       = 0x04,
 279                 TIGER_NO_RD_INT_INT     = 0x00,
 280                 TIGER_RD_INT_INT        = 0x04,
 281         TIGER_DMA_WR_END_INT_MASK       = 0x02,
 282                 TIGER_NO_WR_END_INT     = 0x00,
 283                 TIGER_WR_END_INT        = 0x02,
 284         TIGER_DMA_WR_INT_INT_MASK       = 0x01,
 285                 TIGER_NO_WR_INT_INT     = 0x00,
 286                 TIGER_WR_INT_INT        = 0x01,
 287
 288 /* Interrupt 1 Mask & Status */
 289                 TIGER_NO_AUX_7_INT      = 0x00,
 290                 TIGER_AUX_7_INT         = 0x80,
 291                 TIGER_NO_AUX_6_INT      = 0x00,
 292                 TIGER_AUX_6_INT         = 0x40,
 293                 TIGER_NO_AUX_5_INT      = 0x00,
 294                 TIGER_AUX_5_INT         = 0x20,
 295                 TIGER_NO_AUX_4_INT      = 0x00,
 296                 TIGER_AUX_4_INT         = 0x10,
 297                 TIGER_NO_ISAC_INT       = 0x00,
 298                 TIGER_ISAC_INT          = 0x10,
 299                 TIGER_NO_AUX_3_INT      = 0x00,
 300                 TIGER_AUX_3_INT         = 0x08,
 301                 TIGER_NO_AUX_2_INT      = 0x00,
 302                 TIGER_AUX_2_INT         = 0x04,
 303                 TIGER_NO_AUX_1_INT      = 0x00,
 304                 TIGER_AUX_1_INT         = 0x02,
 305                 TIGER_NO_AUX_0_INT      = 0x00,
 306                 TIGER_AUX_0_INT         = 0x01
 307 };
 308
 309 /*
 310  * Peripheral Interface Bus definitions. This is an ISA like bus
 311  * created by the Tiger ASIC to keep ISA chips like the ISAC happy
 312  * on a PCI environment.
 313  *
 314  * Since the PIB only supplies 4 addressing lines, the 2 higher bits
 315  * (A4 & A5) of the ISAC register addresses are wired on the 2 lower
 316  * AUX lines. Another restriction is that all I/O to the PIB (8bit
 317  * wide) is mapped on the PCI side as 32bit data. So the PCI address
 318  * of a given ISAC register has to be multiplied by 4 before being
 319  * added to the PIB base offset.
 320  */
 321 enum tiger_pib_regs_defs
 322 {
 323         /* Offset from the I/O base to the ISAC registers. */
 324         PIB_OFFSET              = 0xC0,
 325         PIB_LO_ADDR_MASK        = 0x0F,
 326         PIB_HI_ADDR_MASK        = 0x30,
 327         PIB_LO_ADDR_SHIFT       = 2,    /* Align on dword boundary */
 328         PIB_HI_ADDR_SHIFT       = 4     /* Right shift to AUX_1 & AUX_0 */
 329 };
 330
 331
 332 #define itjc_set_pib_addr_msb(a)                                        \
 333 (                                                                       \
 334         itjc_write_1(TIGER_AUX_PORT_DATA,                               \
 335                 ((a) & PIB_HI_ADDR_MASK) >> PIB_HI_ADDR_SHIFT)          \
 336 )
 337
 338 #define itjc_pib_2_pci(a)                                               \
 339 (                                                                       \
 340         (((a) & PIB_LO_ADDR_MASK) << PIB_LO_ADDR_SHIFT) + PIB_OFFSET    \
 341 )
 342
 343 #define itjc_get_dma_offset(ctx,reg)                                    \
 344 (                                                                       \
 345         (u_int16_t)((bus_addr_t)itjc_read_4((reg)) - (ctx)->bus_addr)   \
 346 )
 347
 348
 349 /*
 350  * IOM-2 serial channel 0 DMA data ring buffers.
 351  *
 352  * The Tiger300/320 ASIC do not nothing more than transfer via DMA the
 353  * first 32 bits of every IOM-2 frame on the serial interface to the
 354  * ISAC. So we have no framing/deframing facilities like we would have
 355  * with an HSCX, having to do the job with CPU cycles. On the plus side
 356  * we are able to specify large rings which can limit the occurrence of
 357  * over/underruns.
 358  */
 359
 360 enum
 361 {
 362         ITJC_RING_SLOT_WORDS    = 64,
 363         ITJC_RING_WORDS         = 3 * ITJC_RING_SLOT_WORDS,
 364         ITJC_RING_SLOT_BYTES    = 4 * ITJC_RING_SLOT_WORDS,
 365         ITJC_RING_BYTES         = 4 * ITJC_RING_WORDS,
 366         ITJC_DMA_POOL_WORDS     = 2 * ITJC_RING_WORDS,
 367         ITJC_DMA_POOL_BYTES     = 4 * ITJC_DMA_POOL_WORDS
 368 };
 369
 370 #define itjc_ring_add(x, d)     (((x) + 4 * (d)) % ITJC_RING_BYTES)
 371 #define itjc_ring_sub(x, d)     (((x) + ITJC_RING_BYTES - 4 * (d))      \
 372                                         % ITJC_RING_BYTES)
 373
 374
 375 enum
 376 {
 377         TIGER_CH_A              = 0,
 378         TIGER_CH_B              = 1,
 379
 380         HSCX_CH_A               = 0,    /* For compatibility reasons. */
 381         HSCX_CH_B               = 1,
 382 };
 383
 384 enum
 385 {
 386         ITJC_TEL_SILENCE_BYTE   = 0x00,
 387         ITJC_HDLC_FLAG_BYTE     = 0x7E,
 388         ITJC_HDLC_ABORT_BYTE    = 0xFF
 389 };
 390
 391 /*
 392  * Hardware DMA control block (one per card).
 393  */
 394 typedef enum
 395 {
 396         ITJC_DS_LOAD_FAILED     = -1,
 397         ITJC_DS_FREE            =  0,
 398         ITJC_DS_LOADING,
 399         ITJC_DS_STOPPED,
 400         ITJC_DS_RUNNING
 401 }
 402         dma_state_t;
 403
 404 typedef struct
 405 {
 406         dma_state_t     state;
 407         u_int8_t        *pool;
 408         bus_addr_t      bus_addr;
 409         bus_dma_tag_t   tag;
 410         bus_dmamap_t    map;
 411         int             error;
 412 }
 413         dma_context_t;
 414
 415 dma_context_t
 416         dma_context     [ ITJC_MAXUNIT ];
 417
 418 /*
 419  * B-channel DMA control blocks (4 per card -- 1 RX & 1 TX per channel).
 420  */
 421 typedef enum
 422 {
 423         ITJC_RS_IDLE    = 0,
 424         ITJC_RS_ACTIVE
 425 }
 426         dma_rx_state_t;
 427
 428 typedef enum
 429 {
 430         ITJC_TS_IDLE    = 0,
 431         ITJC_TS_ACTIVE,
 432         ITJC_TS_AFTER_XDU
 433 }
 434         dma_tx_state_t;
 435
 436 typedef struct
 437 {
 438         u_int8_t        *ring;
 439         bus_addr_t      bus_addr;
 440         u_int16_t       next_read;
 441         u_int16_t       hdlc_len;
 442         u_int16_t       hdlc_tmp;
 443         u_int16_t       hdlc_crc;
 444         u_int16_t       hdlc_ib;
 445         u_int8_t        hdlc_blevel;
 446         u_int8_t        hdlc_flag;
 447         dma_rx_state_t  state;
 448 }
 449         dma_rx_context_t;
 450
 451 typedef struct
 452 {
 453         u_int8_t        *ring;
 454         bus_addr_t      bus_addr;
 455         u_int16_t       next_write;
 456         u_int32_t       hdlc_tmp;
 457         u_int16_t       hdlc_blevel;
 458         u_int16_t       hdlc_crc;
 459         u_int16_t       hdlc_ib;
 460         u_int16_t       next_frame;
 461         u_int16_t       filled;
 462         u_int8_t        hdlc_flag;
 463         dma_tx_state_t  state;
 464 }
 465         dma_tx_context_t;
 466
 467 dma_rx_context_t
 468         dma_rx_context  [ ITJC_MAXUNIT ] [ 2 ];
 469
 470 dma_tx_context_t
 471         dma_tx_context  [ ITJC_MAXUNIT ] [ 2 ];
 472
 473 /*
 474  * Used by the mbuf handling functions.
 475  */
 476 typedef enum
 477 {
 478         ITJC_MB_CURR = 0,
 479         ITJC_MB_NEXT = 1,
 480         ITJC_MB_NEW  = 2
 481 }
 482         which_mb_t;
 483
 484
 485 /*---------------------------------------------------------------------------*
 486  *      itjc_map_callback - get DMA bus address from resource mgr.
 487  *---------------------------------------------------------------------------*/
 488 static void
 489 itjc_map_callback(void *arg, bus_dma_segment_t *segs, int nseg, int error)
 490 {
 491         dma_context_t           *ctx = (dma_context_t *)arg;
 492
 493         if (error)
 494         {
 495                 ctx->error = error;
 496                 ctx->state = ITJC_DS_LOAD_FAILED;
 497                 return;
 498         }
 499
 500         ctx->bus_addr = segs->ds_addr;
 501         ctx->state = ITJC_DS_STOPPED;
 502 }
 503
 504
 505 /*---------------------------------------------------------------------------*
 506  *      itjc_dma_start - Complete DMA setup & start the Tiger DMA engine.
 507  *---------------------------------------------------------------------------*/
 508 static int
 509 itjc_dma_start(struct l1_softc *sc)
 510 {
 511         int                     unit    = sc->sc_unit;
 512         dma_context_t           *ctx    = &dma_context[unit];
 513         dma_rx_context_t        *rxc    = &dma_rx_context[unit][0];
 514         dma_tx_context_t        *txc    = &dma_tx_context[unit][0];
 515         bus_addr_t              ba;
 516         u_int8_t                i;
 517         u_int32_t               *pool_end,
 518                                 *ip;
 519
 520         bus_space_handle_t h = rman_get_bushandle(sc->sc_resources.io_base[0]);
 521         bus_space_tag_t t = rman_get_bustag(sc->sc_resources.io_base[0]);
 522
 523         /* See if it is already running. */
 524
 525         if (ctx->state == ITJC_DS_RUNNING)
 526                 return 0;
 527
 528         if (ctx->state == ITJC_DS_LOAD_FAILED)
 529         {
 530                 NDBGL1(L1_ERROR, "itjc%d: dma_start: DMA map loading "
 531                         "failed (error=%d).\n", unit, ctx->error);
 532                 return 1;
 533         }
 534
 535         if (ctx->state != ITJC_DS_STOPPED)
 536         {
 537                 NDBGL1(L1_ERROR, "itjc%d: dma_start: Unexpected DMA "
 538                         "state (%d).\n", unit, ctx->state);
 539                 return 1;
 540         }
 541
 542         /*
 543          * Initialize the DMA control structures (hardware & B-channel).
 544          */
 545         ba = ctx->bus_addr;
 546
 547         txc->ring = ctx->pool + TIGER_CH_A;
 548         rxc->ring = ctx->pool + TIGER_CH_A + ITJC_RING_BYTES;
 549
 550         txc->bus_addr = ba;
 551         rxc->bus_addr = ba + ITJC_RING_BYTES;
 552
 553         ++rxc; ++txc;
 554
 555         txc->ring = ctx->pool + TIGER_CH_B;
 556         rxc->ring = ctx->pool + TIGER_CH_B + ITJC_RING_BYTES;
 557
 558         txc->bus_addr = ba;
 559         rxc->bus_addr = ba + ITJC_RING_BYTES;
 560
 561         /*
 562          * Fill the DMA ring buffers with IOM-2 channel 0 frames made of
 563          * idle/abort sequences for the B & D channels and NOP for IOM-2
 564          * cmd/ind, monitor handshake & data.
 565          */
 566         pool_end = (u_int32_t *)ctx->pool + ITJC_DMA_POOL_WORDS;
 567         for (ip = (u_int32_t *)ctx->pool; ip < pool_end; ++ip)
 568                 *ip = 0xFFFFFFFF;
 569
 570         /*
 571          * Program the Tiger DMA gears.
 572          */
 573
 574         itjc_write_4(TIGER_DMA_WR_START_ADDR, ba);
 575         itjc_write_4(TIGER_DMA_WR_INT_ADDR, ba + ITJC_RING_SLOT_BYTES - 4);
 576         itjc_write_4(TIGER_DMA_WR_END_ADDR, ba + ITJC_RING_BYTES - 4);
 577
 578         ba += ITJC_RING_BYTES;
 579
 580         itjc_write_4(TIGER_DMA_RD_START_ADDR, ba);
 581         itjc_write_4(TIGER_DMA_RD_INT_ADDR, ba + ITJC_RING_SLOT_BYTES * 2 - 4);
 582         itjc_write_4(TIGER_DMA_RD_END_ADDR, ba + ITJC_RING_BYTES - 4);
 583
 584         itjc_write_1(TIGER_INT0_MASK,
 585                 TIGER_WR_END_INT | TIGER_WR_INT_INT | TIGER_RD_INT_INT);
 586
 587         itjc_write_1(TIGER_DMA_OPER, TIGER_ENABLE_DMA);
 588
 589         /*
 590          * See if it really started.
 591          */
 592         ba = itjc_read_4(TIGER_DMA_RD_CURR_ADDR);
 593         for (i = 0; i < 10; ++i)
 594         {
 595                 DELAY(SEC_DELAY/1000);
 596                 if (ba != itjc_read_4(TIGER_DMA_RD_CURR_ADDR))
 597                 {
 598                         ctx->state = ITJC_DS_RUNNING;
 599                         return 0;
 600                 }
 601         }
 602
 603         NDBGL1(L1_ERROR, "itjc%d: dma_start: DMA start failed.\n ", unit);
 604         return 1;
 605 }
 606
 607
 608 /*---------------------------------------------------------------------------*
 609  *      itjc_dma_stop - Stop the Tiger DMA engine.
 610  *---------------------------------------------------------------------------*/
 611 void
 612 itjc_dma_stop(struct l1_softc *sc)
 613 {
 614         dma_context_t           *ctx    = &dma_context[sc->sc_unit];
 615
 616         bus_space_handle_t h = rman_get_bushandle(sc->sc_resources.io_base[0]);
 617         bus_space_tag_t t = rman_get_bustag(sc->sc_resources.io_base[0]);
 618
 619         /* Only stop the DMA if it is running. */
 620
 621         if (ctx->state != ITJC_DS_RUNNING)
 622                 return;
 623
 624         itjc_write_1(TIGER_DMA_OPER, TIGER_DISABLE_DMA);
 625         DELAY(SEC_DELAY/1000);
 626
 627         ctx->state = ITJC_DS_STOPPED;
 628 }
 629
 630
 631 /*---------------------------------------------------------------------------*
 632  *      itjc_bchannel_dma_setup - The DMA side of itjc_bchannel_setup.
 633  *---------------------------------------------------------------------------*/
 634 static void
 635 itjc_bchannel_dma_setup(struct l1_softc *sc, int h_chan, int activate)
 636 {
 637         dma_rx_context_t        *rxc  = &dma_rx_context[sc->sc_unit][h_chan];
 638         dma_tx_context_t        *txc  = &dma_tx_context[sc->sc_unit][h_chan];
 639
 640         l1_bchan_state_t        *chan = &sc->sc_chan[h_chan];
 641
 642         u_int8_t                fill_byte,
 643                                 *ring_end,
 644                                 *cp;
 645         bus_space_handle_t h;
 646         bus_space_tag_t t;
 647
 648         crit_enter();
 649         h = rman_get_bushandle(sc->sc_resources.io_base[0]);
 650         t = rman_get_bustag(sc->sc_resources.io_base[0]);
 651
 652         if (activate)
 653         {
 654                 /*
 655                  * Get the DMA engine going if it's not running already.
 656                  */
 657                 itjc_dma_start(sc);
 658
 659                 rxc->hdlc_len   = rxc->hdlc_tmp    = rxc->hdlc_crc  = 0;
 660                 rxc->hdlc_ib    = rxc->hdlc_blevel = rxc->hdlc_flag = 0;
 661
 662                 txc->hdlc_tmp   = txc->hdlc_blevel = txc->hdlc_crc  = 0;
 663                 txc->hdlc_ib    = 0;
 664                 txc->hdlc_flag  = 2;
 665                 txc->filled     = 0;
 666
 667                 if (chan->bprot == BPROT_NONE)
 668                         fill_byte = ITJC_TEL_SILENCE_BYTE;
 669                 else
 670                         fill_byte = ITJC_HDLC_ABORT_BYTE;
 671
 672                 ring_end = rxc->ring + ITJC_RING_BYTES;
 673                 for (cp = rxc->ring; cp < ring_end; cp += 4)
 674                         *cp = fill_byte;
 675
 676                 ring_end = txc->ring + ITJC_RING_BYTES;
 677                 for (cp = txc->ring; cp < ring_end; cp += 4)
 678                         *cp = fill_byte;
 679
 680                 rxc->next_read  =
 681                         itjc_get_dma_offset(rxc, TIGER_DMA_RD_CURR_ADDR);
 682
 683                 txc->next_frame = txc->next_write =
 684                         itjc_get_dma_offset(txc, TIGER_DMA_WR_CURR_ADDR);
 685
 686                 rxc->state      = ITJC_RS_ACTIVE;
 687                 txc->state      = ITJC_TS_AFTER_XDU;
 688         }
 689         else
 690         {
 691                 dma_rx_context_t        *rxc2;
 692
 693                 txc->state      = ITJC_TS_IDLE;
 694                 rxc->state      = ITJC_RS_IDLE;
 695
 696                 rxc2 = &dma_rx_context[sc->sc_unit][0];
 697
 698                 if (rxc2->state == ITJC_RS_IDLE
 699                 && rxc2[1].state == ITJC_RS_IDLE)
 700                         itjc_dma_stop(sc);
 701         }
 702
 703         crit_exit();
 704 }
 705
 706
 707 /*---------------------------------------------------------------------------*
 708  *      Mbuf & if_queues management routines.
 709  *---------------------------------------------------------------------------*/
 710
 711 static u_int8_t *
 712 itjc_get_rx_mbuf(l1_bchan_state_t *chan, u_int8_t **dst_end_p,
 713 which_mb_t which)
 714 {
 715         struct mbuf     *mbuf = chan->in_mbuf;
 716
 717         if (mbuf == NULL && which == ITJC_MB_NEW)
 718         {
 719                 if ((mbuf = i4b_Bgetmbuf(BCH_MAX_DATALEN)) == NULL)
 720                         panic("itjc_get_rx_mbuf: cannot allocate mbuf!");
 721
 722                 chan->in_mbuf  = mbuf;
 723                 chan->in_cbptr = (u_int8_t *)mbuf->m_data;
 724                 chan->in_len   = 0;
 725         }
 726
 727         if (dst_end_p != NULL)
 728         {
 729                 if (mbuf != NULL)
 730                         *dst_end_p = (u_int8_t *)(mbuf->m_data)
 731                                 + BCH_MAX_DATALEN;
 732                 else
 733                         *dst_end_p = NULL;
 734         }
 735
 736         return chan->in_cbptr;
 737 }
 738
 739
 740 static void
 741 itjc_save_rx_mbuf(l1_bchan_state_t *chan, u_int8_t * dst)
 742 {
 743         struct mbuf     *mbuf = chan->in_mbuf;
 744
 745         if (dst != NULL && mbuf != NULL)
 746         {
 747                 chan->in_cbptr = dst;
 748                 chan->in_len   = dst - (u_int8_t *)mbuf->m_data;
 749         }
 750         else if (dst == NULL && mbuf == NULL)
 751         {
 752                 chan->in_cbptr = NULL;
 753                 chan->in_len   = 0;
 754         }
 755         else
 756                 panic("itjc_save_rx_mbuf: stale pointer dst=%p mbuf=%p "
 757                         "in_cbptr=%p in_len=%d", dst, mbuf,
 758                         chan->in_cbptr, chan->in_len);
 759 }
 760
 761
 762 static void
 763 itjc_free_rx_mbuf(l1_bchan_state_t *chan)
 764 {
 765         struct mbuf     *mbuf = chan->in_mbuf;
 766
 767         if (mbuf != NULL)
 768                 i4b_Bfreembuf(mbuf);
 769
 770         chan->in_mbuf  = NULL;
 771         chan->in_cbptr = NULL;
 772         chan->in_len   = 0;
 773 }
 774
 775
 776 static void
 777 itjc_put_rx_mbuf(struct l1_softc *sc, l1_bchan_state_t *chan, u_int16_t len)
 778 {
 779         i4b_trace_hdr_t hdr;
 780         struct mbuf     *mbuf    = chan->in_mbuf;
 781         u_int8_t        *data    = mbuf->m_data;
 782         int             activity = 1;
 783
 784         mbuf->m_pkthdr.len = mbuf->m_len = len;
 785
 786         if (sc->sc_trace & TRACE_B_RX)
 787         {
 788                 hdr.unit = L0ITJCUNIT(sc->sc_unit);
 789                 hdr.type = (chan->channel == HSCX_CH_A ? TRC_CH_B1 : TRC_CH_B2);
 790                 hdr.dir = FROM_NT;
 791                 hdr.count = ++sc->sc_trace_bcount;
 792                 MICROTIME(hdr.time);
 793                 i4b_l1_trace_ind(&hdr, len, data);
 794         }
 795
 796         if (chan->bprot == BPROT_NONE)
 797         {
 798                 activity = ! i4b_l1_bchan_tel_silence(data, len);
 799
 800                 /* move rx'd data to rx queue */
 801
 802                 if (!IF_QFULL(&chan->rx_queue))
 803                 {
 804                         IF_ENQUEUE(&chan->rx_queue, mbuf);
 805                 }
 806                 else
 807                 {
 808                         i4b_Bfreembuf(mbuf);
 809                         len = 0;
 810                 }
 811         }
 812
 813         if (len != 0)
 814         {
 815                 chan->rxcount += len;
 816
 817                 (*chan->isic_drvr_linktab->bch_rx_data_ready)
 818                         (chan->isic_drvr_linktab->unit);
 819         }
 820
 821         if (activity)
 822                 (*chan->isic_drvr_linktab->bch_activity)
 823                         (chan->isic_drvr_linktab->unit, ACT_RX);
 824
 825         chan->in_mbuf  = NULL;
 826         chan->in_cbptr = NULL;
 827         chan->in_len   = 0;
 828 }
 829
 830
 831 #define itjc_free_tx_mbufs(chan)                                        \
 832 {                                                                       \
 833         i4b_Bfreembuf((chan)->out_mbuf_head);                           \
 834         (chan)->out_mbuf_cur = (chan)->out_mbuf_head = NULL;            \
 835         (chan)->out_mbuf_cur_ptr = NULL;                                \
 836         (chan)->out_mbuf_cur_len = 0;                                   \
 837 }
 838
 839
 840 static u_int16_t
 841 itjc_get_tx_mbuf(struct l1_softc *sc, l1_bchan_state_t *chan,
 842         u_int8_t **src_p, which_mb_t which)
 843 {
 844         i4b_trace_hdr_t hdr;
 845         struct mbuf     *mbuf = chan->out_mbuf_cur;
 846         u_int8_t        activity = 1;
 847         u_int16_t       len;
 848         void            *data;
 849
 850         switch (which)
 851         {
 852         case ITJC_MB_CURR:
 853                 if (mbuf != NULL)
 854                 {
 855                         *src_p = chan->out_mbuf_cur_ptr;
 856                         return   chan->out_mbuf_cur_len;
 857                 }
 858
 859                 break;
 860
 861         case ITJC_MB_NEXT:
 862                 if (mbuf != NULL)
 863                 {
 864                         chan->txcount += mbuf->m_len;
 865
 866                         mbuf = mbuf->m_next;
 867
 868                         if (mbuf != NULL)
 869                                 goto new_mbuf;
 870                 }
 871
 872                 chan->out_mbuf_cur_ptr = *src_p = NULL;
 873                 chan->out_mbuf_cur_len = 0;
 874
 875                 if (chan->out_mbuf_head != NULL)
 876                 {
 877                         i4b_Bfreembuf(chan->out_mbuf_head);
 878                         chan->out_mbuf_head = NULL;
 879                 }
 880
 881                 return 0;
 882
 883         case ITJC_MB_NEW:
 884                 if (mbuf != NULL)
 885                         chan->txcount += mbuf->m_len;
 886         }
 887
 888         if (chan->out_mbuf_head != NULL)
 889                 i4b_Bfreembuf(chan->out_mbuf_head);
 890
 891         IF_DEQUEUE(&chan->tx_queue, mbuf);
 892
 893         if (mbuf == NULL)
 894         {
 895                 chan->out_mbuf_cur = chan->out_mbuf_head = NULL;
 896                 chan->out_mbuf_cur_ptr = *src_p = NULL;
 897                 chan->out_mbuf_cur_len = 0;
 898
 899                 chan->state &= ~(HSCX_TX_ACTIVE);
 900
 901                 (*chan->isic_drvr_linktab->bch_tx_queue_empty)
 902                         (chan->isic_drvr_linktab->unit);
 903
 904                 return 0;
 905         }
 906
 907         chan->out_mbuf_head = mbuf;
 908
 909 new_mbuf:
 910         chan->out_mbuf_cur      = mbuf;
 911         chan->out_mbuf_cur_ptr  = data = mbuf->m_data;
 912         chan->out_mbuf_cur_len  = len  = mbuf->m_len;
 913
 914         chan->state |= HSCX_TX_ACTIVE;
 915
 916         if (sc->sc_trace & TRACE_B_TX)
 917         {
 918                 hdr.unit = L0ITJCUNIT(sc->sc_unit);
 919                 hdr.type = (chan->channel == HSCX_CH_A ? TRC_CH_B1 : TRC_CH_B2);
 920                 hdr.dir = FROM_TE;
 921                 hdr.count = ++sc->sc_trace_bcount;
 922                 MICROTIME(hdr.time);
 923                 i4b_l1_trace_ind(&hdr, len, data);
 924         }
 925
 926         if (chan->bprot == BPROT_NONE)
 927                 activity = ! i4b_l1_bchan_tel_silence(data, len);
 928
 929         if (activity)
 930                 (*chan->isic_drvr_linktab->bch_activity)
 931                         (chan->isic_drvr_linktab->unit, ACT_TX);
 932
 933         *src_p = data;
 934         return len;
 935 }
 936
 937
 938 #define itjc_save_tx_mbuf(chan, src, dst)                               \
 939 (                                                                       \
 940         (chan)->out_mbuf_cur != NULL ?                                  \
 941         (                                                               \
 942                 (chan)->out_mbuf_cur_ptr = (src),                       \
 943                 (chan)->out_mbuf_cur_len = (len)                        \
 944         )                                                               \
 945         :                                                               \
 946                 0                                                       \
 947 )
 948
 949
 950 /*---------------------------------------------------------------------------*
 951  *      B-channel interrupt service routines.
 952  *---------------------------------------------------------------------------*/
 953
 954 /*
 955  * Since the Tiger ASIC doesn't produce a XMIT underflow indication,
 956  * we need to deduce it ourselves. This is somewhat tricky because we
 957  * are dealing with modulo m arithmetic. The idea here is to have a
 958  * "XDU zone" ahead of the writing pointer sized 1/3 of total ring
 959  * length (a ring slot). If the hardware DMA pointer is found there we
 960  * consider that a XDU has occurred. To complete the scheme, we never
 961  * let the ring have more than 2 slots of (unsent) data and adjust the
 962  * interrupt registers to cause an interrupt at every slot.
 963  */
 964 static u_int8_t
 965 itjc_xdu(struct l1_softc *sc, l1_bchan_state_t *chan, dma_tx_context_t *ctx,
 966 u_int16_t *dst_p, u_int16_t *dst_end_p, u_int8_t tx_restart)
 967 {
 968         u_int8_t        xdu;
 969
 970         u_int16_t       dst_end,
 971                         dst,
 972                         dma,
 973                         dma_l,
 974                         dma_h,
 975                         xdu_l,
 976                         xdu_h;
 977
 978         bus_space_handle_t h = rman_get_bushandle(sc->sc_resources.io_base[0]);
 979         bus_space_tag_t t = rman_get_bustag(sc->sc_resources.io_base[0]);
 980
 981         /*
 982          * Since the hardware is running, be conservative and assume
 983          * the pointer location has a `fuzy' error factor.
 984          */
 985         dma   = itjc_get_dma_offset(ctx, TIGER_DMA_WR_CURR_ADDR);
 986         dma_l = dma;
 987         dma_h = itjc_ring_add(dma, 1);
 988
 989         dst_end = itjc_ring_sub(dma_l, ITJC_RING_SLOT_WORDS);
 990
 991         if (ctx->state != ITJC_TS_ACTIVE)
 992         {
 993                 xdu = (ctx->state == ITJC_TS_AFTER_XDU);
 994                 dst = itjc_ring_add(dma_h, 4);
 995                 goto done;
 996         }
 997
 998         /*
 999          * Check for xmit underruns.
1000          */
1001         xdu_l = dst = ctx->next_write;
1002         xdu_h = itjc_ring_add(dst, ITJC_RING_SLOT_WORDS);
1003
1004         if (xdu_l < xdu_h)
1005                 xdu =      (xdu_l <= dma_l && dma_l < xdu_h)
1006                         || (xdu_l <= dma_h && dma_h < xdu_h);
1007         else
1008                 xdu =      (xdu_l <= dma_l || dma_l < xdu_h)
1009                         || (xdu_l <= dma_h || dma_h < xdu_h);
1010
1011         if (xdu)
1012         {
1013                 ctx->state = ITJC_TS_AFTER_XDU;
1014
1015                 dst = itjc_ring_add(dma_h, 4);
1016         }
1017         else if (tx_restart)
1018         {
1019                 /*
1020                  * See if we still can restart from immediately
1021                  * after the last frame sent. It's a XDU test but
1022                  * using the real data end on the comparsions. We
1023                  * don't consider XDU an error here because we were
1024                  * just trying to avoid send a filling gap between
1025                  * frames. If it's already sent no harm is done.
1026                  */
1027                 xdu_l = dst = ctx->next_frame;
1028                 xdu_h = itjc_ring_add(dst, ITJC_RING_SLOT_WORDS);
1029
1030                 if (xdu_l < xdu_h)
1031                         xdu =      (xdu_l <= dma_l && dma_l < xdu_h)
1032                                 || (xdu_l <= dma_h && dma_h < xdu_h);
1033                 else
1034                         xdu =      (xdu_l <= dma_l || dma_l < xdu_h)
1035                                 || (xdu_l <= dma_h || dma_h < xdu_h);
1036
1037                 if (xdu)
1038                         dst = itjc_ring_add(dma_h, 4);
1039
1040                 xdu = 0;
1041         }
1042
1043 done:
1044         if (dst_p != NULL)
1045                 *dst_p = dst;
1046
1047         if (dst_end_p != NULL)
1048                 *dst_end_p = dst_end;
1049
1050         ctx->next_write = dst_end;
1051
1052         return xdu;
1053 }
1054
1055
1056 #define itjc_rotate_hdlc_flag(blevel)                                   \
1057         ((u_int8_t)(0x7E7E >> (8 - (u_int8_t)((blevel) >> 8))))
1058
1059
1060 static void
1061 itjc_dma_rx_intr(struct l1_softc *sc, l1_bchan_state_t *chan,
1062 dma_rx_context_t *ctx)
1063 {
1064         u_int8_t        *ring,
1065                         *dst,
1066                         *dst_end,
1067                         flag,
1068                         blevel;
1069
1070         u_int16_t       dma,
1071                         src,
1072                         tmp2,
1073                         tmp,
1074                         len,
1075                         crc,
1076                         ib;
1077
1078         bus_space_handle_t h = rman_get_bushandle(sc->sc_resources.io_base[0]);
1079         bus_space_tag_t t = rman_get_bustag(sc->sc_resources.io_base[0]);
1080
1081
1082         if (ctx->state == ITJC_RS_IDLE)
1083                 return;
1084
1085         ring = ctx->ring;
1086         dma = itjc_get_dma_offset(ctx, TIGER_DMA_RD_CURR_ADDR);
1087         dma = itjc_ring_sub(dma, 1);
1088         src = ctx->next_read;
1089
1090         if (chan->bprot == BPROT_NONE)
1091         {
1092                 dst = itjc_get_rx_mbuf(chan, &dst_end, ITJC_MB_CURR);
1093
1094                 while (src != dma)
1095                 {
1096                         if (dst == NULL)
1097                                 dst = itjc_get_rx_mbuf(chan, &dst_end,
1098                                         ITJC_MB_NEW);
1099
1100                         *dst++ = ring[src];
1101                         src = itjc_ring_add(src, 1);
1102
1103                         if (dst >= dst_end)
1104                         {
1105                                 itjc_put_rx_mbuf(sc, chan, BCH_MAX_DATALEN);
1106                                 dst = dst_end = NULL;
1107                         }
1108                 }
1109                 ctx->next_read = src;
1110                 itjc_save_rx_mbuf(chan, dst);
1111                 return;
1112         }
1113
1114         blevel = ctx->hdlc_blevel;
1115         flag   = ctx->hdlc_flag;
1116         len    = ctx->hdlc_len;
1117         tmp    = ctx->hdlc_tmp;
1118         crc    = ctx->hdlc_crc;
1119         ib     = ctx->hdlc_ib;
1120
1121         dst = itjc_get_rx_mbuf(chan, NULL, ITJC_MB_CURR);
1122
1123         while (src != dma)
1124         {
1125                 HDLC_DECODE(*dst++, len, tmp, tmp2, blevel, ib, crc, flag,
1126                 {/* rdd */
1127                         tmp2 = ring[src];
1128                         src = itjc_ring_add(src, 1);
1129                 },
1130                 {/* nfr */
1131                         if (dst != NULL)
1132                                 panic("itjc_dma_rx_intr: nfrcmd with "
1133                                         "valid current frame");
1134
1135                         dst = itjc_get_rx_mbuf(chan, &dst_end, ITJC_MB_NEW);
1136                         len = dst_end - dst;
1137                 },
1138                 {/* cfr */
1139                         len = BCH_MAX_DATALEN - len;
1140
1141                         if ((!len) || (len > BCH_MAX_DATALEN))
1142                         {
1143                                 /*
1144                                  * NOTE: frames without any data, only crc
1145                                  * field, should be silently discared.
1146                                  */
1147                                 NDBGL1(L1_S_MSG, "itjc_dma_rx_intr: "
1148                                         "bad frame (len=%d, unit=%d)",
1149                                         len, sc->sc_unit);
1150
1151                                 itjc_free_rx_mbuf(chan);
1152
1153                                 goto s0;
1154                         }
1155
1156                         if (crc)
1157                         {
1158                                 NDBGL1(L1_S_ERR,
1159                                         "CRC (crc=0x%04x, len=%d, unit=%d)",
1160                                         crc, len, sc->sc_unit);
1161
1162                                 itjc_free_rx_mbuf(chan);
1163
1164                                 goto s0;
1165                         }
1166
1167                         itjc_put_rx_mbuf(sc, chan, len);
1168
1169                 s0:
1170                         dst = NULL;
1171                         len = 0;
1172                 },
1173                 {/* rab */
1174                         NDBGL1(L1_S_ERR, "Read Abort (unit=%d)", sc->sc_unit);
1175
1176                         itjc_free_rx_mbuf(chan);
1177                         dst = NULL;
1178                         len = 0;
1179                 },
1180                 {/* rdo */
1181                         NDBGL1(L1_S_ERR, "RDO (unit=%d) dma=%d src=%d",
1182                                 sc->sc_unit, dma, src);
1183
1184                         itjc_free_rx_mbuf(chan);
1185                         dst = NULL;
1186                         len = 0;
1187                 },
1188                 continue,
1189                 d);
1190         }
1191
1192         itjc_save_rx_mbuf(chan, dst);
1193
1194         ctx->next_read  = src;
1195         ctx->hdlc_blevel= blevel;
1196         ctx->hdlc_flag  = flag;
1197         ctx->hdlc_len   = len;
1198         ctx->hdlc_tmp   = tmp;
1199         ctx->hdlc_crc   = crc;
1200         ctx->hdlc_ib    = ib;
1201 }
1202
1203
1204 /*
1205  * The HDLC side of itjc_dma_tx_intr. We made a separate function
1206  * to improve readability and (perhaps) help the compiler with
1207  * register allocation.
1208  */
1209 static void
1210 itjc_hdlc_encode(struct l1_softc *sc, l1_bchan_state_t *chan,
1211 dma_tx_context_t * ctx)
1212 {
1213         u_int8_t        *ring,
1214                         *src,
1215                         xdu,
1216                         flag,
1217                         flag_byte,
1218                         tx_restart;
1219
1220         u_int16_t       saved_len,
1221                         dst_end,
1222                         dst_end1,
1223                         dst,
1224                         filled,
1225                         blevel,
1226                         tmp2,
1227                         len,
1228                         crc,
1229                         ib;
1230
1231         u_int32_t       tmp;
1232
1233
1234         saved_len = len = itjc_get_tx_mbuf(sc, chan, &src, ITJC_MB_CURR);
1235
1236         filled = ctx->filled;
1237         flag   = ctx->hdlc_flag;
1238
1239         if (src == NULL && flag == 2 && filled >= ITJC_RING_WORDS)
1240                 return;
1241
1242         tx_restart = (flag == 2 && src != NULL);
1243         xdu = itjc_xdu(sc, chan, ctx, &dst, &dst_end, tx_restart);
1244
1245         ring   = ctx->ring;
1246
1247         ib     = ctx->hdlc_ib;
1248         crc    = ctx->hdlc_crc;
1249         tmp    = ctx->hdlc_tmp;
1250         blevel = ctx->hdlc_blevel;
1251
1252         if (xdu)
1253         {
1254                 if (flag != 2)
1255                 {
1256                         NDBGL1(L1_H_XFRERR, "XDU");
1257                         ++chan->stat_XDU;
1258
1259                         /*
1260                          * Abort the current frame and
1261                          * prepare for a full restart.
1262                          */
1263                         itjc_free_tx_mbufs(chan);
1264                         saved_len = len = filled = 0;
1265                         flag = (u_int8_t)-2;
1266                 }
1267                 else if (filled < ITJC_RING_SLOT_WORDS)
1268                 {
1269                         /*
1270                          * A little garbage may have been retransmitted.
1271                          * Send an abort before any new data.
1272                          */
1273                         filled = 0;
1274                         flag = (u_int8_t)-2;
1275                 }
1276         }
1277
1278         if (flag != 3)
1279                 len = 0;
1280
1281         while (dst != dst_end)
1282         {
1283                 HDLC_ENCODE(
1284                 *src++, len, tmp, tmp2, blevel, ib, crc, flag,
1285                 {/* gfr */
1286                         if ((len = saved_len) == 0)
1287                                 len = itjc_get_tx_mbuf(sc, chan, &src,
1288                                         ITJC_MB_NEW);
1289
1290                         if (len == 0)
1291                         {
1292                                 ctx->next_frame = dst;
1293
1294                                 flag_byte = itjc_rotate_hdlc_flag(blevel);
1295
1296                                 for (dst_end1 = itjc_ring_sub(dst_end, 1);
1297                                 dst != dst_end1;
1298                                 dst = itjc_ring_add(dst, 1))
1299                                 {
1300                                         ring[dst] = flag_byte;
1301                                         ++filled;
1302                                 }
1303                         }
1304                         else
1305                                 filled = 0;
1306
1307                         ctx->state = ITJC_TS_ACTIVE;
1308                 },
1309                 {/* nmb */
1310                         saved_len = 0;
1311                         len = itjc_get_tx_mbuf(sc, chan, &src, ITJC_MB_NEXT);
1312                 },
1313                 {/* wrd */
1314                         ring[dst] = (u_int8_t)tmp;
1315                         dst = itjc_ring_add(dst, 1);
1316                 },
1317                 d1);
1318         }
1319
1320         ctx->hdlc_blevel = blevel;
1321         ctx->hdlc_flag   = flag;
1322         ctx->hdlc_tmp    = tmp;
1323         ctx->hdlc_crc    = crc;
1324         ctx->hdlc_ib     = ib;
1325
1326         ctx->filled = filled;
1327         ctx->next_write = dst;
1328
1329         itjc_save_tx_mbuf(chan, src, len);
1330 }
1331
1332
1333 static void
1334 itjc_dma_tx_intr(struct l1_softc *sc, l1_bchan_state_t *chan,
1335 dma_tx_context_t * ctx)
1336 {
1337         u_int8_t        *data_end,
1338                         *ring,
1339                         *src,
1340                         xdu;
1341
1342         u_int16_t       dst,
1343                         dst_end,
1344                         filled,
1345                         len;
1346
1347
1348         if (ctx->state == ITJC_TS_IDLE)
1349                 goto done;
1350
1351         if (chan->bprot != BPROT_NONE)
1352         {
1353                 itjc_hdlc_encode(sc, chan, ctx);
1354                 goto done;
1355         }
1356
1357         ring   = ctx->ring;
1358         filled = ctx->filled;
1359
1360         len = itjc_get_tx_mbuf(sc, chan, &src, ITJC_MB_CURR);
1361
1362         if (len == 0 && filled >= ITJC_RING_WORDS)
1363                 goto done;
1364
1365         xdu = itjc_xdu(sc, chan, ctx, &dst, &dst_end, len != 0);
1366
1367         if (xdu && filled < ITJC_RING_WORDS)
1368         {
1369                 NDBGL1(L1_H_XFRERR, "XDU");
1370                 ++chan->stat_XDU;
1371                 filled = 0;
1372         }
1373
1374         if (len == 0)
1375                 goto fill_ring;
1376
1377         ctx->state = ITJC_TS_ACTIVE;
1378
1379         data_end = src + len;
1380         while (dst != dst_end)
1381         {
1382                 ring[dst] = *src++; --len;
1383
1384                 dst = itjc_ring_add(dst, 1);
1385
1386                 if (src >= data_end)
1387                 {
1388                         len = itjc_get_tx_mbuf(sc, chan, &src, ITJC_MB_NEXT);
1389                         if (len == 0)
1390                                 len = itjc_get_tx_mbuf(sc, chan,
1391                                          &src, ITJC_MB_NEW);
1392
1393                         if (len == 0)
1394                         {
1395                                 data_end = NULL;
1396                                 break;
1397                         }
1398                         data_end = src + len;
1399                 }
1400         }
1401
1402         itjc_save_tx_mbuf(chan, src, len);
1403
1404         filled = 0;
1405
1406 fill_ring:
1407         ctx->next_frame = dst;
1408
1409         for (; dst != dst_end; dst = itjc_ring_add(dst, 1))
1410         {
1411                 ring[dst] = ITJC_TEL_SILENCE_BYTE;
1412                 ++filled;
1413         }
1414
1415         ctx->next_write = dst;
1416         ctx->filled = filled;
1417
1418 done:
1419         ;
1420 }
1421
1422
1423 /*---------------------------------------------------------------------------*
1424  *      NetJet fifo read/write routines.
1425  *---------------------------------------------------------------------------*/
1426
1427 static void
1428 itjc_read_fifo(struct l1_softc *sc, int what, void *buf, size_t size)
1429 {
1430         bus_space_handle_t h = rman_get_bushandle(sc->sc_resources.io_base[0]);
1431         bus_space_tag_t t = rman_get_bustag(sc->sc_resources.io_base[0]);
1432
1433         if (what != ISIC_WHAT_ISAC)
1434                 panic("itjc_write_fifo: Trying to read from HSCX fifo.\n");
1435
1436         itjc_set_pib_addr_msb(0);
1437         itjc_read_multi_1(PIB_OFFSET, buf, size);
1438 }
1439
1440
1441 static void
1442 itjc_write_fifo(struct l1_softc *sc, int what, void *buf, size_t size)
1443 {
1444         bus_space_handle_t h = rman_get_bushandle(sc->sc_resources.io_base[0]);
1445         bus_space_tag_t t = rman_get_bustag(sc->sc_resources.io_base[0]);
1446
1447         if (what != ISIC_WHAT_ISAC)
1448                 panic("itjc_write_fifo: Trying to write to HSCX fifo.\n");
1449
1450         itjc_set_pib_addr_msb(0);
1451         itjc_write_multi_1(PIB_OFFSET, buf, size);
1452 }
1453
1454
1455 /*---------------------------------------------------------------------------*
1456  *      Read an ISAC register.
1457  *---------------------------------------------------------------------------*/
1458 static u_int8_t
1459 itjc_read_reg(struct l1_softc *sc, int what, bus_size_t offs)
1460 {
1461         bus_space_handle_t h = rman_get_bushandle(sc->sc_resources.io_base[0]);
1462         bus_space_tag_t t = rman_get_bustag(sc->sc_resources.io_base[0]);
1463
1464         if (what != ISIC_WHAT_ISAC)
1465         {
1466                 panic("itjc_read_reg: what(%d) != ISIC_WHAT_ISAC\n",
1467                         what);
1468                 return 0;
1469         }
1470
1471         itjc_set_pib_addr_msb(offs);
1472         return itjc_read_1(itjc_pib_2_pci(offs));
1473 }
1474
1475
1476 /*---------------------------------------------------------------------------*
1477  *      Write an ISAC register.
1478  *---------------------------------------------------------------------------*/
1479 static void
1480 itjc_write_reg(struct l1_softc *sc, int what, bus_size_t offs, u_int8_t data)
1481 {
1482         bus_space_handle_t h = rman_get_bushandle(sc->sc_resources.io_base[0]);
1483         bus_space_tag_t t = rman_get_bustag(sc->sc_resources.io_base[0]);
1484
1485         if (what != ISIC_WHAT_ISAC)
1486         {
1487                 panic("itjc_write_reg: what(%d) != ISIC_WHAT_ISAC\n",
1488                         what);
1489                 return;
1490         }
1491
1492         itjc_set_pib_addr_msb(offs);
1493         itjc_write_1(itjc_pib_2_pci(offs), data);
1494 }
1495
1496
1497 /*---------------------------------------------------------------------------*
1498  *      itjc_probe - probe for a card.
1499  *---------------------------------------------------------------------------*/
1500 static int itjc_probe(device_t dev)
1501 {
1502         u_int16_t       vid = pci_get_vendor(dev),
1503                         did = pci_get_device(dev);
1504
1505         if ((vid == PCI_TJNET_VID) && (did == PCI_TJ300_DID))
1506         {
1507                 device_set_desc(dev, "NetJet-S");
1508                 return 0;
1509         }
1510
1511         return ENXIO;
1512 }
1513
1514
1515 /*---------------------------------------------------------------------------*
1516  *      itjc_attach - attach a (previously probed) card.
1517  *---------------------------------------------------------------------------*/
1518 int
1519 itjc_attach(device_t dev)
1520 {
1521         bus_space_handle_t      h;
1522         bus_space_tag_t         t;
1523
1524         struct l1_softc         *sc = device_get_softc(dev);
1525
1526         u_int16_t               vid = pci_get_vendor(dev),
1527                                 did = pci_get_device(dev);
1528
1529         int                     unit = device_get_unit(dev),
1530                                 res_init_level = 0,
1531                                 error = 0;
1532
1533         void                    *ih = 0;
1534
1535         dma_context_t           *ctx = &dma_context[unit];
1536
1537         crit_enter();
1538         bzero(sc, sizeof(struct l1_softc));
1539
1540         /* Probably not really required. */
1541         if (unit > ITJC_MAXUNIT)
1542         {
1543                 printf("itjc%d: Error, unit > ITJC_MAXUNIT!\n", unit);
1544                 crit_exit();
1545                 return ENXIO;
1546         }
1547
1548         if (!(vid == PCI_TJNET_VID && did == PCI_TJ300_DID))
1549         {
1550                 printf("itjc%d: unknown device (%04X,%04X)!\n", unit, vid, did);
1551                 goto fail;
1552         }
1553
1554         itjc_scp[unit] = sc;
1555
1556         sc->sc_resources.io_rid[0] = PCIR_MAPS+0;
1557         sc->sc_resources.io_base[0] = bus_alloc_resource(dev, SYS_RES_IOPORT,
1558                 &sc->sc_resources.io_rid[0], 0, ~0, 1, RF_ACTIVE);
1559
1560         if (sc->sc_resources.io_base[0] == NULL)
1561         {
1562                 printf("itjc%d: couldn't map IO port\n", unit);
1563                 error = ENXIO;
1564                 goto fail;
1565         }
1566
1567         h = rman_get_bushandle(sc->sc_resources.io_base[0]);
1568         t = rman_get_bustag(sc->sc_resources.io_base[0]);
1569
1570         ++res_init_level;
1571
1572         /* Allocate interrupt. */
1573         sc->sc_resources.irq_rid = 0;
1574         sc->sc_resources.irq = bus_alloc_resource(dev, SYS_RES_IRQ,
1575                 &sc->sc_resources.irq_rid, 0, ~0, 1, RF_SHAREABLE | RF_ACTIVE);
1576
1577         if (sc->sc_resources.irq == NULL)
1578         {
1579                 printf("itjc%d: couldn't map interrupt\n", unit);
1580                 error = ENXIO;
1581                 goto fail;
1582         }
1583
1584         ++res_init_level;
1585
1586         error = bus_setup_intr(dev, sc->sc_resources.irq, INTR_TYPE_NET,
1587                                itjc_intr, sc, &ih, NULL);
1588
1589         if (error)
1590         {
1591                 printf("itjc%d: couldn't set up irq handler\n", unit);
1592                 error = ENXIO;
1593                 goto fail;
1594         }
1595
1596         /*
1597          * Reset the ASIC & the ISAC.
1598          */
1599         itjc_write_1(TIGER_RESET_PIB_CL_TIME, TIGER_RESET_ALL);
1600
1601         DELAY(SEC_DELAY/100); /* Give it 10 ms to reset ...*/
1602
1603         itjc_write_1(TIGER_RESET_PIB_CL_TIME,
1604                 TIGER_SELF_ADDR_DMA | TIGER_PIB_3_CYCLES);
1605
1606         DELAY(SEC_DELAY/100); /* ... and more 10 to recover. */
1607
1608         /*
1609          * First part of DMA initialization. Create & map the memory
1610          * pool that will be used to bear the rx & tx ring buffers.
1611          */
1612         ctx->state = ITJC_DS_LOADING;
1613
1614         error = bus_dma_tag_create(
1615                 NULL,                                   /* parent */
1616                 4,                                      /* alignment*/
1617                 0,                                      /* boundary*/
1618                 BUS_SPACE_MAXADDR_32BIT,                /* lowaddr*/
1619                 BUS_SPACE_MAXADDR,                      /* highaddr*/
1620                 NULL,                                   /* filter*/
1621                 NULL,                                   /* filterarg*/
1622                 ITJC_DMA_POOL_BYTES,                    /* maxsize*/
1623                 1,                                      /* nsegments*/
1624                 ITJC_DMA_POOL_BYTES,                    /* maxsegsz*/
1625                 BUS_DMA_ALLOCNOW | BUS_DMA_COHERENT,    /* flags*/
1626                 &ctx->tag);
1627
1628         if (error)
1629         {
1630                 printf("itjc%d: couldn't create bus DMA tag.\n", unit);
1631                 goto fail;
1632         }
1633
1634         ++res_init_level;
1635
1636         error = bus_dmamem_alloc(
1637                 ctx->tag,                               /* DMA tag */
1638                 (void **)&ctx->pool,    /* KV addr of the allocated memory */
1639                 BUS_DMA_NOWAIT | BUS_DMA_COHERENT,      /* flags */
1640                 &ctx->map);                             /* KV <-> PCI map */
1641
1642         if (error)
1643                 goto fail;
1644
1645         /*
1646          * Load the KV <-> PCI map so the device sees the same
1647          * memory segment as pointed by pool. Note: since the
1648          * load may happen assyncronously (completion indicated by
1649          * the execution of the callback function) we have to
1650          * delay the initialization of the DMA engine to a moment we
1651          * actually have the proper bus addresses to feed the Tiger
1652          * and our DMA control blocks. This will be done in
1653          * itjc_bchannel_setup via a call to itjc_dma_start.
1654          */
1655         bus_dmamap_load(
1656                 ctx->tag,               /* DMA tag */
1657                 ctx->map,               /* DMA map */
1658                 ctx->pool,              /* KV addr of buffer */
1659                 ITJC_DMA_POOL_BYTES,    /* buffer size */
1660                 itjc_map_callback,      /* this receive the bus addr/error */
1661                 ctx,                    /* callback aux arg */
1662                 0);                     /* flags */
1663
1664         ++res_init_level;
1665
1666         /*
1667          * Setup the AUX port so we can talk to the ISAC.
1668          */
1669         itjc_write_1(TIGER_AUX_PORT_CNTL, TIGER_AUX_NJ_DEFAULT);
1670         itjc_write_1(TIGER_INT1_MASK, TIGER_ISAC_INT);
1671
1672         /*
1673          * From now on, almost like a `normal' ISIC driver.
1674          */
1675
1676         sc->sc_unit = unit;
1677
1678         ISAC_BASE = (caddr_t)ISIC_WHAT_ISAC;
1679
1680         HSCX_A_BASE = (caddr_t)ISIC_WHAT_HSCXA;
1681         HSCX_B_BASE = (caddr_t)ISIC_WHAT_HSCXB;
1682
1683         /* setup access routines */
1684
1685         sc->clearirq = NULL;
1686         sc->readreg = itjc_read_reg;
1687         sc->writereg = itjc_write_reg;
1688
1689         sc->readfifo = itjc_read_fifo;
1690         sc->writefifo = itjc_write_fifo;
1691
1692         /* setup card type */
1693
1694         sc->sc_cardtyp = CARD_TYPEP_NETJET_S;
1695
1696         /* setup IOM bus type */
1697
1698         sc->sc_bustyp = BUS_TYPE_IOM2;
1699
1700         /* set up some other miscellaneous things */
1701         sc->sc_ipac = 0;
1702         sc->sc_bfifolen = 2 * ITJC_RING_SLOT_WORDS;
1703
1704         printf("itjc%d: ISAC 2186 Version 1.1 (IOM-2)\n", unit);
1705
1706         /* init the ISAC */
1707         itjc_isac_init(sc);
1708
1709         /* init the "HSCX" */
1710         itjc_bchannel_setup(sc->sc_unit, HSCX_CH_A, BPROT_NONE, 0);
1711
1712         itjc_bchannel_setup(sc->sc_unit, HSCX_CH_B, BPROT_NONE, 0);
1713
1714         /* can't use the normal B-Channel stuff */
1715         itjc_init_linktab(sc);
1716
1717         /* set trace level */
1718
1719         sc->sc_trace = TRACE_OFF;
1720
1721         sc->sc_state = ISAC_IDLE;
1722
1723         sc->sc_ibuf = NULL;
1724         sc->sc_ib = NULL;
1725         sc->sc_ilen = 0;
1726
1727         sc->sc_obuf = NULL;
1728         sc->sc_op = NULL;
1729         sc->sc_ol = 0;
1730         sc->sc_freeflag = 0;
1731
1732         sc->sc_obuf2 = NULL;
1733         sc->sc_freeflag2 = 0;
1734
1735         callout_init(&sc->sc_T3_timeout);
1736         callout_init(&sc->sc_T4_timeout);
1737
1738         /* init higher protocol layers */
1739
1740         i4b_l1_mph_status_ind(L0ITJCUNIT(sc->sc_unit), STI_ATTACH,
1741                 sc->sc_cardtyp, &itjc_l1mux_func);
1742
1743         crit_exit();
1744         return 0;
1745
1746   fail:
1747         switch (res_init_level)
1748         {
1749         case 5:
1750                 bus_dmamap_unload(ctx->tag, ctx->map);
1751                 /* FALL TRHU */
1752
1753         case 4:
1754                 bus_dmamem_free(ctx->tag, ctx->pool, ctx->map);
1755                 bus_dmamap_destroy(ctx->tag, ctx->map);
1756                 /* FALL TRHU */
1757
1758         case 3:
1759                 bus_dma_tag_destroy(ctx->tag);
1760                 /* FALL TRHU */
1761
1762         case 2:
1763                 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_resources.irq);
1764                 /* FALL TRHU */
1765
1766         case 1:
1767                 bus_release_resource(dev, SYS_RES_IOPORT, PCIR_MAPS+0,
1768                         sc->sc_resources.io_base[0]);
1769                 /* FALL TRHU */
1770
1771         case 0:
1772                 break;
1773         }
1774
1775         itjc_scp[unit] = NULL;
1776
1777         crit_exit();
1778         return error;
1779 }
1780
1781
1782 /*---------------------------------------------------------------------------*
1783  *      itjc_intr - main interrupt service routine.
1784  *---------------------------------------------------------------------------*/
1785 static void
1786 itjc_intr(void *xsc)
1787 {
1788         struct l1_softc         *sc     = xsc;
1789         l1_bchan_state_t        *chan   = &sc->sc_chan[0];
1790         dma_context_t           *dma    = &dma_context[sc->sc_unit];
1791         dma_rx_context_t        *rxc    = &dma_rx_context[sc->sc_unit][0];
1792         dma_tx_context_t        *txc    = &dma_tx_context[sc->sc_unit][0];
1793
1794         bus_space_handle_t h = rman_get_bushandle(sc->sc_resources.io_base[0]);
1795         bus_space_tag_t t = rman_get_bustag(sc->sc_resources.io_base[0]);
1796
1797         /* Honor interrupts from successfully configured cards only. */
1798         if (dma->state < ITJC_DS_STOPPED)
1799                 return;
1800
1801         /* First, we check the ISAC... */
1802         if (! (itjc_read_1(TIGER_AUX_PORT_DATA) & TIGER_ISAC_INT_MASK))
1803         {
1804                 itjc_write_1(TIGER_INT1_STATUS, TIGER_ISAC_INT);
1805                 NDBGL1(L1_H_IRQ, "ISAC");
1806                 itjc_isac_intr(sc);
1807         }
1808
1809         /* ... after what we always have a look at the DMA rings. */
1810
1811         NDBGL1(L1_H_IRQ, "Tiger");
1812
1813         itjc_read_1(TIGER_INT0_STATUS);
1814         itjc_write_1(TIGER_INT0_STATUS, TIGER_TARGET_ABORT_INT
1815                 | TIGER_MASTER_ABORT_INT | TIGER_RD_END_INT
1816                 | TIGER_RD_INT_INT       | TIGER_WR_END_INT | TIGER_WR_INT_INT);
1817
1818         itjc_dma_rx_intr(sc, chan, rxc);
1819         itjc_dma_tx_intr(sc, chan, txc);
1820
1821         ++chan; ++rxc; ++txc;
1822
1823         itjc_dma_rx_intr(sc, chan, rxc);
1824         itjc_dma_tx_intr(sc, chan, txc);
1825 }
1826
1827
1828 /*---------------------------------------------------------------------------*
1829  *      itjc_bchannel_setup - (Re)initialize and start/stop a Bchannel.
1830  *---------------------------------------------------------------------------*/
1831 static void
1832 itjc_bchannel_setup(int unit, int h_chan, int bprot, int activate)
1833 {
1834         struct l1_softc         *sc     = itjc_scp[unit];
1835         l1_bchan_state_t        *chan   = &sc->sc_chan[h_chan];
1836
1837         crit_enter();
1838
1839         NDBGL1(L1_BCHAN, "unit=%d, channel=%d, %s",
1840                 unit, h_chan, activate ? "activate" : "deactivate");
1841
1842         /*
1843          * If we are deactivating the channel, we have to stop
1844          * the DMA before we reset the channel control structures.
1845          */
1846         if (! activate)
1847                 itjc_bchannel_dma_setup(sc, h_chan, activate);
1848
1849         /* general part */
1850
1851         chan->state = HSCX_IDLE;
1852
1853         chan->unit = sc->sc_unit;       /* unit number */
1854         chan->channel = h_chan;         /* B channel */
1855         chan->bprot = bprot;            /* B channel protocol */
1856
1857         /* receiver part */
1858
1859         i4b_Bcleanifq(&chan->rx_queue); /* clean rx queue */
1860
1861         chan->rx_queue.ifq_maxlen = IFQ_MAXLEN;
1862
1863         chan->rxcount = 0;              /* reset rx counter */
1864
1865         i4b_Bfreembuf(chan->in_mbuf);   /* clean rx mbuf */
1866
1867         chan->in_mbuf = NULL;           /* reset mbuf ptr */
1868         chan->in_cbptr = NULL;          /* reset mbuf curr ptr */
1869         chan->in_len = 0;               /* reset mbuf data len */
1870
1871         /* transmitter part */
1872
1873         i4b_Bcleanifq(&chan->tx_queue); /* clean tx queue */
1874
1875         chan->tx_queue.ifq_maxlen = IFQ_MAXLEN;
1876
1877         chan->txcount = 0;              /* reset tx counter */
1878
1879         i4b_Bfreembuf(chan->out_mbuf_head);     /* clean tx mbuf */
1880
1881         chan->out_mbuf_head = NULL;     /* reset head mbuf ptr */
1882         chan->out_mbuf_cur = NULL;      /* reset current mbuf ptr */
1883         chan->out_mbuf_cur_ptr = NULL;  /* reset current mbuf data ptr */
1884         chan->out_mbuf_cur_len = 0;     /* reset current mbuf data cnt */
1885
1886         /*
1887          * Only setup & start the DMA after all other channel
1888          * control structures are in place.
1889          */
1890         if (activate)
1891                 itjc_bchannel_dma_setup(sc, h_chan, activate);
1892
1893         crit_exit();
1894 }
1895
1896
1897 /*---------------------------------------------------------------------------*
1898  *      itjc_bchannel_start - Signal us we have more data to send.
1899  *---------------------------------------------------------------------------*/
1900 static void
1901 itjc_bchannel_start(int unit, int h_chan)
1902 {
1903 #if Buggy_code
1904         /*
1905          * I disabled this routine because it was causing crashes when
1906          * this driver was used with the ISP (kernel SPPP) protocol driver.
1907          * The scenario is reproductible:
1908          *      Use the -link1 (dial on demand) ifconfig option.
1909          *      Start an interactive  TCP connection to somewhere.
1910          *      Wait until the PPP connection times out and is dropped.
1911          *      Try to send something on the TCP connection.
1912          *      The machine will print some garbage and halt or reboot
1913          *      (no panic messages).
1914          *
1915          * I've nailed down the problem to the fact that this routine
1916          * was being called before the B channel had been setup again.
1917          *
1918          * For now, I don't have a good solution other than this one.
1919          * But, don't despair. The impact of it is unnoticeable.
1920          */
1921
1922         struct l1_softc  *sc    = itjc_scp[unit];
1923         l1_bchan_state_t *chan  = &sc->sc_chan[h_chan];
1924         dma_tx_context_t *txc   = &dma_tx_context[unit][h_chan];
1925
1926         crit_enter();
1927
1928         if (chan->state & HSCX_TX_ACTIVE)
1929         {
1930                 crit_exit();
1931                 return;
1932         }
1933
1934         itjc_dma_tx_intr(sc, chan, txc);
1935
1936         crit_exit();
1937 #endif
1938 }
1939
1940
1941 /*---------------------------------------------------------------------------*
1942  *      itjc_shutdown - Stop the driver and reset the card.
1943  *---------------------------------------------------------------------------*/
1944 static void
1945 itjc_shutdown(device_t dev)
1946 {
1947         struct l1_softc *sc = device_get_softc(dev);
1948         bus_space_handle_t h = rman_get_bushandle(sc->sc_resources.io_base[0]);
1949         bus_space_tag_t t = rman_get_bustag(sc->sc_resources.io_base[0]);
1950
1951         /*
1952          * Stop the DMA the nice and easy way.
1953          */
1954         itjc_bchannel_setup(sc->sc_unit, 0, BPROT_NONE, 0);
1955         itjc_bchannel_setup(sc->sc_unit, 1, BPROT_NONE, 0);
1956
1957         /*
1958          * Reset the card.
1959          */
1960         itjc_write_1(TIGER_RESET_PIB_CL_TIME, TIGER_RESET_ALL);
1961
1962         DELAY(SEC_DELAY/100); /* Give it 10 ms to reset ...*/
1963
1964         itjc_write_1(TIGER_RESET_PIB_CL_TIME,
1965                 TIGER_SELF_ADDR_DMA | TIGER_LATCH_DMA_INT | TIGER_PIB_3_CYCLES);
1966
1967         DELAY(SEC_DELAY/100); /* ... and more 10 to recover */
1968 }
1969
1970
1971 /*---------------------------------------------------------------------------*
1972  *      itjc_ret_linktab - Return the address of itjc drivers linktab.
1973  *---------------------------------------------------------------------------*/
1974 isdn_link_t *
1975 itjc_ret_linktab(int unit, int channel)
1976 {
1977         struct l1_softc         *sc = itjc_scp[unit];
1978         l1_bchan_state_t        *chan = &sc->sc_chan[channel];
1979
1980         return(&chan->isic_isdn_linktab);
1981 }
1982
1983 /*---------------------------------------------------------------------------*
1984  *      itjc_set_linktab - Set the driver linktab in the b channel softc.
1985  *---------------------------------------------------------------------------*/
1986 void
1987 itjc_set_linktab(int unit, int channel, drvr_link_t *dlt)
1988 {
1989         struct l1_softc *sc     = itjc_scp[unit];
1990         l1_bchan_state_t *chan  = &sc->sc_chan[channel];
1991
1992         chan->isic_drvr_linktab = dlt;
1993 }
1994
1995
1996 /*---------------------------------------------------------------------------*
1997  *      itjc_init_linktab - Initialize our local linktab.
1998  *---------------------------------------------------------------------------*/
1999 static void
2000 itjc_init_linktab(struct l1_softc *sc)
2001 {
2002         l1_bchan_state_t *chan = &sc->sc_chan[HSCX_CH_A];
2003         isdn_link_t *lt = &chan->isic_isdn_linktab;
2004
2005         /* make sure the hardware driver is known to layer 4 */
2006         /* avoid overwriting if already set */
2007         if (ctrl_types[CTRL_PASSIVE].set_linktab == NULL)
2008         {
2009                 ctrl_types[CTRL_PASSIVE].set_linktab = itjc_set_linktab;
2010                 ctrl_types[CTRL_PASSIVE].get_linktab = itjc_ret_linktab;
2011         }
2012
2013         /* local setup */
2014         lt->unit = sc->sc_unit;
2015         lt->channel = HSCX_CH_A;
2016         lt->bch_config = itjc_bchannel_setup;
2017         lt->bch_tx_start = itjc_bchannel_start;
2018         lt->bch_stat = itjc_bchannel_stat;
2019         lt->tx_queue = &chan->tx_queue;
2020
2021         /* used by non-HDLC data transfers, i.e. telephony drivers */
2022         lt->rx_queue = &chan->rx_queue;
2023
2024         /* used by HDLC data transfers, i.e. ipr and isp drivers */
2025         lt->rx_mbuf = &chan->in_mbuf;
2026
2027         chan = &sc->sc_chan[HSCX_CH_B];
2028         lt = &chan->isic_isdn_linktab;
2029
2030         lt->unit = sc->sc_unit;
2031         lt->channel = HSCX_CH_B;
2032         lt->bch_config = itjc_bchannel_setup;
2033         lt->bch_tx_start = itjc_bchannel_start;
2034         lt->bch_stat = itjc_bchannel_stat;
2035         lt->tx_queue = &chan->tx_queue;
2036
2037         /* used by non-HDLC data transfers, i.e. telephony drivers */
2038         lt->rx_queue = &chan->rx_queue;
2039
2040         /* used by HDLC data transfers, i.e. ipr and isp drivers */
2041         lt->rx_mbuf = &chan->in_mbuf;
2042 }
2043
2044
2045 /*---------------------------------------------------------------------------*
2046  *      itjc_bchannel_stat - Collect link statistics for a given B channel.
2047  *---------------------------------------------------------------------------*/
2048 static void
2049 itjc_bchannel_stat(int unit, int h_chan, bchan_statistics_t *bsp)
2050 {
2051         struct l1_softc *sc = itjc_scp[unit];
2052         l1_bchan_state_t *chan = &sc->sc_chan[h_chan];
2053
2054         crit_enter();
2055
2056         bsp->outbytes = chan->txcount;
2057         bsp->inbytes = chan->rxcount;
2058
2059         chan->txcount = 0;
2060         chan->rxcount = 0;
2061
2062         crit_exit();
2063 }
2064
2065
2066 /*---------------------------------------------------------------------------*
2067  *      Netjet - ISAC interrupt routine.
2068  *---------------------------------------------------------------------------*/
2069 static void
2070 itjc_isac_intr(struct l1_softc *sc)
2071 {
2072         u_char irq_stat;
2073
2074         do
2075         {
2076                 /* get isac irq status */
2077                 irq_stat = ISAC_READ(I_ISTA);
2078
2079                 if(irq_stat)
2080                         itjc_isac_irq(sc, irq_stat); /* isac handler */
2081         }
2082         while(irq_stat);
2083
2084         ISAC_WRITE(I_MASK, 0xff);
2085
2086         DELAY(100);
2087
2088         ISAC_WRITE(I_MASK, ISAC_IMASK);
2089 }
2090
2091
2092 /*---------------------------------------------------------------------------*
2093  *      itjc_recover - Try to recover from ISAC irq lockup.
2094  *---------------------------------------------------------------------------*/
2095 void
2096 itjc_recover(struct l1_softc *sc)
2097 {
2098         u_char byte;
2099
2100         /* get isac irq status */
2101
2102         byte = ISAC_READ(I_ISTA);
2103
2104         NDBGL1(L1_ERROR, "  ISAC: ISTA = 0x%x", byte);
2105
2106         if(byte & ISAC_ISTA_EXI)
2107                 NDBGL1(L1_ERROR, "  ISAC: EXIR = 0x%x", (u_char)ISAC_READ(I_EXIR));
2108
2109         if(byte & ISAC_ISTA_CISQ)
2110         {
2111                 byte = ISAC_READ(I_CIRR);
2112
2113                 NDBGL1(L1_ERROR, "  ISAC: CISQ = 0x%x", byte);
2114
2115                 if(byte & ISAC_CIRR_SQC)
2116                         NDBGL1(L1_ERROR, "  ISAC: SQRR = 0x%x", (u_char)ISAC_READ(I_SQRR));
2117         }
2118
2119         NDBGL1(L1_ERROR, "  ISAC: IMASK = 0x%x", ISAC_IMASK);
2120
2121         ISAC_WRITE(I_MASK, 0xff);
2122         DELAY(100);
2123         ISAC_WRITE(I_MASK, ISAC_IMASK);
2124 }
2125
2126 #endif /* NITJC > 0 */